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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
63eeaf38 | 29 | #include <linux/sysrq.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
1da177e4 LT |
31 | #include "drmP.h" |
32 | #include "drm.h" | |
33 | #include "i915_drm.h" | |
34 | #include "i915_drv.h" | |
1c5d22f7 | 35 | #include "i915_trace.h" |
79e53945 | 36 | #include "intel_drv.h" |
1da177e4 | 37 | |
1da177e4 | 38 | #define MAX_NOPID ((u32)~0) |
1da177e4 | 39 | |
7c463586 KP |
40 | /** |
41 | * Interrupts that are always left unmasked. | |
42 | * | |
43 | * Since pipe events are edge-triggered from the PIPESTAT register to IIR, | |
44 | * we leave them always unmasked in IMR and then control enabling them through | |
45 | * PIPESTAT alone. | |
46 | */ | |
6b95a207 KH |
47 | #define I915_INTERRUPT_ENABLE_FIX \ |
48 | (I915_ASLE_INTERRUPT | \ | |
49 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ | |
50 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \ | |
51 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \ | |
52 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \ | |
53 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
7c463586 KP |
54 | |
55 | /** Interrupts that we mask and unmask at runtime. */ | |
56 | #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT) | |
57 | ||
79e53945 JB |
58 | #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\ |
59 | PIPE_VBLANK_INTERRUPT_STATUS) | |
60 | ||
61 | #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\ | |
62 | PIPE_VBLANK_INTERRUPT_ENABLE) | |
63 | ||
64 | #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \ | |
65 | DRM_I915_VBLANK_PIPE_B) | |
66 | ||
036a4a7d | 67 | void |
f2b115e6 | 68 | ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d ZW |
69 | { |
70 | if ((dev_priv->gt_irq_mask_reg & mask) != 0) { | |
71 | dev_priv->gt_irq_mask_reg &= ~mask; | |
72 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); | |
73 | (void) I915_READ(GTIMR); | |
74 | } | |
75 | } | |
76 | ||
77 | static inline void | |
f2b115e6 | 78 | ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d ZW |
79 | { |
80 | if ((dev_priv->gt_irq_mask_reg & mask) != mask) { | |
81 | dev_priv->gt_irq_mask_reg |= mask; | |
82 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); | |
83 | (void) I915_READ(GTIMR); | |
84 | } | |
85 | } | |
86 | ||
87 | /* For display hotplug interrupt */ | |
88 | void | |
f2b115e6 | 89 | ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d ZW |
90 | { |
91 | if ((dev_priv->irq_mask_reg & mask) != 0) { | |
92 | dev_priv->irq_mask_reg &= ~mask; | |
93 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); | |
94 | (void) I915_READ(DEIMR); | |
95 | } | |
96 | } | |
97 | ||
98 | static inline void | |
f2b115e6 | 99 | ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d ZW |
100 | { |
101 | if ((dev_priv->irq_mask_reg & mask) != mask) { | |
102 | dev_priv->irq_mask_reg |= mask; | |
103 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); | |
104 | (void) I915_READ(DEIMR); | |
105 | } | |
106 | } | |
107 | ||
8ee1c3db | 108 | void |
ed4cb414 EA |
109 | i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
110 | { | |
111 | if ((dev_priv->irq_mask_reg & mask) != 0) { | |
112 | dev_priv->irq_mask_reg &= ~mask; | |
113 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
114 | (void) I915_READ(IMR); | |
115 | } | |
116 | } | |
117 | ||
118 | static inline void | |
119 | i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) | |
120 | { | |
121 | if ((dev_priv->irq_mask_reg & mask) != mask) { | |
122 | dev_priv->irq_mask_reg |= mask; | |
123 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
124 | (void) I915_READ(IMR); | |
125 | } | |
126 | } | |
127 | ||
7c463586 KP |
128 | static inline u32 |
129 | i915_pipestat(int pipe) | |
130 | { | |
131 | if (pipe == 0) | |
132 | return PIPEASTAT; | |
133 | if (pipe == 1) | |
134 | return PIPEBSTAT; | |
9c84ba4e | 135 | BUG(); |
7c463586 KP |
136 | } |
137 | ||
138 | void | |
139 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
140 | { | |
141 | if ((dev_priv->pipestat[pipe] & mask) != mask) { | |
142 | u32 reg = i915_pipestat(pipe); | |
143 | ||
144 | dev_priv->pipestat[pipe] |= mask; | |
145 | /* Enable the interrupt, clear any pending status */ | |
146 | I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); | |
147 | (void) I915_READ(reg); | |
148 | } | |
149 | } | |
150 | ||
151 | void | |
152 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
153 | { | |
154 | if ((dev_priv->pipestat[pipe] & mask) != 0) { | |
155 | u32 reg = i915_pipestat(pipe); | |
156 | ||
157 | dev_priv->pipestat[pipe] &= ~mask; | |
158 | I915_WRITE(reg, dev_priv->pipestat[pipe]); | |
159 | (void) I915_READ(reg); | |
160 | } | |
161 | } | |
162 | ||
01c66889 ZY |
163 | /** |
164 | * intel_enable_asle - enable ASLE interrupt for OpRegion | |
165 | */ | |
166 | void intel_enable_asle (struct drm_device *dev) | |
167 | { | |
168 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
169 | ||
c619eed4 | 170 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 171 | ironlake_enable_display_irq(dev_priv, DE_GSE); |
edcb49ca | 172 | else { |
01c66889 ZY |
173 | i915_enable_pipestat(dev_priv, 1, |
174 | I915_LEGACY_BLC_EVENT_ENABLE); | |
edcb49ca ZY |
175 | if (IS_I965G(dev)) |
176 | i915_enable_pipestat(dev_priv, 0, | |
177 | I915_LEGACY_BLC_EVENT_ENABLE); | |
178 | } | |
01c66889 ZY |
179 | } |
180 | ||
0a3e67a4 JB |
181 | /** |
182 | * i915_pipe_enabled - check if a pipe is enabled | |
183 | * @dev: DRM device | |
184 | * @pipe: pipe to check | |
185 | * | |
186 | * Reading certain registers when the pipe is disabled can hang the chip. | |
187 | * Use this routine to make sure the PLL is running and the pipe is active | |
188 | * before reading such registers if unsure. | |
189 | */ | |
190 | static int | |
191 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
192 | { | |
193 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
194 | unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF; | |
195 | ||
196 | if (I915_READ(pipeconf) & PIPEACONF_ENABLE) | |
197 | return 1; | |
198 | ||
199 | return 0; | |
200 | } | |
201 | ||
42f52ef8 KP |
202 | /* Called from drm generic code, passed a 'crtc', which |
203 | * we use as a pipe index | |
204 | */ | |
205 | u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
206 | { |
207 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
208 | unsigned long high_frame; | |
209 | unsigned long low_frame; | |
210 | u32 high1, high2, low, count; | |
0a3e67a4 | 211 | |
0a3e67a4 JB |
212 | high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH; |
213 | low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL; | |
214 | ||
215 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 ZY |
216 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
217 | "pipe %d\n", pipe); | |
0a3e67a4 JB |
218 | return 0; |
219 | } | |
220 | ||
221 | /* | |
222 | * High & low register fields aren't synchronized, so make sure | |
223 | * we get a low value that's stable across two reads of the high | |
224 | * register. | |
225 | */ | |
226 | do { | |
227 | high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> | |
228 | PIPE_FRAME_HIGH_SHIFT); | |
229 | low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >> | |
230 | PIPE_FRAME_LOW_SHIFT); | |
231 | high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> | |
232 | PIPE_FRAME_HIGH_SHIFT); | |
233 | } while (high1 != high2); | |
234 | ||
235 | count = (high1 << 8) | low; | |
236 | ||
237 | return count; | |
238 | } | |
239 | ||
9880b7a5 JB |
240 | u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
241 | { | |
242 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
243 | int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45; | |
244 | ||
245 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 ZY |
246 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
247 | "pipe %d\n", pipe); | |
9880b7a5 JB |
248 | return 0; |
249 | } | |
250 | ||
251 | return I915_READ(reg); | |
252 | } | |
253 | ||
5ca58282 JB |
254 | /* |
255 | * Handle hotplug events outside the interrupt handler proper. | |
256 | */ | |
257 | static void i915_hotplug_work_func(struct work_struct *work) | |
258 | { | |
259 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
260 | hotplug_work); | |
261 | struct drm_device *dev = dev_priv->dev; | |
c31c4ba3 | 262 | struct drm_mode_config *mode_config = &dev->mode_config; |
5bf4c9c4 | 263 | struct drm_encoder *encoder; |
c31c4ba3 | 264 | |
5bf4c9c4 ZW |
265 | if (mode_config->num_encoder) { |
266 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { | |
267 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); | |
c31c4ba3 | 268 | |
21d40d37 EA |
269 | if (intel_encoder->hot_plug) |
270 | (*intel_encoder->hot_plug) (intel_encoder); | |
c31c4ba3 KP |
271 | } |
272 | } | |
5ca58282 | 273 | /* Just fire off a uevent and let userspace tell us what to do */ |
4abe3520 | 274 | intelfb_hotplug(dev, false); |
5ca58282 JB |
275 | drm_sysfs_hotplug_event(dev); |
276 | } | |
277 | ||
f97108d1 JB |
278 | static void i915_handle_rps_change(struct drm_device *dev) |
279 | { | |
280 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b5b72e89 | 281 | u32 busy_up, busy_down, max_avg, min_avg; |
f97108d1 JB |
282 | u16 rgvswctl; |
283 | u8 new_delay = dev_priv->cur_delay; | |
284 | ||
285 | I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS) & ~MEMINT_EVAL_CHG); | |
b5b72e89 MG |
286 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
287 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
288 | max_avg = I915_READ(RCBMAXAVG); |
289 | min_avg = I915_READ(RCBMINAVG); | |
290 | ||
291 | /* Handle RCS change request from hw */ | |
b5b72e89 | 292 | if (busy_up > max_avg) { |
f97108d1 JB |
293 | if (dev_priv->cur_delay != dev_priv->max_delay) |
294 | new_delay = dev_priv->cur_delay - 1; | |
295 | if (new_delay < dev_priv->max_delay) | |
296 | new_delay = dev_priv->max_delay; | |
b5b72e89 | 297 | } else if (busy_down < min_avg) { |
f97108d1 JB |
298 | if (dev_priv->cur_delay != dev_priv->min_delay) |
299 | new_delay = dev_priv->cur_delay + 1; | |
300 | if (new_delay > dev_priv->min_delay) | |
301 | new_delay = dev_priv->min_delay; | |
302 | } | |
303 | ||
304 | DRM_DEBUG("rps change requested: %d -> %d\n", | |
305 | dev_priv->cur_delay, new_delay); | |
306 | ||
307 | rgvswctl = I915_READ(MEMSWCTL); | |
308 | if (rgvswctl & MEMCTL_CMD_STS) { | |
b5b72e89 MG |
309 | DRM_ERROR("gpu busy, RCS change rejected\n"); |
310 | return; /* still busy with another command */ | |
f97108d1 JB |
311 | } |
312 | ||
313 | /* Program the new state */ | |
314 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | | |
315 | (new_delay << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; | |
316 | I915_WRITE(MEMSWCTL, rgvswctl); | |
317 | POSTING_READ(MEMSWCTL); | |
318 | ||
319 | rgvswctl |= MEMCTL_CMD_STS; | |
320 | I915_WRITE(MEMSWCTL, rgvswctl); | |
321 | ||
322 | dev_priv->cur_delay = new_delay; | |
323 | ||
324 | DRM_DEBUG("rps changed\n"); | |
325 | ||
326 | return; | |
327 | } | |
328 | ||
f2b115e6 | 329 | irqreturn_t ironlake_irq_handler(struct drm_device *dev) |
036a4a7d ZW |
330 | { |
331 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
332 | int ret = IRQ_NONE; | |
3ff99164 | 333 | u32 de_iir, gt_iir, de_ier, pch_iir; |
036a4a7d ZW |
334 | struct drm_i915_master_private *master_priv; |
335 | ||
2d109a84 ZN |
336 | /* disable master interrupt before clearing iir */ |
337 | de_ier = I915_READ(DEIER); | |
338 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
339 | (void)I915_READ(DEIER); | |
340 | ||
036a4a7d ZW |
341 | de_iir = I915_READ(DEIIR); |
342 | gt_iir = I915_READ(GTIIR); | |
c650156a | 343 | pch_iir = I915_READ(SDEIIR); |
036a4a7d | 344 | |
c7c85101 ZN |
345 | if (de_iir == 0 && gt_iir == 0 && pch_iir == 0) |
346 | goto done; | |
036a4a7d | 347 | |
c7c85101 | 348 | ret = IRQ_HANDLED; |
036a4a7d | 349 | |
c7c85101 ZN |
350 | if (dev->primary->master) { |
351 | master_priv = dev->primary->master->driver_priv; | |
352 | if (master_priv->sarea_priv) | |
353 | master_priv->sarea_priv->last_dispatch = | |
354 | READ_BREADCRUMB(dev_priv); | |
355 | } | |
036a4a7d | 356 | |
c7c85101 ZN |
357 | if (gt_iir & GT_USER_INTERRUPT) { |
358 | u32 seqno = i915_get_gem_seqno(dev); | |
359 | dev_priv->mm.irq_gem_seqno = seqno; | |
360 | trace_i915_gem_request_complete(dev, seqno); | |
361 | DRM_WAKEUP(&dev_priv->irq_queue); | |
362 | dev_priv->hangcheck_count = 0; | |
363 | mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); | |
364 | } | |
01c66889 | 365 | |
c7c85101 ZN |
366 | if (de_iir & DE_GSE) |
367 | ironlake_opregion_gse_intr(dev); | |
c650156a | 368 | |
f072d2e7 | 369 | if (de_iir & DE_PLANEA_FLIP_DONE) { |
013d5aa2 | 370 | intel_prepare_page_flip(dev, 0); |
f072d2e7 ZW |
371 | intel_finish_page_flip(dev, 0); |
372 | } | |
013d5aa2 | 373 | |
f072d2e7 | 374 | if (de_iir & DE_PLANEB_FLIP_DONE) { |
013d5aa2 | 375 | intel_prepare_page_flip(dev, 1); |
f072d2e7 ZW |
376 | intel_finish_page_flip(dev, 1); |
377 | } | |
013d5aa2 | 378 | |
f072d2e7 | 379 | if (de_iir & DE_PIPEA_VBLANK) |
c062df61 LP |
380 | drm_handle_vblank(dev, 0); |
381 | ||
f072d2e7 | 382 | if (de_iir & DE_PIPEB_VBLANK) |
c062df61 LP |
383 | drm_handle_vblank(dev, 1); |
384 | ||
c7c85101 ZN |
385 | /* check event from PCH */ |
386 | if ((de_iir & DE_PCH_EVENT) && | |
387 | (pch_iir & SDE_HOTPLUG_MASK)) { | |
388 | queue_work(dev_priv->wq, &dev_priv->hotplug_work); | |
036a4a7d ZW |
389 | } |
390 | ||
f97108d1 JB |
391 | if (de_iir & DE_PCU_EVENT) { |
392 | I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS)); | |
393 | i915_handle_rps_change(dev); | |
394 | } | |
395 | ||
c7c85101 ZN |
396 | /* should clear PCH hotplug event before clear CPU irq */ |
397 | I915_WRITE(SDEIIR, pch_iir); | |
398 | I915_WRITE(GTIIR, gt_iir); | |
399 | I915_WRITE(DEIIR, de_iir); | |
400 | ||
401 | done: | |
2d109a84 ZN |
402 | I915_WRITE(DEIER, de_ier); |
403 | (void)I915_READ(DEIER); | |
404 | ||
036a4a7d ZW |
405 | return ret; |
406 | } | |
407 | ||
8a905236 JB |
408 | /** |
409 | * i915_error_work_func - do process context error handling work | |
410 | * @work: work struct | |
411 | * | |
412 | * Fire an error uevent so userspace can see that a hang or error | |
413 | * was detected. | |
414 | */ | |
415 | static void i915_error_work_func(struct work_struct *work) | |
416 | { | |
417 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
418 | error_work); | |
419 | struct drm_device *dev = dev_priv->dev; | |
f316a42c BG |
420 | char *error_event[] = { "ERROR=1", NULL }; |
421 | char *reset_event[] = { "RESET=1", NULL }; | |
422 | char *reset_done_event[] = { "ERROR=0", NULL }; | |
8a905236 | 423 | |
44d98a61 | 424 | DRM_DEBUG_DRIVER("generating error event\n"); |
f316a42c BG |
425 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); |
426 | ||
ba1234d1 | 427 | if (atomic_read(&dev_priv->mm.wedged)) { |
f316a42c | 428 | if (IS_I965G(dev)) { |
44d98a61 | 429 | DRM_DEBUG_DRIVER("resetting chip\n"); |
f316a42c BG |
430 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); |
431 | if (!i965_reset(dev, GDRST_RENDER)) { | |
ba1234d1 | 432 | atomic_set(&dev_priv->mm.wedged, 0); |
f316a42c BG |
433 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); |
434 | } | |
435 | } else { | |
44d98a61 | 436 | DRM_DEBUG_DRIVER("reboot required\n"); |
f316a42c BG |
437 | } |
438 | } | |
8a905236 JB |
439 | } |
440 | ||
9df30794 CW |
441 | static struct drm_i915_error_object * |
442 | i915_error_object_create(struct drm_device *dev, | |
443 | struct drm_gem_object *src) | |
444 | { | |
445 | struct drm_i915_error_object *dst; | |
446 | struct drm_i915_gem_object *src_priv; | |
447 | int page, page_count; | |
448 | ||
449 | if (src == NULL) | |
450 | return NULL; | |
451 | ||
23010e43 | 452 | src_priv = to_intel_bo(src); |
9df30794 CW |
453 | if (src_priv->pages == NULL) |
454 | return NULL; | |
455 | ||
456 | page_count = src->size / PAGE_SIZE; | |
457 | ||
458 | dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC); | |
459 | if (dst == NULL) | |
460 | return NULL; | |
461 | ||
462 | for (page = 0; page < page_count; page++) { | |
463 | void *s, *d = kmalloc(PAGE_SIZE, GFP_ATOMIC); | |
464 | if (d == NULL) | |
465 | goto unwind; | |
466 | s = kmap_atomic(src_priv->pages[page], KM_USER0); | |
467 | memcpy(d, s, PAGE_SIZE); | |
468 | kunmap_atomic(s, KM_USER0); | |
469 | dst->pages[page] = d; | |
470 | } | |
471 | dst->page_count = page_count; | |
472 | dst->gtt_offset = src_priv->gtt_offset; | |
473 | ||
474 | return dst; | |
475 | ||
476 | unwind: | |
477 | while (page--) | |
478 | kfree(dst->pages[page]); | |
479 | kfree(dst); | |
480 | return NULL; | |
481 | } | |
482 | ||
483 | static void | |
484 | i915_error_object_free(struct drm_i915_error_object *obj) | |
485 | { | |
486 | int page; | |
487 | ||
488 | if (obj == NULL) | |
489 | return; | |
490 | ||
491 | for (page = 0; page < obj->page_count; page++) | |
492 | kfree(obj->pages[page]); | |
493 | ||
494 | kfree(obj); | |
495 | } | |
496 | ||
497 | static void | |
498 | i915_error_state_free(struct drm_device *dev, | |
499 | struct drm_i915_error_state *error) | |
500 | { | |
501 | i915_error_object_free(error->batchbuffer[0]); | |
502 | i915_error_object_free(error->batchbuffer[1]); | |
503 | i915_error_object_free(error->ringbuffer); | |
504 | kfree(error->active_bo); | |
505 | kfree(error); | |
506 | } | |
507 | ||
508 | static u32 | |
509 | i915_get_bbaddr(struct drm_device *dev, u32 *ring) | |
510 | { | |
511 | u32 cmd; | |
512 | ||
513 | if (IS_I830(dev) || IS_845G(dev)) | |
514 | cmd = MI_BATCH_BUFFER; | |
515 | else if (IS_I965G(dev)) | |
516 | cmd = (MI_BATCH_BUFFER_START | (2 << 6) | | |
517 | MI_BATCH_NON_SECURE_I965); | |
518 | else | |
519 | cmd = (MI_BATCH_BUFFER_START | (2 << 6)); | |
520 | ||
521 | return ring[0] == cmd ? ring[1] : 0; | |
522 | } | |
523 | ||
524 | static u32 | |
525 | i915_ringbuffer_last_batch(struct drm_device *dev) | |
526 | { | |
527 | struct drm_i915_private *dev_priv = dev->dev_private; | |
528 | u32 head, bbaddr; | |
529 | u32 *ring; | |
530 | ||
531 | /* Locate the current position in the ringbuffer and walk back | |
532 | * to find the most recently dispatched batch buffer. | |
533 | */ | |
534 | bbaddr = 0; | |
535 | head = I915_READ(PRB0_HEAD) & HEAD_ADDR; | |
536 | ring = (u32 *)(dev_priv->ring.virtual_start + head); | |
537 | ||
538 | while (--ring >= (u32 *)dev_priv->ring.virtual_start) { | |
539 | bbaddr = i915_get_bbaddr(dev, ring); | |
540 | if (bbaddr) | |
541 | break; | |
542 | } | |
543 | ||
544 | if (bbaddr == 0) { | |
545 | ring = (u32 *)(dev_priv->ring.virtual_start + dev_priv->ring.Size); | |
546 | while (--ring >= (u32 *)dev_priv->ring.virtual_start) { | |
547 | bbaddr = i915_get_bbaddr(dev, ring); | |
548 | if (bbaddr) | |
549 | break; | |
550 | } | |
551 | } | |
552 | ||
553 | return bbaddr; | |
554 | } | |
555 | ||
8a905236 JB |
556 | /** |
557 | * i915_capture_error_state - capture an error record for later analysis | |
558 | * @dev: drm device | |
559 | * | |
560 | * Should be called when an error is detected (either a hang or an error | |
561 | * interrupt) to capture error state from the time of the error. Fills | |
562 | * out a structure which becomes available in debugfs for user level tools | |
563 | * to pick up. | |
564 | */ | |
63eeaf38 JB |
565 | static void i915_capture_error_state(struct drm_device *dev) |
566 | { | |
567 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9df30794 | 568 | struct drm_i915_gem_object *obj_priv; |
63eeaf38 | 569 | struct drm_i915_error_state *error; |
9df30794 | 570 | struct drm_gem_object *batchbuffer[2]; |
63eeaf38 | 571 | unsigned long flags; |
9df30794 CW |
572 | u32 bbaddr; |
573 | int count; | |
63eeaf38 JB |
574 | |
575 | spin_lock_irqsave(&dev_priv->error_lock, flags); | |
9df30794 CW |
576 | error = dev_priv->first_error; |
577 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); | |
578 | if (error) | |
579 | return; | |
63eeaf38 JB |
580 | |
581 | error = kmalloc(sizeof(*error), GFP_ATOMIC); | |
582 | if (!error) { | |
9df30794 CW |
583 | DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); |
584 | return; | |
63eeaf38 JB |
585 | } |
586 | ||
9df30794 | 587 | error->seqno = i915_get_gem_seqno(dev); |
63eeaf38 JB |
588 | error->eir = I915_READ(EIR); |
589 | error->pgtbl_er = I915_READ(PGTBL_ER); | |
590 | error->pipeastat = I915_READ(PIPEASTAT); | |
591 | error->pipebstat = I915_READ(PIPEBSTAT); | |
592 | error->instpm = I915_READ(INSTPM); | |
593 | if (!IS_I965G(dev)) { | |
594 | error->ipeir = I915_READ(IPEIR); | |
595 | error->ipehr = I915_READ(IPEHR); | |
596 | error->instdone = I915_READ(INSTDONE); | |
597 | error->acthd = I915_READ(ACTHD); | |
9df30794 | 598 | error->bbaddr = 0; |
63eeaf38 JB |
599 | } else { |
600 | error->ipeir = I915_READ(IPEIR_I965); | |
601 | error->ipehr = I915_READ(IPEHR_I965); | |
602 | error->instdone = I915_READ(INSTDONE_I965); | |
603 | error->instps = I915_READ(INSTPS); | |
604 | error->instdone1 = I915_READ(INSTDONE1); | |
605 | error->acthd = I915_READ(ACTHD_I965); | |
9df30794 | 606 | error->bbaddr = I915_READ64(BB_ADDR); |
63eeaf38 JB |
607 | } |
608 | ||
9df30794 | 609 | bbaddr = i915_ringbuffer_last_batch(dev); |
8a905236 | 610 | |
9df30794 CW |
611 | /* Grab the current batchbuffer, most likely to have crashed. */ |
612 | batchbuffer[0] = NULL; | |
613 | batchbuffer[1] = NULL; | |
614 | count = 0; | |
615 | list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) { | |
a8089e84 | 616 | struct drm_gem_object *obj = &obj_priv->base; |
63eeaf38 | 617 | |
9df30794 CW |
618 | if (batchbuffer[0] == NULL && |
619 | bbaddr >= obj_priv->gtt_offset && | |
620 | bbaddr < obj_priv->gtt_offset + obj->size) | |
621 | batchbuffer[0] = obj; | |
622 | ||
623 | if (batchbuffer[1] == NULL && | |
624 | error->acthd >= obj_priv->gtt_offset && | |
625 | error->acthd < obj_priv->gtt_offset + obj->size && | |
626 | batchbuffer[0] != obj) | |
627 | batchbuffer[1] = obj; | |
628 | ||
629 | count++; | |
630 | } | |
631 | ||
632 | /* We need to copy these to an anonymous buffer as the simplest | |
633 | * method to avoid being overwritten by userpace. | |
634 | */ | |
635 | error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]); | |
636 | error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]); | |
637 | ||
638 | /* Record the ringbuffer */ | |
639 | error->ringbuffer = i915_error_object_create(dev, dev_priv->ring.ring_obj); | |
640 | ||
641 | /* Record buffers on the active list. */ | |
642 | error->active_bo = NULL; | |
643 | error->active_bo_count = 0; | |
644 | ||
645 | if (count) | |
646 | error->active_bo = kmalloc(sizeof(*error->active_bo)*count, | |
647 | GFP_ATOMIC); | |
648 | ||
649 | if (error->active_bo) { | |
650 | int i = 0; | |
651 | list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) { | |
a8089e84 | 652 | struct drm_gem_object *obj = &obj_priv->base; |
9df30794 CW |
653 | |
654 | error->active_bo[i].size = obj->size; | |
655 | error->active_bo[i].name = obj->name; | |
656 | error->active_bo[i].seqno = obj_priv->last_rendering_seqno; | |
657 | error->active_bo[i].gtt_offset = obj_priv->gtt_offset; | |
658 | error->active_bo[i].read_domains = obj->read_domains; | |
659 | error->active_bo[i].write_domain = obj->write_domain; | |
660 | error->active_bo[i].fence_reg = obj_priv->fence_reg; | |
661 | error->active_bo[i].pinned = 0; | |
662 | if (obj_priv->pin_count > 0) | |
663 | error->active_bo[i].pinned = 1; | |
664 | if (obj_priv->user_pin_count > 0) | |
665 | error->active_bo[i].pinned = -1; | |
666 | error->active_bo[i].tiling = obj_priv->tiling_mode; | |
667 | error->active_bo[i].dirty = obj_priv->dirty; | |
668 | error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED; | |
669 | ||
670 | if (++i == count) | |
671 | break; | |
672 | } | |
673 | error->active_bo_count = i; | |
674 | } | |
675 | ||
676 | do_gettimeofday(&error->time); | |
677 | ||
678 | spin_lock_irqsave(&dev_priv->error_lock, flags); | |
679 | if (dev_priv->first_error == NULL) { | |
680 | dev_priv->first_error = error; | |
681 | error = NULL; | |
682 | } | |
63eeaf38 | 683 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); |
9df30794 CW |
684 | |
685 | if (error) | |
686 | i915_error_state_free(dev, error); | |
687 | } | |
688 | ||
689 | void i915_destroy_error_state(struct drm_device *dev) | |
690 | { | |
691 | struct drm_i915_private *dev_priv = dev->dev_private; | |
692 | struct drm_i915_error_state *error; | |
693 | ||
694 | spin_lock(&dev_priv->error_lock); | |
695 | error = dev_priv->first_error; | |
696 | dev_priv->first_error = NULL; | |
697 | spin_unlock(&dev_priv->error_lock); | |
698 | ||
699 | if (error) | |
700 | i915_error_state_free(dev, error); | |
63eeaf38 JB |
701 | } |
702 | ||
8a905236 JB |
703 | /** |
704 | * i915_handle_error - handle an error interrupt | |
705 | * @dev: drm device | |
706 | * | |
707 | * Do some basic checking of regsiter state at error interrupt time and | |
708 | * dump it to the syslog. Also call i915_capture_error_state() to make | |
709 | * sure we get a record and make it available in debugfs. Fire a uevent | |
710 | * so userspace knows something bad happened (should trigger collection | |
711 | * of a ring dump etc.). | |
712 | */ | |
ba1234d1 | 713 | static void i915_handle_error(struct drm_device *dev, bool wedged) |
8a905236 JB |
714 | { |
715 | struct drm_i915_private *dev_priv = dev->dev_private; | |
716 | u32 eir = I915_READ(EIR); | |
717 | u32 pipea_stats = I915_READ(PIPEASTAT); | |
718 | u32 pipeb_stats = I915_READ(PIPEBSTAT); | |
719 | ||
720 | i915_capture_error_state(dev); | |
721 | ||
722 | printk(KERN_ERR "render error detected, EIR: 0x%08x\n", | |
723 | eir); | |
724 | ||
725 | if (IS_G4X(dev)) { | |
726 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
727 | u32 ipeir = I915_READ(IPEIR_I965); | |
728 | ||
729 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
730 | I915_READ(IPEIR_I965)); | |
731 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
732 | I915_READ(IPEHR_I965)); | |
733 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
734 | I915_READ(INSTDONE_I965)); | |
735 | printk(KERN_ERR " INSTPS: 0x%08x\n", | |
736 | I915_READ(INSTPS)); | |
737 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", | |
738 | I915_READ(INSTDONE1)); | |
739 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
740 | I915_READ(ACTHD_I965)); | |
741 | I915_WRITE(IPEIR_I965, ipeir); | |
742 | (void)I915_READ(IPEIR_I965); | |
743 | } | |
744 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
745 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
746 | printk(KERN_ERR "page table error\n"); | |
747 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", | |
748 | pgtbl_err); | |
749 | I915_WRITE(PGTBL_ER, pgtbl_err); | |
750 | (void)I915_READ(PGTBL_ER); | |
751 | } | |
752 | } | |
753 | ||
754 | if (IS_I9XX(dev)) { | |
755 | if (eir & I915_ERROR_PAGE_TABLE) { | |
756 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
757 | printk(KERN_ERR "page table error\n"); | |
758 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", | |
759 | pgtbl_err); | |
760 | I915_WRITE(PGTBL_ER, pgtbl_err); | |
761 | (void)I915_READ(PGTBL_ER); | |
762 | } | |
763 | } | |
764 | ||
765 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
766 | printk(KERN_ERR "memory refresh error\n"); | |
767 | printk(KERN_ERR "PIPEASTAT: 0x%08x\n", | |
768 | pipea_stats); | |
769 | printk(KERN_ERR "PIPEBSTAT: 0x%08x\n", | |
770 | pipeb_stats); | |
771 | /* pipestat has already been acked */ | |
772 | } | |
773 | if (eir & I915_ERROR_INSTRUCTION) { | |
774 | printk(KERN_ERR "instruction error\n"); | |
775 | printk(KERN_ERR " INSTPM: 0x%08x\n", | |
776 | I915_READ(INSTPM)); | |
777 | if (!IS_I965G(dev)) { | |
778 | u32 ipeir = I915_READ(IPEIR); | |
779 | ||
780 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
781 | I915_READ(IPEIR)); | |
782 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
783 | I915_READ(IPEHR)); | |
784 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
785 | I915_READ(INSTDONE)); | |
786 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
787 | I915_READ(ACTHD)); | |
788 | I915_WRITE(IPEIR, ipeir); | |
789 | (void)I915_READ(IPEIR); | |
790 | } else { | |
791 | u32 ipeir = I915_READ(IPEIR_I965); | |
792 | ||
793 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
794 | I915_READ(IPEIR_I965)); | |
795 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
796 | I915_READ(IPEHR_I965)); | |
797 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
798 | I915_READ(INSTDONE_I965)); | |
799 | printk(KERN_ERR " INSTPS: 0x%08x\n", | |
800 | I915_READ(INSTPS)); | |
801 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", | |
802 | I915_READ(INSTDONE1)); | |
803 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
804 | I915_READ(ACTHD_I965)); | |
805 | I915_WRITE(IPEIR_I965, ipeir); | |
806 | (void)I915_READ(IPEIR_I965); | |
807 | } | |
808 | } | |
809 | ||
810 | I915_WRITE(EIR, eir); | |
811 | (void)I915_READ(EIR); | |
812 | eir = I915_READ(EIR); | |
813 | if (eir) { | |
814 | /* | |
815 | * some errors might have become stuck, | |
816 | * mask them. | |
817 | */ | |
818 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
819 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
820 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
821 | } | |
822 | ||
ba1234d1 BG |
823 | if (wedged) { |
824 | atomic_set(&dev_priv->mm.wedged, 1); | |
825 | ||
11ed50ec BG |
826 | /* |
827 | * Wakeup waiting processes so they don't hang | |
828 | */ | |
11ed50ec BG |
829 | DRM_WAKEUP(&dev_priv->irq_queue); |
830 | } | |
831 | ||
9c9fe1f8 | 832 | queue_work(dev_priv->wq, &dev_priv->error_work); |
8a905236 JB |
833 | } |
834 | ||
1da177e4 LT |
835 | irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) |
836 | { | |
84b1fd10 | 837 | struct drm_device *dev = (struct drm_device *) arg; |
1da177e4 | 838 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 839 | struct drm_i915_master_private *master_priv; |
cdfbc41f EA |
840 | u32 iir, new_iir; |
841 | u32 pipea_stats, pipeb_stats; | |
05eff845 KP |
842 | u32 vblank_status; |
843 | u32 vblank_enable; | |
0a3e67a4 | 844 | int vblank = 0; |
7c463586 | 845 | unsigned long irqflags; |
05eff845 KP |
846 | int irq_received; |
847 | int ret = IRQ_NONE; | |
6e5fca53 | 848 | |
630681d9 EA |
849 | atomic_inc(&dev_priv->irq_received); |
850 | ||
bad720ff | 851 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 852 | return ironlake_irq_handler(dev); |
036a4a7d | 853 | |
ed4cb414 | 854 | iir = I915_READ(IIR); |
a6b54f3f | 855 | |
05eff845 KP |
856 | if (IS_I965G(dev)) { |
857 | vblank_status = I915_START_VBLANK_INTERRUPT_STATUS; | |
858 | vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE; | |
859 | } else { | |
860 | vblank_status = I915_VBLANK_INTERRUPT_STATUS; | |
861 | vblank_enable = I915_VBLANK_INTERRUPT_ENABLE; | |
862 | } | |
af6061af | 863 | |
05eff845 KP |
864 | for (;;) { |
865 | irq_received = iir != 0; | |
866 | ||
867 | /* Can't rely on pipestat interrupt bit in iir as it might | |
868 | * have been cleared after the pipestat interrupt was received. | |
869 | * It doesn't set the bit in iir again, but it still produces | |
870 | * interrupts (for non-MSI). | |
871 | */ | |
872 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); | |
873 | pipea_stats = I915_READ(PIPEASTAT); | |
874 | pipeb_stats = I915_READ(PIPEBSTAT); | |
79e53945 | 875 | |
8a905236 | 876 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
ba1234d1 | 877 | i915_handle_error(dev, false); |
8a905236 | 878 | |
cdfbc41f EA |
879 | /* |
880 | * Clear the PIPE(A|B)STAT regs before the IIR | |
881 | */ | |
05eff845 | 882 | if (pipea_stats & 0x8000ffff) { |
7662c8bd | 883 | if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS) |
44d98a61 | 884 | DRM_DEBUG_DRIVER("pipe a underrun\n"); |
cdfbc41f | 885 | I915_WRITE(PIPEASTAT, pipea_stats); |
05eff845 | 886 | irq_received = 1; |
cdfbc41f | 887 | } |
1da177e4 | 888 | |
05eff845 | 889 | if (pipeb_stats & 0x8000ffff) { |
7662c8bd | 890 | if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS) |
44d98a61 | 891 | DRM_DEBUG_DRIVER("pipe b underrun\n"); |
cdfbc41f | 892 | I915_WRITE(PIPEBSTAT, pipeb_stats); |
05eff845 | 893 | irq_received = 1; |
cdfbc41f | 894 | } |
05eff845 KP |
895 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
896 | ||
897 | if (!irq_received) | |
898 | break; | |
899 | ||
900 | ret = IRQ_HANDLED; | |
8ee1c3db | 901 | |
5ca58282 JB |
902 | /* Consume port. Then clear IIR or we'll miss events */ |
903 | if ((I915_HAS_HOTPLUG(dev)) && | |
904 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { | |
905 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
906 | ||
44d98a61 | 907 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
5ca58282 JB |
908 | hotplug_status); |
909 | if (hotplug_status & dev_priv->hotplug_supported_mask) | |
9c9fe1f8 EA |
910 | queue_work(dev_priv->wq, |
911 | &dev_priv->hotplug_work); | |
5ca58282 JB |
912 | |
913 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
914 | I915_READ(PORT_HOTPLUG_STAT); | |
915 | } | |
916 | ||
cdfbc41f EA |
917 | I915_WRITE(IIR, iir); |
918 | new_iir = I915_READ(IIR); /* Flush posted writes */ | |
7c463586 | 919 | |
7c1c2871 DA |
920 | if (dev->primary->master) { |
921 | master_priv = dev->primary->master->driver_priv; | |
922 | if (master_priv->sarea_priv) | |
923 | master_priv->sarea_priv->last_dispatch = | |
924 | READ_BREADCRUMB(dev_priv); | |
925 | } | |
0a3e67a4 | 926 | |
cdfbc41f | 927 | if (iir & I915_USER_INTERRUPT) { |
1c5d22f7 CW |
928 | u32 seqno = i915_get_gem_seqno(dev); |
929 | dev_priv->mm.irq_gem_seqno = seqno; | |
930 | trace_i915_gem_request_complete(dev, seqno); | |
cdfbc41f | 931 | DRM_WAKEUP(&dev_priv->irq_queue); |
f65d9421 BG |
932 | dev_priv->hangcheck_count = 0; |
933 | mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); | |
cdfbc41f | 934 | } |
673a394b | 935 | |
6b95a207 KH |
936 | if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) |
937 | intel_prepare_page_flip(dev, 0); | |
938 | ||
939 | if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) | |
940 | intel_prepare_page_flip(dev, 1); | |
941 | ||
05eff845 | 942 | if (pipea_stats & vblank_status) { |
cdfbc41f EA |
943 | vblank++; |
944 | drm_handle_vblank(dev, 0); | |
6b95a207 | 945 | intel_finish_page_flip(dev, 0); |
cdfbc41f | 946 | } |
7c463586 | 947 | |
05eff845 | 948 | if (pipeb_stats & vblank_status) { |
cdfbc41f EA |
949 | vblank++; |
950 | drm_handle_vblank(dev, 1); | |
6b95a207 | 951 | intel_finish_page_flip(dev, 1); |
cdfbc41f | 952 | } |
7c463586 | 953 | |
edcb49ca ZY |
954 | if ((pipea_stats & I915_LEGACY_BLC_EVENT_STATUS) || |
955 | (pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) || | |
cdfbc41f EA |
956 | (iir & I915_ASLE_INTERRUPT)) |
957 | opregion_asle_intr(dev); | |
958 | ||
959 | /* With MSI, interrupts are only generated when iir | |
960 | * transitions from zero to nonzero. If another bit got | |
961 | * set while we were handling the existing iir bits, then | |
962 | * we would never get another interrupt. | |
963 | * | |
964 | * This is fine on non-MSI as well, as if we hit this path | |
965 | * we avoid exiting the interrupt handler only to generate | |
966 | * another one. | |
967 | * | |
968 | * Note that for MSI this could cause a stray interrupt report | |
969 | * if an interrupt landed in the time between writing IIR and | |
970 | * the posting read. This should be rare enough to never | |
971 | * trigger the 99% of 100,000 interrupts test for disabling | |
972 | * stray interrupts. | |
973 | */ | |
974 | iir = new_iir; | |
05eff845 | 975 | } |
0a3e67a4 | 976 | |
05eff845 | 977 | return ret; |
1da177e4 LT |
978 | } |
979 | ||
af6061af | 980 | static int i915_emit_irq(struct drm_device * dev) |
1da177e4 LT |
981 | { |
982 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 983 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 LT |
984 | RING_LOCALS; |
985 | ||
986 | i915_kernel_lost_context(dev); | |
987 | ||
44d98a61 | 988 | DRM_DEBUG_DRIVER("\n"); |
1da177e4 | 989 | |
c99b058f | 990 | dev_priv->counter++; |
c29b669c | 991 | if (dev_priv->counter > 0x7FFFFFFFUL) |
c99b058f | 992 | dev_priv->counter = 1; |
7c1c2871 DA |
993 | if (master_priv->sarea_priv) |
994 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; | |
c29b669c | 995 | |
0baf823a | 996 | BEGIN_LP_RING(4); |
585fb111 | 997 | OUT_RING(MI_STORE_DWORD_INDEX); |
0baf823a | 998 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
c29b669c | 999 | OUT_RING(dev_priv->counter); |
585fb111 | 1000 | OUT_RING(MI_USER_INTERRUPT); |
1da177e4 | 1001 | ADVANCE_LP_RING(); |
bc5f4523 | 1002 | |
c29b669c | 1003 | return dev_priv->counter; |
1da177e4 LT |
1004 | } |
1005 | ||
673a394b | 1006 | void i915_user_irq_get(struct drm_device *dev) |
ed4cb414 EA |
1007 | { |
1008 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 1009 | unsigned long irqflags; |
ed4cb414 | 1010 | |
e9d21d7f | 1011 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
036a4a7d | 1012 | if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) { |
bad720ff | 1013 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 1014 | ironlake_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT); |
036a4a7d ZW |
1015 | else |
1016 | i915_enable_irq(dev_priv, I915_USER_INTERRUPT); | |
1017 | } | |
e9d21d7f | 1018 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
ed4cb414 EA |
1019 | } |
1020 | ||
0a3e67a4 | 1021 | void i915_user_irq_put(struct drm_device *dev) |
ed4cb414 EA |
1022 | { |
1023 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 1024 | unsigned long irqflags; |
ed4cb414 | 1025 | |
e9d21d7f | 1026 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
ed4cb414 | 1027 | BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0); |
036a4a7d | 1028 | if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) { |
bad720ff | 1029 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 1030 | ironlake_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT); |
036a4a7d ZW |
1031 | else |
1032 | i915_disable_irq(dev_priv, I915_USER_INTERRUPT); | |
1033 | } | |
e9d21d7f | 1034 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
ed4cb414 EA |
1035 | } |
1036 | ||
9d34e5db CW |
1037 | void i915_trace_irq_get(struct drm_device *dev, u32 seqno) |
1038 | { | |
1039 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1040 | ||
1041 | if (dev_priv->trace_irq_seqno == 0) | |
1042 | i915_user_irq_get(dev); | |
1043 | ||
1044 | dev_priv->trace_irq_seqno = seqno; | |
1045 | } | |
1046 | ||
84b1fd10 | 1047 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) |
1da177e4 LT |
1048 | { |
1049 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
7c1c2871 | 1050 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 LT |
1051 | int ret = 0; |
1052 | ||
44d98a61 | 1053 | DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr, |
1da177e4 LT |
1054 | READ_BREADCRUMB(dev_priv)); |
1055 | ||
ed4cb414 | 1056 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { |
7c1c2871 DA |
1057 | if (master_priv->sarea_priv) |
1058 | master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); | |
1da177e4 | 1059 | return 0; |
ed4cb414 | 1060 | } |
1da177e4 | 1061 | |
7c1c2871 DA |
1062 | if (master_priv->sarea_priv) |
1063 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1da177e4 | 1064 | |
ed4cb414 | 1065 | i915_user_irq_get(dev); |
1da177e4 LT |
1066 | DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ, |
1067 | READ_BREADCRUMB(dev_priv) >= irq_nr); | |
ed4cb414 | 1068 | i915_user_irq_put(dev); |
1da177e4 | 1069 | |
20caafa6 | 1070 | if (ret == -EBUSY) { |
3e684eae | 1071 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", |
1da177e4 LT |
1072 | READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); |
1073 | } | |
1074 | ||
af6061af DA |
1075 | return ret; |
1076 | } | |
1077 | ||
1da177e4 LT |
1078 | /* Needs the lock as it touches the ring. |
1079 | */ | |
c153f45f EA |
1080 | int i915_irq_emit(struct drm_device *dev, void *data, |
1081 | struct drm_file *file_priv) | |
1da177e4 | 1082 | { |
1da177e4 | 1083 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1084 | drm_i915_irq_emit_t *emit = data; |
1da177e4 LT |
1085 | int result; |
1086 | ||
07f4f8bf | 1087 | if (!dev_priv || !dev_priv->ring.virtual_start) { |
3e684eae | 1088 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1089 | return -EINVAL; |
1da177e4 | 1090 | } |
299eb93c EA |
1091 | |
1092 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); | |
1093 | ||
546b0974 | 1094 | mutex_lock(&dev->struct_mutex); |
1da177e4 | 1095 | result = i915_emit_irq(dev); |
546b0974 | 1096 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 1097 | |
c153f45f | 1098 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { |
1da177e4 | 1099 | DRM_ERROR("copy_to_user\n"); |
20caafa6 | 1100 | return -EFAULT; |
1da177e4 LT |
1101 | } |
1102 | ||
1103 | return 0; | |
1104 | } | |
1105 | ||
1106 | /* Doesn't need the hardware lock. | |
1107 | */ | |
c153f45f EA |
1108 | int i915_irq_wait(struct drm_device *dev, void *data, |
1109 | struct drm_file *file_priv) | |
1da177e4 | 1110 | { |
1da177e4 | 1111 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1112 | drm_i915_irq_wait_t *irqwait = data; |
1da177e4 LT |
1113 | |
1114 | if (!dev_priv) { | |
3e684eae | 1115 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1116 | return -EINVAL; |
1da177e4 LT |
1117 | } |
1118 | ||
c153f45f | 1119 | return i915_wait_irq(dev, irqwait->irq_seq); |
1da177e4 LT |
1120 | } |
1121 | ||
42f52ef8 KP |
1122 | /* Called from drm generic code, passed 'crtc' which |
1123 | * we use as a pipe index | |
1124 | */ | |
1125 | int i915_enable_vblank(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
1126 | { |
1127 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 1128 | unsigned long irqflags; |
71e0ffa5 JB |
1129 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; |
1130 | u32 pipeconf; | |
1131 | ||
1132 | pipeconf = I915_READ(pipeconf_reg); | |
1133 | if (!(pipeconf & PIPEACONF_ENABLE)) | |
1134 | return -EINVAL; | |
0a3e67a4 | 1135 | |
e9d21d7f | 1136 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
bad720ff | 1137 | if (HAS_PCH_SPLIT(dev)) |
c062df61 LP |
1138 | ironlake_enable_display_irq(dev_priv, (pipe == 0) ? |
1139 | DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); | |
1140 | else if (IS_I965G(dev)) | |
7c463586 KP |
1141 | i915_enable_pipestat(dev_priv, pipe, |
1142 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 1143 | else |
7c463586 KP |
1144 | i915_enable_pipestat(dev_priv, pipe, |
1145 | PIPE_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 1146 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
0a3e67a4 JB |
1147 | return 0; |
1148 | } | |
1149 | ||
42f52ef8 KP |
1150 | /* Called from drm generic code, passed 'crtc' which |
1151 | * we use as a pipe index | |
1152 | */ | |
1153 | void i915_disable_vblank(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
1154 | { |
1155 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 1156 | unsigned long irqflags; |
0a3e67a4 | 1157 | |
e9d21d7f | 1158 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
bad720ff | 1159 | if (HAS_PCH_SPLIT(dev)) |
c062df61 LP |
1160 | ironlake_disable_display_irq(dev_priv, (pipe == 0) ? |
1161 | DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); | |
1162 | else | |
1163 | i915_disable_pipestat(dev_priv, pipe, | |
1164 | PIPE_VBLANK_INTERRUPT_ENABLE | | |
1165 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 1166 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
0a3e67a4 JB |
1167 | } |
1168 | ||
79e53945 JB |
1169 | void i915_enable_interrupt (struct drm_device *dev) |
1170 | { | |
1171 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e170b030 | 1172 | |
bad720ff | 1173 | if (!HAS_PCH_SPLIT(dev)) |
e170b030 | 1174 | opregion_enable_asle(dev); |
79e53945 JB |
1175 | dev_priv->irq_enabled = 1; |
1176 | } | |
1177 | ||
1178 | ||
702880f2 DA |
1179 | /* Set the vblank monitor pipe |
1180 | */ | |
c153f45f EA |
1181 | int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
1182 | struct drm_file *file_priv) | |
702880f2 | 1183 | { |
702880f2 | 1184 | drm_i915_private_t *dev_priv = dev->dev_private; |
702880f2 DA |
1185 | |
1186 | if (!dev_priv) { | |
3e684eae | 1187 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1188 | return -EINVAL; |
702880f2 DA |
1189 | } |
1190 | ||
5b51694a | 1191 | return 0; |
702880f2 DA |
1192 | } |
1193 | ||
c153f45f EA |
1194 | int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
1195 | struct drm_file *file_priv) | |
702880f2 | 1196 | { |
702880f2 | 1197 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1198 | drm_i915_vblank_pipe_t *pipe = data; |
702880f2 DA |
1199 | |
1200 | if (!dev_priv) { | |
3e684eae | 1201 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1202 | return -EINVAL; |
702880f2 DA |
1203 | } |
1204 | ||
0a3e67a4 | 1205 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
c153f45f | 1206 | |
702880f2 DA |
1207 | return 0; |
1208 | } | |
1209 | ||
a6b54f3f MD |
1210 | /** |
1211 | * Schedule buffer swap at given vertical blank. | |
1212 | */ | |
c153f45f EA |
1213 | int i915_vblank_swap(struct drm_device *dev, void *data, |
1214 | struct drm_file *file_priv) | |
a6b54f3f | 1215 | { |
bd95e0a4 EA |
1216 | /* The delayed swap mechanism was fundamentally racy, and has been |
1217 | * removed. The model was that the client requested a delayed flip/swap | |
1218 | * from the kernel, then waited for vblank before continuing to perform | |
1219 | * rendering. The problem was that the kernel might wake the client | |
1220 | * up before it dispatched the vblank swap (since the lock has to be | |
1221 | * held while touching the ringbuffer), in which case the client would | |
1222 | * clear and start the next frame before the swap occurred, and | |
1223 | * flicker would occur in addition to likely missing the vblank. | |
1224 | * | |
1225 | * In the absence of this ioctl, userland falls back to a correct path | |
1226 | * of waiting for a vblank, then dispatching the swap on its own. | |
1227 | * Context switching to userland and back is plenty fast enough for | |
1228 | * meeting the requirements of vblank swapping. | |
0a3e67a4 | 1229 | */ |
bd95e0a4 | 1230 | return -EINVAL; |
a6b54f3f MD |
1231 | } |
1232 | ||
f65d9421 BG |
1233 | struct drm_i915_gem_request *i915_get_tail_request(struct drm_device *dev) { |
1234 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1235 | return list_entry(dev_priv->mm.request_list.prev, struct drm_i915_gem_request, list); | |
1236 | } | |
1237 | ||
1238 | /** | |
1239 | * This is called when the chip hasn't reported back with completed | |
1240 | * batchbuffers in a long time. The first time this is called we simply record | |
1241 | * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses | |
1242 | * again, we assume the chip is wedged and try to fix it. | |
1243 | */ | |
1244 | void i915_hangcheck_elapsed(unsigned long data) | |
1245 | { | |
1246 | struct drm_device *dev = (struct drm_device *)data; | |
1247 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1248 | uint32_t acthd; | |
b9201c14 EA |
1249 | |
1250 | /* No reset support on this chip yet. */ | |
1251 | if (IS_GEN6(dev)) | |
1252 | return; | |
1253 | ||
f65d9421 BG |
1254 | if (!IS_I965G(dev)) |
1255 | acthd = I915_READ(ACTHD); | |
1256 | else | |
1257 | acthd = I915_READ(ACTHD_I965); | |
1258 | ||
1259 | /* If all work is done then ACTHD clearly hasn't advanced. */ | |
1260 | if (list_empty(&dev_priv->mm.request_list) || | |
1261 | i915_seqno_passed(i915_get_gem_seqno(dev), i915_get_tail_request(dev)->seqno)) { | |
1262 | dev_priv->hangcheck_count = 0; | |
1263 | return; | |
1264 | } | |
1265 | ||
1266 | if (dev_priv->last_acthd == acthd && dev_priv->hangcheck_count > 0) { | |
1267 | DRM_ERROR("Hangcheck timer elapsed... GPU hung\n"); | |
ba1234d1 | 1268 | i915_handle_error(dev, true); |
f65d9421 BG |
1269 | return; |
1270 | } | |
1271 | ||
1272 | /* Reset timer case chip hangs without another request being added */ | |
1273 | mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); | |
1274 | ||
1275 | if (acthd != dev_priv->last_acthd) | |
1276 | dev_priv->hangcheck_count = 0; | |
1277 | else | |
1278 | dev_priv->hangcheck_count++; | |
1279 | ||
1280 | dev_priv->last_acthd = acthd; | |
1281 | } | |
1282 | ||
1da177e4 LT |
1283 | /* drm_dma.h hooks |
1284 | */ | |
f2b115e6 | 1285 | static void ironlake_irq_preinstall(struct drm_device *dev) |
036a4a7d ZW |
1286 | { |
1287 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1288 | ||
1289 | I915_WRITE(HWSTAM, 0xeffe); | |
1290 | ||
1291 | /* XXX hotplug from PCH */ | |
1292 | ||
1293 | I915_WRITE(DEIMR, 0xffffffff); | |
1294 | I915_WRITE(DEIER, 0x0); | |
1295 | (void) I915_READ(DEIER); | |
1296 | ||
1297 | /* and GT */ | |
1298 | I915_WRITE(GTIMR, 0xffffffff); | |
1299 | I915_WRITE(GTIER, 0x0); | |
1300 | (void) I915_READ(GTIER); | |
c650156a ZW |
1301 | |
1302 | /* south display irq */ | |
1303 | I915_WRITE(SDEIMR, 0xffffffff); | |
1304 | I915_WRITE(SDEIER, 0x0); | |
1305 | (void) I915_READ(SDEIER); | |
036a4a7d ZW |
1306 | } |
1307 | ||
f2b115e6 | 1308 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d ZW |
1309 | { |
1310 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1311 | /* enable kind of interrupts always enabled */ | |
013d5aa2 JB |
1312 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | |
1313 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; | |
036a4a7d | 1314 | u32 render_mask = GT_USER_INTERRUPT; |
c650156a ZW |
1315 | u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG | |
1316 | SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG; | |
036a4a7d ZW |
1317 | |
1318 | dev_priv->irq_mask_reg = ~display_mask; | |
643ced9b | 1319 | dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK; |
036a4a7d ZW |
1320 | |
1321 | /* should always can generate irq */ | |
1322 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1323 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); | |
1324 | I915_WRITE(DEIER, dev_priv->de_irq_enable_reg); | |
1325 | (void) I915_READ(DEIER); | |
1326 | ||
1327 | /* user interrupt should be enabled, but masked initial */ | |
1328 | dev_priv->gt_irq_mask_reg = 0xffffffff; | |
1329 | dev_priv->gt_irq_enable_reg = render_mask; | |
1330 | ||
1331 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1332 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); | |
1333 | I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg); | |
1334 | (void) I915_READ(GTIER); | |
1335 | ||
c650156a ZW |
1336 | dev_priv->pch_irq_mask_reg = ~hotplug_mask; |
1337 | dev_priv->pch_irq_enable_reg = hotplug_mask; | |
1338 | ||
1339 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | |
1340 | I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg); | |
1341 | I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg); | |
1342 | (void) I915_READ(SDEIER); | |
1343 | ||
f97108d1 JB |
1344 | if (IS_IRONLAKE_M(dev)) { |
1345 | /* Clear & enable PCU event interrupts */ | |
1346 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
1347 | I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT); | |
1348 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); | |
1349 | } | |
1350 | ||
036a4a7d ZW |
1351 | return 0; |
1352 | } | |
1353 | ||
84b1fd10 | 1354 | void i915_driver_irq_preinstall(struct drm_device * dev) |
1da177e4 LT |
1355 | { |
1356 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1357 | ||
79e53945 JB |
1358 | atomic_set(&dev_priv->irq_received, 0); |
1359 | ||
036a4a7d | 1360 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); |
8a905236 | 1361 | INIT_WORK(&dev_priv->error_work, i915_error_work_func); |
036a4a7d | 1362 | |
bad720ff | 1363 | if (HAS_PCH_SPLIT(dev)) { |
f2b115e6 | 1364 | ironlake_irq_preinstall(dev); |
036a4a7d ZW |
1365 | return; |
1366 | } | |
1367 | ||
5ca58282 JB |
1368 | if (I915_HAS_HOTPLUG(dev)) { |
1369 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
1370 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
1371 | } | |
1372 | ||
0a3e67a4 | 1373 | I915_WRITE(HWSTAM, 0xeffe); |
7c463586 KP |
1374 | I915_WRITE(PIPEASTAT, 0); |
1375 | I915_WRITE(PIPEBSTAT, 0); | |
0a3e67a4 | 1376 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 1377 | I915_WRITE(IER, 0x0); |
7c463586 | 1378 | (void) I915_READ(IER); |
1da177e4 LT |
1379 | } |
1380 | ||
b01f2c3a JB |
1381 | /* |
1382 | * Must be called after intel_modeset_init or hotplug interrupts won't be | |
1383 | * enabled correctly. | |
1384 | */ | |
0a3e67a4 | 1385 | int i915_driver_irq_postinstall(struct drm_device *dev) |
1da177e4 LT |
1386 | { |
1387 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
5ca58282 | 1388 | u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR; |
63eeaf38 | 1389 | u32 error_mask; |
0a3e67a4 | 1390 | |
036a4a7d ZW |
1391 | DRM_INIT_WAITQUEUE(&dev_priv->irq_queue); |
1392 | ||
0a3e67a4 | 1393 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
0a3e67a4 | 1394 | |
bad720ff | 1395 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 1396 | return ironlake_irq_postinstall(dev); |
036a4a7d | 1397 | |
7c463586 KP |
1398 | /* Unmask the interrupts that we always want on. */ |
1399 | dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX; | |
1400 | ||
1401 | dev_priv->pipestat[0] = 0; | |
1402 | dev_priv->pipestat[1] = 0; | |
1403 | ||
5ca58282 JB |
1404 | if (I915_HAS_HOTPLUG(dev)) { |
1405 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
1406 | ||
b01f2c3a JB |
1407 | /* Note HDMI and DP share bits */ |
1408 | if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) | |
1409 | hotplug_en |= HDMIB_HOTPLUG_INT_EN; | |
1410 | if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) | |
1411 | hotplug_en |= HDMIC_HOTPLUG_INT_EN; | |
1412 | if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) | |
1413 | hotplug_en |= HDMID_HOTPLUG_INT_EN; | |
1414 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS) | |
1415 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; | |
1416 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS) | |
1417 | hotplug_en |= SDVOB_HOTPLUG_INT_EN; | |
1418 | if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) | |
1419 | hotplug_en |= CRT_HOTPLUG_INT_EN; | |
1420 | /* Ignore TV since it's buggy */ | |
1421 | ||
5ca58282 JB |
1422 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); |
1423 | ||
5ca58282 JB |
1424 | /* Enable in IER... */ |
1425 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
1426 | /* and unmask in IMR */ | |
1427 | i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT); | |
1428 | } | |
1429 | ||
63eeaf38 JB |
1430 | /* |
1431 | * Enable some error detection, note the instruction error mask | |
1432 | * bit is reserved, so we leave it masked. | |
1433 | */ | |
1434 | if (IS_G4X(dev)) { | |
1435 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
1436 | GM45_ERROR_MEM_PRIV | | |
1437 | GM45_ERROR_CP_PRIV | | |
1438 | I915_ERROR_MEMORY_REFRESH); | |
1439 | } else { | |
1440 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
1441 | I915_ERROR_MEMORY_REFRESH); | |
1442 | } | |
1443 | I915_WRITE(EMR, error_mask); | |
1444 | ||
7c463586 KP |
1445 | /* Disable pipe interrupt enables, clear pending pipe status */ |
1446 | I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); | |
1447 | I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); | |
1448 | /* Clear pending interrupt status */ | |
1449 | I915_WRITE(IIR, I915_READ(IIR)); | |
8ee1c3db | 1450 | |
5ca58282 | 1451 | I915_WRITE(IER, enable_mask); |
7c463586 | 1452 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
ed4cb414 EA |
1453 | (void) I915_READ(IER); |
1454 | ||
8ee1c3db | 1455 | opregion_enable_asle(dev); |
0a3e67a4 JB |
1456 | |
1457 | return 0; | |
1da177e4 LT |
1458 | } |
1459 | ||
f2b115e6 | 1460 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d ZW |
1461 | { |
1462 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1463 | I915_WRITE(HWSTAM, 0xffffffff); | |
1464 | ||
1465 | I915_WRITE(DEIMR, 0xffffffff); | |
1466 | I915_WRITE(DEIER, 0x0); | |
1467 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1468 | ||
1469 | I915_WRITE(GTIMR, 0xffffffff); | |
1470 | I915_WRITE(GTIER, 0x0); | |
1471 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1472 | } | |
1473 | ||
84b1fd10 | 1474 | void i915_driver_irq_uninstall(struct drm_device * dev) |
1da177e4 LT |
1475 | { |
1476 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
91e3738e | 1477 | |
1da177e4 LT |
1478 | if (!dev_priv) |
1479 | return; | |
1480 | ||
0a3e67a4 JB |
1481 | dev_priv->vblank_pipe = 0; |
1482 | ||
bad720ff | 1483 | if (HAS_PCH_SPLIT(dev)) { |
f2b115e6 | 1484 | ironlake_irq_uninstall(dev); |
036a4a7d ZW |
1485 | return; |
1486 | } | |
1487 | ||
5ca58282 JB |
1488 | if (I915_HAS_HOTPLUG(dev)) { |
1489 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
1490 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
1491 | } | |
1492 | ||
0a3e67a4 | 1493 | I915_WRITE(HWSTAM, 0xffffffff); |
7c463586 KP |
1494 | I915_WRITE(PIPEASTAT, 0); |
1495 | I915_WRITE(PIPEBSTAT, 0); | |
0a3e67a4 | 1496 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 1497 | I915_WRITE(IER, 0x0); |
af6061af | 1498 | |
7c463586 KP |
1499 | I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); |
1500 | I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); | |
1501 | I915_WRITE(IIR, I915_READ(IIR)); | |
1da177e4 | 1502 | } |