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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
63eeaf38 | 31 | #include <linux/sysrq.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
b2c88f5b | 33 | #include <linux/circ_buf.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/i915_drm.h> | |
1da177e4 | 36 | #include "i915_drv.h" |
1c5d22f7 | 37 | #include "i915_trace.h" |
79e53945 | 38 | #include "intel_drv.h" |
1da177e4 | 39 | |
e5868a31 EE |
40 | static const u32 hpd_ibx[] = { |
41 | [HPD_CRT] = SDE_CRT_HOTPLUG, | |
42 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, | |
43 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG, | |
44 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG, | |
45 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG | |
46 | }; | |
47 | ||
48 | static const u32 hpd_cpt[] = { | |
49 | [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, | |
73c352a2 | 50 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, |
e5868a31 EE |
51 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
52 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
53 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT | |
54 | }; | |
55 | ||
56 | static const u32 hpd_mask_i915[] = { | |
57 | [HPD_CRT] = CRT_HOTPLUG_INT_EN, | |
58 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, | |
59 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, | |
60 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, | |
61 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, | |
62 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN | |
63 | }; | |
64 | ||
704cfb87 | 65 | static const u32 hpd_status_g4x[] = { |
e5868a31 EE |
66 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
67 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, | |
68 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, | |
69 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
70 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
71 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
72 | }; | |
73 | ||
e5868a31 EE |
74 | static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ |
75 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, | |
76 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, | |
77 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, | |
78 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
79 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
80 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
81 | }; | |
82 | ||
036a4a7d | 83 | /* For display hotplug interrupt */ |
995b6762 | 84 | static void |
f2b115e6 | 85 | ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d | 86 | { |
4bc9d430 DV |
87 | assert_spin_locked(&dev_priv->irq_lock); |
88 | ||
c67a470b PZ |
89 | if (dev_priv->pc8.irqs_disabled) { |
90 | WARN(1, "IRQs disabled\n"); | |
91 | dev_priv->pc8.regsave.deimr &= ~mask; | |
92 | return; | |
93 | } | |
94 | ||
1ec14ad3 CW |
95 | if ((dev_priv->irq_mask & mask) != 0) { |
96 | dev_priv->irq_mask &= ~mask; | |
97 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 98 | POSTING_READ(DEIMR); |
036a4a7d ZW |
99 | } |
100 | } | |
101 | ||
0ff9800a | 102 | static void |
f2b115e6 | 103 | ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d | 104 | { |
4bc9d430 DV |
105 | assert_spin_locked(&dev_priv->irq_lock); |
106 | ||
c67a470b PZ |
107 | if (dev_priv->pc8.irqs_disabled) { |
108 | WARN(1, "IRQs disabled\n"); | |
109 | dev_priv->pc8.regsave.deimr |= mask; | |
110 | return; | |
111 | } | |
112 | ||
1ec14ad3 CW |
113 | if ((dev_priv->irq_mask & mask) != mask) { |
114 | dev_priv->irq_mask |= mask; | |
115 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 116 | POSTING_READ(DEIMR); |
036a4a7d ZW |
117 | } |
118 | } | |
119 | ||
43eaea13 PZ |
120 | /** |
121 | * ilk_update_gt_irq - update GTIMR | |
122 | * @dev_priv: driver private | |
123 | * @interrupt_mask: mask of interrupt bits to update | |
124 | * @enabled_irq_mask: mask of interrupt bits to enable | |
125 | */ | |
126 | static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, | |
127 | uint32_t interrupt_mask, | |
128 | uint32_t enabled_irq_mask) | |
129 | { | |
130 | assert_spin_locked(&dev_priv->irq_lock); | |
131 | ||
c67a470b PZ |
132 | if (dev_priv->pc8.irqs_disabled) { |
133 | WARN(1, "IRQs disabled\n"); | |
134 | dev_priv->pc8.regsave.gtimr &= ~interrupt_mask; | |
135 | dev_priv->pc8.regsave.gtimr |= (~enabled_irq_mask & | |
136 | interrupt_mask); | |
137 | return; | |
138 | } | |
139 | ||
43eaea13 PZ |
140 | dev_priv->gt_irq_mask &= ~interrupt_mask; |
141 | dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); | |
142 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
143 | POSTING_READ(GTIMR); | |
144 | } | |
145 | ||
146 | void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
147 | { | |
148 | ilk_update_gt_irq(dev_priv, mask, mask); | |
149 | } | |
150 | ||
151 | void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
152 | { | |
153 | ilk_update_gt_irq(dev_priv, mask, 0); | |
154 | } | |
155 | ||
edbfdb45 PZ |
156 | /** |
157 | * snb_update_pm_irq - update GEN6_PMIMR | |
158 | * @dev_priv: driver private | |
159 | * @interrupt_mask: mask of interrupt bits to update | |
160 | * @enabled_irq_mask: mask of interrupt bits to enable | |
161 | */ | |
162 | static void snb_update_pm_irq(struct drm_i915_private *dev_priv, | |
163 | uint32_t interrupt_mask, | |
164 | uint32_t enabled_irq_mask) | |
165 | { | |
605cd25b | 166 | uint32_t new_val; |
edbfdb45 PZ |
167 | |
168 | assert_spin_locked(&dev_priv->irq_lock); | |
169 | ||
c67a470b PZ |
170 | if (dev_priv->pc8.irqs_disabled) { |
171 | WARN(1, "IRQs disabled\n"); | |
172 | dev_priv->pc8.regsave.gen6_pmimr &= ~interrupt_mask; | |
173 | dev_priv->pc8.regsave.gen6_pmimr |= (~enabled_irq_mask & | |
174 | interrupt_mask); | |
175 | return; | |
176 | } | |
177 | ||
605cd25b | 178 | new_val = dev_priv->pm_irq_mask; |
f52ecbcf PZ |
179 | new_val &= ~interrupt_mask; |
180 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
181 | ||
605cd25b PZ |
182 | if (new_val != dev_priv->pm_irq_mask) { |
183 | dev_priv->pm_irq_mask = new_val; | |
184 | I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask); | |
f52ecbcf PZ |
185 | POSTING_READ(GEN6_PMIMR); |
186 | } | |
edbfdb45 PZ |
187 | } |
188 | ||
189 | void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
190 | { | |
191 | snb_update_pm_irq(dev_priv, mask, mask); | |
192 | } | |
193 | ||
194 | void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
195 | { | |
196 | snb_update_pm_irq(dev_priv, mask, 0); | |
197 | } | |
198 | ||
8664281b PZ |
199 | static bool ivb_can_enable_err_int(struct drm_device *dev) |
200 | { | |
201 | struct drm_i915_private *dev_priv = dev->dev_private; | |
202 | struct intel_crtc *crtc; | |
203 | enum pipe pipe; | |
204 | ||
4bc9d430 DV |
205 | assert_spin_locked(&dev_priv->irq_lock); |
206 | ||
8664281b PZ |
207 | for_each_pipe(pipe) { |
208 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
209 | ||
210 | if (crtc->cpu_fifo_underrun_disabled) | |
211 | return false; | |
212 | } | |
213 | ||
214 | return true; | |
215 | } | |
216 | ||
217 | static bool cpt_can_enable_serr_int(struct drm_device *dev) | |
218 | { | |
219 | struct drm_i915_private *dev_priv = dev->dev_private; | |
220 | enum pipe pipe; | |
221 | struct intel_crtc *crtc; | |
222 | ||
fee884ed DV |
223 | assert_spin_locked(&dev_priv->irq_lock); |
224 | ||
8664281b PZ |
225 | for_each_pipe(pipe) { |
226 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
227 | ||
228 | if (crtc->pch_fifo_underrun_disabled) | |
229 | return false; | |
230 | } | |
231 | ||
232 | return true; | |
233 | } | |
234 | ||
2d9d2b0b VS |
235 | static void i9xx_clear_fifo_underrun(struct drm_device *dev, enum pipe pipe) |
236 | { | |
237 | struct drm_i915_private *dev_priv = dev->dev_private; | |
238 | u32 reg = PIPESTAT(pipe); | |
239 | u32 pipestat = I915_READ(reg) & 0x7fff0000; | |
240 | ||
241 | assert_spin_locked(&dev_priv->irq_lock); | |
242 | ||
243 | I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS); | |
244 | POSTING_READ(reg); | |
245 | } | |
246 | ||
8664281b PZ |
247 | static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev, |
248 | enum pipe pipe, bool enable) | |
249 | { | |
250 | struct drm_i915_private *dev_priv = dev->dev_private; | |
251 | uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN : | |
252 | DE_PIPEB_FIFO_UNDERRUN; | |
253 | ||
254 | if (enable) | |
255 | ironlake_enable_display_irq(dev_priv, bit); | |
256 | else | |
257 | ironlake_disable_display_irq(dev_priv, bit); | |
258 | } | |
259 | ||
260 | static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev, | |
7336df65 | 261 | enum pipe pipe, bool enable) |
8664281b PZ |
262 | { |
263 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8664281b | 264 | if (enable) { |
7336df65 DV |
265 | I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); |
266 | ||
8664281b PZ |
267 | if (!ivb_can_enable_err_int(dev)) |
268 | return; | |
269 | ||
8664281b PZ |
270 | ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB); |
271 | } else { | |
7336df65 DV |
272 | bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB); |
273 | ||
274 | /* Change the state _after_ we've read out the current one. */ | |
8664281b | 275 | ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB); |
7336df65 DV |
276 | |
277 | if (!was_enabled && | |
278 | (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) { | |
279 | DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n", | |
280 | pipe_name(pipe)); | |
281 | } | |
8664281b PZ |
282 | } |
283 | } | |
284 | ||
38d83c96 DV |
285 | static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev, |
286 | enum pipe pipe, bool enable) | |
287 | { | |
288 | struct drm_i915_private *dev_priv = dev->dev_private; | |
289 | ||
290 | assert_spin_locked(&dev_priv->irq_lock); | |
291 | ||
292 | if (enable) | |
293 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN; | |
294 | else | |
295 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN; | |
296 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
297 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
298 | } | |
299 | ||
fee884ed DV |
300 | /** |
301 | * ibx_display_interrupt_update - update SDEIMR | |
302 | * @dev_priv: driver private | |
303 | * @interrupt_mask: mask of interrupt bits to update | |
304 | * @enabled_irq_mask: mask of interrupt bits to enable | |
305 | */ | |
306 | static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, | |
307 | uint32_t interrupt_mask, | |
308 | uint32_t enabled_irq_mask) | |
309 | { | |
310 | uint32_t sdeimr = I915_READ(SDEIMR); | |
311 | sdeimr &= ~interrupt_mask; | |
312 | sdeimr |= (~enabled_irq_mask & interrupt_mask); | |
313 | ||
314 | assert_spin_locked(&dev_priv->irq_lock); | |
315 | ||
c67a470b PZ |
316 | if (dev_priv->pc8.irqs_disabled && |
317 | (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) { | |
318 | WARN(1, "IRQs disabled\n"); | |
319 | dev_priv->pc8.regsave.sdeimr &= ~interrupt_mask; | |
320 | dev_priv->pc8.regsave.sdeimr |= (~enabled_irq_mask & | |
321 | interrupt_mask); | |
322 | return; | |
323 | } | |
324 | ||
fee884ed DV |
325 | I915_WRITE(SDEIMR, sdeimr); |
326 | POSTING_READ(SDEIMR); | |
327 | } | |
328 | #define ibx_enable_display_interrupt(dev_priv, bits) \ | |
329 | ibx_display_interrupt_update((dev_priv), (bits), (bits)) | |
330 | #define ibx_disable_display_interrupt(dev_priv, bits) \ | |
331 | ibx_display_interrupt_update((dev_priv), (bits), 0) | |
332 | ||
de28075d DV |
333 | static void ibx_set_fifo_underrun_reporting(struct drm_device *dev, |
334 | enum transcoder pch_transcoder, | |
8664281b PZ |
335 | bool enable) |
336 | { | |
8664281b | 337 | struct drm_i915_private *dev_priv = dev->dev_private; |
de28075d DV |
338 | uint32_t bit = (pch_transcoder == TRANSCODER_A) ? |
339 | SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER; | |
8664281b PZ |
340 | |
341 | if (enable) | |
fee884ed | 342 | ibx_enable_display_interrupt(dev_priv, bit); |
8664281b | 343 | else |
fee884ed | 344 | ibx_disable_display_interrupt(dev_priv, bit); |
8664281b PZ |
345 | } |
346 | ||
347 | static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, | |
348 | enum transcoder pch_transcoder, | |
349 | bool enable) | |
350 | { | |
351 | struct drm_i915_private *dev_priv = dev->dev_private; | |
352 | ||
353 | if (enable) { | |
1dd246fb DV |
354 | I915_WRITE(SERR_INT, |
355 | SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); | |
356 | ||
8664281b PZ |
357 | if (!cpt_can_enable_serr_int(dev)) |
358 | return; | |
359 | ||
fee884ed | 360 | ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
8664281b | 361 | } else { |
1dd246fb DV |
362 | uint32_t tmp = I915_READ(SERR_INT); |
363 | bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT); | |
364 | ||
365 | /* Change the state _after_ we've read out the current one. */ | |
fee884ed | 366 | ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
1dd246fb DV |
367 | |
368 | if (!was_enabled && | |
369 | (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) { | |
370 | DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n", | |
371 | transcoder_name(pch_transcoder)); | |
372 | } | |
8664281b | 373 | } |
8664281b PZ |
374 | } |
375 | ||
376 | /** | |
377 | * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages | |
378 | * @dev: drm device | |
379 | * @pipe: pipe | |
380 | * @enable: true if we want to report FIFO underrun errors, false otherwise | |
381 | * | |
382 | * This function makes us disable or enable CPU fifo underruns for a specific | |
383 | * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun | |
384 | * reporting for one pipe may also disable all the other CPU error interruts for | |
385 | * the other pipes, due to the fact that there's just one interrupt mask/enable | |
386 | * bit for all the pipes. | |
387 | * | |
388 | * Returns the previous state of underrun reporting. | |
389 | */ | |
390 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, | |
391 | enum pipe pipe, bool enable) | |
392 | { | |
393 | struct drm_i915_private *dev_priv = dev->dev_private; | |
394 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
395 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
396 | unsigned long flags; | |
397 | bool ret; | |
398 | ||
399 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
400 | ||
401 | ret = !intel_crtc->cpu_fifo_underrun_disabled; | |
402 | ||
403 | if (enable == ret) | |
404 | goto done; | |
405 | ||
406 | intel_crtc->cpu_fifo_underrun_disabled = !enable; | |
407 | ||
2d9d2b0b VS |
408 | if (enable && (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))) |
409 | i9xx_clear_fifo_underrun(dev, pipe); | |
410 | else if (IS_GEN5(dev) || IS_GEN6(dev)) | |
8664281b PZ |
411 | ironlake_set_fifo_underrun_reporting(dev, pipe, enable); |
412 | else if (IS_GEN7(dev)) | |
7336df65 | 413 | ivybridge_set_fifo_underrun_reporting(dev, pipe, enable); |
38d83c96 DV |
414 | else if (IS_GEN8(dev)) |
415 | broadwell_set_fifo_underrun_reporting(dev, pipe, enable); | |
8664281b PZ |
416 | |
417 | done: | |
418 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
419 | return ret; | |
420 | } | |
421 | ||
422 | /** | |
423 | * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages | |
424 | * @dev: drm device | |
425 | * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) | |
426 | * @enable: true if we want to report FIFO underrun errors, false otherwise | |
427 | * | |
428 | * This function makes us disable or enable PCH fifo underruns for a specific | |
429 | * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO | |
430 | * underrun reporting for one transcoder may also disable all the other PCH | |
431 | * error interruts for the other transcoders, due to the fact that there's just | |
432 | * one interrupt mask/enable bit for all the transcoders. | |
433 | * | |
434 | * Returns the previous state of underrun reporting. | |
435 | */ | |
436 | bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, | |
437 | enum transcoder pch_transcoder, | |
438 | bool enable) | |
439 | { | |
440 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de28075d DV |
441 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder]; |
442 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8664281b PZ |
443 | unsigned long flags; |
444 | bool ret; | |
445 | ||
de28075d DV |
446 | /* |
447 | * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT | |
448 | * has only one pch transcoder A that all pipes can use. To avoid racy | |
449 | * pch transcoder -> pipe lookups from interrupt code simply store the | |
450 | * underrun statistics in crtc A. Since we never expose this anywhere | |
451 | * nor use it outside of the fifo underrun code here using the "wrong" | |
452 | * crtc on LPT won't cause issues. | |
453 | */ | |
8664281b PZ |
454 | |
455 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
456 | ||
457 | ret = !intel_crtc->pch_fifo_underrun_disabled; | |
458 | ||
459 | if (enable == ret) | |
460 | goto done; | |
461 | ||
462 | intel_crtc->pch_fifo_underrun_disabled = !enable; | |
463 | ||
464 | if (HAS_PCH_IBX(dev)) | |
de28075d | 465 | ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable); |
8664281b PZ |
466 | else |
467 | cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable); | |
468 | ||
469 | done: | |
470 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
471 | return ret; | |
472 | } | |
473 | ||
474 | ||
7c463586 | 475 | void |
755e9019 ID |
476 | __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
477 | u32 enable_mask, u32 status_mask) | |
7c463586 | 478 | { |
46c06a30 | 479 | u32 reg = PIPESTAT(pipe); |
755e9019 | 480 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 481 | |
b79480ba DV |
482 | assert_spin_locked(&dev_priv->irq_lock); |
483 | ||
755e9019 ID |
484 | if (WARN_ON_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
485 | status_mask & ~PIPESTAT_INT_STATUS_MASK)) | |
486 | return; | |
487 | ||
488 | if ((pipestat & enable_mask) == enable_mask) | |
46c06a30 VS |
489 | return; |
490 | ||
491 | /* Enable the interrupt, clear any pending status */ | |
755e9019 | 492 | pipestat |= enable_mask | status_mask; |
46c06a30 VS |
493 | I915_WRITE(reg, pipestat); |
494 | POSTING_READ(reg); | |
7c463586 KP |
495 | } |
496 | ||
497 | void | |
755e9019 ID |
498 | __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
499 | u32 enable_mask, u32 status_mask) | |
7c463586 | 500 | { |
46c06a30 | 501 | u32 reg = PIPESTAT(pipe); |
755e9019 | 502 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 503 | |
b79480ba DV |
504 | assert_spin_locked(&dev_priv->irq_lock); |
505 | ||
755e9019 ID |
506 | if (WARN_ON_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
507 | status_mask & ~PIPESTAT_INT_STATUS_MASK)) | |
46c06a30 VS |
508 | return; |
509 | ||
755e9019 ID |
510 | if ((pipestat & enable_mask) == 0) |
511 | return; | |
512 | ||
513 | pipestat &= ~enable_mask; | |
46c06a30 VS |
514 | I915_WRITE(reg, pipestat); |
515 | POSTING_READ(reg); | |
7c463586 KP |
516 | } |
517 | ||
10c59c51 ID |
518 | static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask) |
519 | { | |
520 | u32 enable_mask = status_mask << 16; | |
521 | ||
522 | /* | |
523 | * On pipe A we don't support the PSR interrupt yet, on pipe B the | |
524 | * same bit MBZ. | |
525 | */ | |
526 | if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV)) | |
527 | return 0; | |
528 | ||
529 | enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | | |
530 | SPRITE0_FLIP_DONE_INT_EN_VLV | | |
531 | SPRITE1_FLIP_DONE_INT_EN_VLV); | |
532 | if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV) | |
533 | enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV; | |
534 | if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV) | |
535 | enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; | |
536 | ||
537 | return enable_mask; | |
538 | } | |
539 | ||
755e9019 ID |
540 | void |
541 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
542 | u32 status_mask) | |
543 | { | |
544 | u32 enable_mask; | |
545 | ||
10c59c51 ID |
546 | if (IS_VALLEYVIEW(dev_priv->dev)) |
547 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, | |
548 | status_mask); | |
549 | else | |
550 | enable_mask = status_mask << 16; | |
755e9019 ID |
551 | __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
552 | } | |
553 | ||
554 | void | |
555 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
556 | u32 status_mask) | |
557 | { | |
558 | u32 enable_mask; | |
559 | ||
10c59c51 ID |
560 | if (IS_VALLEYVIEW(dev_priv->dev)) |
561 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, | |
562 | status_mask); | |
563 | else | |
564 | enable_mask = status_mask << 16; | |
755e9019 ID |
565 | __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
566 | } | |
567 | ||
01c66889 | 568 | /** |
f49e38dd | 569 | * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion |
01c66889 | 570 | */ |
f49e38dd | 571 | static void i915_enable_asle_pipestat(struct drm_device *dev) |
01c66889 | 572 | { |
1ec14ad3 CW |
573 | drm_i915_private_t *dev_priv = dev->dev_private; |
574 | unsigned long irqflags; | |
575 | ||
f49e38dd JN |
576 | if (!dev_priv->opregion.asle || !IS_MOBILE(dev)) |
577 | return; | |
578 | ||
1ec14ad3 | 579 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
01c66889 | 580 | |
755e9019 | 581 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); |
f898780b | 582 | if (INTEL_INFO(dev)->gen >= 4) |
3b6c42e8 | 583 | i915_enable_pipestat(dev_priv, PIPE_A, |
755e9019 | 584 | PIPE_LEGACY_BLC_EVENT_STATUS); |
1ec14ad3 CW |
585 | |
586 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
01c66889 ZY |
587 | } |
588 | ||
0a3e67a4 JB |
589 | /** |
590 | * i915_pipe_enabled - check if a pipe is enabled | |
591 | * @dev: DRM device | |
592 | * @pipe: pipe to check | |
593 | * | |
594 | * Reading certain registers when the pipe is disabled can hang the chip. | |
595 | * Use this routine to make sure the PLL is running and the pipe is active | |
596 | * before reading such registers if unsure. | |
597 | */ | |
598 | static int | |
599 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
600 | { | |
601 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
702e7a56 | 602 | |
a01025af DV |
603 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
604 | /* Locking is horribly broken here, but whatever. */ | |
605 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
606 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
71f8ba6b | 607 | |
a01025af DV |
608 | return intel_crtc->active; |
609 | } else { | |
610 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; | |
611 | } | |
0a3e67a4 JB |
612 | } |
613 | ||
4cdb83ec VS |
614 | static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe) |
615 | { | |
616 | /* Gen2 doesn't have a hardware frame counter */ | |
617 | return 0; | |
618 | } | |
619 | ||
42f52ef8 KP |
620 | /* Called from drm generic code, passed a 'crtc', which |
621 | * we use as a pipe index | |
622 | */ | |
f71d4af4 | 623 | static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
0a3e67a4 JB |
624 | { |
625 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
626 | unsigned long high_frame; | |
627 | unsigned long low_frame; | |
391f75e2 | 628 | u32 high1, high2, low, pixel, vbl_start; |
0a3e67a4 JB |
629 | |
630 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 631 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 632 | "pipe %c\n", pipe_name(pipe)); |
0a3e67a4 JB |
633 | return 0; |
634 | } | |
635 | ||
391f75e2 VS |
636 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
637 | struct intel_crtc *intel_crtc = | |
638 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
639 | const struct drm_display_mode *mode = | |
640 | &intel_crtc->config.adjusted_mode; | |
641 | ||
642 | vbl_start = mode->crtc_vblank_start * mode->crtc_htotal; | |
643 | } else { | |
644 | enum transcoder cpu_transcoder = | |
645 | intel_pipe_to_cpu_transcoder(dev_priv, pipe); | |
646 | u32 htotal; | |
647 | ||
648 | htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1; | |
649 | vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1; | |
650 | ||
651 | vbl_start *= htotal; | |
652 | } | |
653 | ||
9db4a9c7 JB |
654 | high_frame = PIPEFRAME(pipe); |
655 | low_frame = PIPEFRAMEPIXEL(pipe); | |
5eddb70b | 656 | |
0a3e67a4 JB |
657 | /* |
658 | * High & low register fields aren't synchronized, so make sure | |
659 | * we get a low value that's stable across two reads of the high | |
660 | * register. | |
661 | */ | |
662 | do { | |
5eddb70b | 663 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
391f75e2 | 664 | low = I915_READ(low_frame); |
5eddb70b | 665 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
0a3e67a4 JB |
666 | } while (high1 != high2); |
667 | ||
5eddb70b | 668 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
391f75e2 | 669 | pixel = low & PIPE_PIXEL_MASK; |
5eddb70b | 670 | low >>= PIPE_FRAME_LOW_SHIFT; |
391f75e2 VS |
671 | |
672 | /* | |
673 | * The frame counter increments at beginning of active. | |
674 | * Cook up a vblank counter by also checking the pixel | |
675 | * counter against vblank start. | |
676 | */ | |
edc08d0a | 677 | return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; |
0a3e67a4 JB |
678 | } |
679 | ||
f71d4af4 | 680 | static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
9880b7a5 JB |
681 | { |
682 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 683 | int reg = PIPE_FRMCOUNT_GM45(pipe); |
9880b7a5 JB |
684 | |
685 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 686 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 687 | "pipe %c\n", pipe_name(pipe)); |
9880b7a5 JB |
688 | return 0; |
689 | } | |
690 | ||
691 | return I915_READ(reg); | |
692 | } | |
693 | ||
ad3543ed MK |
694 | /* raw reads, only for fast reads of display block, no need for forcewake etc. */ |
695 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) | |
696 | #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__)) | |
697 | ||
095163ba | 698 | static bool ilk_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe) |
54ddcbd2 VS |
699 | { |
700 | struct drm_i915_private *dev_priv = dev->dev_private; | |
701 | uint32_t status; | |
702 | ||
095163ba | 703 | if (INTEL_INFO(dev)->gen < 7) { |
54ddcbd2 VS |
704 | status = pipe == PIPE_A ? |
705 | DE_PIPEA_VBLANK : | |
706 | DE_PIPEB_VBLANK; | |
54ddcbd2 VS |
707 | } else { |
708 | switch (pipe) { | |
709 | default: | |
710 | case PIPE_A: | |
711 | status = DE_PIPEA_VBLANK_IVB; | |
712 | break; | |
713 | case PIPE_B: | |
714 | status = DE_PIPEB_VBLANK_IVB; | |
715 | break; | |
716 | case PIPE_C: | |
717 | status = DE_PIPEC_VBLANK_IVB; | |
718 | break; | |
719 | } | |
54ddcbd2 | 720 | } |
ad3543ed | 721 | |
095163ba | 722 | return __raw_i915_read32(dev_priv, DEISR) & status; |
54ddcbd2 VS |
723 | } |
724 | ||
f71d4af4 | 725 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
abca9e45 VS |
726 | unsigned int flags, int *vpos, int *hpos, |
727 | ktime_t *stime, ktime_t *etime) | |
0af7e4df | 728 | { |
c2baf4b7 VS |
729 | struct drm_i915_private *dev_priv = dev->dev_private; |
730 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
731 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
732 | const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; | |
3aa18df8 | 733 | int position; |
0af7e4df MK |
734 | int vbl_start, vbl_end, htotal, vtotal; |
735 | bool in_vbl = true; | |
736 | int ret = 0; | |
ad3543ed | 737 | unsigned long irqflags; |
0af7e4df | 738 | |
c2baf4b7 | 739 | if (!intel_crtc->active) { |
0af7e4df | 740 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
9db4a9c7 | 741 | "pipe %c\n", pipe_name(pipe)); |
0af7e4df MK |
742 | return 0; |
743 | } | |
744 | ||
c2baf4b7 VS |
745 | htotal = mode->crtc_htotal; |
746 | vtotal = mode->crtc_vtotal; | |
747 | vbl_start = mode->crtc_vblank_start; | |
748 | vbl_end = mode->crtc_vblank_end; | |
0af7e4df | 749 | |
d31faf65 VS |
750 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
751 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
752 | vbl_end /= 2; | |
753 | vtotal /= 2; | |
754 | } | |
755 | ||
c2baf4b7 VS |
756 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; |
757 | ||
ad3543ed MK |
758 | /* |
759 | * Lock uncore.lock, as we will do multiple timing critical raw | |
760 | * register reads, potentially with preemption disabled, so the | |
761 | * following code must not block on uncore.lock. | |
762 | */ | |
763 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
764 | ||
765 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ | |
766 | ||
767 | /* Get optional system timestamp before query. */ | |
768 | if (stime) | |
769 | *stime = ktime_get(); | |
770 | ||
7c06b08a | 771 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
0af7e4df MK |
772 | /* No obvious pixelcount register. Only query vertical |
773 | * scanout position from Display scan line register. | |
774 | */ | |
7c06b08a | 775 | if (IS_GEN2(dev)) |
ad3543ed | 776 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; |
7c06b08a | 777 | else |
ad3543ed | 778 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; |
54ddcbd2 | 779 | |
095163ba VS |
780 | if (HAS_PCH_SPLIT(dev)) { |
781 | /* | |
782 | * The scanline counter increments at the leading edge | |
783 | * of hsync, ie. it completely misses the active portion | |
784 | * of the line. Fix up the counter at both edges of vblank | |
785 | * to get a more accurate picture whether we're in vblank | |
786 | * or not. | |
787 | */ | |
788 | in_vbl = ilk_pipe_in_vblank_locked(dev, pipe); | |
789 | if ((in_vbl && position == vbl_start - 1) || | |
790 | (!in_vbl && position == vbl_end - 1)) | |
791 | position = (position + 1) % vtotal; | |
792 | } else { | |
793 | /* | |
794 | * ISR vblank status bits don't work the way we'd want | |
795 | * them to work on non-PCH platforms (for | |
796 | * ilk_pipe_in_vblank_locked()), and there doesn't | |
797 | * appear any other way to determine if we're currently | |
798 | * in vblank. | |
799 | * | |
800 | * Instead let's assume that we're already in vblank if | |
801 | * we got called from the vblank interrupt and the | |
802 | * scanline counter value indicates that we're on the | |
803 | * line just prior to vblank start. This should result | |
804 | * in the correct answer, unless the vblank interrupt | |
805 | * delivery really got delayed for almost exactly one | |
806 | * full frame/field. | |
807 | */ | |
808 | if (flags & DRM_CALLED_FROM_VBLIRQ && | |
809 | position == vbl_start - 1) { | |
810 | position = (position + 1) % vtotal; | |
811 | ||
812 | /* Signal this correction as "applied". */ | |
813 | ret |= 0x8; | |
814 | } | |
815 | } | |
0af7e4df MK |
816 | } else { |
817 | /* Have access to pixelcount since start of frame. | |
818 | * We can split this into vertical and horizontal | |
819 | * scanout position. | |
820 | */ | |
ad3543ed | 821 | position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; |
0af7e4df | 822 | |
3aa18df8 VS |
823 | /* convert to pixel counts */ |
824 | vbl_start *= htotal; | |
825 | vbl_end *= htotal; | |
826 | vtotal *= htotal; | |
0af7e4df MK |
827 | } |
828 | ||
ad3543ed MK |
829 | /* Get optional system timestamp after query. */ |
830 | if (etime) | |
831 | *etime = ktime_get(); | |
832 | ||
833 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ | |
834 | ||
835 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
836 | ||
3aa18df8 VS |
837 | in_vbl = position >= vbl_start && position < vbl_end; |
838 | ||
839 | /* | |
840 | * While in vblank, position will be negative | |
841 | * counting up towards 0 at vbl_end. And outside | |
842 | * vblank, position will be positive counting | |
843 | * up since vbl_end. | |
844 | */ | |
845 | if (position >= vbl_start) | |
846 | position -= vbl_end; | |
847 | else | |
848 | position += vtotal - vbl_end; | |
0af7e4df | 849 | |
7c06b08a | 850 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
3aa18df8 VS |
851 | *vpos = position; |
852 | *hpos = 0; | |
853 | } else { | |
854 | *vpos = position / htotal; | |
855 | *hpos = position - (*vpos * htotal); | |
856 | } | |
0af7e4df | 857 | |
0af7e4df MK |
858 | /* In vblank? */ |
859 | if (in_vbl) | |
860 | ret |= DRM_SCANOUTPOS_INVBL; | |
861 | ||
862 | return ret; | |
863 | } | |
864 | ||
f71d4af4 | 865 | static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
0af7e4df MK |
866 | int *max_error, |
867 | struct timeval *vblank_time, | |
868 | unsigned flags) | |
869 | { | |
4041b853 | 870 | struct drm_crtc *crtc; |
0af7e4df | 871 | |
7eb552ae | 872 | if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { |
4041b853 | 873 | DRM_ERROR("Invalid crtc %d\n", pipe); |
0af7e4df MK |
874 | return -EINVAL; |
875 | } | |
876 | ||
877 | /* Get drm_crtc to timestamp: */ | |
4041b853 CW |
878 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
879 | if (crtc == NULL) { | |
880 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
881 | return -EINVAL; | |
882 | } | |
883 | ||
884 | if (!crtc->enabled) { | |
885 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); | |
886 | return -EBUSY; | |
887 | } | |
0af7e4df MK |
888 | |
889 | /* Helper routine in DRM core does all the work: */ | |
4041b853 CW |
890 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
891 | vblank_time, flags, | |
7da903ef VS |
892 | crtc, |
893 | &to_intel_crtc(crtc)->config.adjusted_mode); | |
0af7e4df MK |
894 | } |
895 | ||
67c347ff JN |
896 | static bool intel_hpd_irq_event(struct drm_device *dev, |
897 | struct drm_connector *connector) | |
321a1b30 EE |
898 | { |
899 | enum drm_connector_status old_status; | |
900 | ||
901 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); | |
902 | old_status = connector->status; | |
903 | ||
904 | connector->status = connector->funcs->detect(connector, false); | |
67c347ff JN |
905 | if (old_status == connector->status) |
906 | return false; | |
907 | ||
908 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n", | |
321a1b30 EE |
909 | connector->base.id, |
910 | drm_get_connector_name(connector), | |
67c347ff JN |
911 | drm_get_connector_status_name(old_status), |
912 | drm_get_connector_status_name(connector->status)); | |
913 | ||
914 | return true; | |
321a1b30 EE |
915 | } |
916 | ||
5ca58282 JB |
917 | /* |
918 | * Handle hotplug events outside the interrupt handler proper. | |
919 | */ | |
ac4c16c5 EE |
920 | #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000) |
921 | ||
5ca58282 JB |
922 | static void i915_hotplug_work_func(struct work_struct *work) |
923 | { | |
924 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
925 | hotplug_work); | |
926 | struct drm_device *dev = dev_priv->dev; | |
c31c4ba3 | 927 | struct drm_mode_config *mode_config = &dev->mode_config; |
cd569aed EE |
928 | struct intel_connector *intel_connector; |
929 | struct intel_encoder *intel_encoder; | |
930 | struct drm_connector *connector; | |
931 | unsigned long irqflags; | |
932 | bool hpd_disabled = false; | |
321a1b30 | 933 | bool changed = false; |
142e2398 | 934 | u32 hpd_event_bits; |
4ef69c7a | 935 | |
52d7eced DV |
936 | /* HPD irq before everything is fully set up. */ |
937 | if (!dev_priv->enable_hotplug_processing) | |
938 | return; | |
939 | ||
a65e34c7 | 940 | mutex_lock(&mode_config->mutex); |
e67189ab JB |
941 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); |
942 | ||
cd569aed | 943 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
142e2398 EE |
944 | |
945 | hpd_event_bits = dev_priv->hpd_event_bits; | |
946 | dev_priv->hpd_event_bits = 0; | |
cd569aed EE |
947 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
948 | intel_connector = to_intel_connector(connector); | |
949 | intel_encoder = intel_connector->encoder; | |
950 | if (intel_encoder->hpd_pin > HPD_NONE && | |
951 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED && | |
952 | connector->polled == DRM_CONNECTOR_POLL_HPD) { | |
953 | DRM_INFO("HPD interrupt storm detected on connector %s: " | |
954 | "switching from hotplug detection to polling\n", | |
955 | drm_get_connector_name(connector)); | |
956 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED; | |
957 | connector->polled = DRM_CONNECTOR_POLL_CONNECT | |
958 | | DRM_CONNECTOR_POLL_DISCONNECT; | |
959 | hpd_disabled = true; | |
960 | } | |
142e2398 EE |
961 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { |
962 | DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n", | |
963 | drm_get_connector_name(connector), intel_encoder->hpd_pin); | |
964 | } | |
cd569aed EE |
965 | } |
966 | /* if there were no outputs to poll, poll was disabled, | |
967 | * therefore make sure it's enabled when disabling HPD on | |
968 | * some connectors */ | |
ac4c16c5 | 969 | if (hpd_disabled) { |
cd569aed | 970 | drm_kms_helper_poll_enable(dev); |
ac4c16c5 EE |
971 | mod_timer(&dev_priv->hotplug_reenable_timer, |
972 | jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY)); | |
973 | } | |
cd569aed EE |
974 | |
975 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
976 | ||
321a1b30 EE |
977 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
978 | intel_connector = to_intel_connector(connector); | |
979 | intel_encoder = intel_connector->encoder; | |
980 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { | |
981 | if (intel_encoder->hot_plug) | |
982 | intel_encoder->hot_plug(intel_encoder); | |
983 | if (intel_hpd_irq_event(dev, connector)) | |
984 | changed = true; | |
985 | } | |
986 | } | |
40ee3381 KP |
987 | mutex_unlock(&mode_config->mutex); |
988 | ||
321a1b30 EE |
989 | if (changed) |
990 | drm_kms_helper_hotplug_event(dev); | |
5ca58282 JB |
991 | } |
992 | ||
3ca1cced VS |
993 | static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv) |
994 | { | |
995 | del_timer_sync(&dev_priv->hotplug_reenable_timer); | |
996 | } | |
997 | ||
d0ecd7e2 | 998 | static void ironlake_rps_change_irq_handler(struct drm_device *dev) |
f97108d1 JB |
999 | { |
1000 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b5b72e89 | 1001 | u32 busy_up, busy_down, max_avg, min_avg; |
9270388e | 1002 | u8 new_delay; |
9270388e | 1003 | |
d0ecd7e2 | 1004 | spin_lock(&mchdev_lock); |
f97108d1 | 1005 | |
73edd18f DV |
1006 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
1007 | ||
20e4d407 | 1008 | new_delay = dev_priv->ips.cur_delay; |
9270388e | 1009 | |
7648fa99 | 1010 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
1011 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
1012 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
1013 | max_avg = I915_READ(RCBMAXAVG); |
1014 | min_avg = I915_READ(RCBMINAVG); | |
1015 | ||
1016 | /* Handle RCS change request from hw */ | |
b5b72e89 | 1017 | if (busy_up > max_avg) { |
20e4d407 DV |
1018 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
1019 | new_delay = dev_priv->ips.cur_delay - 1; | |
1020 | if (new_delay < dev_priv->ips.max_delay) | |
1021 | new_delay = dev_priv->ips.max_delay; | |
b5b72e89 | 1022 | } else if (busy_down < min_avg) { |
20e4d407 DV |
1023 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
1024 | new_delay = dev_priv->ips.cur_delay + 1; | |
1025 | if (new_delay > dev_priv->ips.min_delay) | |
1026 | new_delay = dev_priv->ips.min_delay; | |
f97108d1 JB |
1027 | } |
1028 | ||
7648fa99 | 1029 | if (ironlake_set_drps(dev, new_delay)) |
20e4d407 | 1030 | dev_priv->ips.cur_delay = new_delay; |
f97108d1 | 1031 | |
d0ecd7e2 | 1032 | spin_unlock(&mchdev_lock); |
9270388e | 1033 | |
f97108d1 JB |
1034 | return; |
1035 | } | |
1036 | ||
549f7365 CW |
1037 | static void notify_ring(struct drm_device *dev, |
1038 | struct intel_ring_buffer *ring) | |
1039 | { | |
475553de CW |
1040 | if (ring->obj == NULL) |
1041 | return; | |
1042 | ||
814e9b57 | 1043 | trace_i915_gem_request_complete(ring); |
9862e600 | 1044 | |
549f7365 | 1045 | wake_up_all(&ring->irq_queue); |
10cd45b6 | 1046 | i915_queue_hangcheck(dev); |
549f7365 CW |
1047 | } |
1048 | ||
76c3552f | 1049 | void gen6_set_pm_mask(struct drm_i915_private *dev_priv, |
27544369 D |
1050 | u32 pm_iir, int new_delay) |
1051 | { | |
1052 | if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { | |
1053 | if (new_delay >= dev_priv->rps.max_delay) { | |
1054 | /* Mask UP THRESHOLD Interrupts */ | |
1055 | I915_WRITE(GEN6_PMINTRMSK, | |
1056 | I915_READ(GEN6_PMINTRMSK) | | |
1057 | GEN6_PM_RP_UP_THRESHOLD); | |
1058 | dev_priv->rps.rp_up_masked = true; | |
1059 | } | |
1060 | if (dev_priv->rps.rp_down_masked) { | |
1061 | /* UnMask DOWN THRESHOLD Interrupts */ | |
1062 | I915_WRITE(GEN6_PMINTRMSK, | |
1063 | I915_READ(GEN6_PMINTRMSK) & | |
1064 | ~GEN6_PM_RP_DOWN_THRESHOLD); | |
1065 | dev_priv->rps.rp_down_masked = false; | |
1066 | } | |
1067 | } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { | |
1068 | if (new_delay <= dev_priv->rps.min_delay) { | |
1069 | /* Mask DOWN THRESHOLD Interrupts */ | |
1070 | I915_WRITE(GEN6_PMINTRMSK, | |
1071 | I915_READ(GEN6_PMINTRMSK) | | |
1072 | GEN6_PM_RP_DOWN_THRESHOLD); | |
1073 | dev_priv->rps.rp_down_masked = true; | |
1074 | } | |
1075 | ||
1076 | if (dev_priv->rps.rp_up_masked) { | |
1077 | /* UnMask UP THRESHOLD Interrupts */ | |
1078 | I915_WRITE(GEN6_PMINTRMSK, | |
1079 | I915_READ(GEN6_PMINTRMSK) & | |
1080 | ~GEN6_PM_RP_UP_THRESHOLD); | |
1081 | dev_priv->rps.rp_up_masked = false; | |
1082 | } | |
1083 | } | |
1084 | } | |
1085 | ||
4912d041 | 1086 | static void gen6_pm_rps_work(struct work_struct *work) |
3b8d8d91 | 1087 | { |
4912d041 | 1088 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
c6a828d3 | 1089 | rps.work); |
edbfdb45 | 1090 | u32 pm_iir; |
dd75fdc8 | 1091 | int new_delay, adj; |
4912d041 | 1092 | |
59cdb63d | 1093 | spin_lock_irq(&dev_priv->irq_lock); |
c6a828d3 DV |
1094 | pm_iir = dev_priv->rps.pm_iir; |
1095 | dev_priv->rps.pm_iir = 0; | |
4848405c | 1096 | /* Make sure not to corrupt PMIMR state used by ringbuffer code */ |
edbfdb45 | 1097 | snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS); |
59cdb63d | 1098 | spin_unlock_irq(&dev_priv->irq_lock); |
3b8d8d91 | 1099 | |
60611c13 PZ |
1100 | /* Make sure we didn't queue anything we're not going to process. */ |
1101 | WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS); | |
1102 | ||
4848405c | 1103 | if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0) |
3b8d8d91 JB |
1104 | return; |
1105 | ||
4fc688ce | 1106 | mutex_lock(&dev_priv->rps.hw_lock); |
7b9e0ae6 | 1107 | |
dd75fdc8 | 1108 | adj = dev_priv->rps.last_adj; |
7425034a | 1109 | if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { |
dd75fdc8 CW |
1110 | if (adj > 0) |
1111 | adj *= 2; | |
1112 | else | |
1113 | adj = 1; | |
1114 | new_delay = dev_priv->rps.cur_delay + adj; | |
7425034a VS |
1115 | |
1116 | /* | |
1117 | * For better performance, jump directly | |
1118 | * to RPe if we're below it. | |
1119 | */ | |
dd75fdc8 CW |
1120 | if (new_delay < dev_priv->rps.rpe_delay) |
1121 | new_delay = dev_priv->rps.rpe_delay; | |
1122 | } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { | |
1123 | if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay) | |
7425034a | 1124 | new_delay = dev_priv->rps.rpe_delay; |
dd75fdc8 CW |
1125 | else |
1126 | new_delay = dev_priv->rps.min_delay; | |
1127 | adj = 0; | |
1128 | } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { | |
1129 | if (adj < 0) | |
1130 | adj *= 2; | |
1131 | else | |
1132 | adj = -1; | |
1133 | new_delay = dev_priv->rps.cur_delay + adj; | |
1134 | } else { /* unknown event */ | |
1135 | new_delay = dev_priv->rps.cur_delay; | |
1136 | } | |
3b8d8d91 | 1137 | |
79249636 BW |
1138 | /* sysfs frequency interfaces may have snuck in while servicing the |
1139 | * interrupt | |
1140 | */ | |
1272e7b8 VS |
1141 | new_delay = clamp_t(int, new_delay, |
1142 | dev_priv->rps.min_delay, dev_priv->rps.max_delay); | |
27544369 D |
1143 | |
1144 | gen6_set_pm_mask(dev_priv, pm_iir, new_delay); | |
dd75fdc8 CW |
1145 | dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay; |
1146 | ||
1147 | if (IS_VALLEYVIEW(dev_priv->dev)) | |
1148 | valleyview_set_rps(dev_priv->dev, new_delay); | |
1149 | else | |
1150 | gen6_set_rps(dev_priv->dev, new_delay); | |
3b8d8d91 | 1151 | |
4fc688ce | 1152 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 JB |
1153 | } |
1154 | ||
e3689190 BW |
1155 | |
1156 | /** | |
1157 | * ivybridge_parity_work - Workqueue called when a parity error interrupt | |
1158 | * occurred. | |
1159 | * @work: workqueue struct | |
1160 | * | |
1161 | * Doesn't actually do anything except notify userspace. As a consequence of | |
1162 | * this event, userspace should try to remap the bad rows since statistically | |
1163 | * it is likely the same row is more likely to go bad again. | |
1164 | */ | |
1165 | static void ivybridge_parity_work(struct work_struct *work) | |
1166 | { | |
1167 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
a4da4fa4 | 1168 | l3_parity.error_work); |
e3689190 | 1169 | u32 error_status, row, bank, subbank; |
35a85ac6 | 1170 | char *parity_event[6]; |
e3689190 BW |
1171 | uint32_t misccpctl; |
1172 | unsigned long flags; | |
35a85ac6 | 1173 | uint8_t slice = 0; |
e3689190 BW |
1174 | |
1175 | /* We must turn off DOP level clock gating to access the L3 registers. | |
1176 | * In order to prevent a get/put style interface, acquire struct mutex | |
1177 | * any time we access those registers. | |
1178 | */ | |
1179 | mutex_lock(&dev_priv->dev->struct_mutex); | |
1180 | ||
35a85ac6 BW |
1181 | /* If we've screwed up tracking, just let the interrupt fire again */ |
1182 | if (WARN_ON(!dev_priv->l3_parity.which_slice)) | |
1183 | goto out; | |
1184 | ||
e3689190 BW |
1185 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
1186 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
1187 | POSTING_READ(GEN7_MISCCPCTL); | |
1188 | ||
35a85ac6 BW |
1189 | while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { |
1190 | u32 reg; | |
e3689190 | 1191 | |
35a85ac6 BW |
1192 | slice--; |
1193 | if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev))) | |
1194 | break; | |
e3689190 | 1195 | |
35a85ac6 | 1196 | dev_priv->l3_parity.which_slice &= ~(1<<slice); |
e3689190 | 1197 | |
35a85ac6 | 1198 | reg = GEN7_L3CDERRST1 + (slice * 0x200); |
e3689190 | 1199 | |
35a85ac6 BW |
1200 | error_status = I915_READ(reg); |
1201 | row = GEN7_PARITY_ERROR_ROW(error_status); | |
1202 | bank = GEN7_PARITY_ERROR_BANK(error_status); | |
1203 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); | |
1204 | ||
1205 | I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); | |
1206 | POSTING_READ(reg); | |
1207 | ||
1208 | parity_event[0] = I915_L3_PARITY_UEVENT "=1"; | |
1209 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); | |
1210 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); | |
1211 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); | |
1212 | parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); | |
1213 | parity_event[5] = NULL; | |
1214 | ||
5bdebb18 | 1215 | kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj, |
35a85ac6 | 1216 | KOBJ_CHANGE, parity_event); |
e3689190 | 1217 | |
35a85ac6 BW |
1218 | DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", |
1219 | slice, row, bank, subbank); | |
e3689190 | 1220 | |
35a85ac6 BW |
1221 | kfree(parity_event[4]); |
1222 | kfree(parity_event[3]); | |
1223 | kfree(parity_event[2]); | |
1224 | kfree(parity_event[1]); | |
1225 | } | |
e3689190 | 1226 | |
35a85ac6 | 1227 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
e3689190 | 1228 | |
35a85ac6 BW |
1229 | out: |
1230 | WARN_ON(dev_priv->l3_parity.which_slice); | |
1231 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1232 | ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev)); | |
1233 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1234 | ||
1235 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
e3689190 BW |
1236 | } |
1237 | ||
35a85ac6 | 1238 | static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir) |
e3689190 BW |
1239 | { |
1240 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e3689190 | 1241 | |
040d2baa | 1242 | if (!HAS_L3_DPF(dev)) |
e3689190 BW |
1243 | return; |
1244 | ||
d0ecd7e2 | 1245 | spin_lock(&dev_priv->irq_lock); |
35a85ac6 | 1246 | ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev)); |
d0ecd7e2 | 1247 | spin_unlock(&dev_priv->irq_lock); |
e3689190 | 1248 | |
35a85ac6 BW |
1249 | iir &= GT_PARITY_ERROR(dev); |
1250 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) | |
1251 | dev_priv->l3_parity.which_slice |= 1 << 1; | |
1252 | ||
1253 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) | |
1254 | dev_priv->l3_parity.which_slice |= 1 << 0; | |
1255 | ||
a4da4fa4 | 1256 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
e3689190 BW |
1257 | } |
1258 | ||
f1af8fc1 PZ |
1259 | static void ilk_gt_irq_handler(struct drm_device *dev, |
1260 | struct drm_i915_private *dev_priv, | |
1261 | u32 gt_iir) | |
1262 | { | |
1263 | if (gt_iir & | |
1264 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
1265 | notify_ring(dev, &dev_priv->ring[RCS]); | |
1266 | if (gt_iir & ILK_BSD_USER_INTERRUPT) | |
1267 | notify_ring(dev, &dev_priv->ring[VCS]); | |
1268 | } | |
1269 | ||
e7b4c6b1 DV |
1270 | static void snb_gt_irq_handler(struct drm_device *dev, |
1271 | struct drm_i915_private *dev_priv, | |
1272 | u32 gt_iir) | |
1273 | { | |
1274 | ||
cc609d5d BW |
1275 | if (gt_iir & |
1276 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
e7b4c6b1 | 1277 | notify_ring(dev, &dev_priv->ring[RCS]); |
cc609d5d | 1278 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
e7b4c6b1 | 1279 | notify_ring(dev, &dev_priv->ring[VCS]); |
cc609d5d | 1280 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
e7b4c6b1 DV |
1281 | notify_ring(dev, &dev_priv->ring[BCS]); |
1282 | ||
cc609d5d BW |
1283 | if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | |
1284 | GT_BSD_CS_ERROR_INTERRUPT | | |
1285 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) { | |
e7b4c6b1 DV |
1286 | DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir); |
1287 | i915_handle_error(dev, false); | |
1288 | } | |
e3689190 | 1289 | |
35a85ac6 BW |
1290 | if (gt_iir & GT_PARITY_ERROR(dev)) |
1291 | ivybridge_parity_error_irq_handler(dev, gt_iir); | |
e7b4c6b1 DV |
1292 | } |
1293 | ||
abd58f01 BW |
1294 | static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev, |
1295 | struct drm_i915_private *dev_priv, | |
1296 | u32 master_ctl) | |
1297 | { | |
1298 | u32 rcs, bcs, vcs; | |
1299 | uint32_t tmp = 0; | |
1300 | irqreturn_t ret = IRQ_NONE; | |
1301 | ||
1302 | if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { | |
1303 | tmp = I915_READ(GEN8_GT_IIR(0)); | |
1304 | if (tmp) { | |
1305 | ret = IRQ_HANDLED; | |
1306 | rcs = tmp >> GEN8_RCS_IRQ_SHIFT; | |
1307 | bcs = tmp >> GEN8_BCS_IRQ_SHIFT; | |
1308 | if (rcs & GT_RENDER_USER_INTERRUPT) | |
1309 | notify_ring(dev, &dev_priv->ring[RCS]); | |
1310 | if (bcs & GT_RENDER_USER_INTERRUPT) | |
1311 | notify_ring(dev, &dev_priv->ring[BCS]); | |
1312 | I915_WRITE(GEN8_GT_IIR(0), tmp); | |
1313 | } else | |
1314 | DRM_ERROR("The master control interrupt lied (GT0)!\n"); | |
1315 | } | |
1316 | ||
1317 | if (master_ctl & GEN8_GT_VCS1_IRQ) { | |
1318 | tmp = I915_READ(GEN8_GT_IIR(1)); | |
1319 | if (tmp) { | |
1320 | ret = IRQ_HANDLED; | |
1321 | vcs = tmp >> GEN8_VCS1_IRQ_SHIFT; | |
1322 | if (vcs & GT_RENDER_USER_INTERRUPT) | |
1323 | notify_ring(dev, &dev_priv->ring[VCS]); | |
1324 | I915_WRITE(GEN8_GT_IIR(1), tmp); | |
1325 | } else | |
1326 | DRM_ERROR("The master control interrupt lied (GT1)!\n"); | |
1327 | } | |
1328 | ||
1329 | if (master_ctl & GEN8_GT_VECS_IRQ) { | |
1330 | tmp = I915_READ(GEN8_GT_IIR(3)); | |
1331 | if (tmp) { | |
1332 | ret = IRQ_HANDLED; | |
1333 | vcs = tmp >> GEN8_VECS_IRQ_SHIFT; | |
1334 | if (vcs & GT_RENDER_USER_INTERRUPT) | |
1335 | notify_ring(dev, &dev_priv->ring[VECS]); | |
1336 | I915_WRITE(GEN8_GT_IIR(3), tmp); | |
1337 | } else | |
1338 | DRM_ERROR("The master control interrupt lied (GT3)!\n"); | |
1339 | } | |
1340 | ||
1341 | return ret; | |
1342 | } | |
1343 | ||
b543fb04 EE |
1344 | #define HPD_STORM_DETECT_PERIOD 1000 |
1345 | #define HPD_STORM_THRESHOLD 5 | |
1346 | ||
10a504de | 1347 | static inline void intel_hpd_irq_handler(struct drm_device *dev, |
22062dba DV |
1348 | u32 hotplug_trigger, |
1349 | const u32 *hpd) | |
b543fb04 EE |
1350 | { |
1351 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b543fb04 | 1352 | int i; |
10a504de | 1353 | bool storm_detected = false; |
b543fb04 | 1354 | |
91d131d2 DV |
1355 | if (!hotplug_trigger) |
1356 | return; | |
1357 | ||
cc9bd499 ID |
1358 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
1359 | hotplug_trigger); | |
1360 | ||
b5ea2d56 | 1361 | spin_lock(&dev_priv->irq_lock); |
b543fb04 | 1362 | for (i = 1; i < HPD_NUM_PINS; i++) { |
821450c6 | 1363 | |
3432087e | 1364 | WARN_ONCE(hpd[i] & hotplug_trigger && |
8b5565b8 | 1365 | dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED, |
cba1c073 CW |
1366 | "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n", |
1367 | hotplug_trigger, i, hpd[i]); | |
b8f102e8 | 1368 | |
b543fb04 EE |
1369 | if (!(hpd[i] & hotplug_trigger) || |
1370 | dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED) | |
1371 | continue; | |
1372 | ||
bc5ead8c | 1373 | dev_priv->hpd_event_bits |= (1 << i); |
b543fb04 EE |
1374 | if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies, |
1375 | dev_priv->hpd_stats[i].hpd_last_jiffies | |
1376 | + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) { | |
1377 | dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies; | |
1378 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
b8f102e8 | 1379 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i); |
b543fb04 EE |
1380 | } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) { |
1381 | dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED; | |
142e2398 | 1382 | dev_priv->hpd_event_bits &= ~(1 << i); |
b543fb04 | 1383 | DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i); |
10a504de | 1384 | storm_detected = true; |
b543fb04 EE |
1385 | } else { |
1386 | dev_priv->hpd_stats[i].hpd_cnt++; | |
b8f102e8 EE |
1387 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i, |
1388 | dev_priv->hpd_stats[i].hpd_cnt); | |
b543fb04 EE |
1389 | } |
1390 | } | |
1391 | ||
10a504de DV |
1392 | if (storm_detected) |
1393 | dev_priv->display.hpd_irq_setup(dev); | |
b5ea2d56 | 1394 | spin_unlock(&dev_priv->irq_lock); |
5876fa0d | 1395 | |
645416f5 DV |
1396 | /* |
1397 | * Our hotplug handler can grab modeset locks (by calling down into the | |
1398 | * fb helpers). Hence it must not be run on our own dev-priv->wq work | |
1399 | * queue for otherwise the flush_work in the pageflip code will | |
1400 | * deadlock. | |
1401 | */ | |
1402 | schedule_work(&dev_priv->hotplug_work); | |
b543fb04 EE |
1403 | } |
1404 | ||
515ac2bb DV |
1405 | static void gmbus_irq_handler(struct drm_device *dev) |
1406 | { | |
28c70f16 DV |
1407 | struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private; |
1408 | ||
28c70f16 | 1409 | wake_up_all(&dev_priv->gmbus_wait_queue); |
515ac2bb DV |
1410 | } |
1411 | ||
ce99c256 DV |
1412 | static void dp_aux_irq_handler(struct drm_device *dev) |
1413 | { | |
9ee32fea DV |
1414 | struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private; |
1415 | ||
9ee32fea | 1416 | wake_up_all(&dev_priv->gmbus_wait_queue); |
ce99c256 DV |
1417 | } |
1418 | ||
8bf1e9f1 | 1419 | #if defined(CONFIG_DEBUG_FS) |
277de95e DV |
1420 | static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, |
1421 | uint32_t crc0, uint32_t crc1, | |
1422 | uint32_t crc2, uint32_t crc3, | |
1423 | uint32_t crc4) | |
8bf1e9f1 SH |
1424 | { |
1425 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1426 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; | |
1427 | struct intel_pipe_crc_entry *entry; | |
ac2300d4 | 1428 | int head, tail; |
b2c88f5b | 1429 | |
d538bbdf DL |
1430 | spin_lock(&pipe_crc->lock); |
1431 | ||
0c912c79 | 1432 | if (!pipe_crc->entries) { |
d538bbdf | 1433 | spin_unlock(&pipe_crc->lock); |
0c912c79 DL |
1434 | DRM_ERROR("spurious interrupt\n"); |
1435 | return; | |
1436 | } | |
1437 | ||
d538bbdf DL |
1438 | head = pipe_crc->head; |
1439 | tail = pipe_crc->tail; | |
b2c88f5b DL |
1440 | |
1441 | if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { | |
d538bbdf | 1442 | spin_unlock(&pipe_crc->lock); |
b2c88f5b DL |
1443 | DRM_ERROR("CRC buffer overflowing\n"); |
1444 | return; | |
1445 | } | |
1446 | ||
1447 | entry = &pipe_crc->entries[head]; | |
8bf1e9f1 | 1448 | |
8bc5e955 | 1449 | entry->frame = dev->driver->get_vblank_counter(dev, pipe); |
eba94eb9 DV |
1450 | entry->crc[0] = crc0; |
1451 | entry->crc[1] = crc1; | |
1452 | entry->crc[2] = crc2; | |
1453 | entry->crc[3] = crc3; | |
1454 | entry->crc[4] = crc4; | |
b2c88f5b DL |
1455 | |
1456 | head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
d538bbdf DL |
1457 | pipe_crc->head = head; |
1458 | ||
1459 | spin_unlock(&pipe_crc->lock); | |
07144428 DL |
1460 | |
1461 | wake_up_interruptible(&pipe_crc->wq); | |
8bf1e9f1 | 1462 | } |
277de95e DV |
1463 | #else |
1464 | static inline void | |
1465 | display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, | |
1466 | uint32_t crc0, uint32_t crc1, | |
1467 | uint32_t crc2, uint32_t crc3, | |
1468 | uint32_t crc4) {} | |
1469 | #endif | |
1470 | ||
eba94eb9 | 1471 | |
277de95e | 1472 | static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5a69b89f DV |
1473 | { |
1474 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1475 | ||
277de95e DV |
1476 | display_pipe_crc_irq_handler(dev, pipe, |
1477 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1478 | 0, 0, 0, 0); | |
5a69b89f DV |
1479 | } |
1480 | ||
277de95e | 1481 | static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
eba94eb9 DV |
1482 | { |
1483 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1484 | ||
277de95e DV |
1485 | display_pipe_crc_irq_handler(dev, pipe, |
1486 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1487 | I915_READ(PIPE_CRC_RES_2_IVB(pipe)), | |
1488 | I915_READ(PIPE_CRC_RES_3_IVB(pipe)), | |
1489 | I915_READ(PIPE_CRC_RES_4_IVB(pipe)), | |
1490 | I915_READ(PIPE_CRC_RES_5_IVB(pipe))); | |
eba94eb9 | 1491 | } |
5b3a856b | 1492 | |
277de95e | 1493 | static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5b3a856b DV |
1494 | { |
1495 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0b5c5ed0 DV |
1496 | uint32_t res1, res2; |
1497 | ||
1498 | if (INTEL_INFO(dev)->gen >= 3) | |
1499 | res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); | |
1500 | else | |
1501 | res1 = 0; | |
1502 | ||
1503 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
1504 | res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); | |
1505 | else | |
1506 | res2 = 0; | |
5b3a856b | 1507 | |
277de95e DV |
1508 | display_pipe_crc_irq_handler(dev, pipe, |
1509 | I915_READ(PIPE_CRC_RES_RED(pipe)), | |
1510 | I915_READ(PIPE_CRC_RES_GREEN(pipe)), | |
1511 | I915_READ(PIPE_CRC_RES_BLUE(pipe)), | |
1512 | res1, res2); | |
5b3a856b | 1513 | } |
8bf1e9f1 | 1514 | |
1403c0d4 PZ |
1515 | /* The RPS events need forcewake, so we add them to a work queue and mask their |
1516 | * IMR bits until the work is done. Other interrupts can be processed without | |
1517 | * the work queue. */ | |
1518 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) | |
baf02a1f | 1519 | { |
41a05a3a | 1520 | if (pm_iir & GEN6_PM_RPS_EVENTS) { |
59cdb63d | 1521 | spin_lock(&dev_priv->irq_lock); |
41a05a3a | 1522 | dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS; |
4d3b3d5f | 1523 | snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS); |
59cdb63d | 1524 | spin_unlock(&dev_priv->irq_lock); |
2adbee62 DV |
1525 | |
1526 | queue_work(dev_priv->wq, &dev_priv->rps.work); | |
baf02a1f | 1527 | } |
baf02a1f | 1528 | |
1403c0d4 PZ |
1529 | if (HAS_VEBOX(dev_priv->dev)) { |
1530 | if (pm_iir & PM_VEBOX_USER_INTERRUPT) | |
1531 | notify_ring(dev_priv->dev, &dev_priv->ring[VECS]); | |
12638c57 | 1532 | |
1403c0d4 PZ |
1533 | if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) { |
1534 | DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir); | |
1535 | i915_handle_error(dev_priv->dev, false); | |
1536 | } | |
12638c57 | 1537 | } |
baf02a1f BW |
1538 | } |
1539 | ||
c1874ed7 ID |
1540 | static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir) |
1541 | { | |
1542 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1543 | u32 pipe_stats[I915_MAX_PIPES]; | |
c1874ed7 ID |
1544 | int pipe; |
1545 | ||
58ead0d7 | 1546 | spin_lock(&dev_priv->irq_lock); |
c1874ed7 ID |
1547 | for_each_pipe(pipe) { |
1548 | int reg = PIPESTAT(pipe); | |
1549 | pipe_stats[pipe] = I915_READ(reg); | |
1550 | ||
1551 | /* | |
1552 | * Clear the PIPE*STAT regs before the IIR | |
1553 | */ | |
1554 | if (pipe_stats[pipe] & 0x8000ffff) | |
1555 | I915_WRITE(reg, pipe_stats[pipe]); | |
1556 | } | |
58ead0d7 | 1557 | spin_unlock(&dev_priv->irq_lock); |
c1874ed7 ID |
1558 | |
1559 | for_each_pipe(pipe) { | |
1560 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) | |
1561 | drm_handle_vblank(dev, pipe); | |
1562 | ||
579a9b0e | 1563 | if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) { |
c1874ed7 ID |
1564 | intel_prepare_page_flip(dev, pipe); |
1565 | intel_finish_page_flip(dev, pipe); | |
1566 | } | |
1567 | ||
1568 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
1569 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
1570 | ||
1571 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && | |
1572 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
1573 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); | |
1574 | } | |
1575 | ||
1576 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) | |
1577 | gmbus_irq_handler(dev); | |
1578 | } | |
1579 | ||
ff1f525e | 1580 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
7e231dbe JB |
1581 | { |
1582 | struct drm_device *dev = (struct drm_device *) arg; | |
1583 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1584 | u32 iir, gt_iir, pm_iir; | |
1585 | irqreturn_t ret = IRQ_NONE; | |
7e231dbe | 1586 | |
7e231dbe JB |
1587 | while (true) { |
1588 | iir = I915_READ(VLV_IIR); | |
1589 | gt_iir = I915_READ(GTIIR); | |
1590 | pm_iir = I915_READ(GEN6_PMIIR); | |
1591 | ||
1592 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) | |
1593 | goto out; | |
1594 | ||
1595 | ret = IRQ_HANDLED; | |
1596 | ||
e7b4c6b1 | 1597 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
7e231dbe | 1598 | |
c1874ed7 | 1599 | valleyview_pipestat_irq_handler(dev, iir); |
31acc7f5 | 1600 | |
7e231dbe JB |
1601 | /* Consume port. Then clear IIR or we'll miss events */ |
1602 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { | |
1603 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
b543fb04 | 1604 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; |
7e231dbe | 1605 | |
91d131d2 DV |
1606 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); |
1607 | ||
4aeebd74 DV |
1608 | if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) |
1609 | dp_aux_irq_handler(dev); | |
1610 | ||
7e231dbe JB |
1611 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
1612 | I915_READ(PORT_HOTPLUG_STAT); | |
1613 | } | |
1614 | ||
7e231dbe | 1615 | |
60611c13 | 1616 | if (pm_iir) |
d0ecd7e2 | 1617 | gen6_rps_irq_handler(dev_priv, pm_iir); |
7e231dbe JB |
1618 | |
1619 | I915_WRITE(GTIIR, gt_iir); | |
1620 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
1621 | I915_WRITE(VLV_IIR, iir); | |
1622 | } | |
1623 | ||
1624 | out: | |
1625 | return ret; | |
1626 | } | |
1627 | ||
23e81d69 | 1628 | static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) |
776ad806 JB |
1629 | { |
1630 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 1631 | int pipe; |
b543fb04 | 1632 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; |
776ad806 | 1633 | |
91d131d2 DV |
1634 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx); |
1635 | ||
cfc33bf7 VS |
1636 | if (pch_iir & SDE_AUDIO_POWER_MASK) { |
1637 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> | |
1638 | SDE_AUDIO_POWER_SHIFT); | |
776ad806 | 1639 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
cfc33bf7 VS |
1640 | port_name(port)); |
1641 | } | |
776ad806 | 1642 | |
ce99c256 DV |
1643 | if (pch_iir & SDE_AUX_MASK) |
1644 | dp_aux_irq_handler(dev); | |
1645 | ||
776ad806 | 1646 | if (pch_iir & SDE_GMBUS) |
515ac2bb | 1647 | gmbus_irq_handler(dev); |
776ad806 JB |
1648 | |
1649 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
1650 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
1651 | ||
1652 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
1653 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
1654 | ||
1655 | if (pch_iir & SDE_POISON) | |
1656 | DRM_ERROR("PCH poison interrupt\n"); | |
1657 | ||
9db4a9c7 JB |
1658 | if (pch_iir & SDE_FDI_MASK) |
1659 | for_each_pipe(pipe) | |
1660 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", | |
1661 | pipe_name(pipe), | |
1662 | I915_READ(FDI_RX_IIR(pipe))); | |
776ad806 JB |
1663 | |
1664 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
1665 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
1666 | ||
1667 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
1668 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
1669 | ||
776ad806 | 1670 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
8664281b PZ |
1671 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, |
1672 | false)) | |
fc2c807b | 1673 | DRM_ERROR("PCH transcoder A FIFO underrun\n"); |
8664281b PZ |
1674 | |
1675 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
1676 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, | |
1677 | false)) | |
fc2c807b | 1678 | DRM_ERROR("PCH transcoder B FIFO underrun\n"); |
8664281b PZ |
1679 | } |
1680 | ||
1681 | static void ivb_err_int_handler(struct drm_device *dev) | |
1682 | { | |
1683 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1684 | u32 err_int = I915_READ(GEN7_ERR_INT); | |
5a69b89f | 1685 | enum pipe pipe; |
8664281b | 1686 | |
de032bf4 PZ |
1687 | if (err_int & ERR_INT_POISON) |
1688 | DRM_ERROR("Poison interrupt\n"); | |
1689 | ||
5a69b89f DV |
1690 | for_each_pipe(pipe) { |
1691 | if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) { | |
1692 | if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, | |
1693 | false)) | |
fc2c807b VS |
1694 | DRM_ERROR("Pipe %c FIFO underrun\n", |
1695 | pipe_name(pipe)); | |
5a69b89f | 1696 | } |
8bf1e9f1 | 1697 | |
5a69b89f DV |
1698 | if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { |
1699 | if (IS_IVYBRIDGE(dev)) | |
277de95e | 1700 | ivb_pipe_crc_irq_handler(dev, pipe); |
5a69b89f | 1701 | else |
277de95e | 1702 | hsw_pipe_crc_irq_handler(dev, pipe); |
5a69b89f DV |
1703 | } |
1704 | } | |
8bf1e9f1 | 1705 | |
8664281b PZ |
1706 | I915_WRITE(GEN7_ERR_INT, err_int); |
1707 | } | |
1708 | ||
1709 | static void cpt_serr_int_handler(struct drm_device *dev) | |
1710 | { | |
1711 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1712 | u32 serr_int = I915_READ(SERR_INT); | |
1713 | ||
de032bf4 PZ |
1714 | if (serr_int & SERR_INT_POISON) |
1715 | DRM_ERROR("PCH poison interrupt\n"); | |
1716 | ||
8664281b PZ |
1717 | if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) |
1718 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, | |
1719 | false)) | |
fc2c807b | 1720 | DRM_ERROR("PCH transcoder A FIFO underrun\n"); |
8664281b PZ |
1721 | |
1722 | if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) | |
1723 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, | |
1724 | false)) | |
fc2c807b | 1725 | DRM_ERROR("PCH transcoder B FIFO underrun\n"); |
8664281b PZ |
1726 | |
1727 | if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) | |
1728 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C, | |
1729 | false)) | |
fc2c807b | 1730 | DRM_ERROR("PCH transcoder C FIFO underrun\n"); |
8664281b PZ |
1731 | |
1732 | I915_WRITE(SERR_INT, serr_int); | |
776ad806 JB |
1733 | } |
1734 | ||
23e81d69 AJ |
1735 | static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) |
1736 | { | |
1737 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1738 | int pipe; | |
b543fb04 | 1739 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; |
23e81d69 | 1740 | |
91d131d2 DV |
1741 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt); |
1742 | ||
cfc33bf7 VS |
1743 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { |
1744 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> | |
1745 | SDE_AUDIO_POWER_SHIFT_CPT); | |
1746 | DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", | |
1747 | port_name(port)); | |
1748 | } | |
23e81d69 AJ |
1749 | |
1750 | if (pch_iir & SDE_AUX_MASK_CPT) | |
ce99c256 | 1751 | dp_aux_irq_handler(dev); |
23e81d69 AJ |
1752 | |
1753 | if (pch_iir & SDE_GMBUS_CPT) | |
515ac2bb | 1754 | gmbus_irq_handler(dev); |
23e81d69 AJ |
1755 | |
1756 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) | |
1757 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); | |
1758 | ||
1759 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) | |
1760 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); | |
1761 | ||
1762 | if (pch_iir & SDE_FDI_MASK_CPT) | |
1763 | for_each_pipe(pipe) | |
1764 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", | |
1765 | pipe_name(pipe), | |
1766 | I915_READ(FDI_RX_IIR(pipe))); | |
8664281b PZ |
1767 | |
1768 | if (pch_iir & SDE_ERROR_CPT) | |
1769 | cpt_serr_int_handler(dev); | |
23e81d69 AJ |
1770 | } |
1771 | ||
c008bc6e PZ |
1772 | static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) |
1773 | { | |
1774 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40da17c2 | 1775 | enum pipe pipe; |
c008bc6e PZ |
1776 | |
1777 | if (de_iir & DE_AUX_CHANNEL_A) | |
1778 | dp_aux_irq_handler(dev); | |
1779 | ||
1780 | if (de_iir & DE_GSE) | |
1781 | intel_opregion_asle_intr(dev); | |
1782 | ||
c008bc6e PZ |
1783 | if (de_iir & DE_POISON) |
1784 | DRM_ERROR("Poison interrupt\n"); | |
1785 | ||
40da17c2 DV |
1786 | for_each_pipe(pipe) { |
1787 | if (de_iir & DE_PIPE_VBLANK(pipe)) | |
1788 | drm_handle_vblank(dev, pipe); | |
5b3a856b | 1789 | |
40da17c2 DV |
1790 | if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) |
1791 | if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
fc2c807b VS |
1792 | DRM_ERROR("Pipe %c FIFO underrun\n", |
1793 | pipe_name(pipe)); | |
5b3a856b | 1794 | |
40da17c2 DV |
1795 | if (de_iir & DE_PIPE_CRC_DONE(pipe)) |
1796 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
c008bc6e | 1797 | |
40da17c2 DV |
1798 | /* plane/pipes map 1:1 on ilk+ */ |
1799 | if (de_iir & DE_PLANE_FLIP_DONE(pipe)) { | |
1800 | intel_prepare_page_flip(dev, pipe); | |
1801 | intel_finish_page_flip_plane(dev, pipe); | |
1802 | } | |
c008bc6e PZ |
1803 | } |
1804 | ||
1805 | /* check event from PCH */ | |
1806 | if (de_iir & DE_PCH_EVENT) { | |
1807 | u32 pch_iir = I915_READ(SDEIIR); | |
1808 | ||
1809 | if (HAS_PCH_CPT(dev)) | |
1810 | cpt_irq_handler(dev, pch_iir); | |
1811 | else | |
1812 | ibx_irq_handler(dev, pch_iir); | |
1813 | ||
1814 | /* should clear PCH hotplug event before clear CPU irq */ | |
1815 | I915_WRITE(SDEIIR, pch_iir); | |
1816 | } | |
1817 | ||
1818 | if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) | |
1819 | ironlake_rps_change_irq_handler(dev); | |
1820 | } | |
1821 | ||
9719fb98 PZ |
1822 | static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir) |
1823 | { | |
1824 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3b6c42e8 | 1825 | enum pipe i; |
9719fb98 PZ |
1826 | |
1827 | if (de_iir & DE_ERR_INT_IVB) | |
1828 | ivb_err_int_handler(dev); | |
1829 | ||
1830 | if (de_iir & DE_AUX_CHANNEL_A_IVB) | |
1831 | dp_aux_irq_handler(dev); | |
1832 | ||
1833 | if (de_iir & DE_GSE_IVB) | |
1834 | intel_opregion_asle_intr(dev); | |
1835 | ||
3b6c42e8 | 1836 | for_each_pipe(i) { |
40da17c2 | 1837 | if (de_iir & (DE_PIPE_VBLANK_IVB(i))) |
9719fb98 | 1838 | drm_handle_vblank(dev, i); |
40da17c2 DV |
1839 | |
1840 | /* plane/pipes map 1:1 on ilk+ */ | |
1841 | if (de_iir & DE_PLANE_FLIP_DONE_IVB(i)) { | |
9719fb98 PZ |
1842 | intel_prepare_page_flip(dev, i); |
1843 | intel_finish_page_flip_plane(dev, i); | |
1844 | } | |
1845 | } | |
1846 | ||
1847 | /* check event from PCH */ | |
1848 | if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) { | |
1849 | u32 pch_iir = I915_READ(SDEIIR); | |
1850 | ||
1851 | cpt_irq_handler(dev, pch_iir); | |
1852 | ||
1853 | /* clear PCH hotplug event before clear CPU irq */ | |
1854 | I915_WRITE(SDEIIR, pch_iir); | |
1855 | } | |
1856 | } | |
1857 | ||
f1af8fc1 | 1858 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
b1f14ad0 JB |
1859 | { |
1860 | struct drm_device *dev = (struct drm_device *) arg; | |
1861 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
f1af8fc1 | 1862 | u32 de_iir, gt_iir, de_ier, sde_ier = 0; |
0e43406b | 1863 | irqreturn_t ret = IRQ_NONE; |
b1f14ad0 | 1864 | |
8664281b PZ |
1865 | /* We get interrupts on unclaimed registers, so check for this before we |
1866 | * do any I915_{READ,WRITE}. */ | |
907b28c5 | 1867 | intel_uncore_check_errors(dev); |
8664281b | 1868 | |
b1f14ad0 JB |
1869 | /* disable master interrupt before clearing iir */ |
1870 | de_ier = I915_READ(DEIER); | |
1871 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
23a78516 | 1872 | POSTING_READ(DEIER); |
b1f14ad0 | 1873 | |
44498aea PZ |
1874 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
1875 | * interrupts will will be stored on its back queue, and then we'll be | |
1876 | * able to process them after we restore SDEIER (as soon as we restore | |
1877 | * it, we'll get an interrupt if SDEIIR still has something to process | |
1878 | * due to its back queue). */ | |
ab5c608b BW |
1879 | if (!HAS_PCH_NOP(dev)) { |
1880 | sde_ier = I915_READ(SDEIER); | |
1881 | I915_WRITE(SDEIER, 0); | |
1882 | POSTING_READ(SDEIER); | |
1883 | } | |
44498aea | 1884 | |
b1f14ad0 | 1885 | gt_iir = I915_READ(GTIIR); |
0e43406b | 1886 | if (gt_iir) { |
d8fc8a47 | 1887 | if (INTEL_INFO(dev)->gen >= 6) |
f1af8fc1 | 1888 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
d8fc8a47 PZ |
1889 | else |
1890 | ilk_gt_irq_handler(dev, dev_priv, gt_iir); | |
0e43406b CW |
1891 | I915_WRITE(GTIIR, gt_iir); |
1892 | ret = IRQ_HANDLED; | |
b1f14ad0 JB |
1893 | } |
1894 | ||
0e43406b CW |
1895 | de_iir = I915_READ(DEIIR); |
1896 | if (de_iir) { | |
f1af8fc1 PZ |
1897 | if (INTEL_INFO(dev)->gen >= 7) |
1898 | ivb_display_irq_handler(dev, de_iir); | |
1899 | else | |
1900 | ilk_display_irq_handler(dev, de_iir); | |
0e43406b CW |
1901 | I915_WRITE(DEIIR, de_iir); |
1902 | ret = IRQ_HANDLED; | |
b1f14ad0 JB |
1903 | } |
1904 | ||
f1af8fc1 PZ |
1905 | if (INTEL_INFO(dev)->gen >= 6) { |
1906 | u32 pm_iir = I915_READ(GEN6_PMIIR); | |
1907 | if (pm_iir) { | |
1403c0d4 | 1908 | gen6_rps_irq_handler(dev_priv, pm_iir); |
f1af8fc1 PZ |
1909 | I915_WRITE(GEN6_PMIIR, pm_iir); |
1910 | ret = IRQ_HANDLED; | |
1911 | } | |
0e43406b | 1912 | } |
b1f14ad0 | 1913 | |
b1f14ad0 JB |
1914 | I915_WRITE(DEIER, de_ier); |
1915 | POSTING_READ(DEIER); | |
ab5c608b BW |
1916 | if (!HAS_PCH_NOP(dev)) { |
1917 | I915_WRITE(SDEIER, sde_ier); | |
1918 | POSTING_READ(SDEIER); | |
1919 | } | |
b1f14ad0 JB |
1920 | |
1921 | return ret; | |
1922 | } | |
1923 | ||
abd58f01 BW |
1924 | static irqreturn_t gen8_irq_handler(int irq, void *arg) |
1925 | { | |
1926 | struct drm_device *dev = arg; | |
1927 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1928 | u32 master_ctl; | |
1929 | irqreturn_t ret = IRQ_NONE; | |
1930 | uint32_t tmp = 0; | |
c42664cc | 1931 | enum pipe pipe; |
abd58f01 | 1932 | |
abd58f01 BW |
1933 | master_ctl = I915_READ(GEN8_MASTER_IRQ); |
1934 | master_ctl &= ~GEN8_MASTER_IRQ_CONTROL; | |
1935 | if (!master_ctl) | |
1936 | return IRQ_NONE; | |
1937 | ||
1938 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
1939 | POSTING_READ(GEN8_MASTER_IRQ); | |
1940 | ||
1941 | ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl); | |
1942 | ||
1943 | if (master_ctl & GEN8_DE_MISC_IRQ) { | |
1944 | tmp = I915_READ(GEN8_DE_MISC_IIR); | |
1945 | if (tmp & GEN8_DE_MISC_GSE) | |
1946 | intel_opregion_asle_intr(dev); | |
1947 | else if (tmp) | |
1948 | DRM_ERROR("Unexpected DE Misc interrupt\n"); | |
1949 | else | |
1950 | DRM_ERROR("The master control interrupt lied (DE MISC)!\n"); | |
1951 | ||
1952 | if (tmp) { | |
1953 | I915_WRITE(GEN8_DE_MISC_IIR, tmp); | |
1954 | ret = IRQ_HANDLED; | |
1955 | } | |
1956 | } | |
1957 | ||
6d766f02 DV |
1958 | if (master_ctl & GEN8_DE_PORT_IRQ) { |
1959 | tmp = I915_READ(GEN8_DE_PORT_IIR); | |
1960 | if (tmp & GEN8_AUX_CHANNEL_A) | |
1961 | dp_aux_irq_handler(dev); | |
1962 | else if (tmp) | |
1963 | DRM_ERROR("Unexpected DE Port interrupt\n"); | |
1964 | else | |
1965 | DRM_ERROR("The master control interrupt lied (DE PORT)!\n"); | |
1966 | ||
1967 | if (tmp) { | |
1968 | I915_WRITE(GEN8_DE_PORT_IIR, tmp); | |
1969 | ret = IRQ_HANDLED; | |
1970 | } | |
1971 | } | |
1972 | ||
c42664cc DV |
1973 | for_each_pipe(pipe) { |
1974 | uint32_t pipe_iir; | |
abd58f01 | 1975 | |
c42664cc DV |
1976 | if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) |
1977 | continue; | |
abd58f01 | 1978 | |
c42664cc DV |
1979 | pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); |
1980 | if (pipe_iir & GEN8_PIPE_VBLANK) | |
1981 | drm_handle_vblank(dev, pipe); | |
abd58f01 | 1982 | |
c42664cc DV |
1983 | if (pipe_iir & GEN8_PIPE_FLIP_DONE) { |
1984 | intel_prepare_page_flip(dev, pipe); | |
1985 | intel_finish_page_flip_plane(dev, pipe); | |
abd58f01 | 1986 | } |
c42664cc | 1987 | |
0fbe7870 DV |
1988 | if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE) |
1989 | hsw_pipe_crc_irq_handler(dev, pipe); | |
1990 | ||
38d83c96 DV |
1991 | if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) { |
1992 | if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, | |
1993 | false)) | |
fc2c807b VS |
1994 | DRM_ERROR("Pipe %c FIFO underrun\n", |
1995 | pipe_name(pipe)); | |
38d83c96 DV |
1996 | } |
1997 | ||
30100f2b DV |
1998 | if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) { |
1999 | DRM_ERROR("Fault errors on pipe %c\n: 0x%08x", | |
2000 | pipe_name(pipe), | |
2001 | pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS); | |
2002 | } | |
c42664cc DV |
2003 | |
2004 | if (pipe_iir) { | |
2005 | ret = IRQ_HANDLED; | |
2006 | I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir); | |
2007 | } else | |
abd58f01 BW |
2008 | DRM_ERROR("The master control interrupt lied (DE PIPE)!\n"); |
2009 | } | |
2010 | ||
92d03a80 DV |
2011 | if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) { |
2012 | /* | |
2013 | * FIXME(BDW): Assume for now that the new interrupt handling | |
2014 | * scheme also closed the SDE interrupt handling race we've seen | |
2015 | * on older pch-split platforms. But this needs testing. | |
2016 | */ | |
2017 | u32 pch_iir = I915_READ(SDEIIR); | |
2018 | ||
2019 | cpt_irq_handler(dev, pch_iir); | |
2020 | ||
2021 | if (pch_iir) { | |
2022 | I915_WRITE(SDEIIR, pch_iir); | |
2023 | ret = IRQ_HANDLED; | |
2024 | } | |
2025 | } | |
2026 | ||
abd58f01 BW |
2027 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
2028 | POSTING_READ(GEN8_MASTER_IRQ); | |
2029 | ||
2030 | return ret; | |
2031 | } | |
2032 | ||
17e1df07 DV |
2033 | static void i915_error_wake_up(struct drm_i915_private *dev_priv, |
2034 | bool reset_completed) | |
2035 | { | |
2036 | struct intel_ring_buffer *ring; | |
2037 | int i; | |
2038 | ||
2039 | /* | |
2040 | * Notify all waiters for GPU completion events that reset state has | |
2041 | * been changed, and that they need to restart their wait after | |
2042 | * checking for potential errors (and bail out to drop locks if there is | |
2043 | * a gpu reset pending so that i915_error_work_func can acquire them). | |
2044 | */ | |
2045 | ||
2046 | /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */ | |
2047 | for_each_ring(ring, dev_priv, i) | |
2048 | wake_up_all(&ring->irq_queue); | |
2049 | ||
2050 | /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */ | |
2051 | wake_up_all(&dev_priv->pending_flip_queue); | |
2052 | ||
2053 | /* | |
2054 | * Signal tasks blocked in i915_gem_wait_for_error that the pending | |
2055 | * reset state is cleared. | |
2056 | */ | |
2057 | if (reset_completed) | |
2058 | wake_up_all(&dev_priv->gpu_error.reset_queue); | |
2059 | } | |
2060 | ||
8a905236 JB |
2061 | /** |
2062 | * i915_error_work_func - do process context error handling work | |
2063 | * @work: work struct | |
2064 | * | |
2065 | * Fire an error uevent so userspace can see that a hang or error | |
2066 | * was detected. | |
2067 | */ | |
2068 | static void i915_error_work_func(struct work_struct *work) | |
2069 | { | |
1f83fee0 DV |
2070 | struct i915_gpu_error *error = container_of(work, struct i915_gpu_error, |
2071 | work); | |
2072 | drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t, | |
2073 | gpu_error); | |
8a905236 | 2074 | struct drm_device *dev = dev_priv->dev; |
cce723ed BW |
2075 | char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; |
2076 | char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; | |
2077 | char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; | |
17e1df07 | 2078 | int ret; |
8a905236 | 2079 | |
5bdebb18 | 2080 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event); |
f316a42c | 2081 | |
7db0ba24 DV |
2082 | /* |
2083 | * Note that there's only one work item which does gpu resets, so we | |
2084 | * need not worry about concurrent gpu resets potentially incrementing | |
2085 | * error->reset_counter twice. We only need to take care of another | |
2086 | * racing irq/hangcheck declaring the gpu dead for a second time. A | |
2087 | * quick check for that is good enough: schedule_work ensures the | |
2088 | * correct ordering between hang detection and this work item, and since | |
2089 | * the reset in-progress bit is only ever set by code outside of this | |
2090 | * work we don't need to worry about any other races. | |
2091 | */ | |
2092 | if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) { | |
f803aa55 | 2093 | DRM_DEBUG_DRIVER("resetting chip\n"); |
5bdebb18 | 2094 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, |
7db0ba24 | 2095 | reset_event); |
1f83fee0 | 2096 | |
17e1df07 DV |
2097 | /* |
2098 | * All state reset _must_ be completed before we update the | |
2099 | * reset counter, for otherwise waiters might miss the reset | |
2100 | * pending state and not properly drop locks, resulting in | |
2101 | * deadlocks with the reset work. | |
2102 | */ | |
f69061be DV |
2103 | ret = i915_reset(dev); |
2104 | ||
17e1df07 DV |
2105 | intel_display_handle_reset(dev); |
2106 | ||
f69061be DV |
2107 | if (ret == 0) { |
2108 | /* | |
2109 | * After all the gem state is reset, increment the reset | |
2110 | * counter and wake up everyone waiting for the reset to | |
2111 | * complete. | |
2112 | * | |
2113 | * Since unlock operations are a one-sided barrier only, | |
2114 | * we need to insert a barrier here to order any seqno | |
2115 | * updates before | |
2116 | * the counter increment. | |
2117 | */ | |
2118 | smp_mb__before_atomic_inc(); | |
2119 | atomic_inc(&dev_priv->gpu_error.reset_counter); | |
2120 | ||
5bdebb18 | 2121 | kobject_uevent_env(&dev->primary->kdev->kobj, |
f69061be | 2122 | KOBJ_CHANGE, reset_done_event); |
1f83fee0 | 2123 | } else { |
2ac0f450 | 2124 | atomic_set_mask(I915_WEDGED, &error->reset_counter); |
f316a42c | 2125 | } |
1f83fee0 | 2126 | |
17e1df07 DV |
2127 | /* |
2128 | * Note: The wake_up also serves as a memory barrier so that | |
2129 | * waiters see the update value of the reset counter atomic_t. | |
2130 | */ | |
2131 | i915_error_wake_up(dev_priv, true); | |
f316a42c | 2132 | } |
8a905236 JB |
2133 | } |
2134 | ||
35aed2e6 | 2135 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
2136 | { |
2137 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bd9854f9 | 2138 | uint32_t instdone[I915_NUM_INSTDONE_REG]; |
8a905236 | 2139 | u32 eir = I915_READ(EIR); |
050ee91f | 2140 | int pipe, i; |
8a905236 | 2141 | |
35aed2e6 CW |
2142 | if (!eir) |
2143 | return; | |
8a905236 | 2144 | |
a70491cc | 2145 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
8a905236 | 2146 | |
bd9854f9 BW |
2147 | i915_get_extra_instdone(dev, instdone); |
2148 | ||
8a905236 JB |
2149 | if (IS_G4X(dev)) { |
2150 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
2151 | u32 ipeir = I915_READ(IPEIR_I965); | |
2152 | ||
a70491cc JP |
2153 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2154 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
050ee91f BW |
2155 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2156 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a70491cc | 2157 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2158 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2159 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2160 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2161 | } |
2162 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
2163 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2164 | pr_err("page table error\n"); |
2165 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2166 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2167 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2168 | } |
2169 | } | |
2170 | ||
a6c45cf0 | 2171 | if (!IS_GEN2(dev)) { |
8a905236 JB |
2172 | if (eir & I915_ERROR_PAGE_TABLE) { |
2173 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2174 | pr_err("page table error\n"); |
2175 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2176 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2177 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2178 | } |
2179 | } | |
2180 | ||
2181 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
a70491cc | 2182 | pr_err("memory refresh error:\n"); |
9db4a9c7 | 2183 | for_each_pipe(pipe) |
a70491cc | 2184 | pr_err("pipe %c stat: 0x%08x\n", |
9db4a9c7 | 2185 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
8a905236 JB |
2186 | /* pipestat has already been acked */ |
2187 | } | |
2188 | if (eir & I915_ERROR_INSTRUCTION) { | |
a70491cc JP |
2189 | pr_err("instruction error\n"); |
2190 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); | |
050ee91f BW |
2191 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2192 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a6c45cf0 | 2193 | if (INTEL_INFO(dev)->gen < 4) { |
8a905236 JB |
2194 | u32 ipeir = I915_READ(IPEIR); |
2195 | ||
a70491cc JP |
2196 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
2197 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); | |
a70491cc | 2198 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); |
8a905236 | 2199 | I915_WRITE(IPEIR, ipeir); |
3143a2bf | 2200 | POSTING_READ(IPEIR); |
8a905236 JB |
2201 | } else { |
2202 | u32 ipeir = I915_READ(IPEIR_I965); | |
2203 | ||
a70491cc JP |
2204 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2205 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
a70491cc | 2206 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2207 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2208 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2209 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2210 | } |
2211 | } | |
2212 | ||
2213 | I915_WRITE(EIR, eir); | |
3143a2bf | 2214 | POSTING_READ(EIR); |
8a905236 JB |
2215 | eir = I915_READ(EIR); |
2216 | if (eir) { | |
2217 | /* | |
2218 | * some errors might have become stuck, | |
2219 | * mask them. | |
2220 | */ | |
2221 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
2222 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
2223 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2224 | } | |
35aed2e6 CW |
2225 | } |
2226 | ||
2227 | /** | |
2228 | * i915_handle_error - handle an error interrupt | |
2229 | * @dev: drm device | |
2230 | * | |
2231 | * Do some basic checking of regsiter state at error interrupt time and | |
2232 | * dump it to the syslog. Also call i915_capture_error_state() to make | |
2233 | * sure we get a record and make it available in debugfs. Fire a uevent | |
2234 | * so userspace knows something bad happened (should trigger collection | |
2235 | * of a ring dump etc.). | |
2236 | */ | |
527f9e90 | 2237 | void i915_handle_error(struct drm_device *dev, bool wedged) |
35aed2e6 CW |
2238 | { |
2239 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2240 | ||
2241 | i915_capture_error_state(dev); | |
2242 | i915_report_and_clear_eir(dev); | |
8a905236 | 2243 | |
ba1234d1 | 2244 | if (wedged) { |
f69061be DV |
2245 | atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG, |
2246 | &dev_priv->gpu_error.reset_counter); | |
ba1234d1 | 2247 | |
11ed50ec | 2248 | /* |
17e1df07 DV |
2249 | * Wakeup waiting processes so that the reset work function |
2250 | * i915_error_work_func doesn't deadlock trying to grab various | |
2251 | * locks. By bumping the reset counter first, the woken | |
2252 | * processes will see a reset in progress and back off, | |
2253 | * releasing their locks and then wait for the reset completion. | |
2254 | * We must do this for _all_ gpu waiters that might hold locks | |
2255 | * that the reset work needs to acquire. | |
2256 | * | |
2257 | * Note: The wake_up serves as the required memory barrier to | |
2258 | * ensure that the waiters see the updated value of the reset | |
2259 | * counter atomic_t. | |
11ed50ec | 2260 | */ |
17e1df07 | 2261 | i915_error_wake_up(dev_priv, false); |
11ed50ec BG |
2262 | } |
2263 | ||
122f46ba DV |
2264 | /* |
2265 | * Our reset work can grab modeset locks (since it needs to reset the | |
2266 | * state of outstanding pagelips). Hence it must not be run on our own | |
2267 | * dev-priv->wq work queue for otherwise the flush_work in the pageflip | |
2268 | * code will deadlock. | |
2269 | */ | |
2270 | schedule_work(&dev_priv->gpu_error.work); | |
8a905236 JB |
2271 | } |
2272 | ||
21ad8330 | 2273 | static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe) |
4e5359cd SF |
2274 | { |
2275 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2276 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
2277 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 2278 | struct drm_i915_gem_object *obj; |
4e5359cd SF |
2279 | struct intel_unpin_work *work; |
2280 | unsigned long flags; | |
2281 | bool stall_detected; | |
2282 | ||
2283 | /* Ignore early vblank irqs */ | |
2284 | if (intel_crtc == NULL) | |
2285 | return; | |
2286 | ||
2287 | spin_lock_irqsave(&dev->event_lock, flags); | |
2288 | work = intel_crtc->unpin_work; | |
2289 | ||
e7d841ca CW |
2290 | if (work == NULL || |
2291 | atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE || | |
2292 | !work->enable_stall_check) { | |
4e5359cd SF |
2293 | /* Either the pending flip IRQ arrived, or we're too early. Don't check */ |
2294 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2295 | return; | |
2296 | } | |
2297 | ||
2298 | /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ | |
05394f39 | 2299 | obj = work->pending_flip_obj; |
a6c45cf0 | 2300 | if (INTEL_INFO(dev)->gen >= 4) { |
9db4a9c7 | 2301 | int dspsurf = DSPSURF(intel_crtc->plane); |
446f2545 | 2302 | stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) == |
f343c5f6 | 2303 | i915_gem_obj_ggtt_offset(obj); |
4e5359cd | 2304 | } else { |
9db4a9c7 | 2305 | int dspaddr = DSPADDR(intel_crtc->plane); |
f343c5f6 | 2306 | stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) + |
01f2c773 | 2307 | crtc->y * crtc->fb->pitches[0] + |
4e5359cd SF |
2308 | crtc->x * crtc->fb->bits_per_pixel/8); |
2309 | } | |
2310 | ||
2311 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2312 | ||
2313 | if (stall_detected) { | |
2314 | DRM_DEBUG_DRIVER("Pageflip stall detected\n"); | |
2315 | intel_prepare_page_flip(dev, intel_crtc->plane); | |
2316 | } | |
2317 | } | |
2318 | ||
42f52ef8 KP |
2319 | /* Called from drm generic code, passed 'crtc' which |
2320 | * we use as a pipe index | |
2321 | */ | |
f71d4af4 | 2322 | static int i915_enable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 JB |
2323 | { |
2324 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 2325 | unsigned long irqflags; |
71e0ffa5 | 2326 | |
5eddb70b | 2327 | if (!i915_pipe_enabled(dev, pipe)) |
71e0ffa5 | 2328 | return -EINVAL; |
0a3e67a4 | 2329 | |
1ec14ad3 | 2330 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2331 | if (INTEL_INFO(dev)->gen >= 4) |
7c463586 | 2332 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2333 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
e9d21d7f | 2334 | else |
7c463586 | 2335 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2336 | PIPE_VBLANK_INTERRUPT_STATUS); |
8692d00e CW |
2337 | |
2338 | /* maintain vblank delivery even in deep C-states */ | |
3d13ef2e | 2339 | if (INTEL_INFO(dev)->gen == 3) |
6b26c86d | 2340 | I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS)); |
1ec14ad3 | 2341 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
8692d00e | 2342 | |
0a3e67a4 JB |
2343 | return 0; |
2344 | } | |
2345 | ||
f71d4af4 | 2346 | static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
f796cf8f JB |
2347 | { |
2348 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2349 | unsigned long irqflags; | |
b518421f | 2350 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2351 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2352 | |
2353 | if (!i915_pipe_enabled(dev, pipe)) | |
2354 | return -EINVAL; | |
2355 | ||
2356 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 2357 | ironlake_enable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2358 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2359 | ||
2360 | return 0; | |
2361 | } | |
2362 | ||
7e231dbe JB |
2363 | static int valleyview_enable_vblank(struct drm_device *dev, int pipe) |
2364 | { | |
2365 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2366 | unsigned long irqflags; | |
7e231dbe JB |
2367 | |
2368 | if (!i915_pipe_enabled(dev, pipe)) | |
2369 | return -EINVAL; | |
2370 | ||
2371 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 | 2372 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2373 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2374 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2375 | ||
2376 | return 0; | |
2377 | } | |
2378 | ||
abd58f01 BW |
2379 | static int gen8_enable_vblank(struct drm_device *dev, int pipe) |
2380 | { | |
2381 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2382 | unsigned long irqflags; | |
abd58f01 BW |
2383 | |
2384 | if (!i915_pipe_enabled(dev, pipe)) | |
2385 | return -EINVAL; | |
2386 | ||
2387 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
7167d7c6 DV |
2388 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK; |
2389 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2390 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2391 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2392 | return 0; | |
2393 | } | |
2394 | ||
42f52ef8 KP |
2395 | /* Called from drm generic code, passed 'crtc' which |
2396 | * we use as a pipe index | |
2397 | */ | |
f71d4af4 | 2398 | static void i915_disable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 JB |
2399 | { |
2400 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 2401 | unsigned long irqflags; |
0a3e67a4 | 2402 | |
1ec14ad3 | 2403 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
3d13ef2e | 2404 | if (INTEL_INFO(dev)->gen == 3) |
6b26c86d | 2405 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS)); |
8692d00e | 2406 | |
f796cf8f | 2407 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 ID |
2408 | PIPE_VBLANK_INTERRUPT_STATUS | |
2409 | PIPE_START_VBLANK_INTERRUPT_STATUS); | |
f796cf8f JB |
2410 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2411 | } | |
2412 | ||
f71d4af4 | 2413 | static void ironlake_disable_vblank(struct drm_device *dev, int pipe) |
f796cf8f JB |
2414 | { |
2415 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2416 | unsigned long irqflags; | |
b518421f | 2417 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2418 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2419 | |
2420 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 2421 | ironlake_disable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2422 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2423 | } | |
2424 | ||
7e231dbe JB |
2425 | static void valleyview_disable_vblank(struct drm_device *dev, int pipe) |
2426 | { | |
2427 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2428 | unsigned long irqflags; | |
7e231dbe JB |
2429 | |
2430 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 | 2431 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 | 2432 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2433 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2434 | } | |
2435 | ||
abd58f01 BW |
2436 | static void gen8_disable_vblank(struct drm_device *dev, int pipe) |
2437 | { | |
2438 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2439 | unsigned long irqflags; | |
abd58f01 BW |
2440 | |
2441 | if (!i915_pipe_enabled(dev, pipe)) | |
2442 | return; | |
2443 | ||
2444 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
7167d7c6 DV |
2445 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK; |
2446 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2447 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2448 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2449 | } | |
2450 | ||
893eead0 CW |
2451 | static u32 |
2452 | ring_last_seqno(struct intel_ring_buffer *ring) | |
852835f3 | 2453 | { |
893eead0 CW |
2454 | return list_entry(ring->request_list.prev, |
2455 | struct drm_i915_gem_request, list)->seqno; | |
2456 | } | |
2457 | ||
9107e9d2 CW |
2458 | static bool |
2459 | ring_idle(struct intel_ring_buffer *ring, u32 seqno) | |
2460 | { | |
2461 | return (list_empty(&ring->request_list) || | |
2462 | i915_seqno_passed(seqno, ring_last_seqno(ring))); | |
f65d9421 BG |
2463 | } |
2464 | ||
6274f212 CW |
2465 | static struct intel_ring_buffer * |
2466 | semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno) | |
a24a11e6 CW |
2467 | { |
2468 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
6274f212 | 2469 | u32 cmd, ipehr, acthd, acthd_min; |
a24a11e6 CW |
2470 | |
2471 | ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); | |
2472 | if ((ipehr & ~(0x3 << 16)) != | |
2473 | (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER)) | |
6274f212 | 2474 | return NULL; |
a24a11e6 CW |
2475 | |
2476 | /* ACTHD is likely pointing to the dword after the actual command, | |
2477 | * so scan backwards until we find the MBOX. | |
2478 | */ | |
6274f212 | 2479 | acthd = intel_ring_get_active_head(ring) & HEAD_ADDR; |
a24a11e6 CW |
2480 | acthd_min = max((int)acthd - 3 * 4, 0); |
2481 | do { | |
2482 | cmd = ioread32(ring->virtual_start + acthd); | |
2483 | if (cmd == ipehr) | |
2484 | break; | |
2485 | ||
2486 | acthd -= 4; | |
2487 | if (acthd < acthd_min) | |
6274f212 | 2488 | return NULL; |
a24a11e6 CW |
2489 | } while (1); |
2490 | ||
6274f212 CW |
2491 | *seqno = ioread32(ring->virtual_start+acthd+4)+1; |
2492 | return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3]; | |
a24a11e6 CW |
2493 | } |
2494 | ||
6274f212 CW |
2495 | static int semaphore_passed(struct intel_ring_buffer *ring) |
2496 | { | |
2497 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
2498 | struct intel_ring_buffer *signaller; | |
2499 | u32 seqno, ctl; | |
2500 | ||
2501 | ring->hangcheck.deadlock = true; | |
2502 | ||
2503 | signaller = semaphore_waits_for(ring, &seqno); | |
2504 | if (signaller == NULL || signaller->hangcheck.deadlock) | |
2505 | return -1; | |
2506 | ||
2507 | /* cursory check for an unkickable deadlock */ | |
2508 | ctl = I915_READ_CTL(signaller); | |
2509 | if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0) | |
2510 | return -1; | |
2511 | ||
2512 | return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno); | |
2513 | } | |
2514 | ||
2515 | static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) | |
2516 | { | |
2517 | struct intel_ring_buffer *ring; | |
2518 | int i; | |
2519 | ||
2520 | for_each_ring(ring, dev_priv, i) | |
2521 | ring->hangcheck.deadlock = false; | |
2522 | } | |
2523 | ||
ad8beaea MK |
2524 | static enum intel_ring_hangcheck_action |
2525 | ring_stuck(struct intel_ring_buffer *ring, u32 acthd) | |
1ec14ad3 CW |
2526 | { |
2527 | struct drm_device *dev = ring->dev; | |
2528 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9107e9d2 CW |
2529 | u32 tmp; |
2530 | ||
6274f212 | 2531 | if (ring->hangcheck.acthd != acthd) |
f2f4d82f | 2532 | return HANGCHECK_ACTIVE; |
6274f212 | 2533 | |
9107e9d2 | 2534 | if (IS_GEN2(dev)) |
f2f4d82f | 2535 | return HANGCHECK_HUNG; |
9107e9d2 CW |
2536 | |
2537 | /* Is the chip hanging on a WAIT_FOR_EVENT? | |
2538 | * If so we can simply poke the RB_WAIT bit | |
2539 | * and break the hang. This should work on | |
2540 | * all but the second generation chipsets. | |
2541 | */ | |
2542 | tmp = I915_READ_CTL(ring); | |
1ec14ad3 CW |
2543 | if (tmp & RING_WAIT) { |
2544 | DRM_ERROR("Kicking stuck wait on %s\n", | |
2545 | ring->name); | |
09e14bf3 | 2546 | i915_handle_error(dev, false); |
1ec14ad3 | 2547 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2548 | return HANGCHECK_KICK; |
6274f212 CW |
2549 | } |
2550 | ||
2551 | if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { | |
2552 | switch (semaphore_passed(ring)) { | |
2553 | default: | |
f2f4d82f | 2554 | return HANGCHECK_HUNG; |
6274f212 CW |
2555 | case 1: |
2556 | DRM_ERROR("Kicking stuck semaphore on %s\n", | |
2557 | ring->name); | |
09e14bf3 | 2558 | i915_handle_error(dev, false); |
6274f212 | 2559 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2560 | return HANGCHECK_KICK; |
6274f212 | 2561 | case 0: |
f2f4d82f | 2562 | return HANGCHECK_WAIT; |
6274f212 | 2563 | } |
9107e9d2 | 2564 | } |
ed5cbb03 | 2565 | |
f2f4d82f | 2566 | return HANGCHECK_HUNG; |
ed5cbb03 MK |
2567 | } |
2568 | ||
f65d9421 BG |
2569 | /** |
2570 | * This is called when the chip hasn't reported back with completed | |
05407ff8 MK |
2571 | * batchbuffers in a long time. We keep track per ring seqno progress and |
2572 | * if there are no progress, hangcheck score for that ring is increased. | |
2573 | * Further, acthd is inspected to see if the ring is stuck. On stuck case | |
2574 | * we kick the ring. If we see no progress on three subsequent calls | |
2575 | * we assume chip is wedged and try to fix it by resetting the chip. | |
f65d9421 | 2576 | */ |
a658b5d2 | 2577 | static void i915_hangcheck_elapsed(unsigned long data) |
f65d9421 BG |
2578 | { |
2579 | struct drm_device *dev = (struct drm_device *)data; | |
2580 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2581 | struct intel_ring_buffer *ring; |
b4519513 | 2582 | int i; |
05407ff8 | 2583 | int busy_count = 0, rings_hung = 0; |
9107e9d2 CW |
2584 | bool stuck[I915_NUM_RINGS] = { 0 }; |
2585 | #define BUSY 1 | |
2586 | #define KICK 5 | |
2587 | #define HUNG 20 | |
893eead0 | 2588 | |
d330a953 | 2589 | if (!i915.enable_hangcheck) |
3e0dc6b0 BW |
2590 | return; |
2591 | ||
b4519513 | 2592 | for_each_ring(ring, dev_priv, i) { |
05407ff8 | 2593 | u32 seqno, acthd; |
9107e9d2 | 2594 | bool busy = true; |
05407ff8 | 2595 | |
6274f212 CW |
2596 | semaphore_clear_deadlocks(dev_priv); |
2597 | ||
05407ff8 MK |
2598 | seqno = ring->get_seqno(ring, false); |
2599 | acthd = intel_ring_get_active_head(ring); | |
b4519513 | 2600 | |
9107e9d2 CW |
2601 | if (ring->hangcheck.seqno == seqno) { |
2602 | if (ring_idle(ring, seqno)) { | |
da661464 MK |
2603 | ring->hangcheck.action = HANGCHECK_IDLE; |
2604 | ||
9107e9d2 CW |
2605 | if (waitqueue_active(&ring->irq_queue)) { |
2606 | /* Issue a wake-up to catch stuck h/w. */ | |
094f9a54 | 2607 | if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) { |
f4adcd24 DV |
2608 | if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring))) |
2609 | DRM_ERROR("Hangcheck timer elapsed... %s idle\n", | |
2610 | ring->name); | |
2611 | else | |
2612 | DRM_INFO("Fake missed irq on %s\n", | |
2613 | ring->name); | |
094f9a54 CW |
2614 | wake_up_all(&ring->irq_queue); |
2615 | } | |
2616 | /* Safeguard against driver failure */ | |
2617 | ring->hangcheck.score += BUSY; | |
9107e9d2 CW |
2618 | } else |
2619 | busy = false; | |
05407ff8 | 2620 | } else { |
6274f212 CW |
2621 | /* We always increment the hangcheck score |
2622 | * if the ring is busy and still processing | |
2623 | * the same request, so that no single request | |
2624 | * can run indefinitely (such as a chain of | |
2625 | * batches). The only time we do not increment | |
2626 | * the hangcheck score on this ring, if this | |
2627 | * ring is in a legitimate wait for another | |
2628 | * ring. In that case the waiting ring is a | |
2629 | * victim and we want to be sure we catch the | |
2630 | * right culprit. Then every time we do kick | |
2631 | * the ring, add a small increment to the | |
2632 | * score so that we can catch a batch that is | |
2633 | * being repeatedly kicked and so responsible | |
2634 | * for stalling the machine. | |
2635 | */ | |
ad8beaea MK |
2636 | ring->hangcheck.action = ring_stuck(ring, |
2637 | acthd); | |
2638 | ||
2639 | switch (ring->hangcheck.action) { | |
da661464 | 2640 | case HANGCHECK_IDLE: |
f2f4d82f | 2641 | case HANGCHECK_WAIT: |
6274f212 | 2642 | break; |
f2f4d82f | 2643 | case HANGCHECK_ACTIVE: |
ea04cb31 | 2644 | ring->hangcheck.score += BUSY; |
6274f212 | 2645 | break; |
f2f4d82f | 2646 | case HANGCHECK_KICK: |
ea04cb31 | 2647 | ring->hangcheck.score += KICK; |
6274f212 | 2648 | break; |
f2f4d82f | 2649 | case HANGCHECK_HUNG: |
ea04cb31 | 2650 | ring->hangcheck.score += HUNG; |
6274f212 CW |
2651 | stuck[i] = true; |
2652 | break; | |
2653 | } | |
05407ff8 | 2654 | } |
9107e9d2 | 2655 | } else { |
da661464 MK |
2656 | ring->hangcheck.action = HANGCHECK_ACTIVE; |
2657 | ||
9107e9d2 CW |
2658 | /* Gradually reduce the count so that we catch DoS |
2659 | * attempts across multiple batches. | |
2660 | */ | |
2661 | if (ring->hangcheck.score > 0) | |
2662 | ring->hangcheck.score--; | |
d1e61e7f CW |
2663 | } |
2664 | ||
05407ff8 MK |
2665 | ring->hangcheck.seqno = seqno; |
2666 | ring->hangcheck.acthd = acthd; | |
9107e9d2 | 2667 | busy_count += busy; |
893eead0 | 2668 | } |
b9201c14 | 2669 | |
92cab734 | 2670 | for_each_ring(ring, dev_priv, i) { |
b6b0fac0 | 2671 | if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) { |
b8d88d1d DV |
2672 | DRM_INFO("%s on %s\n", |
2673 | stuck[i] ? "stuck" : "no progress", | |
2674 | ring->name); | |
a43adf07 | 2675 | rings_hung++; |
92cab734 MK |
2676 | } |
2677 | } | |
2678 | ||
05407ff8 MK |
2679 | if (rings_hung) |
2680 | return i915_handle_error(dev, true); | |
f65d9421 | 2681 | |
05407ff8 MK |
2682 | if (busy_count) |
2683 | /* Reset timer case chip hangs without another request | |
2684 | * being added */ | |
10cd45b6 MK |
2685 | i915_queue_hangcheck(dev); |
2686 | } | |
2687 | ||
2688 | void i915_queue_hangcheck(struct drm_device *dev) | |
2689 | { | |
2690 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d330a953 | 2691 | if (!i915.enable_hangcheck) |
10cd45b6 MK |
2692 | return; |
2693 | ||
2694 | mod_timer(&dev_priv->gpu_error.hangcheck_timer, | |
2695 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); | |
f65d9421 BG |
2696 | } |
2697 | ||
91738a95 PZ |
2698 | static void ibx_irq_preinstall(struct drm_device *dev) |
2699 | { | |
2700 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2701 | ||
2702 | if (HAS_PCH_NOP(dev)) | |
2703 | return; | |
2704 | ||
2705 | /* south display irq */ | |
2706 | I915_WRITE(SDEIMR, 0xffffffff); | |
2707 | /* | |
2708 | * SDEIER is also touched by the interrupt handler to work around missed | |
2709 | * PCH interrupts. Hence we can't update it after the interrupt handler | |
2710 | * is enabled - instead we unconditionally enable all PCH interrupt | |
2711 | * sources here, but then only unmask them as needed with SDEIMR. | |
2712 | */ | |
2713 | I915_WRITE(SDEIER, 0xffffffff); | |
2714 | POSTING_READ(SDEIER); | |
2715 | } | |
2716 | ||
d18ea1b5 DV |
2717 | static void gen5_gt_irq_preinstall(struct drm_device *dev) |
2718 | { | |
2719 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2720 | ||
2721 | /* and GT */ | |
2722 | I915_WRITE(GTIMR, 0xffffffff); | |
2723 | I915_WRITE(GTIER, 0x0); | |
2724 | POSTING_READ(GTIER); | |
2725 | ||
2726 | if (INTEL_INFO(dev)->gen >= 6) { | |
2727 | /* and PM */ | |
2728 | I915_WRITE(GEN6_PMIMR, 0xffffffff); | |
2729 | I915_WRITE(GEN6_PMIER, 0x0); | |
2730 | POSTING_READ(GEN6_PMIER); | |
2731 | } | |
2732 | } | |
2733 | ||
1da177e4 LT |
2734 | /* drm_dma.h hooks |
2735 | */ | |
f71d4af4 | 2736 | static void ironlake_irq_preinstall(struct drm_device *dev) |
036a4a7d ZW |
2737 | { |
2738 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2739 | ||
2740 | I915_WRITE(HWSTAM, 0xeffe); | |
bdfcdb63 | 2741 | |
036a4a7d ZW |
2742 | I915_WRITE(DEIMR, 0xffffffff); |
2743 | I915_WRITE(DEIER, 0x0); | |
3143a2bf | 2744 | POSTING_READ(DEIER); |
036a4a7d | 2745 | |
d18ea1b5 | 2746 | gen5_gt_irq_preinstall(dev); |
c650156a | 2747 | |
91738a95 | 2748 | ibx_irq_preinstall(dev); |
7d99163d BW |
2749 | } |
2750 | ||
7e231dbe JB |
2751 | static void valleyview_irq_preinstall(struct drm_device *dev) |
2752 | { | |
2753 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2754 | int pipe; | |
2755 | ||
7e231dbe JB |
2756 | /* VLV magic */ |
2757 | I915_WRITE(VLV_IMR, 0); | |
2758 | I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); | |
2759 | I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); | |
2760 | I915_WRITE(RING_IMR(BLT_RING_BASE), 0); | |
2761 | ||
7e231dbe JB |
2762 | /* and GT */ |
2763 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
2764 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
d18ea1b5 DV |
2765 | |
2766 | gen5_gt_irq_preinstall(dev); | |
7e231dbe JB |
2767 | |
2768 | I915_WRITE(DPINVGTT, 0xff); | |
2769 | ||
2770 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
2771 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
2772 | for_each_pipe(pipe) | |
2773 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
2774 | I915_WRITE(VLV_IIR, 0xffffffff); | |
2775 | I915_WRITE(VLV_IMR, 0xffffffff); | |
2776 | I915_WRITE(VLV_IER, 0x0); | |
2777 | POSTING_READ(VLV_IER); | |
2778 | } | |
2779 | ||
abd58f01 BW |
2780 | static void gen8_irq_preinstall(struct drm_device *dev) |
2781 | { | |
2782 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2783 | int pipe; | |
2784 | ||
abd58f01 BW |
2785 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
2786 | POSTING_READ(GEN8_MASTER_IRQ); | |
2787 | ||
2788 | /* IIR can theoretically queue up two events. Be paranoid */ | |
2789 | #define GEN8_IRQ_INIT_NDX(type, which) do { \ | |
2790 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ | |
2791 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
2792 | I915_WRITE(GEN8_##type##_IER(which), 0); \ | |
2793 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
2794 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
2795 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
2796 | } while (0) | |
2797 | ||
2798 | #define GEN8_IRQ_INIT(type) do { \ | |
2799 | I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \ | |
2800 | POSTING_READ(GEN8_##type##_IMR); \ | |
2801 | I915_WRITE(GEN8_##type##_IER, 0); \ | |
2802 | I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ | |
2803 | POSTING_READ(GEN8_##type##_IIR); \ | |
2804 | I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ | |
2805 | } while (0) | |
2806 | ||
2807 | GEN8_IRQ_INIT_NDX(GT, 0); | |
2808 | GEN8_IRQ_INIT_NDX(GT, 1); | |
2809 | GEN8_IRQ_INIT_NDX(GT, 2); | |
2810 | GEN8_IRQ_INIT_NDX(GT, 3); | |
2811 | ||
2812 | for_each_pipe(pipe) { | |
2813 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe); | |
2814 | } | |
2815 | ||
2816 | GEN8_IRQ_INIT(DE_PORT); | |
2817 | GEN8_IRQ_INIT(DE_MISC); | |
2818 | GEN8_IRQ_INIT(PCU); | |
2819 | #undef GEN8_IRQ_INIT | |
2820 | #undef GEN8_IRQ_INIT_NDX | |
2821 | ||
2822 | POSTING_READ(GEN8_PCU_IIR); | |
09f2344d JB |
2823 | |
2824 | ibx_irq_preinstall(dev); | |
abd58f01 BW |
2825 | } |
2826 | ||
82a28bcf | 2827 | static void ibx_hpd_irq_setup(struct drm_device *dev) |
7fe0b973 KP |
2828 | { |
2829 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
82a28bcf DV |
2830 | struct drm_mode_config *mode_config = &dev->mode_config; |
2831 | struct intel_encoder *intel_encoder; | |
fee884ed | 2832 | u32 hotplug_irqs, hotplug, enabled_irqs = 0; |
82a28bcf DV |
2833 | |
2834 | if (HAS_PCH_IBX(dev)) { | |
fee884ed | 2835 | hotplug_irqs = SDE_HOTPLUG_MASK; |
82a28bcf | 2836 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
cd569aed | 2837 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
fee884ed | 2838 | enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin]; |
82a28bcf | 2839 | } else { |
fee884ed | 2840 | hotplug_irqs = SDE_HOTPLUG_MASK_CPT; |
82a28bcf | 2841 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
cd569aed | 2842 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
fee884ed | 2843 | enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin]; |
82a28bcf | 2844 | } |
7fe0b973 | 2845 | |
fee884ed | 2846 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); |
82a28bcf DV |
2847 | |
2848 | /* | |
2849 | * Enable digital hotplug on the PCH, and configure the DP short pulse | |
2850 | * duration to 2ms (which is the minimum in the Display Port spec) | |
2851 | * | |
2852 | * This register is the same on all known PCH chips. | |
2853 | */ | |
7fe0b973 KP |
2854 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
2855 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); | |
2856 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; | |
2857 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; | |
2858 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; | |
2859 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); | |
2860 | } | |
2861 | ||
d46da437 PZ |
2862 | static void ibx_irq_postinstall(struct drm_device *dev) |
2863 | { | |
2864 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
82a28bcf | 2865 | u32 mask; |
e5868a31 | 2866 | |
692a04cf DV |
2867 | if (HAS_PCH_NOP(dev)) |
2868 | return; | |
2869 | ||
8664281b PZ |
2870 | if (HAS_PCH_IBX(dev)) { |
2871 | mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER | | |
de032bf4 | 2872 | SDE_TRANSA_FIFO_UNDER | SDE_POISON; |
8664281b PZ |
2873 | } else { |
2874 | mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT; | |
2875 | ||
2876 | I915_WRITE(SERR_INT, I915_READ(SERR_INT)); | |
2877 | } | |
ab5c608b | 2878 | |
d46da437 PZ |
2879 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); |
2880 | I915_WRITE(SDEIMR, ~mask); | |
d46da437 PZ |
2881 | } |
2882 | ||
0a9a8c91 DV |
2883 | static void gen5_gt_irq_postinstall(struct drm_device *dev) |
2884 | { | |
2885 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2886 | u32 pm_irqs, gt_irqs; | |
2887 | ||
2888 | pm_irqs = gt_irqs = 0; | |
2889 | ||
2890 | dev_priv->gt_irq_mask = ~0; | |
040d2baa | 2891 | if (HAS_L3_DPF(dev)) { |
0a9a8c91 | 2892 | /* L3 parity interrupt is always unmasked. */ |
35a85ac6 BW |
2893 | dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev); |
2894 | gt_irqs |= GT_PARITY_ERROR(dev); | |
0a9a8c91 DV |
2895 | } |
2896 | ||
2897 | gt_irqs |= GT_RENDER_USER_INTERRUPT; | |
2898 | if (IS_GEN5(dev)) { | |
2899 | gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | | |
2900 | ILK_BSD_USER_INTERRUPT; | |
2901 | } else { | |
2902 | gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; | |
2903 | } | |
2904 | ||
2905 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
2906 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
2907 | I915_WRITE(GTIER, gt_irqs); | |
2908 | POSTING_READ(GTIER); | |
2909 | ||
2910 | if (INTEL_INFO(dev)->gen >= 6) { | |
2911 | pm_irqs |= GEN6_PM_RPS_EVENTS; | |
2912 | ||
2913 | if (HAS_VEBOX(dev)) | |
2914 | pm_irqs |= PM_VEBOX_USER_INTERRUPT; | |
2915 | ||
605cd25b | 2916 | dev_priv->pm_irq_mask = 0xffffffff; |
0a9a8c91 | 2917 | I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); |
605cd25b | 2918 | I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask); |
0a9a8c91 DV |
2919 | I915_WRITE(GEN6_PMIER, pm_irqs); |
2920 | POSTING_READ(GEN6_PMIER); | |
2921 | } | |
2922 | } | |
2923 | ||
f71d4af4 | 2924 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d | 2925 | { |
4bc9d430 | 2926 | unsigned long irqflags; |
036a4a7d | 2927 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
8e76f8dc PZ |
2928 | u32 display_mask, extra_mask; |
2929 | ||
2930 | if (INTEL_INFO(dev)->gen >= 7) { | |
2931 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | | |
2932 | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | | |
2933 | DE_PLANEB_FLIP_DONE_IVB | | |
2934 | DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB | | |
2935 | DE_ERR_INT_IVB); | |
2936 | extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | | |
2937 | DE_PIPEA_VBLANK_IVB); | |
2938 | ||
2939 | I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT)); | |
2940 | } else { | |
2941 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | | |
2942 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | | |
5b3a856b DV |
2943 | DE_AUX_CHANNEL_A | |
2944 | DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN | | |
2945 | DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE | | |
2946 | DE_POISON); | |
8e76f8dc PZ |
2947 | extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT; |
2948 | } | |
036a4a7d | 2949 | |
1ec14ad3 | 2950 | dev_priv->irq_mask = ~display_mask; |
036a4a7d ZW |
2951 | |
2952 | /* should always can generate irq */ | |
2953 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1ec14ad3 | 2954 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
8e76f8dc | 2955 | I915_WRITE(DEIER, display_mask | extra_mask); |
3143a2bf | 2956 | POSTING_READ(DEIER); |
036a4a7d | 2957 | |
0a9a8c91 | 2958 | gen5_gt_irq_postinstall(dev); |
036a4a7d | 2959 | |
d46da437 | 2960 | ibx_irq_postinstall(dev); |
7fe0b973 | 2961 | |
f97108d1 | 2962 | if (IS_IRONLAKE_M(dev)) { |
6005ce42 DV |
2963 | /* Enable PCU event interrupts |
2964 | * | |
2965 | * spinlocking not required here for correctness since interrupt | |
4bc9d430 DV |
2966 | * setup is guaranteed to run in single-threaded context. But we |
2967 | * need it to make the assert_spin_locked happy. */ | |
2968 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
f97108d1 | 2969 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); |
4bc9d430 | 2970 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
f97108d1 JB |
2971 | } |
2972 | ||
036a4a7d ZW |
2973 | return 0; |
2974 | } | |
2975 | ||
7e231dbe JB |
2976 | static int valleyview_irq_postinstall(struct drm_device *dev) |
2977 | { | |
2978 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
7e231dbe | 2979 | u32 enable_mask; |
755e9019 ID |
2980 | u32 pipestat_enable = PLANE_FLIP_DONE_INT_STATUS_VLV | |
2981 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
b79480ba | 2982 | unsigned long irqflags; |
7e231dbe JB |
2983 | |
2984 | enable_mask = I915_DISPLAY_PORT_INTERRUPT; | |
31acc7f5 JB |
2985 | enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
2986 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | | |
2987 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
7e231dbe JB |
2988 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
2989 | ||
31acc7f5 JB |
2990 | /* |
2991 | *Leave vblank interrupts masked initially. enable/disable will | |
2992 | * toggle them based on usage. | |
2993 | */ | |
2994 | dev_priv->irq_mask = (~enable_mask) | | |
2995 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | | |
2996 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; | |
7e231dbe | 2997 | |
20afbda2 DV |
2998 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
2999 | POSTING_READ(PORT_HOTPLUG_EN); | |
3000 | ||
7e231dbe JB |
3001 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
3002 | I915_WRITE(VLV_IER, enable_mask); | |
3003 | I915_WRITE(VLV_IIR, 0xffffffff); | |
3004 | I915_WRITE(PIPESTAT(0), 0xffff); | |
3005 | I915_WRITE(PIPESTAT(1), 0xffff); | |
3006 | POSTING_READ(VLV_IER); | |
3007 | ||
b79480ba DV |
3008 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3009 | * just to make the assert_spin_locked check happy. */ | |
3010 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3b6c42e8 | 3011 | i915_enable_pipestat(dev_priv, PIPE_A, pipestat_enable); |
755e9019 | 3012 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
3b6c42e8 | 3013 | i915_enable_pipestat(dev_priv, PIPE_B, pipestat_enable); |
b79480ba | 3014 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
31acc7f5 | 3015 | |
7e231dbe JB |
3016 | I915_WRITE(VLV_IIR, 0xffffffff); |
3017 | I915_WRITE(VLV_IIR, 0xffffffff); | |
3018 | ||
0a9a8c91 | 3019 | gen5_gt_irq_postinstall(dev); |
7e231dbe JB |
3020 | |
3021 | /* ack & enable invalid PTE error interrupts */ | |
3022 | #if 0 /* FIXME: add support to irq handler for checking these bits */ | |
3023 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); | |
3024 | I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); | |
3025 | #endif | |
3026 | ||
3027 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); | |
20afbda2 DV |
3028 | |
3029 | return 0; | |
3030 | } | |
3031 | ||
abd58f01 BW |
3032 | static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) |
3033 | { | |
3034 | int i; | |
3035 | ||
3036 | /* These are interrupts we'll toggle with the ring mask register */ | |
3037 | uint32_t gt_interrupts[] = { | |
3038 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | | |
3039 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT | | |
3040 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT, | |
3041 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | | |
3042 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT, | |
3043 | 0, | |
3044 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
3045 | }; | |
3046 | ||
3047 | for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) { | |
3048 | u32 tmp = I915_READ(GEN8_GT_IIR(i)); | |
3049 | if (tmp) | |
3050 | DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n", | |
3051 | i, tmp); | |
3052 | I915_WRITE(GEN8_GT_IMR(i), ~gt_interrupts[i]); | |
3053 | I915_WRITE(GEN8_GT_IER(i), gt_interrupts[i]); | |
3054 | } | |
3055 | POSTING_READ(GEN8_GT_IER(0)); | |
3056 | } | |
3057 | ||
3058 | static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) | |
3059 | { | |
3060 | struct drm_device *dev = dev_priv->dev; | |
13b3a0a7 DV |
3061 | uint32_t de_pipe_masked = GEN8_PIPE_FLIP_DONE | |
3062 | GEN8_PIPE_CDCLK_CRC_DONE | | |
3063 | GEN8_PIPE_FIFO_UNDERRUN | | |
3064 | GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
3065 | uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK; | |
abd58f01 | 3066 | int pipe; |
13b3a0a7 DV |
3067 | dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; |
3068 | dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; | |
3069 | dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; | |
abd58f01 BW |
3070 | |
3071 | for_each_pipe(pipe) { | |
3072 | u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe)); | |
3073 | if (tmp) | |
3074 | DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n", | |
3075 | pipe, tmp); | |
3076 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
3077 | I915_WRITE(GEN8_DE_PIPE_IER(pipe), de_pipe_enables); | |
3078 | } | |
3079 | POSTING_READ(GEN8_DE_PIPE_ISR(0)); | |
3080 | ||
6d766f02 DV |
3081 | I915_WRITE(GEN8_DE_PORT_IMR, ~GEN8_AUX_CHANNEL_A); |
3082 | I915_WRITE(GEN8_DE_PORT_IER, GEN8_AUX_CHANNEL_A); | |
abd58f01 BW |
3083 | POSTING_READ(GEN8_DE_PORT_IER); |
3084 | } | |
3085 | ||
3086 | static int gen8_irq_postinstall(struct drm_device *dev) | |
3087 | { | |
3088 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3089 | ||
3090 | gen8_gt_irq_postinstall(dev_priv); | |
3091 | gen8_de_irq_postinstall(dev_priv); | |
3092 | ||
3093 | ibx_irq_postinstall(dev); | |
3094 | ||
3095 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); | |
3096 | POSTING_READ(GEN8_MASTER_IRQ); | |
3097 | ||
3098 | return 0; | |
3099 | } | |
3100 | ||
3101 | static void gen8_irq_uninstall(struct drm_device *dev) | |
3102 | { | |
3103 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3104 | int pipe; | |
3105 | ||
3106 | if (!dev_priv) | |
3107 | return; | |
3108 | ||
abd58f01 BW |
3109 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
3110 | ||
3111 | #define GEN8_IRQ_FINI_NDX(type, which) do { \ | |
3112 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ | |
3113 | I915_WRITE(GEN8_##type##_IER(which), 0); \ | |
3114 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
3115 | } while (0) | |
3116 | ||
3117 | #define GEN8_IRQ_FINI(type) do { \ | |
3118 | I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \ | |
3119 | I915_WRITE(GEN8_##type##_IER, 0); \ | |
3120 | I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ | |
3121 | } while (0) | |
3122 | ||
3123 | GEN8_IRQ_FINI_NDX(GT, 0); | |
3124 | GEN8_IRQ_FINI_NDX(GT, 1); | |
3125 | GEN8_IRQ_FINI_NDX(GT, 2); | |
3126 | GEN8_IRQ_FINI_NDX(GT, 3); | |
3127 | ||
3128 | for_each_pipe(pipe) { | |
3129 | GEN8_IRQ_FINI_NDX(DE_PIPE, pipe); | |
3130 | } | |
3131 | ||
3132 | GEN8_IRQ_FINI(DE_PORT); | |
3133 | GEN8_IRQ_FINI(DE_MISC); | |
3134 | GEN8_IRQ_FINI(PCU); | |
3135 | #undef GEN8_IRQ_FINI | |
3136 | #undef GEN8_IRQ_FINI_NDX | |
3137 | ||
3138 | POSTING_READ(GEN8_PCU_IIR); | |
3139 | } | |
3140 | ||
7e231dbe JB |
3141 | static void valleyview_irq_uninstall(struct drm_device *dev) |
3142 | { | |
3143 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
3144 | int pipe; | |
3145 | ||
3146 | if (!dev_priv) | |
3147 | return; | |
3148 | ||
3ca1cced | 3149 | intel_hpd_irq_uninstall(dev_priv); |
ac4c16c5 | 3150 | |
7e231dbe JB |
3151 | for_each_pipe(pipe) |
3152 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
3153 | ||
3154 | I915_WRITE(HWSTAM, 0xffffffff); | |
3155 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3156 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3157 | for_each_pipe(pipe) | |
3158 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
3159 | I915_WRITE(VLV_IIR, 0xffffffff); | |
3160 | I915_WRITE(VLV_IMR, 0xffffffff); | |
3161 | I915_WRITE(VLV_IER, 0x0); | |
3162 | POSTING_READ(VLV_IER); | |
3163 | } | |
3164 | ||
f71d4af4 | 3165 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d ZW |
3166 | { |
3167 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
4697995b JB |
3168 | |
3169 | if (!dev_priv) | |
3170 | return; | |
3171 | ||
3ca1cced | 3172 | intel_hpd_irq_uninstall(dev_priv); |
ac4c16c5 | 3173 | |
036a4a7d ZW |
3174 | I915_WRITE(HWSTAM, 0xffffffff); |
3175 | ||
3176 | I915_WRITE(DEIMR, 0xffffffff); | |
3177 | I915_WRITE(DEIER, 0x0); | |
3178 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
8664281b PZ |
3179 | if (IS_GEN7(dev)) |
3180 | I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT)); | |
036a4a7d ZW |
3181 | |
3182 | I915_WRITE(GTIMR, 0xffffffff); | |
3183 | I915_WRITE(GTIER, 0x0); | |
3184 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
192aac1f | 3185 | |
ab5c608b BW |
3186 | if (HAS_PCH_NOP(dev)) |
3187 | return; | |
3188 | ||
192aac1f KP |
3189 | I915_WRITE(SDEIMR, 0xffffffff); |
3190 | I915_WRITE(SDEIER, 0x0); | |
3191 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | |
8664281b PZ |
3192 | if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) |
3193 | I915_WRITE(SERR_INT, I915_READ(SERR_INT)); | |
036a4a7d ZW |
3194 | } |
3195 | ||
a266c7d5 | 3196 | static void i8xx_irq_preinstall(struct drm_device * dev) |
1da177e4 LT |
3197 | { |
3198 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 3199 | int pipe; |
91e3738e | 3200 | |
9db4a9c7 JB |
3201 | for_each_pipe(pipe) |
3202 | I915_WRITE(PIPESTAT(pipe), 0); | |
a266c7d5 CW |
3203 | I915_WRITE16(IMR, 0xffff); |
3204 | I915_WRITE16(IER, 0x0); | |
3205 | POSTING_READ16(IER); | |
c2798b19 CW |
3206 | } |
3207 | ||
3208 | static int i8xx_irq_postinstall(struct drm_device *dev) | |
3209 | { | |
3210 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
379ef82d | 3211 | unsigned long irqflags; |
c2798b19 | 3212 | |
c2798b19 CW |
3213 | I915_WRITE16(EMR, |
3214 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); | |
3215 | ||
3216 | /* Unmask the interrupts that we always want on. */ | |
3217 | dev_priv->irq_mask = | |
3218 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3219 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3220 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3221 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3222 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3223 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
3224 | ||
3225 | I915_WRITE16(IER, | |
3226 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3227 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3228 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
3229 | I915_USER_INTERRUPT); | |
3230 | POSTING_READ16(IER); | |
3231 | ||
379ef82d DV |
3232 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3233 | * just to make the assert_spin_locked check happy. */ | |
3234 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
755e9019 ID |
3235 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3236 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
379ef82d DV |
3237 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
3238 | ||
c2798b19 CW |
3239 | return 0; |
3240 | } | |
3241 | ||
90a72f87 VS |
3242 | /* |
3243 | * Returns true when a page flip has completed. | |
3244 | */ | |
3245 | static bool i8xx_handle_vblank(struct drm_device *dev, | |
1f1c2e24 | 3246 | int plane, int pipe, u32 iir) |
90a72f87 VS |
3247 | { |
3248 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1f1c2e24 | 3249 | u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
90a72f87 VS |
3250 | |
3251 | if (!drm_handle_vblank(dev, pipe)) | |
3252 | return false; | |
3253 | ||
3254 | if ((iir & flip_pending) == 0) | |
3255 | return false; | |
3256 | ||
1f1c2e24 | 3257 | intel_prepare_page_flip(dev, plane); |
90a72f87 VS |
3258 | |
3259 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
3260 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3261 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3262 | * the flip is completed (no longer pending). Since this doesn't raise | |
3263 | * an interrupt per se, we watch for the change at vblank. | |
3264 | */ | |
3265 | if (I915_READ16(ISR) & flip_pending) | |
3266 | return false; | |
3267 | ||
3268 | intel_finish_page_flip(dev, pipe); | |
3269 | ||
3270 | return true; | |
3271 | } | |
3272 | ||
ff1f525e | 3273 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
c2798b19 CW |
3274 | { |
3275 | struct drm_device *dev = (struct drm_device *) arg; | |
3276 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
c2798b19 CW |
3277 | u16 iir, new_iir; |
3278 | u32 pipe_stats[2]; | |
3279 | unsigned long irqflags; | |
c2798b19 CW |
3280 | int pipe; |
3281 | u16 flip_mask = | |
3282 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3283 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
3284 | ||
c2798b19 CW |
3285 | iir = I915_READ16(IIR); |
3286 | if (iir == 0) | |
3287 | return IRQ_NONE; | |
3288 | ||
3289 | while (iir & ~flip_mask) { | |
3290 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3291 | * have been cleared after the pipestat interrupt was received. | |
3292 | * It doesn't set the bit in iir again, but it still produces | |
3293 | * interrupts (for non-MSI). | |
3294 | */ | |
3295 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3296 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
3297 | i915_handle_error(dev, false); | |
3298 | ||
3299 | for_each_pipe(pipe) { | |
3300 | int reg = PIPESTAT(pipe); | |
3301 | pipe_stats[pipe] = I915_READ(reg); | |
3302 | ||
3303 | /* | |
3304 | * Clear the PIPE*STAT regs before the IIR | |
3305 | */ | |
2d9d2b0b | 3306 | if (pipe_stats[pipe] & 0x8000ffff) |
c2798b19 | 3307 | I915_WRITE(reg, pipe_stats[pipe]); |
c2798b19 CW |
3308 | } |
3309 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3310 | ||
3311 | I915_WRITE16(IIR, iir & ~flip_mask); | |
3312 | new_iir = I915_READ16(IIR); /* Flush posted writes */ | |
3313 | ||
d05c617e | 3314 | i915_update_dri1_breadcrumb(dev); |
c2798b19 CW |
3315 | |
3316 | if (iir & I915_USER_INTERRUPT) | |
3317 | notify_ring(dev, &dev_priv->ring[RCS]); | |
3318 | ||
4356d586 | 3319 | for_each_pipe(pipe) { |
1f1c2e24 | 3320 | int plane = pipe; |
3a77c4c4 | 3321 | if (HAS_FBC(dev)) |
1f1c2e24 VS |
3322 | plane = !plane; |
3323 | ||
4356d586 | 3324 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
1f1c2e24 VS |
3325 | i8xx_handle_vblank(dev, plane, pipe, iir)) |
3326 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
c2798b19 | 3327 | |
4356d586 | 3328 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
277de95e | 3329 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b VS |
3330 | |
3331 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && | |
3332 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
fc2c807b | 3333 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); |
4356d586 | 3334 | } |
c2798b19 CW |
3335 | |
3336 | iir = new_iir; | |
3337 | } | |
3338 | ||
3339 | return IRQ_HANDLED; | |
3340 | } | |
3341 | ||
3342 | static void i8xx_irq_uninstall(struct drm_device * dev) | |
3343 | { | |
3344 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
3345 | int pipe; | |
3346 | ||
c2798b19 CW |
3347 | for_each_pipe(pipe) { |
3348 | /* Clear enable bits; then clear status bits */ | |
3349 | I915_WRITE(PIPESTAT(pipe), 0); | |
3350 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); | |
3351 | } | |
3352 | I915_WRITE16(IMR, 0xffff); | |
3353 | I915_WRITE16(IER, 0x0); | |
3354 | I915_WRITE16(IIR, I915_READ16(IIR)); | |
3355 | } | |
3356 | ||
a266c7d5 CW |
3357 | static void i915_irq_preinstall(struct drm_device * dev) |
3358 | { | |
3359 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
3360 | int pipe; | |
3361 | ||
a266c7d5 CW |
3362 | if (I915_HAS_HOTPLUG(dev)) { |
3363 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3364 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3365 | } | |
3366 | ||
00d98ebd | 3367 | I915_WRITE16(HWSTAM, 0xeffe); |
a266c7d5 CW |
3368 | for_each_pipe(pipe) |
3369 | I915_WRITE(PIPESTAT(pipe), 0); | |
3370 | I915_WRITE(IMR, 0xffffffff); | |
3371 | I915_WRITE(IER, 0x0); | |
3372 | POSTING_READ(IER); | |
3373 | } | |
3374 | ||
3375 | static int i915_irq_postinstall(struct drm_device *dev) | |
3376 | { | |
3377 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
38bde180 | 3378 | u32 enable_mask; |
379ef82d | 3379 | unsigned long irqflags; |
a266c7d5 | 3380 | |
38bde180 CW |
3381 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
3382 | ||
3383 | /* Unmask the interrupts that we always want on. */ | |
3384 | dev_priv->irq_mask = | |
3385 | ~(I915_ASLE_INTERRUPT | | |
3386 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3387 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3388 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3389 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3390 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3391 | ||
3392 | enable_mask = | |
3393 | I915_ASLE_INTERRUPT | | |
3394 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3395 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3396 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
3397 | I915_USER_INTERRUPT; | |
3398 | ||
a266c7d5 | 3399 | if (I915_HAS_HOTPLUG(dev)) { |
20afbda2 DV |
3400 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3401 | POSTING_READ(PORT_HOTPLUG_EN); | |
3402 | ||
a266c7d5 CW |
3403 | /* Enable in IER... */ |
3404 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
3405 | /* and unmask in IMR */ | |
3406 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; | |
3407 | } | |
3408 | ||
a266c7d5 CW |
3409 | I915_WRITE(IMR, dev_priv->irq_mask); |
3410 | I915_WRITE(IER, enable_mask); | |
3411 | POSTING_READ(IER); | |
3412 | ||
f49e38dd | 3413 | i915_enable_asle_pipestat(dev); |
20afbda2 | 3414 | |
379ef82d DV |
3415 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3416 | * just to make the assert_spin_locked check happy. */ | |
3417 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
755e9019 ID |
3418 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3419 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
379ef82d DV |
3420 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
3421 | ||
20afbda2 DV |
3422 | return 0; |
3423 | } | |
3424 | ||
90a72f87 VS |
3425 | /* |
3426 | * Returns true when a page flip has completed. | |
3427 | */ | |
3428 | static bool i915_handle_vblank(struct drm_device *dev, | |
3429 | int plane, int pipe, u32 iir) | |
3430 | { | |
3431 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3432 | u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); | |
3433 | ||
3434 | if (!drm_handle_vblank(dev, pipe)) | |
3435 | return false; | |
3436 | ||
3437 | if ((iir & flip_pending) == 0) | |
3438 | return false; | |
3439 | ||
3440 | intel_prepare_page_flip(dev, plane); | |
3441 | ||
3442 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
3443 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3444 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3445 | * the flip is completed (no longer pending). Since this doesn't raise | |
3446 | * an interrupt per se, we watch for the change at vblank. | |
3447 | */ | |
3448 | if (I915_READ(ISR) & flip_pending) | |
3449 | return false; | |
3450 | ||
3451 | intel_finish_page_flip(dev, pipe); | |
3452 | ||
3453 | return true; | |
3454 | } | |
3455 | ||
ff1f525e | 3456 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
a266c7d5 CW |
3457 | { |
3458 | struct drm_device *dev = (struct drm_device *) arg; | |
3459 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
8291ee90 | 3460 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
a266c7d5 | 3461 | unsigned long irqflags; |
38bde180 CW |
3462 | u32 flip_mask = |
3463 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3464 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
38bde180 | 3465 | int pipe, ret = IRQ_NONE; |
a266c7d5 | 3466 | |
a266c7d5 | 3467 | iir = I915_READ(IIR); |
38bde180 CW |
3468 | do { |
3469 | bool irq_received = (iir & ~flip_mask) != 0; | |
8291ee90 | 3470 | bool blc_event = false; |
a266c7d5 CW |
3471 | |
3472 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3473 | * have been cleared after the pipestat interrupt was received. | |
3474 | * It doesn't set the bit in iir again, but it still produces | |
3475 | * interrupts (for non-MSI). | |
3476 | */ | |
3477 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3478 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
3479 | i915_handle_error(dev, false); | |
3480 | ||
3481 | for_each_pipe(pipe) { | |
3482 | int reg = PIPESTAT(pipe); | |
3483 | pipe_stats[pipe] = I915_READ(reg); | |
3484 | ||
38bde180 | 3485 | /* Clear the PIPE*STAT regs before the IIR */ |
a266c7d5 | 3486 | if (pipe_stats[pipe] & 0x8000ffff) { |
a266c7d5 | 3487 | I915_WRITE(reg, pipe_stats[pipe]); |
38bde180 | 3488 | irq_received = true; |
a266c7d5 CW |
3489 | } |
3490 | } | |
3491 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3492 | ||
3493 | if (!irq_received) | |
3494 | break; | |
3495 | ||
a266c7d5 CW |
3496 | /* Consume port. Then clear IIR or we'll miss events */ |
3497 | if ((I915_HAS_HOTPLUG(dev)) && | |
3498 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { | |
3499 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
b543fb04 | 3500 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; |
a266c7d5 | 3501 | |
91d131d2 DV |
3502 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); |
3503 | ||
a266c7d5 | 3504 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
38bde180 | 3505 | POSTING_READ(PORT_HOTPLUG_STAT); |
a266c7d5 CW |
3506 | } |
3507 | ||
38bde180 | 3508 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
3509 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
3510 | ||
a266c7d5 CW |
3511 | if (iir & I915_USER_INTERRUPT) |
3512 | notify_ring(dev, &dev_priv->ring[RCS]); | |
a266c7d5 | 3513 | |
a266c7d5 | 3514 | for_each_pipe(pipe) { |
38bde180 | 3515 | int plane = pipe; |
3a77c4c4 | 3516 | if (HAS_FBC(dev)) |
38bde180 | 3517 | plane = !plane; |
90a72f87 | 3518 | |
8291ee90 | 3519 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
3520 | i915_handle_vblank(dev, plane, pipe, iir)) |
3521 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
a266c7d5 CW |
3522 | |
3523 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
3524 | blc_event = true; | |
4356d586 DV |
3525 | |
3526 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 3527 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b VS |
3528 | |
3529 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && | |
3530 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
fc2c807b | 3531 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); |
a266c7d5 CW |
3532 | } |
3533 | ||
a266c7d5 CW |
3534 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
3535 | intel_opregion_asle_intr(dev); | |
3536 | ||
3537 | /* With MSI, interrupts are only generated when iir | |
3538 | * transitions from zero to nonzero. If another bit got | |
3539 | * set while we were handling the existing iir bits, then | |
3540 | * we would never get another interrupt. | |
3541 | * | |
3542 | * This is fine on non-MSI as well, as if we hit this path | |
3543 | * we avoid exiting the interrupt handler only to generate | |
3544 | * another one. | |
3545 | * | |
3546 | * Note that for MSI this could cause a stray interrupt report | |
3547 | * if an interrupt landed in the time between writing IIR and | |
3548 | * the posting read. This should be rare enough to never | |
3549 | * trigger the 99% of 100,000 interrupts test for disabling | |
3550 | * stray interrupts. | |
3551 | */ | |
38bde180 | 3552 | ret = IRQ_HANDLED; |
a266c7d5 | 3553 | iir = new_iir; |
38bde180 | 3554 | } while (iir & ~flip_mask); |
a266c7d5 | 3555 | |
d05c617e | 3556 | i915_update_dri1_breadcrumb(dev); |
8291ee90 | 3557 | |
a266c7d5 CW |
3558 | return ret; |
3559 | } | |
3560 | ||
3561 | static void i915_irq_uninstall(struct drm_device * dev) | |
3562 | { | |
3563 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
3564 | int pipe; | |
3565 | ||
3ca1cced | 3566 | intel_hpd_irq_uninstall(dev_priv); |
ac4c16c5 | 3567 | |
a266c7d5 CW |
3568 | if (I915_HAS_HOTPLUG(dev)) { |
3569 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3570 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3571 | } | |
3572 | ||
00d98ebd | 3573 | I915_WRITE16(HWSTAM, 0xffff); |
55b39755 CW |
3574 | for_each_pipe(pipe) { |
3575 | /* Clear enable bits; then clear status bits */ | |
a266c7d5 | 3576 | I915_WRITE(PIPESTAT(pipe), 0); |
55b39755 CW |
3577 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
3578 | } | |
a266c7d5 CW |
3579 | I915_WRITE(IMR, 0xffffffff); |
3580 | I915_WRITE(IER, 0x0); | |
3581 | ||
a266c7d5 CW |
3582 | I915_WRITE(IIR, I915_READ(IIR)); |
3583 | } | |
3584 | ||
3585 | static void i965_irq_preinstall(struct drm_device * dev) | |
3586 | { | |
3587 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
3588 | int pipe; | |
3589 | ||
adca4730 CW |
3590 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3591 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
3592 | |
3593 | I915_WRITE(HWSTAM, 0xeffe); | |
3594 | for_each_pipe(pipe) | |
3595 | I915_WRITE(PIPESTAT(pipe), 0); | |
3596 | I915_WRITE(IMR, 0xffffffff); | |
3597 | I915_WRITE(IER, 0x0); | |
3598 | POSTING_READ(IER); | |
3599 | } | |
3600 | ||
3601 | static int i965_irq_postinstall(struct drm_device *dev) | |
3602 | { | |
3603 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
bbba0a97 | 3604 | u32 enable_mask; |
a266c7d5 | 3605 | u32 error_mask; |
b79480ba | 3606 | unsigned long irqflags; |
a266c7d5 | 3607 | |
a266c7d5 | 3608 | /* Unmask the interrupts that we always want on. */ |
bbba0a97 | 3609 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
adca4730 | 3610 | I915_DISPLAY_PORT_INTERRUPT | |
bbba0a97 CW |
3611 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
3612 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3613 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3614 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3615 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3616 | ||
3617 | enable_mask = ~dev_priv->irq_mask; | |
21ad8330 VS |
3618 | enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
3619 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); | |
bbba0a97 CW |
3620 | enable_mask |= I915_USER_INTERRUPT; |
3621 | ||
3622 | if (IS_G4X(dev)) | |
3623 | enable_mask |= I915_BSD_USER_INTERRUPT; | |
a266c7d5 | 3624 | |
b79480ba DV |
3625 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3626 | * just to make the assert_spin_locked check happy. */ | |
3627 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
755e9019 ID |
3628 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
3629 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
3630 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
b79480ba | 3631 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
a266c7d5 | 3632 | |
a266c7d5 CW |
3633 | /* |
3634 | * Enable some error detection, note the instruction error mask | |
3635 | * bit is reserved, so we leave it masked. | |
3636 | */ | |
3637 | if (IS_G4X(dev)) { | |
3638 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
3639 | GM45_ERROR_MEM_PRIV | | |
3640 | GM45_ERROR_CP_PRIV | | |
3641 | I915_ERROR_MEMORY_REFRESH); | |
3642 | } else { | |
3643 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
3644 | I915_ERROR_MEMORY_REFRESH); | |
3645 | } | |
3646 | I915_WRITE(EMR, error_mask); | |
3647 | ||
3648 | I915_WRITE(IMR, dev_priv->irq_mask); | |
3649 | I915_WRITE(IER, enable_mask); | |
3650 | POSTING_READ(IER); | |
3651 | ||
20afbda2 DV |
3652 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3653 | POSTING_READ(PORT_HOTPLUG_EN); | |
3654 | ||
f49e38dd | 3655 | i915_enable_asle_pipestat(dev); |
20afbda2 DV |
3656 | |
3657 | return 0; | |
3658 | } | |
3659 | ||
bac56d5b | 3660 | static void i915_hpd_irq_setup(struct drm_device *dev) |
20afbda2 DV |
3661 | { |
3662 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e5868a31 | 3663 | struct drm_mode_config *mode_config = &dev->mode_config; |
cd569aed | 3664 | struct intel_encoder *intel_encoder; |
20afbda2 DV |
3665 | u32 hotplug_en; |
3666 | ||
b5ea2d56 DV |
3667 | assert_spin_locked(&dev_priv->irq_lock); |
3668 | ||
bac56d5b EE |
3669 | if (I915_HAS_HOTPLUG(dev)) { |
3670 | hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
3671 | hotplug_en &= ~HOTPLUG_INT_EN_MASK; | |
3672 | /* Note HDMI and DP share hotplug bits */ | |
e5868a31 | 3673 | /* enable bits are the same for all generations */ |
cd569aed EE |
3674 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
3675 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) | |
3676 | hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin]; | |
bac56d5b EE |
3677 | /* Programming the CRT detection parameters tends |
3678 | to generate a spurious hotplug event about three | |
3679 | seconds later. So just do it once. | |
3680 | */ | |
3681 | if (IS_G4X(dev)) | |
3682 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
85fc95ba | 3683 | hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK; |
bac56d5b | 3684 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
a266c7d5 | 3685 | |
bac56d5b EE |
3686 | /* Ignore TV since it's buggy */ |
3687 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
3688 | } | |
a266c7d5 CW |
3689 | } |
3690 | ||
ff1f525e | 3691 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
a266c7d5 CW |
3692 | { |
3693 | struct drm_device *dev = (struct drm_device *) arg; | |
3694 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
a266c7d5 CW |
3695 | u32 iir, new_iir; |
3696 | u32 pipe_stats[I915_MAX_PIPES]; | |
a266c7d5 | 3697 | unsigned long irqflags; |
a266c7d5 | 3698 | int ret = IRQ_NONE, pipe; |
21ad8330 VS |
3699 | u32 flip_mask = |
3700 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3701 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
a266c7d5 | 3702 | |
a266c7d5 CW |
3703 | iir = I915_READ(IIR); |
3704 | ||
a266c7d5 | 3705 | for (;;) { |
501e01d7 | 3706 | bool irq_received = (iir & ~flip_mask) != 0; |
2c8ba29f CW |
3707 | bool blc_event = false; |
3708 | ||
a266c7d5 CW |
3709 | /* Can't rely on pipestat interrupt bit in iir as it might |
3710 | * have been cleared after the pipestat interrupt was received. | |
3711 | * It doesn't set the bit in iir again, but it still produces | |
3712 | * interrupts (for non-MSI). | |
3713 | */ | |
3714 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3715 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
3716 | i915_handle_error(dev, false); | |
3717 | ||
3718 | for_each_pipe(pipe) { | |
3719 | int reg = PIPESTAT(pipe); | |
3720 | pipe_stats[pipe] = I915_READ(reg); | |
3721 | ||
3722 | /* | |
3723 | * Clear the PIPE*STAT regs before the IIR | |
3724 | */ | |
3725 | if (pipe_stats[pipe] & 0x8000ffff) { | |
a266c7d5 | 3726 | I915_WRITE(reg, pipe_stats[pipe]); |
501e01d7 | 3727 | irq_received = true; |
a266c7d5 CW |
3728 | } |
3729 | } | |
3730 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3731 | ||
3732 | if (!irq_received) | |
3733 | break; | |
3734 | ||
3735 | ret = IRQ_HANDLED; | |
3736 | ||
3737 | /* Consume port. Then clear IIR or we'll miss events */ | |
adca4730 | 3738 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { |
a266c7d5 | 3739 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
b543fb04 EE |
3740 | u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ? |
3741 | HOTPLUG_INT_STATUS_G4X : | |
4f7fd709 | 3742 | HOTPLUG_INT_STATUS_I915); |
a266c7d5 | 3743 | |
91d131d2 | 3744 | intel_hpd_irq_handler(dev, hotplug_trigger, |
704cfb87 | 3745 | IS_G4X(dev) ? hpd_status_g4x : hpd_status_i915); |
91d131d2 | 3746 | |
4aeebd74 DV |
3747 | if (IS_G4X(dev) && |
3748 | (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)) | |
3749 | dp_aux_irq_handler(dev); | |
3750 | ||
a266c7d5 CW |
3751 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
3752 | I915_READ(PORT_HOTPLUG_STAT); | |
3753 | } | |
3754 | ||
21ad8330 | 3755 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
3756 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
3757 | ||
a266c7d5 CW |
3758 | if (iir & I915_USER_INTERRUPT) |
3759 | notify_ring(dev, &dev_priv->ring[RCS]); | |
3760 | if (iir & I915_BSD_USER_INTERRUPT) | |
3761 | notify_ring(dev, &dev_priv->ring[VCS]); | |
3762 | ||
a266c7d5 | 3763 | for_each_pipe(pipe) { |
2c8ba29f | 3764 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
3765 | i915_handle_vblank(dev, pipe, pipe, iir)) |
3766 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); | |
a266c7d5 CW |
3767 | |
3768 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
3769 | blc_event = true; | |
4356d586 DV |
3770 | |
3771 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 3772 | i9xx_pipe_crc_irq_handler(dev, pipe); |
a266c7d5 | 3773 | |
2d9d2b0b VS |
3774 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && |
3775 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
fc2c807b | 3776 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); |
2d9d2b0b | 3777 | } |
a266c7d5 CW |
3778 | |
3779 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | |
3780 | intel_opregion_asle_intr(dev); | |
3781 | ||
515ac2bb DV |
3782 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
3783 | gmbus_irq_handler(dev); | |
3784 | ||
a266c7d5 CW |
3785 | /* With MSI, interrupts are only generated when iir |
3786 | * transitions from zero to nonzero. If another bit got | |
3787 | * set while we were handling the existing iir bits, then | |
3788 | * we would never get another interrupt. | |
3789 | * | |
3790 | * This is fine on non-MSI as well, as if we hit this path | |
3791 | * we avoid exiting the interrupt handler only to generate | |
3792 | * another one. | |
3793 | * | |
3794 | * Note that for MSI this could cause a stray interrupt report | |
3795 | * if an interrupt landed in the time between writing IIR and | |
3796 | * the posting read. This should be rare enough to never | |
3797 | * trigger the 99% of 100,000 interrupts test for disabling | |
3798 | * stray interrupts. | |
3799 | */ | |
3800 | iir = new_iir; | |
3801 | } | |
3802 | ||
d05c617e | 3803 | i915_update_dri1_breadcrumb(dev); |
2c8ba29f | 3804 | |
a266c7d5 CW |
3805 | return ret; |
3806 | } | |
3807 | ||
3808 | static void i965_irq_uninstall(struct drm_device * dev) | |
3809 | { | |
3810 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
3811 | int pipe; | |
3812 | ||
3813 | if (!dev_priv) | |
3814 | return; | |
3815 | ||
3ca1cced | 3816 | intel_hpd_irq_uninstall(dev_priv); |
ac4c16c5 | 3817 | |
adca4730 CW |
3818 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3819 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
3820 | |
3821 | I915_WRITE(HWSTAM, 0xffffffff); | |
3822 | for_each_pipe(pipe) | |
3823 | I915_WRITE(PIPESTAT(pipe), 0); | |
3824 | I915_WRITE(IMR, 0xffffffff); | |
3825 | I915_WRITE(IER, 0x0); | |
3826 | ||
3827 | for_each_pipe(pipe) | |
3828 | I915_WRITE(PIPESTAT(pipe), | |
3829 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); | |
3830 | I915_WRITE(IIR, I915_READ(IIR)); | |
3831 | } | |
3832 | ||
3ca1cced | 3833 | static void intel_hpd_irq_reenable(unsigned long data) |
ac4c16c5 EE |
3834 | { |
3835 | drm_i915_private_t *dev_priv = (drm_i915_private_t *)data; | |
3836 | struct drm_device *dev = dev_priv->dev; | |
3837 | struct drm_mode_config *mode_config = &dev->mode_config; | |
3838 | unsigned long irqflags; | |
3839 | int i; | |
3840 | ||
3841 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3842 | for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) { | |
3843 | struct drm_connector *connector; | |
3844 | ||
3845 | if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED) | |
3846 | continue; | |
3847 | ||
3848 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
3849 | ||
3850 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
3851 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
3852 | ||
3853 | if (intel_connector->encoder->hpd_pin == i) { | |
3854 | if (connector->polled != intel_connector->polled) | |
3855 | DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n", | |
3856 | drm_get_connector_name(connector)); | |
3857 | connector->polled = intel_connector->polled; | |
3858 | if (!connector->polled) | |
3859 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
3860 | } | |
3861 | } | |
3862 | } | |
3863 | if (dev_priv->display.hpd_irq_setup) | |
3864 | dev_priv->display.hpd_irq_setup(dev); | |
3865 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3866 | } | |
3867 | ||
f71d4af4 JB |
3868 | void intel_irq_init(struct drm_device *dev) |
3869 | { | |
8b2e326d CW |
3870 | struct drm_i915_private *dev_priv = dev->dev_private; |
3871 | ||
3872 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); | |
99584db3 | 3873 | INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func); |
c6a828d3 | 3874 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
a4da4fa4 | 3875 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
8b2e326d | 3876 | |
99584db3 DV |
3877 | setup_timer(&dev_priv->gpu_error.hangcheck_timer, |
3878 | i915_hangcheck_elapsed, | |
61bac78e | 3879 | (unsigned long) dev); |
3ca1cced | 3880 | setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable, |
ac4c16c5 | 3881 | (unsigned long) dev_priv); |
61bac78e | 3882 | |
97a19a24 | 3883 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); |
9ee32fea | 3884 | |
4cdb83ec VS |
3885 | if (IS_GEN2(dev)) { |
3886 | dev->max_vblank_count = 0; | |
3887 | dev->driver->get_vblank_counter = i8xx_get_vblank_counter; | |
3888 | } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { | |
f71d4af4 JB |
3889 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
3890 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; | |
391f75e2 VS |
3891 | } else { |
3892 | dev->driver->get_vblank_counter = i915_get_vblank_counter; | |
3893 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
f71d4af4 JB |
3894 | } |
3895 | ||
c2baf4b7 | 3896 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
c3613de9 | 3897 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; |
c2baf4b7 VS |
3898 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; |
3899 | } | |
f71d4af4 | 3900 | |
7e231dbe JB |
3901 | if (IS_VALLEYVIEW(dev)) { |
3902 | dev->driver->irq_handler = valleyview_irq_handler; | |
3903 | dev->driver->irq_preinstall = valleyview_irq_preinstall; | |
3904 | dev->driver->irq_postinstall = valleyview_irq_postinstall; | |
3905 | dev->driver->irq_uninstall = valleyview_irq_uninstall; | |
3906 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
3907 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
fa00abe0 | 3908 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
abd58f01 BW |
3909 | } else if (IS_GEN8(dev)) { |
3910 | dev->driver->irq_handler = gen8_irq_handler; | |
3911 | dev->driver->irq_preinstall = gen8_irq_preinstall; | |
3912 | dev->driver->irq_postinstall = gen8_irq_postinstall; | |
3913 | dev->driver->irq_uninstall = gen8_irq_uninstall; | |
3914 | dev->driver->enable_vblank = gen8_enable_vblank; | |
3915 | dev->driver->disable_vblank = gen8_disable_vblank; | |
3916 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; | |
f71d4af4 JB |
3917 | } else if (HAS_PCH_SPLIT(dev)) { |
3918 | dev->driver->irq_handler = ironlake_irq_handler; | |
3919 | dev->driver->irq_preinstall = ironlake_irq_preinstall; | |
3920 | dev->driver->irq_postinstall = ironlake_irq_postinstall; | |
3921 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
3922 | dev->driver->enable_vblank = ironlake_enable_vblank; | |
3923 | dev->driver->disable_vblank = ironlake_disable_vblank; | |
82a28bcf | 3924 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; |
f71d4af4 | 3925 | } else { |
c2798b19 CW |
3926 | if (INTEL_INFO(dev)->gen == 2) { |
3927 | dev->driver->irq_preinstall = i8xx_irq_preinstall; | |
3928 | dev->driver->irq_postinstall = i8xx_irq_postinstall; | |
3929 | dev->driver->irq_handler = i8xx_irq_handler; | |
3930 | dev->driver->irq_uninstall = i8xx_irq_uninstall; | |
a266c7d5 CW |
3931 | } else if (INTEL_INFO(dev)->gen == 3) { |
3932 | dev->driver->irq_preinstall = i915_irq_preinstall; | |
3933 | dev->driver->irq_postinstall = i915_irq_postinstall; | |
3934 | dev->driver->irq_uninstall = i915_irq_uninstall; | |
3935 | dev->driver->irq_handler = i915_irq_handler; | |
20afbda2 | 3936 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
c2798b19 | 3937 | } else { |
a266c7d5 CW |
3938 | dev->driver->irq_preinstall = i965_irq_preinstall; |
3939 | dev->driver->irq_postinstall = i965_irq_postinstall; | |
3940 | dev->driver->irq_uninstall = i965_irq_uninstall; | |
3941 | dev->driver->irq_handler = i965_irq_handler; | |
bac56d5b | 3942 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
c2798b19 | 3943 | } |
f71d4af4 JB |
3944 | dev->driver->enable_vblank = i915_enable_vblank; |
3945 | dev->driver->disable_vblank = i915_disable_vblank; | |
3946 | } | |
3947 | } | |
20afbda2 DV |
3948 | |
3949 | void intel_hpd_init(struct drm_device *dev) | |
3950 | { | |
3951 | struct drm_i915_private *dev_priv = dev->dev_private; | |
821450c6 EE |
3952 | struct drm_mode_config *mode_config = &dev->mode_config; |
3953 | struct drm_connector *connector; | |
b5ea2d56 | 3954 | unsigned long irqflags; |
821450c6 | 3955 | int i; |
20afbda2 | 3956 | |
821450c6 EE |
3957 | for (i = 1; i < HPD_NUM_PINS; i++) { |
3958 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
3959 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
3960 | } | |
3961 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
3962 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
3963 | connector->polled = intel_connector->polled; | |
3964 | if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE) | |
3965 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
3966 | } | |
b5ea2d56 DV |
3967 | |
3968 | /* Interrupt setup is already guaranteed to be single-threaded, this is | |
3969 | * just to make the assert_spin_locked checks happy. */ | |
3970 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
20afbda2 DV |
3971 | if (dev_priv->display.hpd_irq_setup) |
3972 | dev_priv->display.hpd_irq_setup(dev); | |
b5ea2d56 | 3973 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
20afbda2 | 3974 | } |
c67a470b PZ |
3975 | |
3976 | /* Disable interrupts so we can allow Package C8+. */ | |
3977 | void hsw_pc8_disable_interrupts(struct drm_device *dev) | |
3978 | { | |
3979 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3980 | unsigned long irqflags; | |
3981 | ||
3982 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3983 | ||
3984 | dev_priv->pc8.regsave.deimr = I915_READ(DEIMR); | |
3985 | dev_priv->pc8.regsave.sdeimr = I915_READ(SDEIMR); | |
3986 | dev_priv->pc8.regsave.gtimr = I915_READ(GTIMR); | |
3987 | dev_priv->pc8.regsave.gtier = I915_READ(GTIER); | |
3988 | dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR); | |
3989 | ||
1f2d4531 PZ |
3990 | ironlake_disable_display_irq(dev_priv, 0xffffffff); |
3991 | ibx_disable_display_interrupt(dev_priv, 0xffffffff); | |
c67a470b PZ |
3992 | ilk_disable_gt_irq(dev_priv, 0xffffffff); |
3993 | snb_disable_pm_irq(dev_priv, 0xffffffff); | |
3994 | ||
3995 | dev_priv->pc8.irqs_disabled = true; | |
3996 | ||
3997 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3998 | } | |
3999 | ||
4000 | /* Restore interrupts so we can recover from Package C8+. */ | |
4001 | void hsw_pc8_restore_interrupts(struct drm_device *dev) | |
4002 | { | |
4003 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4004 | unsigned long irqflags; | |
1f2d4531 | 4005 | uint32_t val; |
c67a470b PZ |
4006 | |
4007 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
4008 | ||
4009 | val = I915_READ(DEIMR); | |
1f2d4531 | 4010 | WARN(val != 0xffffffff, "DEIMR is 0x%08x\n", val); |
c67a470b | 4011 | |
1f2d4531 PZ |
4012 | val = I915_READ(SDEIMR); |
4013 | WARN(val != 0xffffffff, "SDEIMR is 0x%08x\n", val); | |
c67a470b PZ |
4014 | |
4015 | val = I915_READ(GTIMR); | |
1f2d4531 | 4016 | WARN(val != 0xffffffff, "GTIMR is 0x%08x\n", val); |
c67a470b PZ |
4017 | |
4018 | val = I915_READ(GEN6_PMIMR); | |
1f2d4531 | 4019 | WARN(val != 0xffffffff, "GEN6_PMIMR is 0x%08x\n", val); |
c67a470b PZ |
4020 | |
4021 | dev_priv->pc8.irqs_disabled = false; | |
4022 | ||
4023 | ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr); | |
1f2d4531 | 4024 | ibx_enable_display_interrupt(dev_priv, ~dev_priv->pc8.regsave.sdeimr); |
c67a470b PZ |
4025 | ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr); |
4026 | snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr); | |
4027 | I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier); | |
4028 | ||
4029 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
4030 | } |