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drm/i915: Fix HSW parity test
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/i915_drm.h>
1da177e4 35#include "i915_drv.h"
1c5d22f7 36#include "i915_trace.h"
79e53945 37#include "intel_drv.h"
1da177e4 38
e5868a31
EE		 39static const u32 hpd_ibx[] = {
40 [HPD_CRT] = SDE_CRT_HOTPLUG,
41 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
42 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
43 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
44 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
45};
46
47static const u32 hpd_cpt[] = {
48 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
73c352a2 49 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
e5868a31
EE		 50 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
51 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
52 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
53};
54
55static const u32 hpd_mask_i915[] = {
56 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
57 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
58 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
59 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
60 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
61 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
62};
63
64static const u32 hpd_status_gen4[] = {
65 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
66 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
67 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
68 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
69 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
70 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
71};
72
e5868a31
EE		 73static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
74 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
75 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
76 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
77 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
78 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
79 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
80};
81
036a4a7d 82/* For display hotplug interrupt */
995b6762 83static void
f2b115e6 84ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 85{
4bc9d430
DV		 86 assert_spin_locked(&dev_priv->irq_lock);
87
c67a470b
PZ		 88 if (dev_priv->pc8.irqs_disabled) {
89 WARN(1, "IRQs disabled\n");
90 dev_priv->pc8.regsave.deimr &= ~mask;
91 return;
92 }
93
1ec14ad3
CW		 94 if ((dev_priv->irq_mask & mask) != 0) {
95 dev_priv->irq_mask &= ~mask;
96 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 97 POSTING_READ(DEIMR);
036a4a7d
ZW		 98 }
99}
100
0ff9800a 101static void
f2b115e6 102ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 103{
4bc9d430
DV		 104 assert_spin_locked(&dev_priv->irq_lock);
105
c67a470b
PZ		 106 if (dev_priv->pc8.irqs_disabled) {
107 WARN(1, "IRQs disabled\n");
108 dev_priv->pc8.regsave.deimr |= mask;
109 return;
110 }
111
1ec14ad3
CW		 112 if ((dev_priv->irq_mask & mask) != mask) {
113 dev_priv->irq_mask |= mask;
114 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 115 POSTING_READ(DEIMR);
036a4a7d
ZW		 116 }
117}
118
43eaea13
PZ		 119/**
120 * ilk_update_gt_irq - update GTIMR
121 * @dev_priv: driver private
122 * @interrupt_mask: mask of interrupt bits to update
123 * @enabled_irq_mask: mask of interrupt bits to enable
124 */
125static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
126 uint32_t interrupt_mask,
127 uint32_t enabled_irq_mask)
128{
129 assert_spin_locked(&dev_priv->irq_lock);
130
c67a470b
PZ		 131 if (dev_priv->pc8.irqs_disabled) {
132 WARN(1, "IRQs disabled\n");
133 dev_priv->pc8.regsave.gtimr &= ~interrupt_mask;
134 dev_priv->pc8.regsave.gtimr |= (~enabled_irq_mask &
135 interrupt_mask);
136 return;
137 }
138
43eaea13
PZ		 139 dev_priv->gt_irq_mask &= ~interrupt_mask;
140 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
141 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
142 POSTING_READ(GTIMR);
143}
144
145void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
146{
147 ilk_update_gt_irq(dev_priv, mask, mask);
148}
149
150void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
151{
152 ilk_update_gt_irq(dev_priv, mask, 0);
153}
154
edbfdb45
PZ		 155/**
156 * snb_update_pm_irq - update GEN6_PMIMR
157 * @dev_priv: driver private
158 * @interrupt_mask: mask of interrupt bits to update
159 * @enabled_irq_mask: mask of interrupt bits to enable
160 */
161static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
162 uint32_t interrupt_mask,
163 uint32_t enabled_irq_mask)
164{
605cd25b 165 uint32_t new_val;
edbfdb45
PZ		 166
167 assert_spin_locked(&dev_priv->irq_lock);
168
c67a470b
PZ		 169 if (dev_priv->pc8.irqs_disabled) {
170 WARN(1, "IRQs disabled\n");
171 dev_priv->pc8.regsave.gen6_pmimr &= ~interrupt_mask;
172 dev_priv->pc8.regsave.gen6_pmimr |= (~enabled_irq_mask &
173 interrupt_mask);
174 return;
175 }
176
605cd25b 177 new_val = dev_priv->pm_irq_mask;
f52ecbcf
PZ		 178 new_val &= ~interrupt_mask;
179 new_val |= (~enabled_irq_mask & interrupt_mask);
180
605cd25b
PZ		 181 if (new_val != dev_priv->pm_irq_mask) {
182 dev_priv->pm_irq_mask = new_val;
183 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
f52ecbcf
PZ		 184 POSTING_READ(GEN6_PMIMR);
185 }
edbfdb45
PZ		 186}
187
188void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
189{
190 snb_update_pm_irq(dev_priv, mask, mask);
191}
192
193void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
194{
195 snb_update_pm_irq(dev_priv, mask, 0);
196}
197
8664281b
PZ		 198static bool ivb_can_enable_err_int(struct drm_device *dev)
199{
200 struct drm_i915_private *dev_priv = dev->dev_private;
201 struct intel_crtc *crtc;
202 enum pipe pipe;
203
4bc9d430
DV		 204 assert_spin_locked(&dev_priv->irq_lock);
205
8664281b
PZ		 206 for_each_pipe(pipe) {
207 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
208
209 if (crtc->cpu_fifo_underrun_disabled)
210 return false;
211 }
212
213 return true;
214}
215
216static bool cpt_can_enable_serr_int(struct drm_device *dev)
217{
218 struct drm_i915_private *dev_priv = dev->dev_private;
219 enum pipe pipe;
220 struct intel_crtc *crtc;
221
fee884ed
DV		 222 assert_spin_locked(&dev_priv->irq_lock);
223
8664281b
PZ		 224 for_each_pipe(pipe) {
225 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
226
227 if (crtc->pch_fifo_underrun_disabled)
228 return false;
229 }
230
231 return true;
232}
233
234static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
235 enum pipe pipe, bool enable)
236{
237 struct drm_i915_private *dev_priv = dev->dev_private;
238 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
239 DE_PIPEB_FIFO_UNDERRUN;
240
241 if (enable)
242 ironlake_enable_display_irq(dev_priv, bit);
243 else
244 ironlake_disable_display_irq(dev_priv, bit);
245}
246
247static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
7336df65 248 enum pipe pipe, bool enable)
8664281b
PZ		 249{
250 struct drm_i915_private *dev_priv = dev->dev_private;
8664281b 251 if (enable) {
7336df65
DV		 252 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
253
8664281b
PZ		 254 if (!ivb_can_enable_err_int(dev))
255 return;
256
8664281b
PZ		 257 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
258 } else {
7336df65
DV		 259 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
260
261 /* Change the state _after_ we've read out the current one. */
8664281b 262 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
7336df65
DV		 263
264 if (!was_enabled &&
265 (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
266 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
267 pipe_name(pipe));
268 }
8664281b
PZ		 269 }
270}
271
fee884ed
DV		 272/**
273 * ibx_display_interrupt_update - update SDEIMR
274 * @dev_priv: driver private
275 * @interrupt_mask: mask of interrupt bits to update
276 * @enabled_irq_mask: mask of interrupt bits to enable
277 */
278static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
279 uint32_t interrupt_mask,
280 uint32_t enabled_irq_mask)
281{
282 uint32_t sdeimr = I915_READ(SDEIMR);
283 sdeimr &= ~interrupt_mask;
284 sdeimr |= (~enabled_irq_mask & interrupt_mask);
285
286 assert_spin_locked(&dev_priv->irq_lock);
287
c67a470b
PZ		 288 if (dev_priv->pc8.irqs_disabled &&
289 (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) {
290 WARN(1, "IRQs disabled\n");
291 dev_priv->pc8.regsave.sdeimr &= ~interrupt_mask;
292 dev_priv->pc8.regsave.sdeimr |= (~enabled_irq_mask &
293 interrupt_mask);
294 return;
295 }
296
fee884ed
DV		 297 I915_WRITE(SDEIMR, sdeimr);
298 POSTING_READ(SDEIMR);
299}
300#define ibx_enable_display_interrupt(dev_priv, bits) \
301 ibx_display_interrupt_update((dev_priv), (bits), (bits))
302#define ibx_disable_display_interrupt(dev_priv, bits) \
303 ibx_display_interrupt_update((dev_priv), (bits), 0)
304
de28075d
DV		 305static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
306 enum transcoder pch_transcoder,
8664281b
PZ		 307 bool enable)
308{
8664281b 309 struct drm_i915_private *dev_priv = dev->dev_private;
de28075d
DV		 310 uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
311 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
8664281b
PZ		 312
313 if (enable)
fee884ed 314 ibx_enable_display_interrupt(dev_priv, bit);
8664281b 315 else
fee884ed 316 ibx_disable_display_interrupt(dev_priv, bit);
8664281b
PZ		 317}
318
319static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
320 enum transcoder pch_transcoder,
321 bool enable)
322{
323 struct drm_i915_private *dev_priv = dev->dev_private;
324
325 if (enable) {
1dd246fb
DV		 326 I915_WRITE(SERR_INT,
327 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
328
8664281b
PZ		 329 if (!cpt_can_enable_serr_int(dev))
330 return;
331
fee884ed 332 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
8664281b 333 } else {
1dd246fb
DV		 334 uint32_t tmp = I915_READ(SERR_INT);
335 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
336
337 /* Change the state _after_ we've read out the current one. */
fee884ed 338 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
1dd246fb
DV		 339
340 if (!was_enabled &&
341 (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
342 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
343 transcoder_name(pch_transcoder));
344 }
8664281b 345 }
8664281b
PZ		 346}
347
348/**
349 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
350 * @dev: drm device
351 * @pipe: pipe
352 * @enable: true if we want to report FIFO underrun errors, false otherwise
353 *
354 * This function makes us disable or enable CPU fifo underruns for a specific
355 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
356 * reporting for one pipe may also disable all the other CPU error interruts for
357 * the other pipes, due to the fact that there's just one interrupt mask/enable
358 * bit for all the pipes.
359 *
360 * Returns the previous state of underrun reporting.
361 */
362bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
363 enum pipe pipe, bool enable)
364{
365 struct drm_i915_private *dev_priv = dev->dev_private;
366 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
368 unsigned long flags;
369 bool ret;
370
371 spin_lock_irqsave(&dev_priv->irq_lock, flags);
372
373 ret = !intel_crtc->cpu_fifo_underrun_disabled;
374
375 if (enable == ret)
376 goto done;
377
378 intel_crtc->cpu_fifo_underrun_disabled = !enable;
379
380 if (IS_GEN5(dev) || IS_GEN6(dev))
381 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
382 else if (IS_GEN7(dev))
7336df65 383 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
8664281b
PZ		 384
385done:
386 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
387 return ret;
388}
389
390/**
391 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
392 * @dev: drm device
393 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
394 * @enable: true if we want to report FIFO underrun errors, false otherwise
395 *
396 * This function makes us disable or enable PCH fifo underruns for a specific
397 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
398 * underrun reporting for one transcoder may also disable all the other PCH
399 * error interruts for the other transcoders, due to the fact that there's just
400 * one interrupt mask/enable bit for all the transcoders.
401 *
402 * Returns the previous state of underrun reporting.
403 */
404bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
405 enum transcoder pch_transcoder,
406 bool enable)
407{
408 struct drm_i915_private *dev_priv = dev->dev_private;
de28075d
DV		 409 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8664281b
PZ		 411 unsigned long flags;
412 bool ret;
413
de28075d
DV		 414 /*
415 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
416 * has only one pch transcoder A that all pipes can use. To avoid racy
417 * pch transcoder -> pipe lookups from interrupt code simply store the
418 * underrun statistics in crtc A. Since we never expose this anywhere
419 * nor use it outside of the fifo underrun code here using the "wrong"
420 * crtc on LPT won't cause issues.
421 */
8664281b
PZ		 422
423 spin_lock_irqsave(&dev_priv->irq_lock, flags);
424
425 ret = !intel_crtc->pch_fifo_underrun_disabled;
426
427 if (enable == ret)
428 goto done;
429
430 intel_crtc->pch_fifo_underrun_disabled = !enable;
431
432 if (HAS_PCH_IBX(dev))
de28075d 433 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
8664281b
PZ		 434 else
435 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
436
437done:
438 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
439 return ret;
440}
441
442
7c463586
KP		 443void
444i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
445{
46c06a30
VS		 446 u32 reg = PIPESTAT(pipe);
447 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 448
b79480ba
DV		 449 assert_spin_locked(&dev_priv->irq_lock);
450
46c06a30
VS		 451 if ((pipestat & mask) == mask)
452 return;
453
454 /* Enable the interrupt, clear any pending status */
455 pipestat |= mask | (mask >> 16);
456 I915_WRITE(reg, pipestat);
457 POSTING_READ(reg);
7c463586
KP		 458}
459
460void
461i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
462{
46c06a30
VS		 463 u32 reg = PIPESTAT(pipe);
464 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 465
b79480ba
DV		 466 assert_spin_locked(&dev_priv->irq_lock);
467
46c06a30
VS		 468 if ((pipestat & mask) == 0)
469 return;
470
471 pipestat &= ~mask;
472 I915_WRITE(reg, pipestat);
473 POSTING_READ(reg);
7c463586
KP		 474}
475
01c66889 476/**
f49e38dd 477 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
01c66889 478 */
f49e38dd 479static void i915_enable_asle_pipestat(struct drm_device *dev)
01c66889 480{
1ec14ad3
CW		 481 drm_i915_private_t *dev_priv = dev->dev_private;
482 unsigned long irqflags;
483
f49e38dd
JN		 484 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
485 return;
486
1ec14ad3 487 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 488
f898780b
JN		 489 i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE);
490 if (INTEL_INFO(dev)->gen >= 4)
491 i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE);
1ec14ad3
CW		 492
493 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 494}
495
0a3e67a4
JB		 496/**
497 * i915_pipe_enabled - check if a pipe is enabled
498 * @dev: DRM device
499 * @pipe: pipe to check
500 *
501 * Reading certain registers when the pipe is disabled can hang the chip.
502 * Use this routine to make sure the PLL is running and the pipe is active
503 * before reading such registers if unsure.
504 */
505static int
506i915_pipe_enabled(struct drm_device *dev, int pipe)
507{
508 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
702e7a56 509
a01025af
DV		 510 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
511 /* Locking is horribly broken here, but whatever. */
512 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
71f8ba6b 514
a01025af
DV		 515 return intel_crtc->active;
516 } else {
517 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
518 }
0a3e67a4
JB		 519}
520
42f52ef8
KP		 521/* Called from drm generic code, passed a 'crtc', which
522 * we use as a pipe index
523 */
f71d4af4 524static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 525{
526 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
527 unsigned long high_frame;
528 unsigned long low_frame;
5eddb70b 529 u32 high1, high2, low;
0a3e67a4
JB		 530
531 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 532 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 533 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 534 return 0;
535 }
536
9db4a9c7
JB		 537 high_frame = PIPEFRAME(pipe);
538 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 539
0a3e67a4
JB		 540 /*
541 * High & low register fields aren't synchronized, so make sure
542 * we get a low value that's stable across two reads of the high
543 * register.
544 */
545 do {
5eddb70b
CW		 546 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
547 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
548 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 549 } while (high1 != high2);
550
5eddb70b
CW		 551 high1 >>= PIPE_FRAME_HIGH_SHIFT;
552 low >>= PIPE_FRAME_LOW_SHIFT;
553 return (high1 << 8) | low;
0a3e67a4
JB		 554}
555
f71d4af4 556static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 557{
558 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 559 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 560
561 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 562 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 563 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 564 return 0;
565 }
566
567 return I915_READ(reg);
568}
569
f71d4af4 570static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 571 int *vpos, int *hpos)
572{
573 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
574 u32 vbl = 0, position = 0;
575 int vbl_start, vbl_end, htotal, vtotal;
576 bool in_vbl = true;
577 int ret = 0;
fe2b8f9d
PZ		 578 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
579 pipe);
0af7e4df
MK		 580
581 if (!i915_pipe_enabled(dev, pipe)) {
582 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 583 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 584 return 0;
585 }
586
587 /* Get vtotal. */
fe2b8f9d 588 vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 589
590 if (INTEL_INFO(dev)->gen >= 4) {
591 /* No obvious pixelcount register. Only query vertical
592 * scanout position from Display scan line register.
593 */
594 position = I915_READ(PIPEDSL(pipe));
595
596 /* Decode into vertical scanout position. Don't have
597 * horizontal scanout position.
598 */
599 *vpos = position & 0x1fff;
600 *hpos = 0;
601 } else {
602 /* Have access to pixelcount since start of frame.
603 * We can split this into vertical and horizontal
604 * scanout position.
605 */
606 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
607
fe2b8f9d 608 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 609 *vpos = position / htotal;
610 *hpos = position - (*vpos * htotal);
611 }
612
613 /* Query vblank area. */
fe2b8f9d 614 vbl = I915_READ(VBLANK(cpu_transcoder));
0af7e4df
MK		 615
616 /* Test position against vblank region. */
617 vbl_start = vbl & 0x1fff;
618 vbl_end = (vbl >> 16) & 0x1fff;
619
620 if ((*vpos < vbl_start) || (*vpos > vbl_end))
621 in_vbl = false;
622
623 /* Inside "upper part" of vblank area? Apply corrective offset: */
624 if (in_vbl && (*vpos >= vbl_start))
625 *vpos = *vpos - vtotal;
626
627 /* Readouts valid? */
628 if (vbl > 0)
629 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
630
631 /* In vblank? */
632 if (in_vbl)
633 ret |= DRM_SCANOUTPOS_INVBL;
634
635 return ret;
636}
637
f71d4af4 638static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 639 int *max_error,
640 struct timeval *vblank_time,
641 unsigned flags)
642{
4041b853 643 struct drm_crtc *crtc;
0af7e4df 644
7eb552ae 645 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
4041b853 646 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 647 return -EINVAL;
648 }
649
650 /* Get drm_crtc to timestamp: */
4041b853
CW		 651 crtc = intel_get_crtc_for_pipe(dev, pipe);
652 if (crtc == NULL) {
653 DRM_ERROR("Invalid crtc %d\n", pipe);
654 return -EINVAL;
655 }
656
657 if (!crtc->enabled) {
658 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
659 return -EBUSY;
660 }
0af7e4df
MK		 661
662 /* Helper routine in DRM core does all the work: */
4041b853
CW		 663 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
664 vblank_time, flags,
665 crtc);
0af7e4df
MK		 666}
667
67c347ff
JN		 668static bool intel_hpd_irq_event(struct drm_device *dev,
669 struct drm_connector *connector)
321a1b30
EE		 670{
671 enum drm_connector_status old_status;
672
673 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
674 old_status = connector->status;
675
676 connector->status = connector->funcs->detect(connector, false);
67c347ff
JN		 677 if (old_status == connector->status)
678 return false;
679
680 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
321a1b30
EE		 681 connector->base.id,
682 drm_get_connector_name(connector),
67c347ff
JN		 683 drm_get_connector_status_name(old_status),
684 drm_get_connector_status_name(connector->status));
685
686 return true;
321a1b30
EE		 687}
688
5ca58282
JB		 689/*
690 * Handle hotplug events outside the interrupt handler proper.
691 */
ac4c16c5
EE		 692#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
693
5ca58282
JB		 694static void i915_hotplug_work_func(struct work_struct *work)
695{
696 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
697 hotplug_work);
698 struct drm_device *dev = dev_priv->dev;
c31c4ba3 699 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed
EE		 700 struct intel_connector *intel_connector;
701 struct intel_encoder *intel_encoder;
702 struct drm_connector *connector;
703 unsigned long irqflags;
704 bool hpd_disabled = false;
321a1b30 705 bool changed = false;
142e2398 706 u32 hpd_event_bits;
4ef69c7a 707
52d7eced
DV		 708 /* HPD irq before everything is fully set up. */
709 if (!dev_priv->enable_hotplug_processing)
710 return;
711
a65e34c7 712 mutex_lock(&mode_config->mutex);
e67189ab
JB		 713 DRM_DEBUG_KMS("running encoder hotplug functions\n");
714
cd569aed 715 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
142e2398
EE		 716
717 hpd_event_bits = dev_priv->hpd_event_bits;
718 dev_priv->hpd_event_bits = 0;
cd569aed
EE		 719 list_for_each_entry(connector, &mode_config->connector_list, head) {
720 intel_connector = to_intel_connector(connector);
721 intel_encoder = intel_connector->encoder;
722 if (intel_encoder->hpd_pin > HPD_NONE &&
723 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
724 connector->polled == DRM_CONNECTOR_POLL_HPD) {
725 DRM_INFO("HPD interrupt storm detected on connector %s: "
726 "switching from hotplug detection to polling\n",
727 drm_get_connector_name(connector));
728 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
729 connector->polled = DRM_CONNECTOR_POLL_CONNECT
730 | DRM_CONNECTOR_POLL_DISCONNECT;
731 hpd_disabled = true;
732 }
142e2398
EE		 733 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
734 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
735 drm_get_connector_name(connector), intel_encoder->hpd_pin);
736 }
cd569aed
EE		 737 }
738 /* if there were no outputs to poll, poll was disabled,
739 * therefore make sure it's enabled when disabling HPD on
740 * some connectors */
ac4c16c5 741 if (hpd_disabled) {
cd569aed 742 drm_kms_helper_poll_enable(dev);
ac4c16c5
EE		 743 mod_timer(&dev_priv->hotplug_reenable_timer,
744 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
745 }
cd569aed
EE		 746
747 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
748
321a1b30
EE		 749 list_for_each_entry(connector, &mode_config->connector_list, head) {
750 intel_connector = to_intel_connector(connector);
751 intel_encoder = intel_connector->encoder;
752 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
753 if (intel_encoder->hot_plug)
754 intel_encoder->hot_plug(intel_encoder);
755 if (intel_hpd_irq_event(dev, connector))
756 changed = true;
757 }
758 }
40ee3381
KP		 759 mutex_unlock(&mode_config->mutex);
760
321a1b30
EE		 761 if (changed)
762 drm_kms_helper_hotplug_event(dev);
5ca58282
JB		 763}
764
d0ecd7e2 765static void ironlake_rps_change_irq_handler(struct drm_device *dev)
f97108d1
JB		 766{
767 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 768 u32 busy_up, busy_down, max_avg, min_avg;
9270388e 769 u8 new_delay;
9270388e 770
d0ecd7e2 771 spin_lock(&mchdev_lock);
f97108d1 772
73edd18f
DV		 773 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
774
20e4d407 775 new_delay = dev_priv->ips.cur_delay;
9270388e 776
7648fa99 777 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 778 busy_up = I915_READ(RCPREVBSYTUPAVG);
779 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 780 max_avg = I915_READ(RCBMAXAVG);
781 min_avg = I915_READ(RCBMINAVG);
782
783 /* Handle RCS change request from hw */
b5b72e89 784 if (busy_up > max_avg) {
20e4d407
DV		 785 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
786 new_delay = dev_priv->ips.cur_delay - 1;
787 if (new_delay < dev_priv->ips.max_delay)
788 new_delay = dev_priv->ips.max_delay;
b5b72e89 789 } else if (busy_down < min_avg) {
20e4d407
DV		 790 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
791 new_delay = dev_priv->ips.cur_delay + 1;
792 if (new_delay > dev_priv->ips.min_delay)
793 new_delay = dev_priv->ips.min_delay;
f97108d1
JB		 794 }
795
7648fa99 796 if (ironlake_set_drps(dev, new_delay))
20e4d407 797 dev_priv->ips.cur_delay = new_delay;
f97108d1 798
d0ecd7e2 799 spin_unlock(&mchdev_lock);
9270388e 800
f97108d1
JB		 801 return;
802}
803
549f7365
CW		 804static void notify_ring(struct drm_device *dev,
805 struct intel_ring_buffer *ring)
806{
475553de
CW		 807 if (ring->obj == NULL)
808 return;
809
b2eadbc8 810 trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
9862e600 811
549f7365 812 wake_up_all(&ring->irq_queue);
10cd45b6 813 i915_queue_hangcheck(dev);
549f7365
CW		 814}
815
4912d041 816static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 817{
4912d041 818 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
c6a828d3 819 rps.work);
edbfdb45 820 u32 pm_iir;
7b9e0ae6 821 u8 new_delay;
4912d041 822
59cdb63d 823 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3
DV		 824 pm_iir = dev_priv->rps.pm_iir;
825 dev_priv->rps.pm_iir = 0;
4848405c 826 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
edbfdb45 827 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
59cdb63d 828 spin_unlock_irq(&dev_priv->irq_lock);
3b8d8d91 829
60611c13
PZ		 830 /* Make sure we didn't queue anything we're not going to process. */
831 WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS);
832
4848405c 833 if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
3b8d8d91
JB		 834 return;
835
4fc688ce 836 mutex_lock(&dev_priv->rps.hw_lock);
7b9e0ae6 837
7425034a 838 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
c6a828d3 839 new_delay = dev_priv->rps.cur_delay + 1;
7425034a
VS		 840
841 /*
842 * For better performance, jump directly
843 * to RPe if we're below it.
844 */
845 if (IS_VALLEYVIEW(dev_priv->dev) &&
846 dev_priv->rps.cur_delay < dev_priv->rps.rpe_delay)
847 new_delay = dev_priv->rps.rpe_delay;
848 } else
c6a828d3 849 new_delay = dev_priv->rps.cur_delay - 1;
3b8d8d91 850
79249636
BW		 851 /* sysfs frequency interfaces may have snuck in while servicing the
852 * interrupt
853 */
d8289c9e
VS		 854 if (new_delay >= dev_priv->rps.min_delay &&
855 new_delay <= dev_priv->rps.max_delay) {
0a073b84
JB		 856 if (IS_VALLEYVIEW(dev_priv->dev))
857 valleyview_set_rps(dev_priv->dev, new_delay);
858 else
859 gen6_set_rps(dev_priv->dev, new_delay);
79249636 860 }
3b8d8d91 861
52ceb908
JB		 862 if (IS_VALLEYVIEW(dev_priv->dev)) {
863 /*
864 * On VLV, when we enter RC6 we may not be at the minimum
865 * voltage level, so arm a timer to check. It should only
866 * fire when there's activity or once after we've entered
867 * RC6, and then won't be re-armed until the next RPS interrupt.
868 */
869 mod_delayed_work(dev_priv->wq, &dev_priv->rps.vlv_work,
870 msecs_to_jiffies(100));
871 }
872
4fc688ce 873 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91
JB		 874}
875
e3689190
BW		 876
877/**
878 * ivybridge_parity_work - Workqueue called when a parity error interrupt
879 * occurred.
880 * @work: workqueue struct
881 *
882 * Doesn't actually do anything except notify userspace. As a consequence of
883 * this event, userspace should try to remap the bad rows since statistically
884 * it is likely the same row is more likely to go bad again.
885 */
886static void ivybridge_parity_work(struct work_struct *work)
887{
888 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
a4da4fa4 889 l3_parity.error_work);
e3689190
BW		 890 u32 error_status, row, bank, subbank;
891 char *parity_event[5];
892 uint32_t misccpctl;
893 unsigned long flags;
894
895 /* We must turn off DOP level clock gating to access the L3 registers.
896 * In order to prevent a get/put style interface, acquire struct mutex
897 * any time we access those registers.
898 */
899 mutex_lock(&dev_priv->dev->struct_mutex);
900
901 misccpctl = I915_READ(GEN7_MISCCPCTL);
902 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
903 POSTING_READ(GEN7_MISCCPCTL);
904
905 error_status = I915_READ(GEN7_L3CDERRST1);
906 row = GEN7_PARITY_ERROR_ROW(error_status);
907 bank = GEN7_PARITY_ERROR_BANK(error_status);
908 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
909
910 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
911 GEN7_L3CDERRST1_ENABLE);
912 POSTING_READ(GEN7_L3CDERRST1);
913
914 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
915
916 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 917 ilk_enable_gt_irq(dev_priv, GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
e3689190
BW		 918 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
919
920 mutex_unlock(&dev_priv->dev->struct_mutex);
921
cce723ed 922 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
e3689190
BW		 923 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
924 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
925 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
926 parity_event[4] = NULL;
927
928 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
929 KOBJ_CHANGE, parity_event);
930
931 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
932 row, bank, subbank);
933
934 kfree(parity_event[3]);
935 kfree(parity_event[2]);
936 kfree(parity_event[1]);
937}
938
d0ecd7e2 939static void ivybridge_parity_error_irq_handler(struct drm_device *dev)
e3689190
BW		 940{
941 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e3689190 942
e1ef7cc2 943 if (!HAS_L3_GPU_CACHE(dev))
e3689190
BW		 944 return;
945
d0ecd7e2 946 spin_lock(&dev_priv->irq_lock);
43eaea13 947 ilk_disable_gt_irq(dev_priv, GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
d0ecd7e2 948 spin_unlock(&dev_priv->irq_lock);
e3689190 949
a4da4fa4 950 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
e3689190
BW		 951}
952
f1af8fc1
PZ		 953static void ilk_gt_irq_handler(struct drm_device *dev,
954 struct drm_i915_private *dev_priv,
955 u32 gt_iir)
956{
957 if (gt_iir &
958 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
959 notify_ring(dev, &dev_priv->ring[RCS]);
960 if (gt_iir & ILK_BSD_USER_INTERRUPT)
961 notify_ring(dev, &dev_priv->ring[VCS]);
962}
963
e7b4c6b1
DV		 964static void snb_gt_irq_handler(struct drm_device *dev,
965 struct drm_i915_private *dev_priv,
966 u32 gt_iir)
967{
968
cc609d5d
BW		 969 if (gt_iir &
970 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
e7b4c6b1 971 notify_ring(dev, &dev_priv->ring[RCS]);
cc609d5d 972 if (gt_iir & GT_BSD_USER_INTERRUPT)
e7b4c6b1 973 notify_ring(dev, &dev_priv->ring[VCS]);
cc609d5d 974 if (gt_iir & GT_BLT_USER_INTERRUPT)
e7b4c6b1
DV		 975 notify_ring(dev, &dev_priv->ring[BCS]);
976
cc609d5d
BW		 977 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
978 GT_BSD_CS_ERROR_INTERRUPT |
979 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
e7b4c6b1
DV		 980 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
981 i915_handle_error(dev, false);
982 }
e3689190 983
cc609d5d 984 if (gt_iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
d0ecd7e2 985 ivybridge_parity_error_irq_handler(dev);
e7b4c6b1
DV		 986}
987
b543fb04
EE		 988#define HPD_STORM_DETECT_PERIOD 1000
989#define HPD_STORM_THRESHOLD 5
990
10a504de 991static inline void intel_hpd_irq_handler(struct drm_device *dev,
22062dba
DV		 992 u32 hotplug_trigger,
993 const u32 *hpd)
b543fb04
EE		 994{
995 drm_i915_private_t *dev_priv = dev->dev_private;
b543fb04 996 int i;
10a504de 997 bool storm_detected = false;
b543fb04 998
91d131d2
DV		 999 if (!hotplug_trigger)
1000 return;
1001
b5ea2d56 1002 spin_lock(&dev_priv->irq_lock);
b543fb04 1003 for (i = 1; i < HPD_NUM_PINS; i++) {
821450c6 1004
b8f102e8
EE		 1005 WARN(((hpd[i] & hotplug_trigger) &&
1006 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED),
1007 "Received HPD interrupt although disabled\n");
1008
b543fb04
EE		 1009 if (!(hpd[i] & hotplug_trigger) ||
1010 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1011 continue;
1012
bc5ead8c 1013 dev_priv->hpd_event_bits |= (1 << i);
b543fb04
EE		 1014 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1015 dev_priv->hpd_stats[i].hpd_last_jiffies
1016 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1017 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1018 dev_priv->hpd_stats[i].hpd_cnt = 0;
b8f102e8 1019 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
b543fb04
EE		 1020 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1021 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
142e2398 1022 dev_priv->hpd_event_bits &= ~(1 << i);
b543fb04 1023 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
10a504de 1024 storm_detected = true;
b543fb04
EE		 1025 } else {
1026 dev_priv->hpd_stats[i].hpd_cnt++;
b8f102e8
EE		 1027 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1028 dev_priv->hpd_stats[i].hpd_cnt);
b543fb04
EE		 1029 }
1030 }
1031
10a504de
DV		 1032 if (storm_detected)
1033 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 1034 spin_unlock(&dev_priv->irq_lock);
5876fa0d 1035
645416f5
DV		 1036 /*
1037 * Our hotplug handler can grab modeset locks (by calling down into the
1038 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1039 * queue for otherwise the flush_work in the pageflip code will
1040 * deadlock.
1041 */
1042 schedule_work(&dev_priv->hotplug_work);
b543fb04
EE		 1043}
1044
515ac2bb
DV		 1045static void gmbus_irq_handler(struct drm_device *dev)
1046{
28c70f16
DV		 1047 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1048
28c70f16 1049 wake_up_all(&dev_priv->gmbus_wait_queue);
515ac2bb
DV		 1050}
1051
ce99c256
DV		 1052static void dp_aux_irq_handler(struct drm_device *dev)
1053{
9ee32fea
DV		 1054 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1055
9ee32fea 1056 wake_up_all(&dev_priv->gmbus_wait_queue);
ce99c256
DV		 1057}
1058
1403c0d4
PZ		 1059/* The RPS events need forcewake, so we add them to a work queue and mask their
1060 * IMR bits until the work is done. Other interrupts can be processed without
1061 * the work queue. */
1062static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
baf02a1f 1063{
41a05a3a 1064 if (pm_iir & GEN6_PM_RPS_EVENTS) {
59cdb63d 1065 spin_lock(&dev_priv->irq_lock);
41a05a3a 1066 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
4d3b3d5f 1067 snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS);
59cdb63d 1068 spin_unlock(&dev_priv->irq_lock);
2adbee62
DV		 1069
1070 queue_work(dev_priv->wq, &dev_priv->rps.work);
baf02a1f 1071 }
baf02a1f 1072
1403c0d4
PZ		 1073 if (HAS_VEBOX(dev_priv->dev)) {
1074 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1075 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
12638c57 1076
1403c0d4
PZ		 1077 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1078 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
1079 i915_handle_error(dev_priv->dev, false);
1080 }
12638c57 1081 }
baf02a1f
BW		 1082}
1083
ff1f525e 1084static irqreturn_t valleyview_irq_handler(int irq, void *arg)
7e231dbe
JB		 1085{
1086 struct drm_device *dev = (struct drm_device *) arg;
1087 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1088 u32 iir, gt_iir, pm_iir;
1089 irqreturn_t ret = IRQ_NONE;
1090 unsigned long irqflags;
1091 int pipe;
1092 u32 pipe_stats[I915_MAX_PIPES];
7e231dbe
JB		 1093
1094 atomic_inc(&dev_priv->irq_received);
1095
7e231dbe
JB		 1096 while (true) {
1097 iir = I915_READ(VLV_IIR);
1098 gt_iir = I915_READ(GTIIR);
1099 pm_iir = I915_READ(GEN6_PMIIR);
1100
1101 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1102 goto out;
1103
1104 ret = IRQ_HANDLED;
1105
e7b4c6b1 1106 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 1107
1108 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1109 for_each_pipe(pipe) {
1110 int reg = PIPESTAT(pipe);
1111 pipe_stats[pipe] = I915_READ(reg);
1112
1113 /*
1114 * Clear the PIPE*STAT regs before the IIR
1115 */
1116 if (pipe_stats[pipe] & 0x8000ffff) {
1117 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1118 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1119 pipe_name(pipe));
1120 I915_WRITE(reg, pipe_stats[pipe]);
1121 }
1122 }
1123 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1124
31acc7f5
JB		 1125 for_each_pipe(pipe) {
1126 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1127 drm_handle_vblank(dev, pipe);
1128
1129 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
1130 intel_prepare_page_flip(dev, pipe);
1131 intel_finish_page_flip(dev, pipe);
1132 }
1133 }
1134
7e231dbe
JB		 1135 /* Consume port. Then clear IIR or we'll miss events */
1136 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1137 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04 1138 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
7e231dbe
JB		 1139
1140 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1141 hotplug_status);
91d131d2
DV		 1142
1143 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1144
7e231dbe
JB		 1145 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1146 I915_READ(PORT_HOTPLUG_STAT);
1147 }
1148
515ac2bb
DV		 1149 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1150 gmbus_irq_handler(dev);
7e231dbe 1151
60611c13 1152 if (pm_iir)
d0ecd7e2 1153 gen6_rps_irq_handler(dev_priv, pm_iir);
7e231dbe
JB		 1154
1155 I915_WRITE(GTIIR, gt_iir);
1156 I915_WRITE(GEN6_PMIIR, pm_iir);
1157 I915_WRITE(VLV_IIR, iir);
1158 }
1159
1160out:
1161 return ret;
1162}
1163
23e81d69 1164static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 1165{
1166 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 1167 int pipe;
b543fb04 1168 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
776ad806 1169
91d131d2
DV		 1170 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1171
cfc33bf7
VS		 1172 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1173 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1174 SDE_AUDIO_POWER_SHIFT);
776ad806 1175 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
cfc33bf7
VS		 1176 port_name(port));
1177 }
776ad806 1178
ce99c256
DV		 1179 if (pch_iir & SDE_AUX_MASK)
1180 dp_aux_irq_handler(dev);
1181
776ad806 1182 if (pch_iir & SDE_GMBUS)
515ac2bb 1183 gmbus_irq_handler(dev);
776ad806
JB		 1184
1185 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1186 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1187
1188 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1189 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1190
1191 if (pch_iir & SDE_POISON)
1192 DRM_ERROR("PCH poison interrupt\n");
1193
9db4a9c7
JB		 1194 if (pch_iir & SDE_FDI_MASK)
1195 for_each_pipe(pipe)
1196 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1197 pipe_name(pipe),
1198 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 1199
1200 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1201 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1202
1203 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1204 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1205
776ad806 1206 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
8664281b
PZ		 1207 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1208 false))
1209 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1210
1211 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1212 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1213 false))
1214 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1215}
1216
1217static void ivb_err_int_handler(struct drm_device *dev)
1218{
1219 struct drm_i915_private *dev_priv = dev->dev_private;
1220 u32 err_int = I915_READ(GEN7_ERR_INT);
1221
de032bf4
PZ		 1222 if (err_int & ERR_INT_POISON)
1223 DRM_ERROR("Poison interrupt\n");
1224
8664281b
PZ		 1225 if (err_int & ERR_INT_FIFO_UNDERRUN_A)
1226 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1227 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1228
1229 if (err_int & ERR_INT_FIFO_UNDERRUN_B)
1230 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1231 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1232
1233 if (err_int & ERR_INT_FIFO_UNDERRUN_C)
1234 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false))
1235 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1236
1237 I915_WRITE(GEN7_ERR_INT, err_int);
1238}
1239
1240static void cpt_serr_int_handler(struct drm_device *dev)
1241{
1242 struct drm_i915_private *dev_priv = dev->dev_private;
1243 u32 serr_int = I915_READ(SERR_INT);
1244
de032bf4
PZ		 1245 if (serr_int & SERR_INT_POISON)
1246 DRM_ERROR("PCH poison interrupt\n");
1247
8664281b
PZ		 1248 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1249 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1250 false))
1251 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1252
1253 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1254 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1255 false))
1256 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1257
1258 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1259 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1260 false))
1261 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1262
1263 I915_WRITE(SERR_INT, serr_int);
776ad806
JB		 1264}
1265
23e81d69
AJ		 1266static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1267{
1268 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1269 int pipe;
b543fb04 1270 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
23e81d69 1271
91d131d2
DV		 1272 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1273
cfc33bf7
VS		 1274 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1275 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1276 SDE_AUDIO_POWER_SHIFT_CPT);
1277 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1278 port_name(port));
1279 }
23e81d69
AJ		 1280
1281 if (pch_iir & SDE_AUX_MASK_CPT)
ce99c256 1282 dp_aux_irq_handler(dev);
23e81d69
AJ		 1283
1284 if (pch_iir & SDE_GMBUS_CPT)
515ac2bb 1285 gmbus_irq_handler(dev);
23e81d69
AJ		 1286
1287 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1288 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1289
1290 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1291 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1292
1293 if (pch_iir & SDE_FDI_MASK_CPT)
1294 for_each_pipe(pipe)
1295 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1296 pipe_name(pipe),
1297 I915_READ(FDI_RX_IIR(pipe)));
8664281b
PZ		 1298
1299 if (pch_iir & SDE_ERROR_CPT)
1300 cpt_serr_int_handler(dev);
23e81d69
AJ		 1301}
1302
c008bc6e
PZ		 1303static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1304{
1305 struct drm_i915_private *dev_priv = dev->dev_private;
1306
1307 if (de_iir & DE_AUX_CHANNEL_A)
1308 dp_aux_irq_handler(dev);
1309
1310 if (de_iir & DE_GSE)
1311 intel_opregion_asle_intr(dev);
1312
1313 if (de_iir & DE_PIPEA_VBLANK)
1314 drm_handle_vblank(dev, 0);
1315
1316 if (de_iir & DE_PIPEB_VBLANK)
1317 drm_handle_vblank(dev, 1);
1318
1319 if (de_iir & DE_POISON)
1320 DRM_ERROR("Poison interrupt\n");
1321
1322 if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
1323 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1324 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1325
1326 if (de_iir & DE_PIPEB_FIFO_UNDERRUN)
1327 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1328 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1329
1330 if (de_iir & DE_PLANEA_FLIP_DONE) {
1331 intel_prepare_page_flip(dev, 0);
1332 intel_finish_page_flip_plane(dev, 0);
1333 }
1334
1335 if (de_iir & DE_PLANEB_FLIP_DONE) {
1336 intel_prepare_page_flip(dev, 1);
1337 intel_finish_page_flip_plane(dev, 1);
1338 }
1339
1340 /* check event from PCH */
1341 if (de_iir & DE_PCH_EVENT) {
1342 u32 pch_iir = I915_READ(SDEIIR);
1343
1344 if (HAS_PCH_CPT(dev))
1345 cpt_irq_handler(dev, pch_iir);
1346 else
1347 ibx_irq_handler(dev, pch_iir);
1348
1349 /* should clear PCH hotplug event before clear CPU irq */
1350 I915_WRITE(SDEIIR, pch_iir);
1351 }
1352
1353 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1354 ironlake_rps_change_irq_handler(dev);
1355}
1356
9719fb98
PZ		 1357static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
1358{
1359 struct drm_i915_private *dev_priv = dev->dev_private;
1360 int i;
1361
1362 if (de_iir & DE_ERR_INT_IVB)
1363 ivb_err_int_handler(dev);
1364
1365 if (de_iir & DE_AUX_CHANNEL_A_IVB)
1366 dp_aux_irq_handler(dev);
1367
1368 if (de_iir & DE_GSE_IVB)
1369 intel_opregion_asle_intr(dev);
1370
1371 for (i = 0; i < 3; i++) {
1372 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
1373 drm_handle_vblank(dev, i);
1374 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
1375 intel_prepare_page_flip(dev, i);
1376 intel_finish_page_flip_plane(dev, i);
1377 }
1378 }
1379
1380 /* check event from PCH */
1381 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1382 u32 pch_iir = I915_READ(SDEIIR);
1383
1384 cpt_irq_handler(dev, pch_iir);
1385
1386 /* clear PCH hotplug event before clear CPU irq */
1387 I915_WRITE(SDEIIR, pch_iir);
1388 }
1389}
1390
f1af8fc1 1391static irqreturn_t ironlake_irq_handler(int irq, void *arg)
b1f14ad0
JB		 1392{
1393 struct drm_device *dev = (struct drm_device *) arg;
1394 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
f1af8fc1 1395 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
0e43406b 1396 irqreturn_t ret = IRQ_NONE;
333a8204 1397 bool err_int_reenable = false;
b1f14ad0
JB		 1398
1399 atomic_inc(&dev_priv->irq_received);
1400
8664281b
PZ		 1401 /* We get interrupts on unclaimed registers, so check for this before we
1402 * do any I915_{READ,WRITE}. */
907b28c5 1403 intel_uncore_check_errors(dev);
8664281b 1404
b1f14ad0
JB		 1405 /* disable master interrupt before clearing iir */
1406 de_ier = I915_READ(DEIER);
1407 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
23a78516 1408 POSTING_READ(DEIER);
b1f14ad0 1409
44498aea
PZ		 1410 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1411 * interrupts will will be stored on its back queue, and then we'll be
1412 * able to process them after we restore SDEIER (as soon as we restore
1413 * it, we'll get an interrupt if SDEIIR still has something to process
1414 * due to its back queue). */
ab5c608b
BW		 1415 if (!HAS_PCH_NOP(dev)) {
1416 sde_ier = I915_READ(SDEIER);
1417 I915_WRITE(SDEIER, 0);
1418 POSTING_READ(SDEIER);
1419 }
44498aea 1420
8664281b
PZ		 1421 /* On Haswell, also mask ERR_INT because we don't want to risk
1422 * generating "unclaimed register" interrupts from inside the interrupt
1423 * handler. */
4bc9d430
DV		 1424 if (IS_HASWELL(dev)) {
1425 spin_lock(&dev_priv->irq_lock);
333a8204
PZ		 1426 err_int_reenable = ~dev_priv->irq_mask & DE_ERR_INT_IVB;
1427 if (err_int_reenable)
1428 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
4bc9d430
DV		 1429 spin_unlock(&dev_priv->irq_lock);
1430 }
8664281b 1431
b1f14ad0 1432 gt_iir = I915_READ(GTIIR);
0e43406b 1433 if (gt_iir) {
d8fc8a47 1434 if (INTEL_INFO(dev)->gen >= 6)
f1af8fc1 1435 snb_gt_irq_handler(dev, dev_priv, gt_iir);
d8fc8a47
PZ		 1436 else
1437 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
0e43406b
CW		 1438 I915_WRITE(GTIIR, gt_iir);
1439 ret = IRQ_HANDLED;
b1f14ad0
JB		 1440 }
1441
0e43406b
CW		 1442 de_iir = I915_READ(DEIIR);
1443 if (de_iir) {
f1af8fc1
PZ		 1444 if (INTEL_INFO(dev)->gen >= 7)
1445 ivb_display_irq_handler(dev, de_iir);
1446 else
1447 ilk_display_irq_handler(dev, de_iir);
0e43406b
CW		 1448 I915_WRITE(DEIIR, de_iir);
1449 ret = IRQ_HANDLED;
b1f14ad0
JB		 1450 }
1451
f1af8fc1
PZ		 1452 if (INTEL_INFO(dev)->gen >= 6) {
1453 u32 pm_iir = I915_READ(GEN6_PMIIR);
1454 if (pm_iir) {
1403c0d4 1455 gen6_rps_irq_handler(dev_priv, pm_iir);
f1af8fc1
PZ		 1456 I915_WRITE(GEN6_PMIIR, pm_iir);
1457 ret = IRQ_HANDLED;
1458 }
0e43406b 1459 }
b1f14ad0 1460
333a8204 1461 if (err_int_reenable) {
4bc9d430
DV		 1462 spin_lock(&dev_priv->irq_lock);
1463 if (ivb_can_enable_err_int(dev))
1464 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
1465 spin_unlock(&dev_priv->irq_lock);
1466 }
8664281b 1467
b1f14ad0
JB		 1468 I915_WRITE(DEIER, de_ier);
1469 POSTING_READ(DEIER);
ab5c608b
BW		 1470 if (!HAS_PCH_NOP(dev)) {
1471 I915_WRITE(SDEIER, sde_ier);
1472 POSTING_READ(SDEIER);
1473 }
b1f14ad0
JB		 1474
1475 return ret;
1476}
1477
8a905236
JB		 1478/**
1479 * i915_error_work_func - do process context error handling work
1480 * @work: work struct
1481 *
1482 * Fire an error uevent so userspace can see that a hang or error
1483 * was detected.
1484 */
1485static void i915_error_work_func(struct work_struct *work)
1486{
1f83fee0
DV		 1487 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
1488 work);
1489 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1490 gpu_error);
8a905236 1491 struct drm_device *dev = dev_priv->dev;
f69061be 1492 struct intel_ring_buffer *ring;
cce723ed
BW		 1493 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1494 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1495 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
f69061be 1496 int i, ret;
8a905236 1497
f316a42c
BG		 1498 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
1499
7db0ba24
DV		 1500 /*
1501 * Note that there's only one work item which does gpu resets, so we
1502 * need not worry about concurrent gpu resets potentially incrementing
1503 * error->reset_counter twice. We only need to take care of another
1504 * racing irq/hangcheck declaring the gpu dead for a second time. A
1505 * quick check for that is good enough: schedule_work ensures the
1506 * correct ordering between hang detection and this work item, and since
1507 * the reset in-progress bit is only ever set by code outside of this
1508 * work we don't need to worry about any other races.
1509 */
1510 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
f803aa55 1511 DRM_DEBUG_DRIVER("resetting chip\n");
7db0ba24
DV		 1512 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
1513 reset_event);
1f83fee0 1514
f69061be
DV		 1515 ret = i915_reset(dev);
1516
1517 if (ret == 0) {
1518 /*
1519 * After all the gem state is reset, increment the reset
1520 * counter and wake up everyone waiting for the reset to
1521 * complete.
1522 *
1523 * Since unlock operations are a one-sided barrier only,
1524 * we need to insert a barrier here to order any seqno
1525 * updates before
1526 * the counter increment.
1527 */
1528 smp_mb__before_atomic_inc();
1529 atomic_inc(&dev_priv->gpu_error.reset_counter);
1530
1531 kobject_uevent_env(&dev->primary->kdev.kobj,
1532 KOBJ_CHANGE, reset_done_event);
1f83fee0
DV		 1533 } else {
1534 atomic_set(&error->reset_counter, I915_WEDGED);
f316a42c 1535 }
1f83fee0 1536
f69061be
DV		 1537 for_each_ring(ring, dev_priv, i)
1538 wake_up_all(&ring->irq_queue);
1539
96a02917
VS		 1540 intel_display_handle_reset(dev);
1541
1f83fee0 1542 wake_up_all(&dev_priv->gpu_error.reset_queue);
f316a42c 1543 }
8a905236
JB		 1544}
1545
35aed2e6 1546static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1547{
1548 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 1549 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 1550 u32 eir = I915_READ(EIR);
050ee91f 1551 int pipe, i;
8a905236 1552
35aed2e6
CW		 1553 if (!eir)
1554 return;
8a905236 1555
a70491cc 1556 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 1557
bd9854f9
BW		 1558 i915_get_extra_instdone(dev, instdone);
1559
8a905236
JB		 1560 if (IS_G4X(dev)) {
1561 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1562 u32 ipeir = I915_READ(IPEIR_I965);
1563
a70491cc
JP		 1564 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1565 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 1566 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1567 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 1568 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1569 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1570 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1571 POSTING_READ(IPEIR_I965);
8a905236
JB		 1572 }
1573 if (eir & GM45_ERROR_PAGE_TABLE) {
1574 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1575 pr_err("page table error\n");
1576 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1577 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1578 POSTING_READ(PGTBL_ER);
8a905236
JB		 1579 }
1580 }
1581
a6c45cf0 1582 if (!IS_GEN2(dev)) {
8a905236
JB		 1583 if (eir & I915_ERROR_PAGE_TABLE) {
1584 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1585 pr_err("page table error\n");
1586 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1587 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1588 POSTING_READ(PGTBL_ER);
8a905236
JB		 1589 }
1590 }
1591
1592 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 1593 pr_err("memory refresh error:\n");
9db4a9c7 1594 for_each_pipe(pipe)
a70491cc 1595 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 1596 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 1597 /* pipestat has already been acked */
1598 }
1599 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 1600 pr_err("instruction error\n");
1601 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 1602 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1603 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 1604 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 1605 u32 ipeir = I915_READ(IPEIR);
1606
a70491cc
JP		 1607 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1608 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 1609 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 1610 I915_WRITE(IPEIR, ipeir);
3143a2bf 1611 POSTING_READ(IPEIR);
8a905236
JB		 1612 } else {
1613 u32 ipeir = I915_READ(IPEIR_I965);
1614
a70491cc
JP		 1615 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1616 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 1617 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1618 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1619 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1620 POSTING_READ(IPEIR_I965);
8a905236
JB		 1621 }
1622 }
1623
1624 I915_WRITE(EIR, eir);
3143a2bf 1625 POSTING_READ(EIR);
8a905236
JB		 1626 eir = I915_READ(EIR);
1627 if (eir) {
1628 /*
1629 * some errors might have become stuck,
1630 * mask them.
1631 */
1632 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1633 I915_WRITE(EMR, I915_READ(EMR) | eir);
1634 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1635 }
35aed2e6
CW		 1636}
1637
1638/**
1639 * i915_handle_error - handle an error interrupt
1640 * @dev: drm device
1641 *
1642 * Do some basic checking of regsiter state at error interrupt time and
1643 * dump it to the syslog. Also call i915_capture_error_state() to make
1644 * sure we get a record and make it available in debugfs. Fire a uevent
1645 * so userspace knows something bad happened (should trigger collection
1646 * of a ring dump etc.).
1647 */
527f9e90 1648void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 1649{
1650 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513
CW		 1651 struct intel_ring_buffer *ring;
1652 int i;
35aed2e6
CW		 1653
1654 i915_capture_error_state(dev);
1655 i915_report_and_clear_eir(dev);
8a905236 1656
ba1234d1 1657 if (wedged) {
f69061be
DV		 1658 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
1659 &dev_priv->gpu_error.reset_counter);
ba1234d1 1660
11ed50ec 1661 /*
1f83fee0
DV		 1662 * Wakeup waiting processes so that the reset work item
1663 * doesn't deadlock trying to grab various locks.
11ed50ec 1664 */
b4519513
CW		 1665 for_each_ring(ring, dev_priv, i)
1666 wake_up_all(&ring->irq_queue);
11ed50ec
BG		 1667 }
1668
99584db3 1669 queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
8a905236
JB		 1670}
1671
21ad8330 1672static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
4e5359cd
SF		 1673{
1674 drm_i915_private_t *dev_priv = dev->dev_private;
1675 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1676 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 1677 struct drm_i915_gem_object *obj;
4e5359cd
SF		 1678 struct intel_unpin_work *work;
1679 unsigned long flags;
1680 bool stall_detected;
1681
1682 /* Ignore early vblank irqs */
1683 if (intel_crtc == NULL)
1684 return;
1685
1686 spin_lock_irqsave(&dev->event_lock, flags);
1687 work = intel_crtc->unpin_work;
1688
e7d841ca
CW		 1689 if (work == NULL ||
1690 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
1691 !work->enable_stall_check) {
4e5359cd
SF		 1692 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1693 spin_unlock_irqrestore(&dev->event_lock, flags);
1694 return;
1695 }
1696
1697 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 1698 obj = work->pending_flip_obj;
a6c45cf0 1699 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 1700 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545 1701 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
f343c5f6 1702 i915_gem_obj_ggtt_offset(obj);
4e5359cd 1703 } else {
9db4a9c7 1704 int dspaddr = DSPADDR(intel_crtc->plane);
f343c5f6 1705 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
01f2c773 1706 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 1707 crtc->x * crtc->fb->bits_per_pixel/8);
1708 }
1709
1710 spin_unlock_irqrestore(&dev->event_lock, flags);
1711
1712 if (stall_detected) {
1713 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1714 intel_prepare_page_flip(dev, intel_crtc->plane);
1715 }
1716}
1717
42f52ef8
KP		 1718/* Called from drm generic code, passed 'crtc' which
1719 * we use as a pipe index
1720 */
f71d4af4 1721static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1722{
1723 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1724 unsigned long irqflags;
71e0ffa5 1725
5eddb70b 1726 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 1727 return -EINVAL;
0a3e67a4 1728
1ec14ad3 1729 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 1730 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 1731 i915_enable_pipestat(dev_priv, pipe,
1732 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 1733 else
7c463586
KP		 1734 i915_enable_pipestat(dev_priv, pipe,
1735 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 1736
1737 /* maintain vblank delivery even in deep C-states */
1738 if (dev_priv->info->gen == 3)
6b26c86d 1739 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 1740 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 1741
0a3e67a4
JB		 1742 return 0;
1743}
1744
f71d4af4 1745static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1746{
1747 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1748 unsigned long irqflags;
b518421f
PZ		 1749 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
1750 DE_PIPE_VBLANK_ILK(pipe);
f796cf8f
JB		 1751
1752 if (!i915_pipe_enabled(dev, pipe))
1753 return -EINVAL;
1754
1755 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b518421f 1756 ironlake_enable_display_irq(dev_priv, bit);
b1f14ad0
JB		 1757 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1758
1759 return 0;
1760}
1761
7e231dbe
JB		 1762static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1763{
1764 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1765 unsigned long irqflags;
31acc7f5 1766 u32 imr;
7e231dbe
JB		 1767
1768 if (!i915_pipe_enabled(dev, pipe))
1769 return -EINVAL;
1770
1771 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7e231dbe 1772 imr = I915_READ(VLV_IMR);
31acc7f5 1773 if (pipe == 0)
7e231dbe 1774 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1775 else
7e231dbe 1776 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1777 I915_WRITE(VLV_IMR, imr);
31acc7f5
JB		 1778 i915_enable_pipestat(dev_priv, pipe,
1779 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe
JB		 1780 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1781
1782 return 0;
1783}
1784
42f52ef8
KP		 1785/* Called from drm generic code, passed 'crtc' which
1786 * we use as a pipe index
1787 */
f71d4af4 1788static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1789{
1790 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1791 unsigned long irqflags;
0a3e67a4 1792
1ec14ad3 1793 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 1794 if (dev_priv->info->gen == 3)
6b26c86d 1795 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 1796
f796cf8f
JB		 1797 i915_disable_pipestat(dev_priv, pipe,
1798 PIPE_VBLANK_INTERRUPT_ENABLE |
1799 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1800 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1801}
1802
f71d4af4 1803static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1804{
1805 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1806 unsigned long irqflags;
b518421f
PZ		 1807 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
1808 DE_PIPE_VBLANK_ILK(pipe);
f796cf8f
JB		 1809
1810 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b518421f 1811 ironlake_disable_display_irq(dev_priv, bit);
b1f14ad0
JB		 1812 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1813}
1814
7e231dbe
JB		 1815static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1816{
1817 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1818 unsigned long irqflags;
31acc7f5 1819 u32 imr;
7e231dbe
JB		 1820
1821 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5
JB		 1822 i915_disable_pipestat(dev_priv, pipe,
1823 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe 1824 imr = I915_READ(VLV_IMR);
31acc7f5 1825 if (pipe == 0)
7e231dbe 1826 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1827 else
7e231dbe 1828 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1829 I915_WRITE(VLV_IMR, imr);
7e231dbe
JB		 1830 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1831}
1832
893eead0
CW		 1833static u32
1834ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 1835{
893eead0
CW		 1836 return list_entry(ring->request_list.prev,
1837 struct drm_i915_gem_request, list)->seqno;
1838}
1839
9107e9d2
CW		 1840static bool
1841ring_idle(struct intel_ring_buffer *ring, u32 seqno)
1842{
1843 return (list_empty(&ring->request_list) ||
1844 i915_seqno_passed(seqno, ring_last_seqno(ring)));
f65d9421
BG		 1845}
1846
6274f212
CW		 1847static struct intel_ring_buffer *
1848semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
a24a11e6
CW		 1849{
1850 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6274f212 1851 u32 cmd, ipehr, acthd, acthd_min;
a24a11e6
CW		 1852
1853 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
1854 if ((ipehr & ~(0x3 << 16)) !=
1855 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
6274f212 1856 return NULL;
a24a11e6
CW		 1857
1858 /* ACTHD is likely pointing to the dword after the actual command,
1859 * so scan backwards until we find the MBOX.
1860 */
6274f212 1861 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
a24a11e6
CW		 1862 acthd_min = max((int)acthd - 3 * 4, 0);
1863 do {
1864 cmd = ioread32(ring->virtual_start + acthd);
1865 if (cmd == ipehr)
1866 break;
1867
1868 acthd -= 4;
1869 if (acthd < acthd_min)
6274f212 1870 return NULL;
a24a11e6
CW		 1871 } while (1);
1872
6274f212
CW		 1873 *seqno = ioread32(ring->virtual_start+acthd+4)+1;
1874 return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
a24a11e6
CW		 1875}
1876
6274f212
CW		 1877static int semaphore_passed(struct intel_ring_buffer *ring)
1878{
1879 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1880 struct intel_ring_buffer *signaller;
1881 u32 seqno, ctl;
1882
1883 ring->hangcheck.deadlock = true;
1884
1885 signaller = semaphore_waits_for(ring, &seqno);
1886 if (signaller == NULL || signaller->hangcheck.deadlock)
1887 return -1;
1888
1889 /* cursory check for an unkickable deadlock */
1890 ctl = I915_READ_CTL(signaller);
1891 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
1892 return -1;
1893
1894 return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
1895}
1896
1897static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
1898{
1899 struct intel_ring_buffer *ring;
1900 int i;
1901
1902 for_each_ring(ring, dev_priv, i)
1903 ring->hangcheck.deadlock = false;
1904}
1905
ad8beaea
MK		 1906static enum intel_ring_hangcheck_action
1907ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
1ec14ad3
CW		 1908{
1909 struct drm_device *dev = ring->dev;
1910 struct drm_i915_private *dev_priv = dev->dev_private;
9107e9d2
CW		 1911 u32 tmp;
1912
6274f212 1913 if (ring->hangcheck.acthd != acthd)
f2f4d82f 1914 return HANGCHECK_ACTIVE;
6274f212 1915
9107e9d2 1916 if (IS_GEN2(dev))
f2f4d82f 1917 return HANGCHECK_HUNG;
9107e9d2
CW		 1918
1919 /* Is the chip hanging on a WAIT_FOR_EVENT?
1920 * If so we can simply poke the RB_WAIT bit
1921 * and break the hang. This should work on
1922 * all but the second generation chipsets.
1923 */
1924 tmp = I915_READ_CTL(ring);
1ec14ad3
CW		 1925 if (tmp & RING_WAIT) {
1926 DRM_ERROR("Kicking stuck wait on %s\n",
1927 ring->name);
1928 I915_WRITE_CTL(ring, tmp);
f2f4d82f 1929 return HANGCHECK_KICK;
6274f212
CW		 1930 }
1931
1932 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
1933 switch (semaphore_passed(ring)) {
1934 default:
f2f4d82f 1935 return HANGCHECK_HUNG;
6274f212
CW		 1936 case 1:
1937 DRM_ERROR("Kicking stuck semaphore on %s\n",
1938 ring->name);
1939 I915_WRITE_CTL(ring, tmp);
f2f4d82f 1940 return HANGCHECK_KICK;
6274f212 1941 case 0:
f2f4d82f 1942 return HANGCHECK_WAIT;
6274f212 1943 }
9107e9d2 1944 }
ed5cbb03 1945
f2f4d82f 1946 return HANGCHECK_HUNG;
ed5cbb03
MK		 1947}
1948
f65d9421
BG		 1949/**
1950 * This is called when the chip hasn't reported back with completed
05407ff8
MK		 1951 * batchbuffers in a long time. We keep track per ring seqno progress and
1952 * if there are no progress, hangcheck score for that ring is increased.
1953 * Further, acthd is inspected to see if the ring is stuck. On stuck case
1954 * we kick the ring. If we see no progress on three subsequent calls
1955 * we assume chip is wedged and try to fix it by resetting the chip.
f65d9421 1956 */
a658b5d2 1957static void i915_hangcheck_elapsed(unsigned long data)
f65d9421
BG		 1958{
1959 struct drm_device *dev = (struct drm_device *)data;
1960 drm_i915_private_t *dev_priv = dev->dev_private;
b4519513 1961 struct intel_ring_buffer *ring;
b4519513 1962 int i;
05407ff8 1963 int busy_count = 0, rings_hung = 0;
9107e9d2
CW		 1964 bool stuck[I915_NUM_RINGS] = { 0 };
1965#define BUSY 1
1966#define KICK 5
1967#define HUNG 20
1968#define FIRE 30
893eead0 1969
3e0dc6b0
BW		 1970 if (!i915_enable_hangcheck)
1971 return;
1972
b4519513 1973 for_each_ring(ring, dev_priv, i) {
05407ff8 1974 u32 seqno, acthd;
9107e9d2 1975 bool busy = true;
05407ff8 1976
6274f212
CW		 1977 semaphore_clear_deadlocks(dev_priv);
1978
05407ff8
MK		 1979 seqno = ring->get_seqno(ring, false);
1980 acthd = intel_ring_get_active_head(ring);
b4519513 1981
9107e9d2
CW		 1982 if (ring->hangcheck.seqno == seqno) {
1983 if (ring_idle(ring, seqno)) {
da661464
MK		 1984 ring->hangcheck.action = HANGCHECK_IDLE;
1985
9107e9d2
CW		 1986 if (waitqueue_active(&ring->irq_queue)) {
1987 /* Issue a wake-up to catch stuck h/w. */
1988 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1989 ring->name);
1990 wake_up_all(&ring->irq_queue);
1991 ring->hangcheck.score += HUNG;
1992 } else
1993 busy = false;
05407ff8 1994 } else {
6274f212
CW		 1995 /* We always increment the hangcheck score
1996 * if the ring is busy and still processing
1997 * the same request, so that no single request
1998 * can run indefinitely (such as a chain of
1999 * batches). The only time we do not increment
2000 * the hangcheck score on this ring, if this
2001 * ring is in a legitimate wait for another
2002 * ring. In that case the waiting ring is a
2003 * victim and we want to be sure we catch the
2004 * right culprit. Then every time we do kick
2005 * the ring, add a small increment to the
2006 * score so that we can catch a batch that is
2007 * being repeatedly kicked and so responsible
2008 * for stalling the machine.
2009 */
ad8beaea
MK		 2010 ring->hangcheck.action = ring_stuck(ring,
2011 acthd);
2012
2013 switch (ring->hangcheck.action) {
da661464 2014 case HANGCHECK_IDLE:
f2f4d82f 2015 case HANGCHECK_WAIT:
6274f212 2016 break;
f2f4d82f 2017 case HANGCHECK_ACTIVE:
ea04cb31 2018 ring->hangcheck.score += BUSY;
6274f212 2019 break;
f2f4d82f 2020 case HANGCHECK_KICK:
ea04cb31 2021 ring->hangcheck.score += KICK;
6274f212 2022 break;
f2f4d82f 2023 case HANGCHECK_HUNG:
ea04cb31 2024 ring->hangcheck.score += HUNG;
6274f212
CW		 2025 stuck[i] = true;
2026 break;
2027 }
05407ff8 2028 }
9107e9d2 2029 } else {
da661464
MK		 2030 ring->hangcheck.action = HANGCHECK_ACTIVE;
2031
9107e9d2
CW		 2032 /* Gradually reduce the count so that we catch DoS
2033 * attempts across multiple batches.
2034 */
2035 if (ring->hangcheck.score > 0)
2036 ring->hangcheck.score--;
d1e61e7f
CW		 2037 }
2038
05407ff8
MK		 2039 ring->hangcheck.seqno = seqno;
2040 ring->hangcheck.acthd = acthd;
9107e9d2 2041 busy_count += busy;
893eead0 2042 }
b9201c14 2043
92cab734 2044 for_each_ring(ring, dev_priv, i) {
9107e9d2 2045 if (ring->hangcheck.score > FIRE) {
b8d88d1d
DV		 2046 DRM_INFO("%s on %s\n",
2047 stuck[i] ? "stuck" : "no progress",
2048 ring->name);
a43adf07 2049 rings_hung++;
92cab734
MK		 2050 }
2051 }
2052
05407ff8
MK		 2053 if (rings_hung)
2054 return i915_handle_error(dev, true);
f65d9421 2055
05407ff8
MK		 2056 if (busy_count)
2057 /* Reset timer case chip hangs without another request
2058 * being added */
10cd45b6
MK		 2059 i915_queue_hangcheck(dev);
2060}
2061
2062void i915_queue_hangcheck(struct drm_device *dev)
2063{
2064 struct drm_i915_private *dev_priv = dev->dev_private;
2065 if (!i915_enable_hangcheck)
2066 return;
2067
2068 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2069 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
f65d9421
BG		 2070}
2071
91738a95
PZ		 2072static void ibx_irq_preinstall(struct drm_device *dev)
2073{
2074 struct drm_i915_private *dev_priv = dev->dev_private;
2075
2076 if (HAS_PCH_NOP(dev))
2077 return;
2078
2079 /* south display irq */
2080 I915_WRITE(SDEIMR, 0xffffffff);
2081 /*
2082 * SDEIER is also touched by the interrupt handler to work around missed
2083 * PCH interrupts. Hence we can't update it after the interrupt handler
2084 * is enabled - instead we unconditionally enable all PCH interrupt
2085 * sources here, but then only unmask them as needed with SDEIMR.
2086 */
2087 I915_WRITE(SDEIER, 0xffffffff);
2088 POSTING_READ(SDEIER);
2089}
2090
d18ea1b5
DV		 2091static void gen5_gt_irq_preinstall(struct drm_device *dev)
2092{
2093 struct drm_i915_private *dev_priv = dev->dev_private;
2094
2095 /* and GT */
2096 I915_WRITE(GTIMR, 0xffffffff);
2097 I915_WRITE(GTIER, 0x0);
2098 POSTING_READ(GTIER);
2099
2100 if (INTEL_INFO(dev)->gen >= 6) {
2101 /* and PM */
2102 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2103 I915_WRITE(GEN6_PMIER, 0x0);
2104 POSTING_READ(GEN6_PMIER);
2105 }
2106}
2107
1da177e4
LT		 2108/* drm_dma.h hooks
2109*/
f71d4af4 2110static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 2111{
2112 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2113
4697995b
JB		 2114 atomic_set(&dev_priv->irq_received, 0);
2115
036a4a7d 2116 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 2117
036a4a7d
ZW		 2118 I915_WRITE(DEIMR, 0xffffffff);
2119 I915_WRITE(DEIER, 0x0);
3143a2bf 2120 POSTING_READ(DEIER);
036a4a7d 2121
d18ea1b5 2122 gen5_gt_irq_preinstall(dev);
c650156a 2123
91738a95 2124 ibx_irq_preinstall(dev);
7d99163d
BW		 2125}
2126
7e231dbe
JB		 2127static void valleyview_irq_preinstall(struct drm_device *dev)
2128{
2129 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2130 int pipe;
2131
2132 atomic_set(&dev_priv->irq_received, 0);
2133
7e231dbe
JB		 2134 /* VLV magic */
2135 I915_WRITE(VLV_IMR, 0);
2136 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2137 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2138 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2139
7e231dbe
JB		 2140 /* and GT */
2141 I915_WRITE(GTIIR, I915_READ(GTIIR));
2142 I915_WRITE(GTIIR, I915_READ(GTIIR));
d18ea1b5
DV		 2143
2144 gen5_gt_irq_preinstall(dev);
7e231dbe
JB		 2145
2146 I915_WRITE(DPINVGTT, 0xff);
2147
2148 I915_WRITE(PORT_HOTPLUG_EN, 0);
2149 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2150 for_each_pipe(pipe)
2151 I915_WRITE(PIPESTAT(pipe), 0xffff);
2152 I915_WRITE(VLV_IIR, 0xffffffff);
2153 I915_WRITE(VLV_IMR, 0xffffffff);
2154 I915_WRITE(VLV_IER, 0x0);
2155 POSTING_READ(VLV_IER);
2156}
2157
82a28bcf 2158static void ibx_hpd_irq_setup(struct drm_device *dev)
7fe0b973
KP		 2159{
2160 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82a28bcf
DV		 2161 struct drm_mode_config *mode_config = &dev->mode_config;
2162 struct intel_encoder *intel_encoder;
fee884ed 2163 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
82a28bcf
DV		 2164
2165 if (HAS_PCH_IBX(dev)) {
fee884ed 2166 hotplug_irqs = SDE_HOTPLUG_MASK;
82a28bcf 2167 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed 2168 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
fee884ed 2169 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
82a28bcf 2170 } else {
fee884ed 2171 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
82a28bcf 2172 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed 2173 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
fee884ed 2174 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
82a28bcf 2175 }
7fe0b973 2176
fee884ed 2177 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
82a28bcf
DV		 2178
2179 /*
2180 * Enable digital hotplug on the PCH, and configure the DP short pulse
2181 * duration to 2ms (which is the minimum in the Display Port spec)
2182 *
2183 * This register is the same on all known PCH chips.
2184 */
7fe0b973
KP		 2185 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2186 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2187 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2188 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2189 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2190 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2191}
2192
d46da437
PZ		 2193static void ibx_irq_postinstall(struct drm_device *dev)
2194{
2195 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82a28bcf 2196 u32 mask;
e5868a31 2197
692a04cf
DV		 2198 if (HAS_PCH_NOP(dev))
2199 return;
2200
8664281b
PZ		 2201 if (HAS_PCH_IBX(dev)) {
2202 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
de032bf4 2203 SDE_TRANSA_FIFO_UNDER | SDE_POISON;
8664281b
PZ		 2204 } else {
2205 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2206
2207 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2208 }
ab5c608b 2209
d46da437
PZ		 2210 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2211 I915_WRITE(SDEIMR, ~mask);
d46da437
PZ		 2212}
2213
0a9a8c91
DV		 2214static void gen5_gt_irq_postinstall(struct drm_device *dev)
2215{
2216 struct drm_i915_private *dev_priv = dev->dev_private;
2217 u32 pm_irqs, gt_irqs;
2218
2219 pm_irqs = gt_irqs = 0;
2220
2221 dev_priv->gt_irq_mask = ~0;
2222 if (HAS_L3_GPU_CACHE(dev)) {
2223 /* L3 parity interrupt is always unmasked. */
2224 dev_priv->gt_irq_mask = ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2225 gt_irqs |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2226 }
2227
2228 gt_irqs |= GT_RENDER_USER_INTERRUPT;
2229 if (IS_GEN5(dev)) {
2230 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2231 ILK_BSD_USER_INTERRUPT;
2232 } else {
2233 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
2234 }
2235
2236 I915_WRITE(GTIIR, I915_READ(GTIIR));
2237 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2238 I915_WRITE(GTIER, gt_irqs);
2239 POSTING_READ(GTIER);
2240
2241 if (INTEL_INFO(dev)->gen >= 6) {
2242 pm_irqs |= GEN6_PM_RPS_EVENTS;
2243
2244 if (HAS_VEBOX(dev))
2245 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
2246
605cd25b 2247 dev_priv->pm_irq_mask = 0xffffffff;
0a9a8c91 2248 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
605cd25b 2249 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
0a9a8c91
DV		 2250 I915_WRITE(GEN6_PMIER, pm_irqs);
2251 POSTING_READ(GEN6_PMIER);
2252 }
2253}
2254
f71d4af4 2255static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d 2256{
4bc9d430 2257 unsigned long irqflags;
036a4a7d 2258 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8e76f8dc
PZ		 2259 u32 display_mask, extra_mask;
2260
2261 if (INTEL_INFO(dev)->gen >= 7) {
2262 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
2263 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
2264 DE_PLANEB_FLIP_DONE_IVB |
2265 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB |
2266 DE_ERR_INT_IVB);
2267 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
2268 DE_PIPEA_VBLANK_IVB);
2269
2270 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2271 } else {
2272 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2273 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
2274 DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
2275 DE_PIPEA_FIFO_UNDERRUN | DE_POISON);
2276 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT;
2277 }
036a4a7d 2278
1ec14ad3 2279 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 2280
2281 /* should always can generate irq */
2282 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3 2283 I915_WRITE(DEIMR, dev_priv->irq_mask);
8e76f8dc 2284 I915_WRITE(DEIER, display_mask | extra_mask);
3143a2bf 2285 POSTING_READ(DEIER);
036a4a7d 2286
0a9a8c91 2287 gen5_gt_irq_postinstall(dev);
036a4a7d 2288
d46da437 2289 ibx_irq_postinstall(dev);
7fe0b973 2290
f97108d1 2291 if (IS_IRONLAKE_M(dev)) {
6005ce42
DV		 2292 /* Enable PCU event interrupts
2293 *
2294 * spinlocking not required here for correctness since interrupt
4bc9d430
DV		 2295 * setup is guaranteed to run in single-threaded context. But we
2296 * need it to make the assert_spin_locked happy. */
2297 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f97108d1 2298 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
4bc9d430 2299 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
f97108d1
JB		 2300 }
2301
036a4a7d
ZW		 2302 return 0;
2303}
2304
7e231dbe
JB		 2305static int valleyview_irq_postinstall(struct drm_device *dev)
2306{
2307 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7e231dbe 2308 u32 enable_mask;
31acc7f5 2309 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
b79480ba 2310 unsigned long irqflags;
7e231dbe
JB		 2311
2312 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
31acc7f5
JB		 2313 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2314 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2315 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
7e231dbe
JB		 2316 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2317
31acc7f5
JB		 2318 /*
2319 *Leave vblank interrupts masked initially. enable/disable will
2320 * toggle them based on usage.
2321 */
2322 dev_priv->irq_mask = (~enable_mask) |
2323 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2324 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2325
20afbda2
DV		 2326 I915_WRITE(PORT_HOTPLUG_EN, 0);
2327 POSTING_READ(PORT_HOTPLUG_EN);
2328
7e231dbe
JB		 2329 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2330 I915_WRITE(VLV_IER, enable_mask);
2331 I915_WRITE(VLV_IIR, 0xffffffff);
2332 I915_WRITE(PIPESTAT(0), 0xffff);
2333 I915_WRITE(PIPESTAT(1), 0xffff);
2334 POSTING_READ(VLV_IER);
2335
b79480ba
DV		 2336 /* Interrupt setup is already guaranteed to be single-threaded, this is
2337 * just to make the assert_spin_locked check happy. */
2338 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5 2339 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
515ac2bb 2340 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
31acc7f5 2341 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
b79480ba 2342 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
31acc7f5 2343
7e231dbe
JB		 2344 I915_WRITE(VLV_IIR, 0xffffffff);
2345 I915_WRITE(VLV_IIR, 0xffffffff);
2346
0a9a8c91 2347 gen5_gt_irq_postinstall(dev);
7e231dbe
JB		 2348
2349 /* ack & enable invalid PTE error interrupts */
2350#if 0 /* FIXME: add support to irq handler for checking these bits */
2351 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2352 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2353#endif
2354
2355 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
20afbda2
DV		 2356
2357 return 0;
2358}
2359
7e231dbe
JB		 2360static void valleyview_irq_uninstall(struct drm_device *dev)
2361{
2362 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2363 int pipe;
2364
2365 if (!dev_priv)
2366 return;
2367
ac4c16c5
EE		 2368 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2369
7e231dbe
JB		 2370 for_each_pipe(pipe)
2371 I915_WRITE(PIPESTAT(pipe), 0xffff);
2372
2373 I915_WRITE(HWSTAM, 0xffffffff);
2374 I915_WRITE(PORT_HOTPLUG_EN, 0);
2375 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2376 for_each_pipe(pipe)
2377 I915_WRITE(PIPESTAT(pipe), 0xffff);
2378 I915_WRITE(VLV_IIR, 0xffffffff);
2379 I915_WRITE(VLV_IMR, 0xffffffff);
2380 I915_WRITE(VLV_IER, 0x0);
2381 POSTING_READ(VLV_IER);
2382}
2383
f71d4af4 2384static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 2385{
2386 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 2387
2388 if (!dev_priv)
2389 return;
2390
ac4c16c5
EE		 2391 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2392
036a4a7d
ZW		 2393 I915_WRITE(HWSTAM, 0xffffffff);
2394
2395 I915_WRITE(DEIMR, 0xffffffff);
2396 I915_WRITE(DEIER, 0x0);
2397 I915_WRITE(DEIIR, I915_READ(DEIIR));
8664281b
PZ		 2398 if (IS_GEN7(dev))
2399 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
036a4a7d
ZW		 2400
2401 I915_WRITE(GTIMR, 0xffffffff);
2402 I915_WRITE(GTIER, 0x0);
2403 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f 2404
ab5c608b
BW		 2405 if (HAS_PCH_NOP(dev))
2406 return;
2407
192aac1f
KP		 2408 I915_WRITE(SDEIMR, 0xffffffff);
2409 I915_WRITE(SDEIER, 0x0);
2410 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
8664281b
PZ		 2411 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
2412 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
036a4a7d
ZW		 2413}
2414
a266c7d5 2415static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 2416{
2417 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2418 int pipe;
91e3738e 2419
a266c7d5 2420 atomic_set(&dev_priv->irq_received, 0);
5ca58282 2421
9db4a9c7
JB		 2422 for_each_pipe(pipe)
2423 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 2424 I915_WRITE16(IMR, 0xffff);
2425 I915_WRITE16(IER, 0x0);
2426 POSTING_READ16(IER);
c2798b19
CW		 2427}
2428
2429static int i8xx_irq_postinstall(struct drm_device *dev)
2430{
2431 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2432
c2798b19
CW		 2433 I915_WRITE16(EMR,
2434 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2435
2436 /* Unmask the interrupts that we always want on. */
2437 dev_priv->irq_mask =
2438 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2439 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2440 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2441 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2442 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2443 I915_WRITE16(IMR, dev_priv->irq_mask);
2444
2445 I915_WRITE16(IER,
2446 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2447 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2448 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2449 I915_USER_INTERRUPT);
2450 POSTING_READ16(IER);
2451
2452 return 0;
2453}
2454
90a72f87
VS		 2455/*
2456 * Returns true when a page flip has completed.
2457 */
2458static bool i8xx_handle_vblank(struct drm_device *dev,
2459 int pipe, u16 iir)
2460{
2461 drm_i915_private_t *dev_priv = dev->dev_private;
2462 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
2463
2464 if (!drm_handle_vblank(dev, pipe))
2465 return false;
2466
2467 if ((iir & flip_pending) == 0)
2468 return false;
2469
2470 intel_prepare_page_flip(dev, pipe);
2471
2472 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2473 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2474 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2475 * the flip is completed (no longer pending). Since this doesn't raise
2476 * an interrupt per se, we watch for the change at vblank.
2477 */
2478 if (I915_READ16(ISR) & flip_pending)
2479 return false;
2480
2481 intel_finish_page_flip(dev, pipe);
2482
2483 return true;
2484}
2485
ff1f525e 2486static irqreturn_t i8xx_irq_handler(int irq, void *arg)
c2798b19
CW		 2487{
2488 struct drm_device *dev = (struct drm_device *) arg;
2489 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 2490 u16 iir, new_iir;
2491 u32 pipe_stats[2];
2492 unsigned long irqflags;
c2798b19
CW		 2493 int pipe;
2494 u16 flip_mask =
2495 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2496 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2497
2498 atomic_inc(&dev_priv->irq_received);
2499
2500 iir = I915_READ16(IIR);
2501 if (iir == 0)
2502 return IRQ_NONE;
2503
2504 while (iir & ~flip_mask) {
2505 /* Can't rely on pipestat interrupt bit in iir as it might
2506 * have been cleared after the pipestat interrupt was received.
2507 * It doesn't set the bit in iir again, but it still produces
2508 * interrupts (for non-MSI).
2509 */
2510 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2511 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2512 i915_handle_error(dev, false);
2513
2514 for_each_pipe(pipe) {
2515 int reg = PIPESTAT(pipe);
2516 pipe_stats[pipe] = I915_READ(reg);
2517
2518 /*
2519 * Clear the PIPE*STAT regs before the IIR
2520 */
2521 if (pipe_stats[pipe] & 0x8000ffff) {
2522 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2523 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2524 pipe_name(pipe));
2525 I915_WRITE(reg, pipe_stats[pipe]);
c2798b19
CW		 2526 }
2527 }
2528 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2529
2530 I915_WRITE16(IIR, iir & ~flip_mask);
2531 new_iir = I915_READ16(IIR); /* Flush posted writes */
2532
d05c617e 2533 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 2534
2535 if (iir & I915_USER_INTERRUPT)
2536 notify_ring(dev, &dev_priv->ring[RCS]);
2537
2538 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2539 i8xx_handle_vblank(dev, 0, iir))
2540 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
c2798b19
CW		 2541
2542 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2543 i8xx_handle_vblank(dev, 1, iir))
2544 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
c2798b19
CW		 2545
2546 iir = new_iir;
2547 }
2548
2549 return IRQ_HANDLED;
2550}
2551
2552static void i8xx_irq_uninstall(struct drm_device * dev)
2553{
2554 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2555 int pipe;
2556
c2798b19
CW		 2557 for_each_pipe(pipe) {
2558 /* Clear enable bits; then clear status bits */
2559 I915_WRITE(PIPESTAT(pipe), 0);
2560 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2561 }
2562 I915_WRITE16(IMR, 0xffff);
2563 I915_WRITE16(IER, 0x0);
2564 I915_WRITE16(IIR, I915_READ16(IIR));
2565}
2566
a266c7d5
CW		 2567static void i915_irq_preinstall(struct drm_device * dev)
2568{
2569 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2570 int pipe;
2571
2572 atomic_set(&dev_priv->irq_received, 0);
2573
2574 if (I915_HAS_HOTPLUG(dev)) {
2575 I915_WRITE(PORT_HOTPLUG_EN, 0);
2576 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2577 }
2578
00d98ebd 2579 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 2580 for_each_pipe(pipe)
2581 I915_WRITE(PIPESTAT(pipe), 0);
2582 I915_WRITE(IMR, 0xffffffff);
2583 I915_WRITE(IER, 0x0);
2584 POSTING_READ(IER);
2585}
2586
2587static int i915_irq_postinstall(struct drm_device *dev)
2588{
2589 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 2590 u32 enable_mask;
a266c7d5 2591
38bde180
CW		 2592 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2593
2594 /* Unmask the interrupts that we always want on. */
2595 dev_priv->irq_mask =
2596 ~(I915_ASLE_INTERRUPT |
2597 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2598 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2599 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2600 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2601 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2602
2603 enable_mask =
2604 I915_ASLE_INTERRUPT |
2605 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2606 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2607 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2608 I915_USER_INTERRUPT;
2609
a266c7d5 2610 if (I915_HAS_HOTPLUG(dev)) {
20afbda2
DV		 2611 I915_WRITE(PORT_HOTPLUG_EN, 0);
2612 POSTING_READ(PORT_HOTPLUG_EN);
2613
a266c7d5
CW		 2614 /* Enable in IER... */
2615 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2616 /* and unmask in IMR */
2617 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2618 }
2619
a266c7d5
CW		 2620 I915_WRITE(IMR, dev_priv->irq_mask);
2621 I915_WRITE(IER, enable_mask);
2622 POSTING_READ(IER);
2623
f49e38dd 2624 i915_enable_asle_pipestat(dev);
20afbda2
DV		 2625
2626 return 0;
2627}
2628
90a72f87
VS		 2629/*
2630 * Returns true when a page flip has completed.
2631 */
2632static bool i915_handle_vblank(struct drm_device *dev,
2633 int plane, int pipe, u32 iir)
2634{
2635 drm_i915_private_t *dev_priv = dev->dev_private;
2636 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
2637
2638 if (!drm_handle_vblank(dev, pipe))
2639 return false;
2640
2641 if ((iir & flip_pending) == 0)
2642 return false;
2643
2644 intel_prepare_page_flip(dev, plane);
2645
2646 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2647 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2648 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2649 * the flip is completed (no longer pending). Since this doesn't raise
2650 * an interrupt per se, we watch for the change at vblank.
2651 */
2652 if (I915_READ(ISR) & flip_pending)
2653 return false;
2654
2655 intel_finish_page_flip(dev, pipe);
2656
2657 return true;
2658}
2659
ff1f525e 2660static irqreturn_t i915_irq_handler(int irq, void *arg)
a266c7d5
CW		 2661{
2662 struct drm_device *dev = (struct drm_device *) arg;
2663 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 2664 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 2665 unsigned long irqflags;
38bde180
CW		 2666 u32 flip_mask =
2667 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2668 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
38bde180 2669 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 2670
2671 atomic_inc(&dev_priv->irq_received);
2672
2673 iir = I915_READ(IIR);
38bde180
CW		 2674 do {
2675 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 2676 bool blc_event = false;
a266c7d5
CW		 2677
2678 /* Can't rely on pipestat interrupt bit in iir as it might
2679 * have been cleared after the pipestat interrupt was received.
2680 * It doesn't set the bit in iir again, but it still produces
2681 * interrupts (for non-MSI).
2682 */
2683 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2684 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2685 i915_handle_error(dev, false);
2686
2687 for_each_pipe(pipe) {
2688 int reg = PIPESTAT(pipe);
2689 pipe_stats[pipe] = I915_READ(reg);
2690
38bde180 2691 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 2692 if (pipe_stats[pipe] & 0x8000ffff) {
2693 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2694 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2695 pipe_name(pipe));
2696 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 2697 irq_received = true;
a266c7d5
CW		 2698 }
2699 }
2700 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2701
2702 if (!irq_received)
2703 break;
2704
a266c7d5
CW		 2705 /* Consume port. Then clear IIR or we'll miss events */
2706 if ((I915_HAS_HOTPLUG(dev)) &&
2707 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2708 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04 2709 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
a266c7d5
CW		 2710
2711 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2712 hotplug_status);
91d131d2
DV		 2713
2714 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
2715
a266c7d5 2716 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 2717 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 2718 }
2719
38bde180 2720 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2721 new_iir = I915_READ(IIR); /* Flush posted writes */
2722
a266c7d5
CW		 2723 if (iir & I915_USER_INTERRUPT)
2724 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 2725
a266c7d5 2726 for_each_pipe(pipe) {
38bde180
CW		 2727 int plane = pipe;
2728 if (IS_MOBILE(dev))
2729 plane = !plane;
90a72f87 2730
8291ee90 2731 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2732 i915_handle_vblank(dev, plane, pipe, iir))
2733 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
a266c7d5
CW		 2734
2735 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2736 blc_event = true;
2737 }
2738
a266c7d5
CW		 2739 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2740 intel_opregion_asle_intr(dev);
2741
2742 /* With MSI, interrupts are only generated when iir
2743 * transitions from zero to nonzero. If another bit got
2744 * set while we were handling the existing iir bits, then
2745 * we would never get another interrupt.
2746 *
2747 * This is fine on non-MSI as well, as if we hit this path
2748 * we avoid exiting the interrupt handler only to generate
2749 * another one.
2750 *
2751 * Note that for MSI this could cause a stray interrupt report
2752 * if an interrupt landed in the time between writing IIR and
2753 * the posting read. This should be rare enough to never
2754 * trigger the 99% of 100,000 interrupts test for disabling
2755 * stray interrupts.
2756 */
38bde180 2757 ret = IRQ_HANDLED;
a266c7d5 2758 iir = new_iir;
38bde180 2759 } while (iir & ~flip_mask);
a266c7d5 2760
d05c617e 2761 i915_update_dri1_breadcrumb(dev);
8291ee90 2762
a266c7d5
CW		 2763 return ret;
2764}
2765
2766static void i915_irq_uninstall(struct drm_device * dev)
2767{
2768 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2769 int pipe;
2770
ac4c16c5
EE		 2771 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2772
a266c7d5
CW		 2773 if (I915_HAS_HOTPLUG(dev)) {
2774 I915_WRITE(PORT_HOTPLUG_EN, 0);
2775 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2776 }
2777
00d98ebd 2778 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 2779 for_each_pipe(pipe) {
2780 /* Clear enable bits; then clear status bits */
a266c7d5 2781 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 2782 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2783 }
a266c7d5
CW		 2784 I915_WRITE(IMR, 0xffffffff);
2785 I915_WRITE(IER, 0x0);
2786
a266c7d5
CW		 2787 I915_WRITE(IIR, I915_READ(IIR));
2788}
2789
2790static void i965_irq_preinstall(struct drm_device * dev)
2791{
2792 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2793 int pipe;
2794
2795 atomic_set(&dev_priv->irq_received, 0);
2796
adca4730
CW		 2797 I915_WRITE(PORT_HOTPLUG_EN, 0);
2798 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2799
2800 I915_WRITE(HWSTAM, 0xeffe);
2801 for_each_pipe(pipe)
2802 I915_WRITE(PIPESTAT(pipe), 0);
2803 I915_WRITE(IMR, 0xffffffff);
2804 I915_WRITE(IER, 0x0);
2805 POSTING_READ(IER);
2806}
2807
2808static int i965_irq_postinstall(struct drm_device *dev)
2809{
2810 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
bbba0a97 2811 u32 enable_mask;
a266c7d5 2812 u32 error_mask;
b79480ba 2813 unsigned long irqflags;
a266c7d5 2814
a266c7d5 2815 /* Unmask the interrupts that we always want on. */
bbba0a97 2816 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 2817 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 2818 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2819 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2820 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2821 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2822 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2823
2824 enable_mask = ~dev_priv->irq_mask;
21ad8330
VS		 2825 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2826 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
bbba0a97
CW		 2827 enable_mask |= I915_USER_INTERRUPT;
2828
2829 if (IS_G4X(dev))
2830 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5 2831
b79480ba
DV		 2832 /* Interrupt setup is already guaranteed to be single-threaded, this is
2833 * just to make the assert_spin_locked check happy. */
2834 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
515ac2bb 2835 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
b79480ba 2836 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
a266c7d5 2837
a266c7d5
CW		 2838 /*
2839 * Enable some error detection, note the instruction error mask
2840 * bit is reserved, so we leave it masked.
2841 */
2842 if (IS_G4X(dev)) {
2843 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2844 GM45_ERROR_MEM_PRIV |
2845 GM45_ERROR_CP_PRIV |
2846 I915_ERROR_MEMORY_REFRESH);
2847 } else {
2848 error_mask = ~(I915_ERROR_PAGE_TABLE |
2849 I915_ERROR_MEMORY_REFRESH);
2850 }
2851 I915_WRITE(EMR, error_mask);
2852
2853 I915_WRITE(IMR, dev_priv->irq_mask);
2854 I915_WRITE(IER, enable_mask);
2855 POSTING_READ(IER);
2856
20afbda2
DV		 2857 I915_WRITE(PORT_HOTPLUG_EN, 0);
2858 POSTING_READ(PORT_HOTPLUG_EN);
2859
f49e38dd 2860 i915_enable_asle_pipestat(dev);
20afbda2
DV		 2861
2862 return 0;
2863}
2864
bac56d5b 2865static void i915_hpd_irq_setup(struct drm_device *dev)
20afbda2
DV		 2866{
2867 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e5868a31 2868 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed 2869 struct intel_encoder *intel_encoder;
20afbda2
DV		 2870 u32 hotplug_en;
2871
b5ea2d56
DV		 2872 assert_spin_locked(&dev_priv->irq_lock);
2873
bac56d5b
EE		 2874 if (I915_HAS_HOTPLUG(dev)) {
2875 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2876 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
2877 /* Note HDMI and DP share hotplug bits */
e5868a31 2878 /* enable bits are the same for all generations */
cd569aed
EE		 2879 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2880 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2881 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
bac56d5b
EE		 2882 /* Programming the CRT detection parameters tends
2883 to generate a spurious hotplug event about three
2884 seconds later. So just do it once.
2885 */
2886 if (IS_G4X(dev))
2887 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
85fc95ba 2888 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
bac56d5b 2889 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
a266c7d5 2890
bac56d5b
EE		 2891 /* Ignore TV since it's buggy */
2892 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2893 }
a266c7d5
CW		 2894}
2895
ff1f525e 2896static irqreturn_t i965_irq_handler(int irq, void *arg)
a266c7d5
CW		 2897{
2898 struct drm_device *dev = (struct drm_device *) arg;
2899 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 2900 u32 iir, new_iir;
2901 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 2902 unsigned long irqflags;
2903 int irq_received;
2904 int ret = IRQ_NONE, pipe;
21ad8330
VS		 2905 u32 flip_mask =
2906 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2907 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
a266c7d5
CW		 2908
2909 atomic_inc(&dev_priv->irq_received);
2910
2911 iir = I915_READ(IIR);
2912
a266c7d5 2913 for (;;) {
2c8ba29f
CW		 2914 bool blc_event = false;
2915
21ad8330 2916 irq_received = (iir & ~flip_mask) != 0;
a266c7d5
CW		 2917
2918 /* Can't rely on pipestat interrupt bit in iir as it might
2919 * have been cleared after the pipestat interrupt was received.
2920 * It doesn't set the bit in iir again, but it still produces
2921 * interrupts (for non-MSI).
2922 */
2923 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2924 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2925 i915_handle_error(dev, false);
2926
2927 for_each_pipe(pipe) {
2928 int reg = PIPESTAT(pipe);
2929 pipe_stats[pipe] = I915_READ(reg);
2930
2931 /*
2932 * Clear the PIPE*STAT regs before the IIR
2933 */
2934 if (pipe_stats[pipe] & 0x8000ffff) {
2935 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2936 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2937 pipe_name(pipe));
2938 I915_WRITE(reg, pipe_stats[pipe]);
2939 irq_received = 1;
2940 }
2941 }
2942 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2943
2944 if (!irq_received)
2945 break;
2946
2947 ret = IRQ_HANDLED;
2948
2949 /* Consume port. Then clear IIR or we'll miss events */
adca4730 2950 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
a266c7d5 2951 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04
EE		 2952 u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
2953 HOTPLUG_INT_STATUS_G4X :
4f7fd709 2954 HOTPLUG_INT_STATUS_I915);
a266c7d5
CW		 2955
2956 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2957 hotplug_status);
91d131d2
DV		 2958
2959 intel_hpd_irq_handler(dev, hotplug_trigger,
2960 IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915);
2961
a266c7d5
CW		 2962 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2963 I915_READ(PORT_HOTPLUG_STAT);
2964 }
2965
21ad8330 2966 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2967 new_iir = I915_READ(IIR); /* Flush posted writes */
2968
a266c7d5
CW		 2969 if (iir & I915_USER_INTERRUPT)
2970 notify_ring(dev, &dev_priv->ring[RCS]);
2971 if (iir & I915_BSD_USER_INTERRUPT)
2972 notify_ring(dev, &dev_priv->ring[VCS]);
2973
a266c7d5 2974 for_each_pipe(pipe) {
2c8ba29f 2975 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2976 i915_handle_vblank(dev, pipe, pipe, iir))
2977 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
a266c7d5
CW		 2978
2979 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2980 blc_event = true;
2981 }
2982
2983
2984 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2985 intel_opregion_asle_intr(dev);
2986
515ac2bb
DV		 2987 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
2988 gmbus_irq_handler(dev);
2989
a266c7d5
CW		 2990 /* With MSI, interrupts are only generated when iir
2991 * transitions from zero to nonzero. If another bit got
2992 * set while we were handling the existing iir bits, then
2993 * we would never get another interrupt.
2994 *
2995 * This is fine on non-MSI as well, as if we hit this path
2996 * we avoid exiting the interrupt handler only to generate
2997 * another one.
2998 *
2999 * Note that for MSI this could cause a stray interrupt report
3000 * if an interrupt landed in the time between writing IIR and
3001 * the posting read. This should be rare enough to never
3002 * trigger the 99% of 100,000 interrupts test for disabling
3003 * stray interrupts.
3004 */
3005 iir = new_iir;
3006 }
3007
d05c617e 3008 i915_update_dri1_breadcrumb(dev);
2c8ba29f 3009
a266c7d5
CW		 3010 return ret;
3011}
3012
3013static void i965_irq_uninstall(struct drm_device * dev)
3014{
3015 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3016 int pipe;
3017
3018 if (!dev_priv)
3019 return;
3020
ac4c16c5
EE		 3021 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3022
adca4730
CW		 3023 I915_WRITE(PORT_HOTPLUG_EN, 0);
3024 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 3025
3026 I915_WRITE(HWSTAM, 0xffffffff);
3027 for_each_pipe(pipe)
3028 I915_WRITE(PIPESTAT(pipe), 0);
3029 I915_WRITE(IMR, 0xffffffff);
3030 I915_WRITE(IER, 0x0);
3031
3032 for_each_pipe(pipe)
3033 I915_WRITE(PIPESTAT(pipe),
3034 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3035 I915_WRITE(IIR, I915_READ(IIR));
3036}
3037
ac4c16c5
EE		 3038static void i915_reenable_hotplug_timer_func(unsigned long data)
3039{
3040 drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3041 struct drm_device *dev = dev_priv->dev;
3042 struct drm_mode_config *mode_config = &dev->mode_config;
3043 unsigned long irqflags;
3044 int i;
3045
3046 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3047 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3048 struct drm_connector *connector;
3049
3050 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3051 continue;
3052
3053 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3054
3055 list_for_each_entry(connector, &mode_config->connector_list, head) {
3056 struct intel_connector *intel_connector = to_intel_connector(connector);
3057
3058 if (intel_connector->encoder->hpd_pin == i) {
3059 if (connector->polled != intel_connector->polled)
3060 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3061 drm_get_connector_name(connector));
3062 connector->polled = intel_connector->polled;
3063 if (!connector->polled)
3064 connector->polled = DRM_CONNECTOR_POLL_HPD;
3065 }
3066 }
3067 }
3068 if (dev_priv->display.hpd_irq_setup)
3069 dev_priv->display.hpd_irq_setup(dev);
3070 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3071}
3072
f71d4af4
JB		 3073void intel_irq_init(struct drm_device *dev)
3074{
8b2e326d
CW		 3075 struct drm_i915_private *dev_priv = dev->dev_private;
3076
3077 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
99584db3 3078 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
c6a828d3 3079 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
a4da4fa4 3080 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
8b2e326d 3081
99584db3
DV		 3082 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3083 i915_hangcheck_elapsed,
61bac78e 3084 (unsigned long) dev);
ac4c16c5
EE		 3085 setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
3086 (unsigned long) dev_priv);
61bac78e 3087
97a19a24 3088 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
9ee32fea 3089
f71d4af4
JB		 3090 dev->driver->get_vblank_counter = i915_get_vblank_counter;
3091 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7d4e146f 3092 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 3093 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3094 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
3095 }
3096
c3613de9
KP		 3097 if (drm_core_check_feature(dev, DRIVER_MODESET))
3098 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
3099 else
3100 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 3101 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3102
7e231dbe
JB		 3103 if (IS_VALLEYVIEW(dev)) {
3104 dev->driver->irq_handler = valleyview_irq_handler;
3105 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3106 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3107 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3108 dev->driver->enable_vblank = valleyview_enable_vblank;
3109 dev->driver->disable_vblank = valleyview_disable_vblank;
fa00abe0 3110 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
f71d4af4
JB		 3111 } else if (HAS_PCH_SPLIT(dev)) {
3112 dev->driver->irq_handler = ironlake_irq_handler;
3113 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3114 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3115 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3116 dev->driver->enable_vblank = ironlake_enable_vblank;
3117 dev->driver->disable_vblank = ironlake_disable_vblank;
82a28bcf 3118 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4 3119 } else {
c2798b19
CW		 3120 if (INTEL_INFO(dev)->gen == 2) {
3121 dev->driver->irq_preinstall = i8xx_irq_preinstall;
3122 dev->driver->irq_postinstall = i8xx_irq_postinstall;
3123 dev->driver->irq_handler = i8xx_irq_handler;
3124 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5
CW		 3125 } else if (INTEL_INFO(dev)->gen == 3) {
3126 dev->driver->irq_preinstall = i915_irq_preinstall;
3127 dev->driver->irq_postinstall = i915_irq_postinstall;
3128 dev->driver->irq_uninstall = i915_irq_uninstall;
3129 dev->driver->irq_handler = i915_irq_handler;
20afbda2 3130 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 3131 } else {
a266c7d5
CW		 3132 dev->driver->irq_preinstall = i965_irq_preinstall;
3133 dev->driver->irq_postinstall = i965_irq_postinstall;
3134 dev->driver->irq_uninstall = i965_irq_uninstall;
3135 dev->driver->irq_handler = i965_irq_handler;
bac56d5b 3136 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 3137 }
f71d4af4
JB		 3138 dev->driver->enable_vblank = i915_enable_vblank;
3139 dev->driver->disable_vblank = i915_disable_vblank;
3140 }
3141}
20afbda2
DV		 3142
3143void intel_hpd_init(struct drm_device *dev)
3144{
3145 struct drm_i915_private *dev_priv = dev->dev_private;
821450c6
EE		 3146 struct drm_mode_config *mode_config = &dev->mode_config;
3147 struct drm_connector *connector;
b5ea2d56 3148 unsigned long irqflags;
821450c6 3149 int i;
20afbda2 3150
821450c6
EE		 3151 for (i = 1; i < HPD_NUM_PINS; i++) {
3152 dev_priv->hpd_stats[i].hpd_cnt = 0;
3153 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3154 }
3155 list_for_each_entry(connector, &mode_config->connector_list, head) {
3156 struct intel_connector *intel_connector = to_intel_connector(connector);
3157 connector->polled = intel_connector->polled;
3158 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3159 connector->polled = DRM_CONNECTOR_POLL_HPD;
3160 }
b5ea2d56
DV		 3161
3162 /* Interrupt setup is already guaranteed to be single-threaded, this is
3163 * just to make the assert_spin_locked checks happy. */
3164 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
20afbda2
DV		 3165 if (dev_priv->display.hpd_irq_setup)
3166 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 3167 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
20afbda2 3168}
c67a470b
PZ		 3169
3170/* Disable interrupts so we can allow Package C8+. */
3171void hsw_pc8_disable_interrupts(struct drm_device *dev)
3172{
3173 struct drm_i915_private *dev_priv = dev->dev_private;
3174 unsigned long irqflags;
3175
3176 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3177
3178 dev_priv->pc8.regsave.deimr = I915_READ(DEIMR);
3179 dev_priv->pc8.regsave.sdeimr = I915_READ(SDEIMR);
3180 dev_priv->pc8.regsave.gtimr = I915_READ(GTIMR);
3181 dev_priv->pc8.regsave.gtier = I915_READ(GTIER);
3182 dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR);
3183
3184 ironlake_disable_display_irq(dev_priv, ~DE_PCH_EVENT_IVB);
3185 ibx_disable_display_interrupt(dev_priv, ~SDE_HOTPLUG_MASK_CPT);
3186 ilk_disable_gt_irq(dev_priv, 0xffffffff);
3187 snb_disable_pm_irq(dev_priv, 0xffffffff);
3188
3189 dev_priv->pc8.irqs_disabled = true;
3190
3191 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3192}
3193
3194/* Restore interrupts so we can recover from Package C8+. */
3195void hsw_pc8_restore_interrupts(struct drm_device *dev)
3196{
3197 struct drm_i915_private *dev_priv = dev->dev_private;
3198 unsigned long irqflags;
3199 uint32_t val, expected;
3200
3201 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3202
3203 val = I915_READ(DEIMR);
3204 expected = ~DE_PCH_EVENT_IVB;
3205 WARN(val != expected, "DEIMR is 0x%08x, not 0x%08x\n", val, expected);
3206
3207 val = I915_READ(SDEIMR) & ~SDE_HOTPLUG_MASK_CPT;
3208 expected = ~SDE_HOTPLUG_MASK_CPT;
3209 WARN(val != expected, "SDEIMR non-HPD bits are 0x%08x, not 0x%08x\n",
3210 val, expected);
3211
3212 val = I915_READ(GTIMR);
3213 expected = 0xffffffff;
3214 WARN(val != expected, "GTIMR is 0x%08x, not 0x%08x\n", val, expected);
3215
3216 val = I915_READ(GEN6_PMIMR);
3217 expected = 0xffffffff;
3218 WARN(val != expected, "GEN6_PMIMR is 0x%08x, not 0x%08x\n", val,
3219 expected);
3220
3221 dev_priv->pc8.irqs_disabled = false;
3222
3223 ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr);
3224 ibx_enable_display_interrupt(dev_priv,
3225 ~dev_priv->pc8.regsave.sdeimr &
3226 ~SDE_HOTPLUG_MASK_CPT);
3227 ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr);
3228 snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr);
3229 I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier);
3230
3231 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3232}
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