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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
63eeaf38 | 31 | #include <linux/sysrq.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
b2c88f5b | 33 | #include <linux/circ_buf.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/i915_drm.h> | |
1da177e4 | 36 | #include "i915_drv.h" |
1c5d22f7 | 37 | #include "i915_trace.h" |
79e53945 | 38 | #include "intel_drv.h" |
1da177e4 | 39 | |
fca52a55 DV |
40 | /** |
41 | * DOC: interrupt handling | |
42 | * | |
43 | * These functions provide the basic support for enabling and disabling the | |
44 | * interrupt handling support. There's a lot more functionality in i915_irq.c | |
45 | * and related files, but that will be described in separate chapters. | |
46 | */ | |
47 | ||
7c7e10db | 48 | static const u32 hpd_ibx[HPD_NUM_PINS] = { |
e5868a31 EE |
49 | [HPD_CRT] = SDE_CRT_HOTPLUG, |
50 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, | |
51 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG, | |
52 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG, | |
53 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG | |
54 | }; | |
55 | ||
7c7e10db | 56 | static const u32 hpd_cpt[HPD_NUM_PINS] = { |
e5868a31 | 57 | [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, |
73c352a2 | 58 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, |
e5868a31 EE |
59 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
60 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
61 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT | |
62 | }; | |
63 | ||
7c7e10db | 64 | static const u32 hpd_mask_i915[HPD_NUM_PINS] = { |
e5868a31 EE |
65 | [HPD_CRT] = CRT_HOTPLUG_INT_EN, |
66 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, | |
67 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, | |
68 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, | |
69 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, | |
70 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN | |
71 | }; | |
72 | ||
7c7e10db | 73 | static const u32 hpd_status_g4x[HPD_NUM_PINS] = { |
e5868a31 EE |
74 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
75 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, | |
76 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, | |
77 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
78 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
79 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
80 | }; | |
81 | ||
7c7e10db | 82 | static const u32 hpd_status_i915[HPD_NUM_PINS] = { /* i915 and valleyview are the same */ |
e5868a31 EE |
83 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
84 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, | |
85 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, | |
86 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
87 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
88 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
89 | }; | |
90 | ||
5c502442 | 91 | /* IIR can theoretically queue up two events. Be paranoid. */ |
f86f3fb0 | 92 | #define GEN8_IRQ_RESET_NDX(type, which) do { \ |
5c502442 PZ |
93 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ |
94 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
95 | I915_WRITE(GEN8_##type##_IER(which), 0); \ | |
96 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
97 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
98 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
99 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
100 | } while (0) | |
101 | ||
f86f3fb0 | 102 | #define GEN5_IRQ_RESET(type) do { \ |
a9d356a6 | 103 | I915_WRITE(type##IMR, 0xffffffff); \ |
5c502442 | 104 | POSTING_READ(type##IMR); \ |
a9d356a6 | 105 | I915_WRITE(type##IER, 0); \ |
5c502442 PZ |
106 | I915_WRITE(type##IIR, 0xffffffff); \ |
107 | POSTING_READ(type##IIR); \ | |
108 | I915_WRITE(type##IIR, 0xffffffff); \ | |
109 | POSTING_READ(type##IIR); \ | |
a9d356a6 PZ |
110 | } while (0) |
111 | ||
337ba017 PZ |
112 | /* |
113 | * We should clear IMR at preinstall/uninstall, and just check at postinstall. | |
114 | */ | |
115 | #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \ | |
116 | u32 val = I915_READ(reg); \ | |
117 | if (val) { \ | |
118 | WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \ | |
119 | (reg), val); \ | |
120 | I915_WRITE((reg), 0xffffffff); \ | |
121 | POSTING_READ(reg); \ | |
122 | I915_WRITE((reg), 0xffffffff); \ | |
123 | POSTING_READ(reg); \ | |
124 | } \ | |
125 | } while (0) | |
126 | ||
35079899 | 127 | #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \ |
337ba017 | 128 | GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \ |
35079899 | 129 | I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \ |
7d1bd539 VS |
130 | I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \ |
131 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
35079899 PZ |
132 | } while (0) |
133 | ||
134 | #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \ | |
337ba017 | 135 | GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \ |
35079899 | 136 | I915_WRITE(type##IER, (ier_val)); \ |
7d1bd539 VS |
137 | I915_WRITE(type##IMR, (imr_val)); \ |
138 | POSTING_READ(type##IMR); \ | |
35079899 PZ |
139 | } while (0) |
140 | ||
c9a9a268 ID |
141 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir); |
142 | ||
036a4a7d | 143 | /* For display hotplug interrupt */ |
47339cd9 | 144 | void |
2d1013dd | 145 | ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask) |
036a4a7d | 146 | { |
4bc9d430 DV |
147 | assert_spin_locked(&dev_priv->irq_lock); |
148 | ||
9df7575f | 149 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 150 | return; |
c67a470b | 151 | |
1ec14ad3 CW |
152 | if ((dev_priv->irq_mask & mask) != 0) { |
153 | dev_priv->irq_mask &= ~mask; | |
154 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 155 | POSTING_READ(DEIMR); |
036a4a7d ZW |
156 | } |
157 | } | |
158 | ||
47339cd9 | 159 | void |
2d1013dd | 160 | ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask) |
036a4a7d | 161 | { |
4bc9d430 DV |
162 | assert_spin_locked(&dev_priv->irq_lock); |
163 | ||
06ffc778 | 164 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 165 | return; |
c67a470b | 166 | |
1ec14ad3 CW |
167 | if ((dev_priv->irq_mask & mask) != mask) { |
168 | dev_priv->irq_mask |= mask; | |
169 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 170 | POSTING_READ(DEIMR); |
036a4a7d ZW |
171 | } |
172 | } | |
173 | ||
43eaea13 PZ |
174 | /** |
175 | * ilk_update_gt_irq - update GTIMR | |
176 | * @dev_priv: driver private | |
177 | * @interrupt_mask: mask of interrupt bits to update | |
178 | * @enabled_irq_mask: mask of interrupt bits to enable | |
179 | */ | |
180 | static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, | |
181 | uint32_t interrupt_mask, | |
182 | uint32_t enabled_irq_mask) | |
183 | { | |
184 | assert_spin_locked(&dev_priv->irq_lock); | |
185 | ||
15a17aae DV |
186 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
187 | ||
9df7575f | 188 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 189 | return; |
c67a470b | 190 | |
43eaea13 PZ |
191 | dev_priv->gt_irq_mask &= ~interrupt_mask; |
192 | dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); | |
193 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
194 | POSTING_READ(GTIMR); | |
195 | } | |
196 | ||
480c8033 | 197 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
43eaea13 PZ |
198 | { |
199 | ilk_update_gt_irq(dev_priv, mask, mask); | |
200 | } | |
201 | ||
480c8033 | 202 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
43eaea13 PZ |
203 | { |
204 | ilk_update_gt_irq(dev_priv, mask, 0); | |
205 | } | |
206 | ||
b900b949 ID |
207 | static u32 gen6_pm_iir(struct drm_i915_private *dev_priv) |
208 | { | |
209 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; | |
210 | } | |
211 | ||
a72fbc3a ID |
212 | static u32 gen6_pm_imr(struct drm_i915_private *dev_priv) |
213 | { | |
214 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR; | |
215 | } | |
216 | ||
b900b949 ID |
217 | static u32 gen6_pm_ier(struct drm_i915_private *dev_priv) |
218 | { | |
219 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER; | |
220 | } | |
221 | ||
edbfdb45 PZ |
222 | /** |
223 | * snb_update_pm_irq - update GEN6_PMIMR | |
224 | * @dev_priv: driver private | |
225 | * @interrupt_mask: mask of interrupt bits to update | |
226 | * @enabled_irq_mask: mask of interrupt bits to enable | |
227 | */ | |
228 | static void snb_update_pm_irq(struct drm_i915_private *dev_priv, | |
229 | uint32_t interrupt_mask, | |
230 | uint32_t enabled_irq_mask) | |
231 | { | |
605cd25b | 232 | uint32_t new_val; |
edbfdb45 | 233 | |
15a17aae DV |
234 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
235 | ||
edbfdb45 PZ |
236 | assert_spin_locked(&dev_priv->irq_lock); |
237 | ||
605cd25b | 238 | new_val = dev_priv->pm_irq_mask; |
f52ecbcf PZ |
239 | new_val &= ~interrupt_mask; |
240 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
241 | ||
605cd25b PZ |
242 | if (new_val != dev_priv->pm_irq_mask) { |
243 | dev_priv->pm_irq_mask = new_val; | |
a72fbc3a ID |
244 | I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask); |
245 | POSTING_READ(gen6_pm_imr(dev_priv)); | |
f52ecbcf | 246 | } |
edbfdb45 PZ |
247 | } |
248 | ||
480c8033 | 249 | void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
edbfdb45 | 250 | { |
9939fba2 ID |
251 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
252 | return; | |
253 | ||
edbfdb45 PZ |
254 | snb_update_pm_irq(dev_priv, mask, mask); |
255 | } | |
256 | ||
9939fba2 ID |
257 | static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv, |
258 | uint32_t mask) | |
edbfdb45 PZ |
259 | { |
260 | snb_update_pm_irq(dev_priv, mask, 0); | |
261 | } | |
262 | ||
9939fba2 ID |
263 | void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
264 | { | |
265 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) | |
266 | return; | |
267 | ||
268 | __gen6_disable_pm_irq(dev_priv, mask); | |
269 | } | |
270 | ||
3cc134e3 ID |
271 | void gen6_reset_rps_interrupts(struct drm_device *dev) |
272 | { | |
273 | struct drm_i915_private *dev_priv = dev->dev_private; | |
274 | uint32_t reg = gen6_pm_iir(dev_priv); | |
275 | ||
276 | spin_lock_irq(&dev_priv->irq_lock); | |
277 | I915_WRITE(reg, dev_priv->pm_rps_events); | |
278 | I915_WRITE(reg, dev_priv->pm_rps_events); | |
279 | POSTING_READ(reg); | |
280 | spin_unlock_irq(&dev_priv->irq_lock); | |
281 | } | |
282 | ||
b900b949 ID |
283 | void gen6_enable_rps_interrupts(struct drm_device *dev) |
284 | { | |
285 | struct drm_i915_private *dev_priv = dev->dev_private; | |
286 | ||
287 | spin_lock_irq(&dev_priv->irq_lock); | |
78e68d36 | 288 | |
b900b949 | 289 | WARN_ON(dev_priv->rps.pm_iir); |
3cc134e3 | 290 | WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events); |
d4d70aa5 | 291 | dev_priv->rps.interrupts_enabled = true; |
78e68d36 ID |
292 | I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) | |
293 | dev_priv->pm_rps_events); | |
b900b949 | 294 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
78e68d36 | 295 | |
b900b949 ID |
296 | spin_unlock_irq(&dev_priv->irq_lock); |
297 | } | |
298 | ||
59d02a1f ID |
299 | u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask) |
300 | { | |
301 | /* | |
f24eeb19 | 302 | * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer |
59d02a1f | 303 | * if GEN6_PM_UP_EI_EXPIRED is masked. |
f24eeb19 ID |
304 | * |
305 | * TODO: verify if this can be reproduced on VLV,CHV. | |
59d02a1f ID |
306 | */ |
307 | if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv)) | |
308 | mask &= ~GEN6_PM_RP_UP_EI_EXPIRED; | |
309 | ||
310 | if (INTEL_INFO(dev_priv)->gen >= 8) | |
311 | mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP; | |
312 | ||
313 | return mask; | |
314 | } | |
315 | ||
b900b949 ID |
316 | void gen6_disable_rps_interrupts(struct drm_device *dev) |
317 | { | |
318 | struct drm_i915_private *dev_priv = dev->dev_private; | |
319 | ||
d4d70aa5 ID |
320 | spin_lock_irq(&dev_priv->irq_lock); |
321 | dev_priv->rps.interrupts_enabled = false; | |
322 | spin_unlock_irq(&dev_priv->irq_lock); | |
323 | ||
324 | cancel_work_sync(&dev_priv->rps.work); | |
325 | ||
9939fba2 ID |
326 | spin_lock_irq(&dev_priv->irq_lock); |
327 | ||
59d02a1f | 328 | I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0)); |
9939fba2 ID |
329 | |
330 | __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events); | |
b900b949 ID |
331 | I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) & |
332 | ~dev_priv->pm_rps_events); | |
9939fba2 ID |
333 | I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events); |
334 | I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events); | |
b900b949 | 335 | |
b900b949 | 336 | dev_priv->rps.pm_iir = 0; |
b900b949 | 337 | |
9939fba2 | 338 | spin_unlock_irq(&dev_priv->irq_lock); |
b900b949 ID |
339 | } |
340 | ||
fee884ed DV |
341 | /** |
342 | * ibx_display_interrupt_update - update SDEIMR | |
343 | * @dev_priv: driver private | |
344 | * @interrupt_mask: mask of interrupt bits to update | |
345 | * @enabled_irq_mask: mask of interrupt bits to enable | |
346 | */ | |
47339cd9 DV |
347 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
348 | uint32_t interrupt_mask, | |
349 | uint32_t enabled_irq_mask) | |
fee884ed DV |
350 | { |
351 | uint32_t sdeimr = I915_READ(SDEIMR); | |
352 | sdeimr &= ~interrupt_mask; | |
353 | sdeimr |= (~enabled_irq_mask & interrupt_mask); | |
354 | ||
15a17aae DV |
355 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
356 | ||
fee884ed DV |
357 | assert_spin_locked(&dev_priv->irq_lock); |
358 | ||
9df7575f | 359 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 360 | return; |
c67a470b | 361 | |
fee884ed DV |
362 | I915_WRITE(SDEIMR, sdeimr); |
363 | POSTING_READ(SDEIMR); | |
364 | } | |
8664281b | 365 | |
b5ea642a | 366 | static void |
755e9019 ID |
367 | __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
368 | u32 enable_mask, u32 status_mask) | |
7c463586 | 369 | { |
46c06a30 | 370 | u32 reg = PIPESTAT(pipe); |
755e9019 | 371 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 372 | |
b79480ba | 373 | assert_spin_locked(&dev_priv->irq_lock); |
d518ce50 | 374 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
b79480ba | 375 | |
04feced9 VS |
376 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
377 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
378 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
379 | pipe_name(pipe), enable_mask, status_mask)) | |
755e9019 ID |
380 | return; |
381 | ||
382 | if ((pipestat & enable_mask) == enable_mask) | |
46c06a30 VS |
383 | return; |
384 | ||
91d181dd ID |
385 | dev_priv->pipestat_irq_mask[pipe] |= status_mask; |
386 | ||
46c06a30 | 387 | /* Enable the interrupt, clear any pending status */ |
755e9019 | 388 | pipestat |= enable_mask | status_mask; |
46c06a30 VS |
389 | I915_WRITE(reg, pipestat); |
390 | POSTING_READ(reg); | |
7c463586 KP |
391 | } |
392 | ||
b5ea642a | 393 | static void |
755e9019 ID |
394 | __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
395 | u32 enable_mask, u32 status_mask) | |
7c463586 | 396 | { |
46c06a30 | 397 | u32 reg = PIPESTAT(pipe); |
755e9019 | 398 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 399 | |
b79480ba | 400 | assert_spin_locked(&dev_priv->irq_lock); |
d518ce50 | 401 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
b79480ba | 402 | |
04feced9 VS |
403 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
404 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
405 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
406 | pipe_name(pipe), enable_mask, status_mask)) | |
46c06a30 VS |
407 | return; |
408 | ||
755e9019 ID |
409 | if ((pipestat & enable_mask) == 0) |
410 | return; | |
411 | ||
91d181dd ID |
412 | dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; |
413 | ||
755e9019 | 414 | pipestat &= ~enable_mask; |
46c06a30 VS |
415 | I915_WRITE(reg, pipestat); |
416 | POSTING_READ(reg); | |
7c463586 KP |
417 | } |
418 | ||
10c59c51 ID |
419 | static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask) |
420 | { | |
421 | u32 enable_mask = status_mask << 16; | |
422 | ||
423 | /* | |
724a6905 VS |
424 | * On pipe A we don't support the PSR interrupt yet, |
425 | * on pipe B and C the same bit MBZ. | |
10c59c51 ID |
426 | */ |
427 | if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV)) | |
428 | return 0; | |
724a6905 VS |
429 | /* |
430 | * On pipe B and C we don't support the PSR interrupt yet, on pipe | |
431 | * A the same bit is for perf counters which we don't use either. | |
432 | */ | |
433 | if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV)) | |
434 | return 0; | |
10c59c51 ID |
435 | |
436 | enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | | |
437 | SPRITE0_FLIP_DONE_INT_EN_VLV | | |
438 | SPRITE1_FLIP_DONE_INT_EN_VLV); | |
439 | if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV) | |
440 | enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV; | |
441 | if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV) | |
442 | enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; | |
443 | ||
444 | return enable_mask; | |
445 | } | |
446 | ||
755e9019 ID |
447 | void |
448 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
449 | u32 status_mask) | |
450 | { | |
451 | u32 enable_mask; | |
452 | ||
10c59c51 ID |
453 | if (IS_VALLEYVIEW(dev_priv->dev)) |
454 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, | |
455 | status_mask); | |
456 | else | |
457 | enable_mask = status_mask << 16; | |
755e9019 ID |
458 | __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
459 | } | |
460 | ||
461 | void | |
462 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
463 | u32 status_mask) | |
464 | { | |
465 | u32 enable_mask; | |
466 | ||
10c59c51 ID |
467 | if (IS_VALLEYVIEW(dev_priv->dev)) |
468 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, | |
469 | status_mask); | |
470 | else | |
471 | enable_mask = status_mask << 16; | |
755e9019 ID |
472 | __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
473 | } | |
474 | ||
01c66889 | 475 | /** |
f49e38dd | 476 | * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion |
01c66889 | 477 | */ |
f49e38dd | 478 | static void i915_enable_asle_pipestat(struct drm_device *dev) |
01c66889 | 479 | { |
2d1013dd | 480 | struct drm_i915_private *dev_priv = dev->dev_private; |
1ec14ad3 | 481 | |
f49e38dd JN |
482 | if (!dev_priv->opregion.asle || !IS_MOBILE(dev)) |
483 | return; | |
484 | ||
13321786 | 485 | spin_lock_irq(&dev_priv->irq_lock); |
01c66889 | 486 | |
755e9019 | 487 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); |
f898780b | 488 | if (INTEL_INFO(dev)->gen >= 4) |
3b6c42e8 | 489 | i915_enable_pipestat(dev_priv, PIPE_A, |
755e9019 | 490 | PIPE_LEGACY_BLC_EVENT_STATUS); |
1ec14ad3 | 491 | |
13321786 | 492 | spin_unlock_irq(&dev_priv->irq_lock); |
01c66889 ZY |
493 | } |
494 | ||
f75f3746 VS |
495 | /* |
496 | * This timing diagram depicts the video signal in and | |
497 | * around the vertical blanking period. | |
498 | * | |
499 | * Assumptions about the fictitious mode used in this example: | |
500 | * vblank_start >= 3 | |
501 | * vsync_start = vblank_start + 1 | |
502 | * vsync_end = vblank_start + 2 | |
503 | * vtotal = vblank_start + 3 | |
504 | * | |
505 | * start of vblank: | |
506 | * latch double buffered registers | |
507 | * increment frame counter (ctg+) | |
508 | * generate start of vblank interrupt (gen4+) | |
509 | * | | |
510 | * | frame start: | |
511 | * | generate frame start interrupt (aka. vblank interrupt) (gmch) | |
512 | * | may be shifted forward 1-3 extra lines via PIPECONF | |
513 | * | | | |
514 | * | | start of vsync: | |
515 | * | | generate vsync interrupt | |
516 | * | | | | |
517 | * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx | |
518 | * . \hs/ . \hs/ \hs/ \hs/ . \hs/ | |
519 | * ----va---> <-----------------vb--------------------> <--------va------------- | |
520 | * | | <----vs-----> | | |
521 | * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2) | |
522 | * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+) | |
523 | * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi) | |
524 | * | | | | |
525 | * last visible pixel first visible pixel | |
526 | * | increment frame counter (gen3/4) | |
527 | * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4) | |
528 | * | |
529 | * x = horizontal active | |
530 | * _ = horizontal blanking | |
531 | * hs = horizontal sync | |
532 | * va = vertical active | |
533 | * vb = vertical blanking | |
534 | * vs = vertical sync | |
535 | * vbs = vblank_start (number) | |
536 | * | |
537 | * Summary: | |
538 | * - most events happen at the start of horizontal sync | |
539 | * - frame start happens at the start of horizontal blank, 1-4 lines | |
540 | * (depending on PIPECONF settings) after the start of vblank | |
541 | * - gen3/4 pixel and frame counter are synchronized with the start | |
542 | * of horizontal active on the first line of vertical active | |
543 | */ | |
544 | ||
4cdb83ec VS |
545 | static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe) |
546 | { | |
547 | /* Gen2 doesn't have a hardware frame counter */ | |
548 | return 0; | |
549 | } | |
550 | ||
42f52ef8 KP |
551 | /* Called from drm generic code, passed a 'crtc', which |
552 | * we use as a pipe index | |
553 | */ | |
f71d4af4 | 554 | static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
0a3e67a4 | 555 | { |
2d1013dd | 556 | struct drm_i915_private *dev_priv = dev->dev_private; |
0a3e67a4 JB |
557 | unsigned long high_frame; |
558 | unsigned long low_frame; | |
0b2a8e09 | 559 | u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal; |
f3a5c3f6 DV |
560 | struct intel_crtc *intel_crtc = |
561 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
562 | const struct drm_display_mode *mode = | |
563 | &intel_crtc->config->base.adjusted_mode; | |
0a3e67a4 | 564 | |
f3a5c3f6 DV |
565 | htotal = mode->crtc_htotal; |
566 | hsync_start = mode->crtc_hsync_start; | |
567 | vbl_start = mode->crtc_vblank_start; | |
568 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
569 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
391f75e2 | 570 | |
0b2a8e09 VS |
571 | /* Convert to pixel count */ |
572 | vbl_start *= htotal; | |
573 | ||
574 | /* Start of vblank event occurs at start of hsync */ | |
575 | vbl_start -= htotal - hsync_start; | |
576 | ||
9db4a9c7 JB |
577 | high_frame = PIPEFRAME(pipe); |
578 | low_frame = PIPEFRAMEPIXEL(pipe); | |
5eddb70b | 579 | |
0a3e67a4 JB |
580 | /* |
581 | * High & low register fields aren't synchronized, so make sure | |
582 | * we get a low value that's stable across two reads of the high | |
583 | * register. | |
584 | */ | |
585 | do { | |
5eddb70b | 586 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
391f75e2 | 587 | low = I915_READ(low_frame); |
5eddb70b | 588 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
0a3e67a4 JB |
589 | } while (high1 != high2); |
590 | ||
5eddb70b | 591 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
391f75e2 | 592 | pixel = low & PIPE_PIXEL_MASK; |
5eddb70b | 593 | low >>= PIPE_FRAME_LOW_SHIFT; |
391f75e2 VS |
594 | |
595 | /* | |
596 | * The frame counter increments at beginning of active. | |
597 | * Cook up a vblank counter by also checking the pixel | |
598 | * counter against vblank start. | |
599 | */ | |
edc08d0a | 600 | return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; |
0a3e67a4 JB |
601 | } |
602 | ||
f71d4af4 | 603 | static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
9880b7a5 | 604 | { |
2d1013dd | 605 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 606 | int reg = PIPE_FRMCOUNT_GM45(pipe); |
9880b7a5 | 607 | |
9880b7a5 JB |
608 | return I915_READ(reg); |
609 | } | |
610 | ||
ad3543ed MK |
611 | /* raw reads, only for fast reads of display block, no need for forcewake etc. */ |
612 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) | |
ad3543ed | 613 | |
a225f079 VS |
614 | static int __intel_get_crtc_scanline(struct intel_crtc *crtc) |
615 | { | |
616 | struct drm_device *dev = crtc->base.dev; | |
617 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 618 | const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; |
a225f079 | 619 | enum pipe pipe = crtc->pipe; |
80715b2f | 620 | int position, vtotal; |
a225f079 | 621 | |
80715b2f | 622 | vtotal = mode->crtc_vtotal; |
a225f079 VS |
623 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
624 | vtotal /= 2; | |
625 | ||
626 | if (IS_GEN2(dev)) | |
627 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; | |
628 | else | |
629 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; | |
630 | ||
631 | /* | |
80715b2f VS |
632 | * See update_scanline_offset() for the details on the |
633 | * scanline_offset adjustment. | |
a225f079 | 634 | */ |
80715b2f | 635 | return (position + crtc->scanline_offset) % vtotal; |
a225f079 VS |
636 | } |
637 | ||
f71d4af4 | 638 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
abca9e45 VS |
639 | unsigned int flags, int *vpos, int *hpos, |
640 | ktime_t *stime, ktime_t *etime) | |
0af7e4df | 641 | { |
c2baf4b7 VS |
642 | struct drm_i915_private *dev_priv = dev->dev_private; |
643 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
644 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 645 | const struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode; |
3aa18df8 | 646 | int position; |
78e8fc6b | 647 | int vbl_start, vbl_end, hsync_start, htotal, vtotal; |
0af7e4df MK |
648 | bool in_vbl = true; |
649 | int ret = 0; | |
ad3543ed | 650 | unsigned long irqflags; |
0af7e4df | 651 | |
c2baf4b7 | 652 | if (!intel_crtc->active) { |
0af7e4df | 653 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
9db4a9c7 | 654 | "pipe %c\n", pipe_name(pipe)); |
0af7e4df MK |
655 | return 0; |
656 | } | |
657 | ||
c2baf4b7 | 658 | htotal = mode->crtc_htotal; |
78e8fc6b | 659 | hsync_start = mode->crtc_hsync_start; |
c2baf4b7 VS |
660 | vtotal = mode->crtc_vtotal; |
661 | vbl_start = mode->crtc_vblank_start; | |
662 | vbl_end = mode->crtc_vblank_end; | |
0af7e4df | 663 | |
d31faf65 VS |
664 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
665 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
666 | vbl_end /= 2; | |
667 | vtotal /= 2; | |
668 | } | |
669 | ||
c2baf4b7 VS |
670 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; |
671 | ||
ad3543ed MK |
672 | /* |
673 | * Lock uncore.lock, as we will do multiple timing critical raw | |
674 | * register reads, potentially with preemption disabled, so the | |
675 | * following code must not block on uncore.lock. | |
676 | */ | |
677 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
78e8fc6b | 678 | |
ad3543ed MK |
679 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ |
680 | ||
681 | /* Get optional system timestamp before query. */ | |
682 | if (stime) | |
683 | *stime = ktime_get(); | |
684 | ||
7c06b08a | 685 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
0af7e4df MK |
686 | /* No obvious pixelcount register. Only query vertical |
687 | * scanout position from Display scan line register. | |
688 | */ | |
a225f079 | 689 | position = __intel_get_crtc_scanline(intel_crtc); |
0af7e4df MK |
690 | } else { |
691 | /* Have access to pixelcount since start of frame. | |
692 | * We can split this into vertical and horizontal | |
693 | * scanout position. | |
694 | */ | |
ad3543ed | 695 | position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; |
0af7e4df | 696 | |
3aa18df8 VS |
697 | /* convert to pixel counts */ |
698 | vbl_start *= htotal; | |
699 | vbl_end *= htotal; | |
700 | vtotal *= htotal; | |
78e8fc6b | 701 | |
7e78f1cb VS |
702 | /* |
703 | * In interlaced modes, the pixel counter counts all pixels, | |
704 | * so one field will have htotal more pixels. In order to avoid | |
705 | * the reported position from jumping backwards when the pixel | |
706 | * counter is beyond the length of the shorter field, just | |
707 | * clamp the position the length of the shorter field. This | |
708 | * matches how the scanline counter based position works since | |
709 | * the scanline counter doesn't count the two half lines. | |
710 | */ | |
711 | if (position >= vtotal) | |
712 | position = vtotal - 1; | |
713 | ||
78e8fc6b VS |
714 | /* |
715 | * Start of vblank interrupt is triggered at start of hsync, | |
716 | * just prior to the first active line of vblank. However we | |
717 | * consider lines to start at the leading edge of horizontal | |
718 | * active. So, should we get here before we've crossed into | |
719 | * the horizontal active of the first line in vblank, we would | |
720 | * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that, | |
721 | * always add htotal-hsync_start to the current pixel position. | |
722 | */ | |
723 | position = (position + htotal - hsync_start) % vtotal; | |
0af7e4df MK |
724 | } |
725 | ||
ad3543ed MK |
726 | /* Get optional system timestamp after query. */ |
727 | if (etime) | |
728 | *etime = ktime_get(); | |
729 | ||
730 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ | |
731 | ||
732 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
733 | ||
3aa18df8 VS |
734 | in_vbl = position >= vbl_start && position < vbl_end; |
735 | ||
736 | /* | |
737 | * While in vblank, position will be negative | |
738 | * counting up towards 0 at vbl_end. And outside | |
739 | * vblank, position will be positive counting | |
740 | * up since vbl_end. | |
741 | */ | |
742 | if (position >= vbl_start) | |
743 | position -= vbl_end; | |
744 | else | |
745 | position += vtotal - vbl_end; | |
0af7e4df | 746 | |
7c06b08a | 747 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
3aa18df8 VS |
748 | *vpos = position; |
749 | *hpos = 0; | |
750 | } else { | |
751 | *vpos = position / htotal; | |
752 | *hpos = position - (*vpos * htotal); | |
753 | } | |
0af7e4df | 754 | |
0af7e4df MK |
755 | /* In vblank? */ |
756 | if (in_vbl) | |
3d3cbd84 | 757 | ret |= DRM_SCANOUTPOS_IN_VBLANK; |
0af7e4df MK |
758 | |
759 | return ret; | |
760 | } | |
761 | ||
a225f079 VS |
762 | int intel_get_crtc_scanline(struct intel_crtc *crtc) |
763 | { | |
764 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
765 | unsigned long irqflags; | |
766 | int position; | |
767 | ||
768 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
769 | position = __intel_get_crtc_scanline(crtc); | |
770 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
771 | ||
772 | return position; | |
773 | } | |
774 | ||
f71d4af4 | 775 | static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
0af7e4df MK |
776 | int *max_error, |
777 | struct timeval *vblank_time, | |
778 | unsigned flags) | |
779 | { | |
4041b853 | 780 | struct drm_crtc *crtc; |
0af7e4df | 781 | |
7eb552ae | 782 | if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { |
4041b853 | 783 | DRM_ERROR("Invalid crtc %d\n", pipe); |
0af7e4df MK |
784 | return -EINVAL; |
785 | } | |
786 | ||
787 | /* Get drm_crtc to timestamp: */ | |
4041b853 CW |
788 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
789 | if (crtc == NULL) { | |
790 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
791 | return -EINVAL; | |
792 | } | |
793 | ||
83d65738 | 794 | if (!crtc->state->enable) { |
4041b853 CW |
795 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); |
796 | return -EBUSY; | |
797 | } | |
0af7e4df MK |
798 | |
799 | /* Helper routine in DRM core does all the work: */ | |
4041b853 CW |
800 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
801 | vblank_time, flags, | |
7da903ef | 802 | crtc, |
6e3c9717 | 803 | &to_intel_crtc(crtc)->config->base.adjusted_mode); |
0af7e4df MK |
804 | } |
805 | ||
67c347ff JN |
806 | static bool intel_hpd_irq_event(struct drm_device *dev, |
807 | struct drm_connector *connector) | |
321a1b30 EE |
808 | { |
809 | enum drm_connector_status old_status; | |
810 | ||
811 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); | |
812 | old_status = connector->status; | |
813 | ||
814 | connector->status = connector->funcs->detect(connector, false); | |
67c347ff JN |
815 | if (old_status == connector->status) |
816 | return false; | |
817 | ||
818 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n", | |
321a1b30 | 819 | connector->base.id, |
c23cc417 | 820 | connector->name, |
67c347ff JN |
821 | drm_get_connector_status_name(old_status), |
822 | drm_get_connector_status_name(connector->status)); | |
823 | ||
824 | return true; | |
321a1b30 EE |
825 | } |
826 | ||
13cf5504 DA |
827 | static void i915_digport_work_func(struct work_struct *work) |
828 | { | |
829 | struct drm_i915_private *dev_priv = | |
830 | container_of(work, struct drm_i915_private, dig_port_work); | |
13cf5504 DA |
831 | u32 long_port_mask, short_port_mask; |
832 | struct intel_digital_port *intel_dig_port; | |
b2c5c181 | 833 | int i; |
13cf5504 DA |
834 | u32 old_bits = 0; |
835 | ||
4cb21832 | 836 | spin_lock_irq(&dev_priv->irq_lock); |
13cf5504 DA |
837 | long_port_mask = dev_priv->long_hpd_port_mask; |
838 | dev_priv->long_hpd_port_mask = 0; | |
839 | short_port_mask = dev_priv->short_hpd_port_mask; | |
840 | dev_priv->short_hpd_port_mask = 0; | |
4cb21832 | 841 | spin_unlock_irq(&dev_priv->irq_lock); |
13cf5504 DA |
842 | |
843 | for (i = 0; i < I915_MAX_PORTS; i++) { | |
844 | bool valid = false; | |
845 | bool long_hpd = false; | |
846 | intel_dig_port = dev_priv->hpd_irq_port[i]; | |
847 | if (!intel_dig_port || !intel_dig_port->hpd_pulse) | |
848 | continue; | |
849 | ||
850 | if (long_port_mask & (1 << i)) { | |
851 | valid = true; | |
852 | long_hpd = true; | |
853 | } else if (short_port_mask & (1 << i)) | |
854 | valid = true; | |
855 | ||
856 | if (valid) { | |
b2c5c181 DV |
857 | enum irqreturn ret; |
858 | ||
13cf5504 | 859 | ret = intel_dig_port->hpd_pulse(intel_dig_port, long_hpd); |
b2c5c181 DV |
860 | if (ret == IRQ_NONE) { |
861 | /* fall back to old school hpd */ | |
13cf5504 DA |
862 | old_bits |= (1 << intel_dig_port->base.hpd_pin); |
863 | } | |
864 | } | |
865 | } | |
866 | ||
867 | if (old_bits) { | |
4cb21832 | 868 | spin_lock_irq(&dev_priv->irq_lock); |
13cf5504 | 869 | dev_priv->hpd_event_bits |= old_bits; |
4cb21832 | 870 | spin_unlock_irq(&dev_priv->irq_lock); |
13cf5504 DA |
871 | schedule_work(&dev_priv->hotplug_work); |
872 | } | |
873 | } | |
874 | ||
5ca58282 JB |
875 | /* |
876 | * Handle hotplug events outside the interrupt handler proper. | |
877 | */ | |
ac4c16c5 EE |
878 | #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000) |
879 | ||
5ca58282 JB |
880 | static void i915_hotplug_work_func(struct work_struct *work) |
881 | { | |
2d1013dd JN |
882 | struct drm_i915_private *dev_priv = |
883 | container_of(work, struct drm_i915_private, hotplug_work); | |
5ca58282 | 884 | struct drm_device *dev = dev_priv->dev; |
c31c4ba3 | 885 | struct drm_mode_config *mode_config = &dev->mode_config; |
cd569aed EE |
886 | struct intel_connector *intel_connector; |
887 | struct intel_encoder *intel_encoder; | |
888 | struct drm_connector *connector; | |
cd569aed | 889 | bool hpd_disabled = false; |
321a1b30 | 890 | bool changed = false; |
142e2398 | 891 | u32 hpd_event_bits; |
4ef69c7a | 892 | |
a65e34c7 | 893 | mutex_lock(&mode_config->mutex); |
e67189ab JB |
894 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); |
895 | ||
4cb21832 | 896 | spin_lock_irq(&dev_priv->irq_lock); |
142e2398 EE |
897 | |
898 | hpd_event_bits = dev_priv->hpd_event_bits; | |
899 | dev_priv->hpd_event_bits = 0; | |
cd569aed EE |
900 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
901 | intel_connector = to_intel_connector(connector); | |
36cd7444 DA |
902 | if (!intel_connector->encoder) |
903 | continue; | |
cd569aed EE |
904 | intel_encoder = intel_connector->encoder; |
905 | if (intel_encoder->hpd_pin > HPD_NONE && | |
906 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED && | |
907 | connector->polled == DRM_CONNECTOR_POLL_HPD) { | |
908 | DRM_INFO("HPD interrupt storm detected on connector %s: " | |
909 | "switching from hotplug detection to polling\n", | |
c23cc417 | 910 | connector->name); |
cd569aed EE |
911 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED; |
912 | connector->polled = DRM_CONNECTOR_POLL_CONNECT | |
913 | | DRM_CONNECTOR_POLL_DISCONNECT; | |
914 | hpd_disabled = true; | |
915 | } | |
142e2398 EE |
916 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { |
917 | DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n", | |
c23cc417 | 918 | connector->name, intel_encoder->hpd_pin); |
142e2398 | 919 | } |
cd569aed EE |
920 | } |
921 | /* if there were no outputs to poll, poll was disabled, | |
922 | * therefore make sure it's enabled when disabling HPD on | |
923 | * some connectors */ | |
ac4c16c5 | 924 | if (hpd_disabled) { |
cd569aed | 925 | drm_kms_helper_poll_enable(dev); |
6323751d ID |
926 | mod_delayed_work(system_wq, &dev_priv->hotplug_reenable_work, |
927 | msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY)); | |
ac4c16c5 | 928 | } |
cd569aed | 929 | |
4cb21832 | 930 | spin_unlock_irq(&dev_priv->irq_lock); |
cd569aed | 931 | |
321a1b30 EE |
932 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
933 | intel_connector = to_intel_connector(connector); | |
36cd7444 DA |
934 | if (!intel_connector->encoder) |
935 | continue; | |
321a1b30 EE |
936 | intel_encoder = intel_connector->encoder; |
937 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { | |
938 | if (intel_encoder->hot_plug) | |
939 | intel_encoder->hot_plug(intel_encoder); | |
940 | if (intel_hpd_irq_event(dev, connector)) | |
941 | changed = true; | |
942 | } | |
943 | } | |
40ee3381 KP |
944 | mutex_unlock(&mode_config->mutex); |
945 | ||
321a1b30 EE |
946 | if (changed) |
947 | drm_kms_helper_hotplug_event(dev); | |
5ca58282 JB |
948 | } |
949 | ||
d0ecd7e2 | 950 | static void ironlake_rps_change_irq_handler(struct drm_device *dev) |
f97108d1 | 951 | { |
2d1013dd | 952 | struct drm_i915_private *dev_priv = dev->dev_private; |
b5b72e89 | 953 | u32 busy_up, busy_down, max_avg, min_avg; |
9270388e | 954 | u8 new_delay; |
9270388e | 955 | |
d0ecd7e2 | 956 | spin_lock(&mchdev_lock); |
f97108d1 | 957 | |
73edd18f DV |
958 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
959 | ||
20e4d407 | 960 | new_delay = dev_priv->ips.cur_delay; |
9270388e | 961 | |
7648fa99 | 962 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
963 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
964 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
965 | max_avg = I915_READ(RCBMAXAVG); |
966 | min_avg = I915_READ(RCBMINAVG); | |
967 | ||
968 | /* Handle RCS change request from hw */ | |
b5b72e89 | 969 | if (busy_up > max_avg) { |
20e4d407 DV |
970 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
971 | new_delay = dev_priv->ips.cur_delay - 1; | |
972 | if (new_delay < dev_priv->ips.max_delay) | |
973 | new_delay = dev_priv->ips.max_delay; | |
b5b72e89 | 974 | } else if (busy_down < min_avg) { |
20e4d407 DV |
975 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
976 | new_delay = dev_priv->ips.cur_delay + 1; | |
977 | if (new_delay > dev_priv->ips.min_delay) | |
978 | new_delay = dev_priv->ips.min_delay; | |
f97108d1 JB |
979 | } |
980 | ||
7648fa99 | 981 | if (ironlake_set_drps(dev, new_delay)) |
20e4d407 | 982 | dev_priv->ips.cur_delay = new_delay; |
f97108d1 | 983 | |
d0ecd7e2 | 984 | spin_unlock(&mchdev_lock); |
9270388e | 985 | |
f97108d1 JB |
986 | return; |
987 | } | |
988 | ||
549f7365 | 989 | static void notify_ring(struct drm_device *dev, |
a4872ba6 | 990 | struct intel_engine_cs *ring) |
549f7365 | 991 | { |
93b0a4e0 | 992 | if (!intel_ring_initialized(ring)) |
475553de CW |
993 | return; |
994 | ||
bcfcc8ba | 995 | trace_i915_gem_request_notify(ring); |
9862e600 | 996 | |
549f7365 | 997 | wake_up_all(&ring->irq_queue); |
549f7365 CW |
998 | } |
999 | ||
43cf3bf0 CW |
1000 | static void vlv_c0_read(struct drm_i915_private *dev_priv, |
1001 | struct intel_rps_ei *ei) | |
31685c25 | 1002 | { |
43cf3bf0 CW |
1003 | ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP); |
1004 | ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT); | |
1005 | ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT); | |
1006 | } | |
31685c25 | 1007 | |
43cf3bf0 CW |
1008 | static bool vlv_c0_above(struct drm_i915_private *dev_priv, |
1009 | const struct intel_rps_ei *old, | |
1010 | const struct intel_rps_ei *now, | |
1011 | int threshold) | |
1012 | { | |
1013 | u64 time, c0; | |
31685c25 | 1014 | |
43cf3bf0 CW |
1015 | if (old->cz_clock == 0) |
1016 | return false; | |
31685c25 | 1017 | |
43cf3bf0 CW |
1018 | time = now->cz_clock - old->cz_clock; |
1019 | time *= threshold * dev_priv->mem_freq; | |
31685c25 | 1020 | |
43cf3bf0 CW |
1021 | /* Workload can be split between render + media, e.g. SwapBuffers |
1022 | * being blitted in X after being rendered in mesa. To account for | |
1023 | * this we need to combine both engines into our activity counter. | |
31685c25 | 1024 | */ |
43cf3bf0 CW |
1025 | c0 = now->render_c0 - old->render_c0; |
1026 | c0 += now->media_c0 - old->media_c0; | |
1027 | c0 *= 100 * VLV_CZ_CLOCK_TO_MILLI_SEC * 4 / 1000; | |
31685c25 | 1028 | |
43cf3bf0 | 1029 | return c0 >= time; |
31685c25 D |
1030 | } |
1031 | ||
43cf3bf0 | 1032 | void gen6_rps_reset_ei(struct drm_i915_private *dev_priv) |
31685c25 | 1033 | { |
43cf3bf0 CW |
1034 | vlv_c0_read(dev_priv, &dev_priv->rps.down_ei); |
1035 | dev_priv->rps.up_ei = dev_priv->rps.down_ei; | |
43cf3bf0 | 1036 | } |
31685c25 | 1037 | |
43cf3bf0 CW |
1038 | static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir) |
1039 | { | |
1040 | struct intel_rps_ei now; | |
1041 | u32 events = 0; | |
31685c25 | 1042 | |
6f4b12f8 | 1043 | if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0) |
43cf3bf0 | 1044 | return 0; |
31685c25 | 1045 | |
43cf3bf0 CW |
1046 | vlv_c0_read(dev_priv, &now); |
1047 | if (now.cz_clock == 0) | |
1048 | return 0; | |
31685c25 | 1049 | |
43cf3bf0 CW |
1050 | if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) { |
1051 | if (!vlv_c0_above(dev_priv, | |
1052 | &dev_priv->rps.down_ei, &now, | |
1053 | VLV_RP_DOWN_EI_THRESHOLD)) | |
1054 | events |= GEN6_PM_RP_DOWN_THRESHOLD; | |
1055 | dev_priv->rps.down_ei = now; | |
1056 | } | |
31685c25 | 1057 | |
43cf3bf0 CW |
1058 | if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) { |
1059 | if (vlv_c0_above(dev_priv, | |
1060 | &dev_priv->rps.up_ei, &now, | |
1061 | VLV_RP_UP_EI_THRESHOLD)) | |
1062 | events |= GEN6_PM_RP_UP_THRESHOLD; | |
1063 | dev_priv->rps.up_ei = now; | |
31685c25 D |
1064 | } |
1065 | ||
43cf3bf0 | 1066 | return events; |
31685c25 D |
1067 | } |
1068 | ||
4912d041 | 1069 | static void gen6_pm_rps_work(struct work_struct *work) |
3b8d8d91 | 1070 | { |
2d1013dd JN |
1071 | struct drm_i915_private *dev_priv = |
1072 | container_of(work, struct drm_i915_private, rps.work); | |
edbfdb45 | 1073 | u32 pm_iir; |
dd75fdc8 | 1074 | int new_delay, adj; |
4912d041 | 1075 | |
59cdb63d | 1076 | spin_lock_irq(&dev_priv->irq_lock); |
d4d70aa5 ID |
1077 | /* Speed up work cancelation during disabling rps interrupts. */ |
1078 | if (!dev_priv->rps.interrupts_enabled) { | |
1079 | spin_unlock_irq(&dev_priv->irq_lock); | |
1080 | return; | |
1081 | } | |
c6a828d3 DV |
1082 | pm_iir = dev_priv->rps.pm_iir; |
1083 | dev_priv->rps.pm_iir = 0; | |
a72fbc3a ID |
1084 | /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */ |
1085 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); | |
59cdb63d | 1086 | spin_unlock_irq(&dev_priv->irq_lock); |
3b8d8d91 | 1087 | |
60611c13 | 1088 | /* Make sure we didn't queue anything we're not going to process. */ |
a6706b45 | 1089 | WARN_ON(pm_iir & ~dev_priv->pm_rps_events); |
60611c13 | 1090 | |
a6706b45 | 1091 | if ((pm_iir & dev_priv->pm_rps_events) == 0) |
3b8d8d91 JB |
1092 | return; |
1093 | ||
4fc688ce | 1094 | mutex_lock(&dev_priv->rps.hw_lock); |
7b9e0ae6 | 1095 | |
43cf3bf0 CW |
1096 | pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir); |
1097 | ||
dd75fdc8 | 1098 | adj = dev_priv->rps.last_adj; |
7425034a | 1099 | if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { |
dd75fdc8 CW |
1100 | if (adj > 0) |
1101 | adj *= 2; | |
13a5660c D |
1102 | else { |
1103 | /* CHV needs even encode values */ | |
1104 | adj = IS_CHERRYVIEW(dev_priv->dev) ? 2 : 1; | |
1105 | } | |
b39fb297 | 1106 | new_delay = dev_priv->rps.cur_freq + adj; |
7425034a VS |
1107 | |
1108 | /* | |
1109 | * For better performance, jump directly | |
1110 | * to RPe if we're below it. | |
1111 | */ | |
b39fb297 BW |
1112 | if (new_delay < dev_priv->rps.efficient_freq) |
1113 | new_delay = dev_priv->rps.efficient_freq; | |
dd75fdc8 | 1114 | } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { |
b39fb297 BW |
1115 | if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq) |
1116 | new_delay = dev_priv->rps.efficient_freq; | |
dd75fdc8 | 1117 | else |
b39fb297 | 1118 | new_delay = dev_priv->rps.min_freq_softlimit; |
dd75fdc8 CW |
1119 | adj = 0; |
1120 | } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { | |
1121 | if (adj < 0) | |
1122 | adj *= 2; | |
13a5660c D |
1123 | else { |
1124 | /* CHV needs even encode values */ | |
1125 | adj = IS_CHERRYVIEW(dev_priv->dev) ? -2 : -1; | |
1126 | } | |
b39fb297 | 1127 | new_delay = dev_priv->rps.cur_freq + adj; |
dd75fdc8 | 1128 | } else { /* unknown event */ |
b39fb297 | 1129 | new_delay = dev_priv->rps.cur_freq; |
dd75fdc8 | 1130 | } |
3b8d8d91 | 1131 | |
79249636 BW |
1132 | /* sysfs frequency interfaces may have snuck in while servicing the |
1133 | * interrupt | |
1134 | */ | |
1272e7b8 | 1135 | new_delay = clamp_t(int, new_delay, |
b39fb297 BW |
1136 | dev_priv->rps.min_freq_softlimit, |
1137 | dev_priv->rps.max_freq_softlimit); | |
27544369 | 1138 | |
b39fb297 | 1139 | dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq; |
dd75fdc8 | 1140 | |
ffe02b40 | 1141 | intel_set_rps(dev_priv->dev, new_delay); |
3b8d8d91 | 1142 | |
4fc688ce | 1143 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 JB |
1144 | } |
1145 | ||
e3689190 BW |
1146 | |
1147 | /** | |
1148 | * ivybridge_parity_work - Workqueue called when a parity error interrupt | |
1149 | * occurred. | |
1150 | * @work: workqueue struct | |
1151 | * | |
1152 | * Doesn't actually do anything except notify userspace. As a consequence of | |
1153 | * this event, userspace should try to remap the bad rows since statistically | |
1154 | * it is likely the same row is more likely to go bad again. | |
1155 | */ | |
1156 | static void ivybridge_parity_work(struct work_struct *work) | |
1157 | { | |
2d1013dd JN |
1158 | struct drm_i915_private *dev_priv = |
1159 | container_of(work, struct drm_i915_private, l3_parity.error_work); | |
e3689190 | 1160 | u32 error_status, row, bank, subbank; |
35a85ac6 | 1161 | char *parity_event[6]; |
e3689190 | 1162 | uint32_t misccpctl; |
35a85ac6 | 1163 | uint8_t slice = 0; |
e3689190 BW |
1164 | |
1165 | /* We must turn off DOP level clock gating to access the L3 registers. | |
1166 | * In order to prevent a get/put style interface, acquire struct mutex | |
1167 | * any time we access those registers. | |
1168 | */ | |
1169 | mutex_lock(&dev_priv->dev->struct_mutex); | |
1170 | ||
35a85ac6 BW |
1171 | /* If we've screwed up tracking, just let the interrupt fire again */ |
1172 | if (WARN_ON(!dev_priv->l3_parity.which_slice)) | |
1173 | goto out; | |
1174 | ||
e3689190 BW |
1175 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
1176 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
1177 | POSTING_READ(GEN7_MISCCPCTL); | |
1178 | ||
35a85ac6 BW |
1179 | while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { |
1180 | u32 reg; | |
e3689190 | 1181 | |
35a85ac6 BW |
1182 | slice--; |
1183 | if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev))) | |
1184 | break; | |
e3689190 | 1185 | |
35a85ac6 | 1186 | dev_priv->l3_parity.which_slice &= ~(1<<slice); |
e3689190 | 1187 | |
35a85ac6 | 1188 | reg = GEN7_L3CDERRST1 + (slice * 0x200); |
e3689190 | 1189 | |
35a85ac6 BW |
1190 | error_status = I915_READ(reg); |
1191 | row = GEN7_PARITY_ERROR_ROW(error_status); | |
1192 | bank = GEN7_PARITY_ERROR_BANK(error_status); | |
1193 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); | |
1194 | ||
1195 | I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); | |
1196 | POSTING_READ(reg); | |
1197 | ||
1198 | parity_event[0] = I915_L3_PARITY_UEVENT "=1"; | |
1199 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); | |
1200 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); | |
1201 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); | |
1202 | parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); | |
1203 | parity_event[5] = NULL; | |
1204 | ||
5bdebb18 | 1205 | kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj, |
35a85ac6 | 1206 | KOBJ_CHANGE, parity_event); |
e3689190 | 1207 | |
35a85ac6 BW |
1208 | DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", |
1209 | slice, row, bank, subbank); | |
e3689190 | 1210 | |
35a85ac6 BW |
1211 | kfree(parity_event[4]); |
1212 | kfree(parity_event[3]); | |
1213 | kfree(parity_event[2]); | |
1214 | kfree(parity_event[1]); | |
1215 | } | |
e3689190 | 1216 | |
35a85ac6 | 1217 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
e3689190 | 1218 | |
35a85ac6 BW |
1219 | out: |
1220 | WARN_ON(dev_priv->l3_parity.which_slice); | |
4cb21832 | 1221 | spin_lock_irq(&dev_priv->irq_lock); |
480c8033 | 1222 | gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev)); |
4cb21832 | 1223 | spin_unlock_irq(&dev_priv->irq_lock); |
35a85ac6 BW |
1224 | |
1225 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
e3689190 BW |
1226 | } |
1227 | ||
35a85ac6 | 1228 | static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir) |
e3689190 | 1229 | { |
2d1013dd | 1230 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3689190 | 1231 | |
040d2baa | 1232 | if (!HAS_L3_DPF(dev)) |
e3689190 BW |
1233 | return; |
1234 | ||
d0ecd7e2 | 1235 | spin_lock(&dev_priv->irq_lock); |
480c8033 | 1236 | gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev)); |
d0ecd7e2 | 1237 | spin_unlock(&dev_priv->irq_lock); |
e3689190 | 1238 | |
35a85ac6 BW |
1239 | iir &= GT_PARITY_ERROR(dev); |
1240 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) | |
1241 | dev_priv->l3_parity.which_slice |= 1 << 1; | |
1242 | ||
1243 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) | |
1244 | dev_priv->l3_parity.which_slice |= 1 << 0; | |
1245 | ||
a4da4fa4 | 1246 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
e3689190 BW |
1247 | } |
1248 | ||
f1af8fc1 PZ |
1249 | static void ilk_gt_irq_handler(struct drm_device *dev, |
1250 | struct drm_i915_private *dev_priv, | |
1251 | u32 gt_iir) | |
1252 | { | |
1253 | if (gt_iir & | |
1254 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
1255 | notify_ring(dev, &dev_priv->ring[RCS]); | |
1256 | if (gt_iir & ILK_BSD_USER_INTERRUPT) | |
1257 | notify_ring(dev, &dev_priv->ring[VCS]); | |
1258 | } | |
1259 | ||
e7b4c6b1 DV |
1260 | static void snb_gt_irq_handler(struct drm_device *dev, |
1261 | struct drm_i915_private *dev_priv, | |
1262 | u32 gt_iir) | |
1263 | { | |
1264 | ||
cc609d5d BW |
1265 | if (gt_iir & |
1266 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
e7b4c6b1 | 1267 | notify_ring(dev, &dev_priv->ring[RCS]); |
cc609d5d | 1268 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
e7b4c6b1 | 1269 | notify_ring(dev, &dev_priv->ring[VCS]); |
cc609d5d | 1270 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
e7b4c6b1 DV |
1271 | notify_ring(dev, &dev_priv->ring[BCS]); |
1272 | ||
cc609d5d BW |
1273 | if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | |
1274 | GT_BSD_CS_ERROR_INTERRUPT | | |
aaecdf61 DV |
1275 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) |
1276 | DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir); | |
e3689190 | 1277 | |
35a85ac6 BW |
1278 | if (gt_iir & GT_PARITY_ERROR(dev)) |
1279 | ivybridge_parity_error_irq_handler(dev, gt_iir); | |
e7b4c6b1 DV |
1280 | } |
1281 | ||
abd58f01 BW |
1282 | static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev, |
1283 | struct drm_i915_private *dev_priv, | |
1284 | u32 master_ctl) | |
1285 | { | |
e981e7b1 | 1286 | struct intel_engine_cs *ring; |
abd58f01 BW |
1287 | u32 rcs, bcs, vcs; |
1288 | uint32_t tmp = 0; | |
1289 | irqreturn_t ret = IRQ_NONE; | |
1290 | ||
1291 | if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { | |
1292 | tmp = I915_READ(GEN8_GT_IIR(0)); | |
1293 | if (tmp) { | |
38cc46d7 | 1294 | I915_WRITE(GEN8_GT_IIR(0), tmp); |
abd58f01 | 1295 | ret = IRQ_HANDLED; |
e981e7b1 | 1296 | |
abd58f01 | 1297 | rcs = tmp >> GEN8_RCS_IRQ_SHIFT; |
e981e7b1 | 1298 | ring = &dev_priv->ring[RCS]; |
abd58f01 | 1299 | if (rcs & GT_RENDER_USER_INTERRUPT) |
e981e7b1 TD |
1300 | notify_ring(dev, ring); |
1301 | if (rcs & GT_CONTEXT_SWITCH_INTERRUPT) | |
3f7531c3 | 1302 | intel_lrc_irq_handler(ring); |
e981e7b1 TD |
1303 | |
1304 | bcs = tmp >> GEN8_BCS_IRQ_SHIFT; | |
1305 | ring = &dev_priv->ring[BCS]; | |
abd58f01 | 1306 | if (bcs & GT_RENDER_USER_INTERRUPT) |
e981e7b1 TD |
1307 | notify_ring(dev, ring); |
1308 | if (bcs & GT_CONTEXT_SWITCH_INTERRUPT) | |
3f7531c3 | 1309 | intel_lrc_irq_handler(ring); |
abd58f01 BW |
1310 | } else |
1311 | DRM_ERROR("The master control interrupt lied (GT0)!\n"); | |
1312 | } | |
1313 | ||
85f9b5f9 | 1314 | if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) { |
abd58f01 BW |
1315 | tmp = I915_READ(GEN8_GT_IIR(1)); |
1316 | if (tmp) { | |
38cc46d7 | 1317 | I915_WRITE(GEN8_GT_IIR(1), tmp); |
abd58f01 | 1318 | ret = IRQ_HANDLED; |
e981e7b1 | 1319 | |
abd58f01 | 1320 | vcs = tmp >> GEN8_VCS1_IRQ_SHIFT; |
e981e7b1 | 1321 | ring = &dev_priv->ring[VCS]; |
abd58f01 | 1322 | if (vcs & GT_RENDER_USER_INTERRUPT) |
e981e7b1 | 1323 | notify_ring(dev, ring); |
73d477f6 | 1324 | if (vcs & GT_CONTEXT_SWITCH_INTERRUPT) |
3f7531c3 | 1325 | intel_lrc_irq_handler(ring); |
e981e7b1 | 1326 | |
85f9b5f9 | 1327 | vcs = tmp >> GEN8_VCS2_IRQ_SHIFT; |
e981e7b1 | 1328 | ring = &dev_priv->ring[VCS2]; |
85f9b5f9 | 1329 | if (vcs & GT_RENDER_USER_INTERRUPT) |
e981e7b1 | 1330 | notify_ring(dev, ring); |
73d477f6 | 1331 | if (vcs & GT_CONTEXT_SWITCH_INTERRUPT) |
3f7531c3 | 1332 | intel_lrc_irq_handler(ring); |
abd58f01 BW |
1333 | } else |
1334 | DRM_ERROR("The master control interrupt lied (GT1)!\n"); | |
1335 | } | |
1336 | ||
0961021a BW |
1337 | if (master_ctl & GEN8_GT_PM_IRQ) { |
1338 | tmp = I915_READ(GEN8_GT_IIR(2)); | |
1339 | if (tmp & dev_priv->pm_rps_events) { | |
0961021a BW |
1340 | I915_WRITE(GEN8_GT_IIR(2), |
1341 | tmp & dev_priv->pm_rps_events); | |
38cc46d7 | 1342 | ret = IRQ_HANDLED; |
c9a9a268 | 1343 | gen6_rps_irq_handler(dev_priv, tmp); |
0961021a BW |
1344 | } else |
1345 | DRM_ERROR("The master control interrupt lied (PM)!\n"); | |
1346 | } | |
1347 | ||
abd58f01 BW |
1348 | if (master_ctl & GEN8_GT_VECS_IRQ) { |
1349 | tmp = I915_READ(GEN8_GT_IIR(3)); | |
1350 | if (tmp) { | |
38cc46d7 | 1351 | I915_WRITE(GEN8_GT_IIR(3), tmp); |
abd58f01 | 1352 | ret = IRQ_HANDLED; |
e981e7b1 | 1353 | |
abd58f01 | 1354 | vcs = tmp >> GEN8_VECS_IRQ_SHIFT; |
e981e7b1 | 1355 | ring = &dev_priv->ring[VECS]; |
abd58f01 | 1356 | if (vcs & GT_RENDER_USER_INTERRUPT) |
e981e7b1 | 1357 | notify_ring(dev, ring); |
73d477f6 | 1358 | if (vcs & GT_CONTEXT_SWITCH_INTERRUPT) |
3f7531c3 | 1359 | intel_lrc_irq_handler(ring); |
abd58f01 BW |
1360 | } else |
1361 | DRM_ERROR("The master control interrupt lied (GT3)!\n"); | |
1362 | } | |
1363 | ||
1364 | return ret; | |
1365 | } | |
1366 | ||
b543fb04 EE |
1367 | #define HPD_STORM_DETECT_PERIOD 1000 |
1368 | #define HPD_STORM_THRESHOLD 5 | |
1369 | ||
07c338ce | 1370 | static int pch_port_to_hotplug_shift(enum port port) |
13cf5504 DA |
1371 | { |
1372 | switch (port) { | |
1373 | case PORT_A: | |
1374 | case PORT_E: | |
1375 | default: | |
1376 | return -1; | |
1377 | case PORT_B: | |
1378 | return 0; | |
1379 | case PORT_C: | |
1380 | return 8; | |
1381 | case PORT_D: | |
1382 | return 16; | |
1383 | } | |
1384 | } | |
1385 | ||
07c338ce | 1386 | static int i915_port_to_hotplug_shift(enum port port) |
13cf5504 DA |
1387 | { |
1388 | switch (port) { | |
1389 | case PORT_A: | |
1390 | case PORT_E: | |
1391 | default: | |
1392 | return -1; | |
1393 | case PORT_B: | |
1394 | return 17; | |
1395 | case PORT_C: | |
1396 | return 19; | |
1397 | case PORT_D: | |
1398 | return 21; | |
1399 | } | |
1400 | } | |
1401 | ||
1402 | static inline enum port get_port_from_pin(enum hpd_pin pin) | |
1403 | { | |
1404 | switch (pin) { | |
1405 | case HPD_PORT_B: | |
1406 | return PORT_B; | |
1407 | case HPD_PORT_C: | |
1408 | return PORT_C; | |
1409 | case HPD_PORT_D: | |
1410 | return PORT_D; | |
1411 | default: | |
1412 | return PORT_A; /* no hpd */ | |
1413 | } | |
1414 | } | |
1415 | ||
10a504de | 1416 | static inline void intel_hpd_irq_handler(struct drm_device *dev, |
22062dba | 1417 | u32 hotplug_trigger, |
13cf5504 | 1418 | u32 dig_hotplug_reg, |
7c7e10db | 1419 | const u32 hpd[HPD_NUM_PINS]) |
b543fb04 | 1420 | { |
2d1013dd | 1421 | struct drm_i915_private *dev_priv = dev->dev_private; |
b543fb04 | 1422 | int i; |
13cf5504 | 1423 | enum port port; |
10a504de | 1424 | bool storm_detected = false; |
13cf5504 DA |
1425 | bool queue_dig = false, queue_hp = false; |
1426 | u32 dig_shift; | |
1427 | u32 dig_port_mask = 0; | |
b543fb04 | 1428 | |
91d131d2 DV |
1429 | if (!hotplug_trigger) |
1430 | return; | |
1431 | ||
13cf5504 DA |
1432 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x\n", |
1433 | hotplug_trigger, dig_hotplug_reg); | |
cc9bd499 | 1434 | |
b5ea2d56 | 1435 | spin_lock(&dev_priv->irq_lock); |
b543fb04 | 1436 | for (i = 1; i < HPD_NUM_PINS; i++) { |
13cf5504 DA |
1437 | if (!(hpd[i] & hotplug_trigger)) |
1438 | continue; | |
1439 | ||
1440 | port = get_port_from_pin(i); | |
1441 | if (port && dev_priv->hpd_irq_port[port]) { | |
1442 | bool long_hpd; | |
1443 | ||
07c338ce JN |
1444 | if (HAS_PCH_SPLIT(dev)) { |
1445 | dig_shift = pch_port_to_hotplug_shift(port); | |
13cf5504 | 1446 | long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT; |
07c338ce JN |
1447 | } else { |
1448 | dig_shift = i915_port_to_hotplug_shift(port); | |
1449 | long_hpd = (hotplug_trigger >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT; | |
13cf5504 DA |
1450 | } |
1451 | ||
26fbb774 VS |
1452 | DRM_DEBUG_DRIVER("digital hpd port %c - %s\n", |
1453 | port_name(port), | |
1454 | long_hpd ? "long" : "short"); | |
13cf5504 DA |
1455 | /* for long HPD pulses we want to have the digital queue happen, |
1456 | but we still want HPD storm detection to function. */ | |
1457 | if (long_hpd) { | |
1458 | dev_priv->long_hpd_port_mask |= (1 << port); | |
1459 | dig_port_mask |= hpd[i]; | |
1460 | } else { | |
1461 | /* for short HPD just trigger the digital queue */ | |
1462 | dev_priv->short_hpd_port_mask |= (1 << port); | |
1463 | hotplug_trigger &= ~hpd[i]; | |
1464 | } | |
1465 | queue_dig = true; | |
1466 | } | |
1467 | } | |
821450c6 | 1468 | |
13cf5504 | 1469 | for (i = 1; i < HPD_NUM_PINS; i++) { |
3ff04a16 DV |
1470 | if (hpd[i] & hotplug_trigger && |
1471 | dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) { | |
1472 | /* | |
1473 | * On GMCH platforms the interrupt mask bits only | |
1474 | * prevent irq generation, not the setting of the | |
1475 | * hotplug bits itself. So only WARN about unexpected | |
1476 | * interrupts on saner platforms. | |
1477 | */ | |
1478 | WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev), | |
1479 | "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n", | |
1480 | hotplug_trigger, i, hpd[i]); | |
1481 | ||
1482 | continue; | |
1483 | } | |
b8f102e8 | 1484 | |
b543fb04 EE |
1485 | if (!(hpd[i] & hotplug_trigger) || |
1486 | dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED) | |
1487 | continue; | |
1488 | ||
13cf5504 DA |
1489 | if (!(dig_port_mask & hpd[i])) { |
1490 | dev_priv->hpd_event_bits |= (1 << i); | |
1491 | queue_hp = true; | |
1492 | } | |
1493 | ||
b543fb04 EE |
1494 | if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies, |
1495 | dev_priv->hpd_stats[i].hpd_last_jiffies | |
1496 | + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) { | |
1497 | dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies; | |
1498 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
b8f102e8 | 1499 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i); |
b543fb04 EE |
1500 | } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) { |
1501 | dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED; | |
142e2398 | 1502 | dev_priv->hpd_event_bits &= ~(1 << i); |
b543fb04 | 1503 | DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i); |
10a504de | 1504 | storm_detected = true; |
b543fb04 EE |
1505 | } else { |
1506 | dev_priv->hpd_stats[i].hpd_cnt++; | |
b8f102e8 EE |
1507 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i, |
1508 | dev_priv->hpd_stats[i].hpd_cnt); | |
b543fb04 EE |
1509 | } |
1510 | } | |
1511 | ||
10a504de DV |
1512 | if (storm_detected) |
1513 | dev_priv->display.hpd_irq_setup(dev); | |
b5ea2d56 | 1514 | spin_unlock(&dev_priv->irq_lock); |
5876fa0d | 1515 | |
645416f5 DV |
1516 | /* |
1517 | * Our hotplug handler can grab modeset locks (by calling down into the | |
1518 | * fb helpers). Hence it must not be run on our own dev-priv->wq work | |
1519 | * queue for otherwise the flush_work in the pageflip code will | |
1520 | * deadlock. | |
1521 | */ | |
13cf5504 | 1522 | if (queue_dig) |
0e32b39c | 1523 | queue_work(dev_priv->dp_wq, &dev_priv->dig_port_work); |
13cf5504 DA |
1524 | if (queue_hp) |
1525 | schedule_work(&dev_priv->hotplug_work); | |
b543fb04 EE |
1526 | } |
1527 | ||
515ac2bb DV |
1528 | static void gmbus_irq_handler(struct drm_device *dev) |
1529 | { | |
2d1013dd | 1530 | struct drm_i915_private *dev_priv = dev->dev_private; |
28c70f16 | 1531 | |
28c70f16 | 1532 | wake_up_all(&dev_priv->gmbus_wait_queue); |
515ac2bb DV |
1533 | } |
1534 | ||
ce99c256 DV |
1535 | static void dp_aux_irq_handler(struct drm_device *dev) |
1536 | { | |
2d1013dd | 1537 | struct drm_i915_private *dev_priv = dev->dev_private; |
9ee32fea | 1538 | |
9ee32fea | 1539 | wake_up_all(&dev_priv->gmbus_wait_queue); |
ce99c256 DV |
1540 | } |
1541 | ||
8bf1e9f1 | 1542 | #if defined(CONFIG_DEBUG_FS) |
277de95e DV |
1543 | static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, |
1544 | uint32_t crc0, uint32_t crc1, | |
1545 | uint32_t crc2, uint32_t crc3, | |
1546 | uint32_t crc4) | |
8bf1e9f1 SH |
1547 | { |
1548 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1549 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; | |
1550 | struct intel_pipe_crc_entry *entry; | |
ac2300d4 | 1551 | int head, tail; |
b2c88f5b | 1552 | |
d538bbdf DL |
1553 | spin_lock(&pipe_crc->lock); |
1554 | ||
0c912c79 | 1555 | if (!pipe_crc->entries) { |
d538bbdf | 1556 | spin_unlock(&pipe_crc->lock); |
34273620 | 1557 | DRM_DEBUG_KMS("spurious interrupt\n"); |
0c912c79 DL |
1558 | return; |
1559 | } | |
1560 | ||
d538bbdf DL |
1561 | head = pipe_crc->head; |
1562 | tail = pipe_crc->tail; | |
b2c88f5b DL |
1563 | |
1564 | if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { | |
d538bbdf | 1565 | spin_unlock(&pipe_crc->lock); |
b2c88f5b DL |
1566 | DRM_ERROR("CRC buffer overflowing\n"); |
1567 | return; | |
1568 | } | |
1569 | ||
1570 | entry = &pipe_crc->entries[head]; | |
8bf1e9f1 | 1571 | |
8bc5e955 | 1572 | entry->frame = dev->driver->get_vblank_counter(dev, pipe); |
eba94eb9 DV |
1573 | entry->crc[0] = crc0; |
1574 | entry->crc[1] = crc1; | |
1575 | entry->crc[2] = crc2; | |
1576 | entry->crc[3] = crc3; | |
1577 | entry->crc[4] = crc4; | |
b2c88f5b DL |
1578 | |
1579 | head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
d538bbdf DL |
1580 | pipe_crc->head = head; |
1581 | ||
1582 | spin_unlock(&pipe_crc->lock); | |
07144428 DL |
1583 | |
1584 | wake_up_interruptible(&pipe_crc->wq); | |
8bf1e9f1 | 1585 | } |
277de95e DV |
1586 | #else |
1587 | static inline void | |
1588 | display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, | |
1589 | uint32_t crc0, uint32_t crc1, | |
1590 | uint32_t crc2, uint32_t crc3, | |
1591 | uint32_t crc4) {} | |
1592 | #endif | |
1593 | ||
eba94eb9 | 1594 | |
277de95e | 1595 | static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5a69b89f DV |
1596 | { |
1597 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1598 | ||
277de95e DV |
1599 | display_pipe_crc_irq_handler(dev, pipe, |
1600 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1601 | 0, 0, 0, 0); | |
5a69b89f DV |
1602 | } |
1603 | ||
277de95e | 1604 | static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
eba94eb9 DV |
1605 | { |
1606 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1607 | ||
277de95e DV |
1608 | display_pipe_crc_irq_handler(dev, pipe, |
1609 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1610 | I915_READ(PIPE_CRC_RES_2_IVB(pipe)), | |
1611 | I915_READ(PIPE_CRC_RES_3_IVB(pipe)), | |
1612 | I915_READ(PIPE_CRC_RES_4_IVB(pipe)), | |
1613 | I915_READ(PIPE_CRC_RES_5_IVB(pipe))); | |
eba94eb9 | 1614 | } |
5b3a856b | 1615 | |
277de95e | 1616 | static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5b3a856b DV |
1617 | { |
1618 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0b5c5ed0 DV |
1619 | uint32_t res1, res2; |
1620 | ||
1621 | if (INTEL_INFO(dev)->gen >= 3) | |
1622 | res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); | |
1623 | else | |
1624 | res1 = 0; | |
1625 | ||
1626 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
1627 | res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); | |
1628 | else | |
1629 | res2 = 0; | |
5b3a856b | 1630 | |
277de95e DV |
1631 | display_pipe_crc_irq_handler(dev, pipe, |
1632 | I915_READ(PIPE_CRC_RES_RED(pipe)), | |
1633 | I915_READ(PIPE_CRC_RES_GREEN(pipe)), | |
1634 | I915_READ(PIPE_CRC_RES_BLUE(pipe)), | |
1635 | res1, res2); | |
5b3a856b | 1636 | } |
8bf1e9f1 | 1637 | |
1403c0d4 PZ |
1638 | /* The RPS events need forcewake, so we add them to a work queue and mask their |
1639 | * IMR bits until the work is done. Other interrupts can be processed without | |
1640 | * the work queue. */ | |
1641 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) | |
baf02a1f | 1642 | { |
a6706b45 | 1643 | if (pm_iir & dev_priv->pm_rps_events) { |
59cdb63d | 1644 | spin_lock(&dev_priv->irq_lock); |
480c8033 | 1645 | gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); |
d4d70aa5 ID |
1646 | if (dev_priv->rps.interrupts_enabled) { |
1647 | dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; | |
1648 | queue_work(dev_priv->wq, &dev_priv->rps.work); | |
1649 | } | |
59cdb63d | 1650 | spin_unlock(&dev_priv->irq_lock); |
baf02a1f | 1651 | } |
baf02a1f | 1652 | |
c9a9a268 ID |
1653 | if (INTEL_INFO(dev_priv)->gen >= 8) |
1654 | return; | |
1655 | ||
1403c0d4 PZ |
1656 | if (HAS_VEBOX(dev_priv->dev)) { |
1657 | if (pm_iir & PM_VEBOX_USER_INTERRUPT) | |
1658 | notify_ring(dev_priv->dev, &dev_priv->ring[VECS]); | |
12638c57 | 1659 | |
aaecdf61 DV |
1660 | if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) |
1661 | DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir); | |
12638c57 | 1662 | } |
baf02a1f BW |
1663 | } |
1664 | ||
8d7849db VS |
1665 | static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe) |
1666 | { | |
8d7849db VS |
1667 | if (!drm_handle_vblank(dev, pipe)) |
1668 | return false; | |
1669 | ||
8d7849db VS |
1670 | return true; |
1671 | } | |
1672 | ||
c1874ed7 ID |
1673 | static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir) |
1674 | { | |
1675 | struct drm_i915_private *dev_priv = dev->dev_private; | |
91d181dd | 1676 | u32 pipe_stats[I915_MAX_PIPES] = { }; |
c1874ed7 ID |
1677 | int pipe; |
1678 | ||
58ead0d7 | 1679 | spin_lock(&dev_priv->irq_lock); |
055e393f | 1680 | for_each_pipe(dev_priv, pipe) { |
91d181dd | 1681 | int reg; |
bbb5eebf | 1682 | u32 mask, iir_bit = 0; |
91d181dd | 1683 | |
bbb5eebf DV |
1684 | /* |
1685 | * PIPESTAT bits get signalled even when the interrupt is | |
1686 | * disabled with the mask bits, and some of the status bits do | |
1687 | * not generate interrupts at all (like the underrun bit). Hence | |
1688 | * we need to be careful that we only handle what we want to | |
1689 | * handle. | |
1690 | */ | |
0f239f4c DV |
1691 | |
1692 | /* fifo underruns are filterered in the underrun handler. */ | |
1693 | mask = PIPE_FIFO_UNDERRUN_STATUS; | |
bbb5eebf DV |
1694 | |
1695 | switch (pipe) { | |
1696 | case PIPE_A: | |
1697 | iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; | |
1698 | break; | |
1699 | case PIPE_B: | |
1700 | iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
1701 | break; | |
3278f67f VS |
1702 | case PIPE_C: |
1703 | iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
1704 | break; | |
bbb5eebf DV |
1705 | } |
1706 | if (iir & iir_bit) | |
1707 | mask |= dev_priv->pipestat_irq_mask[pipe]; | |
1708 | ||
1709 | if (!mask) | |
91d181dd ID |
1710 | continue; |
1711 | ||
1712 | reg = PIPESTAT(pipe); | |
bbb5eebf DV |
1713 | mask |= PIPESTAT_INT_ENABLE_MASK; |
1714 | pipe_stats[pipe] = I915_READ(reg) & mask; | |
c1874ed7 ID |
1715 | |
1716 | /* | |
1717 | * Clear the PIPE*STAT regs before the IIR | |
1718 | */ | |
91d181dd ID |
1719 | if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS | |
1720 | PIPESTAT_INT_STATUS_MASK)) | |
c1874ed7 ID |
1721 | I915_WRITE(reg, pipe_stats[pipe]); |
1722 | } | |
58ead0d7 | 1723 | spin_unlock(&dev_priv->irq_lock); |
c1874ed7 | 1724 | |
055e393f | 1725 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
1726 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
1727 | intel_pipe_handle_vblank(dev, pipe)) | |
1728 | intel_check_page_flip(dev, pipe); | |
c1874ed7 | 1729 | |
579a9b0e | 1730 | if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) { |
c1874ed7 ID |
1731 | intel_prepare_page_flip(dev, pipe); |
1732 | intel_finish_page_flip(dev, pipe); | |
1733 | } | |
1734 | ||
1735 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
1736 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
1737 | ||
1f7247c0 DV |
1738 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
1739 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
c1874ed7 ID |
1740 | } |
1741 | ||
1742 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) | |
1743 | gmbus_irq_handler(dev); | |
1744 | } | |
1745 | ||
16c6c56b VS |
1746 | static void i9xx_hpd_irq_handler(struct drm_device *dev) |
1747 | { | |
1748 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1749 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
1750 | ||
3ff60f89 OM |
1751 | if (hotplug_status) { |
1752 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
1753 | /* | |
1754 | * Make sure hotplug status is cleared before we clear IIR, or else we | |
1755 | * may miss hotplug events. | |
1756 | */ | |
1757 | POSTING_READ(PORT_HOTPLUG_STAT); | |
16c6c56b | 1758 | |
3ff60f89 OM |
1759 | if (IS_G4X(dev)) { |
1760 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; | |
16c6c56b | 1761 | |
13cf5504 | 1762 | intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_g4x); |
3ff60f89 OM |
1763 | } else { |
1764 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; | |
16c6c56b | 1765 | |
13cf5504 | 1766 | intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_i915); |
3ff60f89 | 1767 | } |
16c6c56b | 1768 | |
3ff60f89 OM |
1769 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && |
1770 | hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) | |
1771 | dp_aux_irq_handler(dev); | |
1772 | } | |
16c6c56b VS |
1773 | } |
1774 | ||
ff1f525e | 1775 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
7e231dbe | 1776 | { |
45a83f84 | 1777 | struct drm_device *dev = arg; |
2d1013dd | 1778 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
1779 | u32 iir, gt_iir, pm_iir; |
1780 | irqreturn_t ret = IRQ_NONE; | |
7e231dbe | 1781 | |
2dd2a883 ID |
1782 | if (!intel_irqs_enabled(dev_priv)) |
1783 | return IRQ_NONE; | |
1784 | ||
7e231dbe | 1785 | while (true) { |
3ff60f89 OM |
1786 | /* Find, clear, then process each source of interrupt */ |
1787 | ||
7e231dbe | 1788 | gt_iir = I915_READ(GTIIR); |
3ff60f89 OM |
1789 | if (gt_iir) |
1790 | I915_WRITE(GTIIR, gt_iir); | |
1791 | ||
7e231dbe | 1792 | pm_iir = I915_READ(GEN6_PMIIR); |
3ff60f89 OM |
1793 | if (pm_iir) |
1794 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
1795 | ||
1796 | iir = I915_READ(VLV_IIR); | |
1797 | if (iir) { | |
1798 | /* Consume port before clearing IIR or we'll miss events */ | |
1799 | if (iir & I915_DISPLAY_PORT_INTERRUPT) | |
1800 | i9xx_hpd_irq_handler(dev); | |
1801 | I915_WRITE(VLV_IIR, iir); | |
1802 | } | |
7e231dbe JB |
1803 | |
1804 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) | |
1805 | goto out; | |
1806 | ||
1807 | ret = IRQ_HANDLED; | |
1808 | ||
3ff60f89 OM |
1809 | if (gt_iir) |
1810 | snb_gt_irq_handler(dev, dev_priv, gt_iir); | |
60611c13 | 1811 | if (pm_iir) |
d0ecd7e2 | 1812 | gen6_rps_irq_handler(dev_priv, pm_iir); |
3ff60f89 OM |
1813 | /* Call regardless, as some status bits might not be |
1814 | * signalled in iir */ | |
1815 | valleyview_pipestat_irq_handler(dev, iir); | |
7e231dbe JB |
1816 | } |
1817 | ||
1818 | out: | |
1819 | return ret; | |
1820 | } | |
1821 | ||
43f328d7 VS |
1822 | static irqreturn_t cherryview_irq_handler(int irq, void *arg) |
1823 | { | |
45a83f84 | 1824 | struct drm_device *dev = arg; |
43f328d7 VS |
1825 | struct drm_i915_private *dev_priv = dev->dev_private; |
1826 | u32 master_ctl, iir; | |
1827 | irqreturn_t ret = IRQ_NONE; | |
43f328d7 | 1828 | |
2dd2a883 ID |
1829 | if (!intel_irqs_enabled(dev_priv)) |
1830 | return IRQ_NONE; | |
1831 | ||
8e5fd599 VS |
1832 | for (;;) { |
1833 | master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; | |
1834 | iir = I915_READ(VLV_IIR); | |
43f328d7 | 1835 | |
8e5fd599 VS |
1836 | if (master_ctl == 0 && iir == 0) |
1837 | break; | |
43f328d7 | 1838 | |
27b6c122 OM |
1839 | ret = IRQ_HANDLED; |
1840 | ||
8e5fd599 | 1841 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
43f328d7 | 1842 | |
27b6c122 | 1843 | /* Find, clear, then process each source of interrupt */ |
43f328d7 | 1844 | |
27b6c122 OM |
1845 | if (iir) { |
1846 | /* Consume port before clearing IIR or we'll miss events */ | |
1847 | if (iir & I915_DISPLAY_PORT_INTERRUPT) | |
1848 | i9xx_hpd_irq_handler(dev); | |
1849 | I915_WRITE(VLV_IIR, iir); | |
1850 | } | |
43f328d7 | 1851 | |
27b6c122 | 1852 | gen8_gt_irq_handler(dev, dev_priv, master_ctl); |
43f328d7 | 1853 | |
27b6c122 OM |
1854 | /* Call regardless, as some status bits might not be |
1855 | * signalled in iir */ | |
1856 | valleyview_pipestat_irq_handler(dev, iir); | |
43f328d7 | 1857 | |
8e5fd599 VS |
1858 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); |
1859 | POSTING_READ(GEN8_MASTER_IRQ); | |
8e5fd599 | 1860 | } |
3278f67f | 1861 | |
43f328d7 VS |
1862 | return ret; |
1863 | } | |
1864 | ||
23e81d69 | 1865 | static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) |
776ad806 | 1866 | { |
2d1013dd | 1867 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 1868 | int pipe; |
b543fb04 | 1869 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; |
13cf5504 DA |
1870 | u32 dig_hotplug_reg; |
1871 | ||
1872 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); | |
1873 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
776ad806 | 1874 | |
13cf5504 | 1875 | intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_ibx); |
91d131d2 | 1876 | |
cfc33bf7 VS |
1877 | if (pch_iir & SDE_AUDIO_POWER_MASK) { |
1878 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> | |
1879 | SDE_AUDIO_POWER_SHIFT); | |
776ad806 | 1880 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
cfc33bf7 VS |
1881 | port_name(port)); |
1882 | } | |
776ad806 | 1883 | |
ce99c256 DV |
1884 | if (pch_iir & SDE_AUX_MASK) |
1885 | dp_aux_irq_handler(dev); | |
1886 | ||
776ad806 | 1887 | if (pch_iir & SDE_GMBUS) |
515ac2bb | 1888 | gmbus_irq_handler(dev); |
776ad806 JB |
1889 | |
1890 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
1891 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
1892 | ||
1893 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
1894 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
1895 | ||
1896 | if (pch_iir & SDE_POISON) | |
1897 | DRM_ERROR("PCH poison interrupt\n"); | |
1898 | ||
9db4a9c7 | 1899 | if (pch_iir & SDE_FDI_MASK) |
055e393f | 1900 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
1901 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
1902 | pipe_name(pipe), | |
1903 | I915_READ(FDI_RX_IIR(pipe))); | |
776ad806 JB |
1904 | |
1905 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
1906 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
1907 | ||
1908 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
1909 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
1910 | ||
776ad806 | 1911 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
1f7247c0 | 1912 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); |
8664281b PZ |
1913 | |
1914 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
1f7247c0 | 1915 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); |
8664281b PZ |
1916 | } |
1917 | ||
1918 | static void ivb_err_int_handler(struct drm_device *dev) | |
1919 | { | |
1920 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1921 | u32 err_int = I915_READ(GEN7_ERR_INT); | |
5a69b89f | 1922 | enum pipe pipe; |
8664281b | 1923 | |
de032bf4 PZ |
1924 | if (err_int & ERR_INT_POISON) |
1925 | DRM_ERROR("Poison interrupt\n"); | |
1926 | ||
055e393f | 1927 | for_each_pipe(dev_priv, pipe) { |
1f7247c0 DV |
1928 | if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) |
1929 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
8bf1e9f1 | 1930 | |
5a69b89f DV |
1931 | if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { |
1932 | if (IS_IVYBRIDGE(dev)) | |
277de95e | 1933 | ivb_pipe_crc_irq_handler(dev, pipe); |
5a69b89f | 1934 | else |
277de95e | 1935 | hsw_pipe_crc_irq_handler(dev, pipe); |
5a69b89f DV |
1936 | } |
1937 | } | |
8bf1e9f1 | 1938 | |
8664281b PZ |
1939 | I915_WRITE(GEN7_ERR_INT, err_int); |
1940 | } | |
1941 | ||
1942 | static void cpt_serr_int_handler(struct drm_device *dev) | |
1943 | { | |
1944 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1945 | u32 serr_int = I915_READ(SERR_INT); | |
1946 | ||
de032bf4 PZ |
1947 | if (serr_int & SERR_INT_POISON) |
1948 | DRM_ERROR("PCH poison interrupt\n"); | |
1949 | ||
8664281b | 1950 | if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) |
1f7247c0 | 1951 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); |
8664281b PZ |
1952 | |
1953 | if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) | |
1f7247c0 | 1954 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); |
8664281b PZ |
1955 | |
1956 | if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) | |
1f7247c0 | 1957 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C); |
8664281b PZ |
1958 | |
1959 | I915_WRITE(SERR_INT, serr_int); | |
776ad806 JB |
1960 | } |
1961 | ||
23e81d69 AJ |
1962 | static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) |
1963 | { | |
2d1013dd | 1964 | struct drm_i915_private *dev_priv = dev->dev_private; |
23e81d69 | 1965 | int pipe; |
b543fb04 | 1966 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; |
13cf5504 DA |
1967 | u32 dig_hotplug_reg; |
1968 | ||
1969 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); | |
1970 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
23e81d69 | 1971 | |
13cf5504 | 1972 | intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_cpt); |
91d131d2 | 1973 | |
cfc33bf7 VS |
1974 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { |
1975 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> | |
1976 | SDE_AUDIO_POWER_SHIFT_CPT); | |
1977 | DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", | |
1978 | port_name(port)); | |
1979 | } | |
23e81d69 AJ |
1980 | |
1981 | if (pch_iir & SDE_AUX_MASK_CPT) | |
ce99c256 | 1982 | dp_aux_irq_handler(dev); |
23e81d69 AJ |
1983 | |
1984 | if (pch_iir & SDE_GMBUS_CPT) | |
515ac2bb | 1985 | gmbus_irq_handler(dev); |
23e81d69 AJ |
1986 | |
1987 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) | |
1988 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); | |
1989 | ||
1990 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) | |
1991 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); | |
1992 | ||
1993 | if (pch_iir & SDE_FDI_MASK_CPT) | |
055e393f | 1994 | for_each_pipe(dev_priv, pipe) |
23e81d69 AJ |
1995 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
1996 | pipe_name(pipe), | |
1997 | I915_READ(FDI_RX_IIR(pipe))); | |
8664281b PZ |
1998 | |
1999 | if (pch_iir & SDE_ERROR_CPT) | |
2000 | cpt_serr_int_handler(dev); | |
23e81d69 AJ |
2001 | } |
2002 | ||
c008bc6e PZ |
2003 | static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) |
2004 | { | |
2005 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40da17c2 | 2006 | enum pipe pipe; |
c008bc6e PZ |
2007 | |
2008 | if (de_iir & DE_AUX_CHANNEL_A) | |
2009 | dp_aux_irq_handler(dev); | |
2010 | ||
2011 | if (de_iir & DE_GSE) | |
2012 | intel_opregion_asle_intr(dev); | |
2013 | ||
c008bc6e PZ |
2014 | if (de_iir & DE_POISON) |
2015 | DRM_ERROR("Poison interrupt\n"); | |
2016 | ||
055e393f | 2017 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
2018 | if (de_iir & DE_PIPE_VBLANK(pipe) && |
2019 | intel_pipe_handle_vblank(dev, pipe)) | |
2020 | intel_check_page_flip(dev, pipe); | |
5b3a856b | 2021 | |
40da17c2 | 2022 | if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) |
1f7247c0 | 2023 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); |
5b3a856b | 2024 | |
40da17c2 DV |
2025 | if (de_iir & DE_PIPE_CRC_DONE(pipe)) |
2026 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
c008bc6e | 2027 | |
40da17c2 DV |
2028 | /* plane/pipes map 1:1 on ilk+ */ |
2029 | if (de_iir & DE_PLANE_FLIP_DONE(pipe)) { | |
2030 | intel_prepare_page_flip(dev, pipe); | |
2031 | intel_finish_page_flip_plane(dev, pipe); | |
2032 | } | |
c008bc6e PZ |
2033 | } |
2034 | ||
2035 | /* check event from PCH */ | |
2036 | if (de_iir & DE_PCH_EVENT) { | |
2037 | u32 pch_iir = I915_READ(SDEIIR); | |
2038 | ||
2039 | if (HAS_PCH_CPT(dev)) | |
2040 | cpt_irq_handler(dev, pch_iir); | |
2041 | else | |
2042 | ibx_irq_handler(dev, pch_iir); | |
2043 | ||
2044 | /* should clear PCH hotplug event before clear CPU irq */ | |
2045 | I915_WRITE(SDEIIR, pch_iir); | |
2046 | } | |
2047 | ||
2048 | if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) | |
2049 | ironlake_rps_change_irq_handler(dev); | |
2050 | } | |
2051 | ||
9719fb98 PZ |
2052 | static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir) |
2053 | { | |
2054 | struct drm_i915_private *dev_priv = dev->dev_private; | |
07d27e20 | 2055 | enum pipe pipe; |
9719fb98 PZ |
2056 | |
2057 | if (de_iir & DE_ERR_INT_IVB) | |
2058 | ivb_err_int_handler(dev); | |
2059 | ||
2060 | if (de_iir & DE_AUX_CHANNEL_A_IVB) | |
2061 | dp_aux_irq_handler(dev); | |
2062 | ||
2063 | if (de_iir & DE_GSE_IVB) | |
2064 | intel_opregion_asle_intr(dev); | |
2065 | ||
055e393f | 2066 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
2067 | if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) && |
2068 | intel_pipe_handle_vblank(dev, pipe)) | |
2069 | intel_check_page_flip(dev, pipe); | |
40da17c2 DV |
2070 | |
2071 | /* plane/pipes map 1:1 on ilk+ */ | |
07d27e20 DL |
2072 | if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) { |
2073 | intel_prepare_page_flip(dev, pipe); | |
2074 | intel_finish_page_flip_plane(dev, pipe); | |
9719fb98 PZ |
2075 | } |
2076 | } | |
2077 | ||
2078 | /* check event from PCH */ | |
2079 | if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) { | |
2080 | u32 pch_iir = I915_READ(SDEIIR); | |
2081 | ||
2082 | cpt_irq_handler(dev, pch_iir); | |
2083 | ||
2084 | /* clear PCH hotplug event before clear CPU irq */ | |
2085 | I915_WRITE(SDEIIR, pch_iir); | |
2086 | } | |
2087 | } | |
2088 | ||
72c90f62 OM |
2089 | /* |
2090 | * To handle irqs with the minimum potential races with fresh interrupts, we: | |
2091 | * 1 - Disable Master Interrupt Control. | |
2092 | * 2 - Find the source(s) of the interrupt. | |
2093 | * 3 - Clear the Interrupt Identity bits (IIR). | |
2094 | * 4 - Process the interrupt(s) that had bits set in the IIRs. | |
2095 | * 5 - Re-enable Master Interrupt Control. | |
2096 | */ | |
f1af8fc1 | 2097 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
b1f14ad0 | 2098 | { |
45a83f84 | 2099 | struct drm_device *dev = arg; |
2d1013dd | 2100 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1af8fc1 | 2101 | u32 de_iir, gt_iir, de_ier, sde_ier = 0; |
0e43406b | 2102 | irqreturn_t ret = IRQ_NONE; |
b1f14ad0 | 2103 | |
2dd2a883 ID |
2104 | if (!intel_irqs_enabled(dev_priv)) |
2105 | return IRQ_NONE; | |
2106 | ||
8664281b PZ |
2107 | /* We get interrupts on unclaimed registers, so check for this before we |
2108 | * do any I915_{READ,WRITE}. */ | |
907b28c5 | 2109 | intel_uncore_check_errors(dev); |
8664281b | 2110 | |
b1f14ad0 JB |
2111 | /* disable master interrupt before clearing iir */ |
2112 | de_ier = I915_READ(DEIER); | |
2113 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
23a78516 | 2114 | POSTING_READ(DEIER); |
b1f14ad0 | 2115 | |
44498aea PZ |
2116 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
2117 | * interrupts will will be stored on its back queue, and then we'll be | |
2118 | * able to process them after we restore SDEIER (as soon as we restore | |
2119 | * it, we'll get an interrupt if SDEIIR still has something to process | |
2120 | * due to its back queue). */ | |
ab5c608b BW |
2121 | if (!HAS_PCH_NOP(dev)) { |
2122 | sde_ier = I915_READ(SDEIER); | |
2123 | I915_WRITE(SDEIER, 0); | |
2124 | POSTING_READ(SDEIER); | |
2125 | } | |
44498aea | 2126 | |
72c90f62 OM |
2127 | /* Find, clear, then process each source of interrupt */ |
2128 | ||
b1f14ad0 | 2129 | gt_iir = I915_READ(GTIIR); |
0e43406b | 2130 | if (gt_iir) { |
72c90f62 OM |
2131 | I915_WRITE(GTIIR, gt_iir); |
2132 | ret = IRQ_HANDLED; | |
d8fc8a47 | 2133 | if (INTEL_INFO(dev)->gen >= 6) |
f1af8fc1 | 2134 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
d8fc8a47 PZ |
2135 | else |
2136 | ilk_gt_irq_handler(dev, dev_priv, gt_iir); | |
b1f14ad0 JB |
2137 | } |
2138 | ||
0e43406b CW |
2139 | de_iir = I915_READ(DEIIR); |
2140 | if (de_iir) { | |
72c90f62 OM |
2141 | I915_WRITE(DEIIR, de_iir); |
2142 | ret = IRQ_HANDLED; | |
f1af8fc1 PZ |
2143 | if (INTEL_INFO(dev)->gen >= 7) |
2144 | ivb_display_irq_handler(dev, de_iir); | |
2145 | else | |
2146 | ilk_display_irq_handler(dev, de_iir); | |
b1f14ad0 JB |
2147 | } |
2148 | ||
f1af8fc1 PZ |
2149 | if (INTEL_INFO(dev)->gen >= 6) { |
2150 | u32 pm_iir = I915_READ(GEN6_PMIIR); | |
2151 | if (pm_iir) { | |
f1af8fc1 PZ |
2152 | I915_WRITE(GEN6_PMIIR, pm_iir); |
2153 | ret = IRQ_HANDLED; | |
72c90f62 | 2154 | gen6_rps_irq_handler(dev_priv, pm_iir); |
f1af8fc1 | 2155 | } |
0e43406b | 2156 | } |
b1f14ad0 | 2157 | |
b1f14ad0 JB |
2158 | I915_WRITE(DEIER, de_ier); |
2159 | POSTING_READ(DEIER); | |
ab5c608b BW |
2160 | if (!HAS_PCH_NOP(dev)) { |
2161 | I915_WRITE(SDEIER, sde_ier); | |
2162 | POSTING_READ(SDEIER); | |
2163 | } | |
b1f14ad0 JB |
2164 | |
2165 | return ret; | |
2166 | } | |
2167 | ||
abd58f01 BW |
2168 | static irqreturn_t gen8_irq_handler(int irq, void *arg) |
2169 | { | |
2170 | struct drm_device *dev = arg; | |
2171 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2172 | u32 master_ctl; | |
2173 | irqreturn_t ret = IRQ_NONE; | |
2174 | uint32_t tmp = 0; | |
c42664cc | 2175 | enum pipe pipe; |
88e04703 JB |
2176 | u32 aux_mask = GEN8_AUX_CHANNEL_A; |
2177 | ||
2dd2a883 ID |
2178 | if (!intel_irqs_enabled(dev_priv)) |
2179 | return IRQ_NONE; | |
2180 | ||
88e04703 JB |
2181 | if (IS_GEN9(dev)) |
2182 | aux_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | | |
2183 | GEN9_AUX_CHANNEL_D; | |
abd58f01 | 2184 | |
abd58f01 BW |
2185 | master_ctl = I915_READ(GEN8_MASTER_IRQ); |
2186 | master_ctl &= ~GEN8_MASTER_IRQ_CONTROL; | |
2187 | if (!master_ctl) | |
2188 | return IRQ_NONE; | |
2189 | ||
2190 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
2191 | POSTING_READ(GEN8_MASTER_IRQ); | |
2192 | ||
38cc46d7 OM |
2193 | /* Find, clear, then process each source of interrupt */ |
2194 | ||
abd58f01 BW |
2195 | ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl); |
2196 | ||
2197 | if (master_ctl & GEN8_DE_MISC_IRQ) { | |
2198 | tmp = I915_READ(GEN8_DE_MISC_IIR); | |
abd58f01 BW |
2199 | if (tmp) { |
2200 | I915_WRITE(GEN8_DE_MISC_IIR, tmp); | |
2201 | ret = IRQ_HANDLED; | |
38cc46d7 OM |
2202 | if (tmp & GEN8_DE_MISC_GSE) |
2203 | intel_opregion_asle_intr(dev); | |
2204 | else | |
2205 | DRM_ERROR("Unexpected DE Misc interrupt\n"); | |
abd58f01 | 2206 | } |
38cc46d7 OM |
2207 | else |
2208 | DRM_ERROR("The master control interrupt lied (DE MISC)!\n"); | |
abd58f01 BW |
2209 | } |
2210 | ||
6d766f02 DV |
2211 | if (master_ctl & GEN8_DE_PORT_IRQ) { |
2212 | tmp = I915_READ(GEN8_DE_PORT_IIR); | |
6d766f02 DV |
2213 | if (tmp) { |
2214 | I915_WRITE(GEN8_DE_PORT_IIR, tmp); | |
2215 | ret = IRQ_HANDLED; | |
88e04703 JB |
2216 | |
2217 | if (tmp & aux_mask) | |
38cc46d7 OM |
2218 | dp_aux_irq_handler(dev); |
2219 | else | |
2220 | DRM_ERROR("Unexpected DE Port interrupt\n"); | |
6d766f02 | 2221 | } |
38cc46d7 OM |
2222 | else |
2223 | DRM_ERROR("The master control interrupt lied (DE PORT)!\n"); | |
6d766f02 DV |
2224 | } |
2225 | ||
055e393f | 2226 | for_each_pipe(dev_priv, pipe) { |
770de83d | 2227 | uint32_t pipe_iir, flip_done = 0, fault_errors = 0; |
abd58f01 | 2228 | |
c42664cc DV |
2229 | if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) |
2230 | continue; | |
abd58f01 | 2231 | |
c42664cc | 2232 | pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); |
c42664cc DV |
2233 | if (pipe_iir) { |
2234 | ret = IRQ_HANDLED; | |
2235 | I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir); | |
770de83d | 2236 | |
d6bbafa1 CW |
2237 | if (pipe_iir & GEN8_PIPE_VBLANK && |
2238 | intel_pipe_handle_vblank(dev, pipe)) | |
2239 | intel_check_page_flip(dev, pipe); | |
38cc46d7 | 2240 | |
770de83d DL |
2241 | if (IS_GEN9(dev)) |
2242 | flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE; | |
2243 | else | |
2244 | flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE; | |
2245 | ||
2246 | if (flip_done) { | |
38cc46d7 OM |
2247 | intel_prepare_page_flip(dev, pipe); |
2248 | intel_finish_page_flip_plane(dev, pipe); | |
2249 | } | |
2250 | ||
2251 | if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE) | |
2252 | hsw_pipe_crc_irq_handler(dev, pipe); | |
2253 | ||
1f7247c0 DV |
2254 | if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) |
2255 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
2256 | pipe); | |
38cc46d7 | 2257 | |
770de83d DL |
2258 | |
2259 | if (IS_GEN9(dev)) | |
2260 | fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS; | |
2261 | else | |
2262 | fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
2263 | ||
2264 | if (fault_errors) | |
38cc46d7 OM |
2265 | DRM_ERROR("Fault errors on pipe %c\n: 0x%08x", |
2266 | pipe_name(pipe), | |
2267 | pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS); | |
c42664cc | 2268 | } else |
abd58f01 BW |
2269 | DRM_ERROR("The master control interrupt lied (DE PIPE)!\n"); |
2270 | } | |
2271 | ||
92d03a80 DV |
2272 | if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) { |
2273 | /* | |
2274 | * FIXME(BDW): Assume for now that the new interrupt handling | |
2275 | * scheme also closed the SDE interrupt handling race we've seen | |
2276 | * on older pch-split platforms. But this needs testing. | |
2277 | */ | |
2278 | u32 pch_iir = I915_READ(SDEIIR); | |
92d03a80 DV |
2279 | if (pch_iir) { |
2280 | I915_WRITE(SDEIIR, pch_iir); | |
2281 | ret = IRQ_HANDLED; | |
38cc46d7 OM |
2282 | cpt_irq_handler(dev, pch_iir); |
2283 | } else | |
2284 | DRM_ERROR("The master control interrupt lied (SDE)!\n"); | |
2285 | ||
92d03a80 DV |
2286 | } |
2287 | ||
abd58f01 BW |
2288 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
2289 | POSTING_READ(GEN8_MASTER_IRQ); | |
2290 | ||
2291 | return ret; | |
2292 | } | |
2293 | ||
17e1df07 DV |
2294 | static void i915_error_wake_up(struct drm_i915_private *dev_priv, |
2295 | bool reset_completed) | |
2296 | { | |
a4872ba6 | 2297 | struct intel_engine_cs *ring; |
17e1df07 DV |
2298 | int i; |
2299 | ||
2300 | /* | |
2301 | * Notify all waiters for GPU completion events that reset state has | |
2302 | * been changed, and that they need to restart their wait after | |
2303 | * checking for potential errors (and bail out to drop locks if there is | |
2304 | * a gpu reset pending so that i915_error_work_func can acquire them). | |
2305 | */ | |
2306 | ||
2307 | /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */ | |
2308 | for_each_ring(ring, dev_priv, i) | |
2309 | wake_up_all(&ring->irq_queue); | |
2310 | ||
2311 | /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */ | |
2312 | wake_up_all(&dev_priv->pending_flip_queue); | |
2313 | ||
2314 | /* | |
2315 | * Signal tasks blocked in i915_gem_wait_for_error that the pending | |
2316 | * reset state is cleared. | |
2317 | */ | |
2318 | if (reset_completed) | |
2319 | wake_up_all(&dev_priv->gpu_error.reset_queue); | |
2320 | } | |
2321 | ||
8a905236 | 2322 | /** |
b8d24a06 | 2323 | * i915_reset_and_wakeup - do process context error handling work |
8a905236 JB |
2324 | * |
2325 | * Fire an error uevent so userspace can see that a hang or error | |
2326 | * was detected. | |
2327 | */ | |
b8d24a06 | 2328 | static void i915_reset_and_wakeup(struct drm_device *dev) |
8a905236 | 2329 | { |
b8d24a06 MK |
2330 | struct drm_i915_private *dev_priv = to_i915(dev); |
2331 | struct i915_gpu_error *error = &dev_priv->gpu_error; | |
cce723ed BW |
2332 | char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; |
2333 | char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; | |
2334 | char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; | |
17e1df07 | 2335 | int ret; |
8a905236 | 2336 | |
5bdebb18 | 2337 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event); |
f316a42c | 2338 | |
7db0ba24 DV |
2339 | /* |
2340 | * Note that there's only one work item which does gpu resets, so we | |
2341 | * need not worry about concurrent gpu resets potentially incrementing | |
2342 | * error->reset_counter twice. We only need to take care of another | |
2343 | * racing irq/hangcheck declaring the gpu dead for a second time. A | |
2344 | * quick check for that is good enough: schedule_work ensures the | |
2345 | * correct ordering between hang detection and this work item, and since | |
2346 | * the reset in-progress bit is only ever set by code outside of this | |
2347 | * work we don't need to worry about any other races. | |
2348 | */ | |
2349 | if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) { | |
f803aa55 | 2350 | DRM_DEBUG_DRIVER("resetting chip\n"); |
5bdebb18 | 2351 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, |
7db0ba24 | 2352 | reset_event); |
1f83fee0 | 2353 | |
f454c694 ID |
2354 | /* |
2355 | * In most cases it's guaranteed that we get here with an RPM | |
2356 | * reference held, for example because there is a pending GPU | |
2357 | * request that won't finish until the reset is done. This | |
2358 | * isn't the case at least when we get here by doing a | |
2359 | * simulated reset via debugs, so get an RPM reference. | |
2360 | */ | |
2361 | intel_runtime_pm_get(dev_priv); | |
7514747d VS |
2362 | |
2363 | intel_prepare_reset(dev); | |
2364 | ||
17e1df07 DV |
2365 | /* |
2366 | * All state reset _must_ be completed before we update the | |
2367 | * reset counter, for otherwise waiters might miss the reset | |
2368 | * pending state and not properly drop locks, resulting in | |
2369 | * deadlocks with the reset work. | |
2370 | */ | |
f69061be DV |
2371 | ret = i915_reset(dev); |
2372 | ||
7514747d | 2373 | intel_finish_reset(dev); |
17e1df07 | 2374 | |
f454c694 ID |
2375 | intel_runtime_pm_put(dev_priv); |
2376 | ||
f69061be DV |
2377 | if (ret == 0) { |
2378 | /* | |
2379 | * After all the gem state is reset, increment the reset | |
2380 | * counter and wake up everyone waiting for the reset to | |
2381 | * complete. | |
2382 | * | |
2383 | * Since unlock operations are a one-sided barrier only, | |
2384 | * we need to insert a barrier here to order any seqno | |
2385 | * updates before | |
2386 | * the counter increment. | |
2387 | */ | |
4e857c58 | 2388 | smp_mb__before_atomic(); |
f69061be DV |
2389 | atomic_inc(&dev_priv->gpu_error.reset_counter); |
2390 | ||
5bdebb18 | 2391 | kobject_uevent_env(&dev->primary->kdev->kobj, |
f69061be | 2392 | KOBJ_CHANGE, reset_done_event); |
1f83fee0 | 2393 | } else { |
2ac0f450 | 2394 | atomic_set_mask(I915_WEDGED, &error->reset_counter); |
f316a42c | 2395 | } |
1f83fee0 | 2396 | |
17e1df07 DV |
2397 | /* |
2398 | * Note: The wake_up also serves as a memory barrier so that | |
2399 | * waiters see the update value of the reset counter atomic_t. | |
2400 | */ | |
2401 | i915_error_wake_up(dev_priv, true); | |
f316a42c | 2402 | } |
8a905236 JB |
2403 | } |
2404 | ||
35aed2e6 | 2405 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
2406 | { |
2407 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bd9854f9 | 2408 | uint32_t instdone[I915_NUM_INSTDONE_REG]; |
8a905236 | 2409 | u32 eir = I915_READ(EIR); |
050ee91f | 2410 | int pipe, i; |
8a905236 | 2411 | |
35aed2e6 CW |
2412 | if (!eir) |
2413 | return; | |
8a905236 | 2414 | |
a70491cc | 2415 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
8a905236 | 2416 | |
bd9854f9 BW |
2417 | i915_get_extra_instdone(dev, instdone); |
2418 | ||
8a905236 JB |
2419 | if (IS_G4X(dev)) { |
2420 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
2421 | u32 ipeir = I915_READ(IPEIR_I965); | |
2422 | ||
a70491cc JP |
2423 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2424 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
050ee91f BW |
2425 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2426 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a70491cc | 2427 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2428 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2429 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2430 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2431 | } |
2432 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
2433 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2434 | pr_err("page table error\n"); |
2435 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2436 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2437 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2438 | } |
2439 | } | |
2440 | ||
a6c45cf0 | 2441 | if (!IS_GEN2(dev)) { |
8a905236 JB |
2442 | if (eir & I915_ERROR_PAGE_TABLE) { |
2443 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2444 | pr_err("page table error\n"); |
2445 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2446 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2447 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2448 | } |
2449 | } | |
2450 | ||
2451 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
a70491cc | 2452 | pr_err("memory refresh error:\n"); |
055e393f | 2453 | for_each_pipe(dev_priv, pipe) |
a70491cc | 2454 | pr_err("pipe %c stat: 0x%08x\n", |
9db4a9c7 | 2455 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
8a905236 JB |
2456 | /* pipestat has already been acked */ |
2457 | } | |
2458 | if (eir & I915_ERROR_INSTRUCTION) { | |
a70491cc JP |
2459 | pr_err("instruction error\n"); |
2460 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); | |
050ee91f BW |
2461 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2462 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a6c45cf0 | 2463 | if (INTEL_INFO(dev)->gen < 4) { |
8a905236 JB |
2464 | u32 ipeir = I915_READ(IPEIR); |
2465 | ||
a70491cc JP |
2466 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
2467 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); | |
a70491cc | 2468 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); |
8a905236 | 2469 | I915_WRITE(IPEIR, ipeir); |
3143a2bf | 2470 | POSTING_READ(IPEIR); |
8a905236 JB |
2471 | } else { |
2472 | u32 ipeir = I915_READ(IPEIR_I965); | |
2473 | ||
a70491cc JP |
2474 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2475 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
a70491cc | 2476 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2477 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2478 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2479 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2480 | } |
2481 | } | |
2482 | ||
2483 | I915_WRITE(EIR, eir); | |
3143a2bf | 2484 | POSTING_READ(EIR); |
8a905236 JB |
2485 | eir = I915_READ(EIR); |
2486 | if (eir) { | |
2487 | /* | |
2488 | * some errors might have become stuck, | |
2489 | * mask them. | |
2490 | */ | |
2491 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
2492 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
2493 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2494 | } | |
35aed2e6 CW |
2495 | } |
2496 | ||
2497 | /** | |
b8d24a06 | 2498 | * i915_handle_error - handle a gpu error |
35aed2e6 CW |
2499 | * @dev: drm device |
2500 | * | |
b8d24a06 | 2501 | * Do some basic checking of regsiter state at error time and |
35aed2e6 CW |
2502 | * dump it to the syslog. Also call i915_capture_error_state() to make |
2503 | * sure we get a record and make it available in debugfs. Fire a uevent | |
2504 | * so userspace knows something bad happened (should trigger collection | |
2505 | * of a ring dump etc.). | |
2506 | */ | |
58174462 MK |
2507 | void i915_handle_error(struct drm_device *dev, bool wedged, |
2508 | const char *fmt, ...) | |
35aed2e6 CW |
2509 | { |
2510 | struct drm_i915_private *dev_priv = dev->dev_private; | |
58174462 MK |
2511 | va_list args; |
2512 | char error_msg[80]; | |
35aed2e6 | 2513 | |
58174462 MK |
2514 | va_start(args, fmt); |
2515 | vscnprintf(error_msg, sizeof(error_msg), fmt, args); | |
2516 | va_end(args); | |
2517 | ||
2518 | i915_capture_error_state(dev, wedged, error_msg); | |
35aed2e6 | 2519 | i915_report_and_clear_eir(dev); |
8a905236 | 2520 | |
ba1234d1 | 2521 | if (wedged) { |
f69061be DV |
2522 | atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG, |
2523 | &dev_priv->gpu_error.reset_counter); | |
ba1234d1 | 2524 | |
11ed50ec | 2525 | /* |
b8d24a06 MK |
2526 | * Wakeup waiting processes so that the reset function |
2527 | * i915_reset_and_wakeup doesn't deadlock trying to grab | |
2528 | * various locks. By bumping the reset counter first, the woken | |
17e1df07 DV |
2529 | * processes will see a reset in progress and back off, |
2530 | * releasing their locks and then wait for the reset completion. | |
2531 | * We must do this for _all_ gpu waiters that might hold locks | |
2532 | * that the reset work needs to acquire. | |
2533 | * | |
2534 | * Note: The wake_up serves as the required memory barrier to | |
2535 | * ensure that the waiters see the updated value of the reset | |
2536 | * counter atomic_t. | |
11ed50ec | 2537 | */ |
17e1df07 | 2538 | i915_error_wake_up(dev_priv, false); |
11ed50ec BG |
2539 | } |
2540 | ||
b8d24a06 | 2541 | i915_reset_and_wakeup(dev); |
8a905236 JB |
2542 | } |
2543 | ||
42f52ef8 KP |
2544 | /* Called from drm generic code, passed 'crtc' which |
2545 | * we use as a pipe index | |
2546 | */ | |
f71d4af4 | 2547 | static int i915_enable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 | 2548 | { |
2d1013dd | 2549 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2550 | unsigned long irqflags; |
71e0ffa5 | 2551 | |
1ec14ad3 | 2552 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2553 | if (INTEL_INFO(dev)->gen >= 4) |
7c463586 | 2554 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2555 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
e9d21d7f | 2556 | else |
7c463586 | 2557 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2558 | PIPE_VBLANK_INTERRUPT_STATUS); |
1ec14ad3 | 2559 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
8692d00e | 2560 | |
0a3e67a4 JB |
2561 | return 0; |
2562 | } | |
2563 | ||
f71d4af4 | 2564 | static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
f796cf8f | 2565 | { |
2d1013dd | 2566 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2567 | unsigned long irqflags; |
b518421f | 2568 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2569 | DE_PIPE_VBLANK(pipe); |
f796cf8f | 2570 | |
f796cf8f | 2571 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
b518421f | 2572 | ironlake_enable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2573 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2574 | ||
2575 | return 0; | |
2576 | } | |
2577 | ||
7e231dbe JB |
2578 | static int valleyview_enable_vblank(struct drm_device *dev, int pipe) |
2579 | { | |
2d1013dd | 2580 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2581 | unsigned long irqflags; |
7e231dbe | 2582 | |
7e231dbe | 2583 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
31acc7f5 | 2584 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2585 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2586 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2587 | ||
2588 | return 0; | |
2589 | } | |
2590 | ||
abd58f01 BW |
2591 | static int gen8_enable_vblank(struct drm_device *dev, int pipe) |
2592 | { | |
2593 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2594 | unsigned long irqflags; | |
abd58f01 | 2595 | |
abd58f01 | 2596 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
7167d7c6 DV |
2597 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK; |
2598 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2599 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2600 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2601 | return 0; | |
2602 | } | |
2603 | ||
42f52ef8 KP |
2604 | /* Called from drm generic code, passed 'crtc' which |
2605 | * we use as a pipe index | |
2606 | */ | |
f71d4af4 | 2607 | static void i915_disable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 | 2608 | { |
2d1013dd | 2609 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2610 | unsigned long irqflags; |
0a3e67a4 | 2611 | |
1ec14ad3 | 2612 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2613 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 ID |
2614 | PIPE_VBLANK_INTERRUPT_STATUS | |
2615 | PIPE_START_VBLANK_INTERRUPT_STATUS); | |
f796cf8f JB |
2616 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2617 | } | |
2618 | ||
f71d4af4 | 2619 | static void ironlake_disable_vblank(struct drm_device *dev, int pipe) |
f796cf8f | 2620 | { |
2d1013dd | 2621 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2622 | unsigned long irqflags; |
b518421f | 2623 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2624 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2625 | |
2626 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 2627 | ironlake_disable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2628 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2629 | } | |
2630 | ||
7e231dbe JB |
2631 | static void valleyview_disable_vblank(struct drm_device *dev, int pipe) |
2632 | { | |
2d1013dd | 2633 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2634 | unsigned long irqflags; |
7e231dbe JB |
2635 | |
2636 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 | 2637 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 | 2638 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2639 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2640 | } | |
2641 | ||
abd58f01 BW |
2642 | static void gen8_disable_vblank(struct drm_device *dev, int pipe) |
2643 | { | |
2644 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2645 | unsigned long irqflags; | |
abd58f01 | 2646 | |
abd58f01 | 2647 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
7167d7c6 DV |
2648 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK; |
2649 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2650 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2651 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2652 | } | |
2653 | ||
44cdd6d2 JH |
2654 | static struct drm_i915_gem_request * |
2655 | ring_last_request(struct intel_engine_cs *ring) | |
852835f3 | 2656 | { |
893eead0 | 2657 | return list_entry(ring->request_list.prev, |
44cdd6d2 | 2658 | struct drm_i915_gem_request, list); |
893eead0 CW |
2659 | } |
2660 | ||
9107e9d2 | 2661 | static bool |
44cdd6d2 | 2662 | ring_idle(struct intel_engine_cs *ring) |
9107e9d2 CW |
2663 | { |
2664 | return (list_empty(&ring->request_list) || | |
1b5a433a | 2665 | i915_gem_request_completed(ring_last_request(ring), false)); |
f65d9421 BG |
2666 | } |
2667 | ||
a028c4b0 DV |
2668 | static bool |
2669 | ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr) | |
2670 | { | |
2671 | if (INTEL_INFO(dev)->gen >= 8) { | |
a6cdb93a | 2672 | return (ipehr >> 23) == 0x1c; |
a028c4b0 DV |
2673 | } else { |
2674 | ipehr &= ~MI_SEMAPHORE_SYNC_MASK; | |
2675 | return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | | |
2676 | MI_SEMAPHORE_REGISTER); | |
2677 | } | |
2678 | } | |
2679 | ||
a4872ba6 | 2680 | static struct intel_engine_cs * |
a6cdb93a | 2681 | semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset) |
921d42ea DV |
2682 | { |
2683 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
a4872ba6 | 2684 | struct intel_engine_cs *signaller; |
921d42ea DV |
2685 | int i; |
2686 | ||
2687 | if (INTEL_INFO(dev_priv->dev)->gen >= 8) { | |
a6cdb93a RV |
2688 | for_each_ring(signaller, dev_priv, i) { |
2689 | if (ring == signaller) | |
2690 | continue; | |
2691 | ||
2692 | if (offset == signaller->semaphore.signal_ggtt[ring->id]) | |
2693 | return signaller; | |
2694 | } | |
921d42ea DV |
2695 | } else { |
2696 | u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK; | |
2697 | ||
2698 | for_each_ring(signaller, dev_priv, i) { | |
2699 | if(ring == signaller) | |
2700 | continue; | |
2701 | ||
ebc348b2 | 2702 | if (sync_bits == signaller->semaphore.mbox.wait[ring->id]) |
921d42ea DV |
2703 | return signaller; |
2704 | } | |
2705 | } | |
2706 | ||
a6cdb93a RV |
2707 | DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n", |
2708 | ring->id, ipehr, offset); | |
921d42ea DV |
2709 | |
2710 | return NULL; | |
2711 | } | |
2712 | ||
a4872ba6 OM |
2713 | static struct intel_engine_cs * |
2714 | semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno) | |
a24a11e6 CW |
2715 | { |
2716 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
88fe429d | 2717 | u32 cmd, ipehr, head; |
a6cdb93a RV |
2718 | u64 offset = 0; |
2719 | int i, backwards; | |
a24a11e6 CW |
2720 | |
2721 | ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); | |
a028c4b0 | 2722 | if (!ipehr_is_semaphore_wait(ring->dev, ipehr)) |
6274f212 | 2723 | return NULL; |
a24a11e6 | 2724 | |
88fe429d DV |
2725 | /* |
2726 | * HEAD is likely pointing to the dword after the actual command, | |
2727 | * so scan backwards until we find the MBOX. But limit it to just 3 | |
a6cdb93a RV |
2728 | * or 4 dwords depending on the semaphore wait command size. |
2729 | * Note that we don't care about ACTHD here since that might | |
88fe429d DV |
2730 | * point at at batch, and semaphores are always emitted into the |
2731 | * ringbuffer itself. | |
a24a11e6 | 2732 | */ |
88fe429d | 2733 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
a6cdb93a | 2734 | backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4; |
88fe429d | 2735 | |
a6cdb93a | 2736 | for (i = backwards; i; --i) { |
88fe429d DV |
2737 | /* |
2738 | * Be paranoid and presume the hw has gone off into the wild - | |
2739 | * our ring is smaller than what the hardware (and hence | |
2740 | * HEAD_ADDR) allows. Also handles wrap-around. | |
2741 | */ | |
ee1b1e5e | 2742 | head &= ring->buffer->size - 1; |
88fe429d DV |
2743 | |
2744 | /* This here seems to blow up */ | |
ee1b1e5e | 2745 | cmd = ioread32(ring->buffer->virtual_start + head); |
a24a11e6 CW |
2746 | if (cmd == ipehr) |
2747 | break; | |
2748 | ||
88fe429d DV |
2749 | head -= 4; |
2750 | } | |
a24a11e6 | 2751 | |
88fe429d DV |
2752 | if (!i) |
2753 | return NULL; | |
a24a11e6 | 2754 | |
ee1b1e5e | 2755 | *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1; |
a6cdb93a RV |
2756 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
2757 | offset = ioread32(ring->buffer->virtual_start + head + 12); | |
2758 | offset <<= 32; | |
2759 | offset = ioread32(ring->buffer->virtual_start + head + 8); | |
2760 | } | |
2761 | return semaphore_wait_to_signaller_ring(ring, ipehr, offset); | |
a24a11e6 CW |
2762 | } |
2763 | ||
a4872ba6 | 2764 | static int semaphore_passed(struct intel_engine_cs *ring) |
6274f212 CW |
2765 | { |
2766 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
a4872ba6 | 2767 | struct intel_engine_cs *signaller; |
a0d036b0 | 2768 | u32 seqno; |
6274f212 | 2769 | |
4be17381 | 2770 | ring->hangcheck.deadlock++; |
6274f212 CW |
2771 | |
2772 | signaller = semaphore_waits_for(ring, &seqno); | |
4be17381 CW |
2773 | if (signaller == NULL) |
2774 | return -1; | |
2775 | ||
2776 | /* Prevent pathological recursion due to driver bugs */ | |
2777 | if (signaller->hangcheck.deadlock >= I915_NUM_RINGS) | |
6274f212 CW |
2778 | return -1; |
2779 | ||
4be17381 CW |
2780 | if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno)) |
2781 | return 1; | |
2782 | ||
a0d036b0 CW |
2783 | /* cursory check for an unkickable deadlock */ |
2784 | if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE && | |
2785 | semaphore_passed(signaller) < 0) | |
4be17381 CW |
2786 | return -1; |
2787 | ||
2788 | return 0; | |
6274f212 CW |
2789 | } |
2790 | ||
2791 | static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) | |
2792 | { | |
a4872ba6 | 2793 | struct intel_engine_cs *ring; |
6274f212 CW |
2794 | int i; |
2795 | ||
2796 | for_each_ring(ring, dev_priv, i) | |
4be17381 | 2797 | ring->hangcheck.deadlock = 0; |
6274f212 CW |
2798 | } |
2799 | ||
ad8beaea | 2800 | static enum intel_ring_hangcheck_action |
a4872ba6 | 2801 | ring_stuck(struct intel_engine_cs *ring, u64 acthd) |
1ec14ad3 CW |
2802 | { |
2803 | struct drm_device *dev = ring->dev; | |
2804 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9107e9d2 CW |
2805 | u32 tmp; |
2806 | ||
f260fe7b MK |
2807 | if (acthd != ring->hangcheck.acthd) { |
2808 | if (acthd > ring->hangcheck.max_acthd) { | |
2809 | ring->hangcheck.max_acthd = acthd; | |
2810 | return HANGCHECK_ACTIVE; | |
2811 | } | |
2812 | ||
2813 | return HANGCHECK_ACTIVE_LOOP; | |
2814 | } | |
6274f212 | 2815 | |
9107e9d2 | 2816 | if (IS_GEN2(dev)) |
f2f4d82f | 2817 | return HANGCHECK_HUNG; |
9107e9d2 CW |
2818 | |
2819 | /* Is the chip hanging on a WAIT_FOR_EVENT? | |
2820 | * If so we can simply poke the RB_WAIT bit | |
2821 | * and break the hang. This should work on | |
2822 | * all but the second generation chipsets. | |
2823 | */ | |
2824 | tmp = I915_READ_CTL(ring); | |
1ec14ad3 | 2825 | if (tmp & RING_WAIT) { |
58174462 MK |
2826 | i915_handle_error(dev, false, |
2827 | "Kicking stuck wait on %s", | |
2828 | ring->name); | |
1ec14ad3 | 2829 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2830 | return HANGCHECK_KICK; |
6274f212 CW |
2831 | } |
2832 | ||
2833 | if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { | |
2834 | switch (semaphore_passed(ring)) { | |
2835 | default: | |
f2f4d82f | 2836 | return HANGCHECK_HUNG; |
6274f212 | 2837 | case 1: |
58174462 MK |
2838 | i915_handle_error(dev, false, |
2839 | "Kicking stuck semaphore on %s", | |
2840 | ring->name); | |
6274f212 | 2841 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2842 | return HANGCHECK_KICK; |
6274f212 | 2843 | case 0: |
f2f4d82f | 2844 | return HANGCHECK_WAIT; |
6274f212 | 2845 | } |
9107e9d2 | 2846 | } |
ed5cbb03 | 2847 | |
f2f4d82f | 2848 | return HANGCHECK_HUNG; |
ed5cbb03 MK |
2849 | } |
2850 | ||
737b1506 | 2851 | /* |
f65d9421 | 2852 | * This is called when the chip hasn't reported back with completed |
05407ff8 MK |
2853 | * batchbuffers in a long time. We keep track per ring seqno progress and |
2854 | * if there are no progress, hangcheck score for that ring is increased. | |
2855 | * Further, acthd is inspected to see if the ring is stuck. On stuck case | |
2856 | * we kick the ring. If we see no progress on three subsequent calls | |
2857 | * we assume chip is wedged and try to fix it by resetting the chip. | |
f65d9421 | 2858 | */ |
737b1506 | 2859 | static void i915_hangcheck_elapsed(struct work_struct *work) |
f65d9421 | 2860 | { |
737b1506 CW |
2861 | struct drm_i915_private *dev_priv = |
2862 | container_of(work, typeof(*dev_priv), | |
2863 | gpu_error.hangcheck_work.work); | |
2864 | struct drm_device *dev = dev_priv->dev; | |
a4872ba6 | 2865 | struct intel_engine_cs *ring; |
b4519513 | 2866 | int i; |
05407ff8 | 2867 | int busy_count = 0, rings_hung = 0; |
9107e9d2 CW |
2868 | bool stuck[I915_NUM_RINGS] = { 0 }; |
2869 | #define BUSY 1 | |
2870 | #define KICK 5 | |
2871 | #define HUNG 20 | |
893eead0 | 2872 | |
d330a953 | 2873 | if (!i915.enable_hangcheck) |
3e0dc6b0 BW |
2874 | return; |
2875 | ||
b4519513 | 2876 | for_each_ring(ring, dev_priv, i) { |
50877445 CW |
2877 | u64 acthd; |
2878 | u32 seqno; | |
9107e9d2 | 2879 | bool busy = true; |
05407ff8 | 2880 | |
6274f212 CW |
2881 | semaphore_clear_deadlocks(dev_priv); |
2882 | ||
05407ff8 MK |
2883 | seqno = ring->get_seqno(ring, false); |
2884 | acthd = intel_ring_get_active_head(ring); | |
b4519513 | 2885 | |
9107e9d2 | 2886 | if (ring->hangcheck.seqno == seqno) { |
44cdd6d2 | 2887 | if (ring_idle(ring)) { |
da661464 MK |
2888 | ring->hangcheck.action = HANGCHECK_IDLE; |
2889 | ||
9107e9d2 CW |
2890 | if (waitqueue_active(&ring->irq_queue)) { |
2891 | /* Issue a wake-up to catch stuck h/w. */ | |
094f9a54 | 2892 | if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) { |
f4adcd24 DV |
2893 | if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring))) |
2894 | DRM_ERROR("Hangcheck timer elapsed... %s idle\n", | |
2895 | ring->name); | |
2896 | else | |
2897 | DRM_INFO("Fake missed irq on %s\n", | |
2898 | ring->name); | |
094f9a54 CW |
2899 | wake_up_all(&ring->irq_queue); |
2900 | } | |
2901 | /* Safeguard against driver failure */ | |
2902 | ring->hangcheck.score += BUSY; | |
9107e9d2 CW |
2903 | } else |
2904 | busy = false; | |
05407ff8 | 2905 | } else { |
6274f212 CW |
2906 | /* We always increment the hangcheck score |
2907 | * if the ring is busy and still processing | |
2908 | * the same request, so that no single request | |
2909 | * can run indefinitely (such as a chain of | |
2910 | * batches). The only time we do not increment | |
2911 | * the hangcheck score on this ring, if this | |
2912 | * ring is in a legitimate wait for another | |
2913 | * ring. In that case the waiting ring is a | |
2914 | * victim and we want to be sure we catch the | |
2915 | * right culprit. Then every time we do kick | |
2916 | * the ring, add a small increment to the | |
2917 | * score so that we can catch a batch that is | |
2918 | * being repeatedly kicked and so responsible | |
2919 | * for stalling the machine. | |
2920 | */ | |
ad8beaea MK |
2921 | ring->hangcheck.action = ring_stuck(ring, |
2922 | acthd); | |
2923 | ||
2924 | switch (ring->hangcheck.action) { | |
da661464 | 2925 | case HANGCHECK_IDLE: |
f2f4d82f | 2926 | case HANGCHECK_WAIT: |
f2f4d82f | 2927 | case HANGCHECK_ACTIVE: |
f260fe7b MK |
2928 | break; |
2929 | case HANGCHECK_ACTIVE_LOOP: | |
ea04cb31 | 2930 | ring->hangcheck.score += BUSY; |
6274f212 | 2931 | break; |
f2f4d82f | 2932 | case HANGCHECK_KICK: |
ea04cb31 | 2933 | ring->hangcheck.score += KICK; |
6274f212 | 2934 | break; |
f2f4d82f | 2935 | case HANGCHECK_HUNG: |
ea04cb31 | 2936 | ring->hangcheck.score += HUNG; |
6274f212 CW |
2937 | stuck[i] = true; |
2938 | break; | |
2939 | } | |
05407ff8 | 2940 | } |
9107e9d2 | 2941 | } else { |
da661464 MK |
2942 | ring->hangcheck.action = HANGCHECK_ACTIVE; |
2943 | ||
9107e9d2 CW |
2944 | /* Gradually reduce the count so that we catch DoS |
2945 | * attempts across multiple batches. | |
2946 | */ | |
2947 | if (ring->hangcheck.score > 0) | |
2948 | ring->hangcheck.score--; | |
f260fe7b MK |
2949 | |
2950 | ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0; | |
d1e61e7f CW |
2951 | } |
2952 | ||
05407ff8 MK |
2953 | ring->hangcheck.seqno = seqno; |
2954 | ring->hangcheck.acthd = acthd; | |
9107e9d2 | 2955 | busy_count += busy; |
893eead0 | 2956 | } |
b9201c14 | 2957 | |
92cab734 | 2958 | for_each_ring(ring, dev_priv, i) { |
b6b0fac0 | 2959 | if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) { |
b8d88d1d DV |
2960 | DRM_INFO("%s on %s\n", |
2961 | stuck[i] ? "stuck" : "no progress", | |
2962 | ring->name); | |
a43adf07 | 2963 | rings_hung++; |
92cab734 MK |
2964 | } |
2965 | } | |
2966 | ||
05407ff8 | 2967 | if (rings_hung) |
58174462 | 2968 | return i915_handle_error(dev, true, "Ring hung"); |
f65d9421 | 2969 | |
05407ff8 MK |
2970 | if (busy_count) |
2971 | /* Reset timer case chip hangs without another request | |
2972 | * being added */ | |
10cd45b6 MK |
2973 | i915_queue_hangcheck(dev); |
2974 | } | |
2975 | ||
2976 | void i915_queue_hangcheck(struct drm_device *dev) | |
2977 | { | |
737b1506 | 2978 | struct i915_gpu_error *e = &to_i915(dev)->gpu_error; |
672e7b7c | 2979 | |
d330a953 | 2980 | if (!i915.enable_hangcheck) |
10cd45b6 MK |
2981 | return; |
2982 | ||
737b1506 CW |
2983 | /* Don't continually defer the hangcheck so that it is always run at |
2984 | * least once after work has been scheduled on any ring. Otherwise, | |
2985 | * we will ignore a hung ring if a second ring is kept busy. | |
2986 | */ | |
2987 | ||
2988 | queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work, | |
2989 | round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES)); | |
f65d9421 BG |
2990 | } |
2991 | ||
1c69eb42 | 2992 | static void ibx_irq_reset(struct drm_device *dev) |
91738a95 PZ |
2993 | { |
2994 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2995 | ||
2996 | if (HAS_PCH_NOP(dev)) | |
2997 | return; | |
2998 | ||
f86f3fb0 | 2999 | GEN5_IRQ_RESET(SDE); |
105b122e PZ |
3000 | |
3001 | if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) | |
3002 | I915_WRITE(SERR_INT, 0xffffffff); | |
622364b6 | 3003 | } |
105b122e | 3004 | |
622364b6 PZ |
3005 | /* |
3006 | * SDEIER is also touched by the interrupt handler to work around missed PCH | |
3007 | * interrupts. Hence we can't update it after the interrupt handler is enabled - | |
3008 | * instead we unconditionally enable all PCH interrupt sources here, but then | |
3009 | * only unmask them as needed with SDEIMR. | |
3010 | * | |
3011 | * This function needs to be called before interrupts are enabled. | |
3012 | */ | |
3013 | static void ibx_irq_pre_postinstall(struct drm_device *dev) | |
3014 | { | |
3015 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3016 | ||
3017 | if (HAS_PCH_NOP(dev)) | |
3018 | return; | |
3019 | ||
3020 | WARN_ON(I915_READ(SDEIER) != 0); | |
91738a95 PZ |
3021 | I915_WRITE(SDEIER, 0xffffffff); |
3022 | POSTING_READ(SDEIER); | |
3023 | } | |
3024 | ||
7c4d664e | 3025 | static void gen5_gt_irq_reset(struct drm_device *dev) |
d18ea1b5 DV |
3026 | { |
3027 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3028 | ||
f86f3fb0 | 3029 | GEN5_IRQ_RESET(GT); |
a9d356a6 | 3030 | if (INTEL_INFO(dev)->gen >= 6) |
f86f3fb0 | 3031 | GEN5_IRQ_RESET(GEN6_PM); |
d18ea1b5 DV |
3032 | } |
3033 | ||
1da177e4 LT |
3034 | /* drm_dma.h hooks |
3035 | */ | |
be30b29f | 3036 | static void ironlake_irq_reset(struct drm_device *dev) |
036a4a7d | 3037 | { |
2d1013dd | 3038 | struct drm_i915_private *dev_priv = dev->dev_private; |
036a4a7d | 3039 | |
0c841212 | 3040 | I915_WRITE(HWSTAM, 0xffffffff); |
bdfcdb63 | 3041 | |
f86f3fb0 | 3042 | GEN5_IRQ_RESET(DE); |
c6d954c1 PZ |
3043 | if (IS_GEN7(dev)) |
3044 | I915_WRITE(GEN7_ERR_INT, 0xffffffff); | |
036a4a7d | 3045 | |
7c4d664e | 3046 | gen5_gt_irq_reset(dev); |
c650156a | 3047 | |
1c69eb42 | 3048 | ibx_irq_reset(dev); |
7d99163d | 3049 | } |
c650156a | 3050 | |
70591a41 VS |
3051 | static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) |
3052 | { | |
3053 | enum pipe pipe; | |
3054 | ||
3055 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3056 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3057 | ||
3058 | for_each_pipe(dev_priv, pipe) | |
3059 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
3060 | ||
3061 | GEN5_IRQ_RESET(VLV_); | |
3062 | } | |
3063 | ||
7e231dbe JB |
3064 | static void valleyview_irq_preinstall(struct drm_device *dev) |
3065 | { | |
2d1013dd | 3066 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 3067 | |
7e231dbe JB |
3068 | /* VLV magic */ |
3069 | I915_WRITE(VLV_IMR, 0); | |
3070 | I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); | |
3071 | I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); | |
3072 | I915_WRITE(RING_IMR(BLT_RING_BASE), 0); | |
3073 | ||
7c4d664e | 3074 | gen5_gt_irq_reset(dev); |
7e231dbe | 3075 | |
7c4cde39 | 3076 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); |
7e231dbe | 3077 | |
70591a41 | 3078 | vlv_display_irq_reset(dev_priv); |
7e231dbe JB |
3079 | } |
3080 | ||
d6e3cca3 DV |
3081 | static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv) |
3082 | { | |
3083 | GEN8_IRQ_RESET_NDX(GT, 0); | |
3084 | GEN8_IRQ_RESET_NDX(GT, 1); | |
3085 | GEN8_IRQ_RESET_NDX(GT, 2); | |
3086 | GEN8_IRQ_RESET_NDX(GT, 3); | |
3087 | } | |
3088 | ||
823f6b38 | 3089 | static void gen8_irq_reset(struct drm_device *dev) |
abd58f01 BW |
3090 | { |
3091 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3092 | int pipe; | |
3093 | ||
abd58f01 BW |
3094 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
3095 | POSTING_READ(GEN8_MASTER_IRQ); | |
3096 | ||
d6e3cca3 | 3097 | gen8_gt_irq_reset(dev_priv); |
abd58f01 | 3098 | |
055e393f | 3099 | for_each_pipe(dev_priv, pipe) |
f458ebbc DV |
3100 | if (intel_display_power_is_enabled(dev_priv, |
3101 | POWER_DOMAIN_PIPE(pipe))) | |
813bde43 | 3102 | GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); |
abd58f01 | 3103 | |
f86f3fb0 PZ |
3104 | GEN5_IRQ_RESET(GEN8_DE_PORT_); |
3105 | GEN5_IRQ_RESET(GEN8_DE_MISC_); | |
3106 | GEN5_IRQ_RESET(GEN8_PCU_); | |
abd58f01 | 3107 | |
1c69eb42 | 3108 | ibx_irq_reset(dev); |
abd58f01 | 3109 | } |
09f2344d | 3110 | |
4c6c03be DL |
3111 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, |
3112 | unsigned int pipe_mask) | |
d49bdb0e | 3113 | { |
1180e206 | 3114 | uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; |
d49bdb0e | 3115 | |
13321786 | 3116 | spin_lock_irq(&dev_priv->irq_lock); |
d14c0343 DL |
3117 | if (pipe_mask & 1 << PIPE_A) |
3118 | GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_A, | |
3119 | dev_priv->de_irq_mask[PIPE_A], | |
3120 | ~dev_priv->de_irq_mask[PIPE_A] | extra_ier); | |
4c6c03be DL |
3121 | if (pipe_mask & 1 << PIPE_B) |
3122 | GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, | |
3123 | dev_priv->de_irq_mask[PIPE_B], | |
3124 | ~dev_priv->de_irq_mask[PIPE_B] | extra_ier); | |
3125 | if (pipe_mask & 1 << PIPE_C) | |
3126 | GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, | |
3127 | dev_priv->de_irq_mask[PIPE_C], | |
3128 | ~dev_priv->de_irq_mask[PIPE_C] | extra_ier); | |
13321786 | 3129 | spin_unlock_irq(&dev_priv->irq_lock); |
d49bdb0e PZ |
3130 | } |
3131 | ||
43f328d7 VS |
3132 | static void cherryview_irq_preinstall(struct drm_device *dev) |
3133 | { | |
3134 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43f328d7 VS |
3135 | |
3136 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3137 | POSTING_READ(GEN8_MASTER_IRQ); | |
3138 | ||
d6e3cca3 | 3139 | gen8_gt_irq_reset(dev_priv); |
43f328d7 VS |
3140 | |
3141 | GEN5_IRQ_RESET(GEN8_PCU_); | |
3142 | ||
43f328d7 VS |
3143 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV); |
3144 | ||
70591a41 | 3145 | vlv_display_irq_reset(dev_priv); |
43f328d7 VS |
3146 | } |
3147 | ||
82a28bcf | 3148 | static void ibx_hpd_irq_setup(struct drm_device *dev) |
7fe0b973 | 3149 | { |
2d1013dd | 3150 | struct drm_i915_private *dev_priv = dev->dev_private; |
82a28bcf | 3151 | struct intel_encoder *intel_encoder; |
fee884ed | 3152 | u32 hotplug_irqs, hotplug, enabled_irqs = 0; |
82a28bcf DV |
3153 | |
3154 | if (HAS_PCH_IBX(dev)) { | |
fee884ed | 3155 | hotplug_irqs = SDE_HOTPLUG_MASK; |
b2784e15 | 3156 | for_each_intel_encoder(dev, intel_encoder) |
cd569aed | 3157 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
fee884ed | 3158 | enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin]; |
82a28bcf | 3159 | } else { |
fee884ed | 3160 | hotplug_irqs = SDE_HOTPLUG_MASK_CPT; |
b2784e15 | 3161 | for_each_intel_encoder(dev, intel_encoder) |
cd569aed | 3162 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
fee884ed | 3163 | enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin]; |
82a28bcf | 3164 | } |
7fe0b973 | 3165 | |
fee884ed | 3166 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); |
82a28bcf DV |
3167 | |
3168 | /* | |
3169 | * Enable digital hotplug on the PCH, and configure the DP short pulse | |
3170 | * duration to 2ms (which is the minimum in the Display Port spec) | |
3171 | * | |
3172 | * This register is the same on all known PCH chips. | |
3173 | */ | |
7fe0b973 KP |
3174 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
3175 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); | |
3176 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; | |
3177 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; | |
3178 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; | |
3179 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); | |
3180 | } | |
3181 | ||
d46da437 PZ |
3182 | static void ibx_irq_postinstall(struct drm_device *dev) |
3183 | { | |
2d1013dd | 3184 | struct drm_i915_private *dev_priv = dev->dev_private; |
82a28bcf | 3185 | u32 mask; |
e5868a31 | 3186 | |
692a04cf DV |
3187 | if (HAS_PCH_NOP(dev)) |
3188 | return; | |
3189 | ||
105b122e | 3190 | if (HAS_PCH_IBX(dev)) |
5c673b60 | 3191 | mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; |
105b122e | 3192 | else |
5c673b60 | 3193 | mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; |
8664281b | 3194 | |
337ba017 | 3195 | GEN5_ASSERT_IIR_IS_ZERO(SDEIIR); |
d46da437 | 3196 | I915_WRITE(SDEIMR, ~mask); |
d46da437 PZ |
3197 | } |
3198 | ||
0a9a8c91 DV |
3199 | static void gen5_gt_irq_postinstall(struct drm_device *dev) |
3200 | { | |
3201 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3202 | u32 pm_irqs, gt_irqs; | |
3203 | ||
3204 | pm_irqs = gt_irqs = 0; | |
3205 | ||
3206 | dev_priv->gt_irq_mask = ~0; | |
040d2baa | 3207 | if (HAS_L3_DPF(dev)) { |
0a9a8c91 | 3208 | /* L3 parity interrupt is always unmasked. */ |
35a85ac6 BW |
3209 | dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev); |
3210 | gt_irqs |= GT_PARITY_ERROR(dev); | |
0a9a8c91 DV |
3211 | } |
3212 | ||
3213 | gt_irqs |= GT_RENDER_USER_INTERRUPT; | |
3214 | if (IS_GEN5(dev)) { | |
3215 | gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | | |
3216 | ILK_BSD_USER_INTERRUPT; | |
3217 | } else { | |
3218 | gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; | |
3219 | } | |
3220 | ||
35079899 | 3221 | GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); |
0a9a8c91 DV |
3222 | |
3223 | if (INTEL_INFO(dev)->gen >= 6) { | |
78e68d36 ID |
3224 | /* |
3225 | * RPS interrupts will get enabled/disabled on demand when RPS | |
3226 | * itself is enabled/disabled. | |
3227 | */ | |
0a9a8c91 DV |
3228 | if (HAS_VEBOX(dev)) |
3229 | pm_irqs |= PM_VEBOX_USER_INTERRUPT; | |
3230 | ||
605cd25b | 3231 | dev_priv->pm_irq_mask = 0xffffffff; |
35079899 | 3232 | GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs); |
0a9a8c91 DV |
3233 | } |
3234 | } | |
3235 | ||
f71d4af4 | 3236 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d | 3237 | { |
2d1013dd | 3238 | struct drm_i915_private *dev_priv = dev->dev_private; |
8e76f8dc PZ |
3239 | u32 display_mask, extra_mask; |
3240 | ||
3241 | if (INTEL_INFO(dev)->gen >= 7) { | |
3242 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | | |
3243 | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | | |
3244 | DE_PLANEB_FLIP_DONE_IVB | | |
5c673b60 | 3245 | DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB); |
8e76f8dc | 3246 | extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | |
5c673b60 | 3247 | DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB); |
8e76f8dc PZ |
3248 | } else { |
3249 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | | |
3250 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | | |
5b3a856b | 3251 | DE_AUX_CHANNEL_A | |
5b3a856b DV |
3252 | DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE | |
3253 | DE_POISON); | |
5c673b60 DV |
3254 | extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT | |
3255 | DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN; | |
8e76f8dc | 3256 | } |
036a4a7d | 3257 | |
1ec14ad3 | 3258 | dev_priv->irq_mask = ~display_mask; |
036a4a7d | 3259 | |
0c841212 PZ |
3260 | I915_WRITE(HWSTAM, 0xeffe); |
3261 | ||
622364b6 PZ |
3262 | ibx_irq_pre_postinstall(dev); |
3263 | ||
35079899 | 3264 | GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); |
036a4a7d | 3265 | |
0a9a8c91 | 3266 | gen5_gt_irq_postinstall(dev); |
036a4a7d | 3267 | |
d46da437 | 3268 | ibx_irq_postinstall(dev); |
7fe0b973 | 3269 | |
f97108d1 | 3270 | if (IS_IRONLAKE_M(dev)) { |
6005ce42 DV |
3271 | /* Enable PCU event interrupts |
3272 | * | |
3273 | * spinlocking not required here for correctness since interrupt | |
4bc9d430 DV |
3274 | * setup is guaranteed to run in single-threaded context. But we |
3275 | * need it to make the assert_spin_locked happy. */ | |
d6207435 | 3276 | spin_lock_irq(&dev_priv->irq_lock); |
f97108d1 | 3277 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); |
d6207435 | 3278 | spin_unlock_irq(&dev_priv->irq_lock); |
f97108d1 JB |
3279 | } |
3280 | ||
036a4a7d ZW |
3281 | return 0; |
3282 | } | |
3283 | ||
f8b79e58 ID |
3284 | static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv) |
3285 | { | |
3286 | u32 pipestat_mask; | |
3287 | u32 iir_mask; | |
120dda4f | 3288 | enum pipe pipe; |
f8b79e58 ID |
3289 | |
3290 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | | |
3291 | PIPE_FIFO_UNDERRUN_STATUS; | |
3292 | ||
120dda4f VS |
3293 | for_each_pipe(dev_priv, pipe) |
3294 | I915_WRITE(PIPESTAT(pipe), pipestat_mask); | |
f8b79e58 ID |
3295 | POSTING_READ(PIPESTAT(PIPE_A)); |
3296 | ||
3297 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3298 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3299 | ||
120dda4f VS |
3300 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
3301 | for_each_pipe(dev_priv, pipe) | |
3302 | i915_enable_pipestat(dev_priv, pipe, pipestat_mask); | |
f8b79e58 ID |
3303 | |
3304 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3305 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3306 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
120dda4f VS |
3307 | if (IS_CHERRYVIEW(dev_priv)) |
3308 | iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
f8b79e58 ID |
3309 | dev_priv->irq_mask &= ~iir_mask; |
3310 | ||
3311 | I915_WRITE(VLV_IIR, iir_mask); | |
3312 | I915_WRITE(VLV_IIR, iir_mask); | |
f8b79e58 | 3313 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); |
76e41860 VS |
3314 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
3315 | POSTING_READ(VLV_IMR); | |
f8b79e58 ID |
3316 | } |
3317 | ||
3318 | static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv) | |
3319 | { | |
3320 | u32 pipestat_mask; | |
3321 | u32 iir_mask; | |
120dda4f | 3322 | enum pipe pipe; |
f8b79e58 ID |
3323 | |
3324 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3325 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
6c7fba04 | 3326 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; |
120dda4f VS |
3327 | if (IS_CHERRYVIEW(dev_priv)) |
3328 | iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
f8b79e58 ID |
3329 | |
3330 | dev_priv->irq_mask |= iir_mask; | |
f8b79e58 | 3331 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
76e41860 | 3332 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); |
f8b79e58 ID |
3333 | I915_WRITE(VLV_IIR, iir_mask); |
3334 | I915_WRITE(VLV_IIR, iir_mask); | |
3335 | POSTING_READ(VLV_IIR); | |
3336 | ||
3337 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3338 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3339 | ||
120dda4f VS |
3340 | i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
3341 | for_each_pipe(dev_priv, pipe) | |
3342 | i915_disable_pipestat(dev_priv, pipe, pipestat_mask); | |
f8b79e58 ID |
3343 | |
3344 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | | |
3345 | PIPE_FIFO_UNDERRUN_STATUS; | |
120dda4f VS |
3346 | |
3347 | for_each_pipe(dev_priv, pipe) | |
3348 | I915_WRITE(PIPESTAT(pipe), pipestat_mask); | |
f8b79e58 ID |
3349 | POSTING_READ(PIPESTAT(PIPE_A)); |
3350 | } | |
3351 | ||
3352 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) | |
3353 | { | |
3354 | assert_spin_locked(&dev_priv->irq_lock); | |
3355 | ||
3356 | if (dev_priv->display_irqs_enabled) | |
3357 | return; | |
3358 | ||
3359 | dev_priv->display_irqs_enabled = true; | |
3360 | ||
950eabaf | 3361 | if (intel_irqs_enabled(dev_priv)) |
f8b79e58 ID |
3362 | valleyview_display_irqs_install(dev_priv); |
3363 | } | |
3364 | ||
3365 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) | |
3366 | { | |
3367 | assert_spin_locked(&dev_priv->irq_lock); | |
3368 | ||
3369 | if (!dev_priv->display_irqs_enabled) | |
3370 | return; | |
3371 | ||
3372 | dev_priv->display_irqs_enabled = false; | |
3373 | ||
950eabaf | 3374 | if (intel_irqs_enabled(dev_priv)) |
f8b79e58 ID |
3375 | valleyview_display_irqs_uninstall(dev_priv); |
3376 | } | |
3377 | ||
0e6c9a9e | 3378 | static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) |
7e231dbe | 3379 | { |
f8b79e58 | 3380 | dev_priv->irq_mask = ~0; |
7e231dbe | 3381 | |
20afbda2 DV |
3382 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3383 | POSTING_READ(PORT_HOTPLUG_EN); | |
3384 | ||
7e231dbe | 3385 | I915_WRITE(VLV_IIR, 0xffffffff); |
76e41860 VS |
3386 | I915_WRITE(VLV_IIR, 0xffffffff); |
3387 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); | |
3388 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); | |
3389 | POSTING_READ(VLV_IMR); | |
7e231dbe | 3390 | |
b79480ba DV |
3391 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3392 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3393 | spin_lock_irq(&dev_priv->irq_lock); |
f8b79e58 ID |
3394 | if (dev_priv->display_irqs_enabled) |
3395 | valleyview_display_irqs_install(dev_priv); | |
d6207435 | 3396 | spin_unlock_irq(&dev_priv->irq_lock); |
0e6c9a9e VS |
3397 | } |
3398 | ||
3399 | static int valleyview_irq_postinstall(struct drm_device *dev) | |
3400 | { | |
3401 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3402 | ||
3403 | vlv_display_irq_postinstall(dev_priv); | |
7e231dbe | 3404 | |
0a9a8c91 | 3405 | gen5_gt_irq_postinstall(dev); |
7e231dbe JB |
3406 | |
3407 | /* ack & enable invalid PTE error interrupts */ | |
3408 | #if 0 /* FIXME: add support to irq handler for checking these bits */ | |
3409 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); | |
3410 | I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); | |
3411 | #endif | |
3412 | ||
3413 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); | |
20afbda2 DV |
3414 | |
3415 | return 0; | |
3416 | } | |
3417 | ||
abd58f01 BW |
3418 | static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) |
3419 | { | |
abd58f01 BW |
3420 | /* These are interrupts we'll toggle with the ring mask register */ |
3421 | uint32_t gt_interrupts[] = { | |
3422 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | | |
73d477f6 | 3423 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT | |
abd58f01 | 3424 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT | |
73d477f6 OM |
3425 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT | |
3426 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT, | |
abd58f01 | 3427 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
73d477f6 OM |
3428 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
3429 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT | | |
3430 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT, | |
abd58f01 | 3431 | 0, |
73d477f6 OM |
3432 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
3433 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
abd58f01 BW |
3434 | }; |
3435 | ||
0961021a | 3436 | dev_priv->pm_irq_mask = 0xffffffff; |
9a2d2d87 D |
3437 | GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]); |
3438 | GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]); | |
78e68d36 ID |
3439 | /* |
3440 | * RPS interrupts will get enabled/disabled on demand when RPS itself | |
3441 | * is enabled/disabled. | |
3442 | */ | |
3443 | GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0); | |
9a2d2d87 | 3444 | GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]); |
abd58f01 BW |
3445 | } |
3446 | ||
3447 | static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) | |
3448 | { | |
770de83d DL |
3449 | uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE; |
3450 | uint32_t de_pipe_enables; | |
abd58f01 | 3451 | int pipe; |
88e04703 | 3452 | u32 aux_en = GEN8_AUX_CHANNEL_A; |
770de83d | 3453 | |
88e04703 | 3454 | if (IS_GEN9(dev_priv)) { |
770de83d DL |
3455 | de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE | |
3456 | GEN9_DE_PIPE_IRQ_FAULT_ERRORS; | |
88e04703 JB |
3457 | aux_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | |
3458 | GEN9_AUX_CHANNEL_D; | |
3459 | } else | |
770de83d DL |
3460 | de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE | |
3461 | GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
3462 | ||
3463 | de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | | |
3464 | GEN8_PIPE_FIFO_UNDERRUN; | |
3465 | ||
13b3a0a7 DV |
3466 | dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; |
3467 | dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; | |
3468 | dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; | |
abd58f01 | 3469 | |
055e393f | 3470 | for_each_pipe(dev_priv, pipe) |
f458ebbc | 3471 | if (intel_display_power_is_enabled(dev_priv, |
813bde43 PZ |
3472 | POWER_DOMAIN_PIPE(pipe))) |
3473 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, | |
3474 | dev_priv->de_irq_mask[pipe], | |
3475 | de_pipe_enables); | |
abd58f01 | 3476 | |
88e04703 | 3477 | GEN5_IRQ_INIT(GEN8_DE_PORT_, ~aux_en, aux_en); |
abd58f01 BW |
3478 | } |
3479 | ||
3480 | static int gen8_irq_postinstall(struct drm_device *dev) | |
3481 | { | |
3482 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3483 | ||
622364b6 PZ |
3484 | ibx_irq_pre_postinstall(dev); |
3485 | ||
abd58f01 BW |
3486 | gen8_gt_irq_postinstall(dev_priv); |
3487 | gen8_de_irq_postinstall(dev_priv); | |
3488 | ||
3489 | ibx_irq_postinstall(dev); | |
3490 | ||
3491 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); | |
3492 | POSTING_READ(GEN8_MASTER_IRQ); | |
3493 | ||
3494 | return 0; | |
3495 | } | |
3496 | ||
43f328d7 VS |
3497 | static int cherryview_irq_postinstall(struct drm_device *dev) |
3498 | { | |
3499 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43f328d7 | 3500 | |
c2b66797 | 3501 | vlv_display_irq_postinstall(dev_priv); |
43f328d7 VS |
3502 | |
3503 | gen8_gt_irq_postinstall(dev_priv); | |
3504 | ||
3505 | I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE); | |
3506 | POSTING_READ(GEN8_MASTER_IRQ); | |
3507 | ||
3508 | return 0; | |
3509 | } | |
3510 | ||
abd58f01 BW |
3511 | static void gen8_irq_uninstall(struct drm_device *dev) |
3512 | { | |
3513 | struct drm_i915_private *dev_priv = dev->dev_private; | |
abd58f01 BW |
3514 | |
3515 | if (!dev_priv) | |
3516 | return; | |
3517 | ||
823f6b38 | 3518 | gen8_irq_reset(dev); |
abd58f01 BW |
3519 | } |
3520 | ||
8ea0be4f VS |
3521 | static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv) |
3522 | { | |
3523 | /* Interrupt setup is already guaranteed to be single-threaded, this is | |
3524 | * just to make the assert_spin_locked check happy. */ | |
3525 | spin_lock_irq(&dev_priv->irq_lock); | |
3526 | if (dev_priv->display_irqs_enabled) | |
3527 | valleyview_display_irqs_uninstall(dev_priv); | |
3528 | spin_unlock_irq(&dev_priv->irq_lock); | |
3529 | ||
3530 | vlv_display_irq_reset(dev_priv); | |
3531 | ||
c352d1ba | 3532 | dev_priv->irq_mask = ~0; |
8ea0be4f VS |
3533 | } |
3534 | ||
7e231dbe JB |
3535 | static void valleyview_irq_uninstall(struct drm_device *dev) |
3536 | { | |
2d1013dd | 3537 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
3538 | |
3539 | if (!dev_priv) | |
3540 | return; | |
3541 | ||
843d0e7d ID |
3542 | I915_WRITE(VLV_MASTER_IER, 0); |
3543 | ||
893fce8e VS |
3544 | gen5_gt_irq_reset(dev); |
3545 | ||
7e231dbe | 3546 | I915_WRITE(HWSTAM, 0xffffffff); |
f8b79e58 | 3547 | |
8ea0be4f | 3548 | vlv_display_irq_uninstall(dev_priv); |
7e231dbe JB |
3549 | } |
3550 | ||
43f328d7 VS |
3551 | static void cherryview_irq_uninstall(struct drm_device *dev) |
3552 | { | |
3553 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43f328d7 VS |
3554 | |
3555 | if (!dev_priv) | |
3556 | return; | |
3557 | ||
3558 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3559 | POSTING_READ(GEN8_MASTER_IRQ); | |
3560 | ||
a2c30fba | 3561 | gen8_gt_irq_reset(dev_priv); |
43f328d7 | 3562 | |
a2c30fba | 3563 | GEN5_IRQ_RESET(GEN8_PCU_); |
43f328d7 | 3564 | |
c2b66797 | 3565 | vlv_display_irq_uninstall(dev_priv); |
43f328d7 VS |
3566 | } |
3567 | ||
f71d4af4 | 3568 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d | 3569 | { |
2d1013dd | 3570 | struct drm_i915_private *dev_priv = dev->dev_private; |
4697995b JB |
3571 | |
3572 | if (!dev_priv) | |
3573 | return; | |
3574 | ||
be30b29f | 3575 | ironlake_irq_reset(dev); |
036a4a7d ZW |
3576 | } |
3577 | ||
a266c7d5 | 3578 | static void i8xx_irq_preinstall(struct drm_device * dev) |
1da177e4 | 3579 | { |
2d1013dd | 3580 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 3581 | int pipe; |
91e3738e | 3582 | |
055e393f | 3583 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 | 3584 | I915_WRITE(PIPESTAT(pipe), 0); |
a266c7d5 CW |
3585 | I915_WRITE16(IMR, 0xffff); |
3586 | I915_WRITE16(IER, 0x0); | |
3587 | POSTING_READ16(IER); | |
c2798b19 CW |
3588 | } |
3589 | ||
3590 | static int i8xx_irq_postinstall(struct drm_device *dev) | |
3591 | { | |
2d1013dd | 3592 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 | 3593 | |
c2798b19 CW |
3594 | I915_WRITE16(EMR, |
3595 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); | |
3596 | ||
3597 | /* Unmask the interrupts that we always want on. */ | |
3598 | dev_priv->irq_mask = | |
3599 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3600 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3601 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3602 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3603 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3604 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
3605 | ||
3606 | I915_WRITE16(IER, | |
3607 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3608 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3609 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
3610 | I915_USER_INTERRUPT); | |
3611 | POSTING_READ16(IER); | |
3612 | ||
379ef82d DV |
3613 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3614 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3615 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
3616 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3617 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 3618 | spin_unlock_irq(&dev_priv->irq_lock); |
379ef82d | 3619 | |
c2798b19 CW |
3620 | return 0; |
3621 | } | |
3622 | ||
90a72f87 VS |
3623 | /* |
3624 | * Returns true when a page flip has completed. | |
3625 | */ | |
3626 | static bool i8xx_handle_vblank(struct drm_device *dev, | |
1f1c2e24 | 3627 | int plane, int pipe, u32 iir) |
90a72f87 | 3628 | { |
2d1013dd | 3629 | struct drm_i915_private *dev_priv = dev->dev_private; |
1f1c2e24 | 3630 | u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
90a72f87 | 3631 | |
8d7849db | 3632 | if (!intel_pipe_handle_vblank(dev, pipe)) |
90a72f87 VS |
3633 | return false; |
3634 | ||
3635 | if ((iir & flip_pending) == 0) | |
d6bbafa1 | 3636 | goto check_page_flip; |
90a72f87 | 3637 | |
90a72f87 VS |
3638 | /* We detect FlipDone by looking for the change in PendingFlip from '1' |
3639 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3640 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3641 | * the flip is completed (no longer pending). Since this doesn't raise | |
3642 | * an interrupt per se, we watch for the change at vblank. | |
3643 | */ | |
3644 | if (I915_READ16(ISR) & flip_pending) | |
d6bbafa1 | 3645 | goto check_page_flip; |
90a72f87 | 3646 | |
7d47559e | 3647 | intel_prepare_page_flip(dev, plane); |
90a72f87 | 3648 | intel_finish_page_flip(dev, pipe); |
90a72f87 | 3649 | return true; |
d6bbafa1 CW |
3650 | |
3651 | check_page_flip: | |
3652 | intel_check_page_flip(dev, pipe); | |
3653 | return false; | |
90a72f87 VS |
3654 | } |
3655 | ||
ff1f525e | 3656 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
c2798b19 | 3657 | { |
45a83f84 | 3658 | struct drm_device *dev = arg; |
2d1013dd | 3659 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
3660 | u16 iir, new_iir; |
3661 | u32 pipe_stats[2]; | |
c2798b19 CW |
3662 | int pipe; |
3663 | u16 flip_mask = | |
3664 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3665 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
3666 | ||
2dd2a883 ID |
3667 | if (!intel_irqs_enabled(dev_priv)) |
3668 | return IRQ_NONE; | |
3669 | ||
c2798b19 CW |
3670 | iir = I915_READ16(IIR); |
3671 | if (iir == 0) | |
3672 | return IRQ_NONE; | |
3673 | ||
3674 | while (iir & ~flip_mask) { | |
3675 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3676 | * have been cleared after the pipestat interrupt was received. | |
3677 | * It doesn't set the bit in iir again, but it still produces | |
3678 | * interrupts (for non-MSI). | |
3679 | */ | |
222c7f51 | 3680 | spin_lock(&dev_priv->irq_lock); |
c2798b19 | 3681 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 3682 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
c2798b19 | 3683 | |
055e393f | 3684 | for_each_pipe(dev_priv, pipe) { |
c2798b19 CW |
3685 | int reg = PIPESTAT(pipe); |
3686 | pipe_stats[pipe] = I915_READ(reg); | |
3687 | ||
3688 | /* | |
3689 | * Clear the PIPE*STAT regs before the IIR | |
3690 | */ | |
2d9d2b0b | 3691 | if (pipe_stats[pipe] & 0x8000ffff) |
c2798b19 | 3692 | I915_WRITE(reg, pipe_stats[pipe]); |
c2798b19 | 3693 | } |
222c7f51 | 3694 | spin_unlock(&dev_priv->irq_lock); |
c2798b19 CW |
3695 | |
3696 | I915_WRITE16(IIR, iir & ~flip_mask); | |
3697 | new_iir = I915_READ16(IIR); /* Flush posted writes */ | |
3698 | ||
c2798b19 CW |
3699 | if (iir & I915_USER_INTERRUPT) |
3700 | notify_ring(dev, &dev_priv->ring[RCS]); | |
3701 | ||
055e393f | 3702 | for_each_pipe(dev_priv, pipe) { |
1f1c2e24 | 3703 | int plane = pipe; |
3a77c4c4 | 3704 | if (HAS_FBC(dev)) |
1f1c2e24 VS |
3705 | plane = !plane; |
3706 | ||
4356d586 | 3707 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
1f1c2e24 VS |
3708 | i8xx_handle_vblank(dev, plane, pipe, iir)) |
3709 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
c2798b19 | 3710 | |
4356d586 | 3711 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
277de95e | 3712 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b | 3713 | |
1f7247c0 DV |
3714 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
3715 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
3716 | pipe); | |
4356d586 | 3717 | } |
c2798b19 CW |
3718 | |
3719 | iir = new_iir; | |
3720 | } | |
3721 | ||
3722 | return IRQ_HANDLED; | |
3723 | } | |
3724 | ||
3725 | static void i8xx_irq_uninstall(struct drm_device * dev) | |
3726 | { | |
2d1013dd | 3727 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
3728 | int pipe; |
3729 | ||
055e393f | 3730 | for_each_pipe(dev_priv, pipe) { |
c2798b19 CW |
3731 | /* Clear enable bits; then clear status bits */ |
3732 | I915_WRITE(PIPESTAT(pipe), 0); | |
3733 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); | |
3734 | } | |
3735 | I915_WRITE16(IMR, 0xffff); | |
3736 | I915_WRITE16(IER, 0x0); | |
3737 | I915_WRITE16(IIR, I915_READ16(IIR)); | |
3738 | } | |
3739 | ||
a266c7d5 CW |
3740 | static void i915_irq_preinstall(struct drm_device * dev) |
3741 | { | |
2d1013dd | 3742 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3743 | int pipe; |
3744 | ||
a266c7d5 CW |
3745 | if (I915_HAS_HOTPLUG(dev)) { |
3746 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3747 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3748 | } | |
3749 | ||
00d98ebd | 3750 | I915_WRITE16(HWSTAM, 0xeffe); |
055e393f | 3751 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
3752 | I915_WRITE(PIPESTAT(pipe), 0); |
3753 | I915_WRITE(IMR, 0xffffffff); | |
3754 | I915_WRITE(IER, 0x0); | |
3755 | POSTING_READ(IER); | |
3756 | } | |
3757 | ||
3758 | static int i915_irq_postinstall(struct drm_device *dev) | |
3759 | { | |
2d1013dd | 3760 | struct drm_i915_private *dev_priv = dev->dev_private; |
38bde180 | 3761 | u32 enable_mask; |
a266c7d5 | 3762 | |
38bde180 CW |
3763 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
3764 | ||
3765 | /* Unmask the interrupts that we always want on. */ | |
3766 | dev_priv->irq_mask = | |
3767 | ~(I915_ASLE_INTERRUPT | | |
3768 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3769 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3770 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3771 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3772 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3773 | ||
3774 | enable_mask = | |
3775 | I915_ASLE_INTERRUPT | | |
3776 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3777 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3778 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
3779 | I915_USER_INTERRUPT; | |
3780 | ||
a266c7d5 | 3781 | if (I915_HAS_HOTPLUG(dev)) { |
20afbda2 DV |
3782 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3783 | POSTING_READ(PORT_HOTPLUG_EN); | |
3784 | ||
a266c7d5 CW |
3785 | /* Enable in IER... */ |
3786 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
3787 | /* and unmask in IMR */ | |
3788 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; | |
3789 | } | |
3790 | ||
a266c7d5 CW |
3791 | I915_WRITE(IMR, dev_priv->irq_mask); |
3792 | I915_WRITE(IER, enable_mask); | |
3793 | POSTING_READ(IER); | |
3794 | ||
f49e38dd | 3795 | i915_enable_asle_pipestat(dev); |
20afbda2 | 3796 | |
379ef82d DV |
3797 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3798 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3799 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
3800 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3801 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 3802 | spin_unlock_irq(&dev_priv->irq_lock); |
379ef82d | 3803 | |
20afbda2 DV |
3804 | return 0; |
3805 | } | |
3806 | ||
90a72f87 VS |
3807 | /* |
3808 | * Returns true when a page flip has completed. | |
3809 | */ | |
3810 | static bool i915_handle_vblank(struct drm_device *dev, | |
3811 | int plane, int pipe, u32 iir) | |
3812 | { | |
2d1013dd | 3813 | struct drm_i915_private *dev_priv = dev->dev_private; |
90a72f87 VS |
3814 | u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
3815 | ||
8d7849db | 3816 | if (!intel_pipe_handle_vblank(dev, pipe)) |
90a72f87 VS |
3817 | return false; |
3818 | ||
3819 | if ((iir & flip_pending) == 0) | |
d6bbafa1 | 3820 | goto check_page_flip; |
90a72f87 | 3821 | |
90a72f87 VS |
3822 | /* We detect FlipDone by looking for the change in PendingFlip from '1' |
3823 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3824 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3825 | * the flip is completed (no longer pending). Since this doesn't raise | |
3826 | * an interrupt per se, we watch for the change at vblank. | |
3827 | */ | |
3828 | if (I915_READ(ISR) & flip_pending) | |
d6bbafa1 | 3829 | goto check_page_flip; |
90a72f87 | 3830 | |
7d47559e | 3831 | intel_prepare_page_flip(dev, plane); |
90a72f87 | 3832 | intel_finish_page_flip(dev, pipe); |
90a72f87 | 3833 | return true; |
d6bbafa1 CW |
3834 | |
3835 | check_page_flip: | |
3836 | intel_check_page_flip(dev, pipe); | |
3837 | return false; | |
90a72f87 VS |
3838 | } |
3839 | ||
ff1f525e | 3840 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
a266c7d5 | 3841 | { |
45a83f84 | 3842 | struct drm_device *dev = arg; |
2d1013dd | 3843 | struct drm_i915_private *dev_priv = dev->dev_private; |
8291ee90 | 3844 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
38bde180 CW |
3845 | u32 flip_mask = |
3846 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3847 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
38bde180 | 3848 | int pipe, ret = IRQ_NONE; |
a266c7d5 | 3849 | |
2dd2a883 ID |
3850 | if (!intel_irqs_enabled(dev_priv)) |
3851 | return IRQ_NONE; | |
3852 | ||
a266c7d5 | 3853 | iir = I915_READ(IIR); |
38bde180 CW |
3854 | do { |
3855 | bool irq_received = (iir & ~flip_mask) != 0; | |
8291ee90 | 3856 | bool blc_event = false; |
a266c7d5 CW |
3857 | |
3858 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3859 | * have been cleared after the pipestat interrupt was received. | |
3860 | * It doesn't set the bit in iir again, but it still produces | |
3861 | * interrupts (for non-MSI). | |
3862 | */ | |
222c7f51 | 3863 | spin_lock(&dev_priv->irq_lock); |
a266c7d5 | 3864 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 3865 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
a266c7d5 | 3866 | |
055e393f | 3867 | for_each_pipe(dev_priv, pipe) { |
a266c7d5 CW |
3868 | int reg = PIPESTAT(pipe); |
3869 | pipe_stats[pipe] = I915_READ(reg); | |
3870 | ||
38bde180 | 3871 | /* Clear the PIPE*STAT regs before the IIR */ |
a266c7d5 | 3872 | if (pipe_stats[pipe] & 0x8000ffff) { |
a266c7d5 | 3873 | I915_WRITE(reg, pipe_stats[pipe]); |
38bde180 | 3874 | irq_received = true; |
a266c7d5 CW |
3875 | } |
3876 | } | |
222c7f51 | 3877 | spin_unlock(&dev_priv->irq_lock); |
a266c7d5 CW |
3878 | |
3879 | if (!irq_received) | |
3880 | break; | |
3881 | ||
a266c7d5 | 3882 | /* Consume port. Then clear IIR or we'll miss events */ |
16c6c56b VS |
3883 | if (I915_HAS_HOTPLUG(dev) && |
3884 | iir & I915_DISPLAY_PORT_INTERRUPT) | |
3885 | i9xx_hpd_irq_handler(dev); | |
a266c7d5 | 3886 | |
38bde180 | 3887 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
3888 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
3889 | ||
a266c7d5 CW |
3890 | if (iir & I915_USER_INTERRUPT) |
3891 | notify_ring(dev, &dev_priv->ring[RCS]); | |
a266c7d5 | 3892 | |
055e393f | 3893 | for_each_pipe(dev_priv, pipe) { |
38bde180 | 3894 | int plane = pipe; |
3a77c4c4 | 3895 | if (HAS_FBC(dev)) |
38bde180 | 3896 | plane = !plane; |
90a72f87 | 3897 | |
8291ee90 | 3898 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
3899 | i915_handle_vblank(dev, plane, pipe, iir)) |
3900 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
a266c7d5 CW |
3901 | |
3902 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
3903 | blc_event = true; | |
4356d586 DV |
3904 | |
3905 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 3906 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b | 3907 | |
1f7247c0 DV |
3908 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
3909 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
3910 | pipe); | |
a266c7d5 CW |
3911 | } |
3912 | ||
a266c7d5 CW |
3913 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
3914 | intel_opregion_asle_intr(dev); | |
3915 | ||
3916 | /* With MSI, interrupts are only generated when iir | |
3917 | * transitions from zero to nonzero. If another bit got | |
3918 | * set while we were handling the existing iir bits, then | |
3919 | * we would never get another interrupt. | |
3920 | * | |
3921 | * This is fine on non-MSI as well, as if we hit this path | |
3922 | * we avoid exiting the interrupt handler only to generate | |
3923 | * another one. | |
3924 | * | |
3925 | * Note that for MSI this could cause a stray interrupt report | |
3926 | * if an interrupt landed in the time between writing IIR and | |
3927 | * the posting read. This should be rare enough to never | |
3928 | * trigger the 99% of 100,000 interrupts test for disabling | |
3929 | * stray interrupts. | |
3930 | */ | |
38bde180 | 3931 | ret = IRQ_HANDLED; |
a266c7d5 | 3932 | iir = new_iir; |
38bde180 | 3933 | } while (iir & ~flip_mask); |
a266c7d5 CW |
3934 | |
3935 | return ret; | |
3936 | } | |
3937 | ||
3938 | static void i915_irq_uninstall(struct drm_device * dev) | |
3939 | { | |
2d1013dd | 3940 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3941 | int pipe; |
3942 | ||
a266c7d5 CW |
3943 | if (I915_HAS_HOTPLUG(dev)) { |
3944 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3945 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3946 | } | |
3947 | ||
00d98ebd | 3948 | I915_WRITE16(HWSTAM, 0xffff); |
055e393f | 3949 | for_each_pipe(dev_priv, pipe) { |
55b39755 | 3950 | /* Clear enable bits; then clear status bits */ |
a266c7d5 | 3951 | I915_WRITE(PIPESTAT(pipe), 0); |
55b39755 CW |
3952 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
3953 | } | |
a266c7d5 CW |
3954 | I915_WRITE(IMR, 0xffffffff); |
3955 | I915_WRITE(IER, 0x0); | |
3956 | ||
a266c7d5 CW |
3957 | I915_WRITE(IIR, I915_READ(IIR)); |
3958 | } | |
3959 | ||
3960 | static void i965_irq_preinstall(struct drm_device * dev) | |
3961 | { | |
2d1013dd | 3962 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3963 | int pipe; |
3964 | ||
adca4730 CW |
3965 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3966 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
3967 | |
3968 | I915_WRITE(HWSTAM, 0xeffe); | |
055e393f | 3969 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
3970 | I915_WRITE(PIPESTAT(pipe), 0); |
3971 | I915_WRITE(IMR, 0xffffffff); | |
3972 | I915_WRITE(IER, 0x0); | |
3973 | POSTING_READ(IER); | |
3974 | } | |
3975 | ||
3976 | static int i965_irq_postinstall(struct drm_device *dev) | |
3977 | { | |
2d1013dd | 3978 | struct drm_i915_private *dev_priv = dev->dev_private; |
bbba0a97 | 3979 | u32 enable_mask; |
a266c7d5 CW |
3980 | u32 error_mask; |
3981 | ||
a266c7d5 | 3982 | /* Unmask the interrupts that we always want on. */ |
bbba0a97 | 3983 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
adca4730 | 3984 | I915_DISPLAY_PORT_INTERRUPT | |
bbba0a97 CW |
3985 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
3986 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3987 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3988 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3989 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3990 | ||
3991 | enable_mask = ~dev_priv->irq_mask; | |
21ad8330 VS |
3992 | enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
3993 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); | |
bbba0a97 CW |
3994 | enable_mask |= I915_USER_INTERRUPT; |
3995 | ||
3996 | if (IS_G4X(dev)) | |
3997 | enable_mask |= I915_BSD_USER_INTERRUPT; | |
a266c7d5 | 3998 | |
b79480ba DV |
3999 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
4000 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 4001 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
4002 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
4003 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
4004 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 4005 | spin_unlock_irq(&dev_priv->irq_lock); |
a266c7d5 | 4006 | |
a266c7d5 CW |
4007 | /* |
4008 | * Enable some error detection, note the instruction error mask | |
4009 | * bit is reserved, so we leave it masked. | |
4010 | */ | |
4011 | if (IS_G4X(dev)) { | |
4012 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
4013 | GM45_ERROR_MEM_PRIV | | |
4014 | GM45_ERROR_CP_PRIV | | |
4015 | I915_ERROR_MEMORY_REFRESH); | |
4016 | } else { | |
4017 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
4018 | I915_ERROR_MEMORY_REFRESH); | |
4019 | } | |
4020 | I915_WRITE(EMR, error_mask); | |
4021 | ||
4022 | I915_WRITE(IMR, dev_priv->irq_mask); | |
4023 | I915_WRITE(IER, enable_mask); | |
4024 | POSTING_READ(IER); | |
4025 | ||
20afbda2 DV |
4026 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
4027 | POSTING_READ(PORT_HOTPLUG_EN); | |
4028 | ||
f49e38dd | 4029 | i915_enable_asle_pipestat(dev); |
20afbda2 DV |
4030 | |
4031 | return 0; | |
4032 | } | |
4033 | ||
bac56d5b | 4034 | static void i915_hpd_irq_setup(struct drm_device *dev) |
20afbda2 | 4035 | { |
2d1013dd | 4036 | struct drm_i915_private *dev_priv = dev->dev_private; |
cd569aed | 4037 | struct intel_encoder *intel_encoder; |
20afbda2 DV |
4038 | u32 hotplug_en; |
4039 | ||
b5ea2d56 DV |
4040 | assert_spin_locked(&dev_priv->irq_lock); |
4041 | ||
778eb334 VS |
4042 | hotplug_en = I915_READ(PORT_HOTPLUG_EN); |
4043 | hotplug_en &= ~HOTPLUG_INT_EN_MASK; | |
4044 | /* Note HDMI and DP share hotplug bits */ | |
4045 | /* enable bits are the same for all generations */ | |
4046 | for_each_intel_encoder(dev, intel_encoder) | |
4047 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) | |
4048 | hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin]; | |
4049 | /* Programming the CRT detection parameters tends | |
4050 | to generate a spurious hotplug event about three | |
4051 | seconds later. So just do it once. | |
4052 | */ | |
4053 | if (IS_G4X(dev)) | |
4054 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
4055 | hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK; | |
4056 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; | |
4057 | ||
4058 | /* Ignore TV since it's buggy */ | |
4059 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
a266c7d5 CW |
4060 | } |
4061 | ||
ff1f525e | 4062 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
a266c7d5 | 4063 | { |
45a83f84 | 4064 | struct drm_device *dev = arg; |
2d1013dd | 4065 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4066 | u32 iir, new_iir; |
4067 | u32 pipe_stats[I915_MAX_PIPES]; | |
a266c7d5 | 4068 | int ret = IRQ_NONE, pipe; |
21ad8330 VS |
4069 | u32 flip_mask = |
4070 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4071 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
a266c7d5 | 4072 | |
2dd2a883 ID |
4073 | if (!intel_irqs_enabled(dev_priv)) |
4074 | return IRQ_NONE; | |
4075 | ||
a266c7d5 CW |
4076 | iir = I915_READ(IIR); |
4077 | ||
a266c7d5 | 4078 | for (;;) { |
501e01d7 | 4079 | bool irq_received = (iir & ~flip_mask) != 0; |
2c8ba29f CW |
4080 | bool blc_event = false; |
4081 | ||
a266c7d5 CW |
4082 | /* Can't rely on pipestat interrupt bit in iir as it might |
4083 | * have been cleared after the pipestat interrupt was received. | |
4084 | * It doesn't set the bit in iir again, but it still produces | |
4085 | * interrupts (for non-MSI). | |
4086 | */ | |
222c7f51 | 4087 | spin_lock(&dev_priv->irq_lock); |
a266c7d5 | 4088 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 4089 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
a266c7d5 | 4090 | |
055e393f | 4091 | for_each_pipe(dev_priv, pipe) { |
a266c7d5 CW |
4092 | int reg = PIPESTAT(pipe); |
4093 | pipe_stats[pipe] = I915_READ(reg); | |
4094 | ||
4095 | /* | |
4096 | * Clear the PIPE*STAT regs before the IIR | |
4097 | */ | |
4098 | if (pipe_stats[pipe] & 0x8000ffff) { | |
a266c7d5 | 4099 | I915_WRITE(reg, pipe_stats[pipe]); |
501e01d7 | 4100 | irq_received = true; |
a266c7d5 CW |
4101 | } |
4102 | } | |
222c7f51 | 4103 | spin_unlock(&dev_priv->irq_lock); |
a266c7d5 CW |
4104 | |
4105 | if (!irq_received) | |
4106 | break; | |
4107 | ||
4108 | ret = IRQ_HANDLED; | |
4109 | ||
4110 | /* Consume port. Then clear IIR or we'll miss events */ | |
16c6c56b VS |
4111 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
4112 | i9xx_hpd_irq_handler(dev); | |
a266c7d5 | 4113 | |
21ad8330 | 4114 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
4115 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
4116 | ||
a266c7d5 CW |
4117 | if (iir & I915_USER_INTERRUPT) |
4118 | notify_ring(dev, &dev_priv->ring[RCS]); | |
4119 | if (iir & I915_BSD_USER_INTERRUPT) | |
4120 | notify_ring(dev, &dev_priv->ring[VCS]); | |
4121 | ||
055e393f | 4122 | for_each_pipe(dev_priv, pipe) { |
2c8ba29f | 4123 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
4124 | i915_handle_vblank(dev, pipe, pipe, iir)) |
4125 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); | |
a266c7d5 CW |
4126 | |
4127 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
4128 | blc_event = true; | |
4356d586 DV |
4129 | |
4130 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 4131 | i9xx_pipe_crc_irq_handler(dev, pipe); |
a266c7d5 | 4132 | |
1f7247c0 DV |
4133 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
4134 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
2d9d2b0b | 4135 | } |
a266c7d5 CW |
4136 | |
4137 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | |
4138 | intel_opregion_asle_intr(dev); | |
4139 | ||
515ac2bb DV |
4140 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
4141 | gmbus_irq_handler(dev); | |
4142 | ||
a266c7d5 CW |
4143 | /* With MSI, interrupts are only generated when iir |
4144 | * transitions from zero to nonzero. If another bit got | |
4145 | * set while we were handling the existing iir bits, then | |
4146 | * we would never get another interrupt. | |
4147 | * | |
4148 | * This is fine on non-MSI as well, as if we hit this path | |
4149 | * we avoid exiting the interrupt handler only to generate | |
4150 | * another one. | |
4151 | * | |
4152 | * Note that for MSI this could cause a stray interrupt report | |
4153 | * if an interrupt landed in the time between writing IIR and | |
4154 | * the posting read. This should be rare enough to never | |
4155 | * trigger the 99% of 100,000 interrupts test for disabling | |
4156 | * stray interrupts. | |
4157 | */ | |
4158 | iir = new_iir; | |
4159 | } | |
4160 | ||
4161 | return ret; | |
4162 | } | |
4163 | ||
4164 | static void i965_irq_uninstall(struct drm_device * dev) | |
4165 | { | |
2d1013dd | 4166 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4167 | int pipe; |
4168 | ||
4169 | if (!dev_priv) | |
4170 | return; | |
4171 | ||
adca4730 CW |
4172 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
4173 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
4174 | |
4175 | I915_WRITE(HWSTAM, 0xffffffff); | |
055e393f | 4176 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4177 | I915_WRITE(PIPESTAT(pipe), 0); |
4178 | I915_WRITE(IMR, 0xffffffff); | |
4179 | I915_WRITE(IER, 0x0); | |
4180 | ||
055e393f | 4181 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4182 | I915_WRITE(PIPESTAT(pipe), |
4183 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); | |
4184 | I915_WRITE(IIR, I915_READ(IIR)); | |
4185 | } | |
4186 | ||
4cb21832 | 4187 | static void intel_hpd_irq_reenable_work(struct work_struct *work) |
ac4c16c5 | 4188 | { |
6323751d ID |
4189 | struct drm_i915_private *dev_priv = |
4190 | container_of(work, typeof(*dev_priv), | |
4191 | hotplug_reenable_work.work); | |
ac4c16c5 EE |
4192 | struct drm_device *dev = dev_priv->dev; |
4193 | struct drm_mode_config *mode_config = &dev->mode_config; | |
ac4c16c5 EE |
4194 | int i; |
4195 | ||
6323751d ID |
4196 | intel_runtime_pm_get(dev_priv); |
4197 | ||
4cb21832 | 4198 | spin_lock_irq(&dev_priv->irq_lock); |
ac4c16c5 EE |
4199 | for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) { |
4200 | struct drm_connector *connector; | |
4201 | ||
4202 | if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED) | |
4203 | continue; | |
4204 | ||
4205 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
4206 | ||
4207 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
4208 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4209 | ||
4210 | if (intel_connector->encoder->hpd_pin == i) { | |
4211 | if (connector->polled != intel_connector->polled) | |
4212 | DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n", | |
c23cc417 | 4213 | connector->name); |
ac4c16c5 EE |
4214 | connector->polled = intel_connector->polled; |
4215 | if (!connector->polled) | |
4216 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
4217 | } | |
4218 | } | |
4219 | } | |
4220 | if (dev_priv->display.hpd_irq_setup) | |
4221 | dev_priv->display.hpd_irq_setup(dev); | |
4cb21832 | 4222 | spin_unlock_irq(&dev_priv->irq_lock); |
6323751d ID |
4223 | |
4224 | intel_runtime_pm_put(dev_priv); | |
ac4c16c5 EE |
4225 | } |
4226 | ||
fca52a55 DV |
4227 | /** |
4228 | * intel_irq_init - initializes irq support | |
4229 | * @dev_priv: i915 device instance | |
4230 | * | |
4231 | * This function initializes all the irq support including work items, timers | |
4232 | * and all the vtables. It does not setup the interrupt itself though. | |
4233 | */ | |
b963291c | 4234 | void intel_irq_init(struct drm_i915_private *dev_priv) |
f71d4af4 | 4235 | { |
b963291c | 4236 | struct drm_device *dev = dev_priv->dev; |
8b2e326d CW |
4237 | |
4238 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); | |
13cf5504 | 4239 | INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func); |
c6a828d3 | 4240 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
a4da4fa4 | 4241 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
8b2e326d | 4242 | |
a6706b45 | 4243 | /* Let's track the enabled rps events */ |
b963291c | 4244 | if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) |
6c65a587 | 4245 | /* WaGsvRC0ResidencyMethod:vlv */ |
6f4b12f8 | 4246 | dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED; |
31685c25 D |
4247 | else |
4248 | dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; | |
a6706b45 | 4249 | |
737b1506 CW |
4250 | INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work, |
4251 | i915_hangcheck_elapsed); | |
6323751d | 4252 | INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work, |
4cb21832 | 4253 | intel_hpd_irq_reenable_work); |
61bac78e | 4254 | |
97a19a24 | 4255 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); |
9ee32fea | 4256 | |
b963291c | 4257 | if (IS_GEN2(dev_priv)) { |
4cdb83ec VS |
4258 | dev->max_vblank_count = 0; |
4259 | dev->driver->get_vblank_counter = i8xx_get_vblank_counter; | |
b963291c | 4260 | } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { |
f71d4af4 JB |
4261 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
4262 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; | |
391f75e2 VS |
4263 | } else { |
4264 | dev->driver->get_vblank_counter = i915_get_vblank_counter; | |
4265 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
f71d4af4 JB |
4266 | } |
4267 | ||
21da2700 VS |
4268 | /* |
4269 | * Opt out of the vblank disable timer on everything except gen2. | |
4270 | * Gen2 doesn't have a hardware frame counter and so depends on | |
4271 | * vblank interrupts to produce sane vblank seuquence numbers. | |
4272 | */ | |
b963291c | 4273 | if (!IS_GEN2(dev_priv)) |
21da2700 VS |
4274 | dev->vblank_disable_immediate = true; |
4275 | ||
f3a5c3f6 DV |
4276 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; |
4277 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; | |
f71d4af4 | 4278 | |
b963291c | 4279 | if (IS_CHERRYVIEW(dev_priv)) { |
43f328d7 VS |
4280 | dev->driver->irq_handler = cherryview_irq_handler; |
4281 | dev->driver->irq_preinstall = cherryview_irq_preinstall; | |
4282 | dev->driver->irq_postinstall = cherryview_irq_postinstall; | |
4283 | dev->driver->irq_uninstall = cherryview_irq_uninstall; | |
4284 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4285 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
4286 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; | |
b963291c | 4287 | } else if (IS_VALLEYVIEW(dev_priv)) { |
7e231dbe JB |
4288 | dev->driver->irq_handler = valleyview_irq_handler; |
4289 | dev->driver->irq_preinstall = valleyview_irq_preinstall; | |
4290 | dev->driver->irq_postinstall = valleyview_irq_postinstall; | |
4291 | dev->driver->irq_uninstall = valleyview_irq_uninstall; | |
4292 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4293 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
fa00abe0 | 4294 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
b963291c | 4295 | } else if (INTEL_INFO(dev_priv)->gen >= 8) { |
abd58f01 | 4296 | dev->driver->irq_handler = gen8_irq_handler; |
723761b8 | 4297 | dev->driver->irq_preinstall = gen8_irq_reset; |
abd58f01 BW |
4298 | dev->driver->irq_postinstall = gen8_irq_postinstall; |
4299 | dev->driver->irq_uninstall = gen8_irq_uninstall; | |
4300 | dev->driver->enable_vblank = gen8_enable_vblank; | |
4301 | dev->driver->disable_vblank = gen8_disable_vblank; | |
4302 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; | |
f71d4af4 JB |
4303 | } else if (HAS_PCH_SPLIT(dev)) { |
4304 | dev->driver->irq_handler = ironlake_irq_handler; | |
723761b8 | 4305 | dev->driver->irq_preinstall = ironlake_irq_reset; |
f71d4af4 JB |
4306 | dev->driver->irq_postinstall = ironlake_irq_postinstall; |
4307 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
4308 | dev->driver->enable_vblank = ironlake_enable_vblank; | |
4309 | dev->driver->disable_vblank = ironlake_disable_vblank; | |
82a28bcf | 4310 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; |
f71d4af4 | 4311 | } else { |
b963291c | 4312 | if (INTEL_INFO(dev_priv)->gen == 2) { |
c2798b19 CW |
4313 | dev->driver->irq_preinstall = i8xx_irq_preinstall; |
4314 | dev->driver->irq_postinstall = i8xx_irq_postinstall; | |
4315 | dev->driver->irq_handler = i8xx_irq_handler; | |
4316 | dev->driver->irq_uninstall = i8xx_irq_uninstall; | |
b963291c | 4317 | } else if (INTEL_INFO(dev_priv)->gen == 3) { |
a266c7d5 CW |
4318 | dev->driver->irq_preinstall = i915_irq_preinstall; |
4319 | dev->driver->irq_postinstall = i915_irq_postinstall; | |
4320 | dev->driver->irq_uninstall = i915_irq_uninstall; | |
4321 | dev->driver->irq_handler = i915_irq_handler; | |
c2798b19 | 4322 | } else { |
a266c7d5 CW |
4323 | dev->driver->irq_preinstall = i965_irq_preinstall; |
4324 | dev->driver->irq_postinstall = i965_irq_postinstall; | |
4325 | dev->driver->irq_uninstall = i965_irq_uninstall; | |
4326 | dev->driver->irq_handler = i965_irq_handler; | |
c2798b19 | 4327 | } |
778eb334 VS |
4328 | if (I915_HAS_HOTPLUG(dev_priv)) |
4329 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; | |
f71d4af4 JB |
4330 | dev->driver->enable_vblank = i915_enable_vblank; |
4331 | dev->driver->disable_vblank = i915_disable_vblank; | |
4332 | } | |
4333 | } | |
20afbda2 | 4334 | |
fca52a55 DV |
4335 | /** |
4336 | * intel_hpd_init - initializes and enables hpd support | |
4337 | * @dev_priv: i915 device instance | |
4338 | * | |
4339 | * This function enables the hotplug support. It requires that interrupts have | |
4340 | * already been enabled with intel_irq_init_hw(). From this point on hotplug and | |
4341 | * poll request can run concurrently to other code, so locking rules must be | |
4342 | * obeyed. | |
4343 | * | |
4344 | * This is a separate step from interrupt enabling to simplify the locking rules | |
4345 | * in the driver load and resume code. | |
4346 | */ | |
b963291c | 4347 | void intel_hpd_init(struct drm_i915_private *dev_priv) |
20afbda2 | 4348 | { |
b963291c | 4349 | struct drm_device *dev = dev_priv->dev; |
821450c6 EE |
4350 | struct drm_mode_config *mode_config = &dev->mode_config; |
4351 | struct drm_connector *connector; | |
4352 | int i; | |
20afbda2 | 4353 | |
821450c6 EE |
4354 | for (i = 1; i < HPD_NUM_PINS; i++) { |
4355 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
4356 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
4357 | } | |
4358 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
4359 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4360 | connector->polled = intel_connector->polled; | |
0e32b39c DA |
4361 | if (connector->encoder && !connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE) |
4362 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
4363 | if (intel_connector->mst_port) | |
821450c6 EE |
4364 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
4365 | } | |
b5ea2d56 DV |
4366 | |
4367 | /* Interrupt setup is already guaranteed to be single-threaded, this is | |
4368 | * just to make the assert_spin_locked checks happy. */ | |
d6207435 | 4369 | spin_lock_irq(&dev_priv->irq_lock); |
20afbda2 DV |
4370 | if (dev_priv->display.hpd_irq_setup) |
4371 | dev_priv->display.hpd_irq_setup(dev); | |
d6207435 | 4372 | spin_unlock_irq(&dev_priv->irq_lock); |
20afbda2 | 4373 | } |
c67a470b | 4374 | |
fca52a55 DV |
4375 | /** |
4376 | * intel_irq_install - enables the hardware interrupt | |
4377 | * @dev_priv: i915 device instance | |
4378 | * | |
4379 | * This function enables the hardware interrupt handling, but leaves the hotplug | |
4380 | * handling still disabled. It is called after intel_irq_init(). | |
4381 | * | |
4382 | * In the driver load and resume code we need working interrupts in a few places | |
4383 | * but don't want to deal with the hassle of concurrent probe and hotplug | |
4384 | * workers. Hence the split into this two-stage approach. | |
4385 | */ | |
2aeb7d3a DV |
4386 | int intel_irq_install(struct drm_i915_private *dev_priv) |
4387 | { | |
4388 | /* | |
4389 | * We enable some interrupt sources in our postinstall hooks, so mark | |
4390 | * interrupts as enabled _before_ actually enabling them to avoid | |
4391 | * special cases in our ordering checks. | |
4392 | */ | |
4393 | dev_priv->pm.irqs_enabled = true; | |
4394 | ||
4395 | return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq); | |
4396 | } | |
4397 | ||
fca52a55 DV |
4398 | /** |
4399 | * intel_irq_uninstall - finilizes all irq handling | |
4400 | * @dev_priv: i915 device instance | |
4401 | * | |
4402 | * This stops interrupt and hotplug handling and unregisters and frees all | |
4403 | * resources acquired in the init functions. | |
4404 | */ | |
2aeb7d3a DV |
4405 | void intel_irq_uninstall(struct drm_i915_private *dev_priv) |
4406 | { | |
4407 | drm_irq_uninstall(dev_priv->dev); | |
4408 | intel_hpd_cancel_work(dev_priv); | |
4409 | dev_priv->pm.irqs_enabled = false; | |
4410 | } | |
4411 | ||
fca52a55 DV |
4412 | /** |
4413 | * intel_runtime_pm_disable_interrupts - runtime interrupt disabling | |
4414 | * @dev_priv: i915 device instance | |
4415 | * | |
4416 | * This function is used to disable interrupts at runtime, both in the runtime | |
4417 | * pm and the system suspend/resume code. | |
4418 | */ | |
b963291c | 4419 | void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv) |
c67a470b | 4420 | { |
b963291c | 4421 | dev_priv->dev->driver->irq_uninstall(dev_priv->dev); |
2aeb7d3a | 4422 | dev_priv->pm.irqs_enabled = false; |
2dd2a883 | 4423 | synchronize_irq(dev_priv->dev->irq); |
c67a470b PZ |
4424 | } |
4425 | ||
fca52a55 DV |
4426 | /** |
4427 | * intel_runtime_pm_enable_interrupts - runtime interrupt enabling | |
4428 | * @dev_priv: i915 device instance | |
4429 | * | |
4430 | * This function is used to enable interrupts at runtime, both in the runtime | |
4431 | * pm and the system suspend/resume code. | |
4432 | */ | |
b963291c | 4433 | void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv) |
c67a470b | 4434 | { |
2aeb7d3a | 4435 | dev_priv->pm.irqs_enabled = true; |
b963291c DV |
4436 | dev_priv->dev->driver->irq_preinstall(dev_priv->dev); |
4437 | dev_priv->dev->driver->irq_postinstall(dev_priv->dev); | |
c67a470b | 4438 | } |