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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
63eeaf38 | 31 | #include <linux/sysrq.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
b2c88f5b | 33 | #include <linux/circ_buf.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/i915_drm.h> | |
1da177e4 | 36 | #include "i915_drv.h" |
1c5d22f7 | 37 | #include "i915_trace.h" |
79e53945 | 38 | #include "intel_drv.h" |
1da177e4 | 39 | |
fca52a55 DV |
40 | /** |
41 | * DOC: interrupt handling | |
42 | * | |
43 | * These functions provide the basic support for enabling and disabling the | |
44 | * interrupt handling support. There's a lot more functionality in i915_irq.c | |
45 | * and related files, but that will be described in separate chapters. | |
46 | */ | |
47 | ||
e4ce95aa VS |
48 | static const u32 hpd_ilk[HPD_NUM_PINS] = { |
49 | [HPD_PORT_A] = DE_DP_A_HOTPLUG, | |
50 | }; | |
51 | ||
23bb4cb5 VS |
52 | static const u32 hpd_ivb[HPD_NUM_PINS] = { |
53 | [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB, | |
54 | }; | |
55 | ||
3a3b3c7d VS |
56 | static const u32 hpd_bdw[HPD_NUM_PINS] = { |
57 | [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG, | |
58 | }; | |
59 | ||
7c7e10db | 60 | static const u32 hpd_ibx[HPD_NUM_PINS] = { |
e5868a31 EE |
61 | [HPD_CRT] = SDE_CRT_HOTPLUG, |
62 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, | |
63 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG, | |
64 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG, | |
65 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG | |
66 | }; | |
67 | ||
7c7e10db | 68 | static const u32 hpd_cpt[HPD_NUM_PINS] = { |
e5868a31 | 69 | [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, |
73c352a2 | 70 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, |
e5868a31 EE |
71 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
72 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
73 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT | |
74 | }; | |
75 | ||
26951caf | 76 | static const u32 hpd_spt[HPD_NUM_PINS] = { |
74c0b395 | 77 | [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT, |
26951caf XZ |
78 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
79 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
80 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT, | |
81 | [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT | |
82 | }; | |
83 | ||
7c7e10db | 84 | static const u32 hpd_mask_i915[HPD_NUM_PINS] = { |
e5868a31 EE |
85 | [HPD_CRT] = CRT_HOTPLUG_INT_EN, |
86 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, | |
87 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, | |
88 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, | |
89 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, | |
90 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN | |
91 | }; | |
92 | ||
7c7e10db | 93 | static const u32 hpd_status_g4x[HPD_NUM_PINS] = { |
e5868a31 EE |
94 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
95 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, | |
96 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, | |
97 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
98 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
99 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
100 | }; | |
101 | ||
4bca26d0 | 102 | static const u32 hpd_status_i915[HPD_NUM_PINS] = { |
e5868a31 EE |
103 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
104 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, | |
105 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, | |
106 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
107 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
108 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
109 | }; | |
110 | ||
e0a20ad7 SS |
111 | /* BXT hpd list */ |
112 | static const u32 hpd_bxt[HPD_NUM_PINS] = { | |
7f3561be | 113 | [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA, |
e0a20ad7 SS |
114 | [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB, |
115 | [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC | |
116 | }; | |
117 | ||
5c502442 | 118 | /* IIR can theoretically queue up two events. Be paranoid. */ |
f86f3fb0 | 119 | #define GEN8_IRQ_RESET_NDX(type, which) do { \ |
5c502442 PZ |
120 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ |
121 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
122 | I915_WRITE(GEN8_##type##_IER(which), 0); \ | |
123 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
124 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
125 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
126 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
127 | } while (0) | |
128 | ||
f86f3fb0 | 129 | #define GEN5_IRQ_RESET(type) do { \ |
a9d356a6 | 130 | I915_WRITE(type##IMR, 0xffffffff); \ |
5c502442 | 131 | POSTING_READ(type##IMR); \ |
a9d356a6 | 132 | I915_WRITE(type##IER, 0); \ |
5c502442 PZ |
133 | I915_WRITE(type##IIR, 0xffffffff); \ |
134 | POSTING_READ(type##IIR); \ | |
135 | I915_WRITE(type##IIR, 0xffffffff); \ | |
136 | POSTING_READ(type##IIR); \ | |
a9d356a6 PZ |
137 | } while (0) |
138 | ||
337ba017 PZ |
139 | /* |
140 | * We should clear IMR at preinstall/uninstall, and just check at postinstall. | |
141 | */ | |
f0f59a00 VS |
142 | static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv, |
143 | i915_reg_t reg) | |
b51a2842 VS |
144 | { |
145 | u32 val = I915_READ(reg); | |
146 | ||
147 | if (val == 0) | |
148 | return; | |
149 | ||
150 | WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", | |
f0f59a00 | 151 | i915_mmio_reg_offset(reg), val); |
b51a2842 VS |
152 | I915_WRITE(reg, 0xffffffff); |
153 | POSTING_READ(reg); | |
154 | I915_WRITE(reg, 0xffffffff); | |
155 | POSTING_READ(reg); | |
156 | } | |
337ba017 | 157 | |
35079899 | 158 | #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \ |
b51a2842 | 159 | gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \ |
35079899 | 160 | I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \ |
7d1bd539 VS |
161 | I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \ |
162 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
35079899 PZ |
163 | } while (0) |
164 | ||
165 | #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \ | |
b51a2842 | 166 | gen5_assert_iir_is_zero(dev_priv, type##IIR); \ |
35079899 | 167 | I915_WRITE(type##IER, (ier_val)); \ |
7d1bd539 VS |
168 | I915_WRITE(type##IMR, (imr_val)); \ |
169 | POSTING_READ(type##IMR); \ | |
35079899 PZ |
170 | } while (0) |
171 | ||
c9a9a268 | 172 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir); |
26705e20 | 173 | static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir); |
c9a9a268 | 174 | |
0706f17c EE |
175 | /* For display hotplug interrupt */ |
176 | static inline void | |
177 | i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv, | |
178 | uint32_t mask, | |
179 | uint32_t bits) | |
180 | { | |
181 | uint32_t val; | |
182 | ||
183 | assert_spin_locked(&dev_priv->irq_lock); | |
184 | WARN_ON(bits & ~mask); | |
185 | ||
186 | val = I915_READ(PORT_HOTPLUG_EN); | |
187 | val &= ~mask; | |
188 | val |= bits; | |
189 | I915_WRITE(PORT_HOTPLUG_EN, val); | |
190 | } | |
191 | ||
192 | /** | |
193 | * i915_hotplug_interrupt_update - update hotplug interrupt enable | |
194 | * @dev_priv: driver private | |
195 | * @mask: bits to update | |
196 | * @bits: bits to enable | |
197 | * NOTE: the HPD enable bits are modified both inside and outside | |
198 | * of an interrupt context. To avoid that read-modify-write cycles | |
199 | * interfer, these bits are protected by a spinlock. Since this | |
200 | * function is usually not called from a context where the lock is | |
201 | * held already, this function acquires the lock itself. A non-locking | |
202 | * version is also available. | |
203 | */ | |
204 | void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, | |
205 | uint32_t mask, | |
206 | uint32_t bits) | |
207 | { | |
208 | spin_lock_irq(&dev_priv->irq_lock); | |
209 | i915_hotplug_interrupt_update_locked(dev_priv, mask, bits); | |
210 | spin_unlock_irq(&dev_priv->irq_lock); | |
211 | } | |
212 | ||
d9dc34f1 VS |
213 | /** |
214 | * ilk_update_display_irq - update DEIMR | |
215 | * @dev_priv: driver private | |
216 | * @interrupt_mask: mask of interrupt bits to update | |
217 | * @enabled_irq_mask: mask of interrupt bits to enable | |
218 | */ | |
fbdedaea VS |
219 | void ilk_update_display_irq(struct drm_i915_private *dev_priv, |
220 | uint32_t interrupt_mask, | |
221 | uint32_t enabled_irq_mask) | |
036a4a7d | 222 | { |
d9dc34f1 VS |
223 | uint32_t new_val; |
224 | ||
4bc9d430 DV |
225 | assert_spin_locked(&dev_priv->irq_lock); |
226 | ||
d9dc34f1 VS |
227 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
228 | ||
9df7575f | 229 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 230 | return; |
c67a470b | 231 | |
d9dc34f1 VS |
232 | new_val = dev_priv->irq_mask; |
233 | new_val &= ~interrupt_mask; | |
234 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
235 | ||
236 | if (new_val != dev_priv->irq_mask) { | |
237 | dev_priv->irq_mask = new_val; | |
1ec14ad3 | 238 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
3143a2bf | 239 | POSTING_READ(DEIMR); |
036a4a7d ZW |
240 | } |
241 | } | |
242 | ||
43eaea13 PZ |
243 | /** |
244 | * ilk_update_gt_irq - update GTIMR | |
245 | * @dev_priv: driver private | |
246 | * @interrupt_mask: mask of interrupt bits to update | |
247 | * @enabled_irq_mask: mask of interrupt bits to enable | |
248 | */ | |
249 | static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, | |
250 | uint32_t interrupt_mask, | |
251 | uint32_t enabled_irq_mask) | |
252 | { | |
253 | assert_spin_locked(&dev_priv->irq_lock); | |
254 | ||
15a17aae DV |
255 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
256 | ||
9df7575f | 257 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 258 | return; |
c67a470b | 259 | |
43eaea13 PZ |
260 | dev_priv->gt_irq_mask &= ~interrupt_mask; |
261 | dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); | |
262 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
43eaea13 PZ |
263 | } |
264 | ||
480c8033 | 265 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
43eaea13 PZ |
266 | { |
267 | ilk_update_gt_irq(dev_priv, mask, mask); | |
31bb59cc | 268 | POSTING_READ_FW(GTIMR); |
43eaea13 PZ |
269 | } |
270 | ||
480c8033 | 271 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
43eaea13 PZ |
272 | { |
273 | ilk_update_gt_irq(dev_priv, mask, 0); | |
274 | } | |
275 | ||
f0f59a00 | 276 | static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv) |
b900b949 ID |
277 | { |
278 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; | |
279 | } | |
280 | ||
f0f59a00 | 281 | static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv) |
a72fbc3a ID |
282 | { |
283 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR; | |
284 | } | |
285 | ||
f0f59a00 | 286 | static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv) |
b900b949 ID |
287 | { |
288 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER; | |
289 | } | |
290 | ||
edbfdb45 | 291 | /** |
81fd874e VS |
292 | * snb_update_pm_irq - update GEN6_PMIMR |
293 | * @dev_priv: driver private | |
294 | * @interrupt_mask: mask of interrupt bits to update | |
295 | * @enabled_irq_mask: mask of interrupt bits to enable | |
296 | */ | |
edbfdb45 PZ |
297 | static void snb_update_pm_irq(struct drm_i915_private *dev_priv, |
298 | uint32_t interrupt_mask, | |
299 | uint32_t enabled_irq_mask) | |
300 | { | |
605cd25b | 301 | uint32_t new_val; |
edbfdb45 | 302 | |
15a17aae DV |
303 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
304 | ||
edbfdb45 PZ |
305 | assert_spin_locked(&dev_priv->irq_lock); |
306 | ||
f4e9af4f | 307 | new_val = dev_priv->pm_imr; |
f52ecbcf PZ |
308 | new_val &= ~interrupt_mask; |
309 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
310 | ||
f4e9af4f AG |
311 | if (new_val != dev_priv->pm_imr) { |
312 | dev_priv->pm_imr = new_val; | |
313 | I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_imr); | |
a72fbc3a | 314 | POSTING_READ(gen6_pm_imr(dev_priv)); |
f52ecbcf | 315 | } |
edbfdb45 PZ |
316 | } |
317 | ||
f4e9af4f | 318 | void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask) |
edbfdb45 | 319 | { |
9939fba2 ID |
320 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
321 | return; | |
322 | ||
edbfdb45 PZ |
323 | snb_update_pm_irq(dev_priv, mask, mask); |
324 | } | |
325 | ||
f4e9af4f | 326 | static void __gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask) |
edbfdb45 PZ |
327 | { |
328 | snb_update_pm_irq(dev_priv, mask, 0); | |
329 | } | |
330 | ||
f4e9af4f | 331 | void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask) |
9939fba2 ID |
332 | { |
333 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) | |
334 | return; | |
335 | ||
f4e9af4f | 336 | __gen6_mask_pm_irq(dev_priv, mask); |
9939fba2 ID |
337 | } |
338 | ||
f4e9af4f | 339 | void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask) |
3cc134e3 | 340 | { |
f0f59a00 | 341 | i915_reg_t reg = gen6_pm_iir(dev_priv); |
3cc134e3 | 342 | |
f4e9af4f AG |
343 | assert_spin_locked(&dev_priv->irq_lock); |
344 | ||
345 | I915_WRITE(reg, reset_mask); | |
346 | I915_WRITE(reg, reset_mask); | |
3cc134e3 | 347 | POSTING_READ(reg); |
f4e9af4f AG |
348 | } |
349 | ||
350 | void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask) | |
351 | { | |
352 | assert_spin_locked(&dev_priv->irq_lock); | |
353 | ||
354 | dev_priv->pm_ier |= enable_mask; | |
355 | I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier); | |
356 | gen6_unmask_pm_irq(dev_priv, enable_mask); | |
357 | /* unmask_pm_irq provides an implicit barrier (POSTING_READ) */ | |
358 | } | |
359 | ||
360 | void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask) | |
361 | { | |
362 | assert_spin_locked(&dev_priv->irq_lock); | |
363 | ||
364 | dev_priv->pm_ier &= ~disable_mask; | |
365 | __gen6_mask_pm_irq(dev_priv, disable_mask); | |
366 | I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier); | |
367 | /* though a barrier is missing here, but don't really need a one */ | |
368 | } | |
369 | ||
370 | void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv) | |
371 | { | |
372 | spin_lock_irq(&dev_priv->irq_lock); | |
373 | gen6_reset_pm_iir(dev_priv, dev_priv->pm_rps_events); | |
096fad9e | 374 | dev_priv->rps.pm_iir = 0; |
3cc134e3 ID |
375 | spin_unlock_irq(&dev_priv->irq_lock); |
376 | } | |
377 | ||
91d14251 | 378 | void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv) |
b900b949 | 379 | { |
f2a91d1a CW |
380 | if (READ_ONCE(dev_priv->rps.interrupts_enabled)) |
381 | return; | |
382 | ||
b900b949 | 383 | spin_lock_irq(&dev_priv->irq_lock); |
c33d247d CW |
384 | WARN_ON_ONCE(dev_priv->rps.pm_iir); |
385 | WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events); | |
d4d70aa5 | 386 | dev_priv->rps.interrupts_enabled = true; |
b900b949 | 387 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
78e68d36 | 388 | |
b900b949 ID |
389 | spin_unlock_irq(&dev_priv->irq_lock); |
390 | } | |
391 | ||
59d02a1f ID |
392 | u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask) |
393 | { | |
1800ad25 | 394 | return (mask & ~dev_priv->rps.pm_intr_keep); |
59d02a1f ID |
395 | } |
396 | ||
91d14251 | 397 | void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv) |
b900b949 | 398 | { |
f2a91d1a CW |
399 | if (!READ_ONCE(dev_priv->rps.interrupts_enabled)) |
400 | return; | |
401 | ||
d4d70aa5 ID |
402 | spin_lock_irq(&dev_priv->irq_lock); |
403 | dev_priv->rps.interrupts_enabled = false; | |
9939fba2 | 404 | |
b20e3cfe | 405 | I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u)); |
9939fba2 | 406 | |
f4e9af4f | 407 | gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
58072ccb ID |
408 | |
409 | spin_unlock_irq(&dev_priv->irq_lock); | |
91c8a326 | 410 | synchronize_irq(dev_priv->drm.irq); |
c33d247d CW |
411 | |
412 | /* Now that we will not be generating any more work, flush any | |
413 | * outsanding tasks. As we are called on the RPS idle path, | |
414 | * we will reset the GPU to minimum frequencies, so the current | |
415 | * state of the worker can be discarded. | |
416 | */ | |
417 | cancel_work_sync(&dev_priv->rps.work); | |
418 | gen6_reset_rps_interrupts(dev_priv); | |
b900b949 ID |
419 | } |
420 | ||
26705e20 SAK |
421 | void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv) |
422 | { | |
423 | spin_lock_irq(&dev_priv->irq_lock); | |
424 | gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events); | |
425 | spin_unlock_irq(&dev_priv->irq_lock); | |
426 | } | |
427 | ||
428 | void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv) | |
429 | { | |
430 | spin_lock_irq(&dev_priv->irq_lock); | |
431 | if (!dev_priv->guc.interrupts_enabled) { | |
432 | WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & | |
433 | dev_priv->pm_guc_events); | |
434 | dev_priv->guc.interrupts_enabled = true; | |
435 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events); | |
436 | } | |
437 | spin_unlock_irq(&dev_priv->irq_lock); | |
438 | } | |
439 | ||
440 | void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv) | |
441 | { | |
442 | spin_lock_irq(&dev_priv->irq_lock); | |
443 | dev_priv->guc.interrupts_enabled = false; | |
444 | ||
445 | gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events); | |
446 | ||
447 | spin_unlock_irq(&dev_priv->irq_lock); | |
448 | synchronize_irq(dev_priv->drm.irq); | |
449 | ||
450 | gen9_reset_guc_interrupts(dev_priv); | |
451 | } | |
452 | ||
3a3b3c7d | 453 | /** |
81fd874e VS |
454 | * bdw_update_port_irq - update DE port interrupt |
455 | * @dev_priv: driver private | |
456 | * @interrupt_mask: mask of interrupt bits to update | |
457 | * @enabled_irq_mask: mask of interrupt bits to enable | |
458 | */ | |
3a3b3c7d VS |
459 | static void bdw_update_port_irq(struct drm_i915_private *dev_priv, |
460 | uint32_t interrupt_mask, | |
461 | uint32_t enabled_irq_mask) | |
462 | { | |
463 | uint32_t new_val; | |
464 | uint32_t old_val; | |
465 | ||
466 | assert_spin_locked(&dev_priv->irq_lock); | |
467 | ||
468 | WARN_ON(enabled_irq_mask & ~interrupt_mask); | |
469 | ||
470 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) | |
471 | return; | |
472 | ||
473 | old_val = I915_READ(GEN8_DE_PORT_IMR); | |
474 | ||
475 | new_val = old_val; | |
476 | new_val &= ~interrupt_mask; | |
477 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
478 | ||
479 | if (new_val != old_val) { | |
480 | I915_WRITE(GEN8_DE_PORT_IMR, new_val); | |
481 | POSTING_READ(GEN8_DE_PORT_IMR); | |
482 | } | |
483 | } | |
484 | ||
013d3752 VS |
485 | /** |
486 | * bdw_update_pipe_irq - update DE pipe interrupt | |
487 | * @dev_priv: driver private | |
488 | * @pipe: pipe whose interrupt to update | |
489 | * @interrupt_mask: mask of interrupt bits to update | |
490 | * @enabled_irq_mask: mask of interrupt bits to enable | |
491 | */ | |
492 | void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, | |
493 | enum pipe pipe, | |
494 | uint32_t interrupt_mask, | |
495 | uint32_t enabled_irq_mask) | |
496 | { | |
497 | uint32_t new_val; | |
498 | ||
499 | assert_spin_locked(&dev_priv->irq_lock); | |
500 | ||
501 | WARN_ON(enabled_irq_mask & ~interrupt_mask); | |
502 | ||
503 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) | |
504 | return; | |
505 | ||
506 | new_val = dev_priv->de_irq_mask[pipe]; | |
507 | new_val &= ~interrupt_mask; | |
508 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
509 | ||
510 | if (new_val != dev_priv->de_irq_mask[pipe]) { | |
511 | dev_priv->de_irq_mask[pipe] = new_val; | |
512 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
513 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
514 | } | |
515 | } | |
516 | ||
fee884ed DV |
517 | /** |
518 | * ibx_display_interrupt_update - update SDEIMR | |
519 | * @dev_priv: driver private | |
520 | * @interrupt_mask: mask of interrupt bits to update | |
521 | * @enabled_irq_mask: mask of interrupt bits to enable | |
522 | */ | |
47339cd9 DV |
523 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
524 | uint32_t interrupt_mask, | |
525 | uint32_t enabled_irq_mask) | |
fee884ed DV |
526 | { |
527 | uint32_t sdeimr = I915_READ(SDEIMR); | |
528 | sdeimr &= ~interrupt_mask; | |
529 | sdeimr |= (~enabled_irq_mask & interrupt_mask); | |
530 | ||
15a17aae DV |
531 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
532 | ||
fee884ed DV |
533 | assert_spin_locked(&dev_priv->irq_lock); |
534 | ||
9df7575f | 535 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 536 | return; |
c67a470b | 537 | |
fee884ed DV |
538 | I915_WRITE(SDEIMR, sdeimr); |
539 | POSTING_READ(SDEIMR); | |
540 | } | |
8664281b | 541 | |
b5ea642a | 542 | static void |
755e9019 ID |
543 | __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
544 | u32 enable_mask, u32 status_mask) | |
7c463586 | 545 | { |
f0f59a00 | 546 | i915_reg_t reg = PIPESTAT(pipe); |
755e9019 | 547 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 548 | |
b79480ba | 549 | assert_spin_locked(&dev_priv->irq_lock); |
d518ce50 | 550 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
b79480ba | 551 | |
04feced9 VS |
552 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
553 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
554 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
555 | pipe_name(pipe), enable_mask, status_mask)) | |
755e9019 ID |
556 | return; |
557 | ||
558 | if ((pipestat & enable_mask) == enable_mask) | |
46c06a30 VS |
559 | return; |
560 | ||
91d181dd ID |
561 | dev_priv->pipestat_irq_mask[pipe] |= status_mask; |
562 | ||
46c06a30 | 563 | /* Enable the interrupt, clear any pending status */ |
755e9019 | 564 | pipestat |= enable_mask | status_mask; |
46c06a30 VS |
565 | I915_WRITE(reg, pipestat); |
566 | POSTING_READ(reg); | |
7c463586 KP |
567 | } |
568 | ||
b5ea642a | 569 | static void |
755e9019 ID |
570 | __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
571 | u32 enable_mask, u32 status_mask) | |
7c463586 | 572 | { |
f0f59a00 | 573 | i915_reg_t reg = PIPESTAT(pipe); |
755e9019 | 574 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 575 | |
b79480ba | 576 | assert_spin_locked(&dev_priv->irq_lock); |
d518ce50 | 577 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
b79480ba | 578 | |
04feced9 VS |
579 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
580 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
581 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
582 | pipe_name(pipe), enable_mask, status_mask)) | |
46c06a30 VS |
583 | return; |
584 | ||
755e9019 ID |
585 | if ((pipestat & enable_mask) == 0) |
586 | return; | |
587 | ||
91d181dd ID |
588 | dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; |
589 | ||
755e9019 | 590 | pipestat &= ~enable_mask; |
46c06a30 VS |
591 | I915_WRITE(reg, pipestat); |
592 | POSTING_READ(reg); | |
7c463586 KP |
593 | } |
594 | ||
10c59c51 ID |
595 | static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask) |
596 | { | |
597 | u32 enable_mask = status_mask << 16; | |
598 | ||
599 | /* | |
724a6905 VS |
600 | * On pipe A we don't support the PSR interrupt yet, |
601 | * on pipe B and C the same bit MBZ. | |
10c59c51 ID |
602 | */ |
603 | if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV)) | |
604 | return 0; | |
724a6905 VS |
605 | /* |
606 | * On pipe B and C we don't support the PSR interrupt yet, on pipe | |
607 | * A the same bit is for perf counters which we don't use either. | |
608 | */ | |
609 | if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV)) | |
610 | return 0; | |
10c59c51 ID |
611 | |
612 | enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | | |
613 | SPRITE0_FLIP_DONE_INT_EN_VLV | | |
614 | SPRITE1_FLIP_DONE_INT_EN_VLV); | |
615 | if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV) | |
616 | enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV; | |
617 | if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV) | |
618 | enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; | |
619 | ||
620 | return enable_mask; | |
621 | } | |
622 | ||
755e9019 ID |
623 | void |
624 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
625 | u32 status_mask) | |
626 | { | |
627 | u32 enable_mask; | |
628 | ||
666a4537 | 629 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
91c8a326 | 630 | enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm, |
10c59c51 ID |
631 | status_mask); |
632 | else | |
633 | enable_mask = status_mask << 16; | |
755e9019 ID |
634 | __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
635 | } | |
636 | ||
637 | void | |
638 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
639 | u32 status_mask) | |
640 | { | |
641 | u32 enable_mask; | |
642 | ||
666a4537 | 643 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
91c8a326 | 644 | enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm, |
10c59c51 ID |
645 | status_mask); |
646 | else | |
647 | enable_mask = status_mask << 16; | |
755e9019 ID |
648 | __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
649 | } | |
650 | ||
01c66889 | 651 | /** |
f49e38dd | 652 | * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion |
14bb2c11 | 653 | * @dev_priv: i915 device private |
01c66889 | 654 | */ |
91d14251 | 655 | static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv) |
01c66889 | 656 | { |
91d14251 | 657 | if (!dev_priv->opregion.asle || !IS_MOBILE(dev_priv)) |
f49e38dd JN |
658 | return; |
659 | ||
13321786 | 660 | spin_lock_irq(&dev_priv->irq_lock); |
01c66889 | 661 | |
755e9019 | 662 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); |
91d14251 | 663 | if (INTEL_GEN(dev_priv) >= 4) |
3b6c42e8 | 664 | i915_enable_pipestat(dev_priv, PIPE_A, |
755e9019 | 665 | PIPE_LEGACY_BLC_EVENT_STATUS); |
1ec14ad3 | 666 | |
13321786 | 667 | spin_unlock_irq(&dev_priv->irq_lock); |
01c66889 ZY |
668 | } |
669 | ||
f75f3746 VS |
670 | /* |
671 | * This timing diagram depicts the video signal in and | |
672 | * around the vertical blanking period. | |
673 | * | |
674 | * Assumptions about the fictitious mode used in this example: | |
675 | * vblank_start >= 3 | |
676 | * vsync_start = vblank_start + 1 | |
677 | * vsync_end = vblank_start + 2 | |
678 | * vtotal = vblank_start + 3 | |
679 | * | |
680 | * start of vblank: | |
681 | * latch double buffered registers | |
682 | * increment frame counter (ctg+) | |
683 | * generate start of vblank interrupt (gen4+) | |
684 | * | | |
685 | * | frame start: | |
686 | * | generate frame start interrupt (aka. vblank interrupt) (gmch) | |
687 | * | may be shifted forward 1-3 extra lines via PIPECONF | |
688 | * | | | |
689 | * | | start of vsync: | |
690 | * | | generate vsync interrupt | |
691 | * | | | | |
692 | * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx | |
693 | * . \hs/ . \hs/ \hs/ \hs/ . \hs/ | |
694 | * ----va---> <-----------------vb--------------------> <--------va------------- | |
695 | * | | <----vs-----> | | |
696 | * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2) | |
697 | * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+) | |
698 | * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi) | |
699 | * | | | | |
700 | * last visible pixel first visible pixel | |
701 | * | increment frame counter (gen3/4) | |
702 | * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4) | |
703 | * | |
704 | * x = horizontal active | |
705 | * _ = horizontal blanking | |
706 | * hs = horizontal sync | |
707 | * va = vertical active | |
708 | * vb = vertical blanking | |
709 | * vs = vertical sync | |
710 | * vbs = vblank_start (number) | |
711 | * | |
712 | * Summary: | |
713 | * - most events happen at the start of horizontal sync | |
714 | * - frame start happens at the start of horizontal blank, 1-4 lines | |
715 | * (depending on PIPECONF settings) after the start of vblank | |
716 | * - gen3/4 pixel and frame counter are synchronized with the start | |
717 | * of horizontal active on the first line of vertical active | |
718 | */ | |
719 | ||
42f52ef8 KP |
720 | /* Called from drm generic code, passed a 'crtc', which |
721 | * we use as a pipe index | |
722 | */ | |
88e72717 | 723 | static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe) |
0a3e67a4 | 724 | { |
fac5e23e | 725 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 726 | i915_reg_t high_frame, low_frame; |
0b2a8e09 | 727 | u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal; |
98187836 VS |
728 | struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv, |
729 | pipe); | |
fc467a22 | 730 | const struct drm_display_mode *mode = &intel_crtc->base.hwmode; |
0a3e67a4 | 731 | |
f3a5c3f6 DV |
732 | htotal = mode->crtc_htotal; |
733 | hsync_start = mode->crtc_hsync_start; | |
734 | vbl_start = mode->crtc_vblank_start; | |
735 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
736 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
391f75e2 | 737 | |
0b2a8e09 VS |
738 | /* Convert to pixel count */ |
739 | vbl_start *= htotal; | |
740 | ||
741 | /* Start of vblank event occurs at start of hsync */ | |
742 | vbl_start -= htotal - hsync_start; | |
743 | ||
9db4a9c7 JB |
744 | high_frame = PIPEFRAME(pipe); |
745 | low_frame = PIPEFRAMEPIXEL(pipe); | |
5eddb70b | 746 | |
0a3e67a4 JB |
747 | /* |
748 | * High & low register fields aren't synchronized, so make sure | |
749 | * we get a low value that's stable across two reads of the high | |
750 | * register. | |
751 | */ | |
752 | do { | |
5eddb70b | 753 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
391f75e2 | 754 | low = I915_READ(low_frame); |
5eddb70b | 755 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
0a3e67a4 JB |
756 | } while (high1 != high2); |
757 | ||
5eddb70b | 758 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
391f75e2 | 759 | pixel = low & PIPE_PIXEL_MASK; |
5eddb70b | 760 | low >>= PIPE_FRAME_LOW_SHIFT; |
391f75e2 VS |
761 | |
762 | /* | |
763 | * The frame counter increments at beginning of active. | |
764 | * Cook up a vblank counter by also checking the pixel | |
765 | * counter against vblank start. | |
766 | */ | |
edc08d0a | 767 | return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; |
0a3e67a4 JB |
768 | } |
769 | ||
974e59ba | 770 | static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe) |
9880b7a5 | 771 | { |
fac5e23e | 772 | struct drm_i915_private *dev_priv = to_i915(dev); |
9880b7a5 | 773 | |
649636ef | 774 | return I915_READ(PIPE_FRMCOUNT_G4X(pipe)); |
9880b7a5 JB |
775 | } |
776 | ||
75aa3f63 | 777 | /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */ |
a225f079 VS |
778 | static int __intel_get_crtc_scanline(struct intel_crtc *crtc) |
779 | { | |
780 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 781 | struct drm_i915_private *dev_priv = to_i915(dev); |
fc467a22 | 782 | const struct drm_display_mode *mode = &crtc->base.hwmode; |
a225f079 | 783 | enum pipe pipe = crtc->pipe; |
80715b2f | 784 | int position, vtotal; |
a225f079 | 785 | |
80715b2f | 786 | vtotal = mode->crtc_vtotal; |
a225f079 VS |
787 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
788 | vtotal /= 2; | |
789 | ||
91d14251 | 790 | if (IS_GEN2(dev_priv)) |
75aa3f63 | 791 | position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; |
a225f079 | 792 | else |
75aa3f63 | 793 | position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; |
a225f079 | 794 | |
41b578fb JB |
795 | /* |
796 | * On HSW, the DSL reg (0x70000) appears to return 0 if we | |
797 | * read it just before the start of vblank. So try it again | |
798 | * so we don't accidentally end up spanning a vblank frame | |
799 | * increment, causing the pipe_update_end() code to squak at us. | |
800 | * | |
801 | * The nature of this problem means we can't simply check the ISR | |
802 | * bit and return the vblank start value; nor can we use the scanline | |
803 | * debug register in the transcoder as it appears to have the same | |
804 | * problem. We may need to extend this to include other platforms, | |
805 | * but so far testing only shows the problem on HSW. | |
806 | */ | |
91d14251 | 807 | if (HAS_DDI(dev_priv) && !position) { |
41b578fb JB |
808 | int i, temp; |
809 | ||
810 | for (i = 0; i < 100; i++) { | |
811 | udelay(1); | |
812 | temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & | |
813 | DSL_LINEMASK_GEN3; | |
814 | if (temp != position) { | |
815 | position = temp; | |
816 | break; | |
817 | } | |
818 | } | |
819 | } | |
820 | ||
a225f079 | 821 | /* |
80715b2f VS |
822 | * See update_scanline_offset() for the details on the |
823 | * scanline_offset adjustment. | |
a225f079 | 824 | */ |
80715b2f | 825 | return (position + crtc->scanline_offset) % vtotal; |
a225f079 VS |
826 | } |
827 | ||
88e72717 | 828 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, |
abca9e45 | 829 | unsigned int flags, int *vpos, int *hpos, |
3bb403bf VS |
830 | ktime_t *stime, ktime_t *etime, |
831 | const struct drm_display_mode *mode) | |
0af7e4df | 832 | { |
fac5e23e | 833 | struct drm_i915_private *dev_priv = to_i915(dev); |
98187836 VS |
834 | struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv, |
835 | pipe); | |
3aa18df8 | 836 | int position; |
78e8fc6b | 837 | int vbl_start, vbl_end, hsync_start, htotal, vtotal; |
0af7e4df MK |
838 | bool in_vbl = true; |
839 | int ret = 0; | |
ad3543ed | 840 | unsigned long irqflags; |
0af7e4df | 841 | |
fc467a22 | 842 | if (WARN_ON(!mode->crtc_clock)) { |
0af7e4df | 843 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
9db4a9c7 | 844 | "pipe %c\n", pipe_name(pipe)); |
0af7e4df MK |
845 | return 0; |
846 | } | |
847 | ||
c2baf4b7 | 848 | htotal = mode->crtc_htotal; |
78e8fc6b | 849 | hsync_start = mode->crtc_hsync_start; |
c2baf4b7 VS |
850 | vtotal = mode->crtc_vtotal; |
851 | vbl_start = mode->crtc_vblank_start; | |
852 | vbl_end = mode->crtc_vblank_end; | |
0af7e4df | 853 | |
d31faf65 VS |
854 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
855 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
856 | vbl_end /= 2; | |
857 | vtotal /= 2; | |
858 | } | |
859 | ||
c2baf4b7 VS |
860 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; |
861 | ||
ad3543ed MK |
862 | /* |
863 | * Lock uncore.lock, as we will do multiple timing critical raw | |
864 | * register reads, potentially with preemption disabled, so the | |
865 | * following code must not block on uncore.lock. | |
866 | */ | |
867 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
78e8fc6b | 868 | |
ad3543ed MK |
869 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ |
870 | ||
871 | /* Get optional system timestamp before query. */ | |
872 | if (stime) | |
873 | *stime = ktime_get(); | |
874 | ||
91d14251 | 875 | if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { |
0af7e4df MK |
876 | /* No obvious pixelcount register. Only query vertical |
877 | * scanout position from Display scan line register. | |
878 | */ | |
a225f079 | 879 | position = __intel_get_crtc_scanline(intel_crtc); |
0af7e4df MK |
880 | } else { |
881 | /* Have access to pixelcount since start of frame. | |
882 | * We can split this into vertical and horizontal | |
883 | * scanout position. | |
884 | */ | |
75aa3f63 | 885 | position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; |
0af7e4df | 886 | |
3aa18df8 VS |
887 | /* convert to pixel counts */ |
888 | vbl_start *= htotal; | |
889 | vbl_end *= htotal; | |
890 | vtotal *= htotal; | |
78e8fc6b | 891 | |
7e78f1cb VS |
892 | /* |
893 | * In interlaced modes, the pixel counter counts all pixels, | |
894 | * so one field will have htotal more pixels. In order to avoid | |
895 | * the reported position from jumping backwards when the pixel | |
896 | * counter is beyond the length of the shorter field, just | |
897 | * clamp the position the length of the shorter field. This | |
898 | * matches how the scanline counter based position works since | |
899 | * the scanline counter doesn't count the two half lines. | |
900 | */ | |
901 | if (position >= vtotal) | |
902 | position = vtotal - 1; | |
903 | ||
78e8fc6b VS |
904 | /* |
905 | * Start of vblank interrupt is triggered at start of hsync, | |
906 | * just prior to the first active line of vblank. However we | |
907 | * consider lines to start at the leading edge of horizontal | |
908 | * active. So, should we get here before we've crossed into | |
909 | * the horizontal active of the first line in vblank, we would | |
910 | * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that, | |
911 | * always add htotal-hsync_start to the current pixel position. | |
912 | */ | |
913 | position = (position + htotal - hsync_start) % vtotal; | |
0af7e4df MK |
914 | } |
915 | ||
ad3543ed MK |
916 | /* Get optional system timestamp after query. */ |
917 | if (etime) | |
918 | *etime = ktime_get(); | |
919 | ||
920 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ | |
921 | ||
922 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
923 | ||
3aa18df8 VS |
924 | in_vbl = position >= vbl_start && position < vbl_end; |
925 | ||
926 | /* | |
927 | * While in vblank, position will be negative | |
928 | * counting up towards 0 at vbl_end. And outside | |
929 | * vblank, position will be positive counting | |
930 | * up since vbl_end. | |
931 | */ | |
932 | if (position >= vbl_start) | |
933 | position -= vbl_end; | |
934 | else | |
935 | position += vtotal - vbl_end; | |
0af7e4df | 936 | |
91d14251 | 937 | if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { |
3aa18df8 VS |
938 | *vpos = position; |
939 | *hpos = 0; | |
940 | } else { | |
941 | *vpos = position / htotal; | |
942 | *hpos = position - (*vpos * htotal); | |
943 | } | |
0af7e4df | 944 | |
0af7e4df MK |
945 | /* In vblank? */ |
946 | if (in_vbl) | |
3d3cbd84 | 947 | ret |= DRM_SCANOUTPOS_IN_VBLANK; |
0af7e4df MK |
948 | |
949 | return ret; | |
950 | } | |
951 | ||
a225f079 VS |
952 | int intel_get_crtc_scanline(struct intel_crtc *crtc) |
953 | { | |
fac5e23e | 954 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
a225f079 VS |
955 | unsigned long irqflags; |
956 | int position; | |
957 | ||
958 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
959 | position = __intel_get_crtc_scanline(crtc); | |
960 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
961 | ||
962 | return position; | |
963 | } | |
964 | ||
88e72717 | 965 | static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe, |
0af7e4df MK |
966 | int *max_error, |
967 | struct timeval *vblank_time, | |
968 | unsigned flags) | |
969 | { | |
b91eb5cc | 970 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2af48c6 | 971 | struct intel_crtc *crtc; |
0af7e4df | 972 | |
b91eb5cc | 973 | if (pipe >= INTEL_INFO(dev_priv)->num_pipes) { |
88e72717 | 974 | DRM_ERROR("Invalid crtc %u\n", pipe); |
0af7e4df MK |
975 | return -EINVAL; |
976 | } | |
977 | ||
978 | /* Get drm_crtc to timestamp: */ | |
b91eb5cc | 979 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
4041b853 | 980 | if (crtc == NULL) { |
88e72717 | 981 | DRM_ERROR("Invalid crtc %u\n", pipe); |
4041b853 CW |
982 | return -EINVAL; |
983 | } | |
984 | ||
e2af48c6 | 985 | if (!crtc->base.hwmode.crtc_clock) { |
88e72717 | 986 | DRM_DEBUG_KMS("crtc %u is disabled\n", pipe); |
4041b853 CW |
987 | return -EBUSY; |
988 | } | |
0af7e4df MK |
989 | |
990 | /* Helper routine in DRM core does all the work: */ | |
4041b853 CW |
991 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
992 | vblank_time, flags, | |
e2af48c6 | 993 | &crtc->base.hwmode); |
0af7e4df MK |
994 | } |
995 | ||
91d14251 | 996 | static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv) |
f97108d1 | 997 | { |
b5b72e89 | 998 | u32 busy_up, busy_down, max_avg, min_avg; |
9270388e | 999 | u8 new_delay; |
9270388e | 1000 | |
d0ecd7e2 | 1001 | spin_lock(&mchdev_lock); |
f97108d1 | 1002 | |
73edd18f DV |
1003 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
1004 | ||
20e4d407 | 1005 | new_delay = dev_priv->ips.cur_delay; |
9270388e | 1006 | |
7648fa99 | 1007 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
1008 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
1009 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
1010 | max_avg = I915_READ(RCBMAXAVG); |
1011 | min_avg = I915_READ(RCBMINAVG); | |
1012 | ||
1013 | /* Handle RCS change request from hw */ | |
b5b72e89 | 1014 | if (busy_up > max_avg) { |
20e4d407 DV |
1015 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
1016 | new_delay = dev_priv->ips.cur_delay - 1; | |
1017 | if (new_delay < dev_priv->ips.max_delay) | |
1018 | new_delay = dev_priv->ips.max_delay; | |
b5b72e89 | 1019 | } else if (busy_down < min_avg) { |
20e4d407 DV |
1020 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
1021 | new_delay = dev_priv->ips.cur_delay + 1; | |
1022 | if (new_delay > dev_priv->ips.min_delay) | |
1023 | new_delay = dev_priv->ips.min_delay; | |
f97108d1 JB |
1024 | } |
1025 | ||
91d14251 | 1026 | if (ironlake_set_drps(dev_priv, new_delay)) |
20e4d407 | 1027 | dev_priv->ips.cur_delay = new_delay; |
f97108d1 | 1028 | |
d0ecd7e2 | 1029 | spin_unlock(&mchdev_lock); |
9270388e | 1030 | |
f97108d1 JB |
1031 | return; |
1032 | } | |
1033 | ||
0bc40be8 | 1034 | static void notify_ring(struct intel_engine_cs *engine) |
549f7365 | 1035 | { |
aca34b6e | 1036 | smp_store_mb(engine->breadcrumbs.irq_posted, true); |
83348ba8 | 1037 | if (intel_engine_wakeup(engine)) |
688e6c72 | 1038 | trace_i915_gem_request_notify(engine); |
549f7365 CW |
1039 | } |
1040 | ||
43cf3bf0 CW |
1041 | static void vlv_c0_read(struct drm_i915_private *dev_priv, |
1042 | struct intel_rps_ei *ei) | |
31685c25 | 1043 | { |
43cf3bf0 CW |
1044 | ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP); |
1045 | ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT); | |
1046 | ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT); | |
1047 | } | |
31685c25 | 1048 | |
43cf3bf0 CW |
1049 | static bool vlv_c0_above(struct drm_i915_private *dev_priv, |
1050 | const struct intel_rps_ei *old, | |
1051 | const struct intel_rps_ei *now, | |
1052 | int threshold) | |
1053 | { | |
1054 | u64 time, c0; | |
7bad74d5 | 1055 | unsigned int mul = 100; |
31685c25 | 1056 | |
43cf3bf0 CW |
1057 | if (old->cz_clock == 0) |
1058 | return false; | |
31685c25 | 1059 | |
7bad74d5 VS |
1060 | if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH) |
1061 | mul <<= 8; | |
1062 | ||
43cf3bf0 | 1063 | time = now->cz_clock - old->cz_clock; |
7bad74d5 | 1064 | time *= threshold * dev_priv->czclk_freq; |
31685c25 | 1065 | |
43cf3bf0 CW |
1066 | /* Workload can be split between render + media, e.g. SwapBuffers |
1067 | * being blitted in X after being rendered in mesa. To account for | |
1068 | * this we need to combine both engines into our activity counter. | |
31685c25 | 1069 | */ |
43cf3bf0 CW |
1070 | c0 = now->render_c0 - old->render_c0; |
1071 | c0 += now->media_c0 - old->media_c0; | |
7bad74d5 | 1072 | c0 *= mul * VLV_CZ_CLOCK_TO_MILLI_SEC; |
31685c25 | 1073 | |
43cf3bf0 | 1074 | return c0 >= time; |
31685c25 D |
1075 | } |
1076 | ||
43cf3bf0 | 1077 | void gen6_rps_reset_ei(struct drm_i915_private *dev_priv) |
31685c25 | 1078 | { |
43cf3bf0 CW |
1079 | vlv_c0_read(dev_priv, &dev_priv->rps.down_ei); |
1080 | dev_priv->rps.up_ei = dev_priv->rps.down_ei; | |
43cf3bf0 | 1081 | } |
31685c25 | 1082 | |
43cf3bf0 CW |
1083 | static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir) |
1084 | { | |
1085 | struct intel_rps_ei now; | |
1086 | u32 events = 0; | |
31685c25 | 1087 | |
6f4b12f8 | 1088 | if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0) |
43cf3bf0 | 1089 | return 0; |
31685c25 | 1090 | |
43cf3bf0 CW |
1091 | vlv_c0_read(dev_priv, &now); |
1092 | if (now.cz_clock == 0) | |
1093 | return 0; | |
31685c25 | 1094 | |
43cf3bf0 CW |
1095 | if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) { |
1096 | if (!vlv_c0_above(dev_priv, | |
1097 | &dev_priv->rps.down_ei, &now, | |
8fb55197 | 1098 | dev_priv->rps.down_threshold)) |
43cf3bf0 CW |
1099 | events |= GEN6_PM_RP_DOWN_THRESHOLD; |
1100 | dev_priv->rps.down_ei = now; | |
1101 | } | |
31685c25 | 1102 | |
43cf3bf0 CW |
1103 | if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) { |
1104 | if (vlv_c0_above(dev_priv, | |
1105 | &dev_priv->rps.up_ei, &now, | |
8fb55197 | 1106 | dev_priv->rps.up_threshold)) |
43cf3bf0 CW |
1107 | events |= GEN6_PM_RP_UP_THRESHOLD; |
1108 | dev_priv->rps.up_ei = now; | |
31685c25 D |
1109 | } |
1110 | ||
43cf3bf0 | 1111 | return events; |
31685c25 D |
1112 | } |
1113 | ||
f5a4c67d CW |
1114 | static bool any_waiters(struct drm_i915_private *dev_priv) |
1115 | { | |
e2f80391 | 1116 | struct intel_engine_cs *engine; |
3b3f1650 | 1117 | enum intel_engine_id id; |
f5a4c67d | 1118 | |
3b3f1650 | 1119 | for_each_engine(engine, dev_priv, id) |
688e6c72 | 1120 | if (intel_engine_has_waiter(engine)) |
f5a4c67d CW |
1121 | return true; |
1122 | ||
1123 | return false; | |
1124 | } | |
1125 | ||
4912d041 | 1126 | static void gen6_pm_rps_work(struct work_struct *work) |
3b8d8d91 | 1127 | { |
2d1013dd JN |
1128 | struct drm_i915_private *dev_priv = |
1129 | container_of(work, struct drm_i915_private, rps.work); | |
8d3afd7d CW |
1130 | bool client_boost; |
1131 | int new_delay, adj, min, max; | |
edbfdb45 | 1132 | u32 pm_iir; |
4912d041 | 1133 | |
59cdb63d | 1134 | spin_lock_irq(&dev_priv->irq_lock); |
d4d70aa5 ID |
1135 | /* Speed up work cancelation during disabling rps interrupts. */ |
1136 | if (!dev_priv->rps.interrupts_enabled) { | |
1137 | spin_unlock_irq(&dev_priv->irq_lock); | |
1138 | return; | |
1139 | } | |
1f814dac | 1140 | |
c6a828d3 DV |
1141 | pm_iir = dev_priv->rps.pm_iir; |
1142 | dev_priv->rps.pm_iir = 0; | |
a72fbc3a | 1143 | /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */ |
f4e9af4f | 1144 | gen6_unmask_pm_irq(dev_priv, dev_priv->pm_rps_events); |
8d3afd7d CW |
1145 | client_boost = dev_priv->rps.client_boost; |
1146 | dev_priv->rps.client_boost = false; | |
59cdb63d | 1147 | spin_unlock_irq(&dev_priv->irq_lock); |
3b8d8d91 | 1148 | |
60611c13 | 1149 | /* Make sure we didn't queue anything we're not going to process. */ |
a6706b45 | 1150 | WARN_ON(pm_iir & ~dev_priv->pm_rps_events); |
60611c13 | 1151 | |
8d3afd7d | 1152 | if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost) |
c33d247d | 1153 | return; |
3b8d8d91 | 1154 | |
4fc688ce | 1155 | mutex_lock(&dev_priv->rps.hw_lock); |
7b9e0ae6 | 1156 | |
43cf3bf0 CW |
1157 | pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir); |
1158 | ||
dd75fdc8 | 1159 | adj = dev_priv->rps.last_adj; |
edcf284b | 1160 | new_delay = dev_priv->rps.cur_freq; |
8d3afd7d CW |
1161 | min = dev_priv->rps.min_freq_softlimit; |
1162 | max = dev_priv->rps.max_freq_softlimit; | |
29ecd78d CW |
1163 | if (client_boost || any_waiters(dev_priv)) |
1164 | max = dev_priv->rps.max_freq; | |
1165 | if (client_boost && new_delay < dev_priv->rps.boost_freq) { | |
1166 | new_delay = dev_priv->rps.boost_freq; | |
8d3afd7d CW |
1167 | adj = 0; |
1168 | } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { | |
dd75fdc8 CW |
1169 | if (adj > 0) |
1170 | adj *= 2; | |
edcf284b CW |
1171 | else /* CHV needs even encode values */ |
1172 | adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1; | |
7425034a VS |
1173 | /* |
1174 | * For better performance, jump directly | |
1175 | * to RPe if we're below it. | |
1176 | */ | |
edcf284b | 1177 | if (new_delay < dev_priv->rps.efficient_freq - adj) { |
b39fb297 | 1178 | new_delay = dev_priv->rps.efficient_freq; |
edcf284b CW |
1179 | adj = 0; |
1180 | } | |
29ecd78d | 1181 | } else if (client_boost || any_waiters(dev_priv)) { |
f5a4c67d | 1182 | adj = 0; |
dd75fdc8 | 1183 | } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { |
b39fb297 BW |
1184 | if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq) |
1185 | new_delay = dev_priv->rps.efficient_freq; | |
dd75fdc8 | 1186 | else |
b39fb297 | 1187 | new_delay = dev_priv->rps.min_freq_softlimit; |
dd75fdc8 CW |
1188 | adj = 0; |
1189 | } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { | |
1190 | if (adj < 0) | |
1191 | adj *= 2; | |
edcf284b CW |
1192 | else /* CHV needs even encode values */ |
1193 | adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1; | |
dd75fdc8 | 1194 | } else { /* unknown event */ |
edcf284b | 1195 | adj = 0; |
dd75fdc8 | 1196 | } |
3b8d8d91 | 1197 | |
edcf284b CW |
1198 | dev_priv->rps.last_adj = adj; |
1199 | ||
79249636 BW |
1200 | /* sysfs frequency interfaces may have snuck in while servicing the |
1201 | * interrupt | |
1202 | */ | |
edcf284b | 1203 | new_delay += adj; |
8d3afd7d | 1204 | new_delay = clamp_t(int, new_delay, min, max); |
27544369 | 1205 | |
dc97997a | 1206 | intel_set_rps(dev_priv, new_delay); |
3b8d8d91 | 1207 | |
4fc688ce | 1208 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 JB |
1209 | } |
1210 | ||
e3689190 BW |
1211 | |
1212 | /** | |
1213 | * ivybridge_parity_work - Workqueue called when a parity error interrupt | |
1214 | * occurred. | |
1215 | * @work: workqueue struct | |
1216 | * | |
1217 | * Doesn't actually do anything except notify userspace. As a consequence of | |
1218 | * this event, userspace should try to remap the bad rows since statistically | |
1219 | * it is likely the same row is more likely to go bad again. | |
1220 | */ | |
1221 | static void ivybridge_parity_work(struct work_struct *work) | |
1222 | { | |
2d1013dd JN |
1223 | struct drm_i915_private *dev_priv = |
1224 | container_of(work, struct drm_i915_private, l3_parity.error_work); | |
e3689190 | 1225 | u32 error_status, row, bank, subbank; |
35a85ac6 | 1226 | char *parity_event[6]; |
e3689190 | 1227 | uint32_t misccpctl; |
35a85ac6 | 1228 | uint8_t slice = 0; |
e3689190 BW |
1229 | |
1230 | /* We must turn off DOP level clock gating to access the L3 registers. | |
1231 | * In order to prevent a get/put style interface, acquire struct mutex | |
1232 | * any time we access those registers. | |
1233 | */ | |
91c8a326 | 1234 | mutex_lock(&dev_priv->drm.struct_mutex); |
e3689190 | 1235 | |
35a85ac6 BW |
1236 | /* If we've screwed up tracking, just let the interrupt fire again */ |
1237 | if (WARN_ON(!dev_priv->l3_parity.which_slice)) | |
1238 | goto out; | |
1239 | ||
e3689190 BW |
1240 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
1241 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
1242 | POSTING_READ(GEN7_MISCCPCTL); | |
1243 | ||
35a85ac6 | 1244 | while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { |
f0f59a00 | 1245 | i915_reg_t reg; |
e3689190 | 1246 | |
35a85ac6 | 1247 | slice--; |
2d1fe073 | 1248 | if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv))) |
35a85ac6 | 1249 | break; |
e3689190 | 1250 | |
35a85ac6 | 1251 | dev_priv->l3_parity.which_slice &= ~(1<<slice); |
e3689190 | 1252 | |
6fa1c5f1 | 1253 | reg = GEN7_L3CDERRST1(slice); |
e3689190 | 1254 | |
35a85ac6 BW |
1255 | error_status = I915_READ(reg); |
1256 | row = GEN7_PARITY_ERROR_ROW(error_status); | |
1257 | bank = GEN7_PARITY_ERROR_BANK(error_status); | |
1258 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); | |
1259 | ||
1260 | I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); | |
1261 | POSTING_READ(reg); | |
1262 | ||
1263 | parity_event[0] = I915_L3_PARITY_UEVENT "=1"; | |
1264 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); | |
1265 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); | |
1266 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); | |
1267 | parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); | |
1268 | parity_event[5] = NULL; | |
1269 | ||
91c8a326 | 1270 | kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj, |
35a85ac6 | 1271 | KOBJ_CHANGE, parity_event); |
e3689190 | 1272 | |
35a85ac6 BW |
1273 | DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", |
1274 | slice, row, bank, subbank); | |
e3689190 | 1275 | |
35a85ac6 BW |
1276 | kfree(parity_event[4]); |
1277 | kfree(parity_event[3]); | |
1278 | kfree(parity_event[2]); | |
1279 | kfree(parity_event[1]); | |
1280 | } | |
e3689190 | 1281 | |
35a85ac6 | 1282 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
e3689190 | 1283 | |
35a85ac6 BW |
1284 | out: |
1285 | WARN_ON(dev_priv->l3_parity.which_slice); | |
4cb21832 | 1286 | spin_lock_irq(&dev_priv->irq_lock); |
2d1fe073 | 1287 | gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv)); |
4cb21832 | 1288 | spin_unlock_irq(&dev_priv->irq_lock); |
35a85ac6 | 1289 | |
91c8a326 | 1290 | mutex_unlock(&dev_priv->drm.struct_mutex); |
e3689190 BW |
1291 | } |
1292 | ||
261e40b8 VS |
1293 | static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv, |
1294 | u32 iir) | |
e3689190 | 1295 | { |
261e40b8 | 1296 | if (!HAS_L3_DPF(dev_priv)) |
e3689190 BW |
1297 | return; |
1298 | ||
d0ecd7e2 | 1299 | spin_lock(&dev_priv->irq_lock); |
261e40b8 | 1300 | gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv)); |
d0ecd7e2 | 1301 | spin_unlock(&dev_priv->irq_lock); |
e3689190 | 1302 | |
261e40b8 | 1303 | iir &= GT_PARITY_ERROR(dev_priv); |
35a85ac6 BW |
1304 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) |
1305 | dev_priv->l3_parity.which_slice |= 1 << 1; | |
1306 | ||
1307 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) | |
1308 | dev_priv->l3_parity.which_slice |= 1 << 0; | |
1309 | ||
a4da4fa4 | 1310 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
e3689190 BW |
1311 | } |
1312 | ||
261e40b8 | 1313 | static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv, |
f1af8fc1 PZ |
1314 | u32 gt_iir) |
1315 | { | |
f8973c21 | 1316 | if (gt_iir & GT_RENDER_USER_INTERRUPT) |
3b3f1650 | 1317 | notify_ring(dev_priv->engine[RCS]); |
f1af8fc1 | 1318 | if (gt_iir & ILK_BSD_USER_INTERRUPT) |
3b3f1650 | 1319 | notify_ring(dev_priv->engine[VCS]); |
f1af8fc1 PZ |
1320 | } |
1321 | ||
261e40b8 | 1322 | static void snb_gt_irq_handler(struct drm_i915_private *dev_priv, |
e7b4c6b1 DV |
1323 | u32 gt_iir) |
1324 | { | |
f8973c21 | 1325 | if (gt_iir & GT_RENDER_USER_INTERRUPT) |
3b3f1650 | 1326 | notify_ring(dev_priv->engine[RCS]); |
cc609d5d | 1327 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
3b3f1650 | 1328 | notify_ring(dev_priv->engine[VCS]); |
cc609d5d | 1329 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
3b3f1650 | 1330 | notify_ring(dev_priv->engine[BCS]); |
e7b4c6b1 | 1331 | |
cc609d5d BW |
1332 | if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | |
1333 | GT_BSD_CS_ERROR_INTERRUPT | | |
aaecdf61 DV |
1334 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) |
1335 | DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir); | |
e3689190 | 1336 | |
261e40b8 VS |
1337 | if (gt_iir & GT_PARITY_ERROR(dev_priv)) |
1338 | ivybridge_parity_error_irq_handler(dev_priv, gt_iir); | |
e7b4c6b1 DV |
1339 | } |
1340 | ||
fbcc1a0c | 1341 | static __always_inline void |
0bc40be8 | 1342 | gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift) |
fbcc1a0c NH |
1343 | { |
1344 | if (iir & (GT_RENDER_USER_INTERRUPT << test_shift)) | |
0bc40be8 | 1345 | notify_ring(engine); |
fbcc1a0c | 1346 | if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift)) |
27af5eea | 1347 | tasklet_schedule(&engine->irq_tasklet); |
fbcc1a0c NH |
1348 | } |
1349 | ||
e30e251a VS |
1350 | static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv, |
1351 | u32 master_ctl, | |
1352 | u32 gt_iir[4]) | |
abd58f01 | 1353 | { |
abd58f01 BW |
1354 | irqreturn_t ret = IRQ_NONE; |
1355 | ||
1356 | if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { | |
e30e251a VS |
1357 | gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0)); |
1358 | if (gt_iir[0]) { | |
1359 | I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]); | |
abd58f01 | 1360 | ret = IRQ_HANDLED; |
abd58f01 BW |
1361 | } else |
1362 | DRM_ERROR("The master control interrupt lied (GT0)!\n"); | |
1363 | } | |
1364 | ||
85f9b5f9 | 1365 | if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) { |
e30e251a VS |
1366 | gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1)); |
1367 | if (gt_iir[1]) { | |
1368 | I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]); | |
abd58f01 | 1369 | ret = IRQ_HANDLED; |
0961021a | 1370 | } else |
abd58f01 | 1371 | DRM_ERROR("The master control interrupt lied (GT1)!\n"); |
0961021a BW |
1372 | } |
1373 | ||
abd58f01 | 1374 | if (master_ctl & GEN8_GT_VECS_IRQ) { |
e30e251a VS |
1375 | gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3)); |
1376 | if (gt_iir[3]) { | |
1377 | I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]); | |
abd58f01 | 1378 | ret = IRQ_HANDLED; |
abd58f01 BW |
1379 | } else |
1380 | DRM_ERROR("The master control interrupt lied (GT3)!\n"); | |
1381 | } | |
1382 | ||
26705e20 | 1383 | if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) { |
e30e251a | 1384 | gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2)); |
26705e20 SAK |
1385 | if (gt_iir[2] & (dev_priv->pm_rps_events | |
1386 | dev_priv->pm_guc_events)) { | |
cb0d205e | 1387 | I915_WRITE_FW(GEN8_GT_IIR(2), |
26705e20 SAK |
1388 | gt_iir[2] & (dev_priv->pm_rps_events | |
1389 | dev_priv->pm_guc_events)); | |
38cc46d7 | 1390 | ret = IRQ_HANDLED; |
0961021a BW |
1391 | } else |
1392 | DRM_ERROR("The master control interrupt lied (PM)!\n"); | |
1393 | } | |
1394 | ||
abd58f01 BW |
1395 | return ret; |
1396 | } | |
1397 | ||
e30e251a VS |
1398 | static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv, |
1399 | u32 gt_iir[4]) | |
1400 | { | |
1401 | if (gt_iir[0]) { | |
3b3f1650 | 1402 | gen8_cs_irq_handler(dev_priv->engine[RCS], |
e30e251a | 1403 | gt_iir[0], GEN8_RCS_IRQ_SHIFT); |
3b3f1650 | 1404 | gen8_cs_irq_handler(dev_priv->engine[BCS], |
e30e251a VS |
1405 | gt_iir[0], GEN8_BCS_IRQ_SHIFT); |
1406 | } | |
1407 | ||
1408 | if (gt_iir[1]) { | |
3b3f1650 | 1409 | gen8_cs_irq_handler(dev_priv->engine[VCS], |
e30e251a | 1410 | gt_iir[1], GEN8_VCS1_IRQ_SHIFT); |
3b3f1650 | 1411 | gen8_cs_irq_handler(dev_priv->engine[VCS2], |
e30e251a VS |
1412 | gt_iir[1], GEN8_VCS2_IRQ_SHIFT); |
1413 | } | |
1414 | ||
1415 | if (gt_iir[3]) | |
3b3f1650 | 1416 | gen8_cs_irq_handler(dev_priv->engine[VECS], |
e30e251a VS |
1417 | gt_iir[3], GEN8_VECS_IRQ_SHIFT); |
1418 | ||
1419 | if (gt_iir[2] & dev_priv->pm_rps_events) | |
1420 | gen6_rps_irq_handler(dev_priv, gt_iir[2]); | |
26705e20 SAK |
1421 | |
1422 | if (gt_iir[2] & dev_priv->pm_guc_events) | |
1423 | gen9_guc_irq_handler(dev_priv, gt_iir[2]); | |
e30e251a VS |
1424 | } |
1425 | ||
63c88d22 ID |
1426 | static bool bxt_port_hotplug_long_detect(enum port port, u32 val) |
1427 | { | |
1428 | switch (port) { | |
1429 | case PORT_A: | |
195baa06 | 1430 | return val & PORTA_HOTPLUG_LONG_DETECT; |
63c88d22 ID |
1431 | case PORT_B: |
1432 | return val & PORTB_HOTPLUG_LONG_DETECT; | |
1433 | case PORT_C: | |
1434 | return val & PORTC_HOTPLUG_LONG_DETECT; | |
63c88d22 ID |
1435 | default: |
1436 | return false; | |
1437 | } | |
1438 | } | |
1439 | ||
6dbf30ce VS |
1440 | static bool spt_port_hotplug2_long_detect(enum port port, u32 val) |
1441 | { | |
1442 | switch (port) { | |
1443 | case PORT_E: | |
1444 | return val & PORTE_HOTPLUG_LONG_DETECT; | |
1445 | default: | |
1446 | return false; | |
1447 | } | |
1448 | } | |
1449 | ||
74c0b395 VS |
1450 | static bool spt_port_hotplug_long_detect(enum port port, u32 val) |
1451 | { | |
1452 | switch (port) { | |
1453 | case PORT_A: | |
1454 | return val & PORTA_HOTPLUG_LONG_DETECT; | |
1455 | case PORT_B: | |
1456 | return val & PORTB_HOTPLUG_LONG_DETECT; | |
1457 | case PORT_C: | |
1458 | return val & PORTC_HOTPLUG_LONG_DETECT; | |
1459 | case PORT_D: | |
1460 | return val & PORTD_HOTPLUG_LONG_DETECT; | |
1461 | default: | |
1462 | return false; | |
1463 | } | |
1464 | } | |
1465 | ||
e4ce95aa VS |
1466 | static bool ilk_port_hotplug_long_detect(enum port port, u32 val) |
1467 | { | |
1468 | switch (port) { | |
1469 | case PORT_A: | |
1470 | return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT; | |
1471 | default: | |
1472 | return false; | |
1473 | } | |
1474 | } | |
1475 | ||
676574df | 1476 | static bool pch_port_hotplug_long_detect(enum port port, u32 val) |
13cf5504 DA |
1477 | { |
1478 | switch (port) { | |
13cf5504 | 1479 | case PORT_B: |
676574df | 1480 | return val & PORTB_HOTPLUG_LONG_DETECT; |
13cf5504 | 1481 | case PORT_C: |
676574df | 1482 | return val & PORTC_HOTPLUG_LONG_DETECT; |
13cf5504 | 1483 | case PORT_D: |
676574df JN |
1484 | return val & PORTD_HOTPLUG_LONG_DETECT; |
1485 | default: | |
1486 | return false; | |
13cf5504 DA |
1487 | } |
1488 | } | |
1489 | ||
676574df | 1490 | static bool i9xx_port_hotplug_long_detect(enum port port, u32 val) |
13cf5504 DA |
1491 | { |
1492 | switch (port) { | |
13cf5504 | 1493 | case PORT_B: |
676574df | 1494 | return val & PORTB_HOTPLUG_INT_LONG_PULSE; |
13cf5504 | 1495 | case PORT_C: |
676574df | 1496 | return val & PORTC_HOTPLUG_INT_LONG_PULSE; |
13cf5504 | 1497 | case PORT_D: |
676574df JN |
1498 | return val & PORTD_HOTPLUG_INT_LONG_PULSE; |
1499 | default: | |
1500 | return false; | |
13cf5504 DA |
1501 | } |
1502 | } | |
1503 | ||
42db67d6 VS |
1504 | /* |
1505 | * Get a bit mask of pins that have triggered, and which ones may be long. | |
1506 | * This can be called multiple times with the same masks to accumulate | |
1507 | * hotplug detection results from several registers. | |
1508 | * | |
1509 | * Note that the caller is expected to zero out the masks initially. | |
1510 | */ | |
fd63e2a9 | 1511 | static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask, |
8c841e57 | 1512 | u32 hotplug_trigger, u32 dig_hotplug_reg, |
fd63e2a9 ID |
1513 | const u32 hpd[HPD_NUM_PINS], |
1514 | bool long_pulse_detect(enum port port, u32 val)) | |
676574df | 1515 | { |
8c841e57 | 1516 | enum port port; |
676574df JN |
1517 | int i; |
1518 | ||
676574df | 1519 | for_each_hpd_pin(i) { |
8c841e57 JN |
1520 | if ((hpd[i] & hotplug_trigger) == 0) |
1521 | continue; | |
676574df | 1522 | |
8c841e57 JN |
1523 | *pin_mask |= BIT(i); |
1524 | ||
cc24fcdc ID |
1525 | if (!intel_hpd_pin_to_port(i, &port)) |
1526 | continue; | |
1527 | ||
fd63e2a9 | 1528 | if (long_pulse_detect(port, dig_hotplug_reg)) |
8c841e57 | 1529 | *long_mask |= BIT(i); |
676574df JN |
1530 | } |
1531 | ||
1532 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n", | |
1533 | hotplug_trigger, dig_hotplug_reg, *pin_mask); | |
1534 | ||
1535 | } | |
1536 | ||
91d14251 | 1537 | static void gmbus_irq_handler(struct drm_i915_private *dev_priv) |
515ac2bb | 1538 | { |
28c70f16 | 1539 | wake_up_all(&dev_priv->gmbus_wait_queue); |
515ac2bb DV |
1540 | } |
1541 | ||
91d14251 | 1542 | static void dp_aux_irq_handler(struct drm_i915_private *dev_priv) |
ce99c256 | 1543 | { |
9ee32fea | 1544 | wake_up_all(&dev_priv->gmbus_wait_queue); |
ce99c256 DV |
1545 | } |
1546 | ||
8bf1e9f1 | 1547 | #if defined(CONFIG_DEBUG_FS) |
91d14251 TU |
1548 | static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, |
1549 | enum pipe pipe, | |
277de95e DV |
1550 | uint32_t crc0, uint32_t crc1, |
1551 | uint32_t crc2, uint32_t crc3, | |
1552 | uint32_t crc4) | |
8bf1e9f1 | 1553 | { |
8bf1e9f1 SH |
1554 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
1555 | struct intel_pipe_crc_entry *entry; | |
ac2300d4 | 1556 | int head, tail; |
b2c88f5b | 1557 | |
d538bbdf DL |
1558 | spin_lock(&pipe_crc->lock); |
1559 | ||
0c912c79 | 1560 | if (!pipe_crc->entries) { |
d538bbdf | 1561 | spin_unlock(&pipe_crc->lock); |
34273620 | 1562 | DRM_DEBUG_KMS("spurious interrupt\n"); |
0c912c79 DL |
1563 | return; |
1564 | } | |
1565 | ||
d538bbdf DL |
1566 | head = pipe_crc->head; |
1567 | tail = pipe_crc->tail; | |
b2c88f5b DL |
1568 | |
1569 | if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { | |
d538bbdf | 1570 | spin_unlock(&pipe_crc->lock); |
b2c88f5b DL |
1571 | DRM_ERROR("CRC buffer overflowing\n"); |
1572 | return; | |
1573 | } | |
1574 | ||
1575 | entry = &pipe_crc->entries[head]; | |
8bf1e9f1 | 1576 | |
91c8a326 | 1577 | entry->frame = dev_priv->drm.driver->get_vblank_counter(&dev_priv->drm, |
91d14251 | 1578 | pipe); |
eba94eb9 DV |
1579 | entry->crc[0] = crc0; |
1580 | entry->crc[1] = crc1; | |
1581 | entry->crc[2] = crc2; | |
1582 | entry->crc[3] = crc3; | |
1583 | entry->crc[4] = crc4; | |
b2c88f5b DL |
1584 | |
1585 | head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
d538bbdf DL |
1586 | pipe_crc->head = head; |
1587 | ||
1588 | spin_unlock(&pipe_crc->lock); | |
07144428 DL |
1589 | |
1590 | wake_up_interruptible(&pipe_crc->wq); | |
8bf1e9f1 | 1591 | } |
277de95e DV |
1592 | #else |
1593 | static inline void | |
91d14251 TU |
1594 | display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, |
1595 | enum pipe pipe, | |
277de95e DV |
1596 | uint32_t crc0, uint32_t crc1, |
1597 | uint32_t crc2, uint32_t crc3, | |
1598 | uint32_t crc4) {} | |
1599 | #endif | |
1600 | ||
eba94eb9 | 1601 | |
91d14251 TU |
1602 | static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, |
1603 | enum pipe pipe) | |
5a69b89f | 1604 | { |
91d14251 | 1605 | display_pipe_crc_irq_handler(dev_priv, pipe, |
277de95e DV |
1606 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), |
1607 | 0, 0, 0, 0); | |
5a69b89f DV |
1608 | } |
1609 | ||
91d14251 TU |
1610 | static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, |
1611 | enum pipe pipe) | |
eba94eb9 | 1612 | { |
91d14251 | 1613 | display_pipe_crc_irq_handler(dev_priv, pipe, |
277de95e DV |
1614 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), |
1615 | I915_READ(PIPE_CRC_RES_2_IVB(pipe)), | |
1616 | I915_READ(PIPE_CRC_RES_3_IVB(pipe)), | |
1617 | I915_READ(PIPE_CRC_RES_4_IVB(pipe)), | |
1618 | I915_READ(PIPE_CRC_RES_5_IVB(pipe))); | |
eba94eb9 | 1619 | } |
5b3a856b | 1620 | |
91d14251 TU |
1621 | static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, |
1622 | enum pipe pipe) | |
5b3a856b | 1623 | { |
0b5c5ed0 DV |
1624 | uint32_t res1, res2; |
1625 | ||
91d14251 | 1626 | if (INTEL_GEN(dev_priv) >= 3) |
0b5c5ed0 DV |
1627 | res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); |
1628 | else | |
1629 | res1 = 0; | |
1630 | ||
91d14251 | 1631 | if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
0b5c5ed0 DV |
1632 | res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); |
1633 | else | |
1634 | res2 = 0; | |
5b3a856b | 1635 | |
91d14251 | 1636 | display_pipe_crc_irq_handler(dev_priv, pipe, |
277de95e DV |
1637 | I915_READ(PIPE_CRC_RES_RED(pipe)), |
1638 | I915_READ(PIPE_CRC_RES_GREEN(pipe)), | |
1639 | I915_READ(PIPE_CRC_RES_BLUE(pipe)), | |
1640 | res1, res2); | |
5b3a856b | 1641 | } |
8bf1e9f1 | 1642 | |
1403c0d4 PZ |
1643 | /* The RPS events need forcewake, so we add them to a work queue and mask their |
1644 | * IMR bits until the work is done. Other interrupts can be processed without | |
1645 | * the work queue. */ | |
1646 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) | |
baf02a1f | 1647 | { |
a6706b45 | 1648 | if (pm_iir & dev_priv->pm_rps_events) { |
59cdb63d | 1649 | spin_lock(&dev_priv->irq_lock); |
f4e9af4f | 1650 | gen6_mask_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); |
d4d70aa5 ID |
1651 | if (dev_priv->rps.interrupts_enabled) { |
1652 | dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; | |
c33d247d | 1653 | schedule_work(&dev_priv->rps.work); |
d4d70aa5 | 1654 | } |
59cdb63d | 1655 | spin_unlock(&dev_priv->irq_lock); |
baf02a1f | 1656 | } |
baf02a1f | 1657 | |
c9a9a268 ID |
1658 | if (INTEL_INFO(dev_priv)->gen >= 8) |
1659 | return; | |
1660 | ||
2d1fe073 | 1661 | if (HAS_VEBOX(dev_priv)) { |
1403c0d4 | 1662 | if (pm_iir & PM_VEBOX_USER_INTERRUPT) |
3b3f1650 | 1663 | notify_ring(dev_priv->engine[VECS]); |
12638c57 | 1664 | |
aaecdf61 DV |
1665 | if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) |
1666 | DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir); | |
12638c57 | 1667 | } |
baf02a1f BW |
1668 | } |
1669 | ||
26705e20 SAK |
1670 | static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir) |
1671 | { | |
1672 | if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT) { | |
4100b2ab SAK |
1673 | /* Sample the log buffer flush related bits & clear them out now |
1674 | * itself from the message identity register to minimize the | |
1675 | * probability of losing a flush interrupt, when there are back | |
1676 | * to back flush interrupts. | |
1677 | * There can be a new flush interrupt, for different log buffer | |
1678 | * type (like for ISR), whilst Host is handling one (for DPC). | |
1679 | * Since same bit is used in message register for ISR & DPC, it | |
1680 | * could happen that GuC sets the bit for 2nd interrupt but Host | |
1681 | * clears out the bit on handling the 1st interrupt. | |
1682 | */ | |
1683 | u32 msg, flush; | |
1684 | ||
1685 | msg = I915_READ(SOFT_SCRATCH(15)); | |
1686 | flush = msg & (GUC2HOST_MSG_CRASH_DUMP_POSTED | | |
1687 | GUC2HOST_MSG_FLUSH_LOG_BUFFER); | |
1688 | if (flush) { | |
1689 | /* Clear the message bits that are handled */ | |
1690 | I915_WRITE(SOFT_SCRATCH(15), msg & ~flush); | |
1691 | ||
1692 | /* Handle flush interrupt in bottom half */ | |
1693 | queue_work(dev_priv->guc.log.flush_wq, | |
1694 | &dev_priv->guc.log.flush_work); | |
5aa1ee4b AG |
1695 | |
1696 | dev_priv->guc.log.flush_interrupt_count++; | |
4100b2ab SAK |
1697 | } else { |
1698 | /* Not clearing of unhandled event bits won't result in | |
1699 | * re-triggering of the interrupt. | |
1700 | */ | |
1701 | } | |
26705e20 SAK |
1702 | } |
1703 | } | |
1704 | ||
5a21b665 | 1705 | static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv, |
91d14251 | 1706 | enum pipe pipe) |
8d7849db | 1707 | { |
5a21b665 DV |
1708 | bool ret; |
1709 | ||
91c8a326 | 1710 | ret = drm_handle_vblank(&dev_priv->drm, pipe); |
5a21b665 | 1711 | if (ret) |
51cbaf01 | 1712 | intel_finish_page_flip_mmio(dev_priv, pipe); |
5a21b665 DV |
1713 | |
1714 | return ret; | |
8d7849db VS |
1715 | } |
1716 | ||
91d14251 TU |
1717 | static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv, |
1718 | u32 iir, u32 pipe_stats[I915_MAX_PIPES]) | |
c1874ed7 | 1719 | { |
c1874ed7 ID |
1720 | int pipe; |
1721 | ||
58ead0d7 | 1722 | spin_lock(&dev_priv->irq_lock); |
1ca993d2 VS |
1723 | |
1724 | if (!dev_priv->display_irqs_enabled) { | |
1725 | spin_unlock(&dev_priv->irq_lock); | |
1726 | return; | |
1727 | } | |
1728 | ||
055e393f | 1729 | for_each_pipe(dev_priv, pipe) { |
f0f59a00 | 1730 | i915_reg_t reg; |
bbb5eebf | 1731 | u32 mask, iir_bit = 0; |
91d181dd | 1732 | |
bbb5eebf DV |
1733 | /* |
1734 | * PIPESTAT bits get signalled even when the interrupt is | |
1735 | * disabled with the mask bits, and some of the status bits do | |
1736 | * not generate interrupts at all (like the underrun bit). Hence | |
1737 | * we need to be careful that we only handle what we want to | |
1738 | * handle. | |
1739 | */ | |
0f239f4c DV |
1740 | |
1741 | /* fifo underruns are filterered in the underrun handler. */ | |
1742 | mask = PIPE_FIFO_UNDERRUN_STATUS; | |
bbb5eebf DV |
1743 | |
1744 | switch (pipe) { | |
1745 | case PIPE_A: | |
1746 | iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; | |
1747 | break; | |
1748 | case PIPE_B: | |
1749 | iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
1750 | break; | |
3278f67f VS |
1751 | case PIPE_C: |
1752 | iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
1753 | break; | |
bbb5eebf DV |
1754 | } |
1755 | if (iir & iir_bit) | |
1756 | mask |= dev_priv->pipestat_irq_mask[pipe]; | |
1757 | ||
1758 | if (!mask) | |
91d181dd ID |
1759 | continue; |
1760 | ||
1761 | reg = PIPESTAT(pipe); | |
bbb5eebf DV |
1762 | mask |= PIPESTAT_INT_ENABLE_MASK; |
1763 | pipe_stats[pipe] = I915_READ(reg) & mask; | |
c1874ed7 ID |
1764 | |
1765 | /* | |
1766 | * Clear the PIPE*STAT regs before the IIR | |
1767 | */ | |
91d181dd ID |
1768 | if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS | |
1769 | PIPESTAT_INT_STATUS_MASK)) | |
c1874ed7 ID |
1770 | I915_WRITE(reg, pipe_stats[pipe]); |
1771 | } | |
58ead0d7 | 1772 | spin_unlock(&dev_priv->irq_lock); |
2ecb8ca4 VS |
1773 | } |
1774 | ||
91d14251 | 1775 | static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv, |
2ecb8ca4 VS |
1776 | u32 pipe_stats[I915_MAX_PIPES]) |
1777 | { | |
2ecb8ca4 | 1778 | enum pipe pipe; |
c1874ed7 | 1779 | |
055e393f | 1780 | for_each_pipe(dev_priv, pipe) { |
5a21b665 DV |
1781 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
1782 | intel_pipe_handle_vblank(dev_priv, pipe)) | |
1783 | intel_check_page_flip(dev_priv, pipe); | |
c1874ed7 | 1784 | |
5251f04e | 1785 | if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) |
51cbaf01 | 1786 | intel_finish_page_flip_cs(dev_priv, pipe); |
c1874ed7 ID |
1787 | |
1788 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
91d14251 | 1789 | i9xx_pipe_crc_irq_handler(dev_priv, pipe); |
c1874ed7 | 1790 | |
1f7247c0 DV |
1791 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
1792 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
c1874ed7 ID |
1793 | } |
1794 | ||
1795 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) | |
91d14251 | 1796 | gmbus_irq_handler(dev_priv); |
c1874ed7 ID |
1797 | } |
1798 | ||
1ae3c34c | 1799 | static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv) |
16c6c56b | 1800 | { |
16c6c56b VS |
1801 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
1802 | ||
1ae3c34c VS |
1803 | if (hotplug_status) |
1804 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
16c6c56b | 1805 | |
1ae3c34c VS |
1806 | return hotplug_status; |
1807 | } | |
1808 | ||
91d14251 | 1809 | static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv, |
1ae3c34c VS |
1810 | u32 hotplug_status) |
1811 | { | |
1812 | u32 pin_mask = 0, long_mask = 0; | |
16c6c56b | 1813 | |
91d14251 TU |
1814 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
1815 | IS_CHERRYVIEW(dev_priv)) { | |
0d2e4297 | 1816 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; |
16c6c56b | 1817 | |
58f2cf24 VS |
1818 | if (hotplug_trigger) { |
1819 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
1820 | hotplug_trigger, hpd_status_g4x, | |
1821 | i9xx_port_hotplug_long_detect); | |
1822 | ||
91d14251 | 1823 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
58f2cf24 | 1824 | } |
369712e8 JN |
1825 | |
1826 | if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) | |
91d14251 | 1827 | dp_aux_irq_handler(dev_priv); |
0d2e4297 JN |
1828 | } else { |
1829 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; | |
16c6c56b | 1830 | |
58f2cf24 VS |
1831 | if (hotplug_trigger) { |
1832 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
44cc6c08 | 1833 | hotplug_trigger, hpd_status_i915, |
58f2cf24 | 1834 | i9xx_port_hotplug_long_detect); |
91d14251 | 1835 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
58f2cf24 | 1836 | } |
3ff60f89 | 1837 | } |
16c6c56b VS |
1838 | } |
1839 | ||
ff1f525e | 1840 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
7e231dbe | 1841 | { |
45a83f84 | 1842 | struct drm_device *dev = arg; |
fac5e23e | 1843 | struct drm_i915_private *dev_priv = to_i915(dev); |
7e231dbe | 1844 | irqreturn_t ret = IRQ_NONE; |
7e231dbe | 1845 | |
2dd2a883 ID |
1846 | if (!intel_irqs_enabled(dev_priv)) |
1847 | return IRQ_NONE; | |
1848 | ||
1f814dac ID |
1849 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
1850 | disable_rpm_wakeref_asserts(dev_priv); | |
1851 | ||
1e1cace9 | 1852 | do { |
6e814800 | 1853 | u32 iir, gt_iir, pm_iir; |
2ecb8ca4 | 1854 | u32 pipe_stats[I915_MAX_PIPES] = {}; |
1ae3c34c | 1855 | u32 hotplug_status = 0; |
a5e485a9 | 1856 | u32 ier = 0; |
3ff60f89 | 1857 | |
7e231dbe JB |
1858 | gt_iir = I915_READ(GTIIR); |
1859 | pm_iir = I915_READ(GEN6_PMIIR); | |
3ff60f89 | 1860 | iir = I915_READ(VLV_IIR); |
7e231dbe JB |
1861 | |
1862 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) | |
1e1cace9 | 1863 | break; |
7e231dbe JB |
1864 | |
1865 | ret = IRQ_HANDLED; | |
1866 | ||
a5e485a9 VS |
1867 | /* |
1868 | * Theory on interrupt generation, based on empirical evidence: | |
1869 | * | |
1870 | * x = ((VLV_IIR & VLV_IER) || | |
1871 | * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) && | |
1872 | * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE))); | |
1873 | * | |
1874 | * A CPU interrupt will only be raised when 'x' has a 0->1 edge. | |
1875 | * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to | |
1876 | * guarantee the CPU interrupt will be raised again even if we | |
1877 | * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR | |
1878 | * bits this time around. | |
1879 | */ | |
4a0a0202 | 1880 | I915_WRITE(VLV_MASTER_IER, 0); |
a5e485a9 VS |
1881 | ier = I915_READ(VLV_IER); |
1882 | I915_WRITE(VLV_IER, 0); | |
4a0a0202 VS |
1883 | |
1884 | if (gt_iir) | |
1885 | I915_WRITE(GTIIR, gt_iir); | |
1886 | if (pm_iir) | |
1887 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
1888 | ||
7ce4d1f2 | 1889 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
1ae3c34c | 1890 | hotplug_status = i9xx_hpd_irq_ack(dev_priv); |
7ce4d1f2 | 1891 | |
3ff60f89 OM |
1892 | /* Call regardless, as some status bits might not be |
1893 | * signalled in iir */ | |
91d14251 | 1894 | valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats); |
7ce4d1f2 VS |
1895 | |
1896 | /* | |
1897 | * VLV_IIR is single buffered, and reflects the level | |
1898 | * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last. | |
1899 | */ | |
1900 | if (iir) | |
1901 | I915_WRITE(VLV_IIR, iir); | |
4a0a0202 | 1902 | |
a5e485a9 | 1903 | I915_WRITE(VLV_IER, ier); |
4a0a0202 VS |
1904 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); |
1905 | POSTING_READ(VLV_MASTER_IER); | |
1ae3c34c | 1906 | |
52894874 | 1907 | if (gt_iir) |
261e40b8 | 1908 | snb_gt_irq_handler(dev_priv, gt_iir); |
52894874 VS |
1909 | if (pm_iir) |
1910 | gen6_rps_irq_handler(dev_priv, pm_iir); | |
1911 | ||
1ae3c34c | 1912 | if (hotplug_status) |
91d14251 | 1913 | i9xx_hpd_irq_handler(dev_priv, hotplug_status); |
2ecb8ca4 | 1914 | |
91d14251 | 1915 | valleyview_pipestat_irq_handler(dev_priv, pipe_stats); |
1e1cace9 | 1916 | } while (0); |
7e231dbe | 1917 | |
1f814dac ID |
1918 | enable_rpm_wakeref_asserts(dev_priv); |
1919 | ||
7e231dbe JB |
1920 | return ret; |
1921 | } | |
1922 | ||
43f328d7 VS |
1923 | static irqreturn_t cherryview_irq_handler(int irq, void *arg) |
1924 | { | |
45a83f84 | 1925 | struct drm_device *dev = arg; |
fac5e23e | 1926 | struct drm_i915_private *dev_priv = to_i915(dev); |
43f328d7 | 1927 | irqreturn_t ret = IRQ_NONE; |
43f328d7 | 1928 | |
2dd2a883 ID |
1929 | if (!intel_irqs_enabled(dev_priv)) |
1930 | return IRQ_NONE; | |
1931 | ||
1f814dac ID |
1932 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
1933 | disable_rpm_wakeref_asserts(dev_priv); | |
1934 | ||
579de73b | 1935 | do { |
6e814800 | 1936 | u32 master_ctl, iir; |
e30e251a | 1937 | u32 gt_iir[4] = {}; |
2ecb8ca4 | 1938 | u32 pipe_stats[I915_MAX_PIPES] = {}; |
1ae3c34c | 1939 | u32 hotplug_status = 0; |
a5e485a9 VS |
1940 | u32 ier = 0; |
1941 | ||
8e5fd599 VS |
1942 | master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; |
1943 | iir = I915_READ(VLV_IIR); | |
43f328d7 | 1944 | |
8e5fd599 VS |
1945 | if (master_ctl == 0 && iir == 0) |
1946 | break; | |
43f328d7 | 1947 | |
27b6c122 OM |
1948 | ret = IRQ_HANDLED; |
1949 | ||
a5e485a9 VS |
1950 | /* |
1951 | * Theory on interrupt generation, based on empirical evidence: | |
1952 | * | |
1953 | * x = ((VLV_IIR & VLV_IER) || | |
1954 | * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) && | |
1955 | * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL))); | |
1956 | * | |
1957 | * A CPU interrupt will only be raised when 'x' has a 0->1 edge. | |
1958 | * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to | |
1959 | * guarantee the CPU interrupt will be raised again even if we | |
1960 | * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL | |
1961 | * bits this time around. | |
1962 | */ | |
8e5fd599 | 1963 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
a5e485a9 VS |
1964 | ier = I915_READ(VLV_IER); |
1965 | I915_WRITE(VLV_IER, 0); | |
43f328d7 | 1966 | |
e30e251a | 1967 | gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir); |
43f328d7 | 1968 | |
7ce4d1f2 | 1969 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
1ae3c34c | 1970 | hotplug_status = i9xx_hpd_irq_ack(dev_priv); |
7ce4d1f2 | 1971 | |
27b6c122 OM |
1972 | /* Call regardless, as some status bits might not be |
1973 | * signalled in iir */ | |
91d14251 | 1974 | valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats); |
43f328d7 | 1975 | |
7ce4d1f2 VS |
1976 | /* |
1977 | * VLV_IIR is single buffered, and reflects the level | |
1978 | * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last. | |
1979 | */ | |
1980 | if (iir) | |
1981 | I915_WRITE(VLV_IIR, iir); | |
1982 | ||
a5e485a9 | 1983 | I915_WRITE(VLV_IER, ier); |
e5328c43 | 1984 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
8e5fd599 | 1985 | POSTING_READ(GEN8_MASTER_IRQ); |
1ae3c34c | 1986 | |
e30e251a VS |
1987 | gen8_gt_irq_handler(dev_priv, gt_iir); |
1988 | ||
1ae3c34c | 1989 | if (hotplug_status) |
91d14251 | 1990 | i9xx_hpd_irq_handler(dev_priv, hotplug_status); |
2ecb8ca4 | 1991 | |
91d14251 | 1992 | valleyview_pipestat_irq_handler(dev_priv, pipe_stats); |
579de73b | 1993 | } while (0); |
3278f67f | 1994 | |
1f814dac ID |
1995 | enable_rpm_wakeref_asserts(dev_priv); |
1996 | ||
43f328d7 VS |
1997 | return ret; |
1998 | } | |
1999 | ||
91d14251 TU |
2000 | static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv, |
2001 | u32 hotplug_trigger, | |
40e56410 VS |
2002 | const u32 hpd[HPD_NUM_PINS]) |
2003 | { | |
40e56410 VS |
2004 | u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; |
2005 | ||
6a39d7c9 JN |
2006 | /* |
2007 | * Somehow the PCH doesn't seem to really ack the interrupt to the CPU | |
2008 | * unless we touch the hotplug register, even if hotplug_trigger is | |
2009 | * zero. Not acking leads to "The master control interrupt lied (SDE)!" | |
2010 | * errors. | |
2011 | */ | |
40e56410 | 2012 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); |
6a39d7c9 JN |
2013 | if (!hotplug_trigger) { |
2014 | u32 mask = PORTA_HOTPLUG_STATUS_MASK | | |
2015 | PORTD_HOTPLUG_STATUS_MASK | | |
2016 | PORTC_HOTPLUG_STATUS_MASK | | |
2017 | PORTB_HOTPLUG_STATUS_MASK; | |
2018 | dig_hotplug_reg &= ~mask; | |
2019 | } | |
2020 | ||
40e56410 | 2021 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); |
6a39d7c9 JN |
2022 | if (!hotplug_trigger) |
2023 | return; | |
40e56410 VS |
2024 | |
2025 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
2026 | dig_hotplug_reg, hpd, | |
2027 | pch_port_hotplug_long_detect); | |
2028 | ||
91d14251 | 2029 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
40e56410 VS |
2030 | } |
2031 | ||
91d14251 | 2032 | static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) |
776ad806 | 2033 | { |
9db4a9c7 | 2034 | int pipe; |
b543fb04 | 2035 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; |
13cf5504 | 2036 | |
91d14251 | 2037 | ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx); |
91d131d2 | 2038 | |
cfc33bf7 VS |
2039 | if (pch_iir & SDE_AUDIO_POWER_MASK) { |
2040 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> | |
2041 | SDE_AUDIO_POWER_SHIFT); | |
776ad806 | 2042 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
cfc33bf7 VS |
2043 | port_name(port)); |
2044 | } | |
776ad806 | 2045 | |
ce99c256 | 2046 | if (pch_iir & SDE_AUX_MASK) |
91d14251 | 2047 | dp_aux_irq_handler(dev_priv); |
ce99c256 | 2048 | |
776ad806 | 2049 | if (pch_iir & SDE_GMBUS) |
91d14251 | 2050 | gmbus_irq_handler(dev_priv); |
776ad806 JB |
2051 | |
2052 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
2053 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
2054 | ||
2055 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
2056 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
2057 | ||
2058 | if (pch_iir & SDE_POISON) | |
2059 | DRM_ERROR("PCH poison interrupt\n"); | |
2060 | ||
9db4a9c7 | 2061 | if (pch_iir & SDE_FDI_MASK) |
055e393f | 2062 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
2063 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
2064 | pipe_name(pipe), | |
2065 | I915_READ(FDI_RX_IIR(pipe))); | |
776ad806 JB |
2066 | |
2067 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
2068 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
2069 | ||
2070 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
2071 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
2072 | ||
776ad806 | 2073 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
1f7247c0 | 2074 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); |
8664281b PZ |
2075 | |
2076 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
1f7247c0 | 2077 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); |
8664281b PZ |
2078 | } |
2079 | ||
91d14251 | 2080 | static void ivb_err_int_handler(struct drm_i915_private *dev_priv) |
8664281b | 2081 | { |
8664281b | 2082 | u32 err_int = I915_READ(GEN7_ERR_INT); |
5a69b89f | 2083 | enum pipe pipe; |
8664281b | 2084 | |
de032bf4 PZ |
2085 | if (err_int & ERR_INT_POISON) |
2086 | DRM_ERROR("Poison interrupt\n"); | |
2087 | ||
055e393f | 2088 | for_each_pipe(dev_priv, pipe) { |
1f7247c0 DV |
2089 | if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) |
2090 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
8bf1e9f1 | 2091 | |
5a69b89f | 2092 | if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { |
91d14251 TU |
2093 | if (IS_IVYBRIDGE(dev_priv)) |
2094 | ivb_pipe_crc_irq_handler(dev_priv, pipe); | |
5a69b89f | 2095 | else |
91d14251 | 2096 | hsw_pipe_crc_irq_handler(dev_priv, pipe); |
5a69b89f DV |
2097 | } |
2098 | } | |
8bf1e9f1 | 2099 | |
8664281b PZ |
2100 | I915_WRITE(GEN7_ERR_INT, err_int); |
2101 | } | |
2102 | ||
91d14251 | 2103 | static void cpt_serr_int_handler(struct drm_i915_private *dev_priv) |
8664281b | 2104 | { |
8664281b PZ |
2105 | u32 serr_int = I915_READ(SERR_INT); |
2106 | ||
de032bf4 PZ |
2107 | if (serr_int & SERR_INT_POISON) |
2108 | DRM_ERROR("PCH poison interrupt\n"); | |
2109 | ||
8664281b | 2110 | if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) |
1f7247c0 | 2111 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); |
8664281b PZ |
2112 | |
2113 | if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) | |
1f7247c0 | 2114 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); |
8664281b PZ |
2115 | |
2116 | if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) | |
1f7247c0 | 2117 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C); |
8664281b PZ |
2118 | |
2119 | I915_WRITE(SERR_INT, serr_int); | |
776ad806 JB |
2120 | } |
2121 | ||
91d14251 | 2122 | static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) |
23e81d69 | 2123 | { |
23e81d69 | 2124 | int pipe; |
6dbf30ce | 2125 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; |
13cf5504 | 2126 | |
91d14251 | 2127 | ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt); |
91d131d2 | 2128 | |
cfc33bf7 VS |
2129 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { |
2130 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> | |
2131 | SDE_AUDIO_POWER_SHIFT_CPT); | |
2132 | DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", | |
2133 | port_name(port)); | |
2134 | } | |
23e81d69 AJ |
2135 | |
2136 | if (pch_iir & SDE_AUX_MASK_CPT) | |
91d14251 | 2137 | dp_aux_irq_handler(dev_priv); |
23e81d69 AJ |
2138 | |
2139 | if (pch_iir & SDE_GMBUS_CPT) | |
91d14251 | 2140 | gmbus_irq_handler(dev_priv); |
23e81d69 AJ |
2141 | |
2142 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) | |
2143 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); | |
2144 | ||
2145 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) | |
2146 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); | |
2147 | ||
2148 | if (pch_iir & SDE_FDI_MASK_CPT) | |
055e393f | 2149 | for_each_pipe(dev_priv, pipe) |
23e81d69 AJ |
2150 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
2151 | pipe_name(pipe), | |
2152 | I915_READ(FDI_RX_IIR(pipe))); | |
8664281b PZ |
2153 | |
2154 | if (pch_iir & SDE_ERROR_CPT) | |
91d14251 | 2155 | cpt_serr_int_handler(dev_priv); |
23e81d69 AJ |
2156 | } |
2157 | ||
91d14251 | 2158 | static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) |
6dbf30ce | 2159 | { |
6dbf30ce VS |
2160 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT & |
2161 | ~SDE_PORTE_HOTPLUG_SPT; | |
2162 | u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT; | |
2163 | u32 pin_mask = 0, long_mask = 0; | |
2164 | ||
2165 | if (hotplug_trigger) { | |
2166 | u32 dig_hotplug_reg; | |
2167 | ||
2168 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); | |
2169 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
2170 | ||
2171 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
2172 | dig_hotplug_reg, hpd_spt, | |
74c0b395 | 2173 | spt_port_hotplug_long_detect); |
6dbf30ce VS |
2174 | } |
2175 | ||
2176 | if (hotplug2_trigger) { | |
2177 | u32 dig_hotplug_reg; | |
2178 | ||
2179 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2); | |
2180 | I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg); | |
2181 | ||
2182 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger, | |
2183 | dig_hotplug_reg, hpd_spt, | |
2184 | spt_port_hotplug2_long_detect); | |
2185 | } | |
2186 | ||
2187 | if (pin_mask) | |
91d14251 | 2188 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
6dbf30ce VS |
2189 | |
2190 | if (pch_iir & SDE_GMBUS_CPT) | |
91d14251 | 2191 | gmbus_irq_handler(dev_priv); |
6dbf30ce VS |
2192 | } |
2193 | ||
91d14251 TU |
2194 | static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv, |
2195 | u32 hotplug_trigger, | |
40e56410 VS |
2196 | const u32 hpd[HPD_NUM_PINS]) |
2197 | { | |
40e56410 VS |
2198 | u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; |
2199 | ||
2200 | dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL); | |
2201 | I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg); | |
2202 | ||
2203 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
2204 | dig_hotplug_reg, hpd, | |
2205 | ilk_port_hotplug_long_detect); | |
2206 | ||
91d14251 | 2207 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
40e56410 VS |
2208 | } |
2209 | ||
91d14251 TU |
2210 | static void ilk_display_irq_handler(struct drm_i915_private *dev_priv, |
2211 | u32 de_iir) | |
c008bc6e | 2212 | { |
40da17c2 | 2213 | enum pipe pipe; |
e4ce95aa VS |
2214 | u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG; |
2215 | ||
40e56410 | 2216 | if (hotplug_trigger) |
91d14251 | 2217 | ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk); |
c008bc6e PZ |
2218 | |
2219 | if (de_iir & DE_AUX_CHANNEL_A) | |
91d14251 | 2220 | dp_aux_irq_handler(dev_priv); |
c008bc6e PZ |
2221 | |
2222 | if (de_iir & DE_GSE) | |
91d14251 | 2223 | intel_opregion_asle_intr(dev_priv); |
c008bc6e | 2224 | |
c008bc6e PZ |
2225 | if (de_iir & DE_POISON) |
2226 | DRM_ERROR("Poison interrupt\n"); | |
2227 | ||
055e393f | 2228 | for_each_pipe(dev_priv, pipe) { |
5a21b665 DV |
2229 | if (de_iir & DE_PIPE_VBLANK(pipe) && |
2230 | intel_pipe_handle_vblank(dev_priv, pipe)) | |
2231 | intel_check_page_flip(dev_priv, pipe); | |
5b3a856b | 2232 | |
40da17c2 | 2233 | if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) |
1f7247c0 | 2234 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); |
5b3a856b | 2235 | |
40da17c2 | 2236 | if (de_iir & DE_PIPE_CRC_DONE(pipe)) |
91d14251 | 2237 | i9xx_pipe_crc_irq_handler(dev_priv, pipe); |
c008bc6e | 2238 | |
40da17c2 | 2239 | /* plane/pipes map 1:1 on ilk+ */ |
5251f04e | 2240 | if (de_iir & DE_PLANE_FLIP_DONE(pipe)) |
51cbaf01 | 2241 | intel_finish_page_flip_cs(dev_priv, pipe); |
c008bc6e PZ |
2242 | } |
2243 | ||
2244 | /* check event from PCH */ | |
2245 | if (de_iir & DE_PCH_EVENT) { | |
2246 | u32 pch_iir = I915_READ(SDEIIR); | |
2247 | ||
91d14251 TU |
2248 | if (HAS_PCH_CPT(dev_priv)) |
2249 | cpt_irq_handler(dev_priv, pch_iir); | |
c008bc6e | 2250 | else |
91d14251 | 2251 | ibx_irq_handler(dev_priv, pch_iir); |
c008bc6e PZ |
2252 | |
2253 | /* should clear PCH hotplug event before clear CPU irq */ | |
2254 | I915_WRITE(SDEIIR, pch_iir); | |
2255 | } | |
2256 | ||
91d14251 TU |
2257 | if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT) |
2258 | ironlake_rps_change_irq_handler(dev_priv); | |
c008bc6e PZ |
2259 | } |
2260 | ||
91d14251 TU |
2261 | static void ivb_display_irq_handler(struct drm_i915_private *dev_priv, |
2262 | u32 de_iir) | |
9719fb98 | 2263 | { |
07d27e20 | 2264 | enum pipe pipe; |
23bb4cb5 VS |
2265 | u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB; |
2266 | ||
40e56410 | 2267 | if (hotplug_trigger) |
91d14251 | 2268 | ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb); |
9719fb98 PZ |
2269 | |
2270 | if (de_iir & DE_ERR_INT_IVB) | |
91d14251 | 2271 | ivb_err_int_handler(dev_priv); |
9719fb98 PZ |
2272 | |
2273 | if (de_iir & DE_AUX_CHANNEL_A_IVB) | |
91d14251 | 2274 | dp_aux_irq_handler(dev_priv); |
9719fb98 PZ |
2275 | |
2276 | if (de_iir & DE_GSE_IVB) | |
91d14251 | 2277 | intel_opregion_asle_intr(dev_priv); |
9719fb98 | 2278 | |
055e393f | 2279 | for_each_pipe(dev_priv, pipe) { |
5a21b665 DV |
2280 | if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) && |
2281 | intel_pipe_handle_vblank(dev_priv, pipe)) | |
2282 | intel_check_page_flip(dev_priv, pipe); | |
40da17c2 DV |
2283 | |
2284 | /* plane/pipes map 1:1 on ilk+ */ | |
5251f04e | 2285 | if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) |
51cbaf01 | 2286 | intel_finish_page_flip_cs(dev_priv, pipe); |
9719fb98 PZ |
2287 | } |
2288 | ||
2289 | /* check event from PCH */ | |
91d14251 | 2290 | if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) { |
9719fb98 PZ |
2291 | u32 pch_iir = I915_READ(SDEIIR); |
2292 | ||
91d14251 | 2293 | cpt_irq_handler(dev_priv, pch_iir); |
9719fb98 PZ |
2294 | |
2295 | /* clear PCH hotplug event before clear CPU irq */ | |
2296 | I915_WRITE(SDEIIR, pch_iir); | |
2297 | } | |
2298 | } | |
2299 | ||
72c90f62 OM |
2300 | /* |
2301 | * To handle irqs with the minimum potential races with fresh interrupts, we: | |
2302 | * 1 - Disable Master Interrupt Control. | |
2303 | * 2 - Find the source(s) of the interrupt. | |
2304 | * 3 - Clear the Interrupt Identity bits (IIR). | |
2305 | * 4 - Process the interrupt(s) that had bits set in the IIRs. | |
2306 | * 5 - Re-enable Master Interrupt Control. | |
2307 | */ | |
f1af8fc1 | 2308 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
b1f14ad0 | 2309 | { |
45a83f84 | 2310 | struct drm_device *dev = arg; |
fac5e23e | 2311 | struct drm_i915_private *dev_priv = to_i915(dev); |
f1af8fc1 | 2312 | u32 de_iir, gt_iir, de_ier, sde_ier = 0; |
0e43406b | 2313 | irqreturn_t ret = IRQ_NONE; |
b1f14ad0 | 2314 | |
2dd2a883 ID |
2315 | if (!intel_irqs_enabled(dev_priv)) |
2316 | return IRQ_NONE; | |
2317 | ||
1f814dac ID |
2318 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
2319 | disable_rpm_wakeref_asserts(dev_priv); | |
2320 | ||
b1f14ad0 JB |
2321 | /* disable master interrupt before clearing iir */ |
2322 | de_ier = I915_READ(DEIER); | |
2323 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
23a78516 | 2324 | POSTING_READ(DEIER); |
b1f14ad0 | 2325 | |
44498aea PZ |
2326 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
2327 | * interrupts will will be stored on its back queue, and then we'll be | |
2328 | * able to process them after we restore SDEIER (as soon as we restore | |
2329 | * it, we'll get an interrupt if SDEIIR still has something to process | |
2330 | * due to its back queue). */ | |
91d14251 | 2331 | if (!HAS_PCH_NOP(dev_priv)) { |
ab5c608b BW |
2332 | sde_ier = I915_READ(SDEIER); |
2333 | I915_WRITE(SDEIER, 0); | |
2334 | POSTING_READ(SDEIER); | |
2335 | } | |
44498aea | 2336 | |
72c90f62 OM |
2337 | /* Find, clear, then process each source of interrupt */ |
2338 | ||
b1f14ad0 | 2339 | gt_iir = I915_READ(GTIIR); |
0e43406b | 2340 | if (gt_iir) { |
72c90f62 OM |
2341 | I915_WRITE(GTIIR, gt_iir); |
2342 | ret = IRQ_HANDLED; | |
91d14251 | 2343 | if (INTEL_GEN(dev_priv) >= 6) |
261e40b8 | 2344 | snb_gt_irq_handler(dev_priv, gt_iir); |
d8fc8a47 | 2345 | else |
261e40b8 | 2346 | ilk_gt_irq_handler(dev_priv, gt_iir); |
b1f14ad0 JB |
2347 | } |
2348 | ||
0e43406b CW |
2349 | de_iir = I915_READ(DEIIR); |
2350 | if (de_iir) { | |
72c90f62 OM |
2351 | I915_WRITE(DEIIR, de_iir); |
2352 | ret = IRQ_HANDLED; | |
91d14251 TU |
2353 | if (INTEL_GEN(dev_priv) >= 7) |
2354 | ivb_display_irq_handler(dev_priv, de_iir); | |
f1af8fc1 | 2355 | else |
91d14251 | 2356 | ilk_display_irq_handler(dev_priv, de_iir); |
b1f14ad0 JB |
2357 | } |
2358 | ||
91d14251 | 2359 | if (INTEL_GEN(dev_priv) >= 6) { |
f1af8fc1 PZ |
2360 | u32 pm_iir = I915_READ(GEN6_PMIIR); |
2361 | if (pm_iir) { | |
f1af8fc1 PZ |
2362 | I915_WRITE(GEN6_PMIIR, pm_iir); |
2363 | ret = IRQ_HANDLED; | |
72c90f62 | 2364 | gen6_rps_irq_handler(dev_priv, pm_iir); |
f1af8fc1 | 2365 | } |
0e43406b | 2366 | } |
b1f14ad0 | 2367 | |
b1f14ad0 JB |
2368 | I915_WRITE(DEIER, de_ier); |
2369 | POSTING_READ(DEIER); | |
91d14251 | 2370 | if (!HAS_PCH_NOP(dev_priv)) { |
ab5c608b BW |
2371 | I915_WRITE(SDEIER, sde_ier); |
2372 | POSTING_READ(SDEIER); | |
2373 | } | |
b1f14ad0 | 2374 | |
1f814dac ID |
2375 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
2376 | enable_rpm_wakeref_asserts(dev_priv); | |
2377 | ||
b1f14ad0 JB |
2378 | return ret; |
2379 | } | |
2380 | ||
91d14251 TU |
2381 | static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv, |
2382 | u32 hotplug_trigger, | |
40e56410 | 2383 | const u32 hpd[HPD_NUM_PINS]) |
d04a492d | 2384 | { |
cebd87a0 | 2385 | u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; |
d04a492d | 2386 | |
a52bb15b VS |
2387 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); |
2388 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
d04a492d | 2389 | |
cebd87a0 | 2390 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, |
40e56410 | 2391 | dig_hotplug_reg, hpd, |
cebd87a0 | 2392 | bxt_port_hotplug_long_detect); |
40e56410 | 2393 | |
91d14251 | 2394 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
d04a492d SS |
2395 | } |
2396 | ||
f11a0f46 TU |
2397 | static irqreturn_t |
2398 | gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) | |
abd58f01 | 2399 | { |
abd58f01 | 2400 | irqreturn_t ret = IRQ_NONE; |
f11a0f46 | 2401 | u32 iir; |
c42664cc | 2402 | enum pipe pipe; |
88e04703 | 2403 | |
abd58f01 | 2404 | if (master_ctl & GEN8_DE_MISC_IRQ) { |
e32192e1 TU |
2405 | iir = I915_READ(GEN8_DE_MISC_IIR); |
2406 | if (iir) { | |
2407 | I915_WRITE(GEN8_DE_MISC_IIR, iir); | |
abd58f01 | 2408 | ret = IRQ_HANDLED; |
e32192e1 | 2409 | if (iir & GEN8_DE_MISC_GSE) |
91d14251 | 2410 | intel_opregion_asle_intr(dev_priv); |
38cc46d7 OM |
2411 | else |
2412 | DRM_ERROR("Unexpected DE Misc interrupt\n"); | |
abd58f01 | 2413 | } |
38cc46d7 OM |
2414 | else |
2415 | DRM_ERROR("The master control interrupt lied (DE MISC)!\n"); | |
abd58f01 BW |
2416 | } |
2417 | ||
6d766f02 | 2418 | if (master_ctl & GEN8_DE_PORT_IRQ) { |
e32192e1 TU |
2419 | iir = I915_READ(GEN8_DE_PORT_IIR); |
2420 | if (iir) { | |
2421 | u32 tmp_mask; | |
d04a492d | 2422 | bool found = false; |
cebd87a0 | 2423 | |
e32192e1 | 2424 | I915_WRITE(GEN8_DE_PORT_IIR, iir); |
6d766f02 | 2425 | ret = IRQ_HANDLED; |
88e04703 | 2426 | |
e32192e1 TU |
2427 | tmp_mask = GEN8_AUX_CHANNEL_A; |
2428 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2429 | tmp_mask |= GEN9_AUX_CHANNEL_B | | |
2430 | GEN9_AUX_CHANNEL_C | | |
2431 | GEN9_AUX_CHANNEL_D; | |
2432 | ||
2433 | if (iir & tmp_mask) { | |
91d14251 | 2434 | dp_aux_irq_handler(dev_priv); |
d04a492d SS |
2435 | found = true; |
2436 | } | |
2437 | ||
e32192e1 TU |
2438 | if (IS_BROXTON(dev_priv)) { |
2439 | tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK; | |
2440 | if (tmp_mask) { | |
91d14251 TU |
2441 | bxt_hpd_irq_handler(dev_priv, tmp_mask, |
2442 | hpd_bxt); | |
e32192e1 TU |
2443 | found = true; |
2444 | } | |
2445 | } else if (IS_BROADWELL(dev_priv)) { | |
2446 | tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG; | |
2447 | if (tmp_mask) { | |
91d14251 TU |
2448 | ilk_hpd_irq_handler(dev_priv, |
2449 | tmp_mask, hpd_bdw); | |
e32192e1 TU |
2450 | found = true; |
2451 | } | |
d04a492d SS |
2452 | } |
2453 | ||
91d14251 TU |
2454 | if (IS_BROXTON(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) { |
2455 | gmbus_irq_handler(dev_priv); | |
9e63743e SS |
2456 | found = true; |
2457 | } | |
2458 | ||
d04a492d | 2459 | if (!found) |
38cc46d7 | 2460 | DRM_ERROR("Unexpected DE Port interrupt\n"); |
6d766f02 | 2461 | } |
38cc46d7 OM |
2462 | else |
2463 | DRM_ERROR("The master control interrupt lied (DE PORT)!\n"); | |
6d766f02 DV |
2464 | } |
2465 | ||
055e393f | 2466 | for_each_pipe(dev_priv, pipe) { |
e32192e1 | 2467 | u32 flip_done, fault_errors; |
abd58f01 | 2468 | |
c42664cc DV |
2469 | if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) |
2470 | continue; | |
abd58f01 | 2471 | |
e32192e1 TU |
2472 | iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); |
2473 | if (!iir) { | |
2474 | DRM_ERROR("The master control interrupt lied (DE PIPE)!\n"); | |
2475 | continue; | |
2476 | } | |
770de83d | 2477 | |
e32192e1 TU |
2478 | ret = IRQ_HANDLED; |
2479 | I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir); | |
38cc46d7 | 2480 | |
5a21b665 DV |
2481 | if (iir & GEN8_PIPE_VBLANK && |
2482 | intel_pipe_handle_vblank(dev_priv, pipe)) | |
2483 | intel_check_page_flip(dev_priv, pipe); | |
770de83d | 2484 | |
e32192e1 TU |
2485 | flip_done = iir; |
2486 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2487 | flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE; | |
2488 | else | |
2489 | flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE; | |
38cc46d7 | 2490 | |
5251f04e | 2491 | if (flip_done) |
51cbaf01 | 2492 | intel_finish_page_flip_cs(dev_priv, pipe); |
38cc46d7 | 2493 | |
e32192e1 | 2494 | if (iir & GEN8_PIPE_CDCLK_CRC_DONE) |
91d14251 | 2495 | hsw_pipe_crc_irq_handler(dev_priv, pipe); |
38cc46d7 | 2496 | |
e32192e1 TU |
2497 | if (iir & GEN8_PIPE_FIFO_UNDERRUN) |
2498 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
770de83d | 2499 | |
e32192e1 TU |
2500 | fault_errors = iir; |
2501 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2502 | fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS; | |
2503 | else | |
2504 | fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
770de83d | 2505 | |
e32192e1 | 2506 | if (fault_errors) |
1353ec38 | 2507 | DRM_ERROR("Fault errors on pipe %c: 0x%08x\n", |
e32192e1 TU |
2508 | pipe_name(pipe), |
2509 | fault_errors); | |
abd58f01 BW |
2510 | } |
2511 | ||
91d14251 | 2512 | if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) && |
266ea3d9 | 2513 | master_ctl & GEN8_DE_PCH_IRQ) { |
92d03a80 DV |
2514 | /* |
2515 | * FIXME(BDW): Assume for now that the new interrupt handling | |
2516 | * scheme also closed the SDE interrupt handling race we've seen | |
2517 | * on older pch-split platforms. But this needs testing. | |
2518 | */ | |
e32192e1 TU |
2519 | iir = I915_READ(SDEIIR); |
2520 | if (iir) { | |
2521 | I915_WRITE(SDEIIR, iir); | |
92d03a80 | 2522 | ret = IRQ_HANDLED; |
6dbf30ce | 2523 | |
22dea0be | 2524 | if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv)) |
91d14251 | 2525 | spt_irq_handler(dev_priv, iir); |
6dbf30ce | 2526 | else |
91d14251 | 2527 | cpt_irq_handler(dev_priv, iir); |
2dfb0b81 JN |
2528 | } else { |
2529 | /* | |
2530 | * Like on previous PCH there seems to be something | |
2531 | * fishy going on with forwarding PCH interrupts. | |
2532 | */ | |
2533 | DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n"); | |
2534 | } | |
92d03a80 DV |
2535 | } |
2536 | ||
f11a0f46 TU |
2537 | return ret; |
2538 | } | |
2539 | ||
2540 | static irqreturn_t gen8_irq_handler(int irq, void *arg) | |
2541 | { | |
2542 | struct drm_device *dev = arg; | |
fac5e23e | 2543 | struct drm_i915_private *dev_priv = to_i915(dev); |
f11a0f46 | 2544 | u32 master_ctl; |
e30e251a | 2545 | u32 gt_iir[4] = {}; |
f11a0f46 TU |
2546 | irqreturn_t ret; |
2547 | ||
2548 | if (!intel_irqs_enabled(dev_priv)) | |
2549 | return IRQ_NONE; | |
2550 | ||
2551 | master_ctl = I915_READ_FW(GEN8_MASTER_IRQ); | |
2552 | master_ctl &= ~GEN8_MASTER_IRQ_CONTROL; | |
2553 | if (!master_ctl) | |
2554 | return IRQ_NONE; | |
2555 | ||
2556 | I915_WRITE_FW(GEN8_MASTER_IRQ, 0); | |
2557 | ||
2558 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ | |
2559 | disable_rpm_wakeref_asserts(dev_priv); | |
2560 | ||
2561 | /* Find, clear, then process each source of interrupt */ | |
e30e251a VS |
2562 | ret = gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir); |
2563 | gen8_gt_irq_handler(dev_priv, gt_iir); | |
f11a0f46 TU |
2564 | ret |= gen8_de_irq_handler(dev_priv, master_ctl); |
2565 | ||
cb0d205e CW |
2566 | I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
2567 | POSTING_READ_FW(GEN8_MASTER_IRQ); | |
abd58f01 | 2568 | |
1f814dac ID |
2569 | enable_rpm_wakeref_asserts(dev_priv); |
2570 | ||
abd58f01 BW |
2571 | return ret; |
2572 | } | |
2573 | ||
1f15b76f | 2574 | static void i915_error_wake_up(struct drm_i915_private *dev_priv) |
17e1df07 | 2575 | { |
17e1df07 DV |
2576 | /* |
2577 | * Notify all waiters for GPU completion events that reset state has | |
2578 | * been changed, and that they need to restart their wait after | |
2579 | * checking for potential errors (and bail out to drop locks if there is | |
2580 | * a gpu reset pending so that i915_error_work_func can acquire them). | |
2581 | */ | |
2582 | ||
2583 | /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */ | |
1f15b76f | 2584 | wake_up_all(&dev_priv->gpu_error.wait_queue); |
17e1df07 DV |
2585 | |
2586 | /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */ | |
2587 | wake_up_all(&dev_priv->pending_flip_queue); | |
17e1df07 DV |
2588 | } |
2589 | ||
8a905236 | 2590 | /** |
b8d24a06 | 2591 | * i915_reset_and_wakeup - do process context error handling work |
14bb2c11 | 2592 | * @dev_priv: i915 device private |
8a905236 JB |
2593 | * |
2594 | * Fire an error uevent so userspace can see that a hang or error | |
2595 | * was detected. | |
2596 | */ | |
c033666a | 2597 | static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv) |
8a905236 | 2598 | { |
91c8a326 | 2599 | struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj; |
cce723ed BW |
2600 | char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; |
2601 | char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; | |
2602 | char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; | |
8a905236 | 2603 | |
c033666a | 2604 | kobject_uevent_env(kobj, KOBJ_CHANGE, error_event); |
f316a42c | 2605 | |
8af29b0c CW |
2606 | DRM_DEBUG_DRIVER("resetting chip\n"); |
2607 | kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event); | |
2608 | ||
7db0ba24 | 2609 | /* |
8af29b0c CW |
2610 | * In most cases it's guaranteed that we get here with an RPM |
2611 | * reference held, for example because there is a pending GPU | |
2612 | * request that won't finish until the reset is done. This | |
2613 | * isn't the case at least when we get here by doing a | |
2614 | * simulated reset via debugs, so get an RPM reference. | |
7db0ba24 | 2615 | */ |
8af29b0c | 2616 | intel_runtime_pm_get(dev_priv); |
8af29b0c | 2617 | intel_prepare_reset(dev_priv); |
7514747d | 2618 | |
780f262a CW |
2619 | do { |
2620 | /* | |
2621 | * All state reset _must_ be completed before we update the | |
2622 | * reset counter, for otherwise waiters might miss the reset | |
2623 | * pending state and not properly drop locks, resulting in | |
2624 | * deadlocks with the reset work. | |
2625 | */ | |
2626 | if (mutex_trylock(&dev_priv->drm.struct_mutex)) { | |
2627 | i915_reset(dev_priv); | |
2628 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
2629 | } | |
f69061be | 2630 | |
780f262a CW |
2631 | /* We need to wait for anyone holding the lock to wakeup */ |
2632 | } while (wait_on_bit_timeout(&dev_priv->gpu_error.flags, | |
2633 | I915_RESET_IN_PROGRESS, | |
2634 | TASK_UNINTERRUPTIBLE, | |
2635 | HZ)); | |
17e1df07 | 2636 | |
780f262a | 2637 | intel_finish_reset(dev_priv); |
8af29b0c | 2638 | intel_runtime_pm_put(dev_priv); |
f454c694 | 2639 | |
780f262a | 2640 | if (!test_bit(I915_WEDGED, &dev_priv->gpu_error.flags)) |
8af29b0c CW |
2641 | kobject_uevent_env(kobj, |
2642 | KOBJ_CHANGE, reset_done_event); | |
1f83fee0 | 2643 | |
8af29b0c CW |
2644 | /* |
2645 | * Note: The wake_up also serves as a memory barrier so that | |
2646 | * waiters see the updated value of the dev_priv->gpu_error. | |
2647 | */ | |
2648 | wake_up_all(&dev_priv->gpu_error.reset_queue); | |
8a905236 JB |
2649 | } |
2650 | ||
d636951e BW |
2651 | static inline void |
2652 | i915_err_print_instdone(struct drm_i915_private *dev_priv, | |
2653 | struct intel_instdone *instdone) | |
2654 | { | |
f9e61372 BW |
2655 | int slice; |
2656 | int subslice; | |
2657 | ||
d636951e BW |
2658 | pr_err(" INSTDONE: 0x%08x\n", instdone->instdone); |
2659 | ||
2660 | if (INTEL_GEN(dev_priv) <= 3) | |
2661 | return; | |
2662 | ||
2663 | pr_err(" SC_INSTDONE: 0x%08x\n", instdone->slice_common); | |
2664 | ||
2665 | if (INTEL_GEN(dev_priv) <= 6) | |
2666 | return; | |
2667 | ||
f9e61372 BW |
2668 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) |
2669 | pr_err(" SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", | |
2670 | slice, subslice, instdone->sampler[slice][subslice]); | |
2671 | ||
2672 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) | |
2673 | pr_err(" ROW_INSTDONE[%d][%d]: 0x%08x\n", | |
2674 | slice, subslice, instdone->row[slice][subslice]); | |
d636951e BW |
2675 | } |
2676 | ||
eaa14c24 | 2677 | static void i915_clear_error_registers(struct drm_i915_private *dev_priv) |
8a905236 | 2678 | { |
eaa14c24 | 2679 | u32 eir; |
8a905236 | 2680 | |
eaa14c24 CW |
2681 | if (!IS_GEN2(dev_priv)) |
2682 | I915_WRITE(PGTBL_ER, I915_READ(PGTBL_ER)); | |
8a905236 | 2683 | |
eaa14c24 CW |
2684 | if (INTEL_GEN(dev_priv) < 4) |
2685 | I915_WRITE(IPEIR, I915_READ(IPEIR)); | |
2686 | else | |
2687 | I915_WRITE(IPEIR_I965, I915_READ(IPEIR_I965)); | |
8a905236 | 2688 | |
eaa14c24 | 2689 | I915_WRITE(EIR, I915_READ(EIR)); |
8a905236 JB |
2690 | eir = I915_READ(EIR); |
2691 | if (eir) { | |
2692 | /* | |
2693 | * some errors might have become stuck, | |
2694 | * mask them. | |
2695 | */ | |
eaa14c24 | 2696 | DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir); |
8a905236 JB |
2697 | I915_WRITE(EMR, I915_READ(EMR) | eir); |
2698 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2699 | } | |
35aed2e6 CW |
2700 | } |
2701 | ||
2702 | /** | |
b8d24a06 | 2703 | * i915_handle_error - handle a gpu error |
14bb2c11 | 2704 | * @dev_priv: i915 device private |
14b730fc | 2705 | * @engine_mask: mask representing engines that are hung |
aafd8581 | 2706 | * Do some basic checking of register state at error time and |
35aed2e6 CW |
2707 | * dump it to the syslog. Also call i915_capture_error_state() to make |
2708 | * sure we get a record and make it available in debugfs. Fire a uevent | |
2709 | * so userspace knows something bad happened (should trigger collection | |
2710 | * of a ring dump etc.). | |
14bb2c11 | 2711 | * @fmt: Error message format string |
35aed2e6 | 2712 | */ |
c033666a CW |
2713 | void i915_handle_error(struct drm_i915_private *dev_priv, |
2714 | u32 engine_mask, | |
58174462 | 2715 | const char *fmt, ...) |
35aed2e6 | 2716 | { |
58174462 MK |
2717 | va_list args; |
2718 | char error_msg[80]; | |
35aed2e6 | 2719 | |
58174462 MK |
2720 | va_start(args, fmt); |
2721 | vscnprintf(error_msg, sizeof(error_msg), fmt, args); | |
2722 | va_end(args); | |
2723 | ||
c033666a | 2724 | i915_capture_error_state(dev_priv, engine_mask, error_msg); |
eaa14c24 | 2725 | i915_clear_error_registers(dev_priv); |
8a905236 | 2726 | |
8af29b0c CW |
2727 | if (!engine_mask) |
2728 | return; | |
ba1234d1 | 2729 | |
8af29b0c CW |
2730 | if (test_and_set_bit(I915_RESET_IN_PROGRESS, |
2731 | &dev_priv->gpu_error.flags)) | |
2732 | return; | |
2733 | ||
2734 | /* | |
2735 | * Wakeup waiting processes so that the reset function | |
2736 | * i915_reset_and_wakeup doesn't deadlock trying to grab | |
2737 | * various locks. By bumping the reset counter first, the woken | |
2738 | * processes will see a reset in progress and back off, | |
2739 | * releasing their locks and then wait for the reset completion. | |
2740 | * We must do this for _all_ gpu waiters that might hold locks | |
2741 | * that the reset work needs to acquire. | |
2742 | * | |
2743 | * Note: The wake_up also provides a memory barrier to ensure that the | |
2744 | * waiters see the updated value of the reset flags. | |
2745 | */ | |
2746 | i915_error_wake_up(dev_priv); | |
11ed50ec | 2747 | |
c033666a | 2748 | i915_reset_and_wakeup(dev_priv); |
8a905236 JB |
2749 | } |
2750 | ||
42f52ef8 KP |
2751 | /* Called from drm generic code, passed 'crtc' which |
2752 | * we use as a pipe index | |
2753 | */ | |
86e83e35 | 2754 | static int i8xx_enable_vblank(struct drm_device *dev, unsigned int pipe) |
0a3e67a4 | 2755 | { |
fac5e23e | 2756 | struct drm_i915_private *dev_priv = to_i915(dev); |
e9d21d7f | 2757 | unsigned long irqflags; |
71e0ffa5 | 2758 | |
1ec14ad3 | 2759 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
86e83e35 | 2760 | i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS); |
1ec14ad3 | 2761 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
8692d00e | 2762 | |
0a3e67a4 JB |
2763 | return 0; |
2764 | } | |
2765 | ||
86e83e35 | 2766 | static int i965_enable_vblank(struct drm_device *dev, unsigned int pipe) |
f796cf8f | 2767 | { |
fac5e23e | 2768 | struct drm_i915_private *dev_priv = to_i915(dev); |
f796cf8f JB |
2769 | unsigned long irqflags; |
2770 | ||
f796cf8f | 2771 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
86e83e35 CW |
2772 | i915_enable_pipestat(dev_priv, pipe, |
2773 | PIPE_START_VBLANK_INTERRUPT_STATUS); | |
b1f14ad0 JB |
2774 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2775 | ||
2776 | return 0; | |
2777 | } | |
2778 | ||
86e83e35 | 2779 | static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe) |
7e231dbe | 2780 | { |
fac5e23e | 2781 | struct drm_i915_private *dev_priv = to_i915(dev); |
7e231dbe | 2782 | unsigned long irqflags; |
55b8f2a7 | 2783 | uint32_t bit = INTEL_GEN(dev_priv) >= 7 ? |
86e83e35 | 2784 | DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); |
7e231dbe | 2785 | |
7e231dbe | 2786 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
86e83e35 | 2787 | ilk_enable_display_irq(dev_priv, bit); |
7e231dbe JB |
2788 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2789 | ||
2790 | return 0; | |
2791 | } | |
2792 | ||
88e72717 | 2793 | static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe) |
abd58f01 | 2794 | { |
fac5e23e | 2795 | struct drm_i915_private *dev_priv = to_i915(dev); |
abd58f01 | 2796 | unsigned long irqflags; |
abd58f01 | 2797 | |
abd58f01 | 2798 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
013d3752 | 2799 | bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); |
abd58f01 | 2800 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
013d3752 | 2801 | |
abd58f01 BW |
2802 | return 0; |
2803 | } | |
2804 | ||
42f52ef8 KP |
2805 | /* Called from drm generic code, passed 'crtc' which |
2806 | * we use as a pipe index | |
2807 | */ | |
86e83e35 | 2808 | static void i8xx_disable_vblank(struct drm_device *dev, unsigned int pipe) |
0a3e67a4 | 2809 | { |
fac5e23e | 2810 | struct drm_i915_private *dev_priv = to_i915(dev); |
e9d21d7f | 2811 | unsigned long irqflags; |
0a3e67a4 | 2812 | |
1ec14ad3 | 2813 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
86e83e35 | 2814 | i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS); |
f796cf8f JB |
2815 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2816 | } | |
2817 | ||
86e83e35 | 2818 | static void i965_disable_vblank(struct drm_device *dev, unsigned int pipe) |
f796cf8f | 2819 | { |
fac5e23e | 2820 | struct drm_i915_private *dev_priv = to_i915(dev); |
f796cf8f JB |
2821 | unsigned long irqflags; |
2822 | ||
2823 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
86e83e35 CW |
2824 | i915_disable_pipestat(dev_priv, pipe, |
2825 | PIPE_START_VBLANK_INTERRUPT_STATUS); | |
b1f14ad0 JB |
2826 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2827 | } | |
2828 | ||
86e83e35 | 2829 | static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe) |
7e231dbe | 2830 | { |
fac5e23e | 2831 | struct drm_i915_private *dev_priv = to_i915(dev); |
7e231dbe | 2832 | unsigned long irqflags; |
55b8f2a7 | 2833 | uint32_t bit = INTEL_GEN(dev_priv) >= 7 ? |
86e83e35 | 2834 | DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); |
7e231dbe JB |
2835 | |
2836 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
86e83e35 | 2837 | ilk_disable_display_irq(dev_priv, bit); |
7e231dbe JB |
2838 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2839 | } | |
2840 | ||
88e72717 | 2841 | static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe) |
abd58f01 | 2842 | { |
fac5e23e | 2843 | struct drm_i915_private *dev_priv = to_i915(dev); |
abd58f01 | 2844 | unsigned long irqflags; |
abd58f01 | 2845 | |
abd58f01 | 2846 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
013d3752 | 2847 | bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); |
abd58f01 BW |
2848 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2849 | } | |
2850 | ||
b243f530 | 2851 | static void ibx_irq_reset(struct drm_i915_private *dev_priv) |
91738a95 | 2852 | { |
6e266956 | 2853 | if (HAS_PCH_NOP(dev_priv)) |
91738a95 PZ |
2854 | return; |
2855 | ||
f86f3fb0 | 2856 | GEN5_IRQ_RESET(SDE); |
105b122e | 2857 | |
6e266956 | 2858 | if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv)) |
105b122e | 2859 | I915_WRITE(SERR_INT, 0xffffffff); |
622364b6 | 2860 | } |
105b122e | 2861 | |
622364b6 PZ |
2862 | /* |
2863 | * SDEIER is also touched by the interrupt handler to work around missed PCH | |
2864 | * interrupts. Hence we can't update it after the interrupt handler is enabled - | |
2865 | * instead we unconditionally enable all PCH interrupt sources here, but then | |
2866 | * only unmask them as needed with SDEIMR. | |
2867 | * | |
2868 | * This function needs to be called before interrupts are enabled. | |
2869 | */ | |
2870 | static void ibx_irq_pre_postinstall(struct drm_device *dev) | |
2871 | { | |
fac5e23e | 2872 | struct drm_i915_private *dev_priv = to_i915(dev); |
622364b6 | 2873 | |
6e266956 | 2874 | if (HAS_PCH_NOP(dev_priv)) |
622364b6 PZ |
2875 | return; |
2876 | ||
2877 | WARN_ON(I915_READ(SDEIER) != 0); | |
91738a95 PZ |
2878 | I915_WRITE(SDEIER, 0xffffffff); |
2879 | POSTING_READ(SDEIER); | |
2880 | } | |
2881 | ||
b243f530 | 2882 | static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv) |
d18ea1b5 | 2883 | { |
f86f3fb0 | 2884 | GEN5_IRQ_RESET(GT); |
b243f530 | 2885 | if (INTEL_GEN(dev_priv) >= 6) |
f86f3fb0 | 2886 | GEN5_IRQ_RESET(GEN6_PM); |
d18ea1b5 DV |
2887 | } |
2888 | ||
70591a41 VS |
2889 | static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) |
2890 | { | |
2891 | enum pipe pipe; | |
2892 | ||
71b8b41d VS |
2893 | if (IS_CHERRYVIEW(dev_priv)) |
2894 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV); | |
2895 | else | |
2896 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); | |
2897 | ||
ad22d106 | 2898 | i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0); |
70591a41 VS |
2899 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
2900 | ||
ad22d106 VS |
2901 | for_each_pipe(dev_priv, pipe) { |
2902 | I915_WRITE(PIPESTAT(pipe), | |
2903 | PIPE_FIFO_UNDERRUN_STATUS | | |
2904 | PIPESTAT_INT_STATUS_MASK); | |
2905 | dev_priv->pipestat_irq_mask[pipe] = 0; | |
2906 | } | |
70591a41 VS |
2907 | |
2908 | GEN5_IRQ_RESET(VLV_); | |
ad22d106 | 2909 | dev_priv->irq_mask = ~0; |
70591a41 VS |
2910 | } |
2911 | ||
8bb61306 VS |
2912 | static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) |
2913 | { | |
2914 | u32 pipestat_mask; | |
9ab981f2 | 2915 | u32 enable_mask; |
8bb61306 VS |
2916 | enum pipe pipe; |
2917 | ||
8bb61306 VS |
2918 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | |
2919 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
2920 | ||
2921 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); | |
2922 | for_each_pipe(dev_priv, pipe) | |
2923 | i915_enable_pipestat(dev_priv, pipe, pipestat_mask); | |
2924 | ||
9ab981f2 VS |
2925 | enable_mask = I915_DISPLAY_PORT_INTERRUPT | |
2926 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
2927 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
8bb61306 | 2928 | if (IS_CHERRYVIEW(dev_priv)) |
9ab981f2 | 2929 | enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; |
6b7eafc1 VS |
2930 | |
2931 | WARN_ON(dev_priv->irq_mask != ~0); | |
2932 | ||
9ab981f2 VS |
2933 | dev_priv->irq_mask = ~enable_mask; |
2934 | ||
2935 | GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask); | |
8bb61306 VS |
2936 | } |
2937 | ||
2938 | /* drm_dma.h hooks | |
2939 | */ | |
2940 | static void ironlake_irq_reset(struct drm_device *dev) | |
2941 | { | |
fac5e23e | 2942 | struct drm_i915_private *dev_priv = to_i915(dev); |
8bb61306 VS |
2943 | |
2944 | I915_WRITE(HWSTAM, 0xffffffff); | |
2945 | ||
2946 | GEN5_IRQ_RESET(DE); | |
5db94019 | 2947 | if (IS_GEN7(dev_priv)) |
8bb61306 VS |
2948 | I915_WRITE(GEN7_ERR_INT, 0xffffffff); |
2949 | ||
b243f530 | 2950 | gen5_gt_irq_reset(dev_priv); |
8bb61306 | 2951 | |
b243f530 | 2952 | ibx_irq_reset(dev_priv); |
8bb61306 VS |
2953 | } |
2954 | ||
7e231dbe JB |
2955 | static void valleyview_irq_preinstall(struct drm_device *dev) |
2956 | { | |
fac5e23e | 2957 | struct drm_i915_private *dev_priv = to_i915(dev); |
7e231dbe | 2958 | |
34c7b8a7 VS |
2959 | I915_WRITE(VLV_MASTER_IER, 0); |
2960 | POSTING_READ(VLV_MASTER_IER); | |
2961 | ||
b243f530 | 2962 | gen5_gt_irq_reset(dev_priv); |
7e231dbe | 2963 | |
ad22d106 | 2964 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
2965 | if (dev_priv->display_irqs_enabled) |
2966 | vlv_display_irq_reset(dev_priv); | |
ad22d106 | 2967 | spin_unlock_irq(&dev_priv->irq_lock); |
7e231dbe JB |
2968 | } |
2969 | ||
d6e3cca3 DV |
2970 | static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv) |
2971 | { | |
2972 | GEN8_IRQ_RESET_NDX(GT, 0); | |
2973 | GEN8_IRQ_RESET_NDX(GT, 1); | |
2974 | GEN8_IRQ_RESET_NDX(GT, 2); | |
2975 | GEN8_IRQ_RESET_NDX(GT, 3); | |
2976 | } | |
2977 | ||
823f6b38 | 2978 | static void gen8_irq_reset(struct drm_device *dev) |
abd58f01 | 2979 | { |
fac5e23e | 2980 | struct drm_i915_private *dev_priv = to_i915(dev); |
abd58f01 BW |
2981 | int pipe; |
2982 | ||
abd58f01 BW |
2983 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
2984 | POSTING_READ(GEN8_MASTER_IRQ); | |
2985 | ||
d6e3cca3 | 2986 | gen8_gt_irq_reset(dev_priv); |
abd58f01 | 2987 | |
055e393f | 2988 | for_each_pipe(dev_priv, pipe) |
f458ebbc DV |
2989 | if (intel_display_power_is_enabled(dev_priv, |
2990 | POWER_DOMAIN_PIPE(pipe))) | |
813bde43 | 2991 | GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); |
abd58f01 | 2992 | |
f86f3fb0 PZ |
2993 | GEN5_IRQ_RESET(GEN8_DE_PORT_); |
2994 | GEN5_IRQ_RESET(GEN8_DE_MISC_); | |
2995 | GEN5_IRQ_RESET(GEN8_PCU_); | |
abd58f01 | 2996 | |
6e266956 | 2997 | if (HAS_PCH_SPLIT(dev_priv)) |
b243f530 | 2998 | ibx_irq_reset(dev_priv); |
abd58f01 | 2999 | } |
09f2344d | 3000 | |
4c6c03be DL |
3001 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, |
3002 | unsigned int pipe_mask) | |
d49bdb0e | 3003 | { |
1180e206 | 3004 | uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; |
6831f3e3 | 3005 | enum pipe pipe; |
d49bdb0e | 3006 | |
13321786 | 3007 | spin_lock_irq(&dev_priv->irq_lock); |
6831f3e3 VS |
3008 | for_each_pipe_masked(dev_priv, pipe, pipe_mask) |
3009 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, | |
3010 | dev_priv->de_irq_mask[pipe], | |
3011 | ~dev_priv->de_irq_mask[pipe] | extra_ier); | |
13321786 | 3012 | spin_unlock_irq(&dev_priv->irq_lock); |
d49bdb0e PZ |
3013 | } |
3014 | ||
aae8ba84 VS |
3015 | void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, |
3016 | unsigned int pipe_mask) | |
3017 | { | |
6831f3e3 VS |
3018 | enum pipe pipe; |
3019 | ||
aae8ba84 | 3020 | spin_lock_irq(&dev_priv->irq_lock); |
6831f3e3 VS |
3021 | for_each_pipe_masked(dev_priv, pipe, pipe_mask) |
3022 | GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); | |
aae8ba84 VS |
3023 | spin_unlock_irq(&dev_priv->irq_lock); |
3024 | ||
3025 | /* make sure we're done processing display irqs */ | |
91c8a326 | 3026 | synchronize_irq(dev_priv->drm.irq); |
aae8ba84 VS |
3027 | } |
3028 | ||
43f328d7 VS |
3029 | static void cherryview_irq_preinstall(struct drm_device *dev) |
3030 | { | |
fac5e23e | 3031 | struct drm_i915_private *dev_priv = to_i915(dev); |
43f328d7 VS |
3032 | |
3033 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3034 | POSTING_READ(GEN8_MASTER_IRQ); | |
3035 | ||
d6e3cca3 | 3036 | gen8_gt_irq_reset(dev_priv); |
43f328d7 VS |
3037 | |
3038 | GEN5_IRQ_RESET(GEN8_PCU_); | |
3039 | ||
ad22d106 | 3040 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3041 | if (dev_priv->display_irqs_enabled) |
3042 | vlv_display_irq_reset(dev_priv); | |
ad22d106 | 3043 | spin_unlock_irq(&dev_priv->irq_lock); |
43f328d7 VS |
3044 | } |
3045 | ||
91d14251 | 3046 | static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv, |
87a02106 VS |
3047 | const u32 hpd[HPD_NUM_PINS]) |
3048 | { | |
87a02106 VS |
3049 | struct intel_encoder *encoder; |
3050 | u32 enabled_irqs = 0; | |
3051 | ||
91c8a326 | 3052 | for_each_intel_encoder(&dev_priv->drm, encoder) |
87a02106 VS |
3053 | if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED) |
3054 | enabled_irqs |= hpd[encoder->hpd_pin]; | |
3055 | ||
3056 | return enabled_irqs; | |
3057 | } | |
3058 | ||
91d14251 | 3059 | static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv) |
7fe0b973 | 3060 | { |
87a02106 | 3061 | u32 hotplug_irqs, hotplug, enabled_irqs; |
82a28bcf | 3062 | |
91d14251 | 3063 | if (HAS_PCH_IBX(dev_priv)) { |
fee884ed | 3064 | hotplug_irqs = SDE_HOTPLUG_MASK; |
91d14251 | 3065 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx); |
82a28bcf | 3066 | } else { |
fee884ed | 3067 | hotplug_irqs = SDE_HOTPLUG_MASK_CPT; |
91d14251 | 3068 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt); |
82a28bcf | 3069 | } |
7fe0b973 | 3070 | |
fee884ed | 3071 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); |
82a28bcf DV |
3072 | |
3073 | /* | |
3074 | * Enable digital hotplug on the PCH, and configure the DP short pulse | |
6dbf30ce VS |
3075 | * duration to 2ms (which is the minimum in the Display Port spec). |
3076 | * The pulse duration bits are reserved on LPT+. | |
82a28bcf | 3077 | */ |
7fe0b973 KP |
3078 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
3079 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); | |
3080 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; | |
3081 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; | |
3082 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; | |
0b2eb33e VS |
3083 | /* |
3084 | * When CPU and PCH are on the same package, port A | |
3085 | * HPD must be enabled in both north and south. | |
3086 | */ | |
91d14251 | 3087 | if (HAS_PCH_LPT_LP(dev_priv)) |
0b2eb33e | 3088 | hotplug |= PORTA_HOTPLUG_ENABLE; |
7fe0b973 | 3089 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
6dbf30ce | 3090 | } |
26951caf | 3091 | |
207ebbb5 | 3092 | static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv) |
6dbf30ce | 3093 | { |
207ebbb5 | 3094 | u32 hotplug; |
6dbf30ce VS |
3095 | |
3096 | /* Enable digital hotplug on the PCH */ | |
3097 | hotplug = I915_READ(PCH_PORT_HOTPLUG); | |
207ebbb5 ID |
3098 | hotplug |= PORTA_HOTPLUG_ENABLE | |
3099 | PORTB_HOTPLUG_ENABLE | | |
3100 | PORTC_HOTPLUG_ENABLE | | |
3101 | PORTD_HOTPLUG_ENABLE; | |
6dbf30ce VS |
3102 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
3103 | ||
3104 | hotplug = I915_READ(PCH_PORT_HOTPLUG2); | |
3105 | hotplug |= PORTE_HOTPLUG_ENABLE; | |
3106 | I915_WRITE(PCH_PORT_HOTPLUG2, hotplug); | |
7fe0b973 KP |
3107 | } |
3108 | ||
207ebbb5 ID |
3109 | static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv) |
3110 | { | |
3111 | u32 hotplug_irqs, enabled_irqs; | |
3112 | ||
3113 | hotplug_irqs = SDE_HOTPLUG_MASK_SPT; | |
3114 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt); | |
3115 | ||
3116 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); | |
3117 | ||
3118 | spt_hpd_detection_setup(dev_priv); | |
3119 | } | |
3120 | ||
91d14251 | 3121 | static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv) |
e4ce95aa | 3122 | { |
e4ce95aa VS |
3123 | u32 hotplug_irqs, hotplug, enabled_irqs; |
3124 | ||
91d14251 | 3125 | if (INTEL_GEN(dev_priv) >= 8) { |
3a3b3c7d | 3126 | hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG; |
91d14251 | 3127 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw); |
3a3b3c7d VS |
3128 | |
3129 | bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); | |
91d14251 | 3130 | } else if (INTEL_GEN(dev_priv) >= 7) { |
23bb4cb5 | 3131 | hotplug_irqs = DE_DP_A_HOTPLUG_IVB; |
91d14251 | 3132 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb); |
3a3b3c7d VS |
3133 | |
3134 | ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); | |
23bb4cb5 VS |
3135 | } else { |
3136 | hotplug_irqs = DE_DP_A_HOTPLUG; | |
91d14251 | 3137 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk); |
e4ce95aa | 3138 | |
3a3b3c7d VS |
3139 | ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); |
3140 | } | |
e4ce95aa VS |
3141 | |
3142 | /* | |
3143 | * Enable digital hotplug on the CPU, and configure the DP short pulse | |
3144 | * duration to 2ms (which is the minimum in the Display Port spec) | |
23bb4cb5 | 3145 | * The pulse duration bits are reserved on HSW+. |
e4ce95aa VS |
3146 | */ |
3147 | hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL); | |
3148 | hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK; | |
3149 | hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_2ms; | |
3150 | I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug); | |
3151 | ||
91d14251 | 3152 | ibx_hpd_irq_setup(dev_priv); |
e4ce95aa VS |
3153 | } |
3154 | ||
207ebbb5 ID |
3155 | static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv, |
3156 | u32 enabled_irqs) | |
e0a20ad7 | 3157 | { |
207ebbb5 | 3158 | u32 hotplug; |
e0a20ad7 | 3159 | |
a52bb15b | 3160 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
207ebbb5 ID |
3161 | hotplug |= PORTA_HOTPLUG_ENABLE | |
3162 | PORTB_HOTPLUG_ENABLE | | |
3163 | PORTC_HOTPLUG_ENABLE; | |
d252bf68 SS |
3164 | |
3165 | DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n", | |
3166 | hotplug, enabled_irqs); | |
3167 | hotplug &= ~BXT_DDI_HPD_INVERT_MASK; | |
3168 | ||
3169 | /* | |
3170 | * For BXT invert bit has to be set based on AOB design | |
3171 | * for HPD detection logic, update it based on VBT fields. | |
3172 | */ | |
d252bf68 SS |
3173 | if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) && |
3174 | intel_bios_is_port_hpd_inverted(dev_priv, PORT_A)) | |
3175 | hotplug |= BXT_DDIA_HPD_INVERT; | |
3176 | if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) && | |
3177 | intel_bios_is_port_hpd_inverted(dev_priv, PORT_B)) | |
3178 | hotplug |= BXT_DDIB_HPD_INVERT; | |
3179 | if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) && | |
3180 | intel_bios_is_port_hpd_inverted(dev_priv, PORT_C)) | |
3181 | hotplug |= BXT_DDIC_HPD_INVERT; | |
3182 | ||
a52bb15b | 3183 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
e0a20ad7 SS |
3184 | } |
3185 | ||
207ebbb5 ID |
3186 | static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv) |
3187 | { | |
3188 | __bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK); | |
3189 | } | |
3190 | ||
3191 | static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv) | |
3192 | { | |
3193 | u32 hotplug_irqs, enabled_irqs; | |
3194 | ||
3195 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt); | |
3196 | hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK; | |
3197 | ||
3198 | bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); | |
3199 | ||
3200 | __bxt_hpd_detection_setup(dev_priv, enabled_irqs); | |
3201 | } | |
3202 | ||
d46da437 PZ |
3203 | static void ibx_irq_postinstall(struct drm_device *dev) |
3204 | { | |
fac5e23e | 3205 | struct drm_i915_private *dev_priv = to_i915(dev); |
82a28bcf | 3206 | u32 mask; |
e5868a31 | 3207 | |
6e266956 | 3208 | if (HAS_PCH_NOP(dev_priv)) |
692a04cf DV |
3209 | return; |
3210 | ||
6e266956 | 3211 | if (HAS_PCH_IBX(dev_priv)) |
5c673b60 | 3212 | mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; |
105b122e | 3213 | else |
5c673b60 | 3214 | mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; |
8664281b | 3215 | |
b51a2842 | 3216 | gen5_assert_iir_is_zero(dev_priv, SDEIIR); |
d46da437 | 3217 | I915_WRITE(SDEIMR, ~mask); |
207ebbb5 ID |
3218 | |
3219 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || | |
3220 | HAS_PCH_LPT(dev_priv)) | |
3221 | ; /* TODO: Enable HPD detection on older PCH platforms too */ | |
3222 | else | |
3223 | spt_hpd_detection_setup(dev_priv); | |
d46da437 PZ |
3224 | } |
3225 | ||
0a9a8c91 DV |
3226 | static void gen5_gt_irq_postinstall(struct drm_device *dev) |
3227 | { | |
fac5e23e | 3228 | struct drm_i915_private *dev_priv = to_i915(dev); |
0a9a8c91 DV |
3229 | u32 pm_irqs, gt_irqs; |
3230 | ||
3231 | pm_irqs = gt_irqs = 0; | |
3232 | ||
3233 | dev_priv->gt_irq_mask = ~0; | |
3c9192bc | 3234 | if (HAS_L3_DPF(dev_priv)) { |
0a9a8c91 | 3235 | /* L3 parity interrupt is always unmasked. */ |
772c2a51 TU |
3236 | dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev_priv); |
3237 | gt_irqs |= GT_PARITY_ERROR(dev_priv); | |
0a9a8c91 DV |
3238 | } |
3239 | ||
3240 | gt_irqs |= GT_RENDER_USER_INTERRUPT; | |
5db94019 | 3241 | if (IS_GEN5(dev_priv)) { |
f8973c21 | 3242 | gt_irqs |= ILK_BSD_USER_INTERRUPT; |
0a9a8c91 DV |
3243 | } else { |
3244 | gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; | |
3245 | } | |
3246 | ||
35079899 | 3247 | GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); |
0a9a8c91 | 3248 | |
b243f530 | 3249 | if (INTEL_GEN(dev_priv) >= 6) { |
78e68d36 ID |
3250 | /* |
3251 | * RPS interrupts will get enabled/disabled on demand when RPS | |
3252 | * itself is enabled/disabled. | |
3253 | */ | |
f4e9af4f | 3254 | if (HAS_VEBOX(dev_priv)) { |
0a9a8c91 | 3255 | pm_irqs |= PM_VEBOX_USER_INTERRUPT; |
f4e9af4f AG |
3256 | dev_priv->pm_ier |= PM_VEBOX_USER_INTERRUPT; |
3257 | } | |
0a9a8c91 | 3258 | |
f4e9af4f AG |
3259 | dev_priv->pm_imr = 0xffffffff; |
3260 | GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_imr, pm_irqs); | |
0a9a8c91 DV |
3261 | } |
3262 | } | |
3263 | ||
f71d4af4 | 3264 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d | 3265 | { |
fac5e23e | 3266 | struct drm_i915_private *dev_priv = to_i915(dev); |
8e76f8dc PZ |
3267 | u32 display_mask, extra_mask; |
3268 | ||
b243f530 | 3269 | if (INTEL_GEN(dev_priv) >= 7) { |
8e76f8dc PZ |
3270 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | |
3271 | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | | |
3272 | DE_PLANEB_FLIP_DONE_IVB | | |
5c673b60 | 3273 | DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB); |
8e76f8dc | 3274 | extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | |
23bb4cb5 VS |
3275 | DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB | |
3276 | DE_DP_A_HOTPLUG_IVB); | |
8e76f8dc PZ |
3277 | } else { |
3278 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | | |
3279 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | | |
5b3a856b | 3280 | DE_AUX_CHANNEL_A | |
5b3a856b DV |
3281 | DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE | |
3282 | DE_POISON); | |
e4ce95aa VS |
3283 | extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT | |
3284 | DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN | | |
3285 | DE_DP_A_HOTPLUG); | |
8e76f8dc | 3286 | } |
036a4a7d | 3287 | |
1ec14ad3 | 3288 | dev_priv->irq_mask = ~display_mask; |
036a4a7d | 3289 | |
0c841212 PZ |
3290 | I915_WRITE(HWSTAM, 0xeffe); |
3291 | ||
622364b6 PZ |
3292 | ibx_irq_pre_postinstall(dev); |
3293 | ||
35079899 | 3294 | GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); |
036a4a7d | 3295 | |
0a9a8c91 | 3296 | gen5_gt_irq_postinstall(dev); |
036a4a7d | 3297 | |
d46da437 | 3298 | ibx_irq_postinstall(dev); |
7fe0b973 | 3299 | |
50a0bc90 | 3300 | if (IS_IRONLAKE_M(dev_priv)) { |
6005ce42 DV |
3301 | /* Enable PCU event interrupts |
3302 | * | |
3303 | * spinlocking not required here for correctness since interrupt | |
4bc9d430 DV |
3304 | * setup is guaranteed to run in single-threaded context. But we |
3305 | * need it to make the assert_spin_locked happy. */ | |
d6207435 | 3306 | spin_lock_irq(&dev_priv->irq_lock); |
fbdedaea | 3307 | ilk_enable_display_irq(dev_priv, DE_PCU_EVENT); |
d6207435 | 3308 | spin_unlock_irq(&dev_priv->irq_lock); |
f97108d1 JB |
3309 | } |
3310 | ||
036a4a7d ZW |
3311 | return 0; |
3312 | } | |
3313 | ||
f8b79e58 ID |
3314 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) |
3315 | { | |
3316 | assert_spin_locked(&dev_priv->irq_lock); | |
3317 | ||
3318 | if (dev_priv->display_irqs_enabled) | |
3319 | return; | |
3320 | ||
3321 | dev_priv->display_irqs_enabled = true; | |
3322 | ||
d6c69803 VS |
3323 | if (intel_irqs_enabled(dev_priv)) { |
3324 | vlv_display_irq_reset(dev_priv); | |
ad22d106 | 3325 | vlv_display_irq_postinstall(dev_priv); |
d6c69803 | 3326 | } |
f8b79e58 ID |
3327 | } |
3328 | ||
3329 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) | |
3330 | { | |
3331 | assert_spin_locked(&dev_priv->irq_lock); | |
3332 | ||
3333 | if (!dev_priv->display_irqs_enabled) | |
3334 | return; | |
3335 | ||
3336 | dev_priv->display_irqs_enabled = false; | |
3337 | ||
950eabaf | 3338 | if (intel_irqs_enabled(dev_priv)) |
ad22d106 | 3339 | vlv_display_irq_reset(dev_priv); |
f8b79e58 ID |
3340 | } |
3341 | ||
0e6c9a9e VS |
3342 | |
3343 | static int valleyview_irq_postinstall(struct drm_device *dev) | |
3344 | { | |
fac5e23e | 3345 | struct drm_i915_private *dev_priv = to_i915(dev); |
0e6c9a9e | 3346 | |
0a9a8c91 | 3347 | gen5_gt_irq_postinstall(dev); |
7e231dbe | 3348 | |
ad22d106 | 3349 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3350 | if (dev_priv->display_irqs_enabled) |
3351 | vlv_display_irq_postinstall(dev_priv); | |
ad22d106 VS |
3352 | spin_unlock_irq(&dev_priv->irq_lock); |
3353 | ||
7e231dbe | 3354 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); |
34c7b8a7 | 3355 | POSTING_READ(VLV_MASTER_IER); |
20afbda2 DV |
3356 | |
3357 | return 0; | |
3358 | } | |
3359 | ||
abd58f01 BW |
3360 | static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) |
3361 | { | |
abd58f01 BW |
3362 | /* These are interrupts we'll toggle with the ring mask register */ |
3363 | uint32_t gt_interrupts[] = { | |
3364 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | | |
73d477f6 | 3365 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT | |
73d477f6 OM |
3366 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT | |
3367 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT, | |
abd58f01 | 3368 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
73d477f6 OM |
3369 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
3370 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT | | |
3371 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT, | |
abd58f01 | 3372 | 0, |
73d477f6 OM |
3373 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
3374 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
abd58f01 BW |
3375 | }; |
3376 | ||
98735739 TU |
3377 | if (HAS_L3_DPF(dev_priv)) |
3378 | gt_interrupts[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
3379 | ||
f4e9af4f AG |
3380 | dev_priv->pm_ier = 0x0; |
3381 | dev_priv->pm_imr = ~dev_priv->pm_ier; | |
9a2d2d87 D |
3382 | GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]); |
3383 | GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]); | |
78e68d36 ID |
3384 | /* |
3385 | * RPS interrupts will get enabled/disabled on demand when RPS itself | |
26705e20 | 3386 | * is enabled/disabled. Same wil be the case for GuC interrupts. |
78e68d36 | 3387 | */ |
f4e9af4f | 3388 | GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_imr, dev_priv->pm_ier); |
9a2d2d87 | 3389 | GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]); |
abd58f01 BW |
3390 | } |
3391 | ||
3392 | static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) | |
3393 | { | |
770de83d DL |
3394 | uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE; |
3395 | uint32_t de_pipe_enables; | |
3a3b3c7d VS |
3396 | u32 de_port_masked = GEN8_AUX_CHANNEL_A; |
3397 | u32 de_port_enables; | |
11825b0d | 3398 | u32 de_misc_masked = GEN8_DE_MISC_GSE; |
3a3b3c7d | 3399 | enum pipe pipe; |
770de83d | 3400 | |
b4834a50 | 3401 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
770de83d DL |
3402 | de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE | |
3403 | GEN9_DE_PIPE_IRQ_FAULT_ERRORS; | |
3a3b3c7d VS |
3404 | de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | |
3405 | GEN9_AUX_CHANNEL_D; | |
9e63743e | 3406 | if (IS_BROXTON(dev_priv)) |
3a3b3c7d VS |
3407 | de_port_masked |= BXT_DE_PORT_GMBUS; |
3408 | } else { | |
770de83d DL |
3409 | de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE | |
3410 | GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
3a3b3c7d | 3411 | } |
770de83d DL |
3412 | |
3413 | de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | | |
3414 | GEN8_PIPE_FIFO_UNDERRUN; | |
3415 | ||
3a3b3c7d | 3416 | de_port_enables = de_port_masked; |
a52bb15b VS |
3417 | if (IS_BROXTON(dev_priv)) |
3418 | de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK; | |
3419 | else if (IS_BROADWELL(dev_priv)) | |
3a3b3c7d VS |
3420 | de_port_enables |= GEN8_PORT_DP_A_HOTPLUG; |
3421 | ||
13b3a0a7 DV |
3422 | dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; |
3423 | dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; | |
3424 | dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; | |
abd58f01 | 3425 | |
055e393f | 3426 | for_each_pipe(dev_priv, pipe) |
f458ebbc | 3427 | if (intel_display_power_is_enabled(dev_priv, |
813bde43 PZ |
3428 | POWER_DOMAIN_PIPE(pipe))) |
3429 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, | |
3430 | dev_priv->de_irq_mask[pipe], | |
3431 | de_pipe_enables); | |
abd58f01 | 3432 | |
3a3b3c7d | 3433 | GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables); |
11825b0d | 3434 | GEN5_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked); |
207ebbb5 ID |
3435 | |
3436 | if (IS_BROXTON(dev_priv)) | |
3437 | bxt_hpd_detection_setup(dev_priv); | |
abd58f01 BW |
3438 | } |
3439 | ||
3440 | static int gen8_irq_postinstall(struct drm_device *dev) | |
3441 | { | |
fac5e23e | 3442 | struct drm_i915_private *dev_priv = to_i915(dev); |
abd58f01 | 3443 | |
6e266956 | 3444 | if (HAS_PCH_SPLIT(dev_priv)) |
266ea3d9 | 3445 | ibx_irq_pre_postinstall(dev); |
622364b6 | 3446 | |
abd58f01 BW |
3447 | gen8_gt_irq_postinstall(dev_priv); |
3448 | gen8_de_irq_postinstall(dev_priv); | |
3449 | ||
6e266956 | 3450 | if (HAS_PCH_SPLIT(dev_priv)) |
266ea3d9 | 3451 | ibx_irq_postinstall(dev); |
abd58f01 | 3452 | |
e5328c43 | 3453 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
abd58f01 BW |
3454 | POSTING_READ(GEN8_MASTER_IRQ); |
3455 | ||
3456 | return 0; | |
3457 | } | |
3458 | ||
43f328d7 VS |
3459 | static int cherryview_irq_postinstall(struct drm_device *dev) |
3460 | { | |
fac5e23e | 3461 | struct drm_i915_private *dev_priv = to_i915(dev); |
43f328d7 | 3462 | |
43f328d7 VS |
3463 | gen8_gt_irq_postinstall(dev_priv); |
3464 | ||
ad22d106 | 3465 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3466 | if (dev_priv->display_irqs_enabled) |
3467 | vlv_display_irq_postinstall(dev_priv); | |
ad22d106 VS |
3468 | spin_unlock_irq(&dev_priv->irq_lock); |
3469 | ||
e5328c43 | 3470 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
43f328d7 VS |
3471 | POSTING_READ(GEN8_MASTER_IRQ); |
3472 | ||
3473 | return 0; | |
3474 | } | |
3475 | ||
abd58f01 BW |
3476 | static void gen8_irq_uninstall(struct drm_device *dev) |
3477 | { | |
fac5e23e | 3478 | struct drm_i915_private *dev_priv = to_i915(dev); |
abd58f01 BW |
3479 | |
3480 | if (!dev_priv) | |
3481 | return; | |
3482 | ||
823f6b38 | 3483 | gen8_irq_reset(dev); |
abd58f01 BW |
3484 | } |
3485 | ||
7e231dbe JB |
3486 | static void valleyview_irq_uninstall(struct drm_device *dev) |
3487 | { | |
fac5e23e | 3488 | struct drm_i915_private *dev_priv = to_i915(dev); |
7e231dbe JB |
3489 | |
3490 | if (!dev_priv) | |
3491 | return; | |
3492 | ||
843d0e7d | 3493 | I915_WRITE(VLV_MASTER_IER, 0); |
34c7b8a7 | 3494 | POSTING_READ(VLV_MASTER_IER); |
843d0e7d | 3495 | |
b243f530 | 3496 | gen5_gt_irq_reset(dev_priv); |
893fce8e | 3497 | |
7e231dbe | 3498 | I915_WRITE(HWSTAM, 0xffffffff); |
f8b79e58 | 3499 | |
ad22d106 | 3500 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3501 | if (dev_priv->display_irqs_enabled) |
3502 | vlv_display_irq_reset(dev_priv); | |
ad22d106 | 3503 | spin_unlock_irq(&dev_priv->irq_lock); |
7e231dbe JB |
3504 | } |
3505 | ||
43f328d7 VS |
3506 | static void cherryview_irq_uninstall(struct drm_device *dev) |
3507 | { | |
fac5e23e | 3508 | struct drm_i915_private *dev_priv = to_i915(dev); |
43f328d7 VS |
3509 | |
3510 | if (!dev_priv) | |
3511 | return; | |
3512 | ||
3513 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3514 | POSTING_READ(GEN8_MASTER_IRQ); | |
3515 | ||
a2c30fba | 3516 | gen8_gt_irq_reset(dev_priv); |
43f328d7 | 3517 | |
a2c30fba | 3518 | GEN5_IRQ_RESET(GEN8_PCU_); |
43f328d7 | 3519 | |
ad22d106 | 3520 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3521 | if (dev_priv->display_irqs_enabled) |
3522 | vlv_display_irq_reset(dev_priv); | |
ad22d106 | 3523 | spin_unlock_irq(&dev_priv->irq_lock); |
43f328d7 VS |
3524 | } |
3525 | ||
f71d4af4 | 3526 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d | 3527 | { |
fac5e23e | 3528 | struct drm_i915_private *dev_priv = to_i915(dev); |
4697995b JB |
3529 | |
3530 | if (!dev_priv) | |
3531 | return; | |
3532 | ||
be30b29f | 3533 | ironlake_irq_reset(dev); |
036a4a7d ZW |
3534 | } |
3535 | ||
a266c7d5 | 3536 | static void i8xx_irq_preinstall(struct drm_device * dev) |
1da177e4 | 3537 | { |
fac5e23e | 3538 | struct drm_i915_private *dev_priv = to_i915(dev); |
9db4a9c7 | 3539 | int pipe; |
91e3738e | 3540 | |
055e393f | 3541 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 | 3542 | I915_WRITE(PIPESTAT(pipe), 0); |
a266c7d5 CW |
3543 | I915_WRITE16(IMR, 0xffff); |
3544 | I915_WRITE16(IER, 0x0); | |
3545 | POSTING_READ16(IER); | |
c2798b19 CW |
3546 | } |
3547 | ||
3548 | static int i8xx_irq_postinstall(struct drm_device *dev) | |
3549 | { | |
fac5e23e | 3550 | struct drm_i915_private *dev_priv = to_i915(dev); |
c2798b19 | 3551 | |
c2798b19 CW |
3552 | I915_WRITE16(EMR, |
3553 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); | |
3554 | ||
3555 | /* Unmask the interrupts that we always want on. */ | |
3556 | dev_priv->irq_mask = | |
3557 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3558 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3559 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
37ef01ab | 3560 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); |
c2798b19 CW |
3561 | I915_WRITE16(IMR, dev_priv->irq_mask); |
3562 | ||
3563 | I915_WRITE16(IER, | |
3564 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3565 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
c2798b19 CW |
3566 | I915_USER_INTERRUPT); |
3567 | POSTING_READ16(IER); | |
3568 | ||
379ef82d DV |
3569 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3570 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3571 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
3572 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3573 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 3574 | spin_unlock_irq(&dev_priv->irq_lock); |
379ef82d | 3575 | |
c2798b19 CW |
3576 | return 0; |
3577 | } | |
3578 | ||
5a21b665 DV |
3579 | /* |
3580 | * Returns true when a page flip has completed. | |
3581 | */ | |
3582 | static bool i8xx_handle_vblank(struct drm_i915_private *dev_priv, | |
3583 | int plane, int pipe, u32 iir) | |
3584 | { | |
3585 | u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); | |
3586 | ||
3587 | if (!intel_pipe_handle_vblank(dev_priv, pipe)) | |
3588 | return false; | |
3589 | ||
3590 | if ((iir & flip_pending) == 0) | |
3591 | goto check_page_flip; | |
3592 | ||
3593 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
3594 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3595 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3596 | * the flip is completed (no longer pending). Since this doesn't raise | |
3597 | * an interrupt per se, we watch for the change at vblank. | |
3598 | */ | |
3599 | if (I915_READ16(ISR) & flip_pending) | |
3600 | goto check_page_flip; | |
3601 | ||
3602 | intel_finish_page_flip_cs(dev_priv, pipe); | |
3603 | return true; | |
3604 | ||
3605 | check_page_flip: | |
3606 | intel_check_page_flip(dev_priv, pipe); | |
3607 | return false; | |
3608 | } | |
3609 | ||
ff1f525e | 3610 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
c2798b19 | 3611 | { |
45a83f84 | 3612 | struct drm_device *dev = arg; |
fac5e23e | 3613 | struct drm_i915_private *dev_priv = to_i915(dev); |
c2798b19 CW |
3614 | u16 iir, new_iir; |
3615 | u32 pipe_stats[2]; | |
c2798b19 CW |
3616 | int pipe; |
3617 | u16 flip_mask = | |
3618 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3619 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
1f814dac | 3620 | irqreturn_t ret; |
c2798b19 | 3621 | |
2dd2a883 ID |
3622 | if (!intel_irqs_enabled(dev_priv)) |
3623 | return IRQ_NONE; | |
3624 | ||
1f814dac ID |
3625 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
3626 | disable_rpm_wakeref_asserts(dev_priv); | |
3627 | ||
3628 | ret = IRQ_NONE; | |
c2798b19 CW |
3629 | iir = I915_READ16(IIR); |
3630 | if (iir == 0) | |
1f814dac | 3631 | goto out; |
c2798b19 CW |
3632 | |
3633 | while (iir & ~flip_mask) { | |
3634 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3635 | * have been cleared after the pipestat interrupt was received. | |
3636 | * It doesn't set the bit in iir again, but it still produces | |
3637 | * interrupts (for non-MSI). | |
3638 | */ | |
222c7f51 | 3639 | spin_lock(&dev_priv->irq_lock); |
c2798b19 | 3640 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 3641 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
c2798b19 | 3642 | |
055e393f | 3643 | for_each_pipe(dev_priv, pipe) { |
f0f59a00 | 3644 | i915_reg_t reg = PIPESTAT(pipe); |
c2798b19 CW |
3645 | pipe_stats[pipe] = I915_READ(reg); |
3646 | ||
3647 | /* | |
3648 | * Clear the PIPE*STAT regs before the IIR | |
3649 | */ | |
2d9d2b0b | 3650 | if (pipe_stats[pipe] & 0x8000ffff) |
c2798b19 | 3651 | I915_WRITE(reg, pipe_stats[pipe]); |
c2798b19 | 3652 | } |
222c7f51 | 3653 | spin_unlock(&dev_priv->irq_lock); |
c2798b19 CW |
3654 | |
3655 | I915_WRITE16(IIR, iir & ~flip_mask); | |
3656 | new_iir = I915_READ16(IIR); /* Flush posted writes */ | |
3657 | ||
c2798b19 | 3658 | if (iir & I915_USER_INTERRUPT) |
3b3f1650 | 3659 | notify_ring(dev_priv->engine[RCS]); |
c2798b19 | 3660 | |
055e393f | 3661 | for_each_pipe(dev_priv, pipe) { |
5a21b665 DV |
3662 | int plane = pipe; |
3663 | if (HAS_FBC(dev_priv)) | |
3664 | plane = !plane; | |
3665 | ||
3666 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && | |
3667 | i8xx_handle_vblank(dev_priv, plane, pipe, iir)) | |
3668 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
c2798b19 | 3669 | |
4356d586 | 3670 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
91d14251 | 3671 | i9xx_pipe_crc_irq_handler(dev_priv, pipe); |
2d9d2b0b | 3672 | |
1f7247c0 DV |
3673 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
3674 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
3675 | pipe); | |
4356d586 | 3676 | } |
c2798b19 CW |
3677 | |
3678 | iir = new_iir; | |
3679 | } | |
1f814dac ID |
3680 | ret = IRQ_HANDLED; |
3681 | ||
3682 | out: | |
3683 | enable_rpm_wakeref_asserts(dev_priv); | |
c2798b19 | 3684 | |
1f814dac | 3685 | return ret; |
c2798b19 CW |
3686 | } |
3687 | ||
3688 | static void i8xx_irq_uninstall(struct drm_device * dev) | |
3689 | { | |
fac5e23e | 3690 | struct drm_i915_private *dev_priv = to_i915(dev); |
c2798b19 CW |
3691 | int pipe; |
3692 | ||
055e393f | 3693 | for_each_pipe(dev_priv, pipe) { |
c2798b19 CW |
3694 | /* Clear enable bits; then clear status bits */ |
3695 | I915_WRITE(PIPESTAT(pipe), 0); | |
3696 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); | |
3697 | } | |
3698 | I915_WRITE16(IMR, 0xffff); | |
3699 | I915_WRITE16(IER, 0x0); | |
3700 | I915_WRITE16(IIR, I915_READ16(IIR)); | |
3701 | } | |
3702 | ||
a266c7d5 CW |
3703 | static void i915_irq_preinstall(struct drm_device * dev) |
3704 | { | |
fac5e23e | 3705 | struct drm_i915_private *dev_priv = to_i915(dev); |
a266c7d5 CW |
3706 | int pipe; |
3707 | ||
56b857a5 | 3708 | if (I915_HAS_HOTPLUG(dev_priv)) { |
0706f17c | 3709 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
a266c7d5 CW |
3710 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
3711 | } | |
3712 | ||
00d98ebd | 3713 | I915_WRITE16(HWSTAM, 0xeffe); |
055e393f | 3714 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
3715 | I915_WRITE(PIPESTAT(pipe), 0); |
3716 | I915_WRITE(IMR, 0xffffffff); | |
3717 | I915_WRITE(IER, 0x0); | |
3718 | POSTING_READ(IER); | |
3719 | } | |
3720 | ||
3721 | static int i915_irq_postinstall(struct drm_device *dev) | |
3722 | { | |
fac5e23e | 3723 | struct drm_i915_private *dev_priv = to_i915(dev); |
38bde180 | 3724 | u32 enable_mask; |
a266c7d5 | 3725 | |
38bde180 CW |
3726 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
3727 | ||
3728 | /* Unmask the interrupts that we always want on. */ | |
3729 | dev_priv->irq_mask = | |
3730 | ~(I915_ASLE_INTERRUPT | | |
3731 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3732 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3733 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
37ef01ab | 3734 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); |
38bde180 CW |
3735 | |
3736 | enable_mask = | |
3737 | I915_ASLE_INTERRUPT | | |
3738 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3739 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
38bde180 CW |
3740 | I915_USER_INTERRUPT; |
3741 | ||
56b857a5 | 3742 | if (I915_HAS_HOTPLUG(dev_priv)) { |
0706f17c | 3743 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
20afbda2 DV |
3744 | POSTING_READ(PORT_HOTPLUG_EN); |
3745 | ||
a266c7d5 CW |
3746 | /* Enable in IER... */ |
3747 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
3748 | /* and unmask in IMR */ | |
3749 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; | |
3750 | } | |
3751 | ||
a266c7d5 CW |
3752 | I915_WRITE(IMR, dev_priv->irq_mask); |
3753 | I915_WRITE(IER, enable_mask); | |
3754 | POSTING_READ(IER); | |
3755 | ||
91d14251 | 3756 | i915_enable_asle_pipestat(dev_priv); |
20afbda2 | 3757 | |
379ef82d DV |
3758 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3759 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3760 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
3761 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3762 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 3763 | spin_unlock_irq(&dev_priv->irq_lock); |
379ef82d | 3764 | |
20afbda2 DV |
3765 | return 0; |
3766 | } | |
3767 | ||
5a21b665 DV |
3768 | /* |
3769 | * Returns true when a page flip has completed. | |
3770 | */ | |
3771 | static bool i915_handle_vblank(struct drm_i915_private *dev_priv, | |
3772 | int plane, int pipe, u32 iir) | |
3773 | { | |
3774 | u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); | |
3775 | ||
3776 | if (!intel_pipe_handle_vblank(dev_priv, pipe)) | |
3777 | return false; | |
3778 | ||
3779 | if ((iir & flip_pending) == 0) | |
3780 | goto check_page_flip; | |
3781 | ||
3782 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
3783 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3784 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3785 | * the flip is completed (no longer pending). Since this doesn't raise | |
3786 | * an interrupt per se, we watch for the change at vblank. | |
3787 | */ | |
3788 | if (I915_READ(ISR) & flip_pending) | |
3789 | goto check_page_flip; | |
3790 | ||
3791 | intel_finish_page_flip_cs(dev_priv, pipe); | |
3792 | return true; | |
3793 | ||
3794 | check_page_flip: | |
3795 | intel_check_page_flip(dev_priv, pipe); | |
3796 | return false; | |
3797 | } | |
3798 | ||
ff1f525e | 3799 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
a266c7d5 | 3800 | { |
45a83f84 | 3801 | struct drm_device *dev = arg; |
fac5e23e | 3802 | struct drm_i915_private *dev_priv = to_i915(dev); |
8291ee90 | 3803 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
38bde180 CW |
3804 | u32 flip_mask = |
3805 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3806 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
38bde180 | 3807 | int pipe, ret = IRQ_NONE; |
a266c7d5 | 3808 | |
2dd2a883 ID |
3809 | if (!intel_irqs_enabled(dev_priv)) |
3810 | return IRQ_NONE; | |
3811 | ||
1f814dac ID |
3812 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
3813 | disable_rpm_wakeref_asserts(dev_priv); | |
3814 | ||
a266c7d5 | 3815 | iir = I915_READ(IIR); |
38bde180 CW |
3816 | do { |
3817 | bool irq_received = (iir & ~flip_mask) != 0; | |
8291ee90 | 3818 | bool blc_event = false; |
a266c7d5 CW |
3819 | |
3820 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3821 | * have been cleared after the pipestat interrupt was received. | |
3822 | * It doesn't set the bit in iir again, but it still produces | |
3823 | * interrupts (for non-MSI). | |
3824 | */ | |
222c7f51 | 3825 | spin_lock(&dev_priv->irq_lock); |
a266c7d5 | 3826 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 3827 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
a266c7d5 | 3828 | |
055e393f | 3829 | for_each_pipe(dev_priv, pipe) { |
f0f59a00 | 3830 | i915_reg_t reg = PIPESTAT(pipe); |
a266c7d5 CW |
3831 | pipe_stats[pipe] = I915_READ(reg); |
3832 | ||
38bde180 | 3833 | /* Clear the PIPE*STAT regs before the IIR */ |
a266c7d5 | 3834 | if (pipe_stats[pipe] & 0x8000ffff) { |
a266c7d5 | 3835 | I915_WRITE(reg, pipe_stats[pipe]); |
38bde180 | 3836 | irq_received = true; |
a266c7d5 CW |
3837 | } |
3838 | } | |
222c7f51 | 3839 | spin_unlock(&dev_priv->irq_lock); |
a266c7d5 CW |
3840 | |
3841 | if (!irq_received) | |
3842 | break; | |
3843 | ||
a266c7d5 | 3844 | /* Consume port. Then clear IIR or we'll miss events */ |
91d14251 | 3845 | if (I915_HAS_HOTPLUG(dev_priv) && |
1ae3c34c VS |
3846 | iir & I915_DISPLAY_PORT_INTERRUPT) { |
3847 | u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv); | |
3848 | if (hotplug_status) | |
91d14251 | 3849 | i9xx_hpd_irq_handler(dev_priv, hotplug_status); |
1ae3c34c | 3850 | } |
a266c7d5 | 3851 | |
38bde180 | 3852 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
3853 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
3854 | ||
a266c7d5 | 3855 | if (iir & I915_USER_INTERRUPT) |
3b3f1650 | 3856 | notify_ring(dev_priv->engine[RCS]); |
a266c7d5 | 3857 | |
055e393f | 3858 | for_each_pipe(dev_priv, pipe) { |
5a21b665 DV |
3859 | int plane = pipe; |
3860 | if (HAS_FBC(dev_priv)) | |
3861 | plane = !plane; | |
3862 | ||
3863 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && | |
3864 | i915_handle_vblank(dev_priv, plane, pipe, iir)) | |
3865 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
a266c7d5 CW |
3866 | |
3867 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
3868 | blc_event = true; | |
4356d586 DV |
3869 | |
3870 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
91d14251 | 3871 | i9xx_pipe_crc_irq_handler(dev_priv, pipe); |
2d9d2b0b | 3872 | |
1f7247c0 DV |
3873 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
3874 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
3875 | pipe); | |
a266c7d5 CW |
3876 | } |
3877 | ||
a266c7d5 | 3878 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
91d14251 | 3879 | intel_opregion_asle_intr(dev_priv); |
a266c7d5 CW |
3880 | |
3881 | /* With MSI, interrupts are only generated when iir | |
3882 | * transitions from zero to nonzero. If another bit got | |
3883 | * set while we were handling the existing iir bits, then | |
3884 | * we would never get another interrupt. | |
3885 | * | |
3886 | * This is fine on non-MSI as well, as if we hit this path | |
3887 | * we avoid exiting the interrupt handler only to generate | |
3888 | * another one. | |
3889 | * | |
3890 | * Note that for MSI this could cause a stray interrupt report | |
3891 | * if an interrupt landed in the time between writing IIR and | |
3892 | * the posting read. This should be rare enough to never | |
3893 | * trigger the 99% of 100,000 interrupts test for disabling | |
3894 | * stray interrupts. | |
3895 | */ | |
38bde180 | 3896 | ret = IRQ_HANDLED; |
a266c7d5 | 3897 | iir = new_iir; |
38bde180 | 3898 | } while (iir & ~flip_mask); |
a266c7d5 | 3899 | |
1f814dac ID |
3900 | enable_rpm_wakeref_asserts(dev_priv); |
3901 | ||
a266c7d5 CW |
3902 | return ret; |
3903 | } | |
3904 | ||
3905 | static void i915_irq_uninstall(struct drm_device * dev) | |
3906 | { | |
fac5e23e | 3907 | struct drm_i915_private *dev_priv = to_i915(dev); |
a266c7d5 CW |
3908 | int pipe; |
3909 | ||
56b857a5 | 3910 | if (I915_HAS_HOTPLUG(dev_priv)) { |
0706f17c | 3911 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
a266c7d5 CW |
3912 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
3913 | } | |
3914 | ||
00d98ebd | 3915 | I915_WRITE16(HWSTAM, 0xffff); |
055e393f | 3916 | for_each_pipe(dev_priv, pipe) { |
55b39755 | 3917 | /* Clear enable bits; then clear status bits */ |
a266c7d5 | 3918 | I915_WRITE(PIPESTAT(pipe), 0); |
55b39755 CW |
3919 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
3920 | } | |
a266c7d5 CW |
3921 | I915_WRITE(IMR, 0xffffffff); |
3922 | I915_WRITE(IER, 0x0); | |
3923 | ||
a266c7d5 CW |
3924 | I915_WRITE(IIR, I915_READ(IIR)); |
3925 | } | |
3926 | ||
3927 | static void i965_irq_preinstall(struct drm_device * dev) | |
3928 | { | |
fac5e23e | 3929 | struct drm_i915_private *dev_priv = to_i915(dev); |
a266c7d5 CW |
3930 | int pipe; |
3931 | ||
0706f17c | 3932 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
adca4730 | 3933 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
a266c7d5 CW |
3934 | |
3935 | I915_WRITE(HWSTAM, 0xeffe); | |
055e393f | 3936 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
3937 | I915_WRITE(PIPESTAT(pipe), 0); |
3938 | I915_WRITE(IMR, 0xffffffff); | |
3939 | I915_WRITE(IER, 0x0); | |
3940 | POSTING_READ(IER); | |
3941 | } | |
3942 | ||
3943 | static int i965_irq_postinstall(struct drm_device *dev) | |
3944 | { | |
fac5e23e | 3945 | struct drm_i915_private *dev_priv = to_i915(dev); |
bbba0a97 | 3946 | u32 enable_mask; |
a266c7d5 CW |
3947 | u32 error_mask; |
3948 | ||
a266c7d5 | 3949 | /* Unmask the interrupts that we always want on. */ |
bbba0a97 | 3950 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
adca4730 | 3951 | I915_DISPLAY_PORT_INTERRUPT | |
bbba0a97 CW |
3952 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
3953 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3954 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3955 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3956 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3957 | ||
3958 | enable_mask = ~dev_priv->irq_mask; | |
21ad8330 VS |
3959 | enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
3960 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); | |
bbba0a97 CW |
3961 | enable_mask |= I915_USER_INTERRUPT; |
3962 | ||
91d14251 | 3963 | if (IS_G4X(dev_priv)) |
bbba0a97 | 3964 | enable_mask |= I915_BSD_USER_INTERRUPT; |
a266c7d5 | 3965 | |
b79480ba DV |
3966 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3967 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3968 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
3969 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
3970 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
3971 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 3972 | spin_unlock_irq(&dev_priv->irq_lock); |
a266c7d5 | 3973 | |
a266c7d5 CW |
3974 | /* |
3975 | * Enable some error detection, note the instruction error mask | |
3976 | * bit is reserved, so we leave it masked. | |
3977 | */ | |
91d14251 | 3978 | if (IS_G4X(dev_priv)) { |
a266c7d5 CW |
3979 | error_mask = ~(GM45_ERROR_PAGE_TABLE | |
3980 | GM45_ERROR_MEM_PRIV | | |
3981 | GM45_ERROR_CP_PRIV | | |
3982 | I915_ERROR_MEMORY_REFRESH); | |
3983 | } else { | |
3984 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
3985 | I915_ERROR_MEMORY_REFRESH); | |
3986 | } | |
3987 | I915_WRITE(EMR, error_mask); | |
3988 | ||
3989 | I915_WRITE(IMR, dev_priv->irq_mask); | |
3990 | I915_WRITE(IER, enable_mask); | |
3991 | POSTING_READ(IER); | |
3992 | ||
0706f17c | 3993 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
20afbda2 DV |
3994 | POSTING_READ(PORT_HOTPLUG_EN); |
3995 | ||
91d14251 | 3996 | i915_enable_asle_pipestat(dev_priv); |
20afbda2 DV |
3997 | |
3998 | return 0; | |
3999 | } | |
4000 | ||
91d14251 | 4001 | static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv) |
20afbda2 | 4002 | { |
20afbda2 DV |
4003 | u32 hotplug_en; |
4004 | ||
b5ea2d56 DV |
4005 | assert_spin_locked(&dev_priv->irq_lock); |
4006 | ||
778eb334 VS |
4007 | /* Note HDMI and DP share hotplug bits */ |
4008 | /* enable bits are the same for all generations */ | |
91d14251 | 4009 | hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915); |
778eb334 VS |
4010 | /* Programming the CRT detection parameters tends |
4011 | to generate a spurious hotplug event about three | |
4012 | seconds later. So just do it once. | |
4013 | */ | |
91d14251 | 4014 | if (IS_G4X(dev_priv)) |
778eb334 | 4015 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; |
778eb334 VS |
4016 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
4017 | ||
4018 | /* Ignore TV since it's buggy */ | |
0706f17c | 4019 | i915_hotplug_interrupt_update_locked(dev_priv, |
f9e3dc78 JN |
4020 | HOTPLUG_INT_EN_MASK | |
4021 | CRT_HOTPLUG_VOLTAGE_COMPARE_MASK | | |
4022 | CRT_HOTPLUG_ACTIVATION_PERIOD_64, | |
4023 | hotplug_en); | |
a266c7d5 CW |
4024 | } |
4025 | ||
ff1f525e | 4026 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
a266c7d5 | 4027 | { |
45a83f84 | 4028 | struct drm_device *dev = arg; |
fac5e23e | 4029 | struct drm_i915_private *dev_priv = to_i915(dev); |
a266c7d5 CW |
4030 | u32 iir, new_iir; |
4031 | u32 pipe_stats[I915_MAX_PIPES]; | |
a266c7d5 | 4032 | int ret = IRQ_NONE, pipe; |
21ad8330 VS |
4033 | u32 flip_mask = |
4034 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4035 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
a266c7d5 | 4036 | |
2dd2a883 ID |
4037 | if (!intel_irqs_enabled(dev_priv)) |
4038 | return IRQ_NONE; | |
4039 | ||
1f814dac ID |
4040 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
4041 | disable_rpm_wakeref_asserts(dev_priv); | |
4042 | ||
a266c7d5 CW |
4043 | iir = I915_READ(IIR); |
4044 | ||
a266c7d5 | 4045 | for (;;) { |
501e01d7 | 4046 | bool irq_received = (iir & ~flip_mask) != 0; |
2c8ba29f CW |
4047 | bool blc_event = false; |
4048 | ||
a266c7d5 CW |
4049 | /* Can't rely on pipestat interrupt bit in iir as it might |
4050 | * have been cleared after the pipestat interrupt was received. | |
4051 | * It doesn't set the bit in iir again, but it still produces | |
4052 | * interrupts (for non-MSI). | |
4053 | */ | |
222c7f51 | 4054 | spin_lock(&dev_priv->irq_lock); |
a266c7d5 | 4055 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 4056 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
a266c7d5 | 4057 | |
055e393f | 4058 | for_each_pipe(dev_priv, pipe) { |
f0f59a00 | 4059 | i915_reg_t reg = PIPESTAT(pipe); |
a266c7d5 CW |
4060 | pipe_stats[pipe] = I915_READ(reg); |
4061 | ||
4062 | /* | |
4063 | * Clear the PIPE*STAT regs before the IIR | |
4064 | */ | |
4065 | if (pipe_stats[pipe] & 0x8000ffff) { | |
a266c7d5 | 4066 | I915_WRITE(reg, pipe_stats[pipe]); |
501e01d7 | 4067 | irq_received = true; |
a266c7d5 CW |
4068 | } |
4069 | } | |
222c7f51 | 4070 | spin_unlock(&dev_priv->irq_lock); |
a266c7d5 CW |
4071 | |
4072 | if (!irq_received) | |
4073 | break; | |
4074 | ||
4075 | ret = IRQ_HANDLED; | |
4076 | ||
4077 | /* Consume port. Then clear IIR or we'll miss events */ | |
1ae3c34c VS |
4078 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { |
4079 | u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv); | |
4080 | if (hotplug_status) | |
91d14251 | 4081 | i9xx_hpd_irq_handler(dev_priv, hotplug_status); |
1ae3c34c | 4082 | } |
a266c7d5 | 4083 | |
21ad8330 | 4084 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
4085 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
4086 | ||
a266c7d5 | 4087 | if (iir & I915_USER_INTERRUPT) |
3b3f1650 | 4088 | notify_ring(dev_priv->engine[RCS]); |
a266c7d5 | 4089 | if (iir & I915_BSD_USER_INTERRUPT) |
3b3f1650 | 4090 | notify_ring(dev_priv->engine[VCS]); |
a266c7d5 | 4091 | |
055e393f | 4092 | for_each_pipe(dev_priv, pipe) { |
5a21b665 DV |
4093 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
4094 | i915_handle_vblank(dev_priv, pipe, pipe, iir)) | |
4095 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); | |
a266c7d5 CW |
4096 | |
4097 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
4098 | blc_event = true; | |
4356d586 DV |
4099 | |
4100 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
91d14251 | 4101 | i9xx_pipe_crc_irq_handler(dev_priv, pipe); |
a266c7d5 | 4102 | |
1f7247c0 DV |
4103 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
4104 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
2d9d2b0b | 4105 | } |
a266c7d5 CW |
4106 | |
4107 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | |
91d14251 | 4108 | intel_opregion_asle_intr(dev_priv); |
a266c7d5 | 4109 | |
515ac2bb | 4110 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
91d14251 | 4111 | gmbus_irq_handler(dev_priv); |
515ac2bb | 4112 | |
a266c7d5 CW |
4113 | /* With MSI, interrupts are only generated when iir |
4114 | * transitions from zero to nonzero. If another bit got | |
4115 | * set while we were handling the existing iir bits, then | |
4116 | * we would never get another interrupt. | |
4117 | * | |
4118 | * This is fine on non-MSI as well, as if we hit this path | |
4119 | * we avoid exiting the interrupt handler only to generate | |
4120 | * another one. | |
4121 | * | |
4122 | * Note that for MSI this could cause a stray interrupt report | |
4123 | * if an interrupt landed in the time between writing IIR and | |
4124 | * the posting read. This should be rare enough to never | |
4125 | * trigger the 99% of 100,000 interrupts test for disabling | |
4126 | * stray interrupts. | |
4127 | */ | |
4128 | iir = new_iir; | |
4129 | } | |
4130 | ||
1f814dac ID |
4131 | enable_rpm_wakeref_asserts(dev_priv); |
4132 | ||
a266c7d5 CW |
4133 | return ret; |
4134 | } | |
4135 | ||
4136 | static void i965_irq_uninstall(struct drm_device * dev) | |
4137 | { | |
fac5e23e | 4138 | struct drm_i915_private *dev_priv = to_i915(dev); |
a266c7d5 CW |
4139 | int pipe; |
4140 | ||
4141 | if (!dev_priv) | |
4142 | return; | |
4143 | ||
0706f17c | 4144 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
adca4730 | 4145 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
a266c7d5 CW |
4146 | |
4147 | I915_WRITE(HWSTAM, 0xffffffff); | |
055e393f | 4148 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4149 | I915_WRITE(PIPESTAT(pipe), 0); |
4150 | I915_WRITE(IMR, 0xffffffff); | |
4151 | I915_WRITE(IER, 0x0); | |
4152 | ||
055e393f | 4153 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4154 | I915_WRITE(PIPESTAT(pipe), |
4155 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); | |
4156 | I915_WRITE(IIR, I915_READ(IIR)); | |
4157 | } | |
4158 | ||
fca52a55 DV |
4159 | /** |
4160 | * intel_irq_init - initializes irq support | |
4161 | * @dev_priv: i915 device instance | |
4162 | * | |
4163 | * This function initializes all the irq support including work items, timers | |
4164 | * and all the vtables. It does not setup the interrupt itself though. | |
4165 | */ | |
b963291c | 4166 | void intel_irq_init(struct drm_i915_private *dev_priv) |
f71d4af4 | 4167 | { |
91c8a326 | 4168 | struct drm_device *dev = &dev_priv->drm; |
8b2e326d | 4169 | |
77913b39 JN |
4170 | intel_hpd_init_work(dev_priv); |
4171 | ||
c6a828d3 | 4172 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
a4da4fa4 | 4173 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
8b2e326d | 4174 | |
4805fe82 | 4175 | if (HAS_GUC_SCHED(dev_priv)) |
26705e20 SAK |
4176 | dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT; |
4177 | ||
a6706b45 | 4178 | /* Let's track the enabled rps events */ |
666a4537 | 4179 | if (IS_VALLEYVIEW(dev_priv)) |
6c65a587 | 4180 | /* WaGsvRC0ResidencyMethod:vlv */ |
6f4b12f8 | 4181 | dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED; |
31685c25 D |
4182 | else |
4183 | dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; | |
a6706b45 | 4184 | |
1800ad25 SAK |
4185 | dev_priv->rps.pm_intr_keep = 0; |
4186 | ||
4187 | /* | |
4188 | * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer | |
4189 | * if GEN6_PM_UP_EI_EXPIRED is masked. | |
4190 | * | |
4191 | * TODO: verify if this can be reproduced on VLV,CHV. | |
4192 | */ | |
4193 | if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv)) | |
4194 | dev_priv->rps.pm_intr_keep |= GEN6_PM_RP_UP_EI_EXPIRED; | |
4195 | ||
4196 | if (INTEL_INFO(dev_priv)->gen >= 8) | |
b20e3cfe | 4197 | dev_priv->rps.pm_intr_keep |= GEN8_PMINTR_REDIRECT_TO_GUC; |
1800ad25 | 4198 | |
b963291c | 4199 | if (IS_GEN2(dev_priv)) { |
4194c088 | 4200 | /* Gen2 doesn't have a hardware frame counter */ |
4cdb83ec | 4201 | dev->max_vblank_count = 0; |
4194c088 | 4202 | dev->driver->get_vblank_counter = drm_vblank_no_hw_counter; |
b963291c | 4203 | } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { |
f71d4af4 | 4204 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
fd8f507c | 4205 | dev->driver->get_vblank_counter = g4x_get_vblank_counter; |
391f75e2 VS |
4206 | } else { |
4207 | dev->driver->get_vblank_counter = i915_get_vblank_counter; | |
4208 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
f71d4af4 JB |
4209 | } |
4210 | ||
21da2700 VS |
4211 | /* |
4212 | * Opt out of the vblank disable timer on everything except gen2. | |
4213 | * Gen2 doesn't have a hardware frame counter and so depends on | |
4214 | * vblank interrupts to produce sane vblank seuquence numbers. | |
4215 | */ | |
b963291c | 4216 | if (!IS_GEN2(dev_priv)) |
21da2700 VS |
4217 | dev->vblank_disable_immediate = true; |
4218 | ||
f3a5c3f6 DV |
4219 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; |
4220 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; | |
f71d4af4 | 4221 | |
b963291c | 4222 | if (IS_CHERRYVIEW(dev_priv)) { |
43f328d7 VS |
4223 | dev->driver->irq_handler = cherryview_irq_handler; |
4224 | dev->driver->irq_preinstall = cherryview_irq_preinstall; | |
4225 | dev->driver->irq_postinstall = cherryview_irq_postinstall; | |
4226 | dev->driver->irq_uninstall = cherryview_irq_uninstall; | |
86e83e35 CW |
4227 | dev->driver->enable_vblank = i965_enable_vblank; |
4228 | dev->driver->disable_vblank = i965_disable_vblank; | |
43f328d7 | 4229 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
b963291c | 4230 | } else if (IS_VALLEYVIEW(dev_priv)) { |
7e231dbe JB |
4231 | dev->driver->irq_handler = valleyview_irq_handler; |
4232 | dev->driver->irq_preinstall = valleyview_irq_preinstall; | |
4233 | dev->driver->irq_postinstall = valleyview_irq_postinstall; | |
4234 | dev->driver->irq_uninstall = valleyview_irq_uninstall; | |
86e83e35 CW |
4235 | dev->driver->enable_vblank = i965_enable_vblank; |
4236 | dev->driver->disable_vblank = i965_disable_vblank; | |
fa00abe0 | 4237 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
b963291c | 4238 | } else if (INTEL_INFO(dev_priv)->gen >= 8) { |
abd58f01 | 4239 | dev->driver->irq_handler = gen8_irq_handler; |
723761b8 | 4240 | dev->driver->irq_preinstall = gen8_irq_reset; |
abd58f01 BW |
4241 | dev->driver->irq_postinstall = gen8_irq_postinstall; |
4242 | dev->driver->irq_uninstall = gen8_irq_uninstall; | |
4243 | dev->driver->enable_vblank = gen8_enable_vblank; | |
4244 | dev->driver->disable_vblank = gen8_disable_vblank; | |
e2d214ae | 4245 | if (IS_BROXTON(dev_priv)) |
e0a20ad7 | 4246 | dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup; |
6e266956 | 4247 | else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv)) |
6dbf30ce VS |
4248 | dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup; |
4249 | else | |
3a3b3c7d | 4250 | dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; |
6e266956 | 4251 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
f71d4af4 | 4252 | dev->driver->irq_handler = ironlake_irq_handler; |
723761b8 | 4253 | dev->driver->irq_preinstall = ironlake_irq_reset; |
f71d4af4 JB |
4254 | dev->driver->irq_postinstall = ironlake_irq_postinstall; |
4255 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
4256 | dev->driver->enable_vblank = ironlake_enable_vblank; | |
4257 | dev->driver->disable_vblank = ironlake_disable_vblank; | |
23bb4cb5 | 4258 | dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; |
f71d4af4 | 4259 | } else { |
7e22dbbb | 4260 | if (IS_GEN2(dev_priv)) { |
c2798b19 CW |
4261 | dev->driver->irq_preinstall = i8xx_irq_preinstall; |
4262 | dev->driver->irq_postinstall = i8xx_irq_postinstall; | |
4263 | dev->driver->irq_handler = i8xx_irq_handler; | |
4264 | dev->driver->irq_uninstall = i8xx_irq_uninstall; | |
86e83e35 CW |
4265 | dev->driver->enable_vblank = i8xx_enable_vblank; |
4266 | dev->driver->disable_vblank = i8xx_disable_vblank; | |
7e22dbbb | 4267 | } else if (IS_GEN3(dev_priv)) { |
a266c7d5 CW |
4268 | dev->driver->irq_preinstall = i915_irq_preinstall; |
4269 | dev->driver->irq_postinstall = i915_irq_postinstall; | |
4270 | dev->driver->irq_uninstall = i915_irq_uninstall; | |
4271 | dev->driver->irq_handler = i915_irq_handler; | |
86e83e35 CW |
4272 | dev->driver->enable_vblank = i8xx_enable_vblank; |
4273 | dev->driver->disable_vblank = i8xx_disable_vblank; | |
c2798b19 | 4274 | } else { |
a266c7d5 CW |
4275 | dev->driver->irq_preinstall = i965_irq_preinstall; |
4276 | dev->driver->irq_postinstall = i965_irq_postinstall; | |
4277 | dev->driver->irq_uninstall = i965_irq_uninstall; | |
4278 | dev->driver->irq_handler = i965_irq_handler; | |
86e83e35 CW |
4279 | dev->driver->enable_vblank = i965_enable_vblank; |
4280 | dev->driver->disable_vblank = i965_disable_vblank; | |
c2798b19 | 4281 | } |
778eb334 VS |
4282 | if (I915_HAS_HOTPLUG(dev_priv)) |
4283 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; | |
f71d4af4 JB |
4284 | } |
4285 | } | |
20afbda2 | 4286 | |
fca52a55 DV |
4287 | /** |
4288 | * intel_irq_install - enables the hardware interrupt | |
4289 | * @dev_priv: i915 device instance | |
4290 | * | |
4291 | * This function enables the hardware interrupt handling, but leaves the hotplug | |
4292 | * handling still disabled. It is called after intel_irq_init(). | |
4293 | * | |
4294 | * In the driver load and resume code we need working interrupts in a few places | |
4295 | * but don't want to deal with the hassle of concurrent probe and hotplug | |
4296 | * workers. Hence the split into this two-stage approach. | |
4297 | */ | |
2aeb7d3a DV |
4298 | int intel_irq_install(struct drm_i915_private *dev_priv) |
4299 | { | |
4300 | /* | |
4301 | * We enable some interrupt sources in our postinstall hooks, so mark | |
4302 | * interrupts as enabled _before_ actually enabling them to avoid | |
4303 | * special cases in our ordering checks. | |
4304 | */ | |
4305 | dev_priv->pm.irqs_enabled = true; | |
4306 | ||
91c8a326 | 4307 | return drm_irq_install(&dev_priv->drm, dev_priv->drm.pdev->irq); |
2aeb7d3a DV |
4308 | } |
4309 | ||
fca52a55 DV |
4310 | /** |
4311 | * intel_irq_uninstall - finilizes all irq handling | |
4312 | * @dev_priv: i915 device instance | |
4313 | * | |
4314 | * This stops interrupt and hotplug handling and unregisters and frees all | |
4315 | * resources acquired in the init functions. | |
4316 | */ | |
2aeb7d3a DV |
4317 | void intel_irq_uninstall(struct drm_i915_private *dev_priv) |
4318 | { | |
91c8a326 | 4319 | drm_irq_uninstall(&dev_priv->drm); |
2aeb7d3a DV |
4320 | intel_hpd_cancel_work(dev_priv); |
4321 | dev_priv->pm.irqs_enabled = false; | |
4322 | } | |
4323 | ||
fca52a55 DV |
4324 | /** |
4325 | * intel_runtime_pm_disable_interrupts - runtime interrupt disabling | |
4326 | * @dev_priv: i915 device instance | |
4327 | * | |
4328 | * This function is used to disable interrupts at runtime, both in the runtime | |
4329 | * pm and the system suspend/resume code. | |
4330 | */ | |
b963291c | 4331 | void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv) |
c67a470b | 4332 | { |
91c8a326 | 4333 | dev_priv->drm.driver->irq_uninstall(&dev_priv->drm); |
2aeb7d3a | 4334 | dev_priv->pm.irqs_enabled = false; |
91c8a326 | 4335 | synchronize_irq(dev_priv->drm.irq); |
c67a470b PZ |
4336 | } |
4337 | ||
fca52a55 DV |
4338 | /** |
4339 | * intel_runtime_pm_enable_interrupts - runtime interrupt enabling | |
4340 | * @dev_priv: i915 device instance | |
4341 | * | |
4342 | * This function is used to enable interrupts at runtime, both in the runtime | |
4343 | * pm and the system suspend/resume code. | |
4344 | */ | |
b963291c | 4345 | void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv) |
c67a470b | 4346 | { |
2aeb7d3a | 4347 | dev_priv->pm.irqs_enabled = true; |
91c8a326 CW |
4348 | dev_priv->drm.driver->irq_preinstall(&dev_priv->drm); |
4349 | dev_priv->drm.driver->irq_postinstall(&dev_priv->drm); | |
c67a470b | 4350 | } |