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drm/i915: move dri1 dungeon out of dev_priv
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/i915_drm.h>
1da177e4 35#include "i915_drv.h"
1c5d22f7 36#include "i915_trace.h"
79e53945 37#include "intel_drv.h"
1da177e4 38
036a4a7d 39/* For display hotplug interrupt */
995b6762 40static void
f2b115e6 41ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 42{
1ec14ad3
CW		 43 if ((dev_priv->irq_mask & mask) != 0) {
44 dev_priv->irq_mask &= ~mask;
45 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 46 POSTING_READ(DEIMR);
036a4a7d
ZW		 47 }
48}
49
50static inline void
f2b115e6 51ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 52{
1ec14ad3
CW		 53 if ((dev_priv->irq_mask & mask) != mask) {
54 dev_priv->irq_mask |= mask;
55 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 56 POSTING_READ(DEIMR);
036a4a7d
ZW		 57 }
58}
59
7c463586
KP		 60void
61i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
62{
63 if ((dev_priv->pipestat[pipe] & mask) != mask) {
9db4a9c7 64 u32 reg = PIPESTAT(pipe);
7c463586
KP		 65
66 dev_priv->pipestat[pipe] |= mask;
67 /* Enable the interrupt, clear any pending status */
68 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
3143a2bf 69 POSTING_READ(reg);
7c463586
KP		 70 }
71}
72
73void
74i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
75{
76 if ((dev_priv->pipestat[pipe] & mask) != 0) {
9db4a9c7 77 u32 reg = PIPESTAT(pipe);
7c463586
KP		 78
79 dev_priv->pipestat[pipe] &= ~mask;
80 I915_WRITE(reg, dev_priv->pipestat[pipe]);
3143a2bf 81 POSTING_READ(reg);
7c463586
KP		 82 }
83}
84
01c66889
ZY		 85/**
86 * intel_enable_asle - enable ASLE interrupt for OpRegion
87 */
1ec14ad3 88void intel_enable_asle(struct drm_device *dev)
01c66889 89{
1ec14ad3
CW		 90 drm_i915_private_t *dev_priv = dev->dev_private;
91 unsigned long irqflags;
92
7e231dbe
JB		 93 /* FIXME: opregion/asle for VLV */
94 if (IS_VALLEYVIEW(dev))
95 return;
96
1ec14ad3 97 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 98
c619eed4 99 if (HAS_PCH_SPLIT(dev))
f2b115e6 100 ironlake_enable_display_irq(dev_priv, DE_GSE);
edcb49ca 101 else {
01c66889 102 i915_enable_pipestat(dev_priv, 1,
d874bcff 103 PIPE_LEGACY_BLC_EVENT_ENABLE);
a6c45cf0 104 if (INTEL_INFO(dev)->gen >= 4)
edcb49ca 105 i915_enable_pipestat(dev_priv, 0,
d874bcff 106 PIPE_LEGACY_BLC_EVENT_ENABLE);
edcb49ca 107 }
1ec14ad3
CW		 108
109 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 110}
111
0a3e67a4
JB		 112/**
113 * i915_pipe_enabled - check if a pipe is enabled
114 * @dev: DRM device
115 * @pipe: pipe to check
116 *
117 * Reading certain registers when the pipe is disabled can hang the chip.
118 * Use this routine to make sure the PLL is running and the pipe is active
119 * before reading such registers if unsure.
120 */
121static int
122i915_pipe_enabled(struct drm_device *dev, int pipe)
123{
124 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
702e7a56
PZ		 125 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
126 pipe);
127
128 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
0a3e67a4
JB		 129}
130
42f52ef8
KP		 131/* Called from drm generic code, passed a 'crtc', which
132 * we use as a pipe index
133 */
f71d4af4 134static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 135{
136 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
137 unsigned long high_frame;
138 unsigned long low_frame;
5eddb70b 139 u32 high1, high2, low;
0a3e67a4
JB		 140
141 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 142 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 143 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 144 return 0;
145 }
146
9db4a9c7
JB		 147 high_frame = PIPEFRAME(pipe);
148 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 149
0a3e67a4
JB		 150 /*
151 * High & low register fields aren't synchronized, so make sure
152 * we get a low value that's stable across two reads of the high
153 * register.
154 */
155 do {
5eddb70b
CW		 156 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
157 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
158 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 159 } while (high1 != high2);
160
5eddb70b
CW		 161 high1 >>= PIPE_FRAME_HIGH_SHIFT;
162 low >>= PIPE_FRAME_LOW_SHIFT;
163 return (high1 << 8) | low;
0a3e67a4
JB		 164}
165
f71d4af4 166static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 167{
168 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 169 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 170
171 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 172 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 173 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 174 return 0;
175 }
176
177 return I915_READ(reg);
178}
179
f71d4af4 180static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 181 int *vpos, int *hpos)
182{
183 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
184 u32 vbl = 0, position = 0;
185 int vbl_start, vbl_end, htotal, vtotal;
186 bool in_vbl = true;
187 int ret = 0;
fe2b8f9d
PZ		 188 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
189 pipe);
0af7e4df
MK		 190
191 if (!i915_pipe_enabled(dev, pipe)) {
192 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 193 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 194 return 0;
195 }
196
197 /* Get vtotal. */
fe2b8f9d 198 vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 199
200 if (INTEL_INFO(dev)->gen >= 4) {
201 /* No obvious pixelcount register. Only query vertical
202 * scanout position from Display scan line register.
203 */
204 position = I915_READ(PIPEDSL(pipe));
205
206 /* Decode into vertical scanout position. Don't have
207 * horizontal scanout position.
208 */
209 *vpos = position & 0x1fff;
210 *hpos = 0;
211 } else {
212 /* Have access to pixelcount since start of frame.
213 * We can split this into vertical and horizontal
214 * scanout position.
215 */
216 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
217
fe2b8f9d 218 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 219 *vpos = position / htotal;
220 *hpos = position - (*vpos * htotal);
221 }
222
223 /* Query vblank area. */
fe2b8f9d 224 vbl = I915_READ(VBLANK(cpu_transcoder));
0af7e4df
MK		 225
226 /* Test position against vblank region. */
227 vbl_start = vbl & 0x1fff;
228 vbl_end = (vbl >> 16) & 0x1fff;
229
230 if ((*vpos < vbl_start) || (*vpos > vbl_end))
231 in_vbl = false;
232
233 /* Inside "upper part" of vblank area? Apply corrective offset: */
234 if (in_vbl && (*vpos >= vbl_start))
235 *vpos = *vpos - vtotal;
236
237 /* Readouts valid? */
238 if (vbl > 0)
239 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
240
241 /* In vblank? */
242 if (in_vbl)
243 ret |= DRM_SCANOUTPOS_INVBL;
244
245 return ret;
246}
247
f71d4af4 248static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 249 int *max_error,
250 struct timeval *vblank_time,
251 unsigned flags)
252{
4041b853
CW		 253 struct drm_i915_private *dev_priv = dev->dev_private;
254 struct drm_crtc *crtc;
0af7e4df 255
4041b853
CW		 256 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
257 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 258 return -EINVAL;
259 }
260
261 /* Get drm_crtc to timestamp: */
4041b853
CW		 262 crtc = intel_get_crtc_for_pipe(dev, pipe);
263 if (crtc == NULL) {
264 DRM_ERROR("Invalid crtc %d\n", pipe);
265 return -EINVAL;
266 }
267
268 if (!crtc->enabled) {
269 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
270 return -EBUSY;
271 }
0af7e4df
MK		 272
273 /* Helper routine in DRM core does all the work: */
4041b853
CW		 274 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
275 vblank_time, flags,
276 crtc);
0af7e4df
MK		 277}
278
5ca58282
JB		 279/*
280 * Handle hotplug events outside the interrupt handler proper.
281 */
282static void i915_hotplug_work_func(struct work_struct *work)
283{
284 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
285 hotplug_work);
286 struct drm_device *dev = dev_priv->dev;
c31c4ba3 287 struct drm_mode_config *mode_config = &dev->mode_config;
4ef69c7a
CW		 288 struct intel_encoder *encoder;
289
a65e34c7 290 mutex_lock(&mode_config->mutex);
e67189ab
JB		 291 DRM_DEBUG_KMS("running encoder hotplug functions\n");
292
4ef69c7a
CW		 293 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
294 if (encoder->hot_plug)
295 encoder->hot_plug(encoder);
296
40ee3381
KP		 297 mutex_unlock(&mode_config->mutex);
298
5ca58282 299 /* Just fire off a uevent and let userspace tell us what to do */
eb1f8e4f 300 drm_helper_hpd_irq_event(dev);
5ca58282
JB		 301}
302
9270388e
DV		 303/* defined intel_pm.c */
304extern spinlock_t mchdev_lock;
305
73edd18f 306static void ironlake_handle_rps_change(struct drm_device *dev)
f97108d1
JB		 307{
308 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 309 u32 busy_up, busy_down, max_avg, min_avg;
9270388e
DV		 310 u8 new_delay;
311 unsigned long flags;
312
313 spin_lock_irqsave(&mchdev_lock, flags);
f97108d1 314
73edd18f
DV		 315 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
316
20e4d407 317 new_delay = dev_priv->ips.cur_delay;
9270388e 318
7648fa99 319 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 320 busy_up = I915_READ(RCPREVBSYTUPAVG);
321 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 322 max_avg = I915_READ(RCBMAXAVG);
323 min_avg = I915_READ(RCBMINAVG);
324
325 /* Handle RCS change request from hw */
b5b72e89 326 if (busy_up > max_avg) {
20e4d407
DV		 327 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
328 new_delay = dev_priv->ips.cur_delay - 1;
329 if (new_delay < dev_priv->ips.max_delay)
330 new_delay = dev_priv->ips.max_delay;
b5b72e89 331 } else if (busy_down < min_avg) {
20e4d407
DV		 332 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
333 new_delay = dev_priv->ips.cur_delay + 1;
334 if (new_delay > dev_priv->ips.min_delay)
335 new_delay = dev_priv->ips.min_delay;
f97108d1
JB		 336 }
337
7648fa99 338 if (ironlake_set_drps(dev, new_delay))
20e4d407 339 dev_priv->ips.cur_delay = new_delay;
f97108d1 340
9270388e
DV		 341 spin_unlock_irqrestore(&mchdev_lock, flags);
342
f97108d1
JB		 343 return;
344}
345
549f7365
CW		 346static void notify_ring(struct drm_device *dev,
347 struct intel_ring_buffer *ring)
348{
349 struct drm_i915_private *dev_priv = dev->dev_private;
9862e600 350
475553de
CW		 351 if (ring->obj == NULL)
352 return;
353
b2eadbc8 354 trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
9862e600 355
549f7365 356 wake_up_all(&ring->irq_queue);
3e0dc6b0
BW		 357 if (i915_enable_hangcheck) {
358 dev_priv->hangcheck_count = 0;
359 mod_timer(&dev_priv->hangcheck_timer,
cecc21fe 360 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
3e0dc6b0 361 }
549f7365
CW		 362}
363
4912d041 364static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 365{
4912d041 366 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
c6a828d3 367 rps.work);
4912d041 368 u32 pm_iir, pm_imr;
7b9e0ae6 369 u8 new_delay;
4912d041 370
c6a828d3
DV		 371 spin_lock_irq(&dev_priv->rps.lock);
372 pm_iir = dev_priv->rps.pm_iir;
373 dev_priv->rps.pm_iir = 0;
4912d041 374 pm_imr = I915_READ(GEN6_PMIMR);
a9e2641d 375 I915_WRITE(GEN6_PMIMR, 0);
c6a828d3 376 spin_unlock_irq(&dev_priv->rps.lock);
3b8d8d91 377
7b9e0ae6 378 if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
3b8d8d91
JB		 379 return;
380
4912d041 381 mutex_lock(&dev_priv->dev->struct_mutex);
7b9e0ae6
CW		 382
383 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
c6a828d3 384 new_delay = dev_priv->rps.cur_delay + 1;
7b9e0ae6 385 else
c6a828d3 386 new_delay = dev_priv->rps.cur_delay - 1;
3b8d8d91 387
79249636
BW		 388 /* sysfs frequency interfaces may have snuck in while servicing the
389 * interrupt
390 */
391 if (!(new_delay > dev_priv->rps.max_delay ||
392 new_delay < dev_priv->rps.min_delay)) {
393 gen6_set_rps(dev_priv->dev, new_delay);
394 }
3b8d8d91 395
4912d041 396 mutex_unlock(&dev_priv->dev->struct_mutex);
3b8d8d91
JB		 397}
398
e3689190
BW		 399
400/**
401 * ivybridge_parity_work - Workqueue called when a parity error interrupt
402 * occurred.
403 * @work: workqueue struct
404 *
405 * Doesn't actually do anything except notify userspace. As a consequence of
406 * this event, userspace should try to remap the bad rows since statistically
407 * it is likely the same row is more likely to go bad again.
408 */
409static void ivybridge_parity_work(struct work_struct *work)
410{
411 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
412 parity_error_work);
413 u32 error_status, row, bank, subbank;
414 char *parity_event[5];
415 uint32_t misccpctl;
416 unsigned long flags;
417
418 /* We must turn off DOP level clock gating to access the L3 registers.
419 * In order to prevent a get/put style interface, acquire struct mutex
420 * any time we access those registers.
421 */
422 mutex_lock(&dev_priv->dev->struct_mutex);
423
424 misccpctl = I915_READ(GEN7_MISCCPCTL);
425 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
426 POSTING_READ(GEN7_MISCCPCTL);
427
428 error_status = I915_READ(GEN7_L3CDERRST1);
429 row = GEN7_PARITY_ERROR_ROW(error_status);
430 bank = GEN7_PARITY_ERROR_BANK(error_status);
431 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
432
433 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
434 GEN7_L3CDERRST1_ENABLE);
435 POSTING_READ(GEN7_L3CDERRST1);
436
437 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
438
439 spin_lock_irqsave(&dev_priv->irq_lock, flags);
440 dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
441 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
442 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
443
444 mutex_unlock(&dev_priv->dev->struct_mutex);
445
446 parity_event[0] = "L3_PARITY_ERROR=1";
447 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
448 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
449 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
450 parity_event[4] = NULL;
451
452 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
453 KOBJ_CHANGE, parity_event);
454
455 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
456 row, bank, subbank);
457
458 kfree(parity_event[3]);
459 kfree(parity_event[2]);
460 kfree(parity_event[1]);
461}
462
d2ba8470 463static void ivybridge_handle_parity_error(struct drm_device *dev)
e3689190
BW		 464{
465 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
466 unsigned long flags;
467
e1ef7cc2 468 if (!HAS_L3_GPU_CACHE(dev))
e3689190
BW		 469 return;
470
471 spin_lock_irqsave(&dev_priv->irq_lock, flags);
472 dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
473 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
474 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
475
476 queue_work(dev_priv->wq, &dev_priv->parity_error_work);
477}
478
e7b4c6b1
DV		 479static void snb_gt_irq_handler(struct drm_device *dev,
480 struct drm_i915_private *dev_priv,
481 u32 gt_iir)
482{
483
484 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
485 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
486 notify_ring(dev, &dev_priv->ring[RCS]);
487 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
488 notify_ring(dev, &dev_priv->ring[VCS]);
489 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
490 notify_ring(dev, &dev_priv->ring[BCS]);
491
492 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
493 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
494 GT_RENDER_CS_ERROR_INTERRUPT)) {
495 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
496 i915_handle_error(dev, false);
497 }
e3689190
BW		 498
499 if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
500 ivybridge_handle_parity_error(dev);
e7b4c6b1
DV		 501}
502
fc6826d1
CW		 503static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
504 u32 pm_iir)
505{
506 unsigned long flags;
507
508 /*
509 * IIR bits should never already be set because IMR should
510 * prevent an interrupt from being shown in IIR. The warning
511 * displays a case where we've unsafely cleared
c6a828d3 512 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
fc6826d1
CW		 513 * type is not a problem, it displays a problem in the logic.
514 *
c6a828d3 515 * The mask bit in IMR is cleared by dev_priv->rps.work.
fc6826d1
CW		 516 */
517
c6a828d3 518 spin_lock_irqsave(&dev_priv->rps.lock, flags);
c6a828d3
DV		 519 dev_priv->rps.pm_iir |= pm_iir;
520 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
fc6826d1 521 POSTING_READ(GEN6_PMIMR);
c6a828d3 522 spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
fc6826d1 523
c6a828d3 524 queue_work(dev_priv->wq, &dev_priv->rps.work);
fc6826d1
CW		 525}
526
ff1f525e 527static irqreturn_t valleyview_irq_handler(int irq, void *arg)
7e231dbe
JB		 528{
529 struct drm_device *dev = (struct drm_device *) arg;
530 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
531 u32 iir, gt_iir, pm_iir;
532 irqreturn_t ret = IRQ_NONE;
533 unsigned long irqflags;
534 int pipe;
535 u32 pipe_stats[I915_MAX_PIPES];
7e231dbe
JB		 536 bool blc_event;
537
538 atomic_inc(&dev_priv->irq_received);
539
7e231dbe
JB		 540 while (true) {
541 iir = I915_READ(VLV_IIR);
542 gt_iir = I915_READ(GTIIR);
543 pm_iir = I915_READ(GEN6_PMIIR);
544
545 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
546 goto out;
547
548 ret = IRQ_HANDLED;
549
e7b4c6b1 550 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 551
552 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
553 for_each_pipe(pipe) {
554 int reg = PIPESTAT(pipe);
555 pipe_stats[pipe] = I915_READ(reg);
556
557 /*
558 * Clear the PIPE*STAT regs before the IIR
559 */
560 if (pipe_stats[pipe] & 0x8000ffff) {
561 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
562 DRM_DEBUG_DRIVER("pipe %c underrun\n",
563 pipe_name(pipe));
564 I915_WRITE(reg, pipe_stats[pipe]);
565 }
566 }
567 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
568
31acc7f5
JB		 569 for_each_pipe(pipe) {
570 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
571 drm_handle_vblank(dev, pipe);
572
573 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
574 intel_prepare_page_flip(dev, pipe);
575 intel_finish_page_flip(dev, pipe);
576 }
577 }
578
7e231dbe
JB		 579 /* Consume port. Then clear IIR or we'll miss events */
580 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
581 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
582
583 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
584 hotplug_status);
585 if (hotplug_status & dev_priv->hotplug_supported_mask)
586 queue_work(dev_priv->wq,
587 &dev_priv->hotplug_work);
588
589 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
590 I915_READ(PORT_HOTPLUG_STAT);
591 }
592
7e231dbe
JB		 593 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
594 blc_event = true;
595
fc6826d1
CW		 596 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
597 gen6_queue_rps_work(dev_priv, pm_iir);
7e231dbe
JB		 598
599 I915_WRITE(GTIIR, gt_iir);
600 I915_WRITE(GEN6_PMIIR, pm_iir);
601 I915_WRITE(VLV_IIR, iir);
602 }
603
604out:
605 return ret;
606}
607
23e81d69 608static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 609{
610 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 611 int pipe;
776ad806 612
76e43830
DV		 613 if (pch_iir & SDE_HOTPLUG_MASK)
614 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
615
776ad806
JB		 616 if (pch_iir & SDE_AUDIO_POWER_MASK)
617 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
618 (pch_iir & SDE_AUDIO_POWER_MASK) >>
619 SDE_AUDIO_POWER_SHIFT);
620
621 if (pch_iir & SDE_GMBUS)
622 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
623
624 if (pch_iir & SDE_AUDIO_HDCP_MASK)
625 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
626
627 if (pch_iir & SDE_AUDIO_TRANS_MASK)
628 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
629
630 if (pch_iir & SDE_POISON)
631 DRM_ERROR("PCH poison interrupt\n");
632
9db4a9c7
JB		 633 if (pch_iir & SDE_FDI_MASK)
634 for_each_pipe(pipe)
635 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
636 pipe_name(pipe),
637 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 638
639 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
640 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
641
642 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
643 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
644
645 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
646 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
647 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
648 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
649}
650
23e81d69
AJ		 651static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
652{
653 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
654 int pipe;
655
76e43830
DV		 656 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
657 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
658
23e81d69
AJ		 659 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
660 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
661 (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
662 SDE_AUDIO_POWER_SHIFT_CPT);
663
664 if (pch_iir & SDE_AUX_MASK_CPT)
665 DRM_DEBUG_DRIVER("AUX channel interrupt\n");
666
667 if (pch_iir & SDE_GMBUS_CPT)
668 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
669
670 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
671 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
672
673 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
674 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
675
676 if (pch_iir & SDE_FDI_MASK_CPT)
677 for_each_pipe(pipe)
678 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
679 pipe_name(pipe),
680 I915_READ(FDI_RX_IIR(pipe)));
681}
682
ff1f525e 683static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
b1f14ad0
JB		 684{
685 struct drm_device *dev = (struct drm_device *) arg;
686 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
0e43406b
CW		 687 u32 de_iir, gt_iir, de_ier, pm_iir;
688 irqreturn_t ret = IRQ_NONE;
689 int i;
b1f14ad0
JB		 690
691 atomic_inc(&dev_priv->irq_received);
692
693 /* disable master interrupt before clearing iir */
694 de_ier = I915_READ(DEIER);
695 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
b1f14ad0 696
b1f14ad0 697 gt_iir = I915_READ(GTIIR);
0e43406b
CW		 698 if (gt_iir) {
699 snb_gt_irq_handler(dev, dev_priv, gt_iir);
700 I915_WRITE(GTIIR, gt_iir);
701 ret = IRQ_HANDLED;
b1f14ad0
JB		 702 }
703
0e43406b
CW		 704 de_iir = I915_READ(DEIIR);
705 if (de_iir) {
706 if (de_iir & DE_GSE_IVB)
707 intel_opregion_gse_intr(dev);
708
709 for (i = 0; i < 3; i++) {
74d44445
DV		 710 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
711 drm_handle_vblank(dev, i);
0e43406b
CW		 712 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
713 intel_prepare_page_flip(dev, i);
714 intel_finish_page_flip_plane(dev, i);
715 }
0e43406b 716 }
b615b57a 717
0e43406b
CW		 718 /* check event from PCH */
719 if (de_iir & DE_PCH_EVENT_IVB) {
720 u32 pch_iir = I915_READ(SDEIIR);
b1f14ad0 721
23e81d69 722 cpt_irq_handler(dev, pch_iir);
b1f14ad0 723
0e43406b
CW		 724 /* clear PCH hotplug event before clear CPU irq */
725 I915_WRITE(SDEIIR, pch_iir);
726 }
b615b57a 727
0e43406b
CW		 728 I915_WRITE(DEIIR, de_iir);
729 ret = IRQ_HANDLED;
b1f14ad0
JB		 730 }
731
0e43406b
CW		 732 pm_iir = I915_READ(GEN6_PMIIR);
733 if (pm_iir) {
734 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
735 gen6_queue_rps_work(dev_priv, pm_iir);
736 I915_WRITE(GEN6_PMIIR, pm_iir);
737 ret = IRQ_HANDLED;
738 }
b1f14ad0 739
b1f14ad0
JB		 740 I915_WRITE(DEIER, de_ier);
741 POSTING_READ(DEIER);
742
743 return ret;
744}
745
e7b4c6b1
DV		 746static void ilk_gt_irq_handler(struct drm_device *dev,
747 struct drm_i915_private *dev_priv,
748 u32 gt_iir)
749{
750 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
751 notify_ring(dev, &dev_priv->ring[RCS]);
752 if (gt_iir & GT_BSD_USER_INTERRUPT)
753 notify_ring(dev, &dev_priv->ring[VCS]);
754}
755
ff1f525e 756static irqreturn_t ironlake_irq_handler(int irq, void *arg)
036a4a7d 757{
4697995b 758 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 759 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
760 int ret = IRQ_NONE;
3b8d8d91 761 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
881f47b6 762
4697995b
JB		 763 atomic_inc(&dev_priv->irq_received);
764
2d109a84
ZN		 765 /* disable master interrupt before clearing iir */
766 de_ier = I915_READ(DEIER);
767 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 768 POSTING_READ(DEIER);
2d109a84 769
036a4a7d
ZW		 770 de_iir = I915_READ(DEIIR);
771 gt_iir = I915_READ(GTIIR);
c650156a 772 pch_iir = I915_READ(SDEIIR);
3b8d8d91 773 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 774
3b8d8d91
JB		 775 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
776 (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 777 goto done;
036a4a7d 778
c7c85101 779 ret = IRQ_HANDLED;
036a4a7d 780
e7b4c6b1
DV		 781 if (IS_GEN5(dev))
782 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
783 else
784 snb_gt_irq_handler(dev, dev_priv, gt_iir);
01c66889 785
c7c85101 786 if (de_iir & DE_GSE)
3b617967 787 intel_opregion_gse_intr(dev);
c650156a 788
74d44445
DV		 789 if (de_iir & DE_PIPEA_VBLANK)
790 drm_handle_vblank(dev, 0);
791
792 if (de_iir & DE_PIPEB_VBLANK)
793 drm_handle_vblank(dev, 1);
794
f072d2e7 795 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 796 intel_prepare_page_flip(dev, 0);
2bbda389 797 intel_finish_page_flip_plane(dev, 0);
f072d2e7 798 }
013d5aa2 799
f072d2e7 800 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 801 intel_prepare_page_flip(dev, 1);
2bbda389 802 intel_finish_page_flip_plane(dev, 1);
f072d2e7 803 }
013d5aa2 804
c7c85101 805 /* check event from PCH */
776ad806 806 if (de_iir & DE_PCH_EVENT) {
23e81d69
AJ		 807 if (HAS_PCH_CPT(dev))
808 cpt_irq_handler(dev, pch_iir);
809 else
810 ibx_irq_handler(dev, pch_iir);
776ad806 811 }
036a4a7d 812
73edd18f
DV		 813 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
814 ironlake_handle_rps_change(dev);
f97108d1 815
fc6826d1
CW		 816 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
817 gen6_queue_rps_work(dev_priv, pm_iir);
3b8d8d91 818
c7c85101
ZN		 819 /* should clear PCH hotplug event before clear CPU irq */
820 I915_WRITE(SDEIIR, pch_iir);
821 I915_WRITE(GTIIR, gt_iir);
822 I915_WRITE(DEIIR, de_iir);
4912d041 823 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 824
825done:
2d109a84 826 I915_WRITE(DEIER, de_ier);
3143a2bf 827 POSTING_READ(DEIER);
2d109a84 828
036a4a7d
ZW		 829 return ret;
830}
831
8a905236
JB		 832/**
833 * i915_error_work_func - do process context error handling work
834 * @work: work struct
835 *
836 * Fire an error uevent so userspace can see that a hang or error
837 * was detected.
838 */
839static void i915_error_work_func(struct work_struct *work)
840{
841 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
842 error_work);
843 struct drm_device *dev = dev_priv->dev;
f316a42c
BG		 844 char *error_event[] = { "ERROR=1", NULL };
845 char *reset_event[] = { "RESET=1", NULL };
846 char *reset_done_event[] = { "ERROR=0", NULL };
8a905236 847
f316a42c
BG		 848 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
849
ba1234d1 850 if (atomic_read(&dev_priv->mm.wedged)) {
f803aa55
CW		 851 DRM_DEBUG_DRIVER("resetting chip\n");
852 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
d4b8bb2a 853 if (!i915_reset(dev)) {
f803aa55
CW		 854 atomic_set(&dev_priv->mm.wedged, 0);
855 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
f316a42c 856 }
30dbf0c0 857 complete_all(&dev_priv->error_completion);
f316a42c 858 }
8a905236
JB		 859}
860
85f9e50d
DV		 861/* NB: please notice the memset */
862static void i915_get_extra_instdone(struct drm_device *dev,
863 uint32_t *instdone)
864{
865 struct drm_i915_private *dev_priv = dev->dev_private;
866 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
867
868 switch(INTEL_INFO(dev)->gen) {
869 case 2:
870 case 3:
871 instdone[0] = I915_READ(INSTDONE);
872 break;
873 case 4:
874 case 5:
875 case 6:
876 instdone[0] = I915_READ(INSTDONE_I965);
877 instdone[1] = I915_READ(INSTDONE1);
878 break;
879 default:
880 WARN_ONCE(1, "Unsupported platform\n");
881 case 7:
882 instdone[0] = I915_READ(GEN7_INSTDONE_1);
883 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
884 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
885 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
886 break;
887 }
888}
889
3bd3c932 890#ifdef CONFIG_DEBUG_FS
9df30794 891static struct drm_i915_error_object *
bcfb2e28 892i915_error_object_create(struct drm_i915_private *dev_priv,
05394f39 893 struct drm_i915_gem_object *src)
9df30794
CW		 894{
895 struct drm_i915_error_object *dst;
9da3da66 896 int i, count;
e56660dd 897 u32 reloc_offset;
9df30794 898
05394f39 899 if (src == NULL || src->pages == NULL)
9df30794
CW		 900 return NULL;
901
9da3da66 902 count = src->base.size / PAGE_SIZE;
9df30794 903
9da3da66 904 dst = kmalloc(sizeof(*dst) + count * sizeof(u32 *), GFP_ATOMIC);
9df30794
CW		 905 if (dst == NULL)
906 return NULL;
907
05394f39 908 reloc_offset = src->gtt_offset;
9da3da66 909 for (i = 0; i < count; i++) {
788885ae 910 unsigned long flags;
e56660dd 911 void *d;
788885ae 912
e56660dd 913 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 914 if (d == NULL)
915 goto unwind;
e56660dd 916
788885ae 917 local_irq_save(flags);
74898d7e
DV		 918 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
919 src->has_global_gtt_mapping) {
172975aa
CW		 920 void __iomem *s;
921
922 /* Simply ignore tiling or any overlapping fence.
923 * It's part of the error state, and this hopefully
924 * captures what the GPU read.
925 */
926
927 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
928 reloc_offset);
929 memcpy_fromio(d, s, PAGE_SIZE);
930 io_mapping_unmap_atomic(s);
931 } else {
9da3da66 932 struct page *page;
172975aa
CW		 933 void *s;
934
9da3da66 935 page = i915_gem_object_get_page(src, i);
172975aa 936
9da3da66
CW		 937 drm_clflush_pages(&page, 1);
938
939 s = kmap_atomic(page);
172975aa
CW		 940 memcpy(d, s, PAGE_SIZE);
941 kunmap_atomic(s);
942
9da3da66 943 drm_clflush_pages(&page, 1);
172975aa 944 }
788885ae 945 local_irq_restore(flags);
e56660dd 946
9da3da66 947 dst->pages[i] = d;
e56660dd
CW		 948
949 reloc_offset += PAGE_SIZE;
9df30794 950 }
9da3da66 951 dst->page_count = count;
05394f39 952 dst->gtt_offset = src->gtt_offset;
9df30794
CW		 953
954 return dst;
955
956unwind:
9da3da66
CW		 957 while (i--)
958 kfree(dst->pages[i]);
9df30794
CW		 959 kfree(dst);
960 return NULL;
961}
962
963static void
964i915_error_object_free(struct drm_i915_error_object *obj)
965{
966 int page;
967
968 if (obj == NULL)
969 return;
970
971 for (page = 0; page < obj->page_count; page++)
972 kfree(obj->pages[page]);
973
974 kfree(obj);
975}
976
742cbee8
DV		 977void
978i915_error_state_free(struct kref *error_ref)
9df30794 979{
742cbee8
DV		 980 struct drm_i915_error_state *error = container_of(error_ref,
981 typeof(*error), ref);
e2f973d5
CW		 982 int i;
983
52d39a21
CW		 984 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
985 i915_error_object_free(error->ring[i].batchbuffer);
986 i915_error_object_free(error->ring[i].ringbuffer);
987 kfree(error->ring[i].requests);
988 }
e2f973d5 989
9df30794 990 kfree(error->active_bo);
6ef3d427 991 kfree(error->overlay);
9df30794
CW		 992 kfree(error);
993}
1b50247a
CW		 994static void capture_bo(struct drm_i915_error_buffer *err,
995 struct drm_i915_gem_object *obj)
996{
997 err->size = obj->base.size;
998 err->name = obj->base.name;
0201f1ec
CW		 999 err->rseqno = obj->last_read_seqno;
1000 err->wseqno = obj->last_write_seqno;
1b50247a
CW		 1001 err->gtt_offset = obj->gtt_offset;
1002 err->read_domains = obj->base.read_domains;
1003 err->write_domain = obj->base.write_domain;
1004 err->fence_reg = obj->fence_reg;
1005 err->pinned = 0;
1006 if (obj->pin_count > 0)
1007 err->pinned = 1;
1008 if (obj->user_pin_count > 0)
1009 err->pinned = -1;
1010 err->tiling = obj->tiling_mode;
1011 err->dirty = obj->dirty;
1012 err->purgeable = obj->madv != I915_MADV_WILLNEED;
1013 err->ring = obj->ring ? obj->ring->id : -1;
1014 err->cache_level = obj->cache_level;
1015}
9df30794 1016
1b50247a
CW		 1017static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1018 int count, struct list_head *head)
c724e8a9
CW		 1019{
1020 struct drm_i915_gem_object *obj;
1021 int i = 0;
1022
1023 list_for_each_entry(obj, head, mm_list) {
1b50247a 1024 capture_bo(err++, obj);
c724e8a9
CW		 1025 if (++i == count)
1026 break;
1b50247a
CW		 1027 }
1028
1029 return i;
1030}
1031
1032static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1033 int count, struct list_head *head)
1034{
1035 struct drm_i915_gem_object *obj;
1036 int i = 0;
1037
1038 list_for_each_entry(obj, head, gtt_list) {
1039 if (obj->pin_count == 0)
1040 continue;
c724e8a9 1041
1b50247a
CW		 1042 capture_bo(err++, obj);
1043 if (++i == count)
1044 break;
c724e8a9
CW		 1045 }
1046
1047 return i;
1048}
1049
748ebc60
CW		 1050static void i915_gem_record_fences(struct drm_device *dev,
1051 struct drm_i915_error_state *error)
1052{
1053 struct drm_i915_private *dev_priv = dev->dev_private;
1054 int i;
1055
1056 /* Fences */
1057 switch (INTEL_INFO(dev)->gen) {
775d17b6 1058 case 7:
748ebc60
CW		 1059 case 6:
1060 for (i = 0; i < 16; i++)
1061 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1062 break;
1063 case 5:
1064 case 4:
1065 for (i = 0; i < 16; i++)
1066 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1067 break;
1068 case 3:
1069 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1070 for (i = 0; i < 8; i++)
1071 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1072 case 2:
1073 for (i = 0; i < 8; i++)
1074 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1075 break;
1076
1077 }
1078}
1079
bcfb2e28
CW		 1080static struct drm_i915_error_object *
1081i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1082 struct intel_ring_buffer *ring)
1083{
1084 struct drm_i915_gem_object *obj;
1085 u32 seqno;
1086
1087 if (!ring->get_seqno)
1088 return NULL;
1089
b2eadbc8 1090 seqno = ring->get_seqno(ring, false);
bcfb2e28
CW		 1091 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1092 if (obj->ring != ring)
1093 continue;
1094
0201f1ec 1095 if (i915_seqno_passed(seqno, obj->last_read_seqno))
bcfb2e28
CW		 1096 continue;
1097
1098 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1099 continue;
1100
1101 /* We need to copy these to an anonymous buffer as the simplest
1102 * method to avoid being overwritten by userspace.
1103 */
1104 return i915_error_object_create(dev_priv, obj);
1105 }
1106
1107 return NULL;
1108}
1109
d27b1e0e
DV		 1110static void i915_record_ring_state(struct drm_device *dev,
1111 struct drm_i915_error_state *error,
1112 struct intel_ring_buffer *ring)
1113{
1114 struct drm_i915_private *dev_priv = dev->dev_private;
1115
33f3f518 1116 if (INTEL_INFO(dev)->gen >= 6) {
12f55818 1117 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
33f3f518 1118 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
7e3b8737
DV		 1119 error->semaphore_mboxes[ring->id][0]
1120 = I915_READ(RING_SYNC_0(ring->mmio_base));
1121 error->semaphore_mboxes[ring->id][1]
1122 = I915_READ(RING_SYNC_1(ring->mmio_base));
33f3f518 1123 }
c1cd90ed 1124
d27b1e0e 1125 if (INTEL_INFO(dev)->gen >= 4) {
9d2f41fa 1126 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
d27b1e0e
DV		 1127 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1128 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1129 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
c1cd90ed 1130 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
050ee91f 1131 if (ring->id == RCS)
d27b1e0e 1132 error->bbaddr = I915_READ64(BB_ADDR);
d27b1e0e 1133 } else {
9d2f41fa 1134 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
d27b1e0e
DV		 1135 error->ipeir[ring->id] = I915_READ(IPEIR);
1136 error->ipehr[ring->id] = I915_READ(IPEHR);
1137 error->instdone[ring->id] = I915_READ(INSTDONE);
d27b1e0e
DV		 1138 }
1139
9574b3fe 1140 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
c1cd90ed 1141 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
b2eadbc8 1142 error->seqno[ring->id] = ring->get_seqno(ring, false);
d27b1e0e 1143 error->acthd[ring->id] = intel_ring_get_active_head(ring);
c1cd90ed
DV		 1144 error->head[ring->id] = I915_READ_HEAD(ring);
1145 error->tail[ring->id] = I915_READ_TAIL(ring);
7e3b8737
DV		 1146
1147 error->cpu_ring_head[ring->id] = ring->head;
1148 error->cpu_ring_tail[ring->id] = ring->tail;
d27b1e0e
DV		 1149}
1150
52d39a21
CW		 1151static void i915_gem_record_rings(struct drm_device *dev,
1152 struct drm_i915_error_state *error)
1153{
1154 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 1155 struct intel_ring_buffer *ring;
52d39a21
CW		 1156 struct drm_i915_gem_request *request;
1157 int i, count;
1158
b4519513 1159 for_each_ring(ring, dev_priv, i) {
52d39a21
CW		 1160 i915_record_ring_state(dev, error, ring);
1161
1162 error->ring[i].batchbuffer =
1163 i915_error_first_batchbuffer(dev_priv, ring);
1164
1165 error->ring[i].ringbuffer =
1166 i915_error_object_create(dev_priv, ring->obj);
1167
1168 count = 0;
1169 list_for_each_entry(request, &ring->request_list, list)
1170 count++;
1171
1172 error->ring[i].num_requests = count;
1173 error->ring[i].requests =
1174 kmalloc(count*sizeof(struct drm_i915_error_request),
1175 GFP_ATOMIC);
1176 if (error->ring[i].requests == NULL) {
1177 error->ring[i].num_requests = 0;
1178 continue;
1179 }
1180
1181 count = 0;
1182 list_for_each_entry(request, &ring->request_list, list) {
1183 struct drm_i915_error_request *erq;
1184
1185 erq = &error->ring[i].requests[count++];
1186 erq->seqno = request->seqno;
1187 erq->jiffies = request->emitted_jiffies;
ee4f42b1 1188 erq->tail = request->tail;
52d39a21
CW		 1189 }
1190 }
1191}
1192
8a905236
JB		 1193/**
1194 * i915_capture_error_state - capture an error record for later analysis
1195 * @dev: drm device
1196 *
1197 * Should be called when an error is detected (either a hang or an error
1198 * interrupt) to capture error state from the time of the error. Fills
1199 * out a structure which becomes available in debugfs for user level tools
1200 * to pick up.
1201 */
63eeaf38
JB		 1202static void i915_capture_error_state(struct drm_device *dev)
1203{
1204 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1205 struct drm_i915_gem_object *obj;
63eeaf38
JB		 1206 struct drm_i915_error_state *error;
1207 unsigned long flags;
9db4a9c7 1208 int i, pipe;
63eeaf38
JB		 1209
1210 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1211 error = dev_priv->first_error;
1212 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1213 if (error)
1214 return;
63eeaf38 1215
9db4a9c7 1216 /* Account for pipe specific data like PIPE*STAT */
33f3f518 1217 error = kzalloc(sizeof(*error), GFP_ATOMIC);
63eeaf38 1218 if (!error) {
9df30794
CW		 1219 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1220 return;
63eeaf38
JB		 1221 }
1222
b6f7833b
CW		 1223 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1224 dev->primary->index);
2fa772f3 1225
742cbee8 1226 kref_init(&error->ref);
63eeaf38
JB		 1227 error->eir = I915_READ(EIR);
1228 error->pgtbl_er = I915_READ(PGTBL_ER);
b9a3906b 1229 error->ccid = I915_READ(CCID);
be998e2e
BW		 1230
1231 if (HAS_PCH_SPLIT(dev))
1232 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1233 else if (IS_VALLEYVIEW(dev))
1234 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1235 else if (IS_GEN2(dev))
1236 error->ier = I915_READ16(IER);
1237 else
1238 error->ier = I915_READ(IER);
1239
9db4a9c7
JB		 1240 for_each_pipe(pipe)
1241 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
d27b1e0e 1242
33f3f518 1243 if (INTEL_INFO(dev)->gen >= 6) {
f406839f 1244 error->error = I915_READ(ERROR_GEN6);
33f3f518
DV		 1245 error->done_reg = I915_READ(DONE_REG);
1246 }
d27b1e0e 1247
71e172e8
BW		 1248 if (INTEL_INFO(dev)->gen == 7)
1249 error->err_int = I915_READ(GEN7_ERR_INT);
1250
050ee91f
BW		 1251 i915_get_extra_instdone(dev, error->extra_instdone);
1252
748ebc60 1253 i915_gem_record_fences(dev, error);
52d39a21 1254 i915_gem_record_rings(dev, error);
9df30794 1255
c724e8a9 1256 /* Record buffers on the active and pinned lists. */
9df30794 1257 error->active_bo = NULL;
c724e8a9 1258 error->pinned_bo = NULL;
9df30794 1259
bcfb2e28
CW		 1260 i = 0;
1261 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1262 i++;
1263 error->active_bo_count = i;
6c085a72 1264 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
1b50247a
CW		 1265 if (obj->pin_count)
1266 i++;
bcfb2e28 1267 error->pinned_bo_count = i - error->active_bo_count;
c724e8a9 1268
8e934dbf
CW		 1269 error->active_bo = NULL;
1270 error->pinned_bo = NULL;
bcfb2e28
CW		 1271 if (i) {
1272 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
9df30794 1273 GFP_ATOMIC);
c724e8a9
CW		 1274 if (error->active_bo)
1275 error->pinned_bo =
1276 error->active_bo + error->active_bo_count;
9df30794
CW		 1277 }
1278
c724e8a9
CW		 1279 if (error->active_bo)
1280 error->active_bo_count =
1b50247a
CW		 1281 capture_active_bo(error->active_bo,
1282 error->active_bo_count,
1283 &dev_priv->mm.active_list);
c724e8a9
CW		 1284
1285 if (error->pinned_bo)
1286 error->pinned_bo_count =
1b50247a
CW		 1287 capture_pinned_bo(error->pinned_bo,
1288 error->pinned_bo_count,
6c085a72 1289 &dev_priv->mm.bound_list);
c724e8a9 1290
9df30794
CW		 1291 do_gettimeofday(&error->time);
1292
6ef3d427 1293 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 1294 error->display = intel_display_capture_error_state(dev);
6ef3d427 1295
9df30794
CW		 1296 spin_lock_irqsave(&dev_priv->error_lock, flags);
1297 if (dev_priv->first_error == NULL) {
1298 dev_priv->first_error = error;
1299 error = NULL;
1300 }
63eeaf38 1301 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1302
1303 if (error)
742cbee8 1304 i915_error_state_free(&error->ref);
9df30794
CW		 1305}
1306
1307void i915_destroy_error_state(struct drm_device *dev)
1308{
1309 struct drm_i915_private *dev_priv = dev->dev_private;
1310 struct drm_i915_error_state *error;
6dc0e816 1311 unsigned long flags;
9df30794 1312
6dc0e816 1313 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1314 error = dev_priv->first_error;
1315 dev_priv->first_error = NULL;
6dc0e816 1316 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1317
1318 if (error)
742cbee8 1319 kref_put(&error->ref, i915_error_state_free);
63eeaf38 1320}
3bd3c932
CW		 1321#else
1322#define i915_capture_error_state(x)
1323#endif
63eeaf38 1324
35aed2e6 1325static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1326{
1327 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 1328 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 1329 u32 eir = I915_READ(EIR);
050ee91f 1330 int pipe, i;
8a905236 1331
35aed2e6
CW		 1332 if (!eir)
1333 return;
8a905236 1334
a70491cc 1335 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 1336
bd9854f9
BW		 1337 i915_get_extra_instdone(dev, instdone);
1338
8a905236
JB		 1339 if (IS_G4X(dev)) {
1340 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1341 u32 ipeir = I915_READ(IPEIR_I965);
1342
a70491cc
JP		 1343 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1344 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 1345 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1346 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 1347 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1348 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1349 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1350 POSTING_READ(IPEIR_I965);
8a905236
JB		 1351 }
1352 if (eir & GM45_ERROR_PAGE_TABLE) {
1353 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1354 pr_err("page table error\n");
1355 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1356 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1357 POSTING_READ(PGTBL_ER);
8a905236
JB		 1358 }
1359 }
1360
a6c45cf0 1361 if (!IS_GEN2(dev)) {
8a905236
JB		 1362 if (eir & I915_ERROR_PAGE_TABLE) {
1363 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1364 pr_err("page table error\n");
1365 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1366 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1367 POSTING_READ(PGTBL_ER);
8a905236
JB		 1368 }
1369 }
1370
1371 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 1372 pr_err("memory refresh error:\n");
9db4a9c7 1373 for_each_pipe(pipe)
a70491cc 1374 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 1375 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 1376 /* pipestat has already been acked */
1377 }
1378 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 1379 pr_err("instruction error\n");
1380 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 1381 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1382 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 1383 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 1384 u32 ipeir = I915_READ(IPEIR);
1385
a70491cc
JP		 1386 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1387 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 1388 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 1389 I915_WRITE(IPEIR, ipeir);
3143a2bf 1390 POSTING_READ(IPEIR);
8a905236
JB		 1391 } else {
1392 u32 ipeir = I915_READ(IPEIR_I965);
1393
a70491cc
JP		 1394 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1395 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 1396 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1397 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1398 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1399 POSTING_READ(IPEIR_I965);
8a905236
JB		 1400 }
1401 }
1402
1403 I915_WRITE(EIR, eir);
3143a2bf 1404 POSTING_READ(EIR);
8a905236
JB		 1405 eir = I915_READ(EIR);
1406 if (eir) {
1407 /*
1408 * some errors might have become stuck,
1409 * mask them.
1410 */
1411 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1412 I915_WRITE(EMR, I915_READ(EMR) | eir);
1413 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1414 }
35aed2e6
CW		 1415}
1416
1417/**
1418 * i915_handle_error - handle an error interrupt
1419 * @dev: drm device
1420 *
1421 * Do some basic checking of regsiter state at error interrupt time and
1422 * dump it to the syslog. Also call i915_capture_error_state() to make
1423 * sure we get a record and make it available in debugfs. Fire a uevent
1424 * so userspace knows something bad happened (should trigger collection
1425 * of a ring dump etc.).
1426 */
527f9e90 1427void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 1428{
1429 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513
CW		 1430 struct intel_ring_buffer *ring;
1431 int i;
35aed2e6
CW		 1432
1433 i915_capture_error_state(dev);
1434 i915_report_and_clear_eir(dev);
8a905236 1435
ba1234d1 1436 if (wedged) {
30dbf0c0 1437 INIT_COMPLETION(dev_priv->error_completion);
ba1234d1
BG		 1438 atomic_set(&dev_priv->mm.wedged, 1);
1439
11ed50ec
BG		 1440 /*
1441 * Wakeup waiting processes so they don't hang
1442 */
b4519513
CW		 1443 for_each_ring(ring, dev_priv, i)
1444 wake_up_all(&ring->irq_queue);
11ed50ec
BG		 1445 }
1446
9c9fe1f8 1447 queue_work(dev_priv->wq, &dev_priv->error_work);
8a905236
JB		 1448}
1449
4e5359cd
SF		 1450static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1451{
1452 drm_i915_private_t *dev_priv = dev->dev_private;
1453 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1454 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 1455 struct drm_i915_gem_object *obj;
4e5359cd
SF		 1456 struct intel_unpin_work *work;
1457 unsigned long flags;
1458 bool stall_detected;
1459
1460 /* Ignore early vblank irqs */
1461 if (intel_crtc == NULL)
1462 return;
1463
1464 spin_lock_irqsave(&dev->event_lock, flags);
1465 work = intel_crtc->unpin_work;
1466
1467 if (work == NULL || work->pending || !work->enable_stall_check) {
1468 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1469 spin_unlock_irqrestore(&dev->event_lock, flags);
1470 return;
1471 }
1472
1473 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 1474 obj = work->pending_flip_obj;
a6c45cf0 1475 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 1476 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545
AR		 1477 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1478 obj->gtt_offset;
4e5359cd 1479 } else {
9db4a9c7 1480 int dspaddr = DSPADDR(intel_crtc->plane);
05394f39 1481 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
01f2c773 1482 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 1483 crtc->x * crtc->fb->bits_per_pixel/8);
1484 }
1485
1486 spin_unlock_irqrestore(&dev->event_lock, flags);
1487
1488 if (stall_detected) {
1489 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1490 intel_prepare_page_flip(dev, intel_crtc->plane);
1491 }
1492}
1493
42f52ef8
KP		 1494/* Called from drm generic code, passed 'crtc' which
1495 * we use as a pipe index
1496 */
f71d4af4 1497static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1498{
1499 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1500 unsigned long irqflags;
71e0ffa5 1501
5eddb70b 1502 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 1503 return -EINVAL;
0a3e67a4 1504
1ec14ad3 1505 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 1506 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 1507 i915_enable_pipestat(dev_priv, pipe,
1508 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 1509 else
7c463586
KP		 1510 i915_enable_pipestat(dev_priv, pipe,
1511 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 1512
1513 /* maintain vblank delivery even in deep C-states */
1514 if (dev_priv->info->gen == 3)
6b26c86d 1515 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 1516 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 1517
0a3e67a4
JB		 1518 return 0;
1519}
1520
f71d4af4 1521static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1522{
1523 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1524 unsigned long irqflags;
1525
1526 if (!i915_pipe_enabled(dev, pipe))
1527 return -EINVAL;
1528
1529 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1530 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1531 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
f796cf8f
JB		 1532 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1533
1534 return 0;
1535}
1536
f71d4af4 1537static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1538{
1539 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1540 unsigned long irqflags;
1541
1542 if (!i915_pipe_enabled(dev, pipe))
1543 return -EINVAL;
1544
1545 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1546 ironlake_enable_display_irq(dev_priv,
1547 DE_PIPEA_VBLANK_IVB << (5 * pipe));
b1f14ad0
JB		 1548 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1549
1550 return 0;
1551}
1552
7e231dbe
JB		 1553static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1554{
1555 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1556 unsigned long irqflags;
31acc7f5 1557 u32 imr;
7e231dbe
JB		 1558
1559 if (!i915_pipe_enabled(dev, pipe))
1560 return -EINVAL;
1561
1562 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7e231dbe 1563 imr = I915_READ(VLV_IMR);
31acc7f5 1564 if (pipe == 0)
7e231dbe 1565 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1566 else
7e231dbe 1567 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1568 I915_WRITE(VLV_IMR, imr);
31acc7f5
JB		 1569 i915_enable_pipestat(dev_priv, pipe,
1570 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe
JB		 1571 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1572
1573 return 0;
1574}
1575
42f52ef8
KP		 1576/* Called from drm generic code, passed 'crtc' which
1577 * we use as a pipe index
1578 */
f71d4af4 1579static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1580{
1581 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1582 unsigned long irqflags;
0a3e67a4 1583
1ec14ad3 1584 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 1585 if (dev_priv->info->gen == 3)
6b26c86d 1586 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 1587
f796cf8f
JB		 1588 i915_disable_pipestat(dev_priv, pipe,
1589 PIPE_VBLANK_INTERRUPT_ENABLE |
1590 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1591 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1592}
1593
f71d4af4 1594static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1595{
1596 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1597 unsigned long irqflags;
1598
1599 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1600 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1601 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1ec14ad3 1602 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 1603}
1604
f71d4af4 1605static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1606{
1607 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1608 unsigned long irqflags;
1609
1610 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1611 ironlake_disable_display_irq(dev_priv,
1612 DE_PIPEA_VBLANK_IVB << (pipe * 5));
b1f14ad0
JB		 1613 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1614}
1615
7e231dbe
JB		 1616static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1617{
1618 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1619 unsigned long irqflags;
31acc7f5 1620 u32 imr;
7e231dbe
JB		 1621
1622 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5
JB		 1623 i915_disable_pipestat(dev_priv, pipe,
1624 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe 1625 imr = I915_READ(VLV_IMR);
31acc7f5 1626 if (pipe == 0)
7e231dbe 1627 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1628 else
7e231dbe 1629 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1630 I915_WRITE(VLV_IMR, imr);
7e231dbe
JB		 1631 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1632}
1633
893eead0
CW		 1634static u32
1635ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 1636{
893eead0
CW		 1637 return list_entry(ring->request_list.prev,
1638 struct drm_i915_gem_request, list)->seqno;
1639}
1640
1641static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1642{
1643 if (list_empty(&ring->request_list) ||
b2eadbc8
CW		 1644 i915_seqno_passed(ring->get_seqno(ring, false),
1645 ring_last_seqno(ring))) {
893eead0 1646 /* Issue a wake-up to catch stuck h/w. */
9574b3fe
BW		 1647 if (waitqueue_active(&ring->irq_queue)) {
1648 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1649 ring->name);
893eead0
CW		 1650 wake_up_all(&ring->irq_queue);
1651 *err = true;
1652 }
1653 return true;
1654 }
1655 return false;
f65d9421
BG		 1656}
1657
1ec14ad3
CW		 1658static bool kick_ring(struct intel_ring_buffer *ring)
1659{
1660 struct drm_device *dev = ring->dev;
1661 struct drm_i915_private *dev_priv = dev->dev_private;
1662 u32 tmp = I915_READ_CTL(ring);
1663 if (tmp & RING_WAIT) {
1664 DRM_ERROR("Kicking stuck wait on %s\n",
1665 ring->name);
1666 I915_WRITE_CTL(ring, tmp);
1667 return true;
1668 }
1ec14ad3
CW		 1669 return false;
1670}
1671
d1e61e7f
CW		 1672static bool i915_hangcheck_hung(struct drm_device *dev)
1673{
1674 drm_i915_private_t *dev_priv = dev->dev_private;
1675
1676 if (dev_priv->hangcheck_count++ > 1) {
b4519513
CW		 1677 bool hung = true;
1678
d1e61e7f
CW		 1679 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1680 i915_handle_error(dev, true);
1681
1682 if (!IS_GEN2(dev)) {
b4519513
CW		 1683 struct intel_ring_buffer *ring;
1684 int i;
1685
d1e61e7f
CW		 1686 /* Is the chip hanging on a WAIT_FOR_EVENT?
1687 * If so we can simply poke the RB_WAIT bit
1688 * and break the hang. This should work on
1689 * all but the second generation chipsets.
1690 */
b4519513
CW		 1691 for_each_ring(ring, dev_priv, i)
1692 hung &= !kick_ring(ring);
d1e61e7f
CW		 1693 }
1694
b4519513 1695 return hung;
d1e61e7f
CW		 1696 }
1697
1698 return false;
1699}
1700
f65d9421
BG		 1701/**
1702 * This is called when the chip hasn't reported back with completed
1703 * batchbuffers in a long time. The first time this is called we simply record
1704 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1705 * again, we assume the chip is wedged and try to fix it.
1706 */
1707void i915_hangcheck_elapsed(unsigned long data)
1708{
1709 struct drm_device *dev = (struct drm_device *)data;
1710 drm_i915_private_t *dev_priv = dev->dev_private;
bd9854f9 1711 uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
b4519513
CW		 1712 struct intel_ring_buffer *ring;
1713 bool err = false, idle;
1714 int i;
893eead0 1715
3e0dc6b0
BW		 1716 if (!i915_enable_hangcheck)
1717 return;
1718
b4519513
CW		 1719 memset(acthd, 0, sizeof(acthd));
1720 idle = true;
1721 for_each_ring(ring, dev_priv, i) {
1722 idle &= i915_hangcheck_ring_idle(ring, &err);
1723 acthd[i] = intel_ring_get_active_head(ring);
1724 }
1725
893eead0 1726 /* If all work is done then ACTHD clearly hasn't advanced. */
b4519513 1727 if (idle) {
d1e61e7f
CW		 1728 if (err) {
1729 if (i915_hangcheck_hung(dev))
1730 return;
1731
893eead0 1732 goto repeat;
d1e61e7f
CW		 1733 }
1734
1735 dev_priv->hangcheck_count = 0;
893eead0
CW		 1736 return;
1737 }
b9201c14 1738
bd9854f9 1739 i915_get_extra_instdone(dev, instdone);
b4519513 1740 if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 &&
050ee91f 1741 memcmp(dev_priv->prev_instdone, instdone, sizeof(instdone)) == 0) {
d1e61e7f 1742 if (i915_hangcheck_hung(dev))
cbb465e7 1743 return;
cbb465e7
CW		 1744 } else {
1745 dev_priv->hangcheck_count = 0;
1746
b4519513 1747 memcpy(dev_priv->last_acthd, acthd, sizeof(acthd));
050ee91f 1748 memcpy(dev_priv->prev_instdone, instdone, sizeof(instdone));
cbb465e7 1749 }
f65d9421 1750
893eead0 1751repeat:
f65d9421 1752 /* Reset timer case chip hangs without another request being added */
b3b079db 1753 mod_timer(&dev_priv->hangcheck_timer,
cecc21fe 1754 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
f65d9421
BG		 1755}
1756
1da177e4
LT		 1757/* drm_dma.h hooks
1758*/
f71d4af4 1759static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 1760{
1761 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1762
4697995b
JB		 1763 atomic_set(&dev_priv->irq_received, 0);
1764
036a4a7d 1765 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 1766
036a4a7d
ZW		 1767 /* XXX hotplug from PCH */
1768
1769 I915_WRITE(DEIMR, 0xffffffff);
1770 I915_WRITE(DEIER, 0x0);
3143a2bf 1771 POSTING_READ(DEIER);
036a4a7d
ZW		 1772
1773 /* and GT */
1774 I915_WRITE(GTIMR, 0xffffffff);
1775 I915_WRITE(GTIER, 0x0);
3143a2bf 1776 POSTING_READ(GTIER);
c650156a
ZW		 1777
1778 /* south display irq */
1779 I915_WRITE(SDEIMR, 0xffffffff);
1780 I915_WRITE(SDEIER, 0x0);
3143a2bf 1781 POSTING_READ(SDEIER);
036a4a7d
ZW		 1782}
1783
7e231dbe
JB		 1784static void valleyview_irq_preinstall(struct drm_device *dev)
1785{
1786 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1787 int pipe;
1788
1789 atomic_set(&dev_priv->irq_received, 0);
1790
7e231dbe
JB		 1791 /* VLV magic */
1792 I915_WRITE(VLV_IMR, 0);
1793 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1794 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1795 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1796
7e231dbe
JB		 1797 /* and GT */
1798 I915_WRITE(GTIIR, I915_READ(GTIIR));
1799 I915_WRITE(GTIIR, I915_READ(GTIIR));
1800 I915_WRITE(GTIMR, 0xffffffff);
1801 I915_WRITE(GTIER, 0x0);
1802 POSTING_READ(GTIER);
1803
1804 I915_WRITE(DPINVGTT, 0xff);
1805
1806 I915_WRITE(PORT_HOTPLUG_EN, 0);
1807 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1808 for_each_pipe(pipe)
1809 I915_WRITE(PIPESTAT(pipe), 0xffff);
1810 I915_WRITE(VLV_IIR, 0xffffffff);
1811 I915_WRITE(VLV_IMR, 0xffffffff);
1812 I915_WRITE(VLV_IER, 0x0);
1813 POSTING_READ(VLV_IER);
1814}
1815
7fe0b973
KP		 1816/*
1817 * Enable digital hotplug on the PCH, and configure the DP short pulse
1818 * duration to 2ms (which is the minimum in the Display Port spec)
1819 *
1820 * This register is the same on all known PCH chips.
1821 */
1822
1823static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1824{
1825 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1826 u32 hotplug;
1827
1828 hotplug = I915_READ(PCH_PORT_HOTPLUG);
1829 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1830 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1831 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1832 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1833 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1834}
1835
f71d4af4 1836static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d
ZW		 1837{
1838 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1839 /* enable kind of interrupts always enabled */
013d5aa2
JB		 1840 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1841 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1ec14ad3 1842 u32 render_irqs;
2d7b8366 1843 u32 hotplug_mask;
036a4a7d 1844
1ec14ad3 1845 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 1846
1847 /* should always can generate irq */
1848 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3
CW		 1849 I915_WRITE(DEIMR, dev_priv->irq_mask);
1850 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
3143a2bf 1851 POSTING_READ(DEIER);
036a4a7d 1852
1ec14ad3 1853 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 1854
1855 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 1856 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 1857
1ec14ad3
CW		 1858 if (IS_GEN6(dev))
1859 render_irqs =
1860 GT_USER_INTERRUPT |
e2a1e2f0
BW		 1861 GEN6_BSD_USER_INTERRUPT |
1862 GEN6_BLITTER_USER_INTERRUPT;
1ec14ad3
CW		 1863 else
1864 render_irqs =
88f23b8f 1865 GT_USER_INTERRUPT |
c6df541c 1866 GT_PIPE_NOTIFY |
1ec14ad3
CW		 1867 GT_BSD_USER_INTERRUPT;
1868 I915_WRITE(GTIER, render_irqs);
3143a2bf 1869 POSTING_READ(GTIER);
036a4a7d 1870
2d7b8366 1871 if (HAS_PCH_CPT(dev)) {
9035a97a
CW		 1872 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1873 SDE_PORTB_HOTPLUG_CPT |
1874 SDE_PORTC_HOTPLUG_CPT |
1875 SDE_PORTD_HOTPLUG_CPT);
2d7b8366 1876 } else {
9035a97a
CW		 1877 hotplug_mask = (SDE_CRT_HOTPLUG |
1878 SDE_PORTB_HOTPLUG |
1879 SDE_PORTC_HOTPLUG |
1880 SDE_PORTD_HOTPLUG |
1881 SDE_AUX_MASK);
2d7b8366
YL		 1882 }
1883
1ec14ad3 1884 dev_priv->pch_irq_mask = ~hotplug_mask;
c650156a
ZW		 1885
1886 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1ec14ad3
CW		 1887 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1888 I915_WRITE(SDEIER, hotplug_mask);
3143a2bf 1889 POSTING_READ(SDEIER);
c650156a 1890
7fe0b973
KP		 1891 ironlake_enable_pch_hotplug(dev);
1892
f97108d1
JB		 1893 if (IS_IRONLAKE_M(dev)) {
1894 /* Clear & enable PCU event interrupts */
1895 I915_WRITE(DEIIR, DE_PCU_EVENT);
1896 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1897 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1898 }
1899
036a4a7d
ZW		 1900 return 0;
1901}
1902
f71d4af4 1903static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 1904{
1905 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1906 /* enable kind of interrupts always enabled */
b615b57a
CW		 1907 u32 display_mask =
1908 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
1909 DE_PLANEC_FLIP_DONE_IVB |
1910 DE_PLANEB_FLIP_DONE_IVB |
1911 DE_PLANEA_FLIP_DONE_IVB;
b1f14ad0
JB		 1912 u32 render_irqs;
1913 u32 hotplug_mask;
1914
b1f14ad0
JB		 1915 dev_priv->irq_mask = ~display_mask;
1916
1917 /* should always can generate irq */
1918 I915_WRITE(DEIIR, I915_READ(DEIIR));
1919 I915_WRITE(DEIMR, dev_priv->irq_mask);
b615b57a
CW		 1920 I915_WRITE(DEIER,
1921 display_mask |
1922 DE_PIPEC_VBLANK_IVB |
1923 DE_PIPEB_VBLANK_IVB |
1924 DE_PIPEA_VBLANK_IVB);
b1f14ad0
JB		 1925 POSTING_READ(DEIER);
1926
15b9f80e 1927 dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 1928
1929 I915_WRITE(GTIIR, I915_READ(GTIIR));
1930 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1931
e2a1e2f0 1932 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
15b9f80e 1933 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 1934 I915_WRITE(GTIER, render_irqs);
1935 POSTING_READ(GTIER);
1936
1937 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1938 SDE_PORTB_HOTPLUG_CPT |
1939 SDE_PORTC_HOTPLUG_CPT |
1940 SDE_PORTD_HOTPLUG_CPT);
1941 dev_priv->pch_irq_mask = ~hotplug_mask;
1942
1943 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1944 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1945 I915_WRITE(SDEIER, hotplug_mask);
1946 POSTING_READ(SDEIER);
1947
7fe0b973
KP		 1948 ironlake_enable_pch_hotplug(dev);
1949
b1f14ad0
JB		 1950 return 0;
1951}
1952
7e231dbe
JB		 1953static int valleyview_irq_postinstall(struct drm_device *dev)
1954{
1955 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7e231dbe
JB		 1956 u32 enable_mask;
1957 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
31acc7f5 1958 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
3bcedbe5 1959 u32 render_irqs;
7e231dbe
JB		 1960 u16 msid;
1961
1962 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
31acc7f5
JB		 1963 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
1964 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1965 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
7e231dbe
JB		 1966 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1967
31acc7f5
JB		 1968 /*
1969 *Leave vblank interrupts masked initially. enable/disable will
1970 * toggle them based on usage.
1971 */
1972 dev_priv->irq_mask = (~enable_mask) |
1973 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1974 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1975
7e231dbe
JB		 1976 dev_priv->pipestat[0] = 0;
1977 dev_priv->pipestat[1] = 0;
1978
7e231dbe
JB		 1979 /* Hack for broken MSIs on VLV */
1980 pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
1981 pci_read_config_word(dev->pdev, 0x98, &msid);
1982 msid &= 0xff; /* mask out delivery bits */
1983 msid |= (1<<14);
1984 pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
1985
1986 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
1987 I915_WRITE(VLV_IER, enable_mask);
1988 I915_WRITE(VLV_IIR, 0xffffffff);
1989 I915_WRITE(PIPESTAT(0), 0xffff);
1990 I915_WRITE(PIPESTAT(1), 0xffff);
1991 POSTING_READ(VLV_IER);
1992
31acc7f5
JB		 1993 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
1994 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
1995
7e231dbe
JB		 1996 I915_WRITE(VLV_IIR, 0xffffffff);
1997 I915_WRITE(VLV_IIR, 0xffffffff);
1998
7e231dbe 1999 I915_WRITE(GTIIR, I915_READ(GTIIR));
31acc7f5 2000 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
3bcedbe5
JB		 2001
2002 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2003 GEN6_BLITTER_USER_INTERRUPT;
2004 I915_WRITE(GTIER, render_irqs);
7e231dbe
JB		 2005 POSTING_READ(GTIER);
2006
2007 /* ack & enable invalid PTE error interrupts */
2008#if 0 /* FIXME: add support to irq handler for checking these bits */
2009 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2010 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2011#endif
2012
2013 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
7e231dbe
JB		 2014 /* Note HDMI and DP share bits */
2015 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2016 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2017 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2018 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2019 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2020 hotplug_en |= HDMID_HOTPLUG_INT_EN;
ae33cdcf 2021 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
7e231dbe 2022 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
ae33cdcf 2023 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
7e231dbe
JB		 2024 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2025 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2026 hotplug_en |= CRT_HOTPLUG_INT_EN;
2027 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2028 }
7e231dbe
JB		 2029
2030 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2031
2032 return 0;
2033}
2034
7e231dbe
JB		 2035static void valleyview_irq_uninstall(struct drm_device *dev)
2036{
2037 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2038 int pipe;
2039
2040 if (!dev_priv)
2041 return;
2042
7e231dbe
JB		 2043 for_each_pipe(pipe)
2044 I915_WRITE(PIPESTAT(pipe), 0xffff);
2045
2046 I915_WRITE(HWSTAM, 0xffffffff);
2047 I915_WRITE(PORT_HOTPLUG_EN, 0);
2048 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2049 for_each_pipe(pipe)
2050 I915_WRITE(PIPESTAT(pipe), 0xffff);
2051 I915_WRITE(VLV_IIR, 0xffffffff);
2052 I915_WRITE(VLV_IMR, 0xffffffff);
2053 I915_WRITE(VLV_IER, 0x0);
2054 POSTING_READ(VLV_IER);
2055}
2056
f71d4af4 2057static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 2058{
2059 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 2060
2061 if (!dev_priv)
2062 return;
2063
036a4a7d
ZW		 2064 I915_WRITE(HWSTAM, 0xffffffff);
2065
2066 I915_WRITE(DEIMR, 0xffffffff);
2067 I915_WRITE(DEIER, 0x0);
2068 I915_WRITE(DEIIR, I915_READ(DEIIR));
2069
2070 I915_WRITE(GTIMR, 0xffffffff);
2071 I915_WRITE(GTIER, 0x0);
2072 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f
KP		 2073
2074 I915_WRITE(SDEIMR, 0xffffffff);
2075 I915_WRITE(SDEIER, 0x0);
2076 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
036a4a7d
ZW		 2077}
2078
a266c7d5 2079static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 2080{
2081 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2082 int pipe;
91e3738e 2083
a266c7d5 2084 atomic_set(&dev_priv->irq_received, 0);
5ca58282 2085
9db4a9c7
JB		 2086 for_each_pipe(pipe)
2087 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 2088 I915_WRITE16(IMR, 0xffff);
2089 I915_WRITE16(IER, 0x0);
2090 POSTING_READ16(IER);
c2798b19
CW		 2091}
2092
2093static int i8xx_irq_postinstall(struct drm_device *dev)
2094{
2095 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2096
c2798b19
CW		 2097 dev_priv->pipestat[0] = 0;
2098 dev_priv->pipestat[1] = 0;
2099
2100 I915_WRITE16(EMR,
2101 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2102
2103 /* Unmask the interrupts that we always want on. */
2104 dev_priv->irq_mask =
2105 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2106 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2107 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2108 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2109 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2110 I915_WRITE16(IMR, dev_priv->irq_mask);
2111
2112 I915_WRITE16(IER,
2113 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2114 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2115 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2116 I915_USER_INTERRUPT);
2117 POSTING_READ16(IER);
2118
2119 return 0;
2120}
2121
ff1f525e 2122static irqreturn_t i8xx_irq_handler(int irq, void *arg)
c2798b19
CW		 2123{
2124 struct drm_device *dev = (struct drm_device *) arg;
2125 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 2126 u16 iir, new_iir;
2127 u32 pipe_stats[2];
2128 unsigned long irqflags;
2129 int irq_received;
2130 int pipe;
2131 u16 flip_mask =
2132 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2133 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2134
2135 atomic_inc(&dev_priv->irq_received);
2136
2137 iir = I915_READ16(IIR);
2138 if (iir == 0)
2139 return IRQ_NONE;
2140
2141 while (iir & ~flip_mask) {
2142 /* Can't rely on pipestat interrupt bit in iir as it might
2143 * have been cleared after the pipestat interrupt was received.
2144 * It doesn't set the bit in iir again, but it still produces
2145 * interrupts (for non-MSI).
2146 */
2147 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2148 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2149 i915_handle_error(dev, false);
2150
2151 for_each_pipe(pipe) {
2152 int reg = PIPESTAT(pipe);
2153 pipe_stats[pipe] = I915_READ(reg);
2154
2155 /*
2156 * Clear the PIPE*STAT regs before the IIR
2157 */
2158 if (pipe_stats[pipe] & 0x8000ffff) {
2159 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2160 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2161 pipe_name(pipe));
2162 I915_WRITE(reg, pipe_stats[pipe]);
2163 irq_received = 1;
2164 }
2165 }
2166 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2167
2168 I915_WRITE16(IIR, iir & ~flip_mask);
2169 new_iir = I915_READ16(IIR); /* Flush posted writes */
2170
d05c617e 2171 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 2172
2173 if (iir & I915_USER_INTERRUPT)
2174 notify_ring(dev, &dev_priv->ring[RCS]);
2175
2176 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2177 drm_handle_vblank(dev, 0)) {
2178 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2179 intel_prepare_page_flip(dev, 0);
2180 intel_finish_page_flip(dev, 0);
2181 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2182 }
2183 }
2184
2185 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2186 drm_handle_vblank(dev, 1)) {
2187 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2188 intel_prepare_page_flip(dev, 1);
2189 intel_finish_page_flip(dev, 1);
2190 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2191 }
2192 }
2193
2194 iir = new_iir;
2195 }
2196
2197 return IRQ_HANDLED;
2198}
2199
2200static void i8xx_irq_uninstall(struct drm_device * dev)
2201{
2202 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2203 int pipe;
2204
c2798b19
CW		 2205 for_each_pipe(pipe) {
2206 /* Clear enable bits; then clear status bits */
2207 I915_WRITE(PIPESTAT(pipe), 0);
2208 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2209 }
2210 I915_WRITE16(IMR, 0xffff);
2211 I915_WRITE16(IER, 0x0);
2212 I915_WRITE16(IIR, I915_READ16(IIR));
2213}
2214
a266c7d5
CW		 2215static void i915_irq_preinstall(struct drm_device * dev)
2216{
2217 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2218 int pipe;
2219
2220 atomic_set(&dev_priv->irq_received, 0);
2221
2222 if (I915_HAS_HOTPLUG(dev)) {
2223 I915_WRITE(PORT_HOTPLUG_EN, 0);
2224 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2225 }
2226
00d98ebd 2227 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 2228 for_each_pipe(pipe)
2229 I915_WRITE(PIPESTAT(pipe), 0);
2230 I915_WRITE(IMR, 0xffffffff);
2231 I915_WRITE(IER, 0x0);
2232 POSTING_READ(IER);
2233}
2234
2235static int i915_irq_postinstall(struct drm_device *dev)
2236{
2237 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 2238 u32 enable_mask;
a266c7d5 2239
a266c7d5
CW		 2240 dev_priv->pipestat[0] = 0;
2241 dev_priv->pipestat[1] = 0;
2242
38bde180
CW		 2243 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2244
2245 /* Unmask the interrupts that we always want on. */
2246 dev_priv->irq_mask =
2247 ~(I915_ASLE_INTERRUPT |
2248 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2249 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2250 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2251 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2252 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2253
2254 enable_mask =
2255 I915_ASLE_INTERRUPT |
2256 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2257 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2258 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2259 I915_USER_INTERRUPT;
2260
a266c7d5
CW		 2261 if (I915_HAS_HOTPLUG(dev)) {
2262 /* Enable in IER... */
2263 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2264 /* and unmask in IMR */
2265 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2266 }
2267
a266c7d5
CW		 2268 I915_WRITE(IMR, dev_priv->irq_mask);
2269 I915_WRITE(IER, enable_mask);
2270 POSTING_READ(IER);
2271
2272 if (I915_HAS_HOTPLUG(dev)) {
2273 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2274
a266c7d5
CW		 2275 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2276 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2277 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2278 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2279 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2280 hotplug_en |= HDMID_HOTPLUG_INT_EN;
084b612e 2281 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
a266c7d5 2282 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
084b612e 2283 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
a266c7d5
CW		 2284 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2285 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2286 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5
CW		 2287 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2288 }
2289
2290 /* Ignore TV since it's buggy */
2291
2292 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2293 }
2294
2295 intel_opregion_enable_asle(dev);
2296
2297 return 0;
2298}
2299
ff1f525e 2300static irqreturn_t i915_irq_handler(int irq, void *arg)
a266c7d5
CW		 2301{
2302 struct drm_device *dev = (struct drm_device *) arg;
2303 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 2304 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 2305 unsigned long irqflags;
38bde180
CW		 2306 u32 flip_mask =
2307 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2308 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2309 u32 flip[2] = {
2310 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2311 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2312 };
2313 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 2314
2315 atomic_inc(&dev_priv->irq_received);
2316
2317 iir = I915_READ(IIR);
38bde180
CW		 2318 do {
2319 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 2320 bool blc_event = false;
a266c7d5
CW		 2321
2322 /* Can't rely on pipestat interrupt bit in iir as it might
2323 * have been cleared after the pipestat interrupt was received.
2324 * It doesn't set the bit in iir again, but it still produces
2325 * interrupts (for non-MSI).
2326 */
2327 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2328 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2329 i915_handle_error(dev, false);
2330
2331 for_each_pipe(pipe) {
2332 int reg = PIPESTAT(pipe);
2333 pipe_stats[pipe] = I915_READ(reg);
2334
38bde180 2335 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 2336 if (pipe_stats[pipe] & 0x8000ffff) {
2337 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2338 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2339 pipe_name(pipe));
2340 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 2341 irq_received = true;
a266c7d5
CW		 2342 }
2343 }
2344 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2345
2346 if (!irq_received)
2347 break;
2348
a266c7d5
CW		 2349 /* Consume port. Then clear IIR or we'll miss events */
2350 if ((I915_HAS_HOTPLUG(dev)) &&
2351 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2352 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2353
2354 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2355 hotplug_status);
2356 if (hotplug_status & dev_priv->hotplug_supported_mask)
2357 queue_work(dev_priv->wq,
2358 &dev_priv->hotplug_work);
2359
2360 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 2361 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 2362 }
2363
38bde180 2364 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2365 new_iir = I915_READ(IIR); /* Flush posted writes */
2366
a266c7d5
CW		 2367 if (iir & I915_USER_INTERRUPT)
2368 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 2369
a266c7d5 2370 for_each_pipe(pipe) {
38bde180
CW		 2371 int plane = pipe;
2372 if (IS_MOBILE(dev))
2373 plane = !plane;
8291ee90 2374 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2375 drm_handle_vblank(dev, pipe)) {
38bde180
CW		 2376 if (iir & flip[plane]) {
2377 intel_prepare_page_flip(dev, plane);
2378 intel_finish_page_flip(dev, pipe);
2379 flip_mask &= ~flip[plane];
2380 }
a266c7d5
CW		 2381 }
2382
2383 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2384 blc_event = true;
2385 }
2386
a266c7d5
CW		 2387 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2388 intel_opregion_asle_intr(dev);
2389
2390 /* With MSI, interrupts are only generated when iir
2391 * transitions from zero to nonzero. If another bit got
2392 * set while we were handling the existing iir bits, then
2393 * we would never get another interrupt.
2394 *
2395 * This is fine on non-MSI as well, as if we hit this path
2396 * we avoid exiting the interrupt handler only to generate
2397 * another one.
2398 *
2399 * Note that for MSI this could cause a stray interrupt report
2400 * if an interrupt landed in the time between writing IIR and
2401 * the posting read. This should be rare enough to never
2402 * trigger the 99% of 100,000 interrupts test for disabling
2403 * stray interrupts.
2404 */
38bde180 2405 ret = IRQ_HANDLED;
a266c7d5 2406 iir = new_iir;
38bde180 2407 } while (iir & ~flip_mask);
a266c7d5 2408
d05c617e 2409 i915_update_dri1_breadcrumb(dev);
8291ee90 2410
a266c7d5
CW		 2411 return ret;
2412}
2413
2414static void i915_irq_uninstall(struct drm_device * dev)
2415{
2416 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2417 int pipe;
2418
a266c7d5
CW		 2419 if (I915_HAS_HOTPLUG(dev)) {
2420 I915_WRITE(PORT_HOTPLUG_EN, 0);
2421 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2422 }
2423
00d98ebd 2424 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 2425 for_each_pipe(pipe) {
2426 /* Clear enable bits; then clear status bits */
a266c7d5 2427 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 2428 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2429 }
a266c7d5
CW		 2430 I915_WRITE(IMR, 0xffffffff);
2431 I915_WRITE(IER, 0x0);
2432
a266c7d5
CW		 2433 I915_WRITE(IIR, I915_READ(IIR));
2434}
2435
2436static void i965_irq_preinstall(struct drm_device * dev)
2437{
2438 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2439 int pipe;
2440
2441 atomic_set(&dev_priv->irq_received, 0);
2442
adca4730
CW		 2443 I915_WRITE(PORT_HOTPLUG_EN, 0);
2444 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2445
2446 I915_WRITE(HWSTAM, 0xeffe);
2447 for_each_pipe(pipe)
2448 I915_WRITE(PIPESTAT(pipe), 0);
2449 I915_WRITE(IMR, 0xffffffff);
2450 I915_WRITE(IER, 0x0);
2451 POSTING_READ(IER);
2452}
2453
2454static int i965_irq_postinstall(struct drm_device *dev)
2455{
2456 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
adca4730 2457 u32 hotplug_en;
bbba0a97 2458 u32 enable_mask;
a266c7d5
CW		 2459 u32 error_mask;
2460
a266c7d5 2461 /* Unmask the interrupts that we always want on. */
bbba0a97 2462 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 2463 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 2464 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2465 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2466 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2467 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2468 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2469
2470 enable_mask = ~dev_priv->irq_mask;
2471 enable_mask |= I915_USER_INTERRUPT;
2472
2473 if (IS_G4X(dev))
2474 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5
CW		 2475
2476 dev_priv->pipestat[0] = 0;
2477 dev_priv->pipestat[1] = 0;
2478
a266c7d5
CW		 2479 /*
2480 * Enable some error detection, note the instruction error mask
2481 * bit is reserved, so we leave it masked.
2482 */
2483 if (IS_G4X(dev)) {
2484 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2485 GM45_ERROR_MEM_PRIV |
2486 GM45_ERROR_CP_PRIV |
2487 I915_ERROR_MEMORY_REFRESH);
2488 } else {
2489 error_mask = ~(I915_ERROR_PAGE_TABLE |
2490 I915_ERROR_MEMORY_REFRESH);
2491 }
2492 I915_WRITE(EMR, error_mask);
2493
2494 I915_WRITE(IMR, dev_priv->irq_mask);
2495 I915_WRITE(IER, enable_mask);
2496 POSTING_READ(IER);
2497
adca4730
CW		 2498 /* Note HDMI and DP share hotplug bits */
2499 hotplug_en = 0;
2500 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2501 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2502 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2503 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2504 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2505 hotplug_en |= HDMID_HOTPLUG_INT_EN;
084b612e
CW		 2506 if (IS_G4X(dev)) {
2507 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
2508 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2509 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
2510 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2511 } else {
2512 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
2513 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2514 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
2515 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2516 }
adca4730
CW		 2517 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2518 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5 2519
adca4730
CW		 2520 /* Programming the CRT detection parameters tends
2521 to generate a spurious hotplug event about three
2522 seconds later. So just do it once.
2523 */
2524 if (IS_G4X(dev))
2525 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2526 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2527 }
a266c7d5 2528
adca4730 2529 /* Ignore TV since it's buggy */
a266c7d5 2530
adca4730 2531 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
a266c7d5
CW		 2532
2533 intel_opregion_enable_asle(dev);
2534
2535 return 0;
2536}
2537
ff1f525e 2538static irqreturn_t i965_irq_handler(int irq, void *arg)
a266c7d5
CW		 2539{
2540 struct drm_device *dev = (struct drm_device *) arg;
2541 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 2542 u32 iir, new_iir;
2543 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 2544 unsigned long irqflags;
2545 int irq_received;
2546 int ret = IRQ_NONE, pipe;
a266c7d5
CW		 2547
2548 atomic_inc(&dev_priv->irq_received);
2549
2550 iir = I915_READ(IIR);
2551
a266c7d5 2552 for (;;) {
2c8ba29f
CW		 2553 bool blc_event = false;
2554
a266c7d5
CW		 2555 irq_received = iir != 0;
2556
2557 /* Can't rely on pipestat interrupt bit in iir as it might
2558 * have been cleared after the pipestat interrupt was received.
2559 * It doesn't set the bit in iir again, but it still produces
2560 * interrupts (for non-MSI).
2561 */
2562 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2563 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2564 i915_handle_error(dev, false);
2565
2566 for_each_pipe(pipe) {
2567 int reg = PIPESTAT(pipe);
2568 pipe_stats[pipe] = I915_READ(reg);
2569
2570 /*
2571 * Clear the PIPE*STAT regs before the IIR
2572 */
2573 if (pipe_stats[pipe] & 0x8000ffff) {
2574 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2575 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2576 pipe_name(pipe));
2577 I915_WRITE(reg, pipe_stats[pipe]);
2578 irq_received = 1;
2579 }
2580 }
2581 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2582
2583 if (!irq_received)
2584 break;
2585
2586 ret = IRQ_HANDLED;
2587
2588 /* Consume port. Then clear IIR or we'll miss events */
adca4730 2589 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
a266c7d5
CW		 2590 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2591
2592 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2593 hotplug_status);
2594 if (hotplug_status & dev_priv->hotplug_supported_mask)
2595 queue_work(dev_priv->wq,
2596 &dev_priv->hotplug_work);
2597
2598 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2599 I915_READ(PORT_HOTPLUG_STAT);
2600 }
2601
2602 I915_WRITE(IIR, iir);
2603 new_iir = I915_READ(IIR); /* Flush posted writes */
2604
a266c7d5
CW		 2605 if (iir & I915_USER_INTERRUPT)
2606 notify_ring(dev, &dev_priv->ring[RCS]);
2607 if (iir & I915_BSD_USER_INTERRUPT)
2608 notify_ring(dev, &dev_priv->ring[VCS]);
2609
4f7d1e79 2610 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
a266c7d5 2611 intel_prepare_page_flip(dev, 0);
a266c7d5 2612
4f7d1e79 2613 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
a266c7d5 2614 intel_prepare_page_flip(dev, 1);
a266c7d5
CW		 2615
2616 for_each_pipe(pipe) {
2c8ba29f 2617 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2618 drm_handle_vblank(dev, pipe)) {
4f7d1e79
CW		 2619 i915_pageflip_stall_check(dev, pipe);
2620 intel_finish_page_flip(dev, pipe);
a266c7d5
CW		 2621 }
2622
2623 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2624 blc_event = true;
2625 }
2626
2627
2628 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2629 intel_opregion_asle_intr(dev);
2630
2631 /* With MSI, interrupts are only generated when iir
2632 * transitions from zero to nonzero. If another bit got
2633 * set while we were handling the existing iir bits, then
2634 * we would never get another interrupt.
2635 *
2636 * This is fine on non-MSI as well, as if we hit this path
2637 * we avoid exiting the interrupt handler only to generate
2638 * another one.
2639 *
2640 * Note that for MSI this could cause a stray interrupt report
2641 * if an interrupt landed in the time between writing IIR and
2642 * the posting read. This should be rare enough to never
2643 * trigger the 99% of 100,000 interrupts test for disabling
2644 * stray interrupts.
2645 */
2646 iir = new_iir;
2647 }
2648
d05c617e 2649 i915_update_dri1_breadcrumb(dev);
2c8ba29f 2650
a266c7d5
CW		 2651 return ret;
2652}
2653
2654static void i965_irq_uninstall(struct drm_device * dev)
2655{
2656 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2657 int pipe;
2658
2659 if (!dev_priv)
2660 return;
2661
adca4730
CW		 2662 I915_WRITE(PORT_HOTPLUG_EN, 0);
2663 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2664
2665 I915_WRITE(HWSTAM, 0xffffffff);
2666 for_each_pipe(pipe)
2667 I915_WRITE(PIPESTAT(pipe), 0);
2668 I915_WRITE(IMR, 0xffffffff);
2669 I915_WRITE(IER, 0x0);
2670
2671 for_each_pipe(pipe)
2672 I915_WRITE(PIPESTAT(pipe),
2673 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2674 I915_WRITE(IIR, I915_READ(IIR));
2675}
2676
f71d4af4
JB		 2677void intel_irq_init(struct drm_device *dev)
2678{
8b2e326d
CW		 2679 struct drm_i915_private *dev_priv = dev->dev_private;
2680
2681 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2682 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
c6a828d3 2683 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
98fd81cd 2684 INIT_WORK(&dev_priv->parity_error_work, ivybridge_parity_work);
8b2e326d 2685
f71d4af4
JB		 2686 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2687 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7d4e146f 2688 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 2689 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2690 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2691 }
2692
c3613de9
KP		 2693 if (drm_core_check_feature(dev, DRIVER_MODESET))
2694 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2695 else
2696 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 2697 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2698
7e231dbe
JB		 2699 if (IS_VALLEYVIEW(dev)) {
2700 dev->driver->irq_handler = valleyview_irq_handler;
2701 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2702 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2703 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2704 dev->driver->enable_vblank = valleyview_enable_vblank;
2705 dev->driver->disable_vblank = valleyview_disable_vblank;
2706 } else if (IS_IVYBRIDGE(dev)) {
f71d4af4
JB		 2707 /* Share pre & uninstall handlers with ILK/SNB */
2708 dev->driver->irq_handler = ivybridge_irq_handler;
2709 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2710 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2711 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2712 dev->driver->enable_vblank = ivybridge_enable_vblank;
2713 dev->driver->disable_vblank = ivybridge_disable_vblank;
7d4e146f
ED		 2714 } else if (IS_HASWELL(dev)) {
2715 /* Share interrupts handling with IVB */
2716 dev->driver->irq_handler = ivybridge_irq_handler;
2717 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2718 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2719 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2720 dev->driver->enable_vblank = ivybridge_enable_vblank;
2721 dev->driver->disable_vblank = ivybridge_disable_vblank;
f71d4af4
JB		 2722 } else if (HAS_PCH_SPLIT(dev)) {
2723 dev->driver->irq_handler = ironlake_irq_handler;
2724 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2725 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2726 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2727 dev->driver->enable_vblank = ironlake_enable_vblank;
2728 dev->driver->disable_vblank = ironlake_disable_vblank;
2729 } else {
c2798b19
CW		 2730 if (INTEL_INFO(dev)->gen == 2) {
2731 dev->driver->irq_preinstall = i8xx_irq_preinstall;
2732 dev->driver->irq_postinstall = i8xx_irq_postinstall;
2733 dev->driver->irq_handler = i8xx_irq_handler;
2734 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5
CW		 2735 } else if (INTEL_INFO(dev)->gen == 3) {
2736 dev->driver->irq_preinstall = i915_irq_preinstall;
2737 dev->driver->irq_postinstall = i915_irq_postinstall;
2738 dev->driver->irq_uninstall = i915_irq_uninstall;
2739 dev->driver->irq_handler = i915_irq_handler;
c2798b19 2740 } else {
a266c7d5
CW		 2741 dev->driver->irq_preinstall = i965_irq_preinstall;
2742 dev->driver->irq_postinstall = i965_irq_postinstall;
2743 dev->driver->irq_uninstall = i965_irq_uninstall;
2744 dev->driver->irq_handler = i965_irq_handler;
c2798b19 2745 }
f71d4af4
JB		 2746 dev->driver->enable_vblank = i915_enable_vblank;
2747 dev->driver->disable_vblank = i915_disable_vblank;
2748 }
2749}
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