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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
63eeaf38 | 31 | #include <linux/sysrq.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
b2c88f5b | 33 | #include <linux/circ_buf.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/i915_drm.h> | |
1da177e4 | 36 | #include "i915_drv.h" |
1c5d22f7 | 37 | #include "i915_trace.h" |
79e53945 | 38 | #include "intel_drv.h" |
1da177e4 | 39 | |
e5868a31 EE |
40 | static const u32 hpd_ibx[] = { |
41 | [HPD_CRT] = SDE_CRT_HOTPLUG, | |
42 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, | |
43 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG, | |
44 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG, | |
45 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG | |
46 | }; | |
47 | ||
48 | static const u32 hpd_cpt[] = { | |
49 | [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, | |
73c352a2 | 50 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, |
e5868a31 EE |
51 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
52 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
53 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT | |
54 | }; | |
55 | ||
56 | static const u32 hpd_mask_i915[] = { | |
57 | [HPD_CRT] = CRT_HOTPLUG_INT_EN, | |
58 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, | |
59 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, | |
60 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, | |
61 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, | |
62 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN | |
63 | }; | |
64 | ||
704cfb87 | 65 | static const u32 hpd_status_g4x[] = { |
e5868a31 EE |
66 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
67 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, | |
68 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, | |
69 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
70 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
71 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
72 | }; | |
73 | ||
e5868a31 EE |
74 | static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ |
75 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, | |
76 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, | |
77 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, | |
78 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
79 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
80 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
81 | }; | |
82 | ||
036a4a7d | 83 | /* For display hotplug interrupt */ |
995b6762 | 84 | static void |
f2b115e6 | 85 | ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d | 86 | { |
4bc9d430 DV |
87 | assert_spin_locked(&dev_priv->irq_lock); |
88 | ||
c67a470b PZ |
89 | if (dev_priv->pc8.irqs_disabled) { |
90 | WARN(1, "IRQs disabled\n"); | |
91 | dev_priv->pc8.regsave.deimr &= ~mask; | |
92 | return; | |
93 | } | |
94 | ||
1ec14ad3 CW |
95 | if ((dev_priv->irq_mask & mask) != 0) { |
96 | dev_priv->irq_mask &= ~mask; | |
97 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 98 | POSTING_READ(DEIMR); |
036a4a7d ZW |
99 | } |
100 | } | |
101 | ||
0ff9800a | 102 | static void |
f2b115e6 | 103 | ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d | 104 | { |
4bc9d430 DV |
105 | assert_spin_locked(&dev_priv->irq_lock); |
106 | ||
c67a470b PZ |
107 | if (dev_priv->pc8.irqs_disabled) { |
108 | WARN(1, "IRQs disabled\n"); | |
109 | dev_priv->pc8.regsave.deimr |= mask; | |
110 | return; | |
111 | } | |
112 | ||
1ec14ad3 CW |
113 | if ((dev_priv->irq_mask & mask) != mask) { |
114 | dev_priv->irq_mask |= mask; | |
115 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 116 | POSTING_READ(DEIMR); |
036a4a7d ZW |
117 | } |
118 | } | |
119 | ||
43eaea13 PZ |
120 | /** |
121 | * ilk_update_gt_irq - update GTIMR | |
122 | * @dev_priv: driver private | |
123 | * @interrupt_mask: mask of interrupt bits to update | |
124 | * @enabled_irq_mask: mask of interrupt bits to enable | |
125 | */ | |
126 | static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, | |
127 | uint32_t interrupt_mask, | |
128 | uint32_t enabled_irq_mask) | |
129 | { | |
130 | assert_spin_locked(&dev_priv->irq_lock); | |
131 | ||
c67a470b PZ |
132 | if (dev_priv->pc8.irqs_disabled) { |
133 | WARN(1, "IRQs disabled\n"); | |
134 | dev_priv->pc8.regsave.gtimr &= ~interrupt_mask; | |
135 | dev_priv->pc8.regsave.gtimr |= (~enabled_irq_mask & | |
136 | interrupt_mask); | |
137 | return; | |
138 | } | |
139 | ||
43eaea13 PZ |
140 | dev_priv->gt_irq_mask &= ~interrupt_mask; |
141 | dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); | |
142 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
143 | POSTING_READ(GTIMR); | |
144 | } | |
145 | ||
146 | void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
147 | { | |
148 | ilk_update_gt_irq(dev_priv, mask, mask); | |
149 | } | |
150 | ||
151 | void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
152 | { | |
153 | ilk_update_gt_irq(dev_priv, mask, 0); | |
154 | } | |
155 | ||
edbfdb45 PZ |
156 | /** |
157 | * snb_update_pm_irq - update GEN6_PMIMR | |
158 | * @dev_priv: driver private | |
159 | * @interrupt_mask: mask of interrupt bits to update | |
160 | * @enabled_irq_mask: mask of interrupt bits to enable | |
161 | */ | |
162 | static void snb_update_pm_irq(struct drm_i915_private *dev_priv, | |
163 | uint32_t interrupt_mask, | |
164 | uint32_t enabled_irq_mask) | |
165 | { | |
605cd25b | 166 | uint32_t new_val; |
edbfdb45 PZ |
167 | |
168 | assert_spin_locked(&dev_priv->irq_lock); | |
169 | ||
c67a470b PZ |
170 | if (dev_priv->pc8.irqs_disabled) { |
171 | WARN(1, "IRQs disabled\n"); | |
172 | dev_priv->pc8.regsave.gen6_pmimr &= ~interrupt_mask; | |
173 | dev_priv->pc8.regsave.gen6_pmimr |= (~enabled_irq_mask & | |
174 | interrupt_mask); | |
175 | return; | |
176 | } | |
177 | ||
605cd25b | 178 | new_val = dev_priv->pm_irq_mask; |
f52ecbcf PZ |
179 | new_val &= ~interrupt_mask; |
180 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
181 | ||
605cd25b PZ |
182 | if (new_val != dev_priv->pm_irq_mask) { |
183 | dev_priv->pm_irq_mask = new_val; | |
184 | I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask); | |
f52ecbcf PZ |
185 | POSTING_READ(GEN6_PMIMR); |
186 | } | |
edbfdb45 PZ |
187 | } |
188 | ||
189 | void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
190 | { | |
191 | snb_update_pm_irq(dev_priv, mask, mask); | |
192 | } | |
193 | ||
194 | void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
195 | { | |
196 | snb_update_pm_irq(dev_priv, mask, 0); | |
197 | } | |
198 | ||
8664281b PZ |
199 | static bool ivb_can_enable_err_int(struct drm_device *dev) |
200 | { | |
201 | struct drm_i915_private *dev_priv = dev->dev_private; | |
202 | struct intel_crtc *crtc; | |
203 | enum pipe pipe; | |
204 | ||
4bc9d430 DV |
205 | assert_spin_locked(&dev_priv->irq_lock); |
206 | ||
8664281b PZ |
207 | for_each_pipe(pipe) { |
208 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
209 | ||
210 | if (crtc->cpu_fifo_underrun_disabled) | |
211 | return false; | |
212 | } | |
213 | ||
214 | return true; | |
215 | } | |
216 | ||
217 | static bool cpt_can_enable_serr_int(struct drm_device *dev) | |
218 | { | |
219 | struct drm_i915_private *dev_priv = dev->dev_private; | |
220 | enum pipe pipe; | |
221 | struct intel_crtc *crtc; | |
222 | ||
fee884ed DV |
223 | assert_spin_locked(&dev_priv->irq_lock); |
224 | ||
8664281b PZ |
225 | for_each_pipe(pipe) { |
226 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
227 | ||
228 | if (crtc->pch_fifo_underrun_disabled) | |
229 | return false; | |
230 | } | |
231 | ||
232 | return true; | |
233 | } | |
234 | ||
235 | static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev, | |
236 | enum pipe pipe, bool enable) | |
237 | { | |
238 | struct drm_i915_private *dev_priv = dev->dev_private; | |
239 | uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN : | |
240 | DE_PIPEB_FIFO_UNDERRUN; | |
241 | ||
242 | if (enable) | |
243 | ironlake_enable_display_irq(dev_priv, bit); | |
244 | else | |
245 | ironlake_disable_display_irq(dev_priv, bit); | |
246 | } | |
247 | ||
248 | static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev, | |
7336df65 | 249 | enum pipe pipe, bool enable) |
8664281b PZ |
250 | { |
251 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8664281b | 252 | if (enable) { |
7336df65 DV |
253 | I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); |
254 | ||
8664281b PZ |
255 | if (!ivb_can_enable_err_int(dev)) |
256 | return; | |
257 | ||
8664281b PZ |
258 | ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB); |
259 | } else { | |
7336df65 DV |
260 | bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB); |
261 | ||
262 | /* Change the state _after_ we've read out the current one. */ | |
8664281b | 263 | ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB); |
7336df65 DV |
264 | |
265 | if (!was_enabled && | |
266 | (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) { | |
267 | DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n", | |
268 | pipe_name(pipe)); | |
269 | } | |
8664281b PZ |
270 | } |
271 | } | |
272 | ||
38d83c96 DV |
273 | static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev, |
274 | enum pipe pipe, bool enable) | |
275 | { | |
276 | struct drm_i915_private *dev_priv = dev->dev_private; | |
277 | ||
278 | assert_spin_locked(&dev_priv->irq_lock); | |
279 | ||
280 | if (enable) | |
281 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN; | |
282 | else | |
283 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN; | |
284 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
285 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
286 | } | |
287 | ||
fee884ed DV |
288 | /** |
289 | * ibx_display_interrupt_update - update SDEIMR | |
290 | * @dev_priv: driver private | |
291 | * @interrupt_mask: mask of interrupt bits to update | |
292 | * @enabled_irq_mask: mask of interrupt bits to enable | |
293 | */ | |
294 | static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, | |
295 | uint32_t interrupt_mask, | |
296 | uint32_t enabled_irq_mask) | |
297 | { | |
298 | uint32_t sdeimr = I915_READ(SDEIMR); | |
299 | sdeimr &= ~interrupt_mask; | |
300 | sdeimr |= (~enabled_irq_mask & interrupt_mask); | |
301 | ||
302 | assert_spin_locked(&dev_priv->irq_lock); | |
303 | ||
c67a470b PZ |
304 | if (dev_priv->pc8.irqs_disabled && |
305 | (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) { | |
306 | WARN(1, "IRQs disabled\n"); | |
307 | dev_priv->pc8.regsave.sdeimr &= ~interrupt_mask; | |
308 | dev_priv->pc8.regsave.sdeimr |= (~enabled_irq_mask & | |
309 | interrupt_mask); | |
310 | return; | |
311 | } | |
312 | ||
fee884ed DV |
313 | I915_WRITE(SDEIMR, sdeimr); |
314 | POSTING_READ(SDEIMR); | |
315 | } | |
316 | #define ibx_enable_display_interrupt(dev_priv, bits) \ | |
317 | ibx_display_interrupt_update((dev_priv), (bits), (bits)) | |
318 | #define ibx_disable_display_interrupt(dev_priv, bits) \ | |
319 | ibx_display_interrupt_update((dev_priv), (bits), 0) | |
320 | ||
de28075d DV |
321 | static void ibx_set_fifo_underrun_reporting(struct drm_device *dev, |
322 | enum transcoder pch_transcoder, | |
8664281b PZ |
323 | bool enable) |
324 | { | |
8664281b | 325 | struct drm_i915_private *dev_priv = dev->dev_private; |
de28075d DV |
326 | uint32_t bit = (pch_transcoder == TRANSCODER_A) ? |
327 | SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER; | |
8664281b PZ |
328 | |
329 | if (enable) | |
fee884ed | 330 | ibx_enable_display_interrupt(dev_priv, bit); |
8664281b | 331 | else |
fee884ed | 332 | ibx_disable_display_interrupt(dev_priv, bit); |
8664281b PZ |
333 | } |
334 | ||
335 | static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, | |
336 | enum transcoder pch_transcoder, | |
337 | bool enable) | |
338 | { | |
339 | struct drm_i915_private *dev_priv = dev->dev_private; | |
340 | ||
341 | if (enable) { | |
1dd246fb DV |
342 | I915_WRITE(SERR_INT, |
343 | SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); | |
344 | ||
8664281b PZ |
345 | if (!cpt_can_enable_serr_int(dev)) |
346 | return; | |
347 | ||
fee884ed | 348 | ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
8664281b | 349 | } else { |
1dd246fb DV |
350 | uint32_t tmp = I915_READ(SERR_INT); |
351 | bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT); | |
352 | ||
353 | /* Change the state _after_ we've read out the current one. */ | |
fee884ed | 354 | ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
1dd246fb DV |
355 | |
356 | if (!was_enabled && | |
357 | (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) { | |
358 | DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n", | |
359 | transcoder_name(pch_transcoder)); | |
360 | } | |
8664281b | 361 | } |
8664281b PZ |
362 | } |
363 | ||
364 | /** | |
365 | * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages | |
366 | * @dev: drm device | |
367 | * @pipe: pipe | |
368 | * @enable: true if we want to report FIFO underrun errors, false otherwise | |
369 | * | |
370 | * This function makes us disable or enable CPU fifo underruns for a specific | |
371 | * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun | |
372 | * reporting for one pipe may also disable all the other CPU error interruts for | |
373 | * the other pipes, due to the fact that there's just one interrupt mask/enable | |
374 | * bit for all the pipes. | |
375 | * | |
376 | * Returns the previous state of underrun reporting. | |
377 | */ | |
378 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, | |
379 | enum pipe pipe, bool enable) | |
380 | { | |
381 | struct drm_i915_private *dev_priv = dev->dev_private; | |
382 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
383 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
384 | unsigned long flags; | |
385 | bool ret; | |
386 | ||
387 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
388 | ||
389 | ret = !intel_crtc->cpu_fifo_underrun_disabled; | |
390 | ||
391 | if (enable == ret) | |
392 | goto done; | |
393 | ||
394 | intel_crtc->cpu_fifo_underrun_disabled = !enable; | |
395 | ||
396 | if (IS_GEN5(dev) || IS_GEN6(dev)) | |
397 | ironlake_set_fifo_underrun_reporting(dev, pipe, enable); | |
398 | else if (IS_GEN7(dev)) | |
7336df65 | 399 | ivybridge_set_fifo_underrun_reporting(dev, pipe, enable); |
38d83c96 DV |
400 | else if (IS_GEN8(dev)) |
401 | broadwell_set_fifo_underrun_reporting(dev, pipe, enable); | |
8664281b PZ |
402 | |
403 | done: | |
404 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
405 | return ret; | |
406 | } | |
407 | ||
408 | /** | |
409 | * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages | |
410 | * @dev: drm device | |
411 | * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) | |
412 | * @enable: true if we want to report FIFO underrun errors, false otherwise | |
413 | * | |
414 | * This function makes us disable or enable PCH fifo underruns for a specific | |
415 | * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO | |
416 | * underrun reporting for one transcoder may also disable all the other PCH | |
417 | * error interruts for the other transcoders, due to the fact that there's just | |
418 | * one interrupt mask/enable bit for all the transcoders. | |
419 | * | |
420 | * Returns the previous state of underrun reporting. | |
421 | */ | |
422 | bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, | |
423 | enum transcoder pch_transcoder, | |
424 | bool enable) | |
425 | { | |
426 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de28075d DV |
427 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder]; |
428 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8664281b PZ |
429 | unsigned long flags; |
430 | bool ret; | |
431 | ||
de28075d DV |
432 | /* |
433 | * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT | |
434 | * has only one pch transcoder A that all pipes can use. To avoid racy | |
435 | * pch transcoder -> pipe lookups from interrupt code simply store the | |
436 | * underrun statistics in crtc A. Since we never expose this anywhere | |
437 | * nor use it outside of the fifo underrun code here using the "wrong" | |
438 | * crtc on LPT won't cause issues. | |
439 | */ | |
8664281b PZ |
440 | |
441 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
442 | ||
443 | ret = !intel_crtc->pch_fifo_underrun_disabled; | |
444 | ||
445 | if (enable == ret) | |
446 | goto done; | |
447 | ||
448 | intel_crtc->pch_fifo_underrun_disabled = !enable; | |
449 | ||
450 | if (HAS_PCH_IBX(dev)) | |
de28075d | 451 | ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable); |
8664281b PZ |
452 | else |
453 | cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable); | |
454 | ||
455 | done: | |
456 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
457 | return ret; | |
458 | } | |
459 | ||
460 | ||
7c463586 | 461 | void |
3b6c42e8 | 462 | i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask) |
7c463586 | 463 | { |
46c06a30 VS |
464 | u32 reg = PIPESTAT(pipe); |
465 | u32 pipestat = I915_READ(reg) & 0x7fff0000; | |
7c463586 | 466 | |
b79480ba DV |
467 | assert_spin_locked(&dev_priv->irq_lock); |
468 | ||
46c06a30 VS |
469 | if ((pipestat & mask) == mask) |
470 | return; | |
471 | ||
472 | /* Enable the interrupt, clear any pending status */ | |
473 | pipestat |= mask | (mask >> 16); | |
474 | I915_WRITE(reg, pipestat); | |
475 | POSTING_READ(reg); | |
7c463586 KP |
476 | } |
477 | ||
478 | void | |
3b6c42e8 | 479 | i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask) |
7c463586 | 480 | { |
46c06a30 VS |
481 | u32 reg = PIPESTAT(pipe); |
482 | u32 pipestat = I915_READ(reg) & 0x7fff0000; | |
7c463586 | 483 | |
b79480ba DV |
484 | assert_spin_locked(&dev_priv->irq_lock); |
485 | ||
46c06a30 VS |
486 | if ((pipestat & mask) == 0) |
487 | return; | |
488 | ||
489 | pipestat &= ~mask; | |
490 | I915_WRITE(reg, pipestat); | |
491 | POSTING_READ(reg); | |
7c463586 KP |
492 | } |
493 | ||
01c66889 | 494 | /** |
f49e38dd | 495 | * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion |
01c66889 | 496 | */ |
f49e38dd | 497 | static void i915_enable_asle_pipestat(struct drm_device *dev) |
01c66889 | 498 | { |
1ec14ad3 CW |
499 | drm_i915_private_t *dev_priv = dev->dev_private; |
500 | unsigned long irqflags; | |
501 | ||
f49e38dd JN |
502 | if (!dev_priv->opregion.asle || !IS_MOBILE(dev)) |
503 | return; | |
504 | ||
1ec14ad3 | 505 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
01c66889 | 506 | |
3b6c42e8 | 507 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_ENABLE); |
f898780b | 508 | if (INTEL_INFO(dev)->gen >= 4) |
3b6c42e8 DV |
509 | i915_enable_pipestat(dev_priv, PIPE_A, |
510 | PIPE_LEGACY_BLC_EVENT_ENABLE); | |
1ec14ad3 CW |
511 | |
512 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
01c66889 ZY |
513 | } |
514 | ||
0a3e67a4 JB |
515 | /** |
516 | * i915_pipe_enabled - check if a pipe is enabled | |
517 | * @dev: DRM device | |
518 | * @pipe: pipe to check | |
519 | * | |
520 | * Reading certain registers when the pipe is disabled can hang the chip. | |
521 | * Use this routine to make sure the PLL is running and the pipe is active | |
522 | * before reading such registers if unsure. | |
523 | */ | |
524 | static int | |
525 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
526 | { | |
527 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
702e7a56 | 528 | |
a01025af DV |
529 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
530 | /* Locking is horribly broken here, but whatever. */ | |
531 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
532 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
71f8ba6b | 533 | |
a01025af DV |
534 | return intel_crtc->active; |
535 | } else { | |
536 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; | |
537 | } | |
0a3e67a4 JB |
538 | } |
539 | ||
4cdb83ec VS |
540 | static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe) |
541 | { | |
542 | /* Gen2 doesn't have a hardware frame counter */ | |
543 | return 0; | |
544 | } | |
545 | ||
42f52ef8 KP |
546 | /* Called from drm generic code, passed a 'crtc', which |
547 | * we use as a pipe index | |
548 | */ | |
f71d4af4 | 549 | static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
0a3e67a4 JB |
550 | { |
551 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
552 | unsigned long high_frame; | |
553 | unsigned long low_frame; | |
391f75e2 | 554 | u32 high1, high2, low, pixel, vbl_start; |
0a3e67a4 JB |
555 | |
556 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 557 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 558 | "pipe %c\n", pipe_name(pipe)); |
0a3e67a4 JB |
559 | return 0; |
560 | } | |
561 | ||
391f75e2 VS |
562 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
563 | struct intel_crtc *intel_crtc = | |
564 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
565 | const struct drm_display_mode *mode = | |
566 | &intel_crtc->config.adjusted_mode; | |
567 | ||
568 | vbl_start = mode->crtc_vblank_start * mode->crtc_htotal; | |
569 | } else { | |
a2d213dd | 570 | enum transcoder cpu_transcoder = (enum transcoder) pipe; |
391f75e2 VS |
571 | u32 htotal; |
572 | ||
573 | htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1; | |
574 | vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1; | |
575 | ||
576 | vbl_start *= htotal; | |
577 | } | |
578 | ||
9db4a9c7 JB |
579 | high_frame = PIPEFRAME(pipe); |
580 | low_frame = PIPEFRAMEPIXEL(pipe); | |
5eddb70b | 581 | |
0a3e67a4 JB |
582 | /* |
583 | * High & low register fields aren't synchronized, so make sure | |
584 | * we get a low value that's stable across two reads of the high | |
585 | * register. | |
586 | */ | |
587 | do { | |
5eddb70b | 588 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
391f75e2 | 589 | low = I915_READ(low_frame); |
5eddb70b | 590 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
0a3e67a4 JB |
591 | } while (high1 != high2); |
592 | ||
5eddb70b | 593 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
391f75e2 | 594 | pixel = low & PIPE_PIXEL_MASK; |
5eddb70b | 595 | low >>= PIPE_FRAME_LOW_SHIFT; |
391f75e2 VS |
596 | |
597 | /* | |
598 | * The frame counter increments at beginning of active. | |
599 | * Cook up a vblank counter by also checking the pixel | |
600 | * counter against vblank start. | |
601 | */ | |
edc08d0a | 602 | return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; |
0a3e67a4 JB |
603 | } |
604 | ||
f71d4af4 | 605 | static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
9880b7a5 JB |
606 | { |
607 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 608 | int reg = PIPE_FRMCOUNT_GM45(pipe); |
9880b7a5 JB |
609 | |
610 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 611 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 612 | "pipe %c\n", pipe_name(pipe)); |
9880b7a5 JB |
613 | return 0; |
614 | } | |
615 | ||
616 | return I915_READ(reg); | |
617 | } | |
618 | ||
ad3543ed MK |
619 | /* raw reads, only for fast reads of display block, no need for forcewake etc. */ |
620 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) | |
ad3543ed | 621 | |
095163ba | 622 | static bool ilk_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe) |
54ddcbd2 VS |
623 | { |
624 | struct drm_i915_private *dev_priv = dev->dev_private; | |
625 | uint32_t status; | |
24302624 VS |
626 | int reg; |
627 | ||
628 | if (INTEL_INFO(dev)->gen >= 8) { | |
629 | status = GEN8_PIPE_VBLANK; | |
630 | reg = GEN8_DE_PIPE_ISR(pipe); | |
631 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
632 | status = DE_PIPE_VBLANK_IVB(pipe); | |
633 | reg = DEISR; | |
54ddcbd2 | 634 | } else { |
24302624 VS |
635 | status = DE_PIPE_VBLANK(pipe); |
636 | reg = DEISR; | |
54ddcbd2 | 637 | } |
ad3543ed | 638 | |
24302624 | 639 | return __raw_i915_read32(dev_priv, reg) & status; |
54ddcbd2 VS |
640 | } |
641 | ||
f71d4af4 | 642 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
abca9e45 VS |
643 | unsigned int flags, int *vpos, int *hpos, |
644 | ktime_t *stime, ktime_t *etime) | |
0af7e4df | 645 | { |
c2baf4b7 VS |
646 | struct drm_i915_private *dev_priv = dev->dev_private; |
647 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
648 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
649 | const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; | |
3aa18df8 | 650 | int position; |
0af7e4df MK |
651 | int vbl_start, vbl_end, htotal, vtotal; |
652 | bool in_vbl = true; | |
653 | int ret = 0; | |
ad3543ed | 654 | unsigned long irqflags; |
0af7e4df | 655 | |
c2baf4b7 | 656 | if (!intel_crtc->active) { |
0af7e4df | 657 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
9db4a9c7 | 658 | "pipe %c\n", pipe_name(pipe)); |
0af7e4df MK |
659 | return 0; |
660 | } | |
661 | ||
c2baf4b7 VS |
662 | htotal = mode->crtc_htotal; |
663 | vtotal = mode->crtc_vtotal; | |
664 | vbl_start = mode->crtc_vblank_start; | |
665 | vbl_end = mode->crtc_vblank_end; | |
0af7e4df | 666 | |
d31faf65 VS |
667 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
668 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
669 | vbl_end /= 2; | |
670 | vtotal /= 2; | |
671 | } | |
672 | ||
c2baf4b7 VS |
673 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; |
674 | ||
ad3543ed MK |
675 | /* |
676 | * Lock uncore.lock, as we will do multiple timing critical raw | |
677 | * register reads, potentially with preemption disabled, so the | |
678 | * following code must not block on uncore.lock. | |
679 | */ | |
680 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
681 | ||
682 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ | |
683 | ||
684 | /* Get optional system timestamp before query. */ | |
685 | if (stime) | |
686 | *stime = ktime_get(); | |
687 | ||
7c06b08a | 688 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
0af7e4df MK |
689 | /* No obvious pixelcount register. Only query vertical |
690 | * scanout position from Display scan line register. | |
691 | */ | |
7c06b08a | 692 | if (IS_GEN2(dev)) |
ad3543ed | 693 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; |
7c06b08a | 694 | else |
ad3543ed | 695 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; |
54ddcbd2 | 696 | |
fcb81823 VS |
697 | if (HAS_DDI(dev)) { |
698 | /* | |
699 | * On HSW HDMI outputs there seems to be a 2 line | |
700 | * difference, whereas eDP has the normal 1 line | |
701 | * difference that earlier platforms have. External | |
702 | * DP is unknown. For now just check for the 2 line | |
703 | * difference case on all output types on HSW+. | |
704 | * | |
705 | * This might misinterpret the scanline counter being | |
706 | * one line too far along on eDP, but that's less | |
707 | * dangerous than the alternative since that would lead | |
708 | * the vblank timestamp code astray when it sees a | |
709 | * scanline count before vblank_start during a vblank | |
710 | * interrupt. | |
711 | */ | |
712 | in_vbl = ilk_pipe_in_vblank_locked(dev, pipe); | |
713 | if ((in_vbl && (position == vbl_start - 2 || | |
714 | position == vbl_start - 1)) || | |
715 | (!in_vbl && (position == vbl_end - 2 || | |
716 | position == vbl_end - 1))) | |
717 | position = (position + 2) % vtotal; | |
718 | } else if (HAS_PCH_SPLIT(dev)) { | |
095163ba VS |
719 | /* |
720 | * The scanline counter increments at the leading edge | |
721 | * of hsync, ie. it completely misses the active portion | |
722 | * of the line. Fix up the counter at both edges of vblank | |
723 | * to get a more accurate picture whether we're in vblank | |
724 | * or not. | |
725 | */ | |
726 | in_vbl = ilk_pipe_in_vblank_locked(dev, pipe); | |
727 | if ((in_vbl && position == vbl_start - 1) || | |
728 | (!in_vbl && position == vbl_end - 1)) | |
729 | position = (position + 1) % vtotal; | |
730 | } else { | |
731 | /* | |
732 | * ISR vblank status bits don't work the way we'd want | |
733 | * them to work on non-PCH platforms (for | |
734 | * ilk_pipe_in_vblank_locked()), and there doesn't | |
735 | * appear any other way to determine if we're currently | |
736 | * in vblank. | |
737 | * | |
738 | * Instead let's assume that we're already in vblank if | |
739 | * we got called from the vblank interrupt and the | |
740 | * scanline counter value indicates that we're on the | |
741 | * line just prior to vblank start. This should result | |
742 | * in the correct answer, unless the vblank interrupt | |
743 | * delivery really got delayed for almost exactly one | |
744 | * full frame/field. | |
745 | */ | |
746 | if (flags & DRM_CALLED_FROM_VBLIRQ && | |
747 | position == vbl_start - 1) { | |
748 | position = (position + 1) % vtotal; | |
749 | ||
750 | /* Signal this correction as "applied". */ | |
751 | ret |= 0x8; | |
752 | } | |
753 | } | |
0af7e4df MK |
754 | } else { |
755 | /* Have access to pixelcount since start of frame. | |
756 | * We can split this into vertical and horizontal | |
757 | * scanout position. | |
758 | */ | |
ad3543ed | 759 | position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; |
0af7e4df | 760 | |
3aa18df8 VS |
761 | /* convert to pixel counts */ |
762 | vbl_start *= htotal; | |
763 | vbl_end *= htotal; | |
764 | vtotal *= htotal; | |
0af7e4df MK |
765 | } |
766 | ||
ad3543ed MK |
767 | /* Get optional system timestamp after query. */ |
768 | if (etime) | |
769 | *etime = ktime_get(); | |
770 | ||
771 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ | |
772 | ||
773 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
774 | ||
3aa18df8 VS |
775 | in_vbl = position >= vbl_start && position < vbl_end; |
776 | ||
777 | /* | |
778 | * While in vblank, position will be negative | |
779 | * counting up towards 0 at vbl_end. And outside | |
780 | * vblank, position will be positive counting | |
781 | * up since vbl_end. | |
782 | */ | |
783 | if (position >= vbl_start) | |
784 | position -= vbl_end; | |
785 | else | |
786 | position += vtotal - vbl_end; | |
0af7e4df | 787 | |
7c06b08a | 788 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
3aa18df8 VS |
789 | *vpos = position; |
790 | *hpos = 0; | |
791 | } else { | |
792 | *vpos = position / htotal; | |
793 | *hpos = position - (*vpos * htotal); | |
794 | } | |
0af7e4df | 795 | |
0af7e4df MK |
796 | /* In vblank? */ |
797 | if (in_vbl) | |
798 | ret |= DRM_SCANOUTPOS_INVBL; | |
799 | ||
800 | return ret; | |
801 | } | |
802 | ||
f71d4af4 | 803 | static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
0af7e4df MK |
804 | int *max_error, |
805 | struct timeval *vblank_time, | |
806 | unsigned flags) | |
807 | { | |
4041b853 | 808 | struct drm_crtc *crtc; |
0af7e4df | 809 | |
7eb552ae | 810 | if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { |
4041b853 | 811 | DRM_ERROR("Invalid crtc %d\n", pipe); |
0af7e4df MK |
812 | return -EINVAL; |
813 | } | |
814 | ||
815 | /* Get drm_crtc to timestamp: */ | |
4041b853 CW |
816 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
817 | if (crtc == NULL) { | |
818 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
819 | return -EINVAL; | |
820 | } | |
821 | ||
822 | if (!crtc->enabled) { | |
823 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); | |
824 | return -EBUSY; | |
825 | } | |
0af7e4df MK |
826 | |
827 | /* Helper routine in DRM core does all the work: */ | |
4041b853 CW |
828 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
829 | vblank_time, flags, | |
7da903ef VS |
830 | crtc, |
831 | &to_intel_crtc(crtc)->config.adjusted_mode); | |
0af7e4df MK |
832 | } |
833 | ||
67c347ff JN |
834 | static bool intel_hpd_irq_event(struct drm_device *dev, |
835 | struct drm_connector *connector) | |
321a1b30 EE |
836 | { |
837 | enum drm_connector_status old_status; | |
838 | ||
839 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); | |
840 | old_status = connector->status; | |
841 | ||
842 | connector->status = connector->funcs->detect(connector, false); | |
67c347ff JN |
843 | if (old_status == connector->status) |
844 | return false; | |
845 | ||
846 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n", | |
321a1b30 EE |
847 | connector->base.id, |
848 | drm_get_connector_name(connector), | |
67c347ff JN |
849 | drm_get_connector_status_name(old_status), |
850 | drm_get_connector_status_name(connector->status)); | |
851 | ||
852 | return true; | |
321a1b30 EE |
853 | } |
854 | ||
5ca58282 JB |
855 | /* |
856 | * Handle hotplug events outside the interrupt handler proper. | |
857 | */ | |
ac4c16c5 EE |
858 | #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000) |
859 | ||
5ca58282 JB |
860 | static void i915_hotplug_work_func(struct work_struct *work) |
861 | { | |
862 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
863 | hotplug_work); | |
864 | struct drm_device *dev = dev_priv->dev; | |
c31c4ba3 | 865 | struct drm_mode_config *mode_config = &dev->mode_config; |
cd569aed EE |
866 | struct intel_connector *intel_connector; |
867 | struct intel_encoder *intel_encoder; | |
868 | struct drm_connector *connector; | |
869 | unsigned long irqflags; | |
870 | bool hpd_disabled = false; | |
321a1b30 | 871 | bool changed = false; |
142e2398 | 872 | u32 hpd_event_bits; |
4ef69c7a | 873 | |
52d7eced DV |
874 | /* HPD irq before everything is fully set up. */ |
875 | if (!dev_priv->enable_hotplug_processing) | |
876 | return; | |
877 | ||
a65e34c7 | 878 | mutex_lock(&mode_config->mutex); |
e67189ab JB |
879 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); |
880 | ||
cd569aed | 881 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
142e2398 EE |
882 | |
883 | hpd_event_bits = dev_priv->hpd_event_bits; | |
884 | dev_priv->hpd_event_bits = 0; | |
cd569aed EE |
885 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
886 | intel_connector = to_intel_connector(connector); | |
887 | intel_encoder = intel_connector->encoder; | |
888 | if (intel_encoder->hpd_pin > HPD_NONE && | |
889 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED && | |
890 | connector->polled == DRM_CONNECTOR_POLL_HPD) { | |
891 | DRM_INFO("HPD interrupt storm detected on connector %s: " | |
892 | "switching from hotplug detection to polling\n", | |
893 | drm_get_connector_name(connector)); | |
894 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED; | |
895 | connector->polled = DRM_CONNECTOR_POLL_CONNECT | |
896 | | DRM_CONNECTOR_POLL_DISCONNECT; | |
897 | hpd_disabled = true; | |
898 | } | |
142e2398 EE |
899 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { |
900 | DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n", | |
901 | drm_get_connector_name(connector), intel_encoder->hpd_pin); | |
902 | } | |
cd569aed EE |
903 | } |
904 | /* if there were no outputs to poll, poll was disabled, | |
905 | * therefore make sure it's enabled when disabling HPD on | |
906 | * some connectors */ | |
ac4c16c5 | 907 | if (hpd_disabled) { |
cd569aed | 908 | drm_kms_helper_poll_enable(dev); |
ac4c16c5 EE |
909 | mod_timer(&dev_priv->hotplug_reenable_timer, |
910 | jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY)); | |
911 | } | |
cd569aed EE |
912 | |
913 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
914 | ||
321a1b30 EE |
915 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
916 | intel_connector = to_intel_connector(connector); | |
917 | intel_encoder = intel_connector->encoder; | |
918 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { | |
919 | if (intel_encoder->hot_plug) | |
920 | intel_encoder->hot_plug(intel_encoder); | |
921 | if (intel_hpd_irq_event(dev, connector)) | |
922 | changed = true; | |
923 | } | |
924 | } | |
40ee3381 KP |
925 | mutex_unlock(&mode_config->mutex); |
926 | ||
321a1b30 EE |
927 | if (changed) |
928 | drm_kms_helper_hotplug_event(dev); | |
5ca58282 JB |
929 | } |
930 | ||
d0ecd7e2 | 931 | static void ironlake_rps_change_irq_handler(struct drm_device *dev) |
f97108d1 JB |
932 | { |
933 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b5b72e89 | 934 | u32 busy_up, busy_down, max_avg, min_avg; |
9270388e | 935 | u8 new_delay; |
9270388e | 936 | |
d0ecd7e2 | 937 | spin_lock(&mchdev_lock); |
f97108d1 | 938 | |
73edd18f DV |
939 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
940 | ||
20e4d407 | 941 | new_delay = dev_priv->ips.cur_delay; |
9270388e | 942 | |
7648fa99 | 943 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
944 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
945 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
946 | max_avg = I915_READ(RCBMAXAVG); |
947 | min_avg = I915_READ(RCBMINAVG); | |
948 | ||
949 | /* Handle RCS change request from hw */ | |
b5b72e89 | 950 | if (busy_up > max_avg) { |
20e4d407 DV |
951 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
952 | new_delay = dev_priv->ips.cur_delay - 1; | |
953 | if (new_delay < dev_priv->ips.max_delay) | |
954 | new_delay = dev_priv->ips.max_delay; | |
b5b72e89 | 955 | } else if (busy_down < min_avg) { |
20e4d407 DV |
956 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
957 | new_delay = dev_priv->ips.cur_delay + 1; | |
958 | if (new_delay > dev_priv->ips.min_delay) | |
959 | new_delay = dev_priv->ips.min_delay; | |
f97108d1 JB |
960 | } |
961 | ||
7648fa99 | 962 | if (ironlake_set_drps(dev, new_delay)) |
20e4d407 | 963 | dev_priv->ips.cur_delay = new_delay; |
f97108d1 | 964 | |
d0ecd7e2 | 965 | spin_unlock(&mchdev_lock); |
9270388e | 966 | |
f97108d1 JB |
967 | return; |
968 | } | |
969 | ||
549f7365 CW |
970 | static void notify_ring(struct drm_device *dev, |
971 | struct intel_ring_buffer *ring) | |
972 | { | |
475553de CW |
973 | if (ring->obj == NULL) |
974 | return; | |
975 | ||
814e9b57 | 976 | trace_i915_gem_request_complete(ring); |
9862e600 | 977 | |
549f7365 | 978 | wake_up_all(&ring->irq_queue); |
10cd45b6 | 979 | i915_queue_hangcheck(dev); |
549f7365 CW |
980 | } |
981 | ||
4912d041 | 982 | static void gen6_pm_rps_work(struct work_struct *work) |
3b8d8d91 | 983 | { |
4912d041 | 984 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
c6a828d3 | 985 | rps.work); |
edbfdb45 | 986 | u32 pm_iir; |
dd75fdc8 | 987 | int new_delay, adj; |
4912d041 | 988 | |
59cdb63d | 989 | spin_lock_irq(&dev_priv->irq_lock); |
c6a828d3 DV |
990 | pm_iir = dev_priv->rps.pm_iir; |
991 | dev_priv->rps.pm_iir = 0; | |
4848405c | 992 | /* Make sure not to corrupt PMIMR state used by ringbuffer code */ |
edbfdb45 | 993 | snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS); |
59cdb63d | 994 | spin_unlock_irq(&dev_priv->irq_lock); |
3b8d8d91 | 995 | |
60611c13 PZ |
996 | /* Make sure we didn't queue anything we're not going to process. */ |
997 | WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS); | |
998 | ||
4848405c | 999 | if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0) |
3b8d8d91 JB |
1000 | return; |
1001 | ||
4fc688ce | 1002 | mutex_lock(&dev_priv->rps.hw_lock); |
7b9e0ae6 | 1003 | |
dd75fdc8 | 1004 | adj = dev_priv->rps.last_adj; |
7425034a | 1005 | if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { |
dd75fdc8 CW |
1006 | if (adj > 0) |
1007 | adj *= 2; | |
1008 | else | |
1009 | adj = 1; | |
1010 | new_delay = dev_priv->rps.cur_delay + adj; | |
7425034a VS |
1011 | |
1012 | /* | |
1013 | * For better performance, jump directly | |
1014 | * to RPe if we're below it. | |
1015 | */ | |
dd75fdc8 CW |
1016 | if (new_delay < dev_priv->rps.rpe_delay) |
1017 | new_delay = dev_priv->rps.rpe_delay; | |
1018 | } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { | |
1019 | if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay) | |
7425034a | 1020 | new_delay = dev_priv->rps.rpe_delay; |
dd75fdc8 CW |
1021 | else |
1022 | new_delay = dev_priv->rps.min_delay; | |
1023 | adj = 0; | |
1024 | } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { | |
1025 | if (adj < 0) | |
1026 | adj *= 2; | |
1027 | else | |
1028 | adj = -1; | |
1029 | new_delay = dev_priv->rps.cur_delay + adj; | |
1030 | } else { /* unknown event */ | |
1031 | new_delay = dev_priv->rps.cur_delay; | |
1032 | } | |
3b8d8d91 | 1033 | |
79249636 BW |
1034 | /* sysfs frequency interfaces may have snuck in while servicing the |
1035 | * interrupt | |
1036 | */ | |
1272e7b8 VS |
1037 | new_delay = clamp_t(int, new_delay, |
1038 | dev_priv->rps.min_delay, dev_priv->rps.max_delay); | |
dd75fdc8 CW |
1039 | dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay; |
1040 | ||
1041 | if (IS_VALLEYVIEW(dev_priv->dev)) | |
1042 | valleyview_set_rps(dev_priv->dev, new_delay); | |
1043 | else | |
1044 | gen6_set_rps(dev_priv->dev, new_delay); | |
3b8d8d91 | 1045 | |
4fc688ce | 1046 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 JB |
1047 | } |
1048 | ||
e3689190 BW |
1049 | |
1050 | /** | |
1051 | * ivybridge_parity_work - Workqueue called when a parity error interrupt | |
1052 | * occurred. | |
1053 | * @work: workqueue struct | |
1054 | * | |
1055 | * Doesn't actually do anything except notify userspace. As a consequence of | |
1056 | * this event, userspace should try to remap the bad rows since statistically | |
1057 | * it is likely the same row is more likely to go bad again. | |
1058 | */ | |
1059 | static void ivybridge_parity_work(struct work_struct *work) | |
1060 | { | |
1061 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
a4da4fa4 | 1062 | l3_parity.error_work); |
e3689190 | 1063 | u32 error_status, row, bank, subbank; |
35a85ac6 | 1064 | char *parity_event[6]; |
e3689190 BW |
1065 | uint32_t misccpctl; |
1066 | unsigned long flags; | |
35a85ac6 | 1067 | uint8_t slice = 0; |
e3689190 BW |
1068 | |
1069 | /* We must turn off DOP level clock gating to access the L3 registers. | |
1070 | * In order to prevent a get/put style interface, acquire struct mutex | |
1071 | * any time we access those registers. | |
1072 | */ | |
1073 | mutex_lock(&dev_priv->dev->struct_mutex); | |
1074 | ||
35a85ac6 BW |
1075 | /* If we've screwed up tracking, just let the interrupt fire again */ |
1076 | if (WARN_ON(!dev_priv->l3_parity.which_slice)) | |
1077 | goto out; | |
1078 | ||
e3689190 BW |
1079 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
1080 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
1081 | POSTING_READ(GEN7_MISCCPCTL); | |
1082 | ||
35a85ac6 BW |
1083 | while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { |
1084 | u32 reg; | |
e3689190 | 1085 | |
35a85ac6 BW |
1086 | slice--; |
1087 | if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev))) | |
1088 | break; | |
e3689190 | 1089 | |
35a85ac6 | 1090 | dev_priv->l3_parity.which_slice &= ~(1<<slice); |
e3689190 | 1091 | |
35a85ac6 | 1092 | reg = GEN7_L3CDERRST1 + (slice * 0x200); |
e3689190 | 1093 | |
35a85ac6 BW |
1094 | error_status = I915_READ(reg); |
1095 | row = GEN7_PARITY_ERROR_ROW(error_status); | |
1096 | bank = GEN7_PARITY_ERROR_BANK(error_status); | |
1097 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); | |
1098 | ||
1099 | I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); | |
1100 | POSTING_READ(reg); | |
1101 | ||
1102 | parity_event[0] = I915_L3_PARITY_UEVENT "=1"; | |
1103 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); | |
1104 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); | |
1105 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); | |
1106 | parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); | |
1107 | parity_event[5] = NULL; | |
1108 | ||
5bdebb18 | 1109 | kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj, |
35a85ac6 | 1110 | KOBJ_CHANGE, parity_event); |
e3689190 | 1111 | |
35a85ac6 BW |
1112 | DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", |
1113 | slice, row, bank, subbank); | |
e3689190 | 1114 | |
35a85ac6 BW |
1115 | kfree(parity_event[4]); |
1116 | kfree(parity_event[3]); | |
1117 | kfree(parity_event[2]); | |
1118 | kfree(parity_event[1]); | |
1119 | } | |
e3689190 | 1120 | |
35a85ac6 | 1121 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
e3689190 | 1122 | |
35a85ac6 BW |
1123 | out: |
1124 | WARN_ON(dev_priv->l3_parity.which_slice); | |
1125 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1126 | ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev)); | |
1127 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1128 | ||
1129 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
e3689190 BW |
1130 | } |
1131 | ||
35a85ac6 | 1132 | static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir) |
e3689190 BW |
1133 | { |
1134 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e3689190 | 1135 | |
040d2baa | 1136 | if (!HAS_L3_DPF(dev)) |
e3689190 BW |
1137 | return; |
1138 | ||
d0ecd7e2 | 1139 | spin_lock(&dev_priv->irq_lock); |
35a85ac6 | 1140 | ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev)); |
d0ecd7e2 | 1141 | spin_unlock(&dev_priv->irq_lock); |
e3689190 | 1142 | |
35a85ac6 BW |
1143 | iir &= GT_PARITY_ERROR(dev); |
1144 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) | |
1145 | dev_priv->l3_parity.which_slice |= 1 << 1; | |
1146 | ||
1147 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) | |
1148 | dev_priv->l3_parity.which_slice |= 1 << 0; | |
1149 | ||
a4da4fa4 | 1150 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
e3689190 BW |
1151 | } |
1152 | ||
f1af8fc1 PZ |
1153 | static void ilk_gt_irq_handler(struct drm_device *dev, |
1154 | struct drm_i915_private *dev_priv, | |
1155 | u32 gt_iir) | |
1156 | { | |
1157 | if (gt_iir & | |
1158 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
1159 | notify_ring(dev, &dev_priv->ring[RCS]); | |
1160 | if (gt_iir & ILK_BSD_USER_INTERRUPT) | |
1161 | notify_ring(dev, &dev_priv->ring[VCS]); | |
1162 | } | |
1163 | ||
e7b4c6b1 DV |
1164 | static void snb_gt_irq_handler(struct drm_device *dev, |
1165 | struct drm_i915_private *dev_priv, | |
1166 | u32 gt_iir) | |
1167 | { | |
1168 | ||
cc609d5d BW |
1169 | if (gt_iir & |
1170 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
e7b4c6b1 | 1171 | notify_ring(dev, &dev_priv->ring[RCS]); |
cc609d5d | 1172 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
e7b4c6b1 | 1173 | notify_ring(dev, &dev_priv->ring[VCS]); |
cc609d5d | 1174 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
e7b4c6b1 DV |
1175 | notify_ring(dev, &dev_priv->ring[BCS]); |
1176 | ||
cc609d5d BW |
1177 | if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | |
1178 | GT_BSD_CS_ERROR_INTERRUPT | | |
1179 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) { | |
e7b4c6b1 DV |
1180 | DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir); |
1181 | i915_handle_error(dev, false); | |
1182 | } | |
e3689190 | 1183 | |
35a85ac6 BW |
1184 | if (gt_iir & GT_PARITY_ERROR(dev)) |
1185 | ivybridge_parity_error_irq_handler(dev, gt_iir); | |
e7b4c6b1 DV |
1186 | } |
1187 | ||
abd58f01 BW |
1188 | static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev, |
1189 | struct drm_i915_private *dev_priv, | |
1190 | u32 master_ctl) | |
1191 | { | |
1192 | u32 rcs, bcs, vcs; | |
1193 | uint32_t tmp = 0; | |
1194 | irqreturn_t ret = IRQ_NONE; | |
1195 | ||
1196 | if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { | |
1197 | tmp = I915_READ(GEN8_GT_IIR(0)); | |
1198 | if (tmp) { | |
1199 | ret = IRQ_HANDLED; | |
1200 | rcs = tmp >> GEN8_RCS_IRQ_SHIFT; | |
1201 | bcs = tmp >> GEN8_BCS_IRQ_SHIFT; | |
1202 | if (rcs & GT_RENDER_USER_INTERRUPT) | |
1203 | notify_ring(dev, &dev_priv->ring[RCS]); | |
1204 | if (bcs & GT_RENDER_USER_INTERRUPT) | |
1205 | notify_ring(dev, &dev_priv->ring[BCS]); | |
1206 | I915_WRITE(GEN8_GT_IIR(0), tmp); | |
1207 | } else | |
1208 | DRM_ERROR("The master control interrupt lied (GT0)!\n"); | |
1209 | } | |
1210 | ||
1211 | if (master_ctl & GEN8_GT_VCS1_IRQ) { | |
1212 | tmp = I915_READ(GEN8_GT_IIR(1)); | |
1213 | if (tmp) { | |
1214 | ret = IRQ_HANDLED; | |
1215 | vcs = tmp >> GEN8_VCS1_IRQ_SHIFT; | |
1216 | if (vcs & GT_RENDER_USER_INTERRUPT) | |
1217 | notify_ring(dev, &dev_priv->ring[VCS]); | |
1218 | I915_WRITE(GEN8_GT_IIR(1), tmp); | |
1219 | } else | |
1220 | DRM_ERROR("The master control interrupt lied (GT1)!\n"); | |
1221 | } | |
1222 | ||
1223 | if (master_ctl & GEN8_GT_VECS_IRQ) { | |
1224 | tmp = I915_READ(GEN8_GT_IIR(3)); | |
1225 | if (tmp) { | |
1226 | ret = IRQ_HANDLED; | |
1227 | vcs = tmp >> GEN8_VECS_IRQ_SHIFT; | |
1228 | if (vcs & GT_RENDER_USER_INTERRUPT) | |
1229 | notify_ring(dev, &dev_priv->ring[VECS]); | |
1230 | I915_WRITE(GEN8_GT_IIR(3), tmp); | |
1231 | } else | |
1232 | DRM_ERROR("The master control interrupt lied (GT3)!\n"); | |
1233 | } | |
1234 | ||
1235 | return ret; | |
1236 | } | |
1237 | ||
b543fb04 EE |
1238 | #define HPD_STORM_DETECT_PERIOD 1000 |
1239 | #define HPD_STORM_THRESHOLD 5 | |
1240 | ||
10a504de | 1241 | static inline void intel_hpd_irq_handler(struct drm_device *dev, |
22062dba DV |
1242 | u32 hotplug_trigger, |
1243 | const u32 *hpd) | |
b543fb04 EE |
1244 | { |
1245 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b543fb04 | 1246 | int i; |
10a504de | 1247 | bool storm_detected = false; |
b543fb04 | 1248 | |
91d131d2 DV |
1249 | if (!hotplug_trigger) |
1250 | return; | |
1251 | ||
b5ea2d56 | 1252 | spin_lock(&dev_priv->irq_lock); |
b543fb04 | 1253 | for (i = 1; i < HPD_NUM_PINS; i++) { |
821450c6 | 1254 | |
3432087e | 1255 | WARN_ONCE(hpd[i] & hotplug_trigger && |
8b5565b8 | 1256 | dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED, |
cba1c073 CW |
1257 | "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n", |
1258 | hotplug_trigger, i, hpd[i]); | |
b8f102e8 | 1259 | |
b543fb04 EE |
1260 | if (!(hpd[i] & hotplug_trigger) || |
1261 | dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED) | |
1262 | continue; | |
1263 | ||
bc5ead8c | 1264 | dev_priv->hpd_event_bits |= (1 << i); |
b543fb04 EE |
1265 | if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies, |
1266 | dev_priv->hpd_stats[i].hpd_last_jiffies | |
1267 | + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) { | |
1268 | dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies; | |
1269 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
b8f102e8 | 1270 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i); |
b543fb04 EE |
1271 | } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) { |
1272 | dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED; | |
142e2398 | 1273 | dev_priv->hpd_event_bits &= ~(1 << i); |
b543fb04 | 1274 | DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i); |
10a504de | 1275 | storm_detected = true; |
b543fb04 EE |
1276 | } else { |
1277 | dev_priv->hpd_stats[i].hpd_cnt++; | |
b8f102e8 EE |
1278 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i, |
1279 | dev_priv->hpd_stats[i].hpd_cnt); | |
b543fb04 EE |
1280 | } |
1281 | } | |
1282 | ||
10a504de DV |
1283 | if (storm_detected) |
1284 | dev_priv->display.hpd_irq_setup(dev); | |
b5ea2d56 | 1285 | spin_unlock(&dev_priv->irq_lock); |
5876fa0d | 1286 | |
645416f5 DV |
1287 | /* |
1288 | * Our hotplug handler can grab modeset locks (by calling down into the | |
1289 | * fb helpers). Hence it must not be run on our own dev-priv->wq work | |
1290 | * queue for otherwise the flush_work in the pageflip code will | |
1291 | * deadlock. | |
1292 | */ | |
1293 | schedule_work(&dev_priv->hotplug_work); | |
b543fb04 EE |
1294 | } |
1295 | ||
515ac2bb DV |
1296 | static void gmbus_irq_handler(struct drm_device *dev) |
1297 | { | |
28c70f16 DV |
1298 | struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private; |
1299 | ||
28c70f16 | 1300 | wake_up_all(&dev_priv->gmbus_wait_queue); |
515ac2bb DV |
1301 | } |
1302 | ||
ce99c256 DV |
1303 | static void dp_aux_irq_handler(struct drm_device *dev) |
1304 | { | |
9ee32fea DV |
1305 | struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private; |
1306 | ||
9ee32fea | 1307 | wake_up_all(&dev_priv->gmbus_wait_queue); |
ce99c256 DV |
1308 | } |
1309 | ||
8bf1e9f1 | 1310 | #if defined(CONFIG_DEBUG_FS) |
277de95e DV |
1311 | static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, |
1312 | uint32_t crc0, uint32_t crc1, | |
1313 | uint32_t crc2, uint32_t crc3, | |
1314 | uint32_t crc4) | |
8bf1e9f1 SH |
1315 | { |
1316 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1317 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; | |
1318 | struct intel_pipe_crc_entry *entry; | |
ac2300d4 | 1319 | int head, tail; |
b2c88f5b | 1320 | |
d538bbdf DL |
1321 | spin_lock(&pipe_crc->lock); |
1322 | ||
0c912c79 | 1323 | if (!pipe_crc->entries) { |
d538bbdf | 1324 | spin_unlock(&pipe_crc->lock); |
0c912c79 DL |
1325 | DRM_ERROR("spurious interrupt\n"); |
1326 | return; | |
1327 | } | |
1328 | ||
d538bbdf DL |
1329 | head = pipe_crc->head; |
1330 | tail = pipe_crc->tail; | |
b2c88f5b DL |
1331 | |
1332 | if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { | |
d538bbdf | 1333 | spin_unlock(&pipe_crc->lock); |
b2c88f5b DL |
1334 | DRM_ERROR("CRC buffer overflowing\n"); |
1335 | return; | |
1336 | } | |
1337 | ||
1338 | entry = &pipe_crc->entries[head]; | |
8bf1e9f1 | 1339 | |
8bc5e955 | 1340 | entry->frame = dev->driver->get_vblank_counter(dev, pipe); |
eba94eb9 DV |
1341 | entry->crc[0] = crc0; |
1342 | entry->crc[1] = crc1; | |
1343 | entry->crc[2] = crc2; | |
1344 | entry->crc[3] = crc3; | |
1345 | entry->crc[4] = crc4; | |
b2c88f5b DL |
1346 | |
1347 | head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
d538bbdf DL |
1348 | pipe_crc->head = head; |
1349 | ||
1350 | spin_unlock(&pipe_crc->lock); | |
07144428 DL |
1351 | |
1352 | wake_up_interruptible(&pipe_crc->wq); | |
8bf1e9f1 | 1353 | } |
277de95e DV |
1354 | #else |
1355 | static inline void | |
1356 | display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, | |
1357 | uint32_t crc0, uint32_t crc1, | |
1358 | uint32_t crc2, uint32_t crc3, | |
1359 | uint32_t crc4) {} | |
1360 | #endif | |
1361 | ||
eba94eb9 | 1362 | |
277de95e | 1363 | static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5a69b89f DV |
1364 | { |
1365 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1366 | ||
277de95e DV |
1367 | display_pipe_crc_irq_handler(dev, pipe, |
1368 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1369 | 0, 0, 0, 0); | |
5a69b89f DV |
1370 | } |
1371 | ||
277de95e | 1372 | static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
eba94eb9 DV |
1373 | { |
1374 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1375 | ||
277de95e DV |
1376 | display_pipe_crc_irq_handler(dev, pipe, |
1377 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1378 | I915_READ(PIPE_CRC_RES_2_IVB(pipe)), | |
1379 | I915_READ(PIPE_CRC_RES_3_IVB(pipe)), | |
1380 | I915_READ(PIPE_CRC_RES_4_IVB(pipe)), | |
1381 | I915_READ(PIPE_CRC_RES_5_IVB(pipe))); | |
eba94eb9 | 1382 | } |
5b3a856b | 1383 | |
277de95e | 1384 | static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5b3a856b DV |
1385 | { |
1386 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0b5c5ed0 DV |
1387 | uint32_t res1, res2; |
1388 | ||
1389 | if (INTEL_INFO(dev)->gen >= 3) | |
1390 | res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); | |
1391 | else | |
1392 | res1 = 0; | |
1393 | ||
1394 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
1395 | res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); | |
1396 | else | |
1397 | res2 = 0; | |
5b3a856b | 1398 | |
277de95e DV |
1399 | display_pipe_crc_irq_handler(dev, pipe, |
1400 | I915_READ(PIPE_CRC_RES_RED(pipe)), | |
1401 | I915_READ(PIPE_CRC_RES_GREEN(pipe)), | |
1402 | I915_READ(PIPE_CRC_RES_BLUE(pipe)), | |
1403 | res1, res2); | |
5b3a856b | 1404 | } |
8bf1e9f1 | 1405 | |
1403c0d4 PZ |
1406 | /* The RPS events need forcewake, so we add them to a work queue and mask their |
1407 | * IMR bits until the work is done. Other interrupts can be processed without | |
1408 | * the work queue. */ | |
1409 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) | |
baf02a1f | 1410 | { |
41a05a3a | 1411 | if (pm_iir & GEN6_PM_RPS_EVENTS) { |
59cdb63d | 1412 | spin_lock(&dev_priv->irq_lock); |
41a05a3a | 1413 | dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS; |
4d3b3d5f | 1414 | snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS); |
59cdb63d | 1415 | spin_unlock(&dev_priv->irq_lock); |
2adbee62 DV |
1416 | |
1417 | queue_work(dev_priv->wq, &dev_priv->rps.work); | |
baf02a1f | 1418 | } |
baf02a1f | 1419 | |
1403c0d4 PZ |
1420 | if (HAS_VEBOX(dev_priv->dev)) { |
1421 | if (pm_iir & PM_VEBOX_USER_INTERRUPT) | |
1422 | notify_ring(dev_priv->dev, &dev_priv->ring[VECS]); | |
12638c57 | 1423 | |
1403c0d4 PZ |
1424 | if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) { |
1425 | DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir); | |
1426 | i915_handle_error(dev_priv->dev, false); | |
1427 | } | |
12638c57 | 1428 | } |
baf02a1f BW |
1429 | } |
1430 | ||
ff1f525e | 1431 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
7e231dbe JB |
1432 | { |
1433 | struct drm_device *dev = (struct drm_device *) arg; | |
1434 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1435 | u32 iir, gt_iir, pm_iir; | |
1436 | irqreturn_t ret = IRQ_NONE; | |
1437 | unsigned long irqflags; | |
1438 | int pipe; | |
1439 | u32 pipe_stats[I915_MAX_PIPES]; | |
7e231dbe JB |
1440 | |
1441 | atomic_inc(&dev_priv->irq_received); | |
1442 | ||
7e231dbe JB |
1443 | while (true) { |
1444 | iir = I915_READ(VLV_IIR); | |
1445 | gt_iir = I915_READ(GTIIR); | |
1446 | pm_iir = I915_READ(GEN6_PMIIR); | |
1447 | ||
1448 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) | |
1449 | goto out; | |
1450 | ||
1451 | ret = IRQ_HANDLED; | |
1452 | ||
e7b4c6b1 | 1453 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
7e231dbe JB |
1454 | |
1455 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
1456 | for_each_pipe(pipe) { | |
1457 | int reg = PIPESTAT(pipe); | |
1458 | pipe_stats[pipe] = I915_READ(reg); | |
1459 | ||
1460 | /* | |
1461 | * Clear the PIPE*STAT regs before the IIR | |
1462 | */ | |
1463 | if (pipe_stats[pipe] & 0x8000ffff) { | |
1464 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | |
1465 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | |
1466 | pipe_name(pipe)); | |
1467 | I915_WRITE(reg, pipe_stats[pipe]); | |
1468 | } | |
1469 | } | |
1470 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
1471 | ||
31acc7f5 | 1472 | for_each_pipe(pipe) { |
7b5562d4 | 1473 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) |
31acc7f5 JB |
1474 | drm_handle_vblank(dev, pipe); |
1475 | ||
1476 | if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) { | |
1477 | intel_prepare_page_flip(dev, pipe); | |
1478 | intel_finish_page_flip(dev, pipe); | |
1479 | } | |
4356d586 DV |
1480 | |
1481 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 1482 | i9xx_pipe_crc_irq_handler(dev, pipe); |
31acc7f5 JB |
1483 | } |
1484 | ||
7e231dbe JB |
1485 | /* Consume port. Then clear IIR or we'll miss events */ |
1486 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { | |
1487 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
b543fb04 | 1488 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; |
7e231dbe JB |
1489 | |
1490 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", | |
1491 | hotplug_status); | |
91d131d2 DV |
1492 | |
1493 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); | |
1494 | ||
4aeebd74 DV |
1495 | if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) |
1496 | dp_aux_irq_handler(dev); | |
1497 | ||
7e231dbe JB |
1498 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
1499 | I915_READ(PORT_HOTPLUG_STAT); | |
1500 | } | |
1501 | ||
515ac2bb DV |
1502 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
1503 | gmbus_irq_handler(dev); | |
7e231dbe | 1504 | |
60611c13 | 1505 | if (pm_iir) |
d0ecd7e2 | 1506 | gen6_rps_irq_handler(dev_priv, pm_iir); |
7e231dbe JB |
1507 | |
1508 | I915_WRITE(GTIIR, gt_iir); | |
1509 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
1510 | I915_WRITE(VLV_IIR, iir); | |
1511 | } | |
1512 | ||
1513 | out: | |
1514 | return ret; | |
1515 | } | |
1516 | ||
23e81d69 | 1517 | static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) |
776ad806 JB |
1518 | { |
1519 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 1520 | int pipe; |
b543fb04 | 1521 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; |
776ad806 | 1522 | |
91d131d2 DV |
1523 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx); |
1524 | ||
cfc33bf7 VS |
1525 | if (pch_iir & SDE_AUDIO_POWER_MASK) { |
1526 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> | |
1527 | SDE_AUDIO_POWER_SHIFT); | |
776ad806 | 1528 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
cfc33bf7 VS |
1529 | port_name(port)); |
1530 | } | |
776ad806 | 1531 | |
ce99c256 DV |
1532 | if (pch_iir & SDE_AUX_MASK) |
1533 | dp_aux_irq_handler(dev); | |
1534 | ||
776ad806 | 1535 | if (pch_iir & SDE_GMBUS) |
515ac2bb | 1536 | gmbus_irq_handler(dev); |
776ad806 JB |
1537 | |
1538 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
1539 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
1540 | ||
1541 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
1542 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
1543 | ||
1544 | if (pch_iir & SDE_POISON) | |
1545 | DRM_ERROR("PCH poison interrupt\n"); | |
1546 | ||
9db4a9c7 JB |
1547 | if (pch_iir & SDE_FDI_MASK) |
1548 | for_each_pipe(pipe) | |
1549 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", | |
1550 | pipe_name(pipe), | |
1551 | I915_READ(FDI_RX_IIR(pipe))); | |
776ad806 JB |
1552 | |
1553 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
1554 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
1555 | ||
1556 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
1557 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
1558 | ||
776ad806 | 1559 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
8664281b PZ |
1560 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, |
1561 | false)) | |
1562 | DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n"); | |
1563 | ||
1564 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
1565 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, | |
1566 | false)) | |
1567 | DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n"); | |
1568 | } | |
1569 | ||
1570 | static void ivb_err_int_handler(struct drm_device *dev) | |
1571 | { | |
1572 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1573 | u32 err_int = I915_READ(GEN7_ERR_INT); | |
5a69b89f | 1574 | enum pipe pipe; |
8664281b | 1575 | |
de032bf4 PZ |
1576 | if (err_int & ERR_INT_POISON) |
1577 | DRM_ERROR("Poison interrupt\n"); | |
1578 | ||
5a69b89f DV |
1579 | for_each_pipe(pipe) { |
1580 | if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) { | |
1581 | if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, | |
1582 | false)) | |
1583 | DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n", | |
1584 | pipe_name(pipe)); | |
1585 | } | |
8bf1e9f1 | 1586 | |
5a69b89f DV |
1587 | if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { |
1588 | if (IS_IVYBRIDGE(dev)) | |
277de95e | 1589 | ivb_pipe_crc_irq_handler(dev, pipe); |
5a69b89f | 1590 | else |
277de95e | 1591 | hsw_pipe_crc_irq_handler(dev, pipe); |
5a69b89f DV |
1592 | } |
1593 | } | |
8bf1e9f1 | 1594 | |
8664281b PZ |
1595 | I915_WRITE(GEN7_ERR_INT, err_int); |
1596 | } | |
1597 | ||
1598 | static void cpt_serr_int_handler(struct drm_device *dev) | |
1599 | { | |
1600 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1601 | u32 serr_int = I915_READ(SERR_INT); | |
1602 | ||
de032bf4 PZ |
1603 | if (serr_int & SERR_INT_POISON) |
1604 | DRM_ERROR("PCH poison interrupt\n"); | |
1605 | ||
8664281b PZ |
1606 | if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) |
1607 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, | |
1608 | false)) | |
1609 | DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n"); | |
1610 | ||
1611 | if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) | |
1612 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, | |
1613 | false)) | |
1614 | DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n"); | |
1615 | ||
1616 | if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) | |
1617 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C, | |
1618 | false)) | |
1619 | DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n"); | |
1620 | ||
1621 | I915_WRITE(SERR_INT, serr_int); | |
776ad806 JB |
1622 | } |
1623 | ||
23e81d69 AJ |
1624 | static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) |
1625 | { | |
1626 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1627 | int pipe; | |
b543fb04 | 1628 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; |
23e81d69 | 1629 | |
91d131d2 DV |
1630 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt); |
1631 | ||
cfc33bf7 VS |
1632 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { |
1633 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> | |
1634 | SDE_AUDIO_POWER_SHIFT_CPT); | |
1635 | DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", | |
1636 | port_name(port)); | |
1637 | } | |
23e81d69 AJ |
1638 | |
1639 | if (pch_iir & SDE_AUX_MASK_CPT) | |
ce99c256 | 1640 | dp_aux_irq_handler(dev); |
23e81d69 AJ |
1641 | |
1642 | if (pch_iir & SDE_GMBUS_CPT) | |
515ac2bb | 1643 | gmbus_irq_handler(dev); |
23e81d69 AJ |
1644 | |
1645 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) | |
1646 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); | |
1647 | ||
1648 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) | |
1649 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); | |
1650 | ||
1651 | if (pch_iir & SDE_FDI_MASK_CPT) | |
1652 | for_each_pipe(pipe) | |
1653 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", | |
1654 | pipe_name(pipe), | |
1655 | I915_READ(FDI_RX_IIR(pipe))); | |
8664281b PZ |
1656 | |
1657 | if (pch_iir & SDE_ERROR_CPT) | |
1658 | cpt_serr_int_handler(dev); | |
23e81d69 AJ |
1659 | } |
1660 | ||
c008bc6e PZ |
1661 | static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) |
1662 | { | |
1663 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40da17c2 | 1664 | enum pipe pipe; |
c008bc6e PZ |
1665 | |
1666 | if (de_iir & DE_AUX_CHANNEL_A) | |
1667 | dp_aux_irq_handler(dev); | |
1668 | ||
1669 | if (de_iir & DE_GSE) | |
1670 | intel_opregion_asle_intr(dev); | |
1671 | ||
c008bc6e PZ |
1672 | if (de_iir & DE_POISON) |
1673 | DRM_ERROR("Poison interrupt\n"); | |
1674 | ||
40da17c2 DV |
1675 | for_each_pipe(pipe) { |
1676 | if (de_iir & DE_PIPE_VBLANK(pipe)) | |
1677 | drm_handle_vblank(dev, pipe); | |
5b3a856b | 1678 | |
40da17c2 DV |
1679 | if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) |
1680 | if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
1681 | DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n", | |
1682 | pipe_name(pipe)); | |
5b3a856b | 1683 | |
40da17c2 DV |
1684 | if (de_iir & DE_PIPE_CRC_DONE(pipe)) |
1685 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
c008bc6e | 1686 | |
40da17c2 DV |
1687 | /* plane/pipes map 1:1 on ilk+ */ |
1688 | if (de_iir & DE_PLANE_FLIP_DONE(pipe)) { | |
1689 | intel_prepare_page_flip(dev, pipe); | |
1690 | intel_finish_page_flip_plane(dev, pipe); | |
1691 | } | |
c008bc6e PZ |
1692 | } |
1693 | ||
1694 | /* check event from PCH */ | |
1695 | if (de_iir & DE_PCH_EVENT) { | |
1696 | u32 pch_iir = I915_READ(SDEIIR); | |
1697 | ||
1698 | if (HAS_PCH_CPT(dev)) | |
1699 | cpt_irq_handler(dev, pch_iir); | |
1700 | else | |
1701 | ibx_irq_handler(dev, pch_iir); | |
1702 | ||
1703 | /* should clear PCH hotplug event before clear CPU irq */ | |
1704 | I915_WRITE(SDEIIR, pch_iir); | |
1705 | } | |
1706 | ||
1707 | if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) | |
1708 | ironlake_rps_change_irq_handler(dev); | |
1709 | } | |
1710 | ||
9719fb98 PZ |
1711 | static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir) |
1712 | { | |
1713 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3b6c42e8 | 1714 | enum pipe i; |
9719fb98 PZ |
1715 | |
1716 | if (de_iir & DE_ERR_INT_IVB) | |
1717 | ivb_err_int_handler(dev); | |
1718 | ||
1719 | if (de_iir & DE_AUX_CHANNEL_A_IVB) | |
1720 | dp_aux_irq_handler(dev); | |
1721 | ||
1722 | if (de_iir & DE_GSE_IVB) | |
1723 | intel_opregion_asle_intr(dev); | |
1724 | ||
3b6c42e8 | 1725 | for_each_pipe(i) { |
40da17c2 | 1726 | if (de_iir & (DE_PIPE_VBLANK_IVB(i))) |
9719fb98 | 1727 | drm_handle_vblank(dev, i); |
40da17c2 DV |
1728 | |
1729 | /* plane/pipes map 1:1 on ilk+ */ | |
1730 | if (de_iir & DE_PLANE_FLIP_DONE_IVB(i)) { | |
9719fb98 PZ |
1731 | intel_prepare_page_flip(dev, i); |
1732 | intel_finish_page_flip_plane(dev, i); | |
1733 | } | |
1734 | } | |
1735 | ||
1736 | /* check event from PCH */ | |
1737 | if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) { | |
1738 | u32 pch_iir = I915_READ(SDEIIR); | |
1739 | ||
1740 | cpt_irq_handler(dev, pch_iir); | |
1741 | ||
1742 | /* clear PCH hotplug event before clear CPU irq */ | |
1743 | I915_WRITE(SDEIIR, pch_iir); | |
1744 | } | |
1745 | } | |
1746 | ||
f1af8fc1 | 1747 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
b1f14ad0 JB |
1748 | { |
1749 | struct drm_device *dev = (struct drm_device *) arg; | |
1750 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
f1af8fc1 | 1751 | u32 de_iir, gt_iir, de_ier, sde_ier = 0; |
0e43406b | 1752 | irqreturn_t ret = IRQ_NONE; |
b1f14ad0 JB |
1753 | |
1754 | atomic_inc(&dev_priv->irq_received); | |
1755 | ||
8664281b PZ |
1756 | /* We get interrupts on unclaimed registers, so check for this before we |
1757 | * do any I915_{READ,WRITE}. */ | |
907b28c5 | 1758 | intel_uncore_check_errors(dev); |
8664281b | 1759 | |
b1f14ad0 JB |
1760 | /* disable master interrupt before clearing iir */ |
1761 | de_ier = I915_READ(DEIER); | |
1762 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
23a78516 | 1763 | POSTING_READ(DEIER); |
b1f14ad0 | 1764 | |
44498aea PZ |
1765 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
1766 | * interrupts will will be stored on its back queue, and then we'll be | |
1767 | * able to process them after we restore SDEIER (as soon as we restore | |
1768 | * it, we'll get an interrupt if SDEIIR still has something to process | |
1769 | * due to its back queue). */ | |
ab5c608b BW |
1770 | if (!HAS_PCH_NOP(dev)) { |
1771 | sde_ier = I915_READ(SDEIER); | |
1772 | I915_WRITE(SDEIER, 0); | |
1773 | POSTING_READ(SDEIER); | |
1774 | } | |
44498aea | 1775 | |
b1f14ad0 | 1776 | gt_iir = I915_READ(GTIIR); |
0e43406b | 1777 | if (gt_iir) { |
d8fc8a47 | 1778 | if (INTEL_INFO(dev)->gen >= 6) |
f1af8fc1 | 1779 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
d8fc8a47 PZ |
1780 | else |
1781 | ilk_gt_irq_handler(dev, dev_priv, gt_iir); | |
0e43406b CW |
1782 | I915_WRITE(GTIIR, gt_iir); |
1783 | ret = IRQ_HANDLED; | |
b1f14ad0 JB |
1784 | } |
1785 | ||
0e43406b CW |
1786 | de_iir = I915_READ(DEIIR); |
1787 | if (de_iir) { | |
f1af8fc1 PZ |
1788 | if (INTEL_INFO(dev)->gen >= 7) |
1789 | ivb_display_irq_handler(dev, de_iir); | |
1790 | else | |
1791 | ilk_display_irq_handler(dev, de_iir); | |
0e43406b CW |
1792 | I915_WRITE(DEIIR, de_iir); |
1793 | ret = IRQ_HANDLED; | |
b1f14ad0 JB |
1794 | } |
1795 | ||
f1af8fc1 PZ |
1796 | if (INTEL_INFO(dev)->gen >= 6) { |
1797 | u32 pm_iir = I915_READ(GEN6_PMIIR); | |
1798 | if (pm_iir) { | |
1403c0d4 | 1799 | gen6_rps_irq_handler(dev_priv, pm_iir); |
f1af8fc1 PZ |
1800 | I915_WRITE(GEN6_PMIIR, pm_iir); |
1801 | ret = IRQ_HANDLED; | |
1802 | } | |
0e43406b | 1803 | } |
b1f14ad0 | 1804 | |
b1f14ad0 JB |
1805 | I915_WRITE(DEIER, de_ier); |
1806 | POSTING_READ(DEIER); | |
ab5c608b BW |
1807 | if (!HAS_PCH_NOP(dev)) { |
1808 | I915_WRITE(SDEIER, sde_ier); | |
1809 | POSTING_READ(SDEIER); | |
1810 | } | |
b1f14ad0 JB |
1811 | |
1812 | return ret; | |
1813 | } | |
1814 | ||
abd58f01 BW |
1815 | static irqreturn_t gen8_irq_handler(int irq, void *arg) |
1816 | { | |
1817 | struct drm_device *dev = arg; | |
1818 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1819 | u32 master_ctl; | |
1820 | irqreturn_t ret = IRQ_NONE; | |
1821 | uint32_t tmp = 0; | |
c42664cc | 1822 | enum pipe pipe; |
abd58f01 BW |
1823 | |
1824 | atomic_inc(&dev_priv->irq_received); | |
1825 | ||
1826 | master_ctl = I915_READ(GEN8_MASTER_IRQ); | |
1827 | master_ctl &= ~GEN8_MASTER_IRQ_CONTROL; | |
1828 | if (!master_ctl) | |
1829 | return IRQ_NONE; | |
1830 | ||
1831 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
1832 | POSTING_READ(GEN8_MASTER_IRQ); | |
1833 | ||
1834 | ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl); | |
1835 | ||
1836 | if (master_ctl & GEN8_DE_MISC_IRQ) { | |
1837 | tmp = I915_READ(GEN8_DE_MISC_IIR); | |
1838 | if (tmp & GEN8_DE_MISC_GSE) | |
1839 | intel_opregion_asle_intr(dev); | |
1840 | else if (tmp) | |
1841 | DRM_ERROR("Unexpected DE Misc interrupt\n"); | |
1842 | else | |
1843 | DRM_ERROR("The master control interrupt lied (DE MISC)!\n"); | |
1844 | ||
1845 | if (tmp) { | |
1846 | I915_WRITE(GEN8_DE_MISC_IIR, tmp); | |
1847 | ret = IRQ_HANDLED; | |
1848 | } | |
1849 | } | |
1850 | ||
6d766f02 DV |
1851 | if (master_ctl & GEN8_DE_PORT_IRQ) { |
1852 | tmp = I915_READ(GEN8_DE_PORT_IIR); | |
1853 | if (tmp & GEN8_AUX_CHANNEL_A) | |
1854 | dp_aux_irq_handler(dev); | |
1855 | else if (tmp) | |
1856 | DRM_ERROR("Unexpected DE Port interrupt\n"); | |
1857 | else | |
1858 | DRM_ERROR("The master control interrupt lied (DE PORT)!\n"); | |
1859 | ||
1860 | if (tmp) { | |
1861 | I915_WRITE(GEN8_DE_PORT_IIR, tmp); | |
1862 | ret = IRQ_HANDLED; | |
1863 | } | |
1864 | } | |
1865 | ||
c42664cc DV |
1866 | for_each_pipe(pipe) { |
1867 | uint32_t pipe_iir; | |
abd58f01 | 1868 | |
c42664cc DV |
1869 | if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) |
1870 | continue; | |
abd58f01 | 1871 | |
c42664cc DV |
1872 | pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); |
1873 | if (pipe_iir & GEN8_PIPE_VBLANK) | |
1874 | drm_handle_vblank(dev, pipe); | |
abd58f01 | 1875 | |
c42664cc DV |
1876 | if (pipe_iir & GEN8_PIPE_FLIP_DONE) { |
1877 | intel_prepare_page_flip(dev, pipe); | |
1878 | intel_finish_page_flip_plane(dev, pipe); | |
abd58f01 | 1879 | } |
c42664cc | 1880 | |
0fbe7870 DV |
1881 | if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE) |
1882 | hsw_pipe_crc_irq_handler(dev, pipe); | |
1883 | ||
38d83c96 DV |
1884 | if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) { |
1885 | if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, | |
1886 | false)) | |
1887 | DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n", | |
1888 | pipe_name(pipe)); | |
1889 | } | |
1890 | ||
30100f2b DV |
1891 | if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) { |
1892 | DRM_ERROR("Fault errors on pipe %c\n: 0x%08x", | |
1893 | pipe_name(pipe), | |
1894 | pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS); | |
1895 | } | |
c42664cc DV |
1896 | |
1897 | if (pipe_iir) { | |
1898 | ret = IRQ_HANDLED; | |
1899 | I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir); | |
1900 | } else | |
abd58f01 BW |
1901 | DRM_ERROR("The master control interrupt lied (DE PIPE)!\n"); |
1902 | } | |
1903 | ||
92d03a80 DV |
1904 | if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) { |
1905 | /* | |
1906 | * FIXME(BDW): Assume for now that the new interrupt handling | |
1907 | * scheme also closed the SDE interrupt handling race we've seen | |
1908 | * on older pch-split platforms. But this needs testing. | |
1909 | */ | |
1910 | u32 pch_iir = I915_READ(SDEIIR); | |
1911 | ||
1912 | cpt_irq_handler(dev, pch_iir); | |
1913 | ||
1914 | if (pch_iir) { | |
1915 | I915_WRITE(SDEIIR, pch_iir); | |
1916 | ret = IRQ_HANDLED; | |
1917 | } | |
1918 | } | |
1919 | ||
abd58f01 BW |
1920 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
1921 | POSTING_READ(GEN8_MASTER_IRQ); | |
1922 | ||
1923 | return ret; | |
1924 | } | |
1925 | ||
17e1df07 DV |
1926 | static void i915_error_wake_up(struct drm_i915_private *dev_priv, |
1927 | bool reset_completed) | |
1928 | { | |
1929 | struct intel_ring_buffer *ring; | |
1930 | int i; | |
1931 | ||
1932 | /* | |
1933 | * Notify all waiters for GPU completion events that reset state has | |
1934 | * been changed, and that they need to restart their wait after | |
1935 | * checking for potential errors (and bail out to drop locks if there is | |
1936 | * a gpu reset pending so that i915_error_work_func can acquire them). | |
1937 | */ | |
1938 | ||
1939 | /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */ | |
1940 | for_each_ring(ring, dev_priv, i) | |
1941 | wake_up_all(&ring->irq_queue); | |
1942 | ||
1943 | /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */ | |
1944 | wake_up_all(&dev_priv->pending_flip_queue); | |
1945 | ||
1946 | /* | |
1947 | * Signal tasks blocked in i915_gem_wait_for_error that the pending | |
1948 | * reset state is cleared. | |
1949 | */ | |
1950 | if (reset_completed) | |
1951 | wake_up_all(&dev_priv->gpu_error.reset_queue); | |
1952 | } | |
1953 | ||
8a905236 JB |
1954 | /** |
1955 | * i915_error_work_func - do process context error handling work | |
1956 | * @work: work struct | |
1957 | * | |
1958 | * Fire an error uevent so userspace can see that a hang or error | |
1959 | * was detected. | |
1960 | */ | |
1961 | static void i915_error_work_func(struct work_struct *work) | |
1962 | { | |
1f83fee0 DV |
1963 | struct i915_gpu_error *error = container_of(work, struct i915_gpu_error, |
1964 | work); | |
1965 | drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t, | |
1966 | gpu_error); | |
8a905236 | 1967 | struct drm_device *dev = dev_priv->dev; |
cce723ed BW |
1968 | char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; |
1969 | char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; | |
1970 | char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; | |
17e1df07 | 1971 | int ret; |
8a905236 | 1972 | |
5bdebb18 | 1973 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event); |
f316a42c | 1974 | |
7db0ba24 DV |
1975 | /* |
1976 | * Note that there's only one work item which does gpu resets, so we | |
1977 | * need not worry about concurrent gpu resets potentially incrementing | |
1978 | * error->reset_counter twice. We only need to take care of another | |
1979 | * racing irq/hangcheck declaring the gpu dead for a second time. A | |
1980 | * quick check for that is good enough: schedule_work ensures the | |
1981 | * correct ordering between hang detection and this work item, and since | |
1982 | * the reset in-progress bit is only ever set by code outside of this | |
1983 | * work we don't need to worry about any other races. | |
1984 | */ | |
1985 | if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) { | |
f803aa55 | 1986 | DRM_DEBUG_DRIVER("resetting chip\n"); |
5bdebb18 | 1987 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, |
7db0ba24 | 1988 | reset_event); |
1f83fee0 | 1989 | |
17e1df07 DV |
1990 | /* |
1991 | * All state reset _must_ be completed before we update the | |
1992 | * reset counter, for otherwise waiters might miss the reset | |
1993 | * pending state and not properly drop locks, resulting in | |
1994 | * deadlocks with the reset work. | |
1995 | */ | |
f69061be DV |
1996 | ret = i915_reset(dev); |
1997 | ||
17e1df07 DV |
1998 | intel_display_handle_reset(dev); |
1999 | ||
f69061be DV |
2000 | if (ret == 0) { |
2001 | /* | |
2002 | * After all the gem state is reset, increment the reset | |
2003 | * counter and wake up everyone waiting for the reset to | |
2004 | * complete. | |
2005 | * | |
2006 | * Since unlock operations are a one-sided barrier only, | |
2007 | * we need to insert a barrier here to order any seqno | |
2008 | * updates before | |
2009 | * the counter increment. | |
2010 | */ | |
2011 | smp_mb__before_atomic_inc(); | |
2012 | atomic_inc(&dev_priv->gpu_error.reset_counter); | |
2013 | ||
5bdebb18 | 2014 | kobject_uevent_env(&dev->primary->kdev->kobj, |
f69061be | 2015 | KOBJ_CHANGE, reset_done_event); |
1f83fee0 | 2016 | } else { |
2ac0f450 | 2017 | atomic_set_mask(I915_WEDGED, &error->reset_counter); |
f316a42c | 2018 | } |
1f83fee0 | 2019 | |
17e1df07 DV |
2020 | /* |
2021 | * Note: The wake_up also serves as a memory barrier so that | |
2022 | * waiters see the update value of the reset counter atomic_t. | |
2023 | */ | |
2024 | i915_error_wake_up(dev_priv, true); | |
f316a42c | 2025 | } |
8a905236 JB |
2026 | } |
2027 | ||
35aed2e6 | 2028 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
2029 | { |
2030 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bd9854f9 | 2031 | uint32_t instdone[I915_NUM_INSTDONE_REG]; |
8a905236 | 2032 | u32 eir = I915_READ(EIR); |
050ee91f | 2033 | int pipe, i; |
8a905236 | 2034 | |
35aed2e6 CW |
2035 | if (!eir) |
2036 | return; | |
8a905236 | 2037 | |
a70491cc | 2038 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
8a905236 | 2039 | |
bd9854f9 BW |
2040 | i915_get_extra_instdone(dev, instdone); |
2041 | ||
8a905236 JB |
2042 | if (IS_G4X(dev)) { |
2043 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
2044 | u32 ipeir = I915_READ(IPEIR_I965); | |
2045 | ||
a70491cc JP |
2046 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2047 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
050ee91f BW |
2048 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2049 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a70491cc | 2050 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2051 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2052 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2053 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2054 | } |
2055 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
2056 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2057 | pr_err("page table error\n"); |
2058 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2059 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2060 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2061 | } |
2062 | } | |
2063 | ||
a6c45cf0 | 2064 | if (!IS_GEN2(dev)) { |
8a905236 JB |
2065 | if (eir & I915_ERROR_PAGE_TABLE) { |
2066 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2067 | pr_err("page table error\n"); |
2068 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2069 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2070 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2071 | } |
2072 | } | |
2073 | ||
2074 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
a70491cc | 2075 | pr_err("memory refresh error:\n"); |
9db4a9c7 | 2076 | for_each_pipe(pipe) |
a70491cc | 2077 | pr_err("pipe %c stat: 0x%08x\n", |
9db4a9c7 | 2078 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
8a905236 JB |
2079 | /* pipestat has already been acked */ |
2080 | } | |
2081 | if (eir & I915_ERROR_INSTRUCTION) { | |
a70491cc JP |
2082 | pr_err("instruction error\n"); |
2083 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); | |
050ee91f BW |
2084 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2085 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a6c45cf0 | 2086 | if (INTEL_INFO(dev)->gen < 4) { |
8a905236 JB |
2087 | u32 ipeir = I915_READ(IPEIR); |
2088 | ||
a70491cc JP |
2089 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
2090 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); | |
a70491cc | 2091 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); |
8a905236 | 2092 | I915_WRITE(IPEIR, ipeir); |
3143a2bf | 2093 | POSTING_READ(IPEIR); |
8a905236 JB |
2094 | } else { |
2095 | u32 ipeir = I915_READ(IPEIR_I965); | |
2096 | ||
a70491cc JP |
2097 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2098 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
a70491cc | 2099 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2100 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2101 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2102 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2103 | } |
2104 | } | |
2105 | ||
2106 | I915_WRITE(EIR, eir); | |
3143a2bf | 2107 | POSTING_READ(EIR); |
8a905236 JB |
2108 | eir = I915_READ(EIR); |
2109 | if (eir) { | |
2110 | /* | |
2111 | * some errors might have become stuck, | |
2112 | * mask them. | |
2113 | */ | |
2114 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
2115 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
2116 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2117 | } | |
35aed2e6 CW |
2118 | } |
2119 | ||
2120 | /** | |
2121 | * i915_handle_error - handle an error interrupt | |
2122 | * @dev: drm device | |
2123 | * | |
2124 | * Do some basic checking of regsiter state at error interrupt time and | |
2125 | * dump it to the syslog. Also call i915_capture_error_state() to make | |
2126 | * sure we get a record and make it available in debugfs. Fire a uevent | |
2127 | * so userspace knows something bad happened (should trigger collection | |
2128 | * of a ring dump etc.). | |
2129 | */ | |
527f9e90 | 2130 | void i915_handle_error(struct drm_device *dev, bool wedged) |
35aed2e6 CW |
2131 | { |
2132 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2133 | ||
2134 | i915_capture_error_state(dev); | |
2135 | i915_report_and_clear_eir(dev); | |
8a905236 | 2136 | |
ba1234d1 | 2137 | if (wedged) { |
f69061be DV |
2138 | atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG, |
2139 | &dev_priv->gpu_error.reset_counter); | |
ba1234d1 | 2140 | |
11ed50ec | 2141 | /* |
17e1df07 DV |
2142 | * Wakeup waiting processes so that the reset work function |
2143 | * i915_error_work_func doesn't deadlock trying to grab various | |
2144 | * locks. By bumping the reset counter first, the woken | |
2145 | * processes will see a reset in progress and back off, | |
2146 | * releasing their locks and then wait for the reset completion. | |
2147 | * We must do this for _all_ gpu waiters that might hold locks | |
2148 | * that the reset work needs to acquire. | |
2149 | * | |
2150 | * Note: The wake_up serves as the required memory barrier to | |
2151 | * ensure that the waiters see the updated value of the reset | |
2152 | * counter atomic_t. | |
11ed50ec | 2153 | */ |
17e1df07 | 2154 | i915_error_wake_up(dev_priv, false); |
11ed50ec BG |
2155 | } |
2156 | ||
122f46ba DV |
2157 | /* |
2158 | * Our reset work can grab modeset locks (since it needs to reset the | |
2159 | * state of outstanding pagelips). Hence it must not be run on our own | |
2160 | * dev-priv->wq work queue for otherwise the flush_work in the pageflip | |
2161 | * code will deadlock. | |
2162 | */ | |
2163 | schedule_work(&dev_priv->gpu_error.work); | |
8a905236 JB |
2164 | } |
2165 | ||
21ad8330 | 2166 | static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe) |
4e5359cd SF |
2167 | { |
2168 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2169 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
2170 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 2171 | struct drm_i915_gem_object *obj; |
4e5359cd SF |
2172 | struct intel_unpin_work *work; |
2173 | unsigned long flags; | |
2174 | bool stall_detected; | |
2175 | ||
2176 | /* Ignore early vblank irqs */ | |
2177 | if (intel_crtc == NULL) | |
2178 | return; | |
2179 | ||
2180 | spin_lock_irqsave(&dev->event_lock, flags); | |
2181 | work = intel_crtc->unpin_work; | |
2182 | ||
e7d841ca CW |
2183 | if (work == NULL || |
2184 | atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE || | |
2185 | !work->enable_stall_check) { | |
4e5359cd SF |
2186 | /* Either the pending flip IRQ arrived, or we're too early. Don't check */ |
2187 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2188 | return; | |
2189 | } | |
2190 | ||
2191 | /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ | |
05394f39 | 2192 | obj = work->pending_flip_obj; |
a6c45cf0 | 2193 | if (INTEL_INFO(dev)->gen >= 4) { |
9db4a9c7 | 2194 | int dspsurf = DSPSURF(intel_crtc->plane); |
446f2545 | 2195 | stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) == |
f343c5f6 | 2196 | i915_gem_obj_ggtt_offset(obj); |
4e5359cd | 2197 | } else { |
9db4a9c7 | 2198 | int dspaddr = DSPADDR(intel_crtc->plane); |
f343c5f6 | 2199 | stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) + |
01f2c773 | 2200 | crtc->y * crtc->fb->pitches[0] + |
4e5359cd SF |
2201 | crtc->x * crtc->fb->bits_per_pixel/8); |
2202 | } | |
2203 | ||
2204 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2205 | ||
2206 | if (stall_detected) { | |
2207 | DRM_DEBUG_DRIVER("Pageflip stall detected\n"); | |
2208 | intel_prepare_page_flip(dev, intel_crtc->plane); | |
2209 | } | |
2210 | } | |
2211 | ||
42f52ef8 KP |
2212 | /* Called from drm generic code, passed 'crtc' which |
2213 | * we use as a pipe index | |
2214 | */ | |
f71d4af4 | 2215 | static int i915_enable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 JB |
2216 | { |
2217 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 2218 | unsigned long irqflags; |
71e0ffa5 | 2219 | |
5eddb70b | 2220 | if (!i915_pipe_enabled(dev, pipe)) |
71e0ffa5 | 2221 | return -EINVAL; |
0a3e67a4 | 2222 | |
1ec14ad3 | 2223 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2224 | if (INTEL_INFO(dev)->gen >= 4) |
7c463586 KP |
2225 | i915_enable_pipestat(dev_priv, pipe, |
2226 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 2227 | else |
7c463586 KP |
2228 | i915_enable_pipestat(dev_priv, pipe, |
2229 | PIPE_VBLANK_INTERRUPT_ENABLE); | |
8692d00e CW |
2230 | |
2231 | /* maintain vblank delivery even in deep C-states */ | |
2232 | if (dev_priv->info->gen == 3) | |
6b26c86d | 2233 | I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS)); |
1ec14ad3 | 2234 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
8692d00e | 2235 | |
0a3e67a4 JB |
2236 | return 0; |
2237 | } | |
2238 | ||
f71d4af4 | 2239 | static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
f796cf8f JB |
2240 | { |
2241 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2242 | unsigned long irqflags; | |
b518421f | 2243 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2244 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2245 | |
2246 | if (!i915_pipe_enabled(dev, pipe)) | |
2247 | return -EINVAL; | |
2248 | ||
2249 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 2250 | ironlake_enable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2251 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2252 | ||
2253 | return 0; | |
2254 | } | |
2255 | ||
7e231dbe JB |
2256 | static int valleyview_enable_vblank(struct drm_device *dev, int pipe) |
2257 | { | |
2258 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2259 | unsigned long irqflags; | |
31acc7f5 | 2260 | u32 imr; |
7e231dbe JB |
2261 | |
2262 | if (!i915_pipe_enabled(dev, pipe)) | |
2263 | return -EINVAL; | |
2264 | ||
2265 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
7e231dbe | 2266 | imr = I915_READ(VLV_IMR); |
3b6c42e8 | 2267 | if (pipe == PIPE_A) |
7e231dbe | 2268 | imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; |
31acc7f5 | 2269 | else |
7e231dbe | 2270 | imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
7e231dbe | 2271 | I915_WRITE(VLV_IMR, imr); |
31acc7f5 JB |
2272 | i915_enable_pipestat(dev_priv, pipe, |
2273 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
7e231dbe JB |
2274 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2275 | ||
2276 | return 0; | |
2277 | } | |
2278 | ||
abd58f01 BW |
2279 | static int gen8_enable_vblank(struct drm_device *dev, int pipe) |
2280 | { | |
2281 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2282 | unsigned long irqflags; | |
abd58f01 BW |
2283 | |
2284 | if (!i915_pipe_enabled(dev, pipe)) | |
2285 | return -EINVAL; | |
2286 | ||
2287 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
7167d7c6 DV |
2288 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK; |
2289 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2290 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2291 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2292 | return 0; | |
2293 | } | |
2294 | ||
42f52ef8 KP |
2295 | /* Called from drm generic code, passed 'crtc' which |
2296 | * we use as a pipe index | |
2297 | */ | |
f71d4af4 | 2298 | static void i915_disable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 JB |
2299 | { |
2300 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 2301 | unsigned long irqflags; |
0a3e67a4 | 2302 | |
1ec14ad3 | 2303 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
8692d00e | 2304 | if (dev_priv->info->gen == 3) |
6b26c86d | 2305 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS)); |
8692d00e | 2306 | |
f796cf8f JB |
2307 | i915_disable_pipestat(dev_priv, pipe, |
2308 | PIPE_VBLANK_INTERRUPT_ENABLE | | |
2309 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
2310 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
2311 | } | |
2312 | ||
f71d4af4 | 2313 | static void ironlake_disable_vblank(struct drm_device *dev, int pipe) |
f796cf8f JB |
2314 | { |
2315 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2316 | unsigned long irqflags; | |
b518421f | 2317 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2318 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2319 | |
2320 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 2321 | ironlake_disable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2322 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2323 | } | |
2324 | ||
7e231dbe JB |
2325 | static void valleyview_disable_vblank(struct drm_device *dev, int pipe) |
2326 | { | |
2327 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2328 | unsigned long irqflags; | |
31acc7f5 | 2329 | u32 imr; |
7e231dbe JB |
2330 | |
2331 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 JB |
2332 | i915_disable_pipestat(dev_priv, pipe, |
2333 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
7e231dbe | 2334 | imr = I915_READ(VLV_IMR); |
3b6c42e8 | 2335 | if (pipe == PIPE_A) |
7e231dbe | 2336 | imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; |
31acc7f5 | 2337 | else |
7e231dbe | 2338 | imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
7e231dbe | 2339 | I915_WRITE(VLV_IMR, imr); |
7e231dbe JB |
2340 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2341 | } | |
2342 | ||
abd58f01 BW |
2343 | static void gen8_disable_vblank(struct drm_device *dev, int pipe) |
2344 | { | |
2345 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2346 | unsigned long irqflags; | |
abd58f01 BW |
2347 | |
2348 | if (!i915_pipe_enabled(dev, pipe)) | |
2349 | return; | |
2350 | ||
2351 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
7167d7c6 DV |
2352 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK; |
2353 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2354 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2355 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2356 | } | |
2357 | ||
893eead0 CW |
2358 | static u32 |
2359 | ring_last_seqno(struct intel_ring_buffer *ring) | |
852835f3 | 2360 | { |
893eead0 CW |
2361 | return list_entry(ring->request_list.prev, |
2362 | struct drm_i915_gem_request, list)->seqno; | |
2363 | } | |
2364 | ||
9107e9d2 CW |
2365 | static bool |
2366 | ring_idle(struct intel_ring_buffer *ring, u32 seqno) | |
2367 | { | |
2368 | return (list_empty(&ring->request_list) || | |
2369 | i915_seqno_passed(seqno, ring_last_seqno(ring))); | |
f65d9421 BG |
2370 | } |
2371 | ||
6274f212 CW |
2372 | static struct intel_ring_buffer * |
2373 | semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno) | |
a24a11e6 CW |
2374 | { |
2375 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
6274f212 | 2376 | u32 cmd, ipehr, acthd, acthd_min; |
a24a11e6 CW |
2377 | |
2378 | ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); | |
2379 | if ((ipehr & ~(0x3 << 16)) != | |
2380 | (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER)) | |
6274f212 | 2381 | return NULL; |
a24a11e6 CW |
2382 | |
2383 | /* ACTHD is likely pointing to the dword after the actual command, | |
2384 | * so scan backwards until we find the MBOX. | |
2385 | */ | |
6274f212 | 2386 | acthd = intel_ring_get_active_head(ring) & HEAD_ADDR; |
a24a11e6 CW |
2387 | acthd_min = max((int)acthd - 3 * 4, 0); |
2388 | do { | |
2389 | cmd = ioread32(ring->virtual_start + acthd); | |
2390 | if (cmd == ipehr) | |
2391 | break; | |
2392 | ||
2393 | acthd -= 4; | |
2394 | if (acthd < acthd_min) | |
6274f212 | 2395 | return NULL; |
a24a11e6 CW |
2396 | } while (1); |
2397 | ||
6274f212 CW |
2398 | *seqno = ioread32(ring->virtual_start+acthd+4)+1; |
2399 | return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3]; | |
a24a11e6 CW |
2400 | } |
2401 | ||
6274f212 CW |
2402 | static int semaphore_passed(struct intel_ring_buffer *ring) |
2403 | { | |
2404 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
2405 | struct intel_ring_buffer *signaller; | |
2406 | u32 seqno, ctl; | |
2407 | ||
2408 | ring->hangcheck.deadlock = true; | |
2409 | ||
2410 | signaller = semaphore_waits_for(ring, &seqno); | |
2411 | if (signaller == NULL || signaller->hangcheck.deadlock) | |
2412 | return -1; | |
2413 | ||
2414 | /* cursory check for an unkickable deadlock */ | |
2415 | ctl = I915_READ_CTL(signaller); | |
2416 | if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0) | |
2417 | return -1; | |
2418 | ||
2419 | return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno); | |
2420 | } | |
2421 | ||
2422 | static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) | |
2423 | { | |
2424 | struct intel_ring_buffer *ring; | |
2425 | int i; | |
2426 | ||
2427 | for_each_ring(ring, dev_priv, i) | |
2428 | ring->hangcheck.deadlock = false; | |
2429 | } | |
2430 | ||
ad8beaea MK |
2431 | static enum intel_ring_hangcheck_action |
2432 | ring_stuck(struct intel_ring_buffer *ring, u32 acthd) | |
1ec14ad3 CW |
2433 | { |
2434 | struct drm_device *dev = ring->dev; | |
2435 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9107e9d2 CW |
2436 | u32 tmp; |
2437 | ||
6274f212 | 2438 | if (ring->hangcheck.acthd != acthd) |
f2f4d82f | 2439 | return HANGCHECK_ACTIVE; |
6274f212 | 2440 | |
9107e9d2 | 2441 | if (IS_GEN2(dev)) |
f2f4d82f | 2442 | return HANGCHECK_HUNG; |
9107e9d2 CW |
2443 | |
2444 | /* Is the chip hanging on a WAIT_FOR_EVENT? | |
2445 | * If so we can simply poke the RB_WAIT bit | |
2446 | * and break the hang. This should work on | |
2447 | * all but the second generation chipsets. | |
2448 | */ | |
2449 | tmp = I915_READ_CTL(ring); | |
1ec14ad3 CW |
2450 | if (tmp & RING_WAIT) { |
2451 | DRM_ERROR("Kicking stuck wait on %s\n", | |
2452 | ring->name); | |
09e14bf3 | 2453 | i915_handle_error(dev, false); |
1ec14ad3 | 2454 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2455 | return HANGCHECK_KICK; |
6274f212 CW |
2456 | } |
2457 | ||
2458 | if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { | |
2459 | switch (semaphore_passed(ring)) { | |
2460 | default: | |
f2f4d82f | 2461 | return HANGCHECK_HUNG; |
6274f212 CW |
2462 | case 1: |
2463 | DRM_ERROR("Kicking stuck semaphore on %s\n", | |
2464 | ring->name); | |
09e14bf3 | 2465 | i915_handle_error(dev, false); |
6274f212 | 2466 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2467 | return HANGCHECK_KICK; |
6274f212 | 2468 | case 0: |
f2f4d82f | 2469 | return HANGCHECK_WAIT; |
6274f212 | 2470 | } |
9107e9d2 | 2471 | } |
ed5cbb03 | 2472 | |
f2f4d82f | 2473 | return HANGCHECK_HUNG; |
ed5cbb03 MK |
2474 | } |
2475 | ||
f65d9421 BG |
2476 | /** |
2477 | * This is called when the chip hasn't reported back with completed | |
05407ff8 MK |
2478 | * batchbuffers in a long time. We keep track per ring seqno progress and |
2479 | * if there are no progress, hangcheck score for that ring is increased. | |
2480 | * Further, acthd is inspected to see if the ring is stuck. On stuck case | |
2481 | * we kick the ring. If we see no progress on three subsequent calls | |
2482 | * we assume chip is wedged and try to fix it by resetting the chip. | |
f65d9421 | 2483 | */ |
a658b5d2 | 2484 | static void i915_hangcheck_elapsed(unsigned long data) |
f65d9421 BG |
2485 | { |
2486 | struct drm_device *dev = (struct drm_device *)data; | |
2487 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2488 | struct intel_ring_buffer *ring; |
b4519513 | 2489 | int i; |
05407ff8 | 2490 | int busy_count = 0, rings_hung = 0; |
9107e9d2 CW |
2491 | bool stuck[I915_NUM_RINGS] = { 0 }; |
2492 | #define BUSY 1 | |
2493 | #define KICK 5 | |
2494 | #define HUNG 20 | |
2495 | #define FIRE 30 | |
893eead0 | 2496 | |
3e0dc6b0 BW |
2497 | if (!i915_enable_hangcheck) |
2498 | return; | |
2499 | ||
b4519513 | 2500 | for_each_ring(ring, dev_priv, i) { |
05407ff8 | 2501 | u32 seqno, acthd; |
9107e9d2 | 2502 | bool busy = true; |
05407ff8 | 2503 | |
6274f212 CW |
2504 | semaphore_clear_deadlocks(dev_priv); |
2505 | ||
05407ff8 MK |
2506 | seqno = ring->get_seqno(ring, false); |
2507 | acthd = intel_ring_get_active_head(ring); | |
b4519513 | 2508 | |
9107e9d2 CW |
2509 | if (ring->hangcheck.seqno == seqno) { |
2510 | if (ring_idle(ring, seqno)) { | |
da661464 MK |
2511 | ring->hangcheck.action = HANGCHECK_IDLE; |
2512 | ||
9107e9d2 CW |
2513 | if (waitqueue_active(&ring->irq_queue)) { |
2514 | /* Issue a wake-up to catch stuck h/w. */ | |
094f9a54 | 2515 | if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) { |
f4adcd24 DV |
2516 | if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring))) |
2517 | DRM_ERROR("Hangcheck timer elapsed... %s idle\n", | |
2518 | ring->name); | |
2519 | else | |
2520 | DRM_INFO("Fake missed irq on %s\n", | |
2521 | ring->name); | |
094f9a54 CW |
2522 | wake_up_all(&ring->irq_queue); |
2523 | } | |
2524 | /* Safeguard against driver failure */ | |
2525 | ring->hangcheck.score += BUSY; | |
9107e9d2 CW |
2526 | } else |
2527 | busy = false; | |
05407ff8 | 2528 | } else { |
6274f212 CW |
2529 | /* We always increment the hangcheck score |
2530 | * if the ring is busy and still processing | |
2531 | * the same request, so that no single request | |
2532 | * can run indefinitely (such as a chain of | |
2533 | * batches). The only time we do not increment | |
2534 | * the hangcheck score on this ring, if this | |
2535 | * ring is in a legitimate wait for another | |
2536 | * ring. In that case the waiting ring is a | |
2537 | * victim and we want to be sure we catch the | |
2538 | * right culprit. Then every time we do kick | |
2539 | * the ring, add a small increment to the | |
2540 | * score so that we can catch a batch that is | |
2541 | * being repeatedly kicked and so responsible | |
2542 | * for stalling the machine. | |
2543 | */ | |
ad8beaea MK |
2544 | ring->hangcheck.action = ring_stuck(ring, |
2545 | acthd); | |
2546 | ||
2547 | switch (ring->hangcheck.action) { | |
da661464 | 2548 | case HANGCHECK_IDLE: |
f2f4d82f | 2549 | case HANGCHECK_WAIT: |
6274f212 | 2550 | break; |
f2f4d82f | 2551 | case HANGCHECK_ACTIVE: |
ea04cb31 | 2552 | ring->hangcheck.score += BUSY; |
6274f212 | 2553 | break; |
f2f4d82f | 2554 | case HANGCHECK_KICK: |
ea04cb31 | 2555 | ring->hangcheck.score += KICK; |
6274f212 | 2556 | break; |
f2f4d82f | 2557 | case HANGCHECK_HUNG: |
ea04cb31 | 2558 | ring->hangcheck.score += HUNG; |
6274f212 CW |
2559 | stuck[i] = true; |
2560 | break; | |
2561 | } | |
05407ff8 | 2562 | } |
9107e9d2 | 2563 | } else { |
da661464 MK |
2564 | ring->hangcheck.action = HANGCHECK_ACTIVE; |
2565 | ||
9107e9d2 CW |
2566 | /* Gradually reduce the count so that we catch DoS |
2567 | * attempts across multiple batches. | |
2568 | */ | |
2569 | if (ring->hangcheck.score > 0) | |
2570 | ring->hangcheck.score--; | |
d1e61e7f CW |
2571 | } |
2572 | ||
05407ff8 MK |
2573 | ring->hangcheck.seqno = seqno; |
2574 | ring->hangcheck.acthd = acthd; | |
9107e9d2 | 2575 | busy_count += busy; |
893eead0 | 2576 | } |
b9201c14 | 2577 | |
92cab734 | 2578 | for_each_ring(ring, dev_priv, i) { |
9107e9d2 | 2579 | if (ring->hangcheck.score > FIRE) { |
b8d88d1d DV |
2580 | DRM_INFO("%s on %s\n", |
2581 | stuck[i] ? "stuck" : "no progress", | |
2582 | ring->name); | |
a43adf07 | 2583 | rings_hung++; |
92cab734 MK |
2584 | } |
2585 | } | |
2586 | ||
05407ff8 MK |
2587 | if (rings_hung) |
2588 | return i915_handle_error(dev, true); | |
f65d9421 | 2589 | |
05407ff8 MK |
2590 | if (busy_count) |
2591 | /* Reset timer case chip hangs without another request | |
2592 | * being added */ | |
10cd45b6 MK |
2593 | i915_queue_hangcheck(dev); |
2594 | } | |
2595 | ||
2596 | void i915_queue_hangcheck(struct drm_device *dev) | |
2597 | { | |
2598 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2599 | if (!i915_enable_hangcheck) | |
2600 | return; | |
2601 | ||
2602 | mod_timer(&dev_priv->gpu_error.hangcheck_timer, | |
2603 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); | |
f65d9421 BG |
2604 | } |
2605 | ||
91738a95 PZ |
2606 | static void ibx_irq_preinstall(struct drm_device *dev) |
2607 | { | |
2608 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2609 | ||
2610 | if (HAS_PCH_NOP(dev)) | |
2611 | return; | |
2612 | ||
2613 | /* south display irq */ | |
2614 | I915_WRITE(SDEIMR, 0xffffffff); | |
2615 | /* | |
2616 | * SDEIER is also touched by the interrupt handler to work around missed | |
2617 | * PCH interrupts. Hence we can't update it after the interrupt handler | |
2618 | * is enabled - instead we unconditionally enable all PCH interrupt | |
2619 | * sources here, but then only unmask them as needed with SDEIMR. | |
2620 | */ | |
2621 | I915_WRITE(SDEIER, 0xffffffff); | |
2622 | POSTING_READ(SDEIER); | |
2623 | } | |
2624 | ||
d18ea1b5 DV |
2625 | static void gen5_gt_irq_preinstall(struct drm_device *dev) |
2626 | { | |
2627 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2628 | ||
2629 | /* and GT */ | |
2630 | I915_WRITE(GTIMR, 0xffffffff); | |
2631 | I915_WRITE(GTIER, 0x0); | |
2632 | POSTING_READ(GTIER); | |
2633 | ||
2634 | if (INTEL_INFO(dev)->gen >= 6) { | |
2635 | /* and PM */ | |
2636 | I915_WRITE(GEN6_PMIMR, 0xffffffff); | |
2637 | I915_WRITE(GEN6_PMIER, 0x0); | |
2638 | POSTING_READ(GEN6_PMIER); | |
2639 | } | |
2640 | } | |
2641 | ||
1da177e4 LT |
2642 | /* drm_dma.h hooks |
2643 | */ | |
f71d4af4 | 2644 | static void ironlake_irq_preinstall(struct drm_device *dev) |
036a4a7d ZW |
2645 | { |
2646 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2647 | ||
4697995b JB |
2648 | atomic_set(&dev_priv->irq_received, 0); |
2649 | ||
036a4a7d | 2650 | I915_WRITE(HWSTAM, 0xeffe); |
bdfcdb63 | 2651 | |
036a4a7d ZW |
2652 | I915_WRITE(DEIMR, 0xffffffff); |
2653 | I915_WRITE(DEIER, 0x0); | |
3143a2bf | 2654 | POSTING_READ(DEIER); |
036a4a7d | 2655 | |
d18ea1b5 | 2656 | gen5_gt_irq_preinstall(dev); |
c650156a | 2657 | |
91738a95 | 2658 | ibx_irq_preinstall(dev); |
7d99163d BW |
2659 | } |
2660 | ||
7e231dbe JB |
2661 | static void valleyview_irq_preinstall(struct drm_device *dev) |
2662 | { | |
2663 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2664 | int pipe; | |
2665 | ||
2666 | atomic_set(&dev_priv->irq_received, 0); | |
2667 | ||
7e231dbe JB |
2668 | /* VLV magic */ |
2669 | I915_WRITE(VLV_IMR, 0); | |
2670 | I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); | |
2671 | I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); | |
2672 | I915_WRITE(RING_IMR(BLT_RING_BASE), 0); | |
2673 | ||
7e231dbe JB |
2674 | /* and GT */ |
2675 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
2676 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
d18ea1b5 DV |
2677 | |
2678 | gen5_gt_irq_preinstall(dev); | |
7e231dbe JB |
2679 | |
2680 | I915_WRITE(DPINVGTT, 0xff); | |
2681 | ||
2682 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
2683 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
2684 | for_each_pipe(pipe) | |
2685 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
2686 | I915_WRITE(VLV_IIR, 0xffffffff); | |
2687 | I915_WRITE(VLV_IMR, 0xffffffff); | |
2688 | I915_WRITE(VLV_IER, 0x0); | |
2689 | POSTING_READ(VLV_IER); | |
2690 | } | |
2691 | ||
abd58f01 BW |
2692 | static void gen8_irq_preinstall(struct drm_device *dev) |
2693 | { | |
2694 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2695 | int pipe; | |
2696 | ||
2697 | atomic_set(&dev_priv->irq_received, 0); | |
2698 | ||
2699 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
2700 | POSTING_READ(GEN8_MASTER_IRQ); | |
2701 | ||
2702 | /* IIR can theoretically queue up two events. Be paranoid */ | |
2703 | #define GEN8_IRQ_INIT_NDX(type, which) do { \ | |
2704 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ | |
2705 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
2706 | I915_WRITE(GEN8_##type##_IER(which), 0); \ | |
2707 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
2708 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
2709 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
2710 | } while (0) | |
2711 | ||
2712 | #define GEN8_IRQ_INIT(type) do { \ | |
2713 | I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \ | |
2714 | POSTING_READ(GEN8_##type##_IMR); \ | |
2715 | I915_WRITE(GEN8_##type##_IER, 0); \ | |
2716 | I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ | |
2717 | POSTING_READ(GEN8_##type##_IIR); \ | |
2718 | I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ | |
2719 | } while (0) | |
2720 | ||
2721 | GEN8_IRQ_INIT_NDX(GT, 0); | |
2722 | GEN8_IRQ_INIT_NDX(GT, 1); | |
2723 | GEN8_IRQ_INIT_NDX(GT, 2); | |
2724 | GEN8_IRQ_INIT_NDX(GT, 3); | |
2725 | ||
2726 | for_each_pipe(pipe) { | |
2727 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe); | |
2728 | } | |
2729 | ||
2730 | GEN8_IRQ_INIT(DE_PORT); | |
2731 | GEN8_IRQ_INIT(DE_MISC); | |
2732 | GEN8_IRQ_INIT(PCU); | |
2733 | #undef GEN8_IRQ_INIT | |
2734 | #undef GEN8_IRQ_INIT_NDX | |
2735 | ||
2736 | POSTING_READ(GEN8_PCU_IIR); | |
09f2344d JB |
2737 | |
2738 | ibx_irq_preinstall(dev); | |
abd58f01 BW |
2739 | } |
2740 | ||
82a28bcf | 2741 | static void ibx_hpd_irq_setup(struct drm_device *dev) |
7fe0b973 KP |
2742 | { |
2743 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
82a28bcf DV |
2744 | struct drm_mode_config *mode_config = &dev->mode_config; |
2745 | struct intel_encoder *intel_encoder; | |
fee884ed | 2746 | u32 hotplug_irqs, hotplug, enabled_irqs = 0; |
82a28bcf DV |
2747 | |
2748 | if (HAS_PCH_IBX(dev)) { | |
fee884ed | 2749 | hotplug_irqs = SDE_HOTPLUG_MASK; |
82a28bcf | 2750 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
cd569aed | 2751 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
fee884ed | 2752 | enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin]; |
82a28bcf | 2753 | } else { |
fee884ed | 2754 | hotplug_irqs = SDE_HOTPLUG_MASK_CPT; |
82a28bcf | 2755 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
cd569aed | 2756 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
fee884ed | 2757 | enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin]; |
82a28bcf | 2758 | } |
7fe0b973 | 2759 | |
fee884ed | 2760 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); |
82a28bcf DV |
2761 | |
2762 | /* | |
2763 | * Enable digital hotplug on the PCH, and configure the DP short pulse | |
2764 | * duration to 2ms (which is the minimum in the Display Port spec) | |
2765 | * | |
2766 | * This register is the same on all known PCH chips. | |
2767 | */ | |
7fe0b973 KP |
2768 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
2769 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); | |
2770 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; | |
2771 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; | |
2772 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; | |
2773 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); | |
2774 | } | |
2775 | ||
d46da437 PZ |
2776 | static void ibx_irq_postinstall(struct drm_device *dev) |
2777 | { | |
2778 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
82a28bcf | 2779 | u32 mask; |
e5868a31 | 2780 | |
692a04cf DV |
2781 | if (HAS_PCH_NOP(dev)) |
2782 | return; | |
2783 | ||
8664281b PZ |
2784 | if (HAS_PCH_IBX(dev)) { |
2785 | mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER | | |
de032bf4 | 2786 | SDE_TRANSA_FIFO_UNDER | SDE_POISON; |
8664281b PZ |
2787 | } else { |
2788 | mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT; | |
2789 | ||
2790 | I915_WRITE(SERR_INT, I915_READ(SERR_INT)); | |
2791 | } | |
ab5c608b | 2792 | |
d46da437 PZ |
2793 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); |
2794 | I915_WRITE(SDEIMR, ~mask); | |
d46da437 PZ |
2795 | } |
2796 | ||
0a9a8c91 DV |
2797 | static void gen5_gt_irq_postinstall(struct drm_device *dev) |
2798 | { | |
2799 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2800 | u32 pm_irqs, gt_irqs; | |
2801 | ||
2802 | pm_irqs = gt_irqs = 0; | |
2803 | ||
2804 | dev_priv->gt_irq_mask = ~0; | |
040d2baa | 2805 | if (HAS_L3_DPF(dev)) { |
0a9a8c91 | 2806 | /* L3 parity interrupt is always unmasked. */ |
35a85ac6 BW |
2807 | dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev); |
2808 | gt_irqs |= GT_PARITY_ERROR(dev); | |
0a9a8c91 DV |
2809 | } |
2810 | ||
2811 | gt_irqs |= GT_RENDER_USER_INTERRUPT; | |
2812 | if (IS_GEN5(dev)) { | |
2813 | gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | | |
2814 | ILK_BSD_USER_INTERRUPT; | |
2815 | } else { | |
2816 | gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; | |
2817 | } | |
2818 | ||
2819 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
2820 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
2821 | I915_WRITE(GTIER, gt_irqs); | |
2822 | POSTING_READ(GTIER); | |
2823 | ||
2824 | if (INTEL_INFO(dev)->gen >= 6) { | |
2825 | pm_irqs |= GEN6_PM_RPS_EVENTS; | |
2826 | ||
2827 | if (HAS_VEBOX(dev)) | |
2828 | pm_irqs |= PM_VEBOX_USER_INTERRUPT; | |
2829 | ||
605cd25b | 2830 | dev_priv->pm_irq_mask = 0xffffffff; |
0a9a8c91 | 2831 | I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); |
605cd25b | 2832 | I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask); |
0a9a8c91 DV |
2833 | I915_WRITE(GEN6_PMIER, pm_irqs); |
2834 | POSTING_READ(GEN6_PMIER); | |
2835 | } | |
2836 | } | |
2837 | ||
f71d4af4 | 2838 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d | 2839 | { |
4bc9d430 | 2840 | unsigned long irqflags; |
036a4a7d | 2841 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
8e76f8dc PZ |
2842 | u32 display_mask, extra_mask; |
2843 | ||
2844 | if (INTEL_INFO(dev)->gen >= 7) { | |
2845 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | | |
2846 | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | | |
2847 | DE_PLANEB_FLIP_DONE_IVB | | |
2848 | DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB | | |
2849 | DE_ERR_INT_IVB); | |
2850 | extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | | |
2851 | DE_PIPEA_VBLANK_IVB); | |
2852 | ||
2853 | I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT)); | |
2854 | } else { | |
2855 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | | |
2856 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | | |
5b3a856b DV |
2857 | DE_AUX_CHANNEL_A | |
2858 | DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN | | |
2859 | DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE | | |
2860 | DE_POISON); | |
8e76f8dc PZ |
2861 | extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT; |
2862 | } | |
036a4a7d | 2863 | |
1ec14ad3 | 2864 | dev_priv->irq_mask = ~display_mask; |
036a4a7d ZW |
2865 | |
2866 | /* should always can generate irq */ | |
2867 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1ec14ad3 | 2868 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
8e76f8dc | 2869 | I915_WRITE(DEIER, display_mask | extra_mask); |
3143a2bf | 2870 | POSTING_READ(DEIER); |
036a4a7d | 2871 | |
0a9a8c91 | 2872 | gen5_gt_irq_postinstall(dev); |
036a4a7d | 2873 | |
d46da437 | 2874 | ibx_irq_postinstall(dev); |
7fe0b973 | 2875 | |
f97108d1 | 2876 | if (IS_IRONLAKE_M(dev)) { |
6005ce42 DV |
2877 | /* Enable PCU event interrupts |
2878 | * | |
2879 | * spinlocking not required here for correctness since interrupt | |
4bc9d430 DV |
2880 | * setup is guaranteed to run in single-threaded context. But we |
2881 | * need it to make the assert_spin_locked happy. */ | |
2882 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
f97108d1 | 2883 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); |
4bc9d430 | 2884 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
f97108d1 JB |
2885 | } |
2886 | ||
036a4a7d ZW |
2887 | return 0; |
2888 | } | |
2889 | ||
7e231dbe JB |
2890 | static int valleyview_irq_postinstall(struct drm_device *dev) |
2891 | { | |
2892 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
7e231dbe | 2893 | u32 enable_mask; |
379ef82d DV |
2894 | u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV | |
2895 | PIPE_CRC_DONE_ENABLE; | |
b79480ba | 2896 | unsigned long irqflags; |
7e231dbe JB |
2897 | |
2898 | enable_mask = I915_DISPLAY_PORT_INTERRUPT; | |
31acc7f5 JB |
2899 | enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
2900 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | | |
2901 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
7e231dbe JB |
2902 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
2903 | ||
31acc7f5 JB |
2904 | /* |
2905 | *Leave vblank interrupts masked initially. enable/disable will | |
2906 | * toggle them based on usage. | |
2907 | */ | |
2908 | dev_priv->irq_mask = (~enable_mask) | | |
2909 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | | |
2910 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; | |
7e231dbe | 2911 | |
20afbda2 DV |
2912 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
2913 | POSTING_READ(PORT_HOTPLUG_EN); | |
2914 | ||
7e231dbe JB |
2915 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
2916 | I915_WRITE(VLV_IER, enable_mask); | |
2917 | I915_WRITE(VLV_IIR, 0xffffffff); | |
2918 | I915_WRITE(PIPESTAT(0), 0xffff); | |
2919 | I915_WRITE(PIPESTAT(1), 0xffff); | |
2920 | POSTING_READ(VLV_IER); | |
2921 | ||
b79480ba DV |
2922 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
2923 | * just to make the assert_spin_locked check happy. */ | |
2924 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3b6c42e8 DV |
2925 | i915_enable_pipestat(dev_priv, PIPE_A, pipestat_enable); |
2926 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE); | |
2927 | i915_enable_pipestat(dev_priv, PIPE_B, pipestat_enable); | |
b79480ba | 2928 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
31acc7f5 | 2929 | |
7e231dbe JB |
2930 | I915_WRITE(VLV_IIR, 0xffffffff); |
2931 | I915_WRITE(VLV_IIR, 0xffffffff); | |
2932 | ||
0a9a8c91 | 2933 | gen5_gt_irq_postinstall(dev); |
7e231dbe JB |
2934 | |
2935 | /* ack & enable invalid PTE error interrupts */ | |
2936 | #if 0 /* FIXME: add support to irq handler for checking these bits */ | |
2937 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); | |
2938 | I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); | |
2939 | #endif | |
2940 | ||
2941 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); | |
20afbda2 DV |
2942 | |
2943 | return 0; | |
2944 | } | |
2945 | ||
abd58f01 BW |
2946 | static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) |
2947 | { | |
2948 | int i; | |
2949 | ||
2950 | /* These are interrupts we'll toggle with the ring mask register */ | |
2951 | uint32_t gt_interrupts[] = { | |
2952 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | | |
2953 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT | | |
2954 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT, | |
2955 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | | |
2956 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT, | |
2957 | 0, | |
2958 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
2959 | }; | |
2960 | ||
2961 | for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) { | |
2962 | u32 tmp = I915_READ(GEN8_GT_IIR(i)); | |
2963 | if (tmp) | |
2964 | DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n", | |
2965 | i, tmp); | |
2966 | I915_WRITE(GEN8_GT_IMR(i), ~gt_interrupts[i]); | |
2967 | I915_WRITE(GEN8_GT_IER(i), gt_interrupts[i]); | |
2968 | } | |
2969 | POSTING_READ(GEN8_GT_IER(0)); | |
2970 | } | |
2971 | ||
2972 | static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) | |
2973 | { | |
2974 | struct drm_device *dev = dev_priv->dev; | |
13b3a0a7 DV |
2975 | uint32_t de_pipe_masked = GEN8_PIPE_FLIP_DONE | |
2976 | GEN8_PIPE_CDCLK_CRC_DONE | | |
2977 | GEN8_PIPE_FIFO_UNDERRUN | | |
2978 | GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
2979 | uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK; | |
abd58f01 | 2980 | int pipe; |
13b3a0a7 DV |
2981 | dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; |
2982 | dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; | |
2983 | dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; | |
abd58f01 BW |
2984 | |
2985 | for_each_pipe(pipe) { | |
2986 | u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe)); | |
2987 | if (tmp) | |
2988 | DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n", | |
2989 | pipe, tmp); | |
2990 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2991 | I915_WRITE(GEN8_DE_PIPE_IER(pipe), de_pipe_enables); | |
2992 | } | |
2993 | POSTING_READ(GEN8_DE_PIPE_ISR(0)); | |
2994 | ||
6d766f02 DV |
2995 | I915_WRITE(GEN8_DE_PORT_IMR, ~GEN8_AUX_CHANNEL_A); |
2996 | I915_WRITE(GEN8_DE_PORT_IER, GEN8_AUX_CHANNEL_A); | |
abd58f01 BW |
2997 | POSTING_READ(GEN8_DE_PORT_IER); |
2998 | } | |
2999 | ||
3000 | static int gen8_irq_postinstall(struct drm_device *dev) | |
3001 | { | |
3002 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3003 | ||
3004 | gen8_gt_irq_postinstall(dev_priv); | |
3005 | gen8_de_irq_postinstall(dev_priv); | |
3006 | ||
3007 | ibx_irq_postinstall(dev); | |
3008 | ||
3009 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); | |
3010 | POSTING_READ(GEN8_MASTER_IRQ); | |
3011 | ||
3012 | return 0; | |
3013 | } | |
3014 | ||
3015 | static void gen8_irq_uninstall(struct drm_device *dev) | |
3016 | { | |
3017 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3018 | int pipe; | |
3019 | ||
3020 | if (!dev_priv) | |
3021 | return; | |
3022 | ||
3023 | atomic_set(&dev_priv->irq_received, 0); | |
3024 | ||
3025 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3026 | ||
3027 | #define GEN8_IRQ_FINI_NDX(type, which) do { \ | |
3028 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ | |
3029 | I915_WRITE(GEN8_##type##_IER(which), 0); \ | |
3030 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
3031 | } while (0) | |
3032 | ||
3033 | #define GEN8_IRQ_FINI(type) do { \ | |
3034 | I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \ | |
3035 | I915_WRITE(GEN8_##type##_IER, 0); \ | |
3036 | I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ | |
3037 | } while (0) | |
3038 | ||
3039 | GEN8_IRQ_FINI_NDX(GT, 0); | |
3040 | GEN8_IRQ_FINI_NDX(GT, 1); | |
3041 | GEN8_IRQ_FINI_NDX(GT, 2); | |
3042 | GEN8_IRQ_FINI_NDX(GT, 3); | |
3043 | ||
3044 | for_each_pipe(pipe) { | |
3045 | GEN8_IRQ_FINI_NDX(DE_PIPE, pipe); | |
3046 | } | |
3047 | ||
3048 | GEN8_IRQ_FINI(DE_PORT); | |
3049 | GEN8_IRQ_FINI(DE_MISC); | |
3050 | GEN8_IRQ_FINI(PCU); | |
3051 | #undef GEN8_IRQ_FINI | |
3052 | #undef GEN8_IRQ_FINI_NDX | |
3053 | ||
3054 | POSTING_READ(GEN8_PCU_IIR); | |
3055 | } | |
3056 | ||
7e231dbe JB |
3057 | static void valleyview_irq_uninstall(struct drm_device *dev) |
3058 | { | |
3059 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
3060 | int pipe; | |
3061 | ||
3062 | if (!dev_priv) | |
3063 | return; | |
3064 | ||
ac4c16c5 EE |
3065 | del_timer_sync(&dev_priv->hotplug_reenable_timer); |
3066 | ||
7e231dbe JB |
3067 | for_each_pipe(pipe) |
3068 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
3069 | ||
3070 | I915_WRITE(HWSTAM, 0xffffffff); | |
3071 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3072 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3073 | for_each_pipe(pipe) | |
3074 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
3075 | I915_WRITE(VLV_IIR, 0xffffffff); | |
3076 | I915_WRITE(VLV_IMR, 0xffffffff); | |
3077 | I915_WRITE(VLV_IER, 0x0); | |
3078 | POSTING_READ(VLV_IER); | |
3079 | } | |
3080 | ||
f71d4af4 | 3081 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d ZW |
3082 | { |
3083 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
4697995b JB |
3084 | |
3085 | if (!dev_priv) | |
3086 | return; | |
3087 | ||
ac4c16c5 EE |
3088 | del_timer_sync(&dev_priv->hotplug_reenable_timer); |
3089 | ||
036a4a7d ZW |
3090 | I915_WRITE(HWSTAM, 0xffffffff); |
3091 | ||
3092 | I915_WRITE(DEIMR, 0xffffffff); | |
3093 | I915_WRITE(DEIER, 0x0); | |
3094 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
8664281b PZ |
3095 | if (IS_GEN7(dev)) |
3096 | I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT)); | |
036a4a7d ZW |
3097 | |
3098 | I915_WRITE(GTIMR, 0xffffffff); | |
3099 | I915_WRITE(GTIER, 0x0); | |
3100 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
192aac1f | 3101 | |
ab5c608b BW |
3102 | if (HAS_PCH_NOP(dev)) |
3103 | return; | |
3104 | ||
192aac1f KP |
3105 | I915_WRITE(SDEIMR, 0xffffffff); |
3106 | I915_WRITE(SDEIER, 0x0); | |
3107 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | |
8664281b PZ |
3108 | if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) |
3109 | I915_WRITE(SERR_INT, I915_READ(SERR_INT)); | |
036a4a7d ZW |
3110 | } |
3111 | ||
a266c7d5 | 3112 | static void i8xx_irq_preinstall(struct drm_device * dev) |
1da177e4 LT |
3113 | { |
3114 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 3115 | int pipe; |
91e3738e | 3116 | |
a266c7d5 | 3117 | atomic_set(&dev_priv->irq_received, 0); |
5ca58282 | 3118 | |
9db4a9c7 JB |
3119 | for_each_pipe(pipe) |
3120 | I915_WRITE(PIPESTAT(pipe), 0); | |
a266c7d5 CW |
3121 | I915_WRITE16(IMR, 0xffff); |
3122 | I915_WRITE16(IER, 0x0); | |
3123 | POSTING_READ16(IER); | |
c2798b19 CW |
3124 | } |
3125 | ||
3126 | static int i8xx_irq_postinstall(struct drm_device *dev) | |
3127 | { | |
3128 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
379ef82d | 3129 | unsigned long irqflags; |
c2798b19 | 3130 | |
c2798b19 CW |
3131 | I915_WRITE16(EMR, |
3132 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); | |
3133 | ||
3134 | /* Unmask the interrupts that we always want on. */ | |
3135 | dev_priv->irq_mask = | |
3136 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3137 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3138 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3139 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3140 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3141 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
3142 | ||
3143 | I915_WRITE16(IER, | |
3144 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3145 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3146 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
3147 | I915_USER_INTERRUPT); | |
3148 | POSTING_READ16(IER); | |
3149 | ||
379ef82d DV |
3150 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3151 | * just to make the assert_spin_locked check happy. */ | |
3152 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3b6c42e8 DV |
3153 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE); |
3154 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE); | |
379ef82d DV |
3155 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
3156 | ||
c2798b19 CW |
3157 | return 0; |
3158 | } | |
3159 | ||
90a72f87 VS |
3160 | /* |
3161 | * Returns true when a page flip has completed. | |
3162 | */ | |
3163 | static bool i8xx_handle_vblank(struct drm_device *dev, | |
1f1c2e24 | 3164 | int plane, int pipe, u32 iir) |
90a72f87 VS |
3165 | { |
3166 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1f1c2e24 | 3167 | u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
90a72f87 VS |
3168 | |
3169 | if (!drm_handle_vblank(dev, pipe)) | |
3170 | return false; | |
3171 | ||
3172 | if ((iir & flip_pending) == 0) | |
3173 | return false; | |
3174 | ||
1f1c2e24 | 3175 | intel_prepare_page_flip(dev, plane); |
90a72f87 VS |
3176 | |
3177 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
3178 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3179 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3180 | * the flip is completed (no longer pending). Since this doesn't raise | |
3181 | * an interrupt per se, we watch for the change at vblank. | |
3182 | */ | |
3183 | if (I915_READ16(ISR) & flip_pending) | |
3184 | return false; | |
3185 | ||
3186 | intel_finish_page_flip(dev, pipe); | |
3187 | ||
3188 | return true; | |
3189 | } | |
3190 | ||
ff1f525e | 3191 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
c2798b19 CW |
3192 | { |
3193 | struct drm_device *dev = (struct drm_device *) arg; | |
3194 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
c2798b19 CW |
3195 | u16 iir, new_iir; |
3196 | u32 pipe_stats[2]; | |
3197 | unsigned long irqflags; | |
c2798b19 CW |
3198 | int pipe; |
3199 | u16 flip_mask = | |
3200 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3201 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
3202 | ||
3203 | atomic_inc(&dev_priv->irq_received); | |
3204 | ||
3205 | iir = I915_READ16(IIR); | |
3206 | if (iir == 0) | |
3207 | return IRQ_NONE; | |
3208 | ||
3209 | while (iir & ~flip_mask) { | |
3210 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3211 | * have been cleared after the pipestat interrupt was received. | |
3212 | * It doesn't set the bit in iir again, but it still produces | |
3213 | * interrupts (for non-MSI). | |
3214 | */ | |
3215 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3216 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
3217 | i915_handle_error(dev, false); | |
3218 | ||
3219 | for_each_pipe(pipe) { | |
3220 | int reg = PIPESTAT(pipe); | |
3221 | pipe_stats[pipe] = I915_READ(reg); | |
3222 | ||
3223 | /* | |
3224 | * Clear the PIPE*STAT regs before the IIR | |
3225 | */ | |
3226 | if (pipe_stats[pipe] & 0x8000ffff) { | |
3227 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | |
3228 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | |
3229 | pipe_name(pipe)); | |
3230 | I915_WRITE(reg, pipe_stats[pipe]); | |
c2798b19 CW |
3231 | } |
3232 | } | |
3233 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3234 | ||
3235 | I915_WRITE16(IIR, iir & ~flip_mask); | |
3236 | new_iir = I915_READ16(IIR); /* Flush posted writes */ | |
3237 | ||
d05c617e | 3238 | i915_update_dri1_breadcrumb(dev); |
c2798b19 CW |
3239 | |
3240 | if (iir & I915_USER_INTERRUPT) | |
3241 | notify_ring(dev, &dev_priv->ring[RCS]); | |
3242 | ||
4356d586 | 3243 | for_each_pipe(pipe) { |
1f1c2e24 | 3244 | int plane = pipe; |
3a77c4c4 | 3245 | if (HAS_FBC(dev)) |
1f1c2e24 VS |
3246 | plane = !plane; |
3247 | ||
4356d586 | 3248 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
1f1c2e24 VS |
3249 | i8xx_handle_vblank(dev, plane, pipe, iir)) |
3250 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
c2798b19 | 3251 | |
4356d586 | 3252 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
277de95e | 3253 | i9xx_pipe_crc_irq_handler(dev, pipe); |
4356d586 | 3254 | } |
c2798b19 CW |
3255 | |
3256 | iir = new_iir; | |
3257 | } | |
3258 | ||
3259 | return IRQ_HANDLED; | |
3260 | } | |
3261 | ||
3262 | static void i8xx_irq_uninstall(struct drm_device * dev) | |
3263 | { | |
3264 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
3265 | int pipe; | |
3266 | ||
c2798b19 CW |
3267 | for_each_pipe(pipe) { |
3268 | /* Clear enable bits; then clear status bits */ | |
3269 | I915_WRITE(PIPESTAT(pipe), 0); | |
3270 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); | |
3271 | } | |
3272 | I915_WRITE16(IMR, 0xffff); | |
3273 | I915_WRITE16(IER, 0x0); | |
3274 | I915_WRITE16(IIR, I915_READ16(IIR)); | |
3275 | } | |
3276 | ||
a266c7d5 CW |
3277 | static void i915_irq_preinstall(struct drm_device * dev) |
3278 | { | |
3279 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
3280 | int pipe; | |
3281 | ||
3282 | atomic_set(&dev_priv->irq_received, 0); | |
3283 | ||
3284 | if (I915_HAS_HOTPLUG(dev)) { | |
3285 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3286 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3287 | } | |
3288 | ||
00d98ebd | 3289 | I915_WRITE16(HWSTAM, 0xeffe); |
a266c7d5 CW |
3290 | for_each_pipe(pipe) |
3291 | I915_WRITE(PIPESTAT(pipe), 0); | |
3292 | I915_WRITE(IMR, 0xffffffff); | |
3293 | I915_WRITE(IER, 0x0); | |
3294 | POSTING_READ(IER); | |
3295 | } | |
3296 | ||
3297 | static int i915_irq_postinstall(struct drm_device *dev) | |
3298 | { | |
3299 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
38bde180 | 3300 | u32 enable_mask; |
379ef82d | 3301 | unsigned long irqflags; |
a266c7d5 | 3302 | |
38bde180 CW |
3303 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
3304 | ||
3305 | /* Unmask the interrupts that we always want on. */ | |
3306 | dev_priv->irq_mask = | |
3307 | ~(I915_ASLE_INTERRUPT | | |
3308 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3309 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3310 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3311 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3312 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3313 | ||
3314 | enable_mask = | |
3315 | I915_ASLE_INTERRUPT | | |
3316 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3317 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3318 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
3319 | I915_USER_INTERRUPT; | |
3320 | ||
a266c7d5 | 3321 | if (I915_HAS_HOTPLUG(dev)) { |
20afbda2 DV |
3322 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3323 | POSTING_READ(PORT_HOTPLUG_EN); | |
3324 | ||
a266c7d5 CW |
3325 | /* Enable in IER... */ |
3326 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
3327 | /* and unmask in IMR */ | |
3328 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; | |
3329 | } | |
3330 | ||
a266c7d5 CW |
3331 | I915_WRITE(IMR, dev_priv->irq_mask); |
3332 | I915_WRITE(IER, enable_mask); | |
3333 | POSTING_READ(IER); | |
3334 | ||
f49e38dd | 3335 | i915_enable_asle_pipestat(dev); |
20afbda2 | 3336 | |
379ef82d DV |
3337 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3338 | * just to make the assert_spin_locked check happy. */ | |
3339 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3b6c42e8 DV |
3340 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE); |
3341 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE); | |
379ef82d DV |
3342 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
3343 | ||
20afbda2 DV |
3344 | return 0; |
3345 | } | |
3346 | ||
90a72f87 VS |
3347 | /* |
3348 | * Returns true when a page flip has completed. | |
3349 | */ | |
3350 | static bool i915_handle_vblank(struct drm_device *dev, | |
3351 | int plane, int pipe, u32 iir) | |
3352 | { | |
3353 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3354 | u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); | |
3355 | ||
3356 | if (!drm_handle_vblank(dev, pipe)) | |
3357 | return false; | |
3358 | ||
3359 | if ((iir & flip_pending) == 0) | |
3360 | return false; | |
3361 | ||
3362 | intel_prepare_page_flip(dev, plane); | |
3363 | ||
3364 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
3365 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3366 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3367 | * the flip is completed (no longer pending). Since this doesn't raise | |
3368 | * an interrupt per se, we watch for the change at vblank. | |
3369 | */ | |
3370 | if (I915_READ(ISR) & flip_pending) | |
3371 | return false; | |
3372 | ||
3373 | intel_finish_page_flip(dev, pipe); | |
3374 | ||
3375 | return true; | |
3376 | } | |
3377 | ||
ff1f525e | 3378 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
a266c7d5 CW |
3379 | { |
3380 | struct drm_device *dev = (struct drm_device *) arg; | |
3381 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
8291ee90 | 3382 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
a266c7d5 | 3383 | unsigned long irqflags; |
38bde180 CW |
3384 | u32 flip_mask = |
3385 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3386 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
38bde180 | 3387 | int pipe, ret = IRQ_NONE; |
a266c7d5 CW |
3388 | |
3389 | atomic_inc(&dev_priv->irq_received); | |
3390 | ||
3391 | iir = I915_READ(IIR); | |
38bde180 CW |
3392 | do { |
3393 | bool irq_received = (iir & ~flip_mask) != 0; | |
8291ee90 | 3394 | bool blc_event = false; |
a266c7d5 CW |
3395 | |
3396 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3397 | * have been cleared after the pipestat interrupt was received. | |
3398 | * It doesn't set the bit in iir again, but it still produces | |
3399 | * interrupts (for non-MSI). | |
3400 | */ | |
3401 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3402 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
3403 | i915_handle_error(dev, false); | |
3404 | ||
3405 | for_each_pipe(pipe) { | |
3406 | int reg = PIPESTAT(pipe); | |
3407 | pipe_stats[pipe] = I915_READ(reg); | |
3408 | ||
38bde180 | 3409 | /* Clear the PIPE*STAT regs before the IIR */ |
a266c7d5 CW |
3410 | if (pipe_stats[pipe] & 0x8000ffff) { |
3411 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | |
3412 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | |
3413 | pipe_name(pipe)); | |
3414 | I915_WRITE(reg, pipe_stats[pipe]); | |
38bde180 | 3415 | irq_received = true; |
a266c7d5 CW |
3416 | } |
3417 | } | |
3418 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3419 | ||
3420 | if (!irq_received) | |
3421 | break; | |
3422 | ||
a266c7d5 CW |
3423 | /* Consume port. Then clear IIR or we'll miss events */ |
3424 | if ((I915_HAS_HOTPLUG(dev)) && | |
3425 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { | |
3426 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
b543fb04 | 3427 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; |
a266c7d5 CW |
3428 | |
3429 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", | |
3430 | hotplug_status); | |
91d131d2 DV |
3431 | |
3432 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); | |
3433 | ||
a266c7d5 | 3434 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
38bde180 | 3435 | POSTING_READ(PORT_HOTPLUG_STAT); |
a266c7d5 CW |
3436 | } |
3437 | ||
38bde180 | 3438 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
3439 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
3440 | ||
a266c7d5 CW |
3441 | if (iir & I915_USER_INTERRUPT) |
3442 | notify_ring(dev, &dev_priv->ring[RCS]); | |
a266c7d5 | 3443 | |
a266c7d5 | 3444 | for_each_pipe(pipe) { |
38bde180 | 3445 | int plane = pipe; |
3a77c4c4 | 3446 | if (HAS_FBC(dev)) |
38bde180 | 3447 | plane = !plane; |
90a72f87 | 3448 | |
8291ee90 | 3449 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
3450 | i915_handle_vblank(dev, plane, pipe, iir)) |
3451 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
a266c7d5 CW |
3452 | |
3453 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
3454 | blc_event = true; | |
4356d586 DV |
3455 | |
3456 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 3457 | i9xx_pipe_crc_irq_handler(dev, pipe); |
a266c7d5 CW |
3458 | } |
3459 | ||
a266c7d5 CW |
3460 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
3461 | intel_opregion_asle_intr(dev); | |
3462 | ||
3463 | /* With MSI, interrupts are only generated when iir | |
3464 | * transitions from zero to nonzero. If another bit got | |
3465 | * set while we were handling the existing iir bits, then | |
3466 | * we would never get another interrupt. | |
3467 | * | |
3468 | * This is fine on non-MSI as well, as if we hit this path | |
3469 | * we avoid exiting the interrupt handler only to generate | |
3470 | * another one. | |
3471 | * | |
3472 | * Note that for MSI this could cause a stray interrupt report | |
3473 | * if an interrupt landed in the time between writing IIR and | |
3474 | * the posting read. This should be rare enough to never | |
3475 | * trigger the 99% of 100,000 interrupts test for disabling | |
3476 | * stray interrupts. | |
3477 | */ | |
38bde180 | 3478 | ret = IRQ_HANDLED; |
a266c7d5 | 3479 | iir = new_iir; |
38bde180 | 3480 | } while (iir & ~flip_mask); |
a266c7d5 | 3481 | |
d05c617e | 3482 | i915_update_dri1_breadcrumb(dev); |
8291ee90 | 3483 | |
a266c7d5 CW |
3484 | return ret; |
3485 | } | |
3486 | ||
3487 | static void i915_irq_uninstall(struct drm_device * dev) | |
3488 | { | |
3489 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
3490 | int pipe; | |
3491 | ||
ac4c16c5 EE |
3492 | del_timer_sync(&dev_priv->hotplug_reenable_timer); |
3493 | ||
a266c7d5 CW |
3494 | if (I915_HAS_HOTPLUG(dev)) { |
3495 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3496 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3497 | } | |
3498 | ||
00d98ebd | 3499 | I915_WRITE16(HWSTAM, 0xffff); |
55b39755 CW |
3500 | for_each_pipe(pipe) { |
3501 | /* Clear enable bits; then clear status bits */ | |
a266c7d5 | 3502 | I915_WRITE(PIPESTAT(pipe), 0); |
55b39755 CW |
3503 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
3504 | } | |
a266c7d5 CW |
3505 | I915_WRITE(IMR, 0xffffffff); |
3506 | I915_WRITE(IER, 0x0); | |
3507 | ||
a266c7d5 CW |
3508 | I915_WRITE(IIR, I915_READ(IIR)); |
3509 | } | |
3510 | ||
3511 | static void i965_irq_preinstall(struct drm_device * dev) | |
3512 | { | |
3513 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
3514 | int pipe; | |
3515 | ||
3516 | atomic_set(&dev_priv->irq_received, 0); | |
3517 | ||
adca4730 CW |
3518 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3519 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
3520 | |
3521 | I915_WRITE(HWSTAM, 0xeffe); | |
3522 | for_each_pipe(pipe) | |
3523 | I915_WRITE(PIPESTAT(pipe), 0); | |
3524 | I915_WRITE(IMR, 0xffffffff); | |
3525 | I915_WRITE(IER, 0x0); | |
3526 | POSTING_READ(IER); | |
3527 | } | |
3528 | ||
3529 | static int i965_irq_postinstall(struct drm_device *dev) | |
3530 | { | |
3531 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
bbba0a97 | 3532 | u32 enable_mask; |
a266c7d5 | 3533 | u32 error_mask; |
b79480ba | 3534 | unsigned long irqflags; |
a266c7d5 | 3535 | |
a266c7d5 | 3536 | /* Unmask the interrupts that we always want on. */ |
bbba0a97 | 3537 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
adca4730 | 3538 | I915_DISPLAY_PORT_INTERRUPT | |
bbba0a97 CW |
3539 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
3540 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3541 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3542 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3543 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3544 | ||
3545 | enable_mask = ~dev_priv->irq_mask; | |
21ad8330 VS |
3546 | enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
3547 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); | |
bbba0a97 CW |
3548 | enable_mask |= I915_USER_INTERRUPT; |
3549 | ||
3550 | if (IS_G4X(dev)) | |
3551 | enable_mask |= I915_BSD_USER_INTERRUPT; | |
a266c7d5 | 3552 | |
b79480ba DV |
3553 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3554 | * just to make the assert_spin_locked check happy. */ | |
3555 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3b6c42e8 DV |
3556 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE); |
3557 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE); | |
3558 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE); | |
b79480ba | 3559 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
a266c7d5 | 3560 | |
a266c7d5 CW |
3561 | /* |
3562 | * Enable some error detection, note the instruction error mask | |
3563 | * bit is reserved, so we leave it masked. | |
3564 | */ | |
3565 | if (IS_G4X(dev)) { | |
3566 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
3567 | GM45_ERROR_MEM_PRIV | | |
3568 | GM45_ERROR_CP_PRIV | | |
3569 | I915_ERROR_MEMORY_REFRESH); | |
3570 | } else { | |
3571 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
3572 | I915_ERROR_MEMORY_REFRESH); | |
3573 | } | |
3574 | I915_WRITE(EMR, error_mask); | |
3575 | ||
3576 | I915_WRITE(IMR, dev_priv->irq_mask); | |
3577 | I915_WRITE(IER, enable_mask); | |
3578 | POSTING_READ(IER); | |
3579 | ||
20afbda2 DV |
3580 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3581 | POSTING_READ(PORT_HOTPLUG_EN); | |
3582 | ||
f49e38dd | 3583 | i915_enable_asle_pipestat(dev); |
20afbda2 DV |
3584 | |
3585 | return 0; | |
3586 | } | |
3587 | ||
bac56d5b | 3588 | static void i915_hpd_irq_setup(struct drm_device *dev) |
20afbda2 DV |
3589 | { |
3590 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e5868a31 | 3591 | struct drm_mode_config *mode_config = &dev->mode_config; |
cd569aed | 3592 | struct intel_encoder *intel_encoder; |
20afbda2 DV |
3593 | u32 hotplug_en; |
3594 | ||
b5ea2d56 DV |
3595 | assert_spin_locked(&dev_priv->irq_lock); |
3596 | ||
bac56d5b EE |
3597 | if (I915_HAS_HOTPLUG(dev)) { |
3598 | hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
3599 | hotplug_en &= ~HOTPLUG_INT_EN_MASK; | |
3600 | /* Note HDMI and DP share hotplug bits */ | |
e5868a31 | 3601 | /* enable bits are the same for all generations */ |
cd569aed EE |
3602 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
3603 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) | |
3604 | hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin]; | |
bac56d5b EE |
3605 | /* Programming the CRT detection parameters tends |
3606 | to generate a spurious hotplug event about three | |
3607 | seconds later. So just do it once. | |
3608 | */ | |
3609 | if (IS_G4X(dev)) | |
3610 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
85fc95ba | 3611 | hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK; |
bac56d5b | 3612 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
a266c7d5 | 3613 | |
bac56d5b EE |
3614 | /* Ignore TV since it's buggy */ |
3615 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
3616 | } | |
a266c7d5 CW |
3617 | } |
3618 | ||
ff1f525e | 3619 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
a266c7d5 CW |
3620 | { |
3621 | struct drm_device *dev = (struct drm_device *) arg; | |
3622 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
a266c7d5 CW |
3623 | u32 iir, new_iir; |
3624 | u32 pipe_stats[I915_MAX_PIPES]; | |
a266c7d5 CW |
3625 | unsigned long irqflags; |
3626 | int irq_received; | |
3627 | int ret = IRQ_NONE, pipe; | |
21ad8330 VS |
3628 | u32 flip_mask = |
3629 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3630 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
a266c7d5 CW |
3631 | |
3632 | atomic_inc(&dev_priv->irq_received); | |
3633 | ||
3634 | iir = I915_READ(IIR); | |
3635 | ||
a266c7d5 | 3636 | for (;;) { |
2c8ba29f CW |
3637 | bool blc_event = false; |
3638 | ||
21ad8330 | 3639 | irq_received = (iir & ~flip_mask) != 0; |
a266c7d5 CW |
3640 | |
3641 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3642 | * have been cleared after the pipestat interrupt was received. | |
3643 | * It doesn't set the bit in iir again, but it still produces | |
3644 | * interrupts (for non-MSI). | |
3645 | */ | |
3646 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3647 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
3648 | i915_handle_error(dev, false); | |
3649 | ||
3650 | for_each_pipe(pipe) { | |
3651 | int reg = PIPESTAT(pipe); | |
3652 | pipe_stats[pipe] = I915_READ(reg); | |
3653 | ||
3654 | /* | |
3655 | * Clear the PIPE*STAT regs before the IIR | |
3656 | */ | |
3657 | if (pipe_stats[pipe] & 0x8000ffff) { | |
3658 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | |
3659 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | |
3660 | pipe_name(pipe)); | |
3661 | I915_WRITE(reg, pipe_stats[pipe]); | |
3662 | irq_received = 1; | |
3663 | } | |
3664 | } | |
3665 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3666 | ||
3667 | if (!irq_received) | |
3668 | break; | |
3669 | ||
3670 | ret = IRQ_HANDLED; | |
3671 | ||
3672 | /* Consume port. Then clear IIR or we'll miss events */ | |
adca4730 | 3673 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { |
a266c7d5 | 3674 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
b543fb04 EE |
3675 | u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ? |
3676 | HOTPLUG_INT_STATUS_G4X : | |
4f7fd709 | 3677 | HOTPLUG_INT_STATUS_I915); |
a266c7d5 CW |
3678 | |
3679 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", | |
3680 | hotplug_status); | |
91d131d2 DV |
3681 | |
3682 | intel_hpd_irq_handler(dev, hotplug_trigger, | |
704cfb87 | 3683 | IS_G4X(dev) ? hpd_status_g4x : hpd_status_i915); |
91d131d2 | 3684 | |
4aeebd74 DV |
3685 | if (IS_G4X(dev) && |
3686 | (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)) | |
3687 | dp_aux_irq_handler(dev); | |
3688 | ||
a266c7d5 CW |
3689 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
3690 | I915_READ(PORT_HOTPLUG_STAT); | |
3691 | } | |
3692 | ||
21ad8330 | 3693 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
3694 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
3695 | ||
a266c7d5 CW |
3696 | if (iir & I915_USER_INTERRUPT) |
3697 | notify_ring(dev, &dev_priv->ring[RCS]); | |
3698 | if (iir & I915_BSD_USER_INTERRUPT) | |
3699 | notify_ring(dev, &dev_priv->ring[VCS]); | |
3700 | ||
a266c7d5 | 3701 | for_each_pipe(pipe) { |
2c8ba29f | 3702 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
3703 | i915_handle_vblank(dev, pipe, pipe, iir)) |
3704 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); | |
a266c7d5 CW |
3705 | |
3706 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
3707 | blc_event = true; | |
4356d586 DV |
3708 | |
3709 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 3710 | i9xx_pipe_crc_irq_handler(dev, pipe); |
a266c7d5 CW |
3711 | } |
3712 | ||
3713 | ||
3714 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | |
3715 | intel_opregion_asle_intr(dev); | |
3716 | ||
515ac2bb DV |
3717 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
3718 | gmbus_irq_handler(dev); | |
3719 | ||
a266c7d5 CW |
3720 | /* With MSI, interrupts are only generated when iir |
3721 | * transitions from zero to nonzero. If another bit got | |
3722 | * set while we were handling the existing iir bits, then | |
3723 | * we would never get another interrupt. | |
3724 | * | |
3725 | * This is fine on non-MSI as well, as if we hit this path | |
3726 | * we avoid exiting the interrupt handler only to generate | |
3727 | * another one. | |
3728 | * | |
3729 | * Note that for MSI this could cause a stray interrupt report | |
3730 | * if an interrupt landed in the time between writing IIR and | |
3731 | * the posting read. This should be rare enough to never | |
3732 | * trigger the 99% of 100,000 interrupts test for disabling | |
3733 | * stray interrupts. | |
3734 | */ | |
3735 | iir = new_iir; | |
3736 | } | |
3737 | ||
d05c617e | 3738 | i915_update_dri1_breadcrumb(dev); |
2c8ba29f | 3739 | |
a266c7d5 CW |
3740 | return ret; |
3741 | } | |
3742 | ||
3743 | static void i965_irq_uninstall(struct drm_device * dev) | |
3744 | { | |
3745 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
3746 | int pipe; | |
3747 | ||
3748 | if (!dev_priv) | |
3749 | return; | |
3750 | ||
ac4c16c5 EE |
3751 | del_timer_sync(&dev_priv->hotplug_reenable_timer); |
3752 | ||
adca4730 CW |
3753 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3754 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
3755 | |
3756 | I915_WRITE(HWSTAM, 0xffffffff); | |
3757 | for_each_pipe(pipe) | |
3758 | I915_WRITE(PIPESTAT(pipe), 0); | |
3759 | I915_WRITE(IMR, 0xffffffff); | |
3760 | I915_WRITE(IER, 0x0); | |
3761 | ||
3762 | for_each_pipe(pipe) | |
3763 | I915_WRITE(PIPESTAT(pipe), | |
3764 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); | |
3765 | I915_WRITE(IIR, I915_READ(IIR)); | |
3766 | } | |
3767 | ||
ac4c16c5 EE |
3768 | static void i915_reenable_hotplug_timer_func(unsigned long data) |
3769 | { | |
3770 | drm_i915_private_t *dev_priv = (drm_i915_private_t *)data; | |
3771 | struct drm_device *dev = dev_priv->dev; | |
3772 | struct drm_mode_config *mode_config = &dev->mode_config; | |
3773 | unsigned long irqflags; | |
3774 | int i; | |
3775 | ||
3776 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3777 | for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) { | |
3778 | struct drm_connector *connector; | |
3779 | ||
3780 | if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED) | |
3781 | continue; | |
3782 | ||
3783 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
3784 | ||
3785 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
3786 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
3787 | ||
3788 | if (intel_connector->encoder->hpd_pin == i) { | |
3789 | if (connector->polled != intel_connector->polled) | |
3790 | DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n", | |
3791 | drm_get_connector_name(connector)); | |
3792 | connector->polled = intel_connector->polled; | |
3793 | if (!connector->polled) | |
3794 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
3795 | } | |
3796 | } | |
3797 | } | |
3798 | if (dev_priv->display.hpd_irq_setup) | |
3799 | dev_priv->display.hpd_irq_setup(dev); | |
3800 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3801 | } | |
3802 | ||
f71d4af4 JB |
3803 | void intel_irq_init(struct drm_device *dev) |
3804 | { | |
8b2e326d CW |
3805 | struct drm_i915_private *dev_priv = dev->dev_private; |
3806 | ||
3807 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); | |
99584db3 | 3808 | INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func); |
c6a828d3 | 3809 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
a4da4fa4 | 3810 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
8b2e326d | 3811 | |
99584db3 DV |
3812 | setup_timer(&dev_priv->gpu_error.hangcheck_timer, |
3813 | i915_hangcheck_elapsed, | |
61bac78e | 3814 | (unsigned long) dev); |
ac4c16c5 EE |
3815 | setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func, |
3816 | (unsigned long) dev_priv); | |
61bac78e | 3817 | |
97a19a24 | 3818 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); |
9ee32fea | 3819 | |
4cdb83ec VS |
3820 | if (IS_GEN2(dev)) { |
3821 | dev->max_vblank_count = 0; | |
3822 | dev->driver->get_vblank_counter = i8xx_get_vblank_counter; | |
3823 | } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { | |
f71d4af4 JB |
3824 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
3825 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; | |
391f75e2 VS |
3826 | } else { |
3827 | dev->driver->get_vblank_counter = i915_get_vblank_counter; | |
3828 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
f71d4af4 JB |
3829 | } |
3830 | ||
c2baf4b7 | 3831 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
c3613de9 | 3832 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; |
c2baf4b7 VS |
3833 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; |
3834 | } | |
f71d4af4 | 3835 | |
7e231dbe JB |
3836 | if (IS_VALLEYVIEW(dev)) { |
3837 | dev->driver->irq_handler = valleyview_irq_handler; | |
3838 | dev->driver->irq_preinstall = valleyview_irq_preinstall; | |
3839 | dev->driver->irq_postinstall = valleyview_irq_postinstall; | |
3840 | dev->driver->irq_uninstall = valleyview_irq_uninstall; | |
3841 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
3842 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
fa00abe0 | 3843 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
abd58f01 BW |
3844 | } else if (IS_GEN8(dev)) { |
3845 | dev->driver->irq_handler = gen8_irq_handler; | |
3846 | dev->driver->irq_preinstall = gen8_irq_preinstall; | |
3847 | dev->driver->irq_postinstall = gen8_irq_postinstall; | |
3848 | dev->driver->irq_uninstall = gen8_irq_uninstall; | |
3849 | dev->driver->enable_vblank = gen8_enable_vblank; | |
3850 | dev->driver->disable_vblank = gen8_disable_vblank; | |
3851 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; | |
f71d4af4 JB |
3852 | } else if (HAS_PCH_SPLIT(dev)) { |
3853 | dev->driver->irq_handler = ironlake_irq_handler; | |
3854 | dev->driver->irq_preinstall = ironlake_irq_preinstall; | |
3855 | dev->driver->irq_postinstall = ironlake_irq_postinstall; | |
3856 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
3857 | dev->driver->enable_vblank = ironlake_enable_vblank; | |
3858 | dev->driver->disable_vblank = ironlake_disable_vblank; | |
82a28bcf | 3859 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; |
f71d4af4 | 3860 | } else { |
c2798b19 CW |
3861 | if (INTEL_INFO(dev)->gen == 2) { |
3862 | dev->driver->irq_preinstall = i8xx_irq_preinstall; | |
3863 | dev->driver->irq_postinstall = i8xx_irq_postinstall; | |
3864 | dev->driver->irq_handler = i8xx_irq_handler; | |
3865 | dev->driver->irq_uninstall = i8xx_irq_uninstall; | |
a266c7d5 CW |
3866 | } else if (INTEL_INFO(dev)->gen == 3) { |
3867 | dev->driver->irq_preinstall = i915_irq_preinstall; | |
3868 | dev->driver->irq_postinstall = i915_irq_postinstall; | |
3869 | dev->driver->irq_uninstall = i915_irq_uninstall; | |
3870 | dev->driver->irq_handler = i915_irq_handler; | |
20afbda2 | 3871 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
c2798b19 | 3872 | } else { |
a266c7d5 CW |
3873 | dev->driver->irq_preinstall = i965_irq_preinstall; |
3874 | dev->driver->irq_postinstall = i965_irq_postinstall; | |
3875 | dev->driver->irq_uninstall = i965_irq_uninstall; | |
3876 | dev->driver->irq_handler = i965_irq_handler; | |
bac56d5b | 3877 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
c2798b19 | 3878 | } |
f71d4af4 JB |
3879 | dev->driver->enable_vblank = i915_enable_vblank; |
3880 | dev->driver->disable_vblank = i915_disable_vblank; | |
3881 | } | |
3882 | } | |
20afbda2 DV |
3883 | |
3884 | void intel_hpd_init(struct drm_device *dev) | |
3885 | { | |
3886 | struct drm_i915_private *dev_priv = dev->dev_private; | |
821450c6 EE |
3887 | struct drm_mode_config *mode_config = &dev->mode_config; |
3888 | struct drm_connector *connector; | |
b5ea2d56 | 3889 | unsigned long irqflags; |
821450c6 | 3890 | int i; |
20afbda2 | 3891 | |
821450c6 EE |
3892 | for (i = 1; i < HPD_NUM_PINS; i++) { |
3893 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
3894 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
3895 | } | |
3896 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
3897 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
3898 | connector->polled = intel_connector->polled; | |
3899 | if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE) | |
3900 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
3901 | } | |
b5ea2d56 DV |
3902 | |
3903 | /* Interrupt setup is already guaranteed to be single-threaded, this is | |
3904 | * just to make the assert_spin_locked checks happy. */ | |
3905 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
20afbda2 DV |
3906 | if (dev_priv->display.hpd_irq_setup) |
3907 | dev_priv->display.hpd_irq_setup(dev); | |
b5ea2d56 | 3908 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
20afbda2 | 3909 | } |
c67a470b PZ |
3910 | |
3911 | /* Disable interrupts so we can allow Package C8+. */ | |
3912 | void hsw_pc8_disable_interrupts(struct drm_device *dev) | |
3913 | { | |
3914 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3915 | unsigned long irqflags; | |
3916 | ||
3917 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3918 | ||
3919 | dev_priv->pc8.regsave.deimr = I915_READ(DEIMR); | |
3920 | dev_priv->pc8.regsave.sdeimr = I915_READ(SDEIMR); | |
3921 | dev_priv->pc8.regsave.gtimr = I915_READ(GTIMR); | |
3922 | dev_priv->pc8.regsave.gtier = I915_READ(GTIER); | |
3923 | dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR); | |
3924 | ||
1f2d4531 PZ |
3925 | ironlake_disable_display_irq(dev_priv, 0xffffffff); |
3926 | ibx_disable_display_interrupt(dev_priv, 0xffffffff); | |
c67a470b PZ |
3927 | ilk_disable_gt_irq(dev_priv, 0xffffffff); |
3928 | snb_disable_pm_irq(dev_priv, 0xffffffff); | |
3929 | ||
3930 | dev_priv->pc8.irqs_disabled = true; | |
3931 | ||
3932 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3933 | } | |
3934 | ||
3935 | /* Restore interrupts so we can recover from Package C8+. */ | |
3936 | void hsw_pc8_restore_interrupts(struct drm_device *dev) | |
3937 | { | |
3938 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3939 | unsigned long irqflags; | |
1f2d4531 | 3940 | uint32_t val; |
c67a470b PZ |
3941 | |
3942 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3943 | ||
3944 | val = I915_READ(DEIMR); | |
1f2d4531 | 3945 | WARN(val != 0xffffffff, "DEIMR is 0x%08x\n", val); |
c67a470b | 3946 | |
1f2d4531 PZ |
3947 | val = I915_READ(SDEIMR); |
3948 | WARN(val != 0xffffffff, "SDEIMR is 0x%08x\n", val); | |
c67a470b PZ |
3949 | |
3950 | val = I915_READ(GTIMR); | |
1f2d4531 | 3951 | WARN(val != 0xffffffff, "GTIMR is 0x%08x\n", val); |
c67a470b PZ |
3952 | |
3953 | val = I915_READ(GEN6_PMIMR); | |
1f2d4531 | 3954 | WARN(val != 0xffffffff, "GEN6_PMIMR is 0x%08x\n", val); |
c67a470b PZ |
3955 | |
3956 | dev_priv->pc8.irqs_disabled = false; | |
3957 | ||
3958 | ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr); | |
1f2d4531 | 3959 | ibx_enable_display_interrupt(dev_priv, ~dev_priv->pc8.regsave.sdeimr); |
c67a470b PZ |
3960 | ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr); |
3961 | snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr); | |
3962 | I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier); | |
3963 | ||
3964 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3965 | } |