]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blame - drivers/gpu/drm/i915/i915_irq.c
projects / mirror_ubuntu-jammy-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: use gmbus irq to wait for gmbus idle
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/i915_drm.h>
1da177e4 35#include "i915_drv.h"
1c5d22f7 36#include "i915_trace.h"
79e53945 37#include "intel_drv.h"
1da177e4 38
036a4a7d 39/* For display hotplug interrupt */
995b6762 40static void
f2b115e6 41ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 42{
1ec14ad3
CW		 43 if ((dev_priv->irq_mask & mask) != 0) {
44 dev_priv->irq_mask &= ~mask;
45 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 46 POSTING_READ(DEIMR);
036a4a7d
ZW		 47 }
48}
49
50static inline void
f2b115e6 51ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 52{
1ec14ad3
CW		 53 if ((dev_priv->irq_mask & mask) != mask) {
54 dev_priv->irq_mask |= mask;
55 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 56 POSTING_READ(DEIMR);
036a4a7d
ZW		 57 }
58}
59
7c463586
KP		 60void
61i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
62{
63 if ((dev_priv->pipestat[pipe] & mask) != mask) {
9db4a9c7 64 u32 reg = PIPESTAT(pipe);
7c463586
KP		 65
66 dev_priv->pipestat[pipe] |= mask;
67 /* Enable the interrupt, clear any pending status */
68 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
3143a2bf 69 POSTING_READ(reg);
7c463586
KP		 70 }
71}
72
73void
74i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
75{
76 if ((dev_priv->pipestat[pipe] & mask) != 0) {
9db4a9c7 77 u32 reg = PIPESTAT(pipe);
7c463586
KP		 78
79 dev_priv->pipestat[pipe] &= ~mask;
80 I915_WRITE(reg, dev_priv->pipestat[pipe]);
3143a2bf 81 POSTING_READ(reg);
7c463586
KP		 82 }
83}
84
01c66889
ZY		 85/**
86 * intel_enable_asle - enable ASLE interrupt for OpRegion
87 */
1ec14ad3 88void intel_enable_asle(struct drm_device *dev)
01c66889 89{
1ec14ad3
CW		 90 drm_i915_private_t *dev_priv = dev->dev_private;
91 unsigned long irqflags;
92
7e231dbe
JB		 93 /* FIXME: opregion/asle for VLV */
94 if (IS_VALLEYVIEW(dev))
95 return;
96
1ec14ad3 97 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 98
c619eed4 99 if (HAS_PCH_SPLIT(dev))
f2b115e6 100 ironlake_enable_display_irq(dev_priv, DE_GSE);
edcb49ca 101 else {
01c66889 102 i915_enable_pipestat(dev_priv, 1,
d874bcff 103 PIPE_LEGACY_BLC_EVENT_ENABLE);
a6c45cf0 104 if (INTEL_INFO(dev)->gen >= 4)
edcb49ca 105 i915_enable_pipestat(dev_priv, 0,
d874bcff 106 PIPE_LEGACY_BLC_EVENT_ENABLE);
edcb49ca 107 }
1ec14ad3
CW		 108
109 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 110}
111
0a3e67a4
JB		 112/**
113 * i915_pipe_enabled - check if a pipe is enabled
114 * @dev: DRM device
115 * @pipe: pipe to check
116 *
117 * Reading certain registers when the pipe is disabled can hang the chip.
118 * Use this routine to make sure the PLL is running and the pipe is active
119 * before reading such registers if unsure.
120 */
121static int
122i915_pipe_enabled(struct drm_device *dev, int pipe)
123{
124 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
702e7a56
PZ		 125 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
126 pipe);
127
128 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
0a3e67a4
JB		 129}
130
42f52ef8
KP		 131/* Called from drm generic code, passed a 'crtc', which
132 * we use as a pipe index
133 */
f71d4af4 134static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 135{
136 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
137 unsigned long high_frame;
138 unsigned long low_frame;
5eddb70b 139 u32 high1, high2, low;
0a3e67a4
JB		 140
141 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 142 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 143 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 144 return 0;
145 }
146
9db4a9c7
JB		 147 high_frame = PIPEFRAME(pipe);
148 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 149
0a3e67a4
JB		 150 /*
151 * High & low register fields aren't synchronized, so make sure
152 * we get a low value that's stable across two reads of the high
153 * register.
154 */
155 do {
5eddb70b
CW		 156 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
157 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
158 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 159 } while (high1 != high2);
160
5eddb70b
CW		 161 high1 >>= PIPE_FRAME_HIGH_SHIFT;
162 low >>= PIPE_FRAME_LOW_SHIFT;
163 return (high1 << 8) | low;
0a3e67a4
JB		 164}
165
f71d4af4 166static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 167{
168 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 169 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 170
171 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 172 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 173 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 174 return 0;
175 }
176
177 return I915_READ(reg);
178}
179
f71d4af4 180static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 181 int *vpos, int *hpos)
182{
183 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
184 u32 vbl = 0, position = 0;
185 int vbl_start, vbl_end, htotal, vtotal;
186 bool in_vbl = true;
187 int ret = 0;
fe2b8f9d
PZ		 188 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
189 pipe);
0af7e4df
MK		 190
191 if (!i915_pipe_enabled(dev, pipe)) {
192 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 193 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 194 return 0;
195 }
196
197 /* Get vtotal. */
fe2b8f9d 198 vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 199
200 if (INTEL_INFO(dev)->gen >= 4) {
201 /* No obvious pixelcount register. Only query vertical
202 * scanout position from Display scan line register.
203 */
204 position = I915_READ(PIPEDSL(pipe));
205
206 /* Decode into vertical scanout position. Don't have
207 * horizontal scanout position.
208 */
209 *vpos = position & 0x1fff;
210 *hpos = 0;
211 } else {
212 /* Have access to pixelcount since start of frame.
213 * We can split this into vertical and horizontal
214 * scanout position.
215 */
216 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
217
fe2b8f9d 218 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 219 *vpos = position / htotal;
220 *hpos = position - (*vpos * htotal);
221 }
222
223 /* Query vblank area. */
fe2b8f9d 224 vbl = I915_READ(VBLANK(cpu_transcoder));
0af7e4df
MK		 225
226 /* Test position against vblank region. */
227 vbl_start = vbl & 0x1fff;
228 vbl_end = (vbl >> 16) & 0x1fff;
229
230 if ((*vpos < vbl_start) || (*vpos > vbl_end))
231 in_vbl = false;
232
233 /* Inside "upper part" of vblank area? Apply corrective offset: */
234 if (in_vbl && (*vpos >= vbl_start))
235 *vpos = *vpos - vtotal;
236
237 /* Readouts valid? */
238 if (vbl > 0)
239 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
240
241 /* In vblank? */
242 if (in_vbl)
243 ret |= DRM_SCANOUTPOS_INVBL;
244
245 return ret;
246}
247
f71d4af4 248static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 249 int *max_error,
250 struct timeval *vblank_time,
251 unsigned flags)
252{
4041b853
CW		 253 struct drm_i915_private *dev_priv = dev->dev_private;
254 struct drm_crtc *crtc;
0af7e4df 255
4041b853
CW		 256 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
257 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 258 return -EINVAL;
259 }
260
261 /* Get drm_crtc to timestamp: */
4041b853
CW		 262 crtc = intel_get_crtc_for_pipe(dev, pipe);
263 if (crtc == NULL) {
264 DRM_ERROR("Invalid crtc %d\n", pipe);
265 return -EINVAL;
266 }
267
268 if (!crtc->enabled) {
269 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
270 return -EBUSY;
271 }
0af7e4df
MK		 272
273 /* Helper routine in DRM core does all the work: */
4041b853
CW		 274 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
275 vblank_time, flags,
276 crtc);
0af7e4df
MK		 277}
278
5ca58282
JB		 279/*
280 * Handle hotplug events outside the interrupt handler proper.
281 */
282static void i915_hotplug_work_func(struct work_struct *work)
283{
284 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
285 hotplug_work);
286 struct drm_device *dev = dev_priv->dev;
c31c4ba3 287 struct drm_mode_config *mode_config = &dev->mode_config;
4ef69c7a
CW		 288 struct intel_encoder *encoder;
289
52d7eced
DV		 290 /* HPD irq before everything is fully set up. */
291 if (!dev_priv->enable_hotplug_processing)
292 return;
293
a65e34c7 294 mutex_lock(&mode_config->mutex);
e67189ab
JB		 295 DRM_DEBUG_KMS("running encoder hotplug functions\n");
296
4ef69c7a
CW		 297 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
298 if (encoder->hot_plug)
299 encoder->hot_plug(encoder);
300
40ee3381
KP		 301 mutex_unlock(&mode_config->mutex);
302
5ca58282 303 /* Just fire off a uevent and let userspace tell us what to do */
eb1f8e4f 304 drm_helper_hpd_irq_event(dev);
5ca58282
JB		 305}
306
73edd18f 307static void ironlake_handle_rps_change(struct drm_device *dev)
f97108d1
JB		 308{
309 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 310 u32 busy_up, busy_down, max_avg, min_avg;
9270388e
DV		 311 u8 new_delay;
312 unsigned long flags;
313
314 spin_lock_irqsave(&mchdev_lock, flags);
f97108d1 315
73edd18f
DV		 316 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
317
20e4d407 318 new_delay = dev_priv->ips.cur_delay;
9270388e 319
7648fa99 320 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 321 busy_up = I915_READ(RCPREVBSYTUPAVG);
322 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 323 max_avg = I915_READ(RCBMAXAVG);
324 min_avg = I915_READ(RCBMINAVG);
325
326 /* Handle RCS change request from hw */
b5b72e89 327 if (busy_up > max_avg) {
20e4d407
DV		 328 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
329 new_delay = dev_priv->ips.cur_delay - 1;
330 if (new_delay < dev_priv->ips.max_delay)
331 new_delay = dev_priv->ips.max_delay;
b5b72e89 332 } else if (busy_down < min_avg) {
20e4d407
DV		 333 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
334 new_delay = dev_priv->ips.cur_delay + 1;
335 if (new_delay > dev_priv->ips.min_delay)
336 new_delay = dev_priv->ips.min_delay;
f97108d1
JB		 337 }
338
7648fa99 339 if (ironlake_set_drps(dev, new_delay))
20e4d407 340 dev_priv->ips.cur_delay = new_delay;
f97108d1 341
9270388e
DV		 342 spin_unlock_irqrestore(&mchdev_lock, flags);
343
f97108d1
JB		 344 return;
345}
346
549f7365
CW		 347static void notify_ring(struct drm_device *dev,
348 struct intel_ring_buffer *ring)
349{
350 struct drm_i915_private *dev_priv = dev->dev_private;
9862e600 351
475553de
CW		 352 if (ring->obj == NULL)
353 return;
354
b2eadbc8 355 trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
9862e600 356
549f7365 357 wake_up_all(&ring->irq_queue);
3e0dc6b0
BW		 358 if (i915_enable_hangcheck) {
359 dev_priv->hangcheck_count = 0;
360 mod_timer(&dev_priv->hangcheck_timer,
cecc21fe 361 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
3e0dc6b0 362 }
549f7365
CW		 363}
364
4912d041 365static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 366{
4912d041 367 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
c6a828d3 368 rps.work);
4912d041 369 u32 pm_iir, pm_imr;
7b9e0ae6 370 u8 new_delay;
4912d041 371
c6a828d3
DV		 372 spin_lock_irq(&dev_priv->rps.lock);
373 pm_iir = dev_priv->rps.pm_iir;
374 dev_priv->rps.pm_iir = 0;
4912d041 375 pm_imr = I915_READ(GEN6_PMIMR);
a9e2641d 376 I915_WRITE(GEN6_PMIMR, 0);
c6a828d3 377 spin_unlock_irq(&dev_priv->rps.lock);
3b8d8d91 378
7b9e0ae6 379 if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
3b8d8d91
JB		 380 return;
381
4fc688ce 382 mutex_lock(&dev_priv->rps.hw_lock);
7b9e0ae6
CW		 383
384 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
c6a828d3 385 new_delay = dev_priv->rps.cur_delay + 1;
7b9e0ae6 386 else
c6a828d3 387 new_delay = dev_priv->rps.cur_delay - 1;
3b8d8d91 388
79249636
BW		 389 /* sysfs frequency interfaces may have snuck in while servicing the
390 * interrupt
391 */
392 if (!(new_delay > dev_priv->rps.max_delay ||
393 new_delay < dev_priv->rps.min_delay)) {
394 gen6_set_rps(dev_priv->dev, new_delay);
395 }
3b8d8d91 396
4fc688ce 397 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91
JB		 398}
399
e3689190
BW		 400
401/**
402 * ivybridge_parity_work - Workqueue called when a parity error interrupt
403 * occurred.
404 * @work: workqueue struct
405 *
406 * Doesn't actually do anything except notify userspace. As a consequence of
407 * this event, userspace should try to remap the bad rows since statistically
408 * it is likely the same row is more likely to go bad again.
409 */
410static void ivybridge_parity_work(struct work_struct *work)
411{
412 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
a4da4fa4 413 l3_parity.error_work);
e3689190
BW		 414 u32 error_status, row, bank, subbank;
415 char *parity_event[5];
416 uint32_t misccpctl;
417 unsigned long flags;
418
419 /* We must turn off DOP level clock gating to access the L3 registers.
420 * In order to prevent a get/put style interface, acquire struct mutex
421 * any time we access those registers.
422 */
423 mutex_lock(&dev_priv->dev->struct_mutex);
424
425 misccpctl = I915_READ(GEN7_MISCCPCTL);
426 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
427 POSTING_READ(GEN7_MISCCPCTL);
428
429 error_status = I915_READ(GEN7_L3CDERRST1);
430 row = GEN7_PARITY_ERROR_ROW(error_status);
431 bank = GEN7_PARITY_ERROR_BANK(error_status);
432 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
433
434 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
435 GEN7_L3CDERRST1_ENABLE);
436 POSTING_READ(GEN7_L3CDERRST1);
437
438 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
439
440 spin_lock_irqsave(&dev_priv->irq_lock, flags);
441 dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
442 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
443 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
444
445 mutex_unlock(&dev_priv->dev->struct_mutex);
446
447 parity_event[0] = "L3_PARITY_ERROR=1";
448 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
449 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
450 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
451 parity_event[4] = NULL;
452
453 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
454 KOBJ_CHANGE, parity_event);
455
456 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
457 row, bank, subbank);
458
459 kfree(parity_event[3]);
460 kfree(parity_event[2]);
461 kfree(parity_event[1]);
462}
463
d2ba8470 464static void ivybridge_handle_parity_error(struct drm_device *dev)
e3689190
BW		 465{
466 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
467 unsigned long flags;
468
e1ef7cc2 469 if (!HAS_L3_GPU_CACHE(dev))
e3689190
BW		 470 return;
471
472 spin_lock_irqsave(&dev_priv->irq_lock, flags);
473 dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
474 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
475 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
476
a4da4fa4 477 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
e3689190
BW		 478}
479
e7b4c6b1
DV		 480static void snb_gt_irq_handler(struct drm_device *dev,
481 struct drm_i915_private *dev_priv,
482 u32 gt_iir)
483{
484
485 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
486 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
487 notify_ring(dev, &dev_priv->ring[RCS]);
488 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
489 notify_ring(dev, &dev_priv->ring[VCS]);
490 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
491 notify_ring(dev, &dev_priv->ring[BCS]);
492
493 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
494 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
495 GT_RENDER_CS_ERROR_INTERRUPT)) {
496 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
497 i915_handle_error(dev, false);
498 }
e3689190
BW		 499
500 if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
501 ivybridge_handle_parity_error(dev);
e7b4c6b1
DV		 502}
503
fc6826d1
CW		 504static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
505 u32 pm_iir)
506{
507 unsigned long flags;
508
509 /*
510 * IIR bits should never already be set because IMR should
511 * prevent an interrupt from being shown in IIR. The warning
512 * displays a case where we've unsafely cleared
c6a828d3 513 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
fc6826d1
CW		 514 * type is not a problem, it displays a problem in the logic.
515 *
c6a828d3 516 * The mask bit in IMR is cleared by dev_priv->rps.work.
fc6826d1
CW		 517 */
518
c6a828d3 519 spin_lock_irqsave(&dev_priv->rps.lock, flags);
c6a828d3
DV		 520 dev_priv->rps.pm_iir |= pm_iir;
521 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
fc6826d1 522 POSTING_READ(GEN6_PMIMR);
c6a828d3 523 spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
fc6826d1 524
c6a828d3 525 queue_work(dev_priv->wq, &dev_priv->rps.work);
fc6826d1
CW		 526}
527
515ac2bb
DV		 528static void gmbus_irq_handler(struct drm_device *dev)
529{
28c70f16
DV		 530 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
531
515ac2bb 532 DRM_DEBUG_DRIVER("GMBUS interrupt\n");
28c70f16
DV		 533
534 wake_up_all(&dev_priv->gmbus_wait_queue);
515ac2bb
DV		 535}
536
ff1f525e 537static irqreturn_t valleyview_irq_handler(int irq, void *arg)
7e231dbe
JB		 538{
539 struct drm_device *dev = (struct drm_device *) arg;
540 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
541 u32 iir, gt_iir, pm_iir;
542 irqreturn_t ret = IRQ_NONE;
543 unsigned long irqflags;
544 int pipe;
545 u32 pipe_stats[I915_MAX_PIPES];
7e231dbe
JB		 546
547 atomic_inc(&dev_priv->irq_received);
548
7e231dbe
JB		 549 while (true) {
550 iir = I915_READ(VLV_IIR);
551 gt_iir = I915_READ(GTIIR);
552 pm_iir = I915_READ(GEN6_PMIIR);
553
554 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
555 goto out;
556
557 ret = IRQ_HANDLED;
558
e7b4c6b1 559 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 560
561 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
562 for_each_pipe(pipe) {
563 int reg = PIPESTAT(pipe);
564 pipe_stats[pipe] = I915_READ(reg);
565
566 /*
567 * Clear the PIPE*STAT regs before the IIR
568 */
569 if (pipe_stats[pipe] & 0x8000ffff) {
570 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
571 DRM_DEBUG_DRIVER("pipe %c underrun\n",
572 pipe_name(pipe));
573 I915_WRITE(reg, pipe_stats[pipe]);
574 }
575 }
576 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
577
31acc7f5
JB		 578 for_each_pipe(pipe) {
579 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
580 drm_handle_vblank(dev, pipe);
581
582 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
583 intel_prepare_page_flip(dev, pipe);
584 intel_finish_page_flip(dev, pipe);
585 }
586 }
587
7e231dbe
JB		 588 /* Consume port. Then clear IIR or we'll miss events */
589 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
590 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
591
592 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
593 hotplug_status);
594 if (hotplug_status & dev_priv->hotplug_supported_mask)
595 queue_work(dev_priv->wq,
596 &dev_priv->hotplug_work);
597
598 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
599 I915_READ(PORT_HOTPLUG_STAT);
600 }
601
515ac2bb
DV		 602 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
603 gmbus_irq_handler(dev);
604
fc6826d1
CW		 605 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
606 gen6_queue_rps_work(dev_priv, pm_iir);
7e231dbe
JB		 607
608 I915_WRITE(GTIIR, gt_iir);
609 I915_WRITE(GEN6_PMIIR, pm_iir);
610 I915_WRITE(VLV_IIR, iir);
611 }
612
613out:
614 return ret;
615}
616
23e81d69 617static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 618{
619 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 620 int pipe;
776ad806 621
76e43830
DV		 622 if (pch_iir & SDE_HOTPLUG_MASK)
623 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
624
776ad806
JB		 625 if (pch_iir & SDE_AUDIO_POWER_MASK)
626 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
627 (pch_iir & SDE_AUDIO_POWER_MASK) >>
628 SDE_AUDIO_POWER_SHIFT);
629
630 if (pch_iir & SDE_GMBUS)
515ac2bb 631 gmbus_irq_handler(dev);
776ad806
JB		 632
633 if (pch_iir & SDE_AUDIO_HDCP_MASK)
634 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
635
636 if (pch_iir & SDE_AUDIO_TRANS_MASK)
637 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
638
639 if (pch_iir & SDE_POISON)
640 DRM_ERROR("PCH poison interrupt\n");
641
9db4a9c7
JB		 642 if (pch_iir & SDE_FDI_MASK)
643 for_each_pipe(pipe)
644 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
645 pipe_name(pipe),
646 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 647
648 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
649 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
650
651 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
652 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
653
654 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
655 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
656 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
657 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
658}
659
23e81d69
AJ		 660static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
661{
662 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
663 int pipe;
664
76e43830
DV		 665 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
666 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
667
23e81d69
AJ		 668 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
669 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
670 (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
671 SDE_AUDIO_POWER_SHIFT_CPT);
672
673 if (pch_iir & SDE_AUX_MASK_CPT)
674 DRM_DEBUG_DRIVER("AUX channel interrupt\n");
675
676 if (pch_iir & SDE_GMBUS_CPT)
515ac2bb 677 gmbus_irq_handler(dev);
23e81d69
AJ		 678
679 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
680 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
681
682 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
683 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
684
685 if (pch_iir & SDE_FDI_MASK_CPT)
686 for_each_pipe(pipe)
687 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
688 pipe_name(pipe),
689 I915_READ(FDI_RX_IIR(pipe)));
690}
691
ff1f525e 692static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
b1f14ad0
JB		 693{
694 struct drm_device *dev = (struct drm_device *) arg;
695 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
0e43406b
CW		 696 u32 de_iir, gt_iir, de_ier, pm_iir;
697 irqreturn_t ret = IRQ_NONE;
698 int i;
b1f14ad0
JB		 699
700 atomic_inc(&dev_priv->irq_received);
701
702 /* disable master interrupt before clearing iir */
703 de_ier = I915_READ(DEIER);
704 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
b1f14ad0 705
b1f14ad0 706 gt_iir = I915_READ(GTIIR);
0e43406b
CW		 707 if (gt_iir) {
708 snb_gt_irq_handler(dev, dev_priv, gt_iir);
709 I915_WRITE(GTIIR, gt_iir);
710 ret = IRQ_HANDLED;
b1f14ad0
JB		 711 }
712
0e43406b
CW		 713 de_iir = I915_READ(DEIIR);
714 if (de_iir) {
715 if (de_iir & DE_GSE_IVB)
716 intel_opregion_gse_intr(dev);
717
718 for (i = 0; i < 3; i++) {
74d44445
DV		 719 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
720 drm_handle_vblank(dev, i);
0e43406b
CW		 721 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
722 intel_prepare_page_flip(dev, i);
723 intel_finish_page_flip_plane(dev, i);
724 }
0e43406b 725 }
b615b57a 726
0e43406b
CW		 727 /* check event from PCH */
728 if (de_iir & DE_PCH_EVENT_IVB) {
729 u32 pch_iir = I915_READ(SDEIIR);
b1f14ad0 730
23e81d69 731 cpt_irq_handler(dev, pch_iir);
b1f14ad0 732
0e43406b
CW		 733 /* clear PCH hotplug event before clear CPU irq */
734 I915_WRITE(SDEIIR, pch_iir);
735 }
b615b57a 736
0e43406b
CW		 737 I915_WRITE(DEIIR, de_iir);
738 ret = IRQ_HANDLED;
b1f14ad0
JB		 739 }
740
0e43406b
CW		 741 pm_iir = I915_READ(GEN6_PMIIR);
742 if (pm_iir) {
743 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
744 gen6_queue_rps_work(dev_priv, pm_iir);
745 I915_WRITE(GEN6_PMIIR, pm_iir);
746 ret = IRQ_HANDLED;
747 }
b1f14ad0 748
b1f14ad0
JB		 749 I915_WRITE(DEIER, de_ier);
750 POSTING_READ(DEIER);
751
752 return ret;
753}
754
e7b4c6b1
DV		 755static void ilk_gt_irq_handler(struct drm_device *dev,
756 struct drm_i915_private *dev_priv,
757 u32 gt_iir)
758{
759 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
760 notify_ring(dev, &dev_priv->ring[RCS]);
761 if (gt_iir & GT_BSD_USER_INTERRUPT)
762 notify_ring(dev, &dev_priv->ring[VCS]);
763}
764
ff1f525e 765static irqreturn_t ironlake_irq_handler(int irq, void *arg)
036a4a7d 766{
4697995b 767 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 768 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
769 int ret = IRQ_NONE;
acd15b6c 770 u32 de_iir, gt_iir, de_ier, pm_iir;
881f47b6 771
4697995b
JB		 772 atomic_inc(&dev_priv->irq_received);
773
2d109a84
ZN		 774 /* disable master interrupt before clearing iir */
775 de_ier = I915_READ(DEIER);
776 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 777 POSTING_READ(DEIER);
2d109a84 778
036a4a7d
ZW		 779 de_iir = I915_READ(DEIIR);
780 gt_iir = I915_READ(GTIIR);
3b8d8d91 781 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 782
acd15b6c 783 if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 784 goto done;
036a4a7d 785
c7c85101 786 ret = IRQ_HANDLED;
036a4a7d 787
e7b4c6b1
DV		 788 if (IS_GEN5(dev))
789 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
790 else
791 snb_gt_irq_handler(dev, dev_priv, gt_iir);
01c66889 792
c7c85101 793 if (de_iir & DE_GSE)
3b617967 794 intel_opregion_gse_intr(dev);
c650156a 795
74d44445
DV		 796 if (de_iir & DE_PIPEA_VBLANK)
797 drm_handle_vblank(dev, 0);
798
799 if (de_iir & DE_PIPEB_VBLANK)
800 drm_handle_vblank(dev, 1);
801
f072d2e7 802 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 803 intel_prepare_page_flip(dev, 0);
2bbda389 804 intel_finish_page_flip_plane(dev, 0);
f072d2e7 805 }
013d5aa2 806
f072d2e7 807 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 808 intel_prepare_page_flip(dev, 1);
2bbda389 809 intel_finish_page_flip_plane(dev, 1);
f072d2e7 810 }
013d5aa2 811
c7c85101 812 /* check event from PCH */
776ad806 813 if (de_iir & DE_PCH_EVENT) {
acd15b6c
DV		 814 u32 pch_iir = I915_READ(SDEIIR);
815
23e81d69
AJ		 816 if (HAS_PCH_CPT(dev))
817 cpt_irq_handler(dev, pch_iir);
818 else
819 ibx_irq_handler(dev, pch_iir);
acd15b6c
DV		 820
821 /* should clear PCH hotplug event before clear CPU irq */
822 I915_WRITE(SDEIIR, pch_iir);
776ad806 823 }
036a4a7d 824
73edd18f
DV		 825 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
826 ironlake_handle_rps_change(dev);
f97108d1 827
fc6826d1
CW		 828 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
829 gen6_queue_rps_work(dev_priv, pm_iir);
3b8d8d91 830
c7c85101
ZN		 831 I915_WRITE(GTIIR, gt_iir);
832 I915_WRITE(DEIIR, de_iir);
4912d041 833 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 834
835done:
2d109a84 836 I915_WRITE(DEIER, de_ier);
3143a2bf 837 POSTING_READ(DEIER);
2d109a84 838
036a4a7d
ZW		 839 return ret;
840}
841
8a905236
JB		 842/**
843 * i915_error_work_func - do process context error handling work
844 * @work: work struct
845 *
846 * Fire an error uevent so userspace can see that a hang or error
847 * was detected.
848 */
849static void i915_error_work_func(struct work_struct *work)
850{
851 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
852 error_work);
853 struct drm_device *dev = dev_priv->dev;
f316a42c
BG		 854 char *error_event[] = { "ERROR=1", NULL };
855 char *reset_event[] = { "RESET=1", NULL };
856 char *reset_done_event[] = { "ERROR=0", NULL };
8a905236 857
f316a42c
BG		 858 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
859
ba1234d1 860 if (atomic_read(&dev_priv->mm.wedged)) {
f803aa55
CW		 861 DRM_DEBUG_DRIVER("resetting chip\n");
862 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
d4b8bb2a 863 if (!i915_reset(dev)) {
f803aa55
CW		 864 atomic_set(&dev_priv->mm.wedged, 0);
865 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
f316a42c 866 }
30dbf0c0 867 complete_all(&dev_priv->error_completion);
f316a42c 868 }
8a905236
JB		 869}
870
85f9e50d
DV		 871/* NB: please notice the memset */
872static void i915_get_extra_instdone(struct drm_device *dev,
873 uint32_t *instdone)
874{
875 struct drm_i915_private *dev_priv = dev->dev_private;
876 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
877
878 switch(INTEL_INFO(dev)->gen) {
879 case 2:
880 case 3:
881 instdone[0] = I915_READ(INSTDONE);
882 break;
883 case 4:
884 case 5:
885 case 6:
886 instdone[0] = I915_READ(INSTDONE_I965);
887 instdone[1] = I915_READ(INSTDONE1);
888 break;
889 default:
890 WARN_ONCE(1, "Unsupported platform\n");
891 case 7:
892 instdone[0] = I915_READ(GEN7_INSTDONE_1);
893 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
894 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
895 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
896 break;
897 }
898}
899
3bd3c932 900#ifdef CONFIG_DEBUG_FS
9df30794 901static struct drm_i915_error_object *
bcfb2e28 902i915_error_object_create(struct drm_i915_private *dev_priv,
05394f39 903 struct drm_i915_gem_object *src)
9df30794
CW		 904{
905 struct drm_i915_error_object *dst;
9da3da66 906 int i, count;
e56660dd 907 u32 reloc_offset;
9df30794 908
05394f39 909 if (src == NULL || src->pages == NULL)
9df30794
CW		 910 return NULL;
911
9da3da66 912 count = src->base.size / PAGE_SIZE;
9df30794 913
9da3da66 914 dst = kmalloc(sizeof(*dst) + count * sizeof(u32 *), GFP_ATOMIC);
9df30794
CW		 915 if (dst == NULL)
916 return NULL;
917
05394f39 918 reloc_offset = src->gtt_offset;
9da3da66 919 for (i = 0; i < count; i++) {
788885ae 920 unsigned long flags;
e56660dd 921 void *d;
788885ae 922
e56660dd 923 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 924 if (d == NULL)
925 goto unwind;
e56660dd 926
788885ae 927 local_irq_save(flags);
74898d7e
DV		 928 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
929 src->has_global_gtt_mapping) {
172975aa
CW		 930 void __iomem *s;
931
932 /* Simply ignore tiling or any overlapping fence.
933 * It's part of the error state, and this hopefully
934 * captures what the GPU read.
935 */
936
937 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
938 reloc_offset);
939 memcpy_fromio(d, s, PAGE_SIZE);
940 io_mapping_unmap_atomic(s);
960e3564
CW		 941 } else if (src->stolen) {
942 unsigned long offset;
943
944 offset = dev_priv->mm.stolen_base;
945 offset += src->stolen->start;
946 offset += i << PAGE_SHIFT;
947
1a240d4d 948 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
172975aa 949 } else {
9da3da66 950 struct page *page;
172975aa
CW		 951 void *s;
952
9da3da66 953 page = i915_gem_object_get_page(src, i);
172975aa 954
9da3da66
CW		 955 drm_clflush_pages(&page, 1);
956
957 s = kmap_atomic(page);
172975aa
CW		 958 memcpy(d, s, PAGE_SIZE);
959 kunmap_atomic(s);
960
9da3da66 961 drm_clflush_pages(&page, 1);
172975aa 962 }
788885ae 963 local_irq_restore(flags);
e56660dd 964
9da3da66 965 dst->pages[i] = d;
e56660dd
CW		 966
967 reloc_offset += PAGE_SIZE;
9df30794 968 }
9da3da66 969 dst->page_count = count;
05394f39 970 dst->gtt_offset = src->gtt_offset;
9df30794
CW		 971
972 return dst;
973
974unwind:
9da3da66
CW		 975 while (i--)
976 kfree(dst->pages[i]);
9df30794
CW		 977 kfree(dst);
978 return NULL;
979}
980
981static void
982i915_error_object_free(struct drm_i915_error_object *obj)
983{
984 int page;
985
986 if (obj == NULL)
987 return;
988
989 for (page = 0; page < obj->page_count; page++)
990 kfree(obj->pages[page]);
991
992 kfree(obj);
993}
994
742cbee8
DV		 995void
996i915_error_state_free(struct kref *error_ref)
9df30794 997{
742cbee8
DV		 998 struct drm_i915_error_state *error = container_of(error_ref,
999 typeof(*error), ref);
e2f973d5
CW		 1000 int i;
1001
52d39a21
CW		 1002 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
1003 i915_error_object_free(error->ring[i].batchbuffer);
1004 i915_error_object_free(error->ring[i].ringbuffer);
1005 kfree(error->ring[i].requests);
1006 }
e2f973d5 1007
9df30794 1008 kfree(error->active_bo);
6ef3d427 1009 kfree(error->overlay);
9df30794
CW		 1010 kfree(error);
1011}
1b50247a
CW		 1012static void capture_bo(struct drm_i915_error_buffer *err,
1013 struct drm_i915_gem_object *obj)
1014{
1015 err->size = obj->base.size;
1016 err->name = obj->base.name;
0201f1ec
CW		 1017 err->rseqno = obj->last_read_seqno;
1018 err->wseqno = obj->last_write_seqno;
1b50247a
CW		 1019 err->gtt_offset = obj->gtt_offset;
1020 err->read_domains = obj->base.read_domains;
1021 err->write_domain = obj->base.write_domain;
1022 err->fence_reg = obj->fence_reg;
1023 err->pinned = 0;
1024 if (obj->pin_count > 0)
1025 err->pinned = 1;
1026 if (obj->user_pin_count > 0)
1027 err->pinned = -1;
1028 err->tiling = obj->tiling_mode;
1029 err->dirty = obj->dirty;
1030 err->purgeable = obj->madv != I915_MADV_WILLNEED;
1031 err->ring = obj->ring ? obj->ring->id : -1;
1032 err->cache_level = obj->cache_level;
1033}
9df30794 1034
1b50247a
CW		 1035static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1036 int count, struct list_head *head)
c724e8a9
CW		 1037{
1038 struct drm_i915_gem_object *obj;
1039 int i = 0;
1040
1041 list_for_each_entry(obj, head, mm_list) {
1b50247a 1042 capture_bo(err++, obj);
c724e8a9
CW		 1043 if (++i == count)
1044 break;
1b50247a
CW		 1045 }
1046
1047 return i;
1048}
1049
1050static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1051 int count, struct list_head *head)
1052{
1053 struct drm_i915_gem_object *obj;
1054 int i = 0;
1055
1056 list_for_each_entry(obj, head, gtt_list) {
1057 if (obj->pin_count == 0)
1058 continue;
c724e8a9 1059
1b50247a
CW		 1060 capture_bo(err++, obj);
1061 if (++i == count)
1062 break;
c724e8a9
CW		 1063 }
1064
1065 return i;
1066}
1067
748ebc60
CW		 1068static void i915_gem_record_fences(struct drm_device *dev,
1069 struct drm_i915_error_state *error)
1070{
1071 struct drm_i915_private *dev_priv = dev->dev_private;
1072 int i;
1073
1074 /* Fences */
1075 switch (INTEL_INFO(dev)->gen) {
775d17b6 1076 case 7:
748ebc60
CW		 1077 case 6:
1078 for (i = 0; i < 16; i++)
1079 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1080 break;
1081 case 5:
1082 case 4:
1083 for (i = 0; i < 16; i++)
1084 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1085 break;
1086 case 3:
1087 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1088 for (i = 0; i < 8; i++)
1089 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1090 case 2:
1091 for (i = 0; i < 8; i++)
1092 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1093 break;
1094
1095 }
1096}
1097
bcfb2e28
CW		 1098static struct drm_i915_error_object *
1099i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1100 struct intel_ring_buffer *ring)
1101{
1102 struct drm_i915_gem_object *obj;
1103 u32 seqno;
1104
1105 if (!ring->get_seqno)
1106 return NULL;
1107
b2eadbc8 1108 seqno = ring->get_seqno(ring, false);
bcfb2e28
CW		 1109 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1110 if (obj->ring != ring)
1111 continue;
1112
0201f1ec 1113 if (i915_seqno_passed(seqno, obj->last_read_seqno))
bcfb2e28
CW		 1114 continue;
1115
1116 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1117 continue;
1118
1119 /* We need to copy these to an anonymous buffer as the simplest
1120 * method to avoid being overwritten by userspace.
1121 */
1122 return i915_error_object_create(dev_priv, obj);
1123 }
1124
1125 return NULL;
1126}
1127
d27b1e0e
DV		 1128static void i915_record_ring_state(struct drm_device *dev,
1129 struct drm_i915_error_state *error,
1130 struct intel_ring_buffer *ring)
1131{
1132 struct drm_i915_private *dev_priv = dev->dev_private;
1133
33f3f518 1134 if (INTEL_INFO(dev)->gen >= 6) {
12f55818 1135 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
33f3f518 1136 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
7e3b8737
DV		 1137 error->semaphore_mboxes[ring->id][0]
1138 = I915_READ(RING_SYNC_0(ring->mmio_base));
1139 error->semaphore_mboxes[ring->id][1]
1140 = I915_READ(RING_SYNC_1(ring->mmio_base));
df2b23d9
CW		 1141 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
1142 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
33f3f518 1143 }
c1cd90ed 1144
d27b1e0e 1145 if (INTEL_INFO(dev)->gen >= 4) {
9d2f41fa 1146 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
d27b1e0e
DV		 1147 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1148 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1149 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
c1cd90ed 1150 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
050ee91f 1151 if (ring->id == RCS)
d27b1e0e 1152 error->bbaddr = I915_READ64(BB_ADDR);
d27b1e0e 1153 } else {
9d2f41fa 1154 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
d27b1e0e
DV		 1155 error->ipeir[ring->id] = I915_READ(IPEIR);
1156 error->ipehr[ring->id] = I915_READ(IPEHR);
1157 error->instdone[ring->id] = I915_READ(INSTDONE);
d27b1e0e
DV		 1158 }
1159
9574b3fe 1160 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
c1cd90ed 1161 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
b2eadbc8 1162 error->seqno[ring->id] = ring->get_seqno(ring, false);
d27b1e0e 1163 error->acthd[ring->id] = intel_ring_get_active_head(ring);
c1cd90ed
DV		 1164 error->head[ring->id] = I915_READ_HEAD(ring);
1165 error->tail[ring->id] = I915_READ_TAIL(ring);
7e3b8737
DV		 1166
1167 error->cpu_ring_head[ring->id] = ring->head;
1168 error->cpu_ring_tail[ring->id] = ring->tail;
d27b1e0e
DV		 1169}
1170
52d39a21
CW		 1171static void i915_gem_record_rings(struct drm_device *dev,
1172 struct drm_i915_error_state *error)
1173{
1174 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 1175 struct intel_ring_buffer *ring;
52d39a21
CW		 1176 struct drm_i915_gem_request *request;
1177 int i, count;
1178
b4519513 1179 for_each_ring(ring, dev_priv, i) {
52d39a21
CW		 1180 i915_record_ring_state(dev, error, ring);
1181
1182 error->ring[i].batchbuffer =
1183 i915_error_first_batchbuffer(dev_priv, ring);
1184
1185 error->ring[i].ringbuffer =
1186 i915_error_object_create(dev_priv, ring->obj);
1187
1188 count = 0;
1189 list_for_each_entry(request, &ring->request_list, list)
1190 count++;
1191
1192 error->ring[i].num_requests = count;
1193 error->ring[i].requests =
1194 kmalloc(count*sizeof(struct drm_i915_error_request),
1195 GFP_ATOMIC);
1196 if (error->ring[i].requests == NULL) {
1197 error->ring[i].num_requests = 0;
1198 continue;
1199 }
1200
1201 count = 0;
1202 list_for_each_entry(request, &ring->request_list, list) {
1203 struct drm_i915_error_request *erq;
1204
1205 erq = &error->ring[i].requests[count++];
1206 erq->seqno = request->seqno;
1207 erq->jiffies = request->emitted_jiffies;
ee4f42b1 1208 erq->tail = request->tail;
52d39a21
CW		 1209 }
1210 }
1211}
1212
8a905236
JB		 1213/**
1214 * i915_capture_error_state - capture an error record for later analysis
1215 * @dev: drm device
1216 *
1217 * Should be called when an error is detected (either a hang or an error
1218 * interrupt) to capture error state from the time of the error. Fills
1219 * out a structure which becomes available in debugfs for user level tools
1220 * to pick up.
1221 */
63eeaf38
JB		 1222static void i915_capture_error_state(struct drm_device *dev)
1223{
1224 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1225 struct drm_i915_gem_object *obj;
63eeaf38
JB		 1226 struct drm_i915_error_state *error;
1227 unsigned long flags;
9db4a9c7 1228 int i, pipe;
63eeaf38
JB		 1229
1230 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1231 error = dev_priv->first_error;
1232 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1233 if (error)
1234 return;
63eeaf38 1235
9db4a9c7 1236 /* Account for pipe specific data like PIPE*STAT */
33f3f518 1237 error = kzalloc(sizeof(*error), GFP_ATOMIC);
63eeaf38 1238 if (!error) {
9df30794
CW		 1239 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1240 return;
63eeaf38
JB		 1241 }
1242
b6f7833b
CW		 1243 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1244 dev->primary->index);
2fa772f3 1245
742cbee8 1246 kref_init(&error->ref);
63eeaf38
JB		 1247 error->eir = I915_READ(EIR);
1248 error->pgtbl_er = I915_READ(PGTBL_ER);
b9a3906b 1249 error->ccid = I915_READ(CCID);
be998e2e
BW		 1250
1251 if (HAS_PCH_SPLIT(dev))
1252 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1253 else if (IS_VALLEYVIEW(dev))
1254 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1255 else if (IS_GEN2(dev))
1256 error->ier = I915_READ16(IER);
1257 else
1258 error->ier = I915_READ(IER);
1259
9db4a9c7
JB		 1260 for_each_pipe(pipe)
1261 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
d27b1e0e 1262
33f3f518 1263 if (INTEL_INFO(dev)->gen >= 6) {
f406839f 1264 error->error = I915_READ(ERROR_GEN6);
33f3f518
DV		 1265 error->done_reg = I915_READ(DONE_REG);
1266 }
d27b1e0e 1267
71e172e8
BW		 1268 if (INTEL_INFO(dev)->gen == 7)
1269 error->err_int = I915_READ(GEN7_ERR_INT);
1270
050ee91f
BW		 1271 i915_get_extra_instdone(dev, error->extra_instdone);
1272
748ebc60 1273 i915_gem_record_fences(dev, error);
52d39a21 1274 i915_gem_record_rings(dev, error);
9df30794 1275
c724e8a9 1276 /* Record buffers on the active and pinned lists. */
9df30794 1277 error->active_bo = NULL;
c724e8a9 1278 error->pinned_bo = NULL;
9df30794 1279
bcfb2e28
CW		 1280 i = 0;
1281 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1282 i++;
1283 error->active_bo_count = i;
6c085a72 1284 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
1b50247a
CW		 1285 if (obj->pin_count)
1286 i++;
bcfb2e28 1287 error->pinned_bo_count = i - error->active_bo_count;
c724e8a9 1288
8e934dbf
CW		 1289 error->active_bo = NULL;
1290 error->pinned_bo = NULL;
bcfb2e28
CW		 1291 if (i) {
1292 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
9df30794 1293 GFP_ATOMIC);
c724e8a9
CW		 1294 if (error->active_bo)
1295 error->pinned_bo =
1296 error->active_bo + error->active_bo_count;
9df30794
CW		 1297 }
1298
c724e8a9
CW		 1299 if (error->active_bo)
1300 error->active_bo_count =
1b50247a
CW		 1301 capture_active_bo(error->active_bo,
1302 error->active_bo_count,
1303 &dev_priv->mm.active_list);
c724e8a9
CW		 1304
1305 if (error->pinned_bo)
1306 error->pinned_bo_count =
1b50247a
CW		 1307 capture_pinned_bo(error->pinned_bo,
1308 error->pinned_bo_count,
6c085a72 1309 &dev_priv->mm.bound_list);
c724e8a9 1310
9df30794
CW		 1311 do_gettimeofday(&error->time);
1312
6ef3d427 1313 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 1314 error->display = intel_display_capture_error_state(dev);
6ef3d427 1315
9df30794
CW		 1316 spin_lock_irqsave(&dev_priv->error_lock, flags);
1317 if (dev_priv->first_error == NULL) {
1318 dev_priv->first_error = error;
1319 error = NULL;
1320 }
63eeaf38 1321 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1322
1323 if (error)
742cbee8 1324 i915_error_state_free(&error->ref);
9df30794
CW		 1325}
1326
1327void i915_destroy_error_state(struct drm_device *dev)
1328{
1329 struct drm_i915_private *dev_priv = dev->dev_private;
1330 struct drm_i915_error_state *error;
6dc0e816 1331 unsigned long flags;
9df30794 1332
6dc0e816 1333 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1334 error = dev_priv->first_error;
1335 dev_priv->first_error = NULL;
6dc0e816 1336 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1337
1338 if (error)
742cbee8 1339 kref_put(&error->ref, i915_error_state_free);
63eeaf38 1340}
3bd3c932
CW		 1341#else
1342#define i915_capture_error_state(x)
1343#endif
63eeaf38 1344
35aed2e6 1345static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1346{
1347 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 1348 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 1349 u32 eir = I915_READ(EIR);
050ee91f 1350 int pipe, i;
8a905236 1351
35aed2e6
CW		 1352 if (!eir)
1353 return;
8a905236 1354
a70491cc 1355 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 1356
bd9854f9
BW		 1357 i915_get_extra_instdone(dev, instdone);
1358
8a905236
JB		 1359 if (IS_G4X(dev)) {
1360 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1361 u32 ipeir = I915_READ(IPEIR_I965);
1362
a70491cc
JP		 1363 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1364 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 1365 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1366 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 1367 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1368 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1369 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1370 POSTING_READ(IPEIR_I965);
8a905236
JB		 1371 }
1372 if (eir & GM45_ERROR_PAGE_TABLE) {
1373 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1374 pr_err("page table error\n");
1375 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1376 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1377 POSTING_READ(PGTBL_ER);
8a905236
JB		 1378 }
1379 }
1380
a6c45cf0 1381 if (!IS_GEN2(dev)) {
8a905236
JB		 1382 if (eir & I915_ERROR_PAGE_TABLE) {
1383 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1384 pr_err("page table error\n");
1385 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1386 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1387 POSTING_READ(PGTBL_ER);
8a905236
JB		 1388 }
1389 }
1390
1391 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 1392 pr_err("memory refresh error:\n");
9db4a9c7 1393 for_each_pipe(pipe)
a70491cc 1394 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 1395 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 1396 /* pipestat has already been acked */
1397 }
1398 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 1399 pr_err("instruction error\n");
1400 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 1401 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1402 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 1403 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 1404 u32 ipeir = I915_READ(IPEIR);
1405
a70491cc
JP		 1406 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1407 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 1408 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 1409 I915_WRITE(IPEIR, ipeir);
3143a2bf 1410 POSTING_READ(IPEIR);
8a905236
JB		 1411 } else {
1412 u32 ipeir = I915_READ(IPEIR_I965);
1413
a70491cc
JP		 1414 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1415 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 1416 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1417 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1418 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1419 POSTING_READ(IPEIR_I965);
8a905236
JB		 1420 }
1421 }
1422
1423 I915_WRITE(EIR, eir);
3143a2bf 1424 POSTING_READ(EIR);
8a905236
JB		 1425 eir = I915_READ(EIR);
1426 if (eir) {
1427 /*
1428 * some errors might have become stuck,
1429 * mask them.
1430 */
1431 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1432 I915_WRITE(EMR, I915_READ(EMR) | eir);
1433 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1434 }
35aed2e6
CW		 1435}
1436
1437/**
1438 * i915_handle_error - handle an error interrupt
1439 * @dev: drm device
1440 *
1441 * Do some basic checking of regsiter state at error interrupt time and
1442 * dump it to the syslog. Also call i915_capture_error_state() to make
1443 * sure we get a record and make it available in debugfs. Fire a uevent
1444 * so userspace knows something bad happened (should trigger collection
1445 * of a ring dump etc.).
1446 */
527f9e90 1447void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 1448{
1449 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513
CW		 1450 struct intel_ring_buffer *ring;
1451 int i;
35aed2e6
CW		 1452
1453 i915_capture_error_state(dev);
1454 i915_report_and_clear_eir(dev);
8a905236 1455
ba1234d1 1456 if (wedged) {
30dbf0c0 1457 INIT_COMPLETION(dev_priv->error_completion);
ba1234d1
BG		 1458 atomic_set(&dev_priv->mm.wedged, 1);
1459
11ed50ec
BG		 1460 /*
1461 * Wakeup waiting processes so they don't hang
1462 */
b4519513
CW		 1463 for_each_ring(ring, dev_priv, i)
1464 wake_up_all(&ring->irq_queue);
11ed50ec
BG		 1465 }
1466
9c9fe1f8 1467 queue_work(dev_priv->wq, &dev_priv->error_work);
8a905236
JB		 1468}
1469
4e5359cd
SF		 1470static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1471{
1472 drm_i915_private_t *dev_priv = dev->dev_private;
1473 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 1475 struct drm_i915_gem_object *obj;
4e5359cd
SF		 1476 struct intel_unpin_work *work;
1477 unsigned long flags;
1478 bool stall_detected;
1479
1480 /* Ignore early vblank irqs */
1481 if (intel_crtc == NULL)
1482 return;
1483
1484 spin_lock_irqsave(&dev->event_lock, flags);
1485 work = intel_crtc->unpin_work;
1486
1487 if (work == NULL || work->pending || !work->enable_stall_check) {
1488 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1489 spin_unlock_irqrestore(&dev->event_lock, flags);
1490 return;
1491 }
1492
1493 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 1494 obj = work->pending_flip_obj;
a6c45cf0 1495 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 1496 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545
AR		 1497 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1498 obj->gtt_offset;
4e5359cd 1499 } else {
9db4a9c7 1500 int dspaddr = DSPADDR(intel_crtc->plane);
05394f39 1501 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
01f2c773 1502 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 1503 crtc->x * crtc->fb->bits_per_pixel/8);
1504 }
1505
1506 spin_unlock_irqrestore(&dev->event_lock, flags);
1507
1508 if (stall_detected) {
1509 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1510 intel_prepare_page_flip(dev, intel_crtc->plane);
1511 }
1512}
1513
42f52ef8
KP		 1514/* Called from drm generic code, passed 'crtc' which
1515 * we use as a pipe index
1516 */
f71d4af4 1517static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1518{
1519 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1520 unsigned long irqflags;
71e0ffa5 1521
5eddb70b 1522 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 1523 return -EINVAL;
0a3e67a4 1524
1ec14ad3 1525 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 1526 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 1527 i915_enable_pipestat(dev_priv, pipe,
1528 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 1529 else
7c463586
KP		 1530 i915_enable_pipestat(dev_priv, pipe,
1531 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 1532
1533 /* maintain vblank delivery even in deep C-states */
1534 if (dev_priv->info->gen == 3)
6b26c86d 1535 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 1536 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 1537
0a3e67a4
JB		 1538 return 0;
1539}
1540
f71d4af4 1541static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1542{
1543 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1544 unsigned long irqflags;
1545
1546 if (!i915_pipe_enabled(dev, pipe))
1547 return -EINVAL;
1548
1549 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1550 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1551 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
f796cf8f
JB		 1552 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1553
1554 return 0;
1555}
1556
f71d4af4 1557static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1558{
1559 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1560 unsigned long irqflags;
1561
1562 if (!i915_pipe_enabled(dev, pipe))
1563 return -EINVAL;
1564
1565 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1566 ironlake_enable_display_irq(dev_priv,
1567 DE_PIPEA_VBLANK_IVB << (5 * pipe));
b1f14ad0
JB		 1568 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1569
1570 return 0;
1571}
1572
7e231dbe
JB		 1573static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1574{
1575 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1576 unsigned long irqflags;
31acc7f5 1577 u32 imr;
7e231dbe
JB		 1578
1579 if (!i915_pipe_enabled(dev, pipe))
1580 return -EINVAL;
1581
1582 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7e231dbe 1583 imr = I915_READ(VLV_IMR);
31acc7f5 1584 if (pipe == 0)
7e231dbe 1585 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1586 else
7e231dbe 1587 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1588 I915_WRITE(VLV_IMR, imr);
31acc7f5
JB		 1589 i915_enable_pipestat(dev_priv, pipe,
1590 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe
JB		 1591 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1592
1593 return 0;
1594}
1595
42f52ef8
KP		 1596/* Called from drm generic code, passed 'crtc' which
1597 * we use as a pipe index
1598 */
f71d4af4 1599static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1600{
1601 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1602 unsigned long irqflags;
0a3e67a4 1603
1ec14ad3 1604 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 1605 if (dev_priv->info->gen == 3)
6b26c86d 1606 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 1607
f796cf8f
JB		 1608 i915_disable_pipestat(dev_priv, pipe,
1609 PIPE_VBLANK_INTERRUPT_ENABLE |
1610 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1611 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1612}
1613
f71d4af4 1614static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1615{
1616 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1617 unsigned long irqflags;
1618
1619 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1620 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1621 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1ec14ad3 1622 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 1623}
1624
f71d4af4 1625static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1626{
1627 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1628 unsigned long irqflags;
1629
1630 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1631 ironlake_disable_display_irq(dev_priv,
1632 DE_PIPEA_VBLANK_IVB << (pipe * 5));
b1f14ad0
JB		 1633 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1634}
1635
7e231dbe
JB		 1636static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1637{
1638 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1639 unsigned long irqflags;
31acc7f5 1640 u32 imr;
7e231dbe
JB		 1641
1642 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5
JB		 1643 i915_disable_pipestat(dev_priv, pipe,
1644 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe 1645 imr = I915_READ(VLV_IMR);
31acc7f5 1646 if (pipe == 0)
7e231dbe 1647 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1648 else
7e231dbe 1649 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1650 I915_WRITE(VLV_IMR, imr);
7e231dbe
JB		 1651 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1652}
1653
893eead0
CW		 1654static u32
1655ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 1656{
893eead0
CW		 1657 return list_entry(ring->request_list.prev,
1658 struct drm_i915_gem_request, list)->seqno;
1659}
1660
1661static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1662{
1663 if (list_empty(&ring->request_list) ||
b2eadbc8
CW		 1664 i915_seqno_passed(ring->get_seqno(ring, false),
1665 ring_last_seqno(ring))) {
893eead0 1666 /* Issue a wake-up to catch stuck h/w. */
9574b3fe
BW		 1667 if (waitqueue_active(&ring->irq_queue)) {
1668 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1669 ring->name);
893eead0
CW		 1670 wake_up_all(&ring->irq_queue);
1671 *err = true;
1672 }
1673 return true;
1674 }
1675 return false;
f65d9421
BG		 1676}
1677
1ec14ad3
CW		 1678static bool kick_ring(struct intel_ring_buffer *ring)
1679{
1680 struct drm_device *dev = ring->dev;
1681 struct drm_i915_private *dev_priv = dev->dev_private;
1682 u32 tmp = I915_READ_CTL(ring);
1683 if (tmp & RING_WAIT) {
1684 DRM_ERROR("Kicking stuck wait on %s\n",
1685 ring->name);
1686 I915_WRITE_CTL(ring, tmp);
1687 return true;
1688 }
1ec14ad3
CW		 1689 return false;
1690}
1691
d1e61e7f
CW		 1692static bool i915_hangcheck_hung(struct drm_device *dev)
1693{
1694 drm_i915_private_t *dev_priv = dev->dev_private;
1695
1696 if (dev_priv->hangcheck_count++ > 1) {
b4519513
CW		 1697 bool hung = true;
1698
d1e61e7f
CW		 1699 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1700 i915_handle_error(dev, true);
1701
1702 if (!IS_GEN2(dev)) {
b4519513
CW		 1703 struct intel_ring_buffer *ring;
1704 int i;
1705
d1e61e7f
CW		 1706 /* Is the chip hanging on a WAIT_FOR_EVENT?
1707 * If so we can simply poke the RB_WAIT bit
1708 * and break the hang. This should work on
1709 * all but the second generation chipsets.
1710 */
b4519513
CW		 1711 for_each_ring(ring, dev_priv, i)
1712 hung &= !kick_ring(ring);
d1e61e7f
CW		 1713 }
1714
b4519513 1715 return hung;
d1e61e7f
CW		 1716 }
1717
1718 return false;
1719}
1720
f65d9421
BG		 1721/**
1722 * This is called when the chip hasn't reported back with completed
1723 * batchbuffers in a long time. The first time this is called we simply record
1724 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1725 * again, we assume the chip is wedged and try to fix it.
1726 */
1727void i915_hangcheck_elapsed(unsigned long data)
1728{
1729 struct drm_device *dev = (struct drm_device *)data;
1730 drm_i915_private_t *dev_priv = dev->dev_private;
bd9854f9 1731 uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
b4519513
CW		 1732 struct intel_ring_buffer *ring;
1733 bool err = false, idle;
1734 int i;
893eead0 1735
3e0dc6b0
BW		 1736 if (!i915_enable_hangcheck)
1737 return;
1738
b4519513
CW		 1739 memset(acthd, 0, sizeof(acthd));
1740 idle = true;
1741 for_each_ring(ring, dev_priv, i) {
1742 idle &= i915_hangcheck_ring_idle(ring, &err);
1743 acthd[i] = intel_ring_get_active_head(ring);
1744 }
1745
893eead0 1746 /* If all work is done then ACTHD clearly hasn't advanced. */
b4519513 1747 if (idle) {
d1e61e7f
CW		 1748 if (err) {
1749 if (i915_hangcheck_hung(dev))
1750 return;
1751
893eead0 1752 goto repeat;
d1e61e7f
CW		 1753 }
1754
1755 dev_priv->hangcheck_count = 0;
893eead0
CW		 1756 return;
1757 }
b9201c14 1758
bd9854f9 1759 i915_get_extra_instdone(dev, instdone);
b4519513 1760 if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 &&
050ee91f 1761 memcmp(dev_priv->prev_instdone, instdone, sizeof(instdone)) == 0) {
d1e61e7f 1762 if (i915_hangcheck_hung(dev))
cbb465e7 1763 return;
cbb465e7
CW		 1764 } else {
1765 dev_priv->hangcheck_count = 0;
1766
b4519513 1767 memcpy(dev_priv->last_acthd, acthd, sizeof(acthd));
050ee91f 1768 memcpy(dev_priv->prev_instdone, instdone, sizeof(instdone));
cbb465e7 1769 }
f65d9421 1770
893eead0 1771repeat:
f65d9421 1772 /* Reset timer case chip hangs without another request being added */
b3b079db 1773 mod_timer(&dev_priv->hangcheck_timer,
cecc21fe 1774 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
f65d9421
BG		 1775}
1776
1da177e4
LT		 1777/* drm_dma.h hooks
1778*/
f71d4af4 1779static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 1780{
1781 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1782
4697995b
JB		 1783 atomic_set(&dev_priv->irq_received, 0);
1784
036a4a7d 1785 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 1786
036a4a7d
ZW		 1787 /* XXX hotplug from PCH */
1788
1789 I915_WRITE(DEIMR, 0xffffffff);
1790 I915_WRITE(DEIER, 0x0);
3143a2bf 1791 POSTING_READ(DEIER);
036a4a7d
ZW		 1792
1793 /* and GT */
1794 I915_WRITE(GTIMR, 0xffffffff);
1795 I915_WRITE(GTIER, 0x0);
3143a2bf 1796 POSTING_READ(GTIER);
c650156a
ZW		 1797
1798 /* south display irq */
1799 I915_WRITE(SDEIMR, 0xffffffff);
1800 I915_WRITE(SDEIER, 0x0);
3143a2bf 1801 POSTING_READ(SDEIER);
036a4a7d
ZW		 1802}
1803
7e231dbe
JB		 1804static void valleyview_irq_preinstall(struct drm_device *dev)
1805{
1806 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1807 int pipe;
1808
1809 atomic_set(&dev_priv->irq_received, 0);
1810
7e231dbe
JB		 1811 /* VLV magic */
1812 I915_WRITE(VLV_IMR, 0);
1813 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1814 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1815 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1816
7e231dbe
JB		 1817 /* and GT */
1818 I915_WRITE(GTIIR, I915_READ(GTIIR));
1819 I915_WRITE(GTIIR, I915_READ(GTIIR));
1820 I915_WRITE(GTIMR, 0xffffffff);
1821 I915_WRITE(GTIER, 0x0);
1822 POSTING_READ(GTIER);
1823
1824 I915_WRITE(DPINVGTT, 0xff);
1825
1826 I915_WRITE(PORT_HOTPLUG_EN, 0);
1827 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1828 for_each_pipe(pipe)
1829 I915_WRITE(PIPESTAT(pipe), 0xffff);
1830 I915_WRITE(VLV_IIR, 0xffffffff);
1831 I915_WRITE(VLV_IMR, 0xffffffff);
1832 I915_WRITE(VLV_IER, 0x0);
1833 POSTING_READ(VLV_IER);
1834}
1835
7fe0b973
KP		 1836/*
1837 * Enable digital hotplug on the PCH, and configure the DP short pulse
1838 * duration to 2ms (which is the minimum in the Display Port spec)
1839 *
1840 * This register is the same on all known PCH chips.
1841 */
1842
1843static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1844{
1845 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1846 u32 hotplug;
1847
1848 hotplug = I915_READ(PCH_PORT_HOTPLUG);
1849 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1850 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1851 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1852 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1853 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1854}
1855
f71d4af4 1856static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d
ZW		 1857{
1858 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1859 /* enable kind of interrupts always enabled */
013d5aa2
JB		 1860 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1861 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1ec14ad3 1862 u32 render_irqs;
2d7b8366 1863 u32 hotplug_mask;
036a4a7d 1864
1ec14ad3 1865 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 1866
1867 /* should always can generate irq */
1868 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3
CW		 1869 I915_WRITE(DEIMR, dev_priv->irq_mask);
1870 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
3143a2bf 1871 POSTING_READ(DEIER);
036a4a7d 1872
1ec14ad3 1873 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 1874
1875 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 1876 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 1877
1ec14ad3
CW		 1878 if (IS_GEN6(dev))
1879 render_irqs =
1880 GT_USER_INTERRUPT |
e2a1e2f0
BW		 1881 GEN6_BSD_USER_INTERRUPT |
1882 GEN6_BLITTER_USER_INTERRUPT;
1ec14ad3
CW		 1883 else
1884 render_irqs =
88f23b8f 1885 GT_USER_INTERRUPT |
c6df541c 1886 GT_PIPE_NOTIFY |
1ec14ad3
CW		 1887 GT_BSD_USER_INTERRUPT;
1888 I915_WRITE(GTIER, render_irqs);
3143a2bf 1889 POSTING_READ(GTIER);
036a4a7d 1890
2d7b8366 1891 if (HAS_PCH_CPT(dev)) {
9035a97a
CW		 1892 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1893 SDE_PORTB_HOTPLUG_CPT |
1894 SDE_PORTC_HOTPLUG_CPT |
515ac2bb
DV		 1895 SDE_PORTD_HOTPLUG_CPT |
1896 SDE_GMBUS_CPT);
2d7b8366 1897 } else {
9035a97a
CW		 1898 hotplug_mask = (SDE_CRT_HOTPLUG |
1899 SDE_PORTB_HOTPLUG |
1900 SDE_PORTC_HOTPLUG |
1901 SDE_PORTD_HOTPLUG |
515ac2bb 1902 SDE_GMBUS |
9035a97a 1903 SDE_AUX_MASK);
2d7b8366
YL		 1904 }
1905
1ec14ad3 1906 dev_priv->pch_irq_mask = ~hotplug_mask;
c650156a
ZW		 1907
1908 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1ec14ad3
CW		 1909 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1910 I915_WRITE(SDEIER, hotplug_mask);
3143a2bf 1911 POSTING_READ(SDEIER);
c650156a 1912
7fe0b973
KP		 1913 ironlake_enable_pch_hotplug(dev);
1914
f97108d1
JB		 1915 if (IS_IRONLAKE_M(dev)) {
1916 /* Clear & enable PCU event interrupts */
1917 I915_WRITE(DEIIR, DE_PCU_EVENT);
1918 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1919 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1920 }
1921
036a4a7d
ZW		 1922 return 0;
1923}
1924
f71d4af4 1925static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 1926{
1927 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1928 /* enable kind of interrupts always enabled */
b615b57a
CW		 1929 u32 display_mask =
1930 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
1931 DE_PLANEC_FLIP_DONE_IVB |
1932 DE_PLANEB_FLIP_DONE_IVB |
1933 DE_PLANEA_FLIP_DONE_IVB;
b1f14ad0
JB		 1934 u32 render_irqs;
1935 u32 hotplug_mask;
1936
b1f14ad0
JB		 1937 dev_priv->irq_mask = ~display_mask;
1938
1939 /* should always can generate irq */
1940 I915_WRITE(DEIIR, I915_READ(DEIIR));
1941 I915_WRITE(DEIMR, dev_priv->irq_mask);
b615b57a
CW		 1942 I915_WRITE(DEIER,
1943 display_mask |
1944 DE_PIPEC_VBLANK_IVB |
1945 DE_PIPEB_VBLANK_IVB |
1946 DE_PIPEA_VBLANK_IVB);
b1f14ad0
JB		 1947 POSTING_READ(DEIER);
1948
15b9f80e 1949 dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 1950
1951 I915_WRITE(GTIIR, I915_READ(GTIIR));
1952 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1953
e2a1e2f0 1954 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
15b9f80e 1955 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 1956 I915_WRITE(GTIER, render_irqs);
1957 POSTING_READ(GTIER);
1958
1959 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1960 SDE_PORTB_HOTPLUG_CPT |
1961 SDE_PORTC_HOTPLUG_CPT |
515ac2bb
DV		 1962 SDE_PORTD_HOTPLUG_CPT |
1963 SDE_GMBUS_CPT);
b1f14ad0
JB		 1964 dev_priv->pch_irq_mask = ~hotplug_mask;
1965
1966 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1967 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1968 I915_WRITE(SDEIER, hotplug_mask);
1969 POSTING_READ(SDEIER);
1970
7fe0b973
KP		 1971 ironlake_enable_pch_hotplug(dev);
1972
b1f14ad0
JB		 1973 return 0;
1974}
1975
7e231dbe
JB		 1976static int valleyview_irq_postinstall(struct drm_device *dev)
1977{
1978 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7e231dbe
JB		 1979 u32 enable_mask;
1980 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
31acc7f5 1981 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
3bcedbe5 1982 u32 render_irqs;
7e231dbe
JB		 1983 u16 msid;
1984
1985 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
31acc7f5
JB		 1986 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
1987 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1988 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
7e231dbe
JB		 1989 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1990
31acc7f5
JB		 1991 /*
1992 *Leave vblank interrupts masked initially. enable/disable will
1993 * toggle them based on usage.
1994 */
1995 dev_priv->irq_mask = (~enable_mask) |
1996 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1997 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1998
7e231dbe
JB		 1999 dev_priv->pipestat[0] = 0;
2000 dev_priv->pipestat[1] = 0;
2001
7e231dbe
JB		 2002 /* Hack for broken MSIs on VLV */
2003 pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
2004 pci_read_config_word(dev->pdev, 0x98, &msid);
2005 msid &= 0xff; /* mask out delivery bits */
2006 msid |= (1<<14);
2007 pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
2008
2009 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2010 I915_WRITE(VLV_IER, enable_mask);
2011 I915_WRITE(VLV_IIR, 0xffffffff);
2012 I915_WRITE(PIPESTAT(0), 0xffff);
2013 I915_WRITE(PIPESTAT(1), 0xffff);
2014 POSTING_READ(VLV_IER);
2015
31acc7f5 2016 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
515ac2bb 2017 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
31acc7f5
JB		 2018 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
2019
7e231dbe
JB		 2020 I915_WRITE(VLV_IIR, 0xffffffff);
2021 I915_WRITE(VLV_IIR, 0xffffffff);
2022
7e231dbe 2023 I915_WRITE(GTIIR, I915_READ(GTIIR));
31acc7f5 2024 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
3bcedbe5
JB		 2025
2026 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2027 GEN6_BLITTER_USER_INTERRUPT;
2028 I915_WRITE(GTIER, render_irqs);
7e231dbe
JB		 2029 POSTING_READ(GTIER);
2030
2031 /* ack & enable invalid PTE error interrupts */
2032#if 0 /* FIXME: add support to irq handler for checking these bits */
2033 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2034 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2035#endif
2036
2037 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
7e231dbe
JB		 2038 /* Note HDMI and DP share bits */
2039 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2040 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2041 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2042 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2043 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2044 hotplug_en |= HDMID_HOTPLUG_INT_EN;
ae33cdcf 2045 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
7e231dbe 2046 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
ae33cdcf 2047 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
7e231dbe
JB		 2048 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2049 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2050 hotplug_en |= CRT_HOTPLUG_INT_EN;
2051 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2052 }
7e231dbe
JB		 2053
2054 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2055
2056 return 0;
2057}
2058
7e231dbe
JB		 2059static void valleyview_irq_uninstall(struct drm_device *dev)
2060{
2061 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2062 int pipe;
2063
2064 if (!dev_priv)
2065 return;
2066
7e231dbe
JB		 2067 for_each_pipe(pipe)
2068 I915_WRITE(PIPESTAT(pipe), 0xffff);
2069
2070 I915_WRITE(HWSTAM, 0xffffffff);
2071 I915_WRITE(PORT_HOTPLUG_EN, 0);
2072 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2073 for_each_pipe(pipe)
2074 I915_WRITE(PIPESTAT(pipe), 0xffff);
2075 I915_WRITE(VLV_IIR, 0xffffffff);
2076 I915_WRITE(VLV_IMR, 0xffffffff);
2077 I915_WRITE(VLV_IER, 0x0);
2078 POSTING_READ(VLV_IER);
2079}
2080
f71d4af4 2081static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 2082{
2083 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 2084
2085 if (!dev_priv)
2086 return;
2087
036a4a7d
ZW		 2088 I915_WRITE(HWSTAM, 0xffffffff);
2089
2090 I915_WRITE(DEIMR, 0xffffffff);
2091 I915_WRITE(DEIER, 0x0);
2092 I915_WRITE(DEIIR, I915_READ(DEIIR));
2093
2094 I915_WRITE(GTIMR, 0xffffffff);
2095 I915_WRITE(GTIER, 0x0);
2096 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f
KP		 2097
2098 I915_WRITE(SDEIMR, 0xffffffff);
2099 I915_WRITE(SDEIER, 0x0);
2100 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
036a4a7d
ZW		 2101}
2102
a266c7d5 2103static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 2104{
2105 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2106 int pipe;
91e3738e 2107
a266c7d5 2108 atomic_set(&dev_priv->irq_received, 0);
5ca58282 2109
9db4a9c7
JB		 2110 for_each_pipe(pipe)
2111 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 2112 I915_WRITE16(IMR, 0xffff);
2113 I915_WRITE16(IER, 0x0);
2114 POSTING_READ16(IER);
c2798b19
CW		 2115}
2116
2117static int i8xx_irq_postinstall(struct drm_device *dev)
2118{
2119 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2120
c2798b19
CW		 2121 dev_priv->pipestat[0] = 0;
2122 dev_priv->pipestat[1] = 0;
2123
2124 I915_WRITE16(EMR,
2125 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2126
2127 /* Unmask the interrupts that we always want on. */
2128 dev_priv->irq_mask =
2129 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2130 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2131 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2132 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2133 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2134 I915_WRITE16(IMR, dev_priv->irq_mask);
2135
2136 I915_WRITE16(IER,
2137 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2138 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2139 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2140 I915_USER_INTERRUPT);
2141 POSTING_READ16(IER);
2142
2143 return 0;
2144}
2145
ff1f525e 2146static irqreturn_t i8xx_irq_handler(int irq, void *arg)
c2798b19
CW		 2147{
2148 struct drm_device *dev = (struct drm_device *) arg;
2149 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 2150 u16 iir, new_iir;
2151 u32 pipe_stats[2];
2152 unsigned long irqflags;
2153 int irq_received;
2154 int pipe;
2155 u16 flip_mask =
2156 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2157 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2158
2159 atomic_inc(&dev_priv->irq_received);
2160
2161 iir = I915_READ16(IIR);
2162 if (iir == 0)
2163 return IRQ_NONE;
2164
2165 while (iir & ~flip_mask) {
2166 /* Can't rely on pipestat interrupt bit in iir as it might
2167 * have been cleared after the pipestat interrupt was received.
2168 * It doesn't set the bit in iir again, but it still produces
2169 * interrupts (for non-MSI).
2170 */
2171 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2172 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2173 i915_handle_error(dev, false);
2174
2175 for_each_pipe(pipe) {
2176 int reg = PIPESTAT(pipe);
2177 pipe_stats[pipe] = I915_READ(reg);
2178
2179 /*
2180 * Clear the PIPE*STAT regs before the IIR
2181 */
2182 if (pipe_stats[pipe] & 0x8000ffff) {
2183 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2184 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2185 pipe_name(pipe));
2186 I915_WRITE(reg, pipe_stats[pipe]);
2187 irq_received = 1;
2188 }
2189 }
2190 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2191
2192 I915_WRITE16(IIR, iir & ~flip_mask);
2193 new_iir = I915_READ16(IIR); /* Flush posted writes */
2194
d05c617e 2195 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 2196
2197 if (iir & I915_USER_INTERRUPT)
2198 notify_ring(dev, &dev_priv->ring[RCS]);
2199
2200 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2201 drm_handle_vblank(dev, 0)) {
2202 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2203 intel_prepare_page_flip(dev, 0);
2204 intel_finish_page_flip(dev, 0);
2205 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2206 }
2207 }
2208
2209 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2210 drm_handle_vblank(dev, 1)) {
2211 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2212 intel_prepare_page_flip(dev, 1);
2213 intel_finish_page_flip(dev, 1);
2214 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2215 }
2216 }
2217
2218 iir = new_iir;
2219 }
2220
2221 return IRQ_HANDLED;
2222}
2223
2224static void i8xx_irq_uninstall(struct drm_device * dev)
2225{
2226 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2227 int pipe;
2228
c2798b19
CW		 2229 for_each_pipe(pipe) {
2230 /* Clear enable bits; then clear status bits */
2231 I915_WRITE(PIPESTAT(pipe), 0);
2232 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2233 }
2234 I915_WRITE16(IMR, 0xffff);
2235 I915_WRITE16(IER, 0x0);
2236 I915_WRITE16(IIR, I915_READ16(IIR));
2237}
2238
a266c7d5
CW		 2239static void i915_irq_preinstall(struct drm_device * dev)
2240{
2241 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2242 int pipe;
2243
2244 atomic_set(&dev_priv->irq_received, 0);
2245
2246 if (I915_HAS_HOTPLUG(dev)) {
2247 I915_WRITE(PORT_HOTPLUG_EN, 0);
2248 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2249 }
2250
00d98ebd 2251 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 2252 for_each_pipe(pipe)
2253 I915_WRITE(PIPESTAT(pipe), 0);
2254 I915_WRITE(IMR, 0xffffffff);
2255 I915_WRITE(IER, 0x0);
2256 POSTING_READ(IER);
2257}
2258
2259static int i915_irq_postinstall(struct drm_device *dev)
2260{
2261 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 2262 u32 enable_mask;
a266c7d5 2263
a266c7d5
CW		 2264 dev_priv->pipestat[0] = 0;
2265 dev_priv->pipestat[1] = 0;
2266
38bde180
CW		 2267 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2268
2269 /* Unmask the interrupts that we always want on. */
2270 dev_priv->irq_mask =
2271 ~(I915_ASLE_INTERRUPT |
2272 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2273 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2274 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2275 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2276 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2277
2278 enable_mask =
2279 I915_ASLE_INTERRUPT |
2280 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2281 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2282 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2283 I915_USER_INTERRUPT;
2284
a266c7d5
CW		 2285 if (I915_HAS_HOTPLUG(dev)) {
2286 /* Enable in IER... */
2287 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2288 /* and unmask in IMR */
2289 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2290 }
2291
a266c7d5
CW		 2292 I915_WRITE(IMR, dev_priv->irq_mask);
2293 I915_WRITE(IER, enable_mask);
2294 POSTING_READ(IER);
2295
2296 if (I915_HAS_HOTPLUG(dev)) {
2297 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2298
a266c7d5
CW		 2299 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2300 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2301 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2302 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2303 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2304 hotplug_en |= HDMID_HOTPLUG_INT_EN;
084b612e 2305 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
a266c7d5 2306 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
084b612e 2307 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
a266c7d5
CW		 2308 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2309 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2310 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5
CW		 2311 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2312 }
2313
2314 /* Ignore TV since it's buggy */
2315
2316 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2317 }
2318
2319 intel_opregion_enable_asle(dev);
2320
2321 return 0;
2322}
2323
ff1f525e 2324static irqreturn_t i915_irq_handler(int irq, void *arg)
a266c7d5
CW		 2325{
2326 struct drm_device *dev = (struct drm_device *) arg;
2327 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 2328 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 2329 unsigned long irqflags;
38bde180
CW		 2330 u32 flip_mask =
2331 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2332 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2333 u32 flip[2] = {
2334 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2335 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2336 };
2337 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 2338
2339 atomic_inc(&dev_priv->irq_received);
2340
2341 iir = I915_READ(IIR);
38bde180
CW		 2342 do {
2343 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 2344 bool blc_event = false;
a266c7d5
CW		 2345
2346 /* Can't rely on pipestat interrupt bit in iir as it might
2347 * have been cleared after the pipestat interrupt was received.
2348 * It doesn't set the bit in iir again, but it still produces
2349 * interrupts (for non-MSI).
2350 */
2351 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2352 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2353 i915_handle_error(dev, false);
2354
2355 for_each_pipe(pipe) {
2356 int reg = PIPESTAT(pipe);
2357 pipe_stats[pipe] = I915_READ(reg);
2358
38bde180 2359 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 2360 if (pipe_stats[pipe] & 0x8000ffff) {
2361 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2362 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2363 pipe_name(pipe));
2364 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 2365 irq_received = true;
a266c7d5
CW		 2366 }
2367 }
2368 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2369
2370 if (!irq_received)
2371 break;
2372
a266c7d5
CW		 2373 /* Consume port. Then clear IIR or we'll miss events */
2374 if ((I915_HAS_HOTPLUG(dev)) &&
2375 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2376 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2377
2378 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2379 hotplug_status);
2380 if (hotplug_status & dev_priv->hotplug_supported_mask)
2381 queue_work(dev_priv->wq,
2382 &dev_priv->hotplug_work);
2383
2384 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 2385 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 2386 }
2387
38bde180 2388 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2389 new_iir = I915_READ(IIR); /* Flush posted writes */
2390
a266c7d5
CW		 2391 if (iir & I915_USER_INTERRUPT)
2392 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 2393
a266c7d5 2394 for_each_pipe(pipe) {
38bde180
CW		 2395 int plane = pipe;
2396 if (IS_MOBILE(dev))
2397 plane = !plane;
8291ee90 2398 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2399 drm_handle_vblank(dev, pipe)) {
38bde180
CW		 2400 if (iir & flip[plane]) {
2401 intel_prepare_page_flip(dev, plane);
2402 intel_finish_page_flip(dev, pipe);
2403 flip_mask &= ~flip[plane];
2404 }
a266c7d5
CW		 2405 }
2406
2407 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2408 blc_event = true;
2409 }
2410
a266c7d5
CW		 2411 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2412 intel_opregion_asle_intr(dev);
2413
2414 /* With MSI, interrupts are only generated when iir
2415 * transitions from zero to nonzero. If another bit got
2416 * set while we were handling the existing iir bits, then
2417 * we would never get another interrupt.
2418 *
2419 * This is fine on non-MSI as well, as if we hit this path
2420 * we avoid exiting the interrupt handler only to generate
2421 * another one.
2422 *
2423 * Note that for MSI this could cause a stray interrupt report
2424 * if an interrupt landed in the time between writing IIR and
2425 * the posting read. This should be rare enough to never
2426 * trigger the 99% of 100,000 interrupts test for disabling
2427 * stray interrupts.
2428 */
38bde180 2429 ret = IRQ_HANDLED;
a266c7d5 2430 iir = new_iir;
38bde180 2431 } while (iir & ~flip_mask);
a266c7d5 2432
d05c617e 2433 i915_update_dri1_breadcrumb(dev);
8291ee90 2434
a266c7d5
CW		 2435 return ret;
2436}
2437
2438static void i915_irq_uninstall(struct drm_device * dev)
2439{
2440 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2441 int pipe;
2442
a266c7d5
CW		 2443 if (I915_HAS_HOTPLUG(dev)) {
2444 I915_WRITE(PORT_HOTPLUG_EN, 0);
2445 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2446 }
2447
00d98ebd 2448 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 2449 for_each_pipe(pipe) {
2450 /* Clear enable bits; then clear status bits */
a266c7d5 2451 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 2452 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2453 }
a266c7d5
CW		 2454 I915_WRITE(IMR, 0xffffffff);
2455 I915_WRITE(IER, 0x0);
2456
a266c7d5
CW		 2457 I915_WRITE(IIR, I915_READ(IIR));
2458}
2459
2460static void i965_irq_preinstall(struct drm_device * dev)
2461{
2462 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2463 int pipe;
2464
2465 atomic_set(&dev_priv->irq_received, 0);
2466
adca4730
CW		 2467 I915_WRITE(PORT_HOTPLUG_EN, 0);
2468 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2469
2470 I915_WRITE(HWSTAM, 0xeffe);
2471 for_each_pipe(pipe)
2472 I915_WRITE(PIPESTAT(pipe), 0);
2473 I915_WRITE(IMR, 0xffffffff);
2474 I915_WRITE(IER, 0x0);
2475 POSTING_READ(IER);
2476}
2477
2478static int i965_irq_postinstall(struct drm_device *dev)
2479{
2480 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
adca4730 2481 u32 hotplug_en;
bbba0a97 2482 u32 enable_mask;
a266c7d5
CW		 2483 u32 error_mask;
2484
a266c7d5 2485 /* Unmask the interrupts that we always want on. */
bbba0a97 2486 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 2487 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 2488 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2489 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2490 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2491 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2492 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2493
2494 enable_mask = ~dev_priv->irq_mask;
2495 enable_mask |= I915_USER_INTERRUPT;
2496
2497 if (IS_G4X(dev))
2498 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5
CW		 2499
2500 dev_priv->pipestat[0] = 0;
2501 dev_priv->pipestat[1] = 0;
515ac2bb 2502 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
a266c7d5 2503
a266c7d5
CW		 2504 /*
2505 * Enable some error detection, note the instruction error mask
2506 * bit is reserved, so we leave it masked.
2507 */
2508 if (IS_G4X(dev)) {
2509 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2510 GM45_ERROR_MEM_PRIV |
2511 GM45_ERROR_CP_PRIV |
2512 I915_ERROR_MEMORY_REFRESH);
2513 } else {
2514 error_mask = ~(I915_ERROR_PAGE_TABLE |
2515 I915_ERROR_MEMORY_REFRESH);
2516 }
2517 I915_WRITE(EMR, error_mask);
2518
2519 I915_WRITE(IMR, dev_priv->irq_mask);
2520 I915_WRITE(IER, enable_mask);
2521 POSTING_READ(IER);
2522
adca4730
CW		 2523 /* Note HDMI and DP share hotplug bits */
2524 hotplug_en = 0;
2525 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2526 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2527 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2528 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2529 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2530 hotplug_en |= HDMID_HOTPLUG_INT_EN;
084b612e
CW		 2531 if (IS_G4X(dev)) {
2532 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
2533 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2534 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
2535 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2536 } else {
2537 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
2538 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2539 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
2540 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2541 }
adca4730
CW		 2542 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2543 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5 2544
adca4730
CW		 2545 /* Programming the CRT detection parameters tends
2546 to generate a spurious hotplug event about three
2547 seconds later. So just do it once.
2548 */
2549 if (IS_G4X(dev))
2550 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2551 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2552 }
a266c7d5 2553
adca4730 2554 /* Ignore TV since it's buggy */
a266c7d5 2555
adca4730 2556 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
a266c7d5
CW		 2557
2558 intel_opregion_enable_asle(dev);
2559
2560 return 0;
2561}
2562
ff1f525e 2563static irqreturn_t i965_irq_handler(int irq, void *arg)
a266c7d5
CW		 2564{
2565 struct drm_device *dev = (struct drm_device *) arg;
2566 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 2567 u32 iir, new_iir;
2568 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 2569 unsigned long irqflags;
2570 int irq_received;
2571 int ret = IRQ_NONE, pipe;
a266c7d5
CW		 2572
2573 atomic_inc(&dev_priv->irq_received);
2574
2575 iir = I915_READ(IIR);
2576
a266c7d5 2577 for (;;) {
2c8ba29f
CW		 2578 bool blc_event = false;
2579
a266c7d5
CW		 2580 irq_received = iir != 0;
2581
2582 /* Can't rely on pipestat interrupt bit in iir as it might
2583 * have been cleared after the pipestat interrupt was received.
2584 * It doesn't set the bit in iir again, but it still produces
2585 * interrupts (for non-MSI).
2586 */
2587 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2588 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2589 i915_handle_error(dev, false);
2590
2591 for_each_pipe(pipe) {
2592 int reg = PIPESTAT(pipe);
2593 pipe_stats[pipe] = I915_READ(reg);
2594
2595 /*
2596 * Clear the PIPE*STAT regs before the IIR
2597 */
2598 if (pipe_stats[pipe] & 0x8000ffff) {
2599 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2600 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2601 pipe_name(pipe));
2602 I915_WRITE(reg, pipe_stats[pipe]);
2603 irq_received = 1;
2604 }
2605 }
2606 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2607
2608 if (!irq_received)
2609 break;
2610
2611 ret = IRQ_HANDLED;
2612
2613 /* Consume port. Then clear IIR or we'll miss events */
adca4730 2614 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
a266c7d5
CW		 2615 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2616
2617 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2618 hotplug_status);
2619 if (hotplug_status & dev_priv->hotplug_supported_mask)
2620 queue_work(dev_priv->wq,
2621 &dev_priv->hotplug_work);
2622
2623 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2624 I915_READ(PORT_HOTPLUG_STAT);
2625 }
2626
2627 I915_WRITE(IIR, iir);
2628 new_iir = I915_READ(IIR); /* Flush posted writes */
2629
a266c7d5
CW		 2630 if (iir & I915_USER_INTERRUPT)
2631 notify_ring(dev, &dev_priv->ring[RCS]);
2632 if (iir & I915_BSD_USER_INTERRUPT)
2633 notify_ring(dev, &dev_priv->ring[VCS]);
2634
4f7d1e79 2635 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
a266c7d5 2636 intel_prepare_page_flip(dev, 0);
a266c7d5 2637
4f7d1e79 2638 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
a266c7d5 2639 intel_prepare_page_flip(dev, 1);
a266c7d5
CW		 2640
2641 for_each_pipe(pipe) {
2c8ba29f 2642 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2643 drm_handle_vblank(dev, pipe)) {
4f7d1e79
CW		 2644 i915_pageflip_stall_check(dev, pipe);
2645 intel_finish_page_flip(dev, pipe);
a266c7d5
CW		 2646 }
2647
2648 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2649 blc_event = true;
2650 }
2651
2652
2653 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2654 intel_opregion_asle_intr(dev);
2655
515ac2bb
DV		 2656 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
2657 gmbus_irq_handler(dev);
2658
a266c7d5
CW		 2659 /* With MSI, interrupts are only generated when iir
2660 * transitions from zero to nonzero. If another bit got
2661 * set while we were handling the existing iir bits, then
2662 * we would never get another interrupt.
2663 *
2664 * This is fine on non-MSI as well, as if we hit this path
2665 * we avoid exiting the interrupt handler only to generate
2666 * another one.
2667 *
2668 * Note that for MSI this could cause a stray interrupt report
2669 * if an interrupt landed in the time between writing IIR and
2670 * the posting read. This should be rare enough to never
2671 * trigger the 99% of 100,000 interrupts test for disabling
2672 * stray interrupts.
2673 */
2674 iir = new_iir;
2675 }
2676
d05c617e 2677 i915_update_dri1_breadcrumb(dev);
2c8ba29f 2678
a266c7d5
CW		 2679 return ret;
2680}
2681
2682static void i965_irq_uninstall(struct drm_device * dev)
2683{
2684 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2685 int pipe;
2686
2687 if (!dev_priv)
2688 return;
2689
adca4730
CW		 2690 I915_WRITE(PORT_HOTPLUG_EN, 0);
2691 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2692
2693 I915_WRITE(HWSTAM, 0xffffffff);
2694 for_each_pipe(pipe)
2695 I915_WRITE(PIPESTAT(pipe), 0);
2696 I915_WRITE(IMR, 0xffffffff);
2697 I915_WRITE(IER, 0x0);
2698
2699 for_each_pipe(pipe)
2700 I915_WRITE(PIPESTAT(pipe),
2701 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2702 I915_WRITE(IIR, I915_READ(IIR));
2703}
2704
f71d4af4
JB		 2705void intel_irq_init(struct drm_device *dev)
2706{
8b2e326d
CW		 2707 struct drm_i915_private *dev_priv = dev->dev_private;
2708
2709 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2710 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
c6a828d3 2711 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
a4da4fa4 2712 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
8b2e326d 2713
61bac78e
DV		 2714 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
2715 (unsigned long) dev);
2716
f71d4af4
JB		 2717 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2718 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7d4e146f 2719 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 2720 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2721 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2722 }
2723
c3613de9
KP		 2724 if (drm_core_check_feature(dev, DRIVER_MODESET))
2725 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2726 else
2727 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 2728 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2729
7e231dbe
JB		 2730 if (IS_VALLEYVIEW(dev)) {
2731 dev->driver->irq_handler = valleyview_irq_handler;
2732 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2733 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2734 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2735 dev->driver->enable_vblank = valleyview_enable_vblank;
2736 dev->driver->disable_vblank = valleyview_disable_vblank;
4a06e201 2737 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
f71d4af4
JB		 2738 /* Share pre & uninstall handlers with ILK/SNB */
2739 dev->driver->irq_handler = ivybridge_irq_handler;
2740 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2741 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2742 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2743 dev->driver->enable_vblank = ivybridge_enable_vblank;
2744 dev->driver->disable_vblank = ivybridge_disable_vblank;
2745 } else if (HAS_PCH_SPLIT(dev)) {
2746 dev->driver->irq_handler = ironlake_irq_handler;
2747 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2748 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2749 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2750 dev->driver->enable_vblank = ironlake_enable_vblank;
2751 dev->driver->disable_vblank = ironlake_disable_vblank;
2752 } else {
c2798b19
CW		 2753 if (INTEL_INFO(dev)->gen == 2) {
2754 dev->driver->irq_preinstall = i8xx_irq_preinstall;
2755 dev->driver->irq_postinstall = i8xx_irq_postinstall;
2756 dev->driver->irq_handler = i8xx_irq_handler;
2757 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5
CW		 2758 } else if (INTEL_INFO(dev)->gen == 3) {
2759 dev->driver->irq_preinstall = i915_irq_preinstall;
2760 dev->driver->irq_postinstall = i915_irq_postinstall;
2761 dev->driver->irq_uninstall = i915_irq_uninstall;
2762 dev->driver->irq_handler = i915_irq_handler;
c2798b19 2763 } else {
a266c7d5
CW		 2764 dev->driver->irq_preinstall = i965_irq_preinstall;
2765 dev->driver->irq_postinstall = i965_irq_postinstall;
2766 dev->driver->irq_uninstall = i965_irq_uninstall;
2767 dev->driver->irq_handler = i965_irq_handler;
c2798b19 2768 }
f71d4af4
JB		 2769 dev->driver->enable_vblank = i915_enable_vblank;
2770 dev->driver->disable_vblank = i915_disable_vblank;
2771 }
2772}
Ubuntu Jammy Linux kernel mirror