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drm/i915: use __wait_seqno for ring throttle
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
1da177e4
LT		 33#include "drmP.h"
34#include "drm.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
1c5d22f7 37#include "i915_trace.h"
79e53945 38#include "intel_drv.h"
1da177e4 39
036a4a7d 40/* For display hotplug interrupt */
995b6762 41static void
f2b115e6 42ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 43{
1ec14ad3
CW		 44 if ((dev_priv->irq_mask & mask) != 0) {
45 dev_priv->irq_mask &= ~mask;
46 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 47 POSTING_READ(DEIMR);
036a4a7d
ZW		 48 }
49}
50
51static inline void
f2b115e6 52ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 53{
1ec14ad3
CW		 54 if ((dev_priv->irq_mask & mask) != mask) {
55 dev_priv->irq_mask |= mask;
56 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 57 POSTING_READ(DEIMR);
036a4a7d
ZW		 58 }
59}
60
7c463586
KP		 61void
62i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
63{
64 if ((dev_priv->pipestat[pipe] & mask) != mask) {
9db4a9c7 65 u32 reg = PIPESTAT(pipe);
7c463586
KP		 66
67 dev_priv->pipestat[pipe] |= mask;
68 /* Enable the interrupt, clear any pending status */
69 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
3143a2bf 70 POSTING_READ(reg);
7c463586
KP		 71 }
72}
73
74void
75i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
76{
77 if ((dev_priv->pipestat[pipe] & mask) != 0) {
9db4a9c7 78 u32 reg = PIPESTAT(pipe);
7c463586
KP		 79
80 dev_priv->pipestat[pipe] &= ~mask;
81 I915_WRITE(reg, dev_priv->pipestat[pipe]);
3143a2bf 82 POSTING_READ(reg);
7c463586
KP		 83 }
84}
85
01c66889
ZY		 86/**
87 * intel_enable_asle - enable ASLE interrupt for OpRegion
88 */
1ec14ad3 89void intel_enable_asle(struct drm_device *dev)
01c66889 90{
1ec14ad3
CW		 91 drm_i915_private_t *dev_priv = dev->dev_private;
92 unsigned long irqflags;
93
7e231dbe
JB		 94 /* FIXME: opregion/asle for VLV */
95 if (IS_VALLEYVIEW(dev))
96 return;
97
1ec14ad3 98 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 99
c619eed4 100 if (HAS_PCH_SPLIT(dev))
f2b115e6 101 ironlake_enable_display_irq(dev_priv, DE_GSE);
edcb49ca 102 else {
01c66889 103 i915_enable_pipestat(dev_priv, 1,
d874bcff 104 PIPE_LEGACY_BLC_EVENT_ENABLE);
a6c45cf0 105 if (INTEL_INFO(dev)->gen >= 4)
edcb49ca 106 i915_enable_pipestat(dev_priv, 0,
d874bcff 107 PIPE_LEGACY_BLC_EVENT_ENABLE);
edcb49ca 108 }
1ec14ad3
CW		 109
110 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 111}
112
0a3e67a4
JB		 113/**
114 * i915_pipe_enabled - check if a pipe is enabled
115 * @dev: DRM device
116 * @pipe: pipe to check
117 *
118 * Reading certain registers when the pipe is disabled can hang the chip.
119 * Use this routine to make sure the PLL is running and the pipe is active
120 * before reading such registers if unsure.
121 */
122static int
123i915_pipe_enabled(struct drm_device *dev, int pipe)
124{
125 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
5eddb70b 126 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
0a3e67a4
JB		 127}
128
42f52ef8
KP		 129/* Called from drm generic code, passed a 'crtc', which
130 * we use as a pipe index
131 */
f71d4af4 132static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 133{
134 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
135 unsigned long high_frame;
136 unsigned long low_frame;
5eddb70b 137 u32 high1, high2, low;
0a3e67a4
JB		 138
139 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 140 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 141 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 142 return 0;
143 }
144
9db4a9c7
JB		 145 high_frame = PIPEFRAME(pipe);
146 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 147
0a3e67a4
JB		 148 /*
149 * High & low register fields aren't synchronized, so make sure
150 * we get a low value that's stable across two reads of the high
151 * register.
152 */
153 do {
5eddb70b
CW		 154 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
155 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
156 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 157 } while (high1 != high2);
158
5eddb70b
CW		 159 high1 >>= PIPE_FRAME_HIGH_SHIFT;
160 low >>= PIPE_FRAME_LOW_SHIFT;
161 return (high1 << 8) | low;
0a3e67a4
JB		 162}
163
f71d4af4 164static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 165{
166 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 167 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 168
169 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 170 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 171 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 172 return 0;
173 }
174
175 return I915_READ(reg);
176}
177
f71d4af4 178static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 179 int *vpos, int *hpos)
180{
181 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
182 u32 vbl = 0, position = 0;
183 int vbl_start, vbl_end, htotal, vtotal;
184 bool in_vbl = true;
185 int ret = 0;
186
187 if (!i915_pipe_enabled(dev, pipe)) {
188 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 189 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 190 return 0;
191 }
192
193 /* Get vtotal. */
194 vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
195
196 if (INTEL_INFO(dev)->gen >= 4) {
197 /* No obvious pixelcount register. Only query vertical
198 * scanout position from Display scan line register.
199 */
200 position = I915_READ(PIPEDSL(pipe));
201
202 /* Decode into vertical scanout position. Don't have
203 * horizontal scanout position.
204 */
205 *vpos = position & 0x1fff;
206 *hpos = 0;
207 } else {
208 /* Have access to pixelcount since start of frame.
209 * We can split this into vertical and horizontal
210 * scanout position.
211 */
212 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
213
214 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
215 *vpos = position / htotal;
216 *hpos = position - (*vpos * htotal);
217 }
218
219 /* Query vblank area. */
220 vbl = I915_READ(VBLANK(pipe));
221
222 /* Test position against vblank region. */
223 vbl_start = vbl & 0x1fff;
224 vbl_end = (vbl >> 16) & 0x1fff;
225
226 if ((*vpos < vbl_start) || (*vpos > vbl_end))
227 in_vbl = false;
228
229 /* Inside "upper part" of vblank area? Apply corrective offset: */
230 if (in_vbl && (*vpos >= vbl_start))
231 *vpos = *vpos - vtotal;
232
233 /* Readouts valid? */
234 if (vbl > 0)
235 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
236
237 /* In vblank? */
238 if (in_vbl)
239 ret |= DRM_SCANOUTPOS_INVBL;
240
241 return ret;
242}
243
f71d4af4 244static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 245 int *max_error,
246 struct timeval *vblank_time,
247 unsigned flags)
248{
4041b853
CW		 249 struct drm_i915_private *dev_priv = dev->dev_private;
250 struct drm_crtc *crtc;
0af7e4df 251
4041b853
CW		 252 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
253 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 254 return -EINVAL;
255 }
256
257 /* Get drm_crtc to timestamp: */
4041b853
CW		 258 crtc = intel_get_crtc_for_pipe(dev, pipe);
259 if (crtc == NULL) {
260 DRM_ERROR("Invalid crtc %d\n", pipe);
261 return -EINVAL;
262 }
263
264 if (!crtc->enabled) {
265 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
266 return -EBUSY;
267 }
0af7e4df
MK		 268
269 /* Helper routine in DRM core does all the work: */
4041b853
CW		 270 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
271 vblank_time, flags,
272 crtc);
0af7e4df
MK		 273}
274
5ca58282
JB		 275/*
276 * Handle hotplug events outside the interrupt handler proper.
277 */
278static void i915_hotplug_work_func(struct work_struct *work)
279{
280 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
281 hotplug_work);
282 struct drm_device *dev = dev_priv->dev;
c31c4ba3 283 struct drm_mode_config *mode_config = &dev->mode_config;
4ef69c7a
CW		 284 struct intel_encoder *encoder;
285
a65e34c7 286 mutex_lock(&mode_config->mutex);
e67189ab
JB		 287 DRM_DEBUG_KMS("running encoder hotplug functions\n");
288
4ef69c7a
CW		 289 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
290 if (encoder->hot_plug)
291 encoder->hot_plug(encoder);
292
40ee3381
KP		 293 mutex_unlock(&mode_config->mutex);
294
5ca58282 295 /* Just fire off a uevent and let userspace tell us what to do */
eb1f8e4f 296 drm_helper_hpd_irq_event(dev);
5ca58282
JB		 297}
298
f97108d1
JB		 299static void i915_handle_rps_change(struct drm_device *dev)
300{
301 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 302 u32 busy_up, busy_down, max_avg, min_avg;
f97108d1
JB		 303 u8 new_delay = dev_priv->cur_delay;
304
7648fa99 305 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 306 busy_up = I915_READ(RCPREVBSYTUPAVG);
307 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 308 max_avg = I915_READ(RCBMAXAVG);
309 min_avg = I915_READ(RCBMINAVG);
310
311 /* Handle RCS change request from hw */
b5b72e89 312 if (busy_up > max_avg) {
f97108d1
JB		 313 if (dev_priv->cur_delay != dev_priv->max_delay)
314 new_delay = dev_priv->cur_delay - 1;
315 if (new_delay < dev_priv->max_delay)
316 new_delay = dev_priv->max_delay;
b5b72e89 317 } else if (busy_down < min_avg) {
f97108d1
JB		 318 if (dev_priv->cur_delay != dev_priv->min_delay)
319 new_delay = dev_priv->cur_delay + 1;
320 if (new_delay > dev_priv->min_delay)
321 new_delay = dev_priv->min_delay;
322 }
323
7648fa99
JB		 324 if (ironlake_set_drps(dev, new_delay))
325 dev_priv->cur_delay = new_delay;
f97108d1
JB		 326
327 return;
328}
329
549f7365
CW		 330static void notify_ring(struct drm_device *dev,
331 struct intel_ring_buffer *ring)
332{
333 struct drm_i915_private *dev_priv = dev->dev_private;
475553de 334 u32 seqno;
9862e600 335
475553de
CW		 336 if (ring->obj == NULL)
337 return;
338
339 seqno = ring->get_seqno(ring);
db53a302 340 trace_i915_gem_request_complete(ring, seqno);
9862e600
CW		 341
342 ring->irq_seqno = seqno;
549f7365 343 wake_up_all(&ring->irq_queue);
3e0dc6b0
BW		 344 if (i915_enable_hangcheck) {
345 dev_priv->hangcheck_count = 0;
346 mod_timer(&dev_priv->hangcheck_timer,
347 jiffies +
348 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
349 }
549f7365
CW		 350}
351
4912d041 352static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 353{
4912d041
BW		 354 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
355 rps_work);
3b8d8d91 356 u8 new_delay = dev_priv->cur_delay;
4912d041
BW		 357 u32 pm_iir, pm_imr;
358
359 spin_lock_irq(&dev_priv->rps_lock);
360 pm_iir = dev_priv->pm_iir;
361 dev_priv->pm_iir = 0;
362 pm_imr = I915_READ(GEN6_PMIMR);
a9e2641d 363 I915_WRITE(GEN6_PMIMR, 0);
4912d041 364 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91 365
3b8d8d91
JB		 366 if (!pm_iir)
367 return;
368
4912d041 369 mutex_lock(&dev_priv->dev->struct_mutex);
3b8d8d91
JB		 370 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
371 if (dev_priv->cur_delay != dev_priv->max_delay)
372 new_delay = dev_priv->cur_delay + 1;
373 if (new_delay > dev_priv->max_delay)
374 new_delay = dev_priv->max_delay;
375 } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
4912d041 376 gen6_gt_force_wake_get(dev_priv);
3b8d8d91
JB		 377 if (dev_priv->cur_delay != dev_priv->min_delay)
378 new_delay = dev_priv->cur_delay - 1;
379 if (new_delay < dev_priv->min_delay) {
380 new_delay = dev_priv->min_delay;
381 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
382 I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
383 ((new_delay << 16) & 0x3f0000));
384 } else {
385 /* Make sure we continue to get down interrupts
386 * until we hit the minimum frequency */
387 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
388 I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
389 }
4912d041 390 gen6_gt_force_wake_put(dev_priv);
3b8d8d91
JB		 391 }
392
4912d041 393 gen6_set_rps(dev_priv->dev, new_delay);
3b8d8d91
JB		 394 dev_priv->cur_delay = new_delay;
395
4912d041
BW		 396 /*
397 * rps_lock not held here because clearing is non-destructive. There is
398 * an *extremely* unlikely race with gen6_rps_enable() that is prevented
399 * by holding struct_mutex for the duration of the write.
400 */
4912d041 401 mutex_unlock(&dev_priv->dev->struct_mutex);
3b8d8d91
JB		 402}
403
e7b4c6b1
DV		 404static void snb_gt_irq_handler(struct drm_device *dev,
405 struct drm_i915_private *dev_priv,
406 u32 gt_iir)
407{
408
409 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
410 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
411 notify_ring(dev, &dev_priv->ring[RCS]);
412 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
413 notify_ring(dev, &dev_priv->ring[VCS]);
414 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
415 notify_ring(dev, &dev_priv->ring[BCS]);
416
417 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
418 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
419 GT_RENDER_CS_ERROR_INTERRUPT)) {
420 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
421 i915_handle_error(dev, false);
422 }
423}
424
fc6826d1
CW		 425static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
426 u32 pm_iir)
427{
428 unsigned long flags;
429
430 /*
431 * IIR bits should never already be set because IMR should
432 * prevent an interrupt from being shown in IIR. The warning
433 * displays a case where we've unsafely cleared
434 * dev_priv->pm_iir. Although missing an interrupt of the same
435 * type is not a problem, it displays a problem in the logic.
436 *
437 * The mask bit in IMR is cleared by rps_work.
438 */
439
440 spin_lock_irqsave(&dev_priv->rps_lock, flags);
441 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
442 dev_priv->pm_iir |= pm_iir;
443 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
444 POSTING_READ(GEN6_PMIMR);
445 spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
446
447 queue_work(dev_priv->wq, &dev_priv->rps_work);
448}
449
7e231dbe
JB		 450static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
451{
452 struct drm_device *dev = (struct drm_device *) arg;
453 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
454 u32 iir, gt_iir, pm_iir;
455 irqreturn_t ret = IRQ_NONE;
456 unsigned long irqflags;
457 int pipe;
458 u32 pipe_stats[I915_MAX_PIPES];
459 u32 vblank_status;
460 int vblank = 0;
461 bool blc_event;
462
463 atomic_inc(&dev_priv->irq_received);
464
465 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS |
466 PIPE_VBLANK_INTERRUPT_STATUS;
467
468 while (true) {
469 iir = I915_READ(VLV_IIR);
470 gt_iir = I915_READ(GTIIR);
471 pm_iir = I915_READ(GEN6_PMIIR);
472
473 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
474 goto out;
475
476 ret = IRQ_HANDLED;
477
e7b4c6b1 478 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 479
480 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
481 for_each_pipe(pipe) {
482 int reg = PIPESTAT(pipe);
483 pipe_stats[pipe] = I915_READ(reg);
484
485 /*
486 * Clear the PIPE*STAT regs before the IIR
487 */
488 if (pipe_stats[pipe] & 0x8000ffff) {
489 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
490 DRM_DEBUG_DRIVER("pipe %c underrun\n",
491 pipe_name(pipe));
492 I915_WRITE(reg, pipe_stats[pipe]);
493 }
494 }
495 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
496
497 /* Consume port. Then clear IIR or we'll miss events */
498 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
499 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
500
501 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
502 hotplug_status);
503 if (hotplug_status & dev_priv->hotplug_supported_mask)
504 queue_work(dev_priv->wq,
505 &dev_priv->hotplug_work);
506
507 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
508 I915_READ(PORT_HOTPLUG_STAT);
509 }
510
511
512 if (iir & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) {
513 drm_handle_vblank(dev, 0);
514 vblank++;
e0f608d7 515 intel_finish_page_flip(dev, 0);
7e231dbe
JB		 516 }
517
518 if (iir & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) {
519 drm_handle_vblank(dev, 1);
520 vblank++;
e0f608d7 521 intel_finish_page_flip(dev, 0);
7e231dbe
JB		 522 }
523
524 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
525 blc_event = true;
526
fc6826d1
CW		 527 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
528 gen6_queue_rps_work(dev_priv, pm_iir);
7e231dbe
JB		 529
530 I915_WRITE(GTIIR, gt_iir);
531 I915_WRITE(GEN6_PMIIR, pm_iir);
532 I915_WRITE(VLV_IIR, iir);
533 }
534
535out:
536 return ret;
537}
538
776ad806
JB		 539static void pch_irq_handler(struct drm_device *dev)
540{
541 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
542 u32 pch_iir;
9db4a9c7 543 int pipe;
776ad806
JB		 544
545 pch_iir = I915_READ(SDEIIR);
546
547 if (pch_iir & SDE_AUDIO_POWER_MASK)
548 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
549 (pch_iir & SDE_AUDIO_POWER_MASK) >>
550 SDE_AUDIO_POWER_SHIFT);
551
552 if (pch_iir & SDE_GMBUS)
553 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
554
555 if (pch_iir & SDE_AUDIO_HDCP_MASK)
556 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
557
558 if (pch_iir & SDE_AUDIO_TRANS_MASK)
559 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
560
561 if (pch_iir & SDE_POISON)
562 DRM_ERROR("PCH poison interrupt\n");
563
9db4a9c7
JB		 564 if (pch_iir & SDE_FDI_MASK)
565 for_each_pipe(pipe)
566 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
567 pipe_name(pipe),
568 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 569
570 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
571 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
572
573 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
574 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
575
576 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
577 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
578 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
579 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
580}
581
f71d4af4 582static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
b1f14ad0
JB		 583{
584 struct drm_device *dev = (struct drm_device *) arg;
585 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
586 int ret = IRQ_NONE;
587 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
588 struct drm_i915_master_private *master_priv;
589
590 atomic_inc(&dev_priv->irq_received);
591
592 /* disable master interrupt before clearing iir */
593 de_ier = I915_READ(DEIER);
594 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
595 POSTING_READ(DEIER);
596
597 de_iir = I915_READ(DEIIR);
598 gt_iir = I915_READ(GTIIR);
599 pch_iir = I915_READ(SDEIIR);
600 pm_iir = I915_READ(GEN6_PMIIR);
601
602 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && pm_iir == 0)
603 goto done;
604
605 ret = IRQ_HANDLED;
606
607 if (dev->primary->master) {
608 master_priv = dev->primary->master->driver_priv;
609 if (master_priv->sarea_priv)
610 master_priv->sarea_priv->last_dispatch =
611 READ_BREADCRUMB(dev_priv);
612 }
613
e7b4c6b1 614 snb_gt_irq_handler(dev, dev_priv, gt_iir);
b1f14ad0
JB		 615
616 if (de_iir & DE_GSE_IVB)
617 intel_opregion_gse_intr(dev);
618
619 if (de_iir & DE_PLANEA_FLIP_DONE_IVB) {
620 intel_prepare_page_flip(dev, 0);
621 intel_finish_page_flip_plane(dev, 0);
622 }
623
624 if (de_iir & DE_PLANEB_FLIP_DONE_IVB) {
625 intel_prepare_page_flip(dev, 1);
626 intel_finish_page_flip_plane(dev, 1);
627 }
628
629 if (de_iir & DE_PIPEA_VBLANK_IVB)
630 drm_handle_vblank(dev, 0);
631
f6b07f45 632 if (de_iir & DE_PIPEB_VBLANK_IVB)
b1f14ad0
JB		 633 drm_handle_vblank(dev, 1);
634
635 /* check event from PCH */
636 if (de_iir & DE_PCH_EVENT_IVB) {
637 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
638 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
639 pch_irq_handler(dev);
640 }
641
fc6826d1
CW		 642 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
643 gen6_queue_rps_work(dev_priv, pm_iir);
b1f14ad0
JB		 644
645 /* should clear PCH hotplug event before clear CPU irq */
646 I915_WRITE(SDEIIR, pch_iir);
647 I915_WRITE(GTIIR, gt_iir);
648 I915_WRITE(DEIIR, de_iir);
649 I915_WRITE(GEN6_PMIIR, pm_iir);
650
651done:
652 I915_WRITE(DEIER, de_ier);
653 POSTING_READ(DEIER);
654
655 return ret;
656}
657
e7b4c6b1
DV		 658static void ilk_gt_irq_handler(struct drm_device *dev,
659 struct drm_i915_private *dev_priv,
660 u32 gt_iir)
661{
662 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
663 notify_ring(dev, &dev_priv->ring[RCS]);
664 if (gt_iir & GT_BSD_USER_INTERRUPT)
665 notify_ring(dev, &dev_priv->ring[VCS]);
666}
667
f71d4af4 668static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
036a4a7d 669{
4697995b 670 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 671 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
672 int ret = IRQ_NONE;
3b8d8d91 673 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
2d7b8366 674 u32 hotplug_mask;
036a4a7d 675 struct drm_i915_master_private *master_priv;
881f47b6 676
4697995b
JB		 677 atomic_inc(&dev_priv->irq_received);
678
2d109a84
ZN		 679 /* disable master interrupt before clearing iir */
680 de_ier = I915_READ(DEIER);
681 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 682 POSTING_READ(DEIER);
2d109a84 683
036a4a7d
ZW		 684 de_iir = I915_READ(DEIIR);
685 gt_iir = I915_READ(GTIIR);
c650156a 686 pch_iir = I915_READ(SDEIIR);
3b8d8d91 687 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 688
3b8d8d91
JB		 689 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
690 (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 691 goto done;
036a4a7d 692
2d7b8366
YL		 693 if (HAS_PCH_CPT(dev))
694 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
695 else
696 hotplug_mask = SDE_HOTPLUG_MASK;
697
c7c85101 698 ret = IRQ_HANDLED;
036a4a7d 699
c7c85101
ZN		 700 if (dev->primary->master) {
701 master_priv = dev->primary->master->driver_priv;
702 if (master_priv->sarea_priv)
703 master_priv->sarea_priv->last_dispatch =
704 READ_BREADCRUMB(dev_priv);
705 }
036a4a7d 706
e7b4c6b1
DV		 707 if (IS_GEN5(dev))
708 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
709 else
710 snb_gt_irq_handler(dev, dev_priv, gt_iir);
01c66889 711
c7c85101 712 if (de_iir & DE_GSE)
3b617967 713 intel_opregion_gse_intr(dev);
c650156a 714
f072d2e7 715 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 716 intel_prepare_page_flip(dev, 0);
2bbda389 717 intel_finish_page_flip_plane(dev, 0);
f072d2e7 718 }
013d5aa2 719
f072d2e7 720 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 721 intel_prepare_page_flip(dev, 1);
2bbda389 722 intel_finish_page_flip_plane(dev, 1);
f072d2e7 723 }
013d5aa2 724
f072d2e7 725 if (de_iir & DE_PIPEA_VBLANK)
c062df61
LP		 726 drm_handle_vblank(dev, 0);
727
f072d2e7 728 if (de_iir & DE_PIPEB_VBLANK)
c062df61
LP		 729 drm_handle_vblank(dev, 1);
730
c7c85101 731 /* check event from PCH */
776ad806
JB		 732 if (de_iir & DE_PCH_EVENT) {
733 if (pch_iir & hotplug_mask)
734 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
735 pch_irq_handler(dev);
736 }
036a4a7d 737
f97108d1 738 if (de_iir & DE_PCU_EVENT) {
7648fa99 739 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
f97108d1
JB		 740 i915_handle_rps_change(dev);
741 }
742
fc6826d1
CW		 743 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
744 gen6_queue_rps_work(dev_priv, pm_iir);
3b8d8d91 745
c7c85101
ZN		 746 /* should clear PCH hotplug event before clear CPU irq */
747 I915_WRITE(SDEIIR, pch_iir);
748 I915_WRITE(GTIIR, gt_iir);
749 I915_WRITE(DEIIR, de_iir);
4912d041 750 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 751
752done:
2d109a84 753 I915_WRITE(DEIER, de_ier);
3143a2bf 754 POSTING_READ(DEIER);
2d109a84 755
036a4a7d
ZW		 756 return ret;
757}
758
8a905236
JB		 759/**
760 * i915_error_work_func - do process context error handling work
761 * @work: work struct
762 *
763 * Fire an error uevent so userspace can see that a hang or error
764 * was detected.
765 */
766static void i915_error_work_func(struct work_struct *work)
767{
768 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
769 error_work);
770 struct drm_device *dev = dev_priv->dev;
f316a42c
BG		 771 char *error_event[] = { "ERROR=1", NULL };
772 char *reset_event[] = { "RESET=1", NULL };
773 char *reset_done_event[] = { "ERROR=0", NULL };
8a905236 774
f316a42c
BG		 775 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
776
ba1234d1 777 if (atomic_read(&dev_priv->mm.wedged)) {
f803aa55
CW		 778 DRM_DEBUG_DRIVER("resetting chip\n");
779 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
780 if (!i915_reset(dev, GRDOM_RENDER)) {
781 atomic_set(&dev_priv->mm.wedged, 0);
782 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
f316a42c 783 }
30dbf0c0 784 complete_all(&dev_priv->error_completion);
f316a42c 785 }
8a905236
JB		 786}
787
3bd3c932 788#ifdef CONFIG_DEBUG_FS
9df30794 789static struct drm_i915_error_object *
bcfb2e28 790i915_error_object_create(struct drm_i915_private *dev_priv,
05394f39 791 struct drm_i915_gem_object *src)
9df30794
CW		 792{
793 struct drm_i915_error_object *dst;
9df30794 794 int page, page_count;
e56660dd 795 u32 reloc_offset;
9df30794 796
05394f39 797 if (src == NULL || src->pages == NULL)
9df30794
CW		 798 return NULL;
799
05394f39 800 page_count = src->base.size / PAGE_SIZE;
9df30794 801
0206e353 802 dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
9df30794
CW		 803 if (dst == NULL)
804 return NULL;
805
05394f39 806 reloc_offset = src->gtt_offset;
9df30794 807 for (page = 0; page < page_count; page++) {
788885ae 808 unsigned long flags;
e56660dd 809 void *d;
788885ae 810
e56660dd 811 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 812 if (d == NULL)
813 goto unwind;
e56660dd 814
788885ae 815 local_irq_save(flags);
74898d7e
DV		 816 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
817 src->has_global_gtt_mapping) {
172975aa
CW		 818 void __iomem *s;
819
820 /* Simply ignore tiling or any overlapping fence.
821 * It's part of the error state, and this hopefully
822 * captures what the GPU read.
823 */
824
825 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
826 reloc_offset);
827 memcpy_fromio(d, s, PAGE_SIZE);
828 io_mapping_unmap_atomic(s);
829 } else {
830 void *s;
831
832 drm_clflush_pages(&src->pages[page], 1);
833
834 s = kmap_atomic(src->pages[page]);
835 memcpy(d, s, PAGE_SIZE);
836 kunmap_atomic(s);
837
838 drm_clflush_pages(&src->pages[page], 1);
839 }
788885ae 840 local_irq_restore(flags);
e56660dd 841
9df30794 842 dst->pages[page] = d;
e56660dd
CW		 843
844 reloc_offset += PAGE_SIZE;
9df30794
CW		 845 }
846 dst->page_count = page_count;
05394f39 847 dst->gtt_offset = src->gtt_offset;
9df30794
CW		 848
849 return dst;
850
851unwind:
852 while (page--)
853 kfree(dst->pages[page]);
854 kfree(dst);
855 return NULL;
856}
857
858static void
859i915_error_object_free(struct drm_i915_error_object *obj)
860{
861 int page;
862
863 if (obj == NULL)
864 return;
865
866 for (page = 0; page < obj->page_count; page++)
867 kfree(obj->pages[page]);
868
869 kfree(obj);
870}
871
872static void
873i915_error_state_free(struct drm_device *dev,
874 struct drm_i915_error_state *error)
875{
e2f973d5
CW		 876 int i;
877
52d39a21
CW		 878 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
879 i915_error_object_free(error->ring[i].batchbuffer);
880 i915_error_object_free(error->ring[i].ringbuffer);
881 kfree(error->ring[i].requests);
882 }
e2f973d5 883
9df30794 884 kfree(error->active_bo);
6ef3d427 885 kfree(error->overlay);
9df30794
CW		 886 kfree(error);
887}
1b50247a
CW		 888static void capture_bo(struct drm_i915_error_buffer *err,
889 struct drm_i915_gem_object *obj)
890{
891 err->size = obj->base.size;
892 err->name = obj->base.name;
893 err->seqno = obj->last_rendering_seqno;
894 err->gtt_offset = obj->gtt_offset;
895 err->read_domains = obj->base.read_domains;
896 err->write_domain = obj->base.write_domain;
897 err->fence_reg = obj->fence_reg;
898 err->pinned = 0;
899 if (obj->pin_count > 0)
900 err->pinned = 1;
901 if (obj->user_pin_count > 0)
902 err->pinned = -1;
903 err->tiling = obj->tiling_mode;
904 err->dirty = obj->dirty;
905 err->purgeable = obj->madv != I915_MADV_WILLNEED;
906 err->ring = obj->ring ? obj->ring->id : -1;
907 err->cache_level = obj->cache_level;
908}
9df30794 909
1b50247a
CW		 910static u32 capture_active_bo(struct drm_i915_error_buffer *err,
911 int count, struct list_head *head)
c724e8a9
CW		 912{
913 struct drm_i915_gem_object *obj;
914 int i = 0;
915
916 list_for_each_entry(obj, head, mm_list) {
1b50247a 917 capture_bo(err++, obj);
c724e8a9
CW		 918 if (++i == count)
919 break;
1b50247a
CW		 920 }
921
922 return i;
923}
924
925static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
926 int count, struct list_head *head)
927{
928 struct drm_i915_gem_object *obj;
929 int i = 0;
930
931 list_for_each_entry(obj, head, gtt_list) {
932 if (obj->pin_count == 0)
933 continue;
c724e8a9 934
1b50247a
CW		 935 capture_bo(err++, obj);
936 if (++i == count)
937 break;
c724e8a9
CW		 938 }
939
940 return i;
941}
942
748ebc60
CW		 943static void i915_gem_record_fences(struct drm_device *dev,
944 struct drm_i915_error_state *error)
945{
946 struct drm_i915_private *dev_priv = dev->dev_private;
947 int i;
948
949 /* Fences */
950 switch (INTEL_INFO(dev)->gen) {
775d17b6 951 case 7:
748ebc60
CW		 952 case 6:
953 for (i = 0; i < 16; i++)
954 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
955 break;
956 case 5:
957 case 4:
958 for (i = 0; i < 16; i++)
959 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
960 break;
961 case 3:
962 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
963 for (i = 0; i < 8; i++)
964 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
965 case 2:
966 for (i = 0; i < 8; i++)
967 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
968 break;
969
970 }
971}
972
bcfb2e28
CW		 973static struct drm_i915_error_object *
974i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
975 struct intel_ring_buffer *ring)
976{
977 struct drm_i915_gem_object *obj;
978 u32 seqno;
979
980 if (!ring->get_seqno)
981 return NULL;
982
983 seqno = ring->get_seqno(ring);
984 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
985 if (obj->ring != ring)
986 continue;
987
c37d9a5d 988 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
bcfb2e28
CW		 989 continue;
990
991 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
992 continue;
993
994 /* We need to copy these to an anonymous buffer as the simplest
995 * method to avoid being overwritten by userspace.
996 */
997 return i915_error_object_create(dev_priv, obj);
998 }
999
1000 return NULL;
1001}
1002
d27b1e0e
DV		 1003static void i915_record_ring_state(struct drm_device *dev,
1004 struct drm_i915_error_state *error,
1005 struct intel_ring_buffer *ring)
1006{
1007 struct drm_i915_private *dev_priv = dev->dev_private;
1008
33f3f518 1009 if (INTEL_INFO(dev)->gen >= 6) {
33f3f518 1010 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
7e3b8737
DV		 1011 error->semaphore_mboxes[ring->id][0]
1012 = I915_READ(RING_SYNC_0(ring->mmio_base));
1013 error->semaphore_mboxes[ring->id][1]
1014 = I915_READ(RING_SYNC_1(ring->mmio_base));
33f3f518 1015 }
c1cd90ed 1016
d27b1e0e 1017 if (INTEL_INFO(dev)->gen >= 4) {
9d2f41fa 1018 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
d27b1e0e
DV		 1019 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1020 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1021 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
c1cd90ed 1022 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
d27b1e0e 1023 if (ring->id == RCS) {
d27b1e0e
DV		 1024 error->instdone1 = I915_READ(INSTDONE1);
1025 error->bbaddr = I915_READ64(BB_ADDR);
1026 }
1027 } else {
9d2f41fa 1028 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
d27b1e0e
DV		 1029 error->ipeir[ring->id] = I915_READ(IPEIR);
1030 error->ipehr[ring->id] = I915_READ(IPEHR);
1031 error->instdone[ring->id] = I915_READ(INSTDONE);
d27b1e0e
DV		 1032 }
1033
9574b3fe 1034 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
c1cd90ed 1035 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
d27b1e0e
DV		 1036 error->seqno[ring->id] = ring->get_seqno(ring);
1037 error->acthd[ring->id] = intel_ring_get_active_head(ring);
c1cd90ed
DV		 1038 error->head[ring->id] = I915_READ_HEAD(ring);
1039 error->tail[ring->id] = I915_READ_TAIL(ring);
7e3b8737
DV		 1040
1041 error->cpu_ring_head[ring->id] = ring->head;
1042 error->cpu_ring_tail[ring->id] = ring->tail;
d27b1e0e
DV		 1043}
1044
52d39a21
CW		 1045static void i915_gem_record_rings(struct drm_device *dev,
1046 struct drm_i915_error_state *error)
1047{
1048 struct drm_i915_private *dev_priv = dev->dev_private;
1049 struct drm_i915_gem_request *request;
1050 int i, count;
1051
1052 for (i = 0; i < I915_NUM_RINGS; i++) {
1053 struct intel_ring_buffer *ring = &dev_priv->ring[i];
1054
1055 if (ring->obj == NULL)
1056 continue;
1057
1058 i915_record_ring_state(dev, error, ring);
1059
1060 error->ring[i].batchbuffer =
1061 i915_error_first_batchbuffer(dev_priv, ring);
1062
1063 error->ring[i].ringbuffer =
1064 i915_error_object_create(dev_priv, ring->obj);
1065
1066 count = 0;
1067 list_for_each_entry(request, &ring->request_list, list)
1068 count++;
1069
1070 error->ring[i].num_requests = count;
1071 error->ring[i].requests =
1072 kmalloc(count*sizeof(struct drm_i915_error_request),
1073 GFP_ATOMIC);
1074 if (error->ring[i].requests == NULL) {
1075 error->ring[i].num_requests = 0;
1076 continue;
1077 }
1078
1079 count = 0;
1080 list_for_each_entry(request, &ring->request_list, list) {
1081 struct drm_i915_error_request *erq;
1082
1083 erq = &error->ring[i].requests[count++];
1084 erq->seqno = request->seqno;
1085 erq->jiffies = request->emitted_jiffies;
ee4f42b1 1086 erq->tail = request->tail;
52d39a21
CW		 1087 }
1088 }
1089}
1090
8a905236
JB		 1091/**
1092 * i915_capture_error_state - capture an error record for later analysis
1093 * @dev: drm device
1094 *
1095 * Should be called when an error is detected (either a hang or an error
1096 * interrupt) to capture error state from the time of the error. Fills
1097 * out a structure which becomes available in debugfs for user level tools
1098 * to pick up.
1099 */
63eeaf38
JB		 1100static void i915_capture_error_state(struct drm_device *dev)
1101{
1102 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1103 struct drm_i915_gem_object *obj;
63eeaf38
JB		 1104 struct drm_i915_error_state *error;
1105 unsigned long flags;
9db4a9c7 1106 int i, pipe;
63eeaf38
JB		 1107
1108 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1109 error = dev_priv->first_error;
1110 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1111 if (error)
1112 return;
63eeaf38 1113
9db4a9c7 1114 /* Account for pipe specific data like PIPE*STAT */
33f3f518 1115 error = kzalloc(sizeof(*error), GFP_ATOMIC);
63eeaf38 1116 if (!error) {
9df30794
CW		 1117 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1118 return;
63eeaf38
JB		 1119 }
1120
b6f7833b
CW		 1121 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1122 dev->primary->index);
2fa772f3 1123
63eeaf38
JB		 1124 error->eir = I915_READ(EIR);
1125 error->pgtbl_er = I915_READ(PGTBL_ER);
be998e2e
BW		 1126
1127 if (HAS_PCH_SPLIT(dev))
1128 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1129 else if (IS_VALLEYVIEW(dev))
1130 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1131 else if (IS_GEN2(dev))
1132 error->ier = I915_READ16(IER);
1133 else
1134 error->ier = I915_READ(IER);
1135
9db4a9c7
JB		 1136 for_each_pipe(pipe)
1137 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
d27b1e0e 1138
33f3f518 1139 if (INTEL_INFO(dev)->gen >= 6) {
f406839f 1140 error->error = I915_READ(ERROR_GEN6);
33f3f518
DV		 1141 error->done_reg = I915_READ(DONE_REG);
1142 }
d27b1e0e 1143
748ebc60 1144 i915_gem_record_fences(dev, error);
52d39a21 1145 i915_gem_record_rings(dev, error);
9df30794 1146
c724e8a9 1147 /* Record buffers on the active and pinned lists. */
9df30794 1148 error->active_bo = NULL;
c724e8a9 1149 error->pinned_bo = NULL;
9df30794 1150
bcfb2e28
CW		 1151 i = 0;
1152 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1153 i++;
1154 error->active_bo_count = i;
1b50247a
CW		 1155 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
1156 if (obj->pin_count)
1157 i++;
bcfb2e28 1158 error->pinned_bo_count = i - error->active_bo_count;
c724e8a9 1159
8e934dbf
CW		 1160 error->active_bo = NULL;
1161 error->pinned_bo = NULL;
bcfb2e28
CW		 1162 if (i) {
1163 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
9df30794 1164 GFP_ATOMIC);
c724e8a9
CW		 1165 if (error->active_bo)
1166 error->pinned_bo =
1167 error->active_bo + error->active_bo_count;
9df30794
CW		 1168 }
1169
c724e8a9
CW		 1170 if (error->active_bo)
1171 error->active_bo_count =
1b50247a
CW		 1172 capture_active_bo(error->active_bo,
1173 error->active_bo_count,
1174 &dev_priv->mm.active_list);
c724e8a9
CW		 1175
1176 if (error->pinned_bo)
1177 error->pinned_bo_count =
1b50247a
CW		 1178 capture_pinned_bo(error->pinned_bo,
1179 error->pinned_bo_count,
1180 &dev_priv->mm.gtt_list);
c724e8a9 1181
9df30794
CW		 1182 do_gettimeofday(&error->time);
1183
6ef3d427 1184 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 1185 error->display = intel_display_capture_error_state(dev);
6ef3d427 1186
9df30794
CW		 1187 spin_lock_irqsave(&dev_priv->error_lock, flags);
1188 if (dev_priv->first_error == NULL) {
1189 dev_priv->first_error = error;
1190 error = NULL;
1191 }
63eeaf38 1192 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1193
1194 if (error)
1195 i915_error_state_free(dev, error);
1196}
1197
1198void i915_destroy_error_state(struct drm_device *dev)
1199{
1200 struct drm_i915_private *dev_priv = dev->dev_private;
1201 struct drm_i915_error_state *error;
6dc0e816 1202 unsigned long flags;
9df30794 1203
6dc0e816 1204 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1205 error = dev_priv->first_error;
1206 dev_priv->first_error = NULL;
6dc0e816 1207 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1208
1209 if (error)
1210 i915_error_state_free(dev, error);
63eeaf38 1211}
3bd3c932
CW		 1212#else
1213#define i915_capture_error_state(x)
1214#endif
63eeaf38 1215
35aed2e6 1216static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1217{
1218 struct drm_i915_private *dev_priv = dev->dev_private;
1219 u32 eir = I915_READ(EIR);
9db4a9c7 1220 int pipe;
8a905236 1221
35aed2e6
CW		 1222 if (!eir)
1223 return;
8a905236 1224
a70491cc 1225 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236
JB		 1226
1227 if (IS_G4X(dev)) {
1228 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1229 u32 ipeir = I915_READ(IPEIR_I965);
1230
a70491cc
JP		 1231 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1232 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1233 pr_err(" INSTDONE: 0x%08x\n",
8a905236 1234 I915_READ(INSTDONE_I965));
a70491cc
JP		 1235 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1236 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1237 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1238 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1239 POSTING_READ(IPEIR_I965);
8a905236
JB		 1240 }
1241 if (eir & GM45_ERROR_PAGE_TABLE) {
1242 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1243 pr_err("page table error\n");
1244 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1245 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1246 POSTING_READ(PGTBL_ER);
8a905236
JB		 1247 }
1248 }
1249
a6c45cf0 1250 if (!IS_GEN2(dev)) {
8a905236
JB		 1251 if (eir & I915_ERROR_PAGE_TABLE) {
1252 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1253 pr_err("page table error\n");
1254 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1255 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1256 POSTING_READ(PGTBL_ER);
8a905236
JB		 1257 }
1258 }
1259
1260 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 1261 pr_err("memory refresh error:\n");
9db4a9c7 1262 for_each_pipe(pipe)
a70491cc 1263 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 1264 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 1265 /* pipestat has already been acked */
1266 }
1267 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 1268 pr_err("instruction error\n");
1269 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
a6c45cf0 1270 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 1271 u32 ipeir = I915_READ(IPEIR);
1272
a70491cc
JP		 1273 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1274 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
1275 pr_err(" INSTDONE: 0x%08x\n", I915_READ(INSTDONE));
1276 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 1277 I915_WRITE(IPEIR, ipeir);
3143a2bf 1278 POSTING_READ(IPEIR);
8a905236
JB		 1279 } else {
1280 u32 ipeir = I915_READ(IPEIR_I965);
1281
a70491cc
JP		 1282 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1283 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1284 pr_err(" INSTDONE: 0x%08x\n",
8a905236 1285 I915_READ(INSTDONE_I965));
a70491cc
JP		 1286 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1287 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1288 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1289 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1290 POSTING_READ(IPEIR_I965);
8a905236
JB		 1291 }
1292 }
1293
1294 I915_WRITE(EIR, eir);
3143a2bf 1295 POSTING_READ(EIR);
8a905236
JB		 1296 eir = I915_READ(EIR);
1297 if (eir) {
1298 /*
1299 * some errors might have become stuck,
1300 * mask them.
1301 */
1302 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1303 I915_WRITE(EMR, I915_READ(EMR) | eir);
1304 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1305 }
35aed2e6
CW		 1306}
1307
1308/**
1309 * i915_handle_error - handle an error interrupt
1310 * @dev: drm device
1311 *
1312 * Do some basic checking of regsiter state at error interrupt time and
1313 * dump it to the syslog. Also call i915_capture_error_state() to make
1314 * sure we get a record and make it available in debugfs. Fire a uevent
1315 * so userspace knows something bad happened (should trigger collection
1316 * of a ring dump etc.).
1317 */
527f9e90 1318void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 1319{
1320 struct drm_i915_private *dev_priv = dev->dev_private;
1321
1322 i915_capture_error_state(dev);
1323 i915_report_and_clear_eir(dev);
8a905236 1324
ba1234d1 1325 if (wedged) {
30dbf0c0 1326 INIT_COMPLETION(dev_priv->error_completion);
ba1234d1
BG		 1327 atomic_set(&dev_priv->mm.wedged, 1);
1328
11ed50ec
BG		 1329 /*
1330 * Wakeup waiting processes so they don't hang
1331 */
1ec14ad3 1332 wake_up_all(&dev_priv->ring[RCS].irq_queue);
f787a5f5 1333 if (HAS_BSD(dev))
1ec14ad3 1334 wake_up_all(&dev_priv->ring[VCS].irq_queue);
549f7365 1335 if (HAS_BLT(dev))
1ec14ad3 1336 wake_up_all(&dev_priv->ring[BCS].irq_queue);
11ed50ec
BG		 1337 }
1338
9c9fe1f8 1339 queue_work(dev_priv->wq, &dev_priv->error_work);
8a905236
JB		 1340}
1341
4e5359cd
SF		 1342static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1343{
1344 drm_i915_private_t *dev_priv = dev->dev_private;
1345 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 1347 struct drm_i915_gem_object *obj;
4e5359cd
SF		 1348 struct intel_unpin_work *work;
1349 unsigned long flags;
1350 bool stall_detected;
1351
1352 /* Ignore early vblank irqs */
1353 if (intel_crtc == NULL)
1354 return;
1355
1356 spin_lock_irqsave(&dev->event_lock, flags);
1357 work = intel_crtc->unpin_work;
1358
1359 if (work == NULL || work->pending || !work->enable_stall_check) {
1360 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1361 spin_unlock_irqrestore(&dev->event_lock, flags);
1362 return;
1363 }
1364
1365 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 1366 obj = work->pending_flip_obj;
a6c45cf0 1367 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 1368 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545
AR		 1369 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1370 obj->gtt_offset;
4e5359cd 1371 } else {
9db4a9c7 1372 int dspaddr = DSPADDR(intel_crtc->plane);
05394f39 1373 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
01f2c773 1374 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 1375 crtc->x * crtc->fb->bits_per_pixel/8);
1376 }
1377
1378 spin_unlock_irqrestore(&dev->event_lock, flags);
1379
1380 if (stall_detected) {
1381 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1382 intel_prepare_page_flip(dev, intel_crtc->plane);
1383 }
1384}
1385
af6061af 1386static int i915_emit_irq(struct drm_device * dev)
1da177e4
LT		 1387{
1388 drm_i915_private_t *dev_priv = dev->dev_private;
7c1c2871 1389 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1da177e4
LT		 1390
1391 i915_kernel_lost_context(dev);
1392
44d98a61 1393 DRM_DEBUG_DRIVER("\n");
1da177e4 1394
c99b058f 1395 dev_priv->counter++;
c29b669c 1396 if (dev_priv->counter > 0x7FFFFFFFUL)
c99b058f 1397 dev_priv->counter = 1;
7c1c2871
DA		 1398 if (master_priv->sarea_priv)
1399 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
c29b669c 1400
e1f99ce6
CW		 1401 if (BEGIN_LP_RING(4) == 0) {
1402 OUT_RING(MI_STORE_DWORD_INDEX);
1403 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1404 OUT_RING(dev_priv->counter);
1405 OUT_RING(MI_USER_INTERRUPT);
1406 ADVANCE_LP_RING();
1407 }
bc5f4523 1408
c29b669c 1409 return dev_priv->counter;
1da177e4
LT		 1410}
1411
84b1fd10 1412static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1da177e4
LT		 1413{
1414 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7c1c2871 1415 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1da177e4 1416 int ret = 0;
1ec14ad3 1417 struct intel_ring_buffer *ring = LP_RING(dev_priv);
1da177e4 1418
44d98a61 1419 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1da177e4
LT		 1420 READ_BREADCRUMB(dev_priv));
1421
ed4cb414 1422 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
7c1c2871
DA		 1423 if (master_priv->sarea_priv)
1424 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1da177e4 1425 return 0;
ed4cb414 1426 }
1da177e4 1427
7c1c2871
DA		 1428 if (master_priv->sarea_priv)
1429 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1da177e4 1430
b13c2b96
CW		 1431 if (ring->irq_get(ring)) {
1432 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
1433 READ_BREADCRUMB(dev_priv) >= irq_nr);
1434 ring->irq_put(ring);
5a9a8d1a
CW		 1435 } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
1436 ret = -EBUSY;
1da177e4 1437
20caafa6 1438 if (ret == -EBUSY) {
3e684eae 1439 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1da177e4
LT		 1440 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1441 }
1442
af6061af
DA		 1443 return ret;
1444}
1445
1da177e4
LT		 1446/* Needs the lock as it touches the ring.
1447 */
c153f45f
EA		 1448int i915_irq_emit(struct drm_device *dev, void *data,
1449 struct drm_file *file_priv)
1da177e4 1450{
1da177e4 1451 drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f 1452 drm_i915_irq_emit_t *emit = data;
1da177e4
LT		 1453 int result;
1454
cd9d4e9f
DV		 1455 if (drm_core_check_feature(dev, DRIVER_MODESET))
1456 return -ENODEV;
1457
1ec14ad3 1458 if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
3e684eae 1459 DRM_ERROR("called with no initialization\n");
20caafa6 1460 return -EINVAL;
1da177e4 1461 }
299eb93c
EA		 1462
1463 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1464
546b0974 1465 mutex_lock(&dev->struct_mutex);
1da177e4 1466 result = i915_emit_irq(dev);
546b0974 1467 mutex_unlock(&dev->struct_mutex);
1da177e4 1468
c153f45f 1469 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1da177e4 1470 DRM_ERROR("copy_to_user\n");
20caafa6 1471 return -EFAULT;
1da177e4
LT		 1472 }
1473
1474 return 0;
1475}
1476
1477/* Doesn't need the hardware lock.
1478 */
c153f45f
EA		 1479int i915_irq_wait(struct drm_device *dev, void *data,
1480 struct drm_file *file_priv)
1da177e4 1481{
1da177e4 1482 drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f 1483 drm_i915_irq_wait_t *irqwait = data;
1da177e4 1484
cd9d4e9f
DV		 1485 if (drm_core_check_feature(dev, DRIVER_MODESET))
1486 return -ENODEV;
1487
1da177e4 1488 if (!dev_priv) {
3e684eae 1489 DRM_ERROR("called with no initialization\n");
20caafa6 1490 return -EINVAL;
1da177e4
LT		 1491 }
1492
c153f45f 1493 return i915_wait_irq(dev, irqwait->irq_seq);
1da177e4
LT		 1494}
1495
42f52ef8
KP		 1496/* Called from drm generic code, passed 'crtc' which
1497 * we use as a pipe index
1498 */
f71d4af4 1499static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1500{
1501 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1502 unsigned long irqflags;
71e0ffa5 1503
5eddb70b 1504 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 1505 return -EINVAL;
0a3e67a4 1506
1ec14ad3 1507 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 1508 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 1509 i915_enable_pipestat(dev_priv, pipe,
1510 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 1511 else
7c463586
KP		 1512 i915_enable_pipestat(dev_priv, pipe,
1513 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 1514
1515 /* maintain vblank delivery even in deep C-states */
1516 if (dev_priv->info->gen == 3)
6b26c86d 1517 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 1518 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 1519
0a3e67a4
JB		 1520 return 0;
1521}
1522
f71d4af4 1523static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1524{
1525 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1526 unsigned long irqflags;
1527
1528 if (!i915_pipe_enabled(dev, pipe))
1529 return -EINVAL;
1530
1531 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1532 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1533 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
f796cf8f
JB		 1534 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1535
1536 return 0;
1537}
1538
f71d4af4 1539static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1540{
1541 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1542 unsigned long irqflags;
1543
1544 if (!i915_pipe_enabled(dev, pipe))
1545 return -EINVAL;
1546
1547 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1548 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1549 DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1550 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1551
1552 return 0;
1553}
1554
7e231dbe
JB		 1555static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1556{
1557 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1558 unsigned long irqflags;
1559 u32 dpfl, imr;
1560
1561 if (!i915_pipe_enabled(dev, pipe))
1562 return -EINVAL;
1563
1564 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1565 dpfl = I915_READ(VLV_DPFLIPSTAT);
1566 imr = I915_READ(VLV_IMR);
1567 if (pipe == 0) {
1568 dpfl |= PIPEA_VBLANK_INT_EN;
1569 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1570 } else {
1571 dpfl |= PIPEA_VBLANK_INT_EN;
1572 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1573 }
1574 I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1575 I915_WRITE(VLV_IMR, imr);
1576 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1577
1578 return 0;
1579}
1580
42f52ef8
KP		 1581/* Called from drm generic code, passed 'crtc' which
1582 * we use as a pipe index
1583 */
f71d4af4 1584static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1585{
1586 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1587 unsigned long irqflags;
0a3e67a4 1588
1ec14ad3 1589 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 1590 if (dev_priv->info->gen == 3)
6b26c86d 1591 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 1592
f796cf8f
JB		 1593 i915_disable_pipestat(dev_priv, pipe,
1594 PIPE_VBLANK_INTERRUPT_ENABLE |
1595 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1596 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1597}
1598
f71d4af4 1599static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1600{
1601 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1602 unsigned long irqflags;
1603
1604 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1605 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1606 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1ec14ad3 1607 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 1608}
1609
f71d4af4 1610static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1611{
1612 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1613 unsigned long irqflags;
1614
1615 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1616 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1617 DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1618 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1619}
1620
7e231dbe
JB		 1621static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1622{
1623 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1624 unsigned long irqflags;
1625 u32 dpfl, imr;
1626
1627 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1628 dpfl = I915_READ(VLV_DPFLIPSTAT);
1629 imr = I915_READ(VLV_IMR);
1630 if (pipe == 0) {
1631 dpfl &= ~PIPEA_VBLANK_INT_EN;
1632 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1633 } else {
1634 dpfl &= ~PIPEB_VBLANK_INT_EN;
1635 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1636 }
1637 I915_WRITE(VLV_IMR, imr);
1638 I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1639 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1640}
1641
1642
702880f2
DA		 1643/* Set the vblank monitor pipe
1644 */
c153f45f
EA		 1645int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1646 struct drm_file *file_priv)
702880f2 1647{
702880f2 1648 drm_i915_private_t *dev_priv = dev->dev_private;
702880f2 1649
cd9d4e9f
DV		 1650 if (drm_core_check_feature(dev, DRIVER_MODESET))
1651 return -ENODEV;
1652
702880f2 1653 if (!dev_priv) {
3e684eae 1654 DRM_ERROR("called with no initialization\n");
20caafa6 1655 return -EINVAL;
702880f2
DA		 1656 }
1657
5b51694a 1658 return 0;
702880f2
DA		 1659}
1660
c153f45f
EA		 1661int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1662 struct drm_file *file_priv)
702880f2 1663{
702880f2 1664 drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f 1665 drm_i915_vblank_pipe_t *pipe = data;
702880f2 1666
cd9d4e9f
DV		 1667 if (drm_core_check_feature(dev, DRIVER_MODESET))
1668 return -ENODEV;
1669
702880f2 1670 if (!dev_priv) {
3e684eae 1671 DRM_ERROR("called with no initialization\n");
20caafa6 1672 return -EINVAL;
702880f2
DA		 1673 }
1674
0a3e67a4 1675 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
c153f45f 1676
702880f2
DA		 1677 return 0;
1678}
1679
a6b54f3f
MD		 1680/**
1681 * Schedule buffer swap at given vertical blank.
1682 */
c153f45f
EA		 1683int i915_vblank_swap(struct drm_device *dev, void *data,
1684 struct drm_file *file_priv)
a6b54f3f 1685{
bd95e0a4
EA		 1686 /* The delayed swap mechanism was fundamentally racy, and has been
1687 * removed. The model was that the client requested a delayed flip/swap
1688 * from the kernel, then waited for vblank before continuing to perform
1689 * rendering. The problem was that the kernel might wake the client
1690 * up before it dispatched the vblank swap (since the lock has to be
1691 * held while touching the ringbuffer), in which case the client would
1692 * clear and start the next frame before the swap occurred, and
1693 * flicker would occur in addition to likely missing the vblank.
1694 *
1695 * In the absence of this ioctl, userland falls back to a correct path
1696 * of waiting for a vblank, then dispatching the swap on its own.
1697 * Context switching to userland and back is plenty fast enough for
1698 * meeting the requirements of vblank swapping.
0a3e67a4 1699 */
bd95e0a4 1700 return -EINVAL;
a6b54f3f
MD		 1701}
1702
893eead0
CW		 1703static u32
1704ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 1705{
893eead0
CW		 1706 return list_entry(ring->request_list.prev,
1707 struct drm_i915_gem_request, list)->seqno;
1708}
1709
1710static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1711{
9574b3fe
BW		 1712 /* We don't check whether the ring even exists before calling this
1713 * function. Hence check whether it's initialized. */
1714 if (ring->obj == NULL)
1715 return true;
1716
893eead0
CW		 1717 if (list_empty(&ring->request_list) ||
1718 i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1719 /* Issue a wake-up to catch stuck h/w. */
9574b3fe
BW		 1720 if (waitqueue_active(&ring->irq_queue)) {
1721 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1722 ring->name);
893eead0
CW		 1723 wake_up_all(&ring->irq_queue);
1724 *err = true;
1725 }
1726 return true;
1727 }
1728 return false;
f65d9421
BG		 1729}
1730
1ec14ad3
CW		 1731static bool kick_ring(struct intel_ring_buffer *ring)
1732{
1733 struct drm_device *dev = ring->dev;
1734 struct drm_i915_private *dev_priv = dev->dev_private;
1735 u32 tmp = I915_READ_CTL(ring);
1736 if (tmp & RING_WAIT) {
1737 DRM_ERROR("Kicking stuck wait on %s\n",
1738 ring->name);
1739 I915_WRITE_CTL(ring, tmp);
1740 return true;
1741 }
1ec14ad3
CW		 1742 return false;
1743}
1744
d1e61e7f
CW		 1745static bool i915_hangcheck_hung(struct drm_device *dev)
1746{
1747 drm_i915_private_t *dev_priv = dev->dev_private;
1748
1749 if (dev_priv->hangcheck_count++ > 1) {
1750 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1751 i915_handle_error(dev, true);
1752
1753 if (!IS_GEN2(dev)) {
1754 /* Is the chip hanging on a WAIT_FOR_EVENT?
1755 * If so we can simply poke the RB_WAIT bit
1756 * and break the hang. This should work on
1757 * all but the second generation chipsets.
1758 */
1759 if (kick_ring(&dev_priv->ring[RCS]))
1760 return false;
1761
1762 if (HAS_BSD(dev) && kick_ring(&dev_priv->ring[VCS]))
1763 return false;
1764
1765 if (HAS_BLT(dev) && kick_ring(&dev_priv->ring[BCS]))
1766 return false;
1767 }
1768
1769 return true;
1770 }
1771
1772 return false;
1773}
1774
f65d9421
BG		 1775/**
1776 * This is called when the chip hasn't reported back with completed
1777 * batchbuffers in a long time. The first time this is called we simply record
1778 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1779 * again, we assume the chip is wedged and try to fix it.
1780 */
1781void i915_hangcheck_elapsed(unsigned long data)
1782{
1783 struct drm_device *dev = (struct drm_device *)data;
1784 drm_i915_private_t *dev_priv = dev->dev_private;
097354eb 1785 uint32_t acthd, instdone, instdone1, acthd_bsd, acthd_blt;
893eead0
CW		 1786 bool err = false;
1787
3e0dc6b0
BW		 1788 if (!i915_enable_hangcheck)
1789 return;
1790
893eead0 1791 /* If all work is done then ACTHD clearly hasn't advanced. */
1ec14ad3
CW		 1792 if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) &&
1793 i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) &&
1794 i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) {
d1e61e7f
CW		 1795 if (err) {
1796 if (i915_hangcheck_hung(dev))
1797 return;
1798
893eead0 1799 goto repeat;
d1e61e7f
CW		 1800 }
1801
1802 dev_priv->hangcheck_count = 0;
893eead0
CW		 1803 return;
1804 }
b9201c14 1805
a6c45cf0 1806 if (INTEL_INFO(dev)->gen < 4) {
cbb465e7
CW		 1807 instdone = I915_READ(INSTDONE);
1808 instdone1 = 0;
1809 } else {
cbb465e7
CW		 1810 instdone = I915_READ(INSTDONE_I965);
1811 instdone1 = I915_READ(INSTDONE1);
1812 }
097354eb
DV		 1813 acthd = intel_ring_get_active_head(&dev_priv->ring[RCS]);
1814 acthd_bsd = HAS_BSD(dev) ?
1815 intel_ring_get_active_head(&dev_priv->ring[VCS]) : 0;
1816 acthd_blt = HAS_BLT(dev) ?
1817 intel_ring_get_active_head(&dev_priv->ring[BCS]) : 0;
f65d9421 1818
cbb465e7 1819 if (dev_priv->last_acthd == acthd &&
097354eb
DV		 1820 dev_priv->last_acthd_bsd == acthd_bsd &&
1821 dev_priv->last_acthd_blt == acthd_blt &&
cbb465e7
CW		 1822 dev_priv->last_instdone == instdone &&
1823 dev_priv->last_instdone1 == instdone1) {
d1e61e7f 1824 if (i915_hangcheck_hung(dev))
cbb465e7 1825 return;
cbb465e7
CW		 1826 } else {
1827 dev_priv->hangcheck_count = 0;
1828
1829 dev_priv->last_acthd = acthd;
097354eb
DV		 1830 dev_priv->last_acthd_bsd = acthd_bsd;
1831 dev_priv->last_acthd_blt = acthd_blt;
cbb465e7
CW		 1832 dev_priv->last_instdone = instdone;
1833 dev_priv->last_instdone1 = instdone1;
1834 }
f65d9421 1835
893eead0 1836repeat:
f65d9421 1837 /* Reset timer case chip hangs without another request being added */
b3b079db
CW		 1838 mod_timer(&dev_priv->hangcheck_timer,
1839 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
f65d9421
BG		 1840}
1841
1da177e4
LT		 1842/* drm_dma.h hooks
1843*/
f71d4af4 1844static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 1845{
1846 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1847
4697995b
JB		 1848 atomic_set(&dev_priv->irq_received, 0);
1849
4697995b 1850
036a4a7d 1851 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 1852
036a4a7d
ZW		 1853 /* XXX hotplug from PCH */
1854
1855 I915_WRITE(DEIMR, 0xffffffff);
1856 I915_WRITE(DEIER, 0x0);
3143a2bf 1857 POSTING_READ(DEIER);
036a4a7d
ZW		 1858
1859 /* and GT */
1860 I915_WRITE(GTIMR, 0xffffffff);
1861 I915_WRITE(GTIER, 0x0);
3143a2bf 1862 POSTING_READ(GTIER);
c650156a
ZW		 1863
1864 /* south display irq */
1865 I915_WRITE(SDEIMR, 0xffffffff);
1866 I915_WRITE(SDEIER, 0x0);
3143a2bf 1867 POSTING_READ(SDEIER);
036a4a7d
ZW		 1868}
1869
7e231dbe
JB		 1870static void valleyview_irq_preinstall(struct drm_device *dev)
1871{
1872 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1873 int pipe;
1874
1875 atomic_set(&dev_priv->irq_received, 0);
1876
7e231dbe
JB		 1877 /* VLV magic */
1878 I915_WRITE(VLV_IMR, 0);
1879 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1880 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1881 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1882
7e231dbe
JB		 1883 /* and GT */
1884 I915_WRITE(GTIIR, I915_READ(GTIIR));
1885 I915_WRITE(GTIIR, I915_READ(GTIIR));
1886 I915_WRITE(GTIMR, 0xffffffff);
1887 I915_WRITE(GTIER, 0x0);
1888 POSTING_READ(GTIER);
1889
1890 I915_WRITE(DPINVGTT, 0xff);
1891
1892 I915_WRITE(PORT_HOTPLUG_EN, 0);
1893 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1894 for_each_pipe(pipe)
1895 I915_WRITE(PIPESTAT(pipe), 0xffff);
1896 I915_WRITE(VLV_IIR, 0xffffffff);
1897 I915_WRITE(VLV_IMR, 0xffffffff);
1898 I915_WRITE(VLV_IER, 0x0);
1899 POSTING_READ(VLV_IER);
1900}
1901
7fe0b973
KP		 1902/*
1903 * Enable digital hotplug on the PCH, and configure the DP short pulse
1904 * duration to 2ms (which is the minimum in the Display Port spec)
1905 *
1906 * This register is the same on all known PCH chips.
1907 */
1908
1909static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1910{
1911 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1912 u32 hotplug;
1913
1914 hotplug = I915_READ(PCH_PORT_HOTPLUG);
1915 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1916 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1917 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1918 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1919 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1920}
1921
f71d4af4 1922static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d
ZW		 1923{
1924 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1925 /* enable kind of interrupts always enabled */
013d5aa2
JB		 1926 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1927 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1ec14ad3 1928 u32 render_irqs;
2d7b8366 1929 u32 hotplug_mask;
036a4a7d 1930
4697995b 1931 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1ec14ad3 1932 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 1933
1934 /* should always can generate irq */
1935 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3
CW		 1936 I915_WRITE(DEIMR, dev_priv->irq_mask);
1937 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
3143a2bf 1938 POSTING_READ(DEIER);
036a4a7d 1939
1ec14ad3 1940 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 1941
1942 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 1943 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 1944
1ec14ad3
CW		 1945 if (IS_GEN6(dev))
1946 render_irqs =
1947 GT_USER_INTERRUPT |
e2a1e2f0
BW		 1948 GEN6_BSD_USER_INTERRUPT |
1949 GEN6_BLITTER_USER_INTERRUPT;
1ec14ad3
CW		 1950 else
1951 render_irqs =
88f23b8f 1952 GT_USER_INTERRUPT |
c6df541c 1953 GT_PIPE_NOTIFY |
1ec14ad3
CW		 1954 GT_BSD_USER_INTERRUPT;
1955 I915_WRITE(GTIER, render_irqs);
3143a2bf 1956 POSTING_READ(GTIER);
036a4a7d 1957
2d7b8366 1958 if (HAS_PCH_CPT(dev)) {
9035a97a
CW		 1959 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1960 SDE_PORTB_HOTPLUG_CPT |
1961 SDE_PORTC_HOTPLUG_CPT |
1962 SDE_PORTD_HOTPLUG_CPT);
2d7b8366 1963 } else {
9035a97a
CW		 1964 hotplug_mask = (SDE_CRT_HOTPLUG |
1965 SDE_PORTB_HOTPLUG |
1966 SDE_PORTC_HOTPLUG |
1967 SDE_PORTD_HOTPLUG |
1968 SDE_AUX_MASK);
2d7b8366
YL		 1969 }
1970
1ec14ad3 1971 dev_priv->pch_irq_mask = ~hotplug_mask;
c650156a
ZW		 1972
1973 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1ec14ad3
CW		 1974 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1975 I915_WRITE(SDEIER, hotplug_mask);
3143a2bf 1976 POSTING_READ(SDEIER);
c650156a 1977
7fe0b973
KP		 1978 ironlake_enable_pch_hotplug(dev);
1979
f97108d1
JB		 1980 if (IS_IRONLAKE_M(dev)) {
1981 /* Clear & enable PCU event interrupts */
1982 I915_WRITE(DEIIR, DE_PCU_EVENT);
1983 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1984 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1985 }
1986
036a4a7d
ZW		 1987 return 0;
1988}
1989
f71d4af4 1990static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 1991{
1992 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1993 /* enable kind of interrupts always enabled */
1994 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
1995 DE_PCH_EVENT_IVB | DE_PLANEA_FLIP_DONE_IVB |
1996 DE_PLANEB_FLIP_DONE_IVB;
1997 u32 render_irqs;
1998 u32 hotplug_mask;
1999
b1f14ad0
JB		 2000 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
2001 dev_priv->irq_mask = ~display_mask;
2002
2003 /* should always can generate irq */
2004 I915_WRITE(DEIIR, I915_READ(DEIIR));
2005 I915_WRITE(DEIMR, dev_priv->irq_mask);
2006 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK_IVB |
2007 DE_PIPEB_VBLANK_IVB);
2008 POSTING_READ(DEIER);
2009
2010 dev_priv->gt_irq_mask = ~0;
2011
2012 I915_WRITE(GTIIR, I915_READ(GTIIR));
2013 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2014
e2a1e2f0
BW		 2015 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2016 GEN6_BLITTER_USER_INTERRUPT;
b1f14ad0
JB		 2017 I915_WRITE(GTIER, render_irqs);
2018 POSTING_READ(GTIER);
2019
2020 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
2021 SDE_PORTB_HOTPLUG_CPT |
2022 SDE_PORTC_HOTPLUG_CPT |
2023 SDE_PORTD_HOTPLUG_CPT);
2024 dev_priv->pch_irq_mask = ~hotplug_mask;
2025
2026 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2027 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
2028 I915_WRITE(SDEIER, hotplug_mask);
2029 POSTING_READ(SDEIER);
2030
7fe0b973
KP		 2031 ironlake_enable_pch_hotplug(dev);
2032
b1f14ad0
JB		 2033 return 0;
2034}
2035
7e231dbe
JB		 2036static int valleyview_irq_postinstall(struct drm_device *dev)
2037{
2038 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2039 u32 render_irqs;
2040 u32 enable_mask;
2041 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2042 u16 msid;
2043
2044 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2045 enable_mask |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2046 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2047
2048 dev_priv->irq_mask = ~enable_mask;
2049
7e231dbe
JB		 2050 dev_priv->pipestat[0] = 0;
2051 dev_priv->pipestat[1] = 0;
2052
2053 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
2054
2055 /* Hack for broken MSIs on VLV */
2056 pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
2057 pci_read_config_word(dev->pdev, 0x98, &msid);
2058 msid &= 0xff; /* mask out delivery bits */
2059 msid |= (1<<14);
2060 pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
2061
2062 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2063 I915_WRITE(VLV_IER, enable_mask);
2064 I915_WRITE(VLV_IIR, 0xffffffff);
2065 I915_WRITE(PIPESTAT(0), 0xffff);
2066 I915_WRITE(PIPESTAT(1), 0xffff);
2067 POSTING_READ(VLV_IER);
2068
2069 I915_WRITE(VLV_IIR, 0xffffffff);
2070 I915_WRITE(VLV_IIR, 0xffffffff);
2071
2072 render_irqs = GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
2073 GT_GEN6_BLT_CS_ERROR_INTERRUPT |
e2a1e2f0 2074 GT_GEN6_BLT_USER_INTERRUPT |
7e231dbe
JB		 2075 GT_GEN6_BSD_USER_INTERRUPT |
2076 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
2077 GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
2078 GT_PIPE_NOTIFY |
2079 GT_RENDER_CS_ERROR_INTERRUPT |
2080 GT_SYNC_STATUS |
2081 GT_USER_INTERRUPT;
2082
2083 dev_priv->gt_irq_mask = ~render_irqs;
2084
2085 I915_WRITE(GTIIR, I915_READ(GTIIR));
2086 I915_WRITE(GTIIR, I915_READ(GTIIR));
2087 I915_WRITE(GTIMR, 0);
2088 I915_WRITE(GTIER, render_irqs);
2089 POSTING_READ(GTIER);
2090
2091 /* ack & enable invalid PTE error interrupts */
2092#if 0 /* FIXME: add support to irq handler for checking these bits */
2093 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2094 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2095#endif
2096
2097 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2098#if 0 /* FIXME: check register definitions; some have moved */
2099 /* Note HDMI and DP share bits */
2100 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2101 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2102 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2103 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2104 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2105 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2106 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2107 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2108 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2109 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2110 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2111 hotplug_en |= CRT_HOTPLUG_INT_EN;
2112 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2113 }
2114#endif
2115
2116 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2117
2118 return 0;
2119}
2120
7e231dbe
JB		 2121static void valleyview_irq_uninstall(struct drm_device *dev)
2122{
2123 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2124 int pipe;
2125
2126 if (!dev_priv)
2127 return;
2128
2129 dev_priv->vblank_pipe = 0;
2130
2131 for_each_pipe(pipe)
2132 I915_WRITE(PIPESTAT(pipe), 0xffff);
2133
2134 I915_WRITE(HWSTAM, 0xffffffff);
2135 I915_WRITE(PORT_HOTPLUG_EN, 0);
2136 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2137 for_each_pipe(pipe)
2138 I915_WRITE(PIPESTAT(pipe), 0xffff);
2139 I915_WRITE(VLV_IIR, 0xffffffff);
2140 I915_WRITE(VLV_IMR, 0xffffffff);
2141 I915_WRITE(VLV_IER, 0x0);
2142 POSTING_READ(VLV_IER);
2143}
2144
f71d4af4 2145static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 2146{
2147 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 2148
2149 if (!dev_priv)
2150 return;
2151
2152 dev_priv->vblank_pipe = 0;
2153
036a4a7d
ZW		 2154 I915_WRITE(HWSTAM, 0xffffffff);
2155
2156 I915_WRITE(DEIMR, 0xffffffff);
2157 I915_WRITE(DEIER, 0x0);
2158 I915_WRITE(DEIIR, I915_READ(DEIIR));
2159
2160 I915_WRITE(GTIMR, 0xffffffff);
2161 I915_WRITE(GTIER, 0x0);
2162 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f
KP		 2163
2164 I915_WRITE(SDEIMR, 0xffffffff);
2165 I915_WRITE(SDEIER, 0x0);
2166 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
036a4a7d
ZW		 2167}
2168
a266c7d5 2169static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 2170{
2171 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2172 int pipe;
91e3738e 2173
a266c7d5 2174 atomic_set(&dev_priv->irq_received, 0);
5ca58282 2175
9db4a9c7
JB		 2176 for_each_pipe(pipe)
2177 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 2178 I915_WRITE16(IMR, 0xffff);
2179 I915_WRITE16(IER, 0x0);
2180 POSTING_READ16(IER);
c2798b19
CW		 2181}
2182
2183static int i8xx_irq_postinstall(struct drm_device *dev)
2184{
2185 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2186
2187 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
2188
2189 dev_priv->pipestat[0] = 0;
2190 dev_priv->pipestat[1] = 0;
2191
2192 I915_WRITE16(EMR,
2193 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2194
2195 /* Unmask the interrupts that we always want on. */
2196 dev_priv->irq_mask =
2197 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2198 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2199 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2200 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2201 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2202 I915_WRITE16(IMR, dev_priv->irq_mask);
2203
2204 I915_WRITE16(IER,
2205 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2206 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2207 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2208 I915_USER_INTERRUPT);
2209 POSTING_READ16(IER);
2210
2211 return 0;
2212}
2213
2214static irqreturn_t i8xx_irq_handler(DRM_IRQ_ARGS)
2215{
2216 struct drm_device *dev = (struct drm_device *) arg;
2217 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2218 struct drm_i915_master_private *master_priv;
2219 u16 iir, new_iir;
2220 u32 pipe_stats[2];
2221 unsigned long irqflags;
2222 int irq_received;
2223 int pipe;
2224 u16 flip_mask =
2225 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2226 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2227
2228 atomic_inc(&dev_priv->irq_received);
2229
2230 iir = I915_READ16(IIR);
2231 if (iir == 0)
2232 return IRQ_NONE;
2233
2234 while (iir & ~flip_mask) {
2235 /* Can't rely on pipestat interrupt bit in iir as it might
2236 * have been cleared after the pipestat interrupt was received.
2237 * It doesn't set the bit in iir again, but it still produces
2238 * interrupts (for non-MSI).
2239 */
2240 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2241 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2242 i915_handle_error(dev, false);
2243
2244 for_each_pipe(pipe) {
2245 int reg = PIPESTAT(pipe);
2246 pipe_stats[pipe] = I915_READ(reg);
2247
2248 /*
2249 * Clear the PIPE*STAT regs before the IIR
2250 */
2251 if (pipe_stats[pipe] & 0x8000ffff) {
2252 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2253 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2254 pipe_name(pipe));
2255 I915_WRITE(reg, pipe_stats[pipe]);
2256 irq_received = 1;
2257 }
2258 }
2259 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2260
2261 I915_WRITE16(IIR, iir & ~flip_mask);
2262 new_iir = I915_READ16(IIR); /* Flush posted writes */
2263
2264 if (dev->primary->master) {
2265 master_priv = dev->primary->master->driver_priv;
2266 if (master_priv->sarea_priv)
2267 master_priv->sarea_priv->last_dispatch =
2268 READ_BREADCRUMB(dev_priv);
2269 }
2270
2271 if (iir & I915_USER_INTERRUPT)
2272 notify_ring(dev, &dev_priv->ring[RCS]);
2273
2274 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2275 drm_handle_vblank(dev, 0)) {
2276 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2277 intel_prepare_page_flip(dev, 0);
2278 intel_finish_page_flip(dev, 0);
2279 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2280 }
2281 }
2282
2283 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2284 drm_handle_vblank(dev, 1)) {
2285 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2286 intel_prepare_page_flip(dev, 1);
2287 intel_finish_page_flip(dev, 1);
2288 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2289 }
2290 }
2291
2292 iir = new_iir;
2293 }
2294
2295 return IRQ_HANDLED;
2296}
2297
2298static void i8xx_irq_uninstall(struct drm_device * dev)
2299{
2300 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2301 int pipe;
2302
2303 dev_priv->vblank_pipe = 0;
2304
2305 for_each_pipe(pipe) {
2306 /* Clear enable bits; then clear status bits */
2307 I915_WRITE(PIPESTAT(pipe), 0);
2308 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2309 }
2310 I915_WRITE16(IMR, 0xffff);
2311 I915_WRITE16(IER, 0x0);
2312 I915_WRITE16(IIR, I915_READ16(IIR));
2313}
2314
a266c7d5
CW		 2315static void i915_irq_preinstall(struct drm_device * dev)
2316{
2317 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2318 int pipe;
2319
2320 atomic_set(&dev_priv->irq_received, 0);
2321
2322 if (I915_HAS_HOTPLUG(dev)) {
2323 I915_WRITE(PORT_HOTPLUG_EN, 0);
2324 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2325 }
2326
00d98ebd 2327 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 2328 for_each_pipe(pipe)
2329 I915_WRITE(PIPESTAT(pipe), 0);
2330 I915_WRITE(IMR, 0xffffffff);
2331 I915_WRITE(IER, 0x0);
2332 POSTING_READ(IER);
2333}
2334
2335static int i915_irq_postinstall(struct drm_device *dev)
2336{
2337 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 2338 u32 enable_mask;
a266c7d5
CW		 2339
2340 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
2341
a266c7d5
CW		 2342 dev_priv->pipestat[0] = 0;
2343 dev_priv->pipestat[1] = 0;
2344
38bde180
CW		 2345 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2346
2347 /* Unmask the interrupts that we always want on. */
2348 dev_priv->irq_mask =
2349 ~(I915_ASLE_INTERRUPT |
2350 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2351 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2352 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2353 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2354 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2355
2356 enable_mask =
2357 I915_ASLE_INTERRUPT |
2358 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2359 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2360 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2361 I915_USER_INTERRUPT;
2362
a266c7d5
CW		 2363 if (I915_HAS_HOTPLUG(dev)) {
2364 /* Enable in IER... */
2365 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2366 /* and unmask in IMR */
2367 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2368 }
2369
a266c7d5
CW		 2370 I915_WRITE(IMR, dev_priv->irq_mask);
2371 I915_WRITE(IER, enable_mask);
2372 POSTING_READ(IER);
2373
2374 if (I915_HAS_HOTPLUG(dev)) {
2375 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2376
a266c7d5
CW		 2377 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2378 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2379 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2380 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2381 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2382 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2383 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2384 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2385 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2386 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2387 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2388 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5
CW		 2389 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2390 }
2391
2392 /* Ignore TV since it's buggy */
2393
2394 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2395 }
2396
2397 intel_opregion_enable_asle(dev);
2398
2399 return 0;
2400}
2401
2402static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
2403{
2404 struct drm_device *dev = (struct drm_device *) arg;
2405 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2406 struct drm_i915_master_private *master_priv;
8291ee90 2407 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 2408 unsigned long irqflags;
38bde180
CW		 2409 u32 flip_mask =
2410 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2411 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2412 u32 flip[2] = {
2413 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2414 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2415 };
2416 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 2417
2418 atomic_inc(&dev_priv->irq_received);
2419
2420 iir = I915_READ(IIR);
38bde180
CW		 2421 do {
2422 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 2423 bool blc_event = false;
a266c7d5
CW		 2424
2425 /* Can't rely on pipestat interrupt bit in iir as it might
2426 * have been cleared after the pipestat interrupt was received.
2427 * It doesn't set the bit in iir again, but it still produces
2428 * interrupts (for non-MSI).
2429 */
2430 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2431 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2432 i915_handle_error(dev, false);
2433
2434 for_each_pipe(pipe) {
2435 int reg = PIPESTAT(pipe);
2436 pipe_stats[pipe] = I915_READ(reg);
2437
38bde180 2438 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 2439 if (pipe_stats[pipe] & 0x8000ffff) {
2440 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2441 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2442 pipe_name(pipe));
2443 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 2444 irq_received = true;
a266c7d5
CW		 2445 }
2446 }
2447 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2448
2449 if (!irq_received)
2450 break;
2451
a266c7d5
CW		 2452 /* Consume port. Then clear IIR or we'll miss events */
2453 if ((I915_HAS_HOTPLUG(dev)) &&
2454 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2455 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2456
2457 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2458 hotplug_status);
2459 if (hotplug_status & dev_priv->hotplug_supported_mask)
2460 queue_work(dev_priv->wq,
2461 &dev_priv->hotplug_work);
2462
2463 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 2464 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 2465 }
2466
38bde180 2467 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2468 new_iir = I915_READ(IIR); /* Flush posted writes */
2469
a266c7d5
CW		 2470 if (iir & I915_USER_INTERRUPT)
2471 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 2472
a266c7d5 2473 for_each_pipe(pipe) {
38bde180
CW		 2474 int plane = pipe;
2475 if (IS_MOBILE(dev))
2476 plane = !plane;
8291ee90 2477 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2478 drm_handle_vblank(dev, pipe)) {
38bde180
CW		 2479 if (iir & flip[plane]) {
2480 intel_prepare_page_flip(dev, plane);
2481 intel_finish_page_flip(dev, pipe);
2482 flip_mask &= ~flip[plane];
2483 }
a266c7d5
CW		 2484 }
2485
2486 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2487 blc_event = true;
2488 }
2489
a266c7d5
CW		 2490 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2491 intel_opregion_asle_intr(dev);
2492
2493 /* With MSI, interrupts are only generated when iir
2494 * transitions from zero to nonzero. If another bit got
2495 * set while we were handling the existing iir bits, then
2496 * we would never get another interrupt.
2497 *
2498 * This is fine on non-MSI as well, as if we hit this path
2499 * we avoid exiting the interrupt handler only to generate
2500 * another one.
2501 *
2502 * Note that for MSI this could cause a stray interrupt report
2503 * if an interrupt landed in the time between writing IIR and
2504 * the posting read. This should be rare enough to never
2505 * trigger the 99% of 100,000 interrupts test for disabling
2506 * stray interrupts.
2507 */
38bde180 2508 ret = IRQ_HANDLED;
a266c7d5 2509 iir = new_iir;
38bde180 2510 } while (iir & ~flip_mask);
a266c7d5 2511
8291ee90
CW		 2512 if (dev->primary->master) {
2513 master_priv = dev->primary->master->driver_priv;
2514 if (master_priv->sarea_priv)
2515 master_priv->sarea_priv->last_dispatch =
2516 READ_BREADCRUMB(dev_priv);
2517 }
2518
a266c7d5
CW		 2519 return ret;
2520}
2521
2522static void i915_irq_uninstall(struct drm_device * dev)
2523{
2524 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2525 int pipe;
2526
a266c7d5
CW		 2527 dev_priv->vblank_pipe = 0;
2528
2529 if (I915_HAS_HOTPLUG(dev)) {
2530 I915_WRITE(PORT_HOTPLUG_EN, 0);
2531 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2532 }
2533
00d98ebd 2534 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 2535 for_each_pipe(pipe) {
2536 /* Clear enable bits; then clear status bits */
a266c7d5 2537 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 2538 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2539 }
a266c7d5
CW		 2540 I915_WRITE(IMR, 0xffffffff);
2541 I915_WRITE(IER, 0x0);
2542
a266c7d5
CW		 2543 I915_WRITE(IIR, I915_READ(IIR));
2544}
2545
2546static void i965_irq_preinstall(struct drm_device * dev)
2547{
2548 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2549 int pipe;
2550
2551 atomic_set(&dev_priv->irq_received, 0);
2552
2553 if (I915_HAS_HOTPLUG(dev)) {
2554 I915_WRITE(PORT_HOTPLUG_EN, 0);
2555 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2556 }
2557
2558 I915_WRITE(HWSTAM, 0xeffe);
2559 for_each_pipe(pipe)
2560 I915_WRITE(PIPESTAT(pipe), 0);
2561 I915_WRITE(IMR, 0xffffffff);
2562 I915_WRITE(IER, 0x0);
2563 POSTING_READ(IER);
2564}
2565
2566static int i965_irq_postinstall(struct drm_device *dev)
2567{
2568 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
bbba0a97 2569 u32 enable_mask;
a266c7d5
CW		 2570 u32 error_mask;
2571
2572 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
2573
2574 /* Unmask the interrupts that we always want on. */
bbba0a97
CW		 2575 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2576 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2577 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2578 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2579 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2580 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2581
2582 enable_mask = ~dev_priv->irq_mask;
2583 enable_mask |= I915_USER_INTERRUPT;
2584
2585 if (IS_G4X(dev))
2586 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5
CW		 2587
2588 dev_priv->pipestat[0] = 0;
2589 dev_priv->pipestat[1] = 0;
2590
2591 if (I915_HAS_HOTPLUG(dev)) {
2592 /* Enable in IER... */
2593 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2594 /* and unmask in IMR */
2595 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2596 }
2597
2598 /*
2599 * Enable some error detection, note the instruction error mask
2600 * bit is reserved, so we leave it masked.
2601 */
2602 if (IS_G4X(dev)) {
2603 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2604 GM45_ERROR_MEM_PRIV |
2605 GM45_ERROR_CP_PRIV |
2606 I915_ERROR_MEMORY_REFRESH);
2607 } else {
2608 error_mask = ~(I915_ERROR_PAGE_TABLE |
2609 I915_ERROR_MEMORY_REFRESH);
2610 }
2611 I915_WRITE(EMR, error_mask);
2612
2613 I915_WRITE(IMR, dev_priv->irq_mask);
2614 I915_WRITE(IER, enable_mask);
2615 POSTING_READ(IER);
2616
2617 if (I915_HAS_HOTPLUG(dev)) {
2618 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2619
2620 /* Note HDMI and DP share bits */
2621 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2622 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2623 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2624 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2625 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2626 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2627 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2628 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2629 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2630 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2631 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2632 hotplug_en |= CRT_HOTPLUG_INT_EN;
2633
2634 /* Programming the CRT detection parameters tends
2635 to generate a spurious hotplug event about three
2636 seconds later. So just do it once.
2637 */
2638 if (IS_G4X(dev))
2639 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2640 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2641 }
2642
2643 /* Ignore TV since it's buggy */
2644
2645 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2646 }
2647
2648 intel_opregion_enable_asle(dev);
2649
2650 return 0;
2651}
2652
2653static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS)
2654{
2655 struct drm_device *dev = (struct drm_device *) arg;
2656 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2657 struct drm_i915_master_private *master_priv;
2658 u32 iir, new_iir;
2659 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 2660 unsigned long irqflags;
2661 int irq_received;
2662 int ret = IRQ_NONE, pipe;
a266c7d5
CW		 2663
2664 atomic_inc(&dev_priv->irq_received);
2665
2666 iir = I915_READ(IIR);
2667
a266c7d5 2668 for (;;) {
2c8ba29f
CW		 2669 bool blc_event = false;
2670
a266c7d5
CW		 2671 irq_received = iir != 0;
2672
2673 /* Can't rely on pipestat interrupt bit in iir as it might
2674 * have been cleared after the pipestat interrupt was received.
2675 * It doesn't set the bit in iir again, but it still produces
2676 * interrupts (for non-MSI).
2677 */
2678 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2679 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2680 i915_handle_error(dev, false);
2681
2682 for_each_pipe(pipe) {
2683 int reg = PIPESTAT(pipe);
2684 pipe_stats[pipe] = I915_READ(reg);
2685
2686 /*
2687 * Clear the PIPE*STAT regs before the IIR
2688 */
2689 if (pipe_stats[pipe] & 0x8000ffff) {
2690 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2691 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2692 pipe_name(pipe));
2693 I915_WRITE(reg, pipe_stats[pipe]);
2694 irq_received = 1;
2695 }
2696 }
2697 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2698
2699 if (!irq_received)
2700 break;
2701
2702 ret = IRQ_HANDLED;
2703
2704 /* Consume port. Then clear IIR or we'll miss events */
2705 if ((I915_HAS_HOTPLUG(dev)) &&
2706 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2707 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2708
2709 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2710 hotplug_status);
2711 if (hotplug_status & dev_priv->hotplug_supported_mask)
2712 queue_work(dev_priv->wq,
2713 &dev_priv->hotplug_work);
2714
2715 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2716 I915_READ(PORT_HOTPLUG_STAT);
2717 }
2718
2719 I915_WRITE(IIR, iir);
2720 new_iir = I915_READ(IIR); /* Flush posted writes */
2721
a266c7d5
CW		 2722 if (iir & I915_USER_INTERRUPT)
2723 notify_ring(dev, &dev_priv->ring[RCS]);
2724 if (iir & I915_BSD_USER_INTERRUPT)
2725 notify_ring(dev, &dev_priv->ring[VCS]);
2726
4f7d1e79 2727 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
a266c7d5 2728 intel_prepare_page_flip(dev, 0);
a266c7d5 2729
4f7d1e79 2730 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
a266c7d5 2731 intel_prepare_page_flip(dev, 1);
a266c7d5
CW		 2732
2733 for_each_pipe(pipe) {
2c8ba29f 2734 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2735 drm_handle_vblank(dev, pipe)) {
4f7d1e79
CW		 2736 i915_pageflip_stall_check(dev, pipe);
2737 intel_finish_page_flip(dev, pipe);
a266c7d5
CW		 2738 }
2739
2740 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2741 blc_event = true;
2742 }
2743
2744
2745 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2746 intel_opregion_asle_intr(dev);
2747
2748 /* With MSI, interrupts are only generated when iir
2749 * transitions from zero to nonzero. If another bit got
2750 * set while we were handling the existing iir bits, then
2751 * we would never get another interrupt.
2752 *
2753 * This is fine on non-MSI as well, as if we hit this path
2754 * we avoid exiting the interrupt handler only to generate
2755 * another one.
2756 *
2757 * Note that for MSI this could cause a stray interrupt report
2758 * if an interrupt landed in the time between writing IIR and
2759 * the posting read. This should be rare enough to never
2760 * trigger the 99% of 100,000 interrupts test for disabling
2761 * stray interrupts.
2762 */
2763 iir = new_iir;
2764 }
2765
2c8ba29f
CW		 2766 if (dev->primary->master) {
2767 master_priv = dev->primary->master->driver_priv;
2768 if (master_priv->sarea_priv)
2769 master_priv->sarea_priv->last_dispatch =
2770 READ_BREADCRUMB(dev_priv);
2771 }
2772
a266c7d5
CW		 2773 return ret;
2774}
2775
2776static void i965_irq_uninstall(struct drm_device * dev)
2777{
2778 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2779 int pipe;
2780
2781 if (!dev_priv)
2782 return;
2783
2784 dev_priv->vblank_pipe = 0;
2785
2786 if (I915_HAS_HOTPLUG(dev)) {
2787 I915_WRITE(PORT_HOTPLUG_EN, 0);
2788 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2789 }
2790
2791 I915_WRITE(HWSTAM, 0xffffffff);
2792 for_each_pipe(pipe)
2793 I915_WRITE(PIPESTAT(pipe), 0);
2794 I915_WRITE(IMR, 0xffffffff);
2795 I915_WRITE(IER, 0x0);
2796
2797 for_each_pipe(pipe)
2798 I915_WRITE(PIPESTAT(pipe),
2799 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2800 I915_WRITE(IIR, I915_READ(IIR));
2801}
2802
f71d4af4
JB		 2803void intel_irq_init(struct drm_device *dev)
2804{
8b2e326d
CW		 2805 struct drm_i915_private *dev_priv = dev->dev_private;
2806
2807 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2808 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
2809 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
2810
f71d4af4
JB		 2811 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2812 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7e231dbe
JB		 2813 if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev) ||
2814 IS_VALLEYVIEW(dev)) {
f71d4af4
JB		 2815 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2816 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2817 }
2818
c3613de9
KP		 2819 if (drm_core_check_feature(dev, DRIVER_MODESET))
2820 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2821 else
2822 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 2823 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2824
7e231dbe
JB		 2825 if (IS_VALLEYVIEW(dev)) {
2826 dev->driver->irq_handler = valleyview_irq_handler;
2827 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2828 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2829 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2830 dev->driver->enable_vblank = valleyview_enable_vblank;
2831 dev->driver->disable_vblank = valleyview_disable_vblank;
2832 } else if (IS_IVYBRIDGE(dev)) {
f71d4af4
JB		 2833 /* Share pre & uninstall handlers with ILK/SNB */
2834 dev->driver->irq_handler = ivybridge_irq_handler;
2835 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2836 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2837 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2838 dev->driver->enable_vblank = ivybridge_enable_vblank;
2839 dev->driver->disable_vblank = ivybridge_disable_vblank;
2840 } else if (HAS_PCH_SPLIT(dev)) {
2841 dev->driver->irq_handler = ironlake_irq_handler;
2842 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2843 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2844 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2845 dev->driver->enable_vblank = ironlake_enable_vblank;
2846 dev->driver->disable_vblank = ironlake_disable_vblank;
2847 } else {
c2798b19
CW		 2848 if (INTEL_INFO(dev)->gen == 2) {
2849 dev->driver->irq_preinstall = i8xx_irq_preinstall;
2850 dev->driver->irq_postinstall = i8xx_irq_postinstall;
2851 dev->driver->irq_handler = i8xx_irq_handler;
2852 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5 2853 } else if (INTEL_INFO(dev)->gen == 3) {
4f7d1e79
CW		 2854 /* IIR "flip pending" means done if this bit is set */
2855 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
2856
a266c7d5
CW		 2857 dev->driver->irq_preinstall = i915_irq_preinstall;
2858 dev->driver->irq_postinstall = i915_irq_postinstall;
2859 dev->driver->irq_uninstall = i915_irq_uninstall;
2860 dev->driver->irq_handler = i915_irq_handler;
c2798b19 2861 } else {
a266c7d5
CW		 2862 dev->driver->irq_preinstall = i965_irq_preinstall;
2863 dev->driver->irq_postinstall = i965_irq_postinstall;
2864 dev->driver->irq_uninstall = i965_irq_uninstall;
2865 dev->driver->irq_handler = i965_irq_handler;
c2798b19 2866 }
f71d4af4
JB		 2867 dev->driver->enable_vblank = i915_enable_vblank;
2868 dev->driver->disable_vblank = i915_disable_vblank;
2869 }
2870}
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