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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
63eeaf38 | 31 | #include <linux/sysrq.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
b2c88f5b | 33 | #include <linux/circ_buf.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/i915_drm.h> | |
1da177e4 | 36 | #include "i915_drv.h" |
1c5d22f7 | 37 | #include "i915_trace.h" |
79e53945 | 38 | #include "intel_drv.h" |
1da177e4 | 39 | |
e5868a31 EE |
40 | static const u32 hpd_ibx[] = { |
41 | [HPD_CRT] = SDE_CRT_HOTPLUG, | |
42 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, | |
43 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG, | |
44 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG, | |
45 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG | |
46 | }; | |
47 | ||
48 | static const u32 hpd_cpt[] = { | |
49 | [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, | |
73c352a2 | 50 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, |
e5868a31 EE |
51 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
52 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
53 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT | |
54 | }; | |
55 | ||
56 | static const u32 hpd_mask_i915[] = { | |
57 | [HPD_CRT] = CRT_HOTPLUG_INT_EN, | |
58 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, | |
59 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, | |
60 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, | |
61 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, | |
62 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN | |
63 | }; | |
64 | ||
704cfb87 | 65 | static const u32 hpd_status_g4x[] = { |
e5868a31 EE |
66 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
67 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, | |
68 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, | |
69 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
70 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
71 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
72 | }; | |
73 | ||
e5868a31 EE |
74 | static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ |
75 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, | |
76 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, | |
77 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, | |
78 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
79 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
80 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
81 | }; | |
82 | ||
5c502442 | 83 | /* IIR can theoretically queue up two events. Be paranoid. */ |
f86f3fb0 | 84 | #define GEN8_IRQ_RESET_NDX(type, which) do { \ |
5c502442 PZ |
85 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ |
86 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
87 | I915_WRITE(GEN8_##type##_IER(which), 0); \ | |
88 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
89 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
90 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
91 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
92 | } while (0) | |
93 | ||
f86f3fb0 | 94 | #define GEN5_IRQ_RESET(type) do { \ |
a9d356a6 | 95 | I915_WRITE(type##IMR, 0xffffffff); \ |
5c502442 | 96 | POSTING_READ(type##IMR); \ |
a9d356a6 | 97 | I915_WRITE(type##IER, 0); \ |
5c502442 PZ |
98 | I915_WRITE(type##IIR, 0xffffffff); \ |
99 | POSTING_READ(type##IIR); \ | |
100 | I915_WRITE(type##IIR, 0xffffffff); \ | |
101 | POSTING_READ(type##IIR); \ | |
a9d356a6 PZ |
102 | } while (0) |
103 | ||
337ba017 PZ |
104 | /* |
105 | * We should clear IMR at preinstall/uninstall, and just check at postinstall. | |
106 | */ | |
107 | #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \ | |
108 | u32 val = I915_READ(reg); \ | |
109 | if (val) { \ | |
110 | WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \ | |
111 | (reg), val); \ | |
112 | I915_WRITE((reg), 0xffffffff); \ | |
113 | POSTING_READ(reg); \ | |
114 | I915_WRITE((reg), 0xffffffff); \ | |
115 | POSTING_READ(reg); \ | |
116 | } \ | |
117 | } while (0) | |
118 | ||
35079899 | 119 | #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \ |
337ba017 | 120 | GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \ |
35079899 PZ |
121 | I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \ |
122 | I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \ | |
123 | POSTING_READ(GEN8_##type##_IER(which)); \ | |
124 | } while (0) | |
125 | ||
126 | #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \ | |
337ba017 | 127 | GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \ |
35079899 PZ |
128 | I915_WRITE(type##IMR, (imr_val)); \ |
129 | I915_WRITE(type##IER, (ier_val)); \ | |
130 | POSTING_READ(type##IER); \ | |
131 | } while (0) | |
132 | ||
036a4a7d | 133 | /* For display hotplug interrupt */ |
995b6762 | 134 | static void |
2d1013dd | 135 | ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask) |
036a4a7d | 136 | { |
4bc9d430 DV |
137 | assert_spin_locked(&dev_priv->irq_lock); |
138 | ||
730488b2 | 139 | if (WARN_ON(dev_priv->pm.irqs_disabled)) |
c67a470b | 140 | return; |
c67a470b | 141 | |
1ec14ad3 CW |
142 | if ((dev_priv->irq_mask & mask) != 0) { |
143 | dev_priv->irq_mask &= ~mask; | |
144 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 145 | POSTING_READ(DEIMR); |
036a4a7d ZW |
146 | } |
147 | } | |
148 | ||
0ff9800a | 149 | static void |
2d1013dd | 150 | ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask) |
036a4a7d | 151 | { |
4bc9d430 DV |
152 | assert_spin_locked(&dev_priv->irq_lock); |
153 | ||
730488b2 | 154 | if (WARN_ON(dev_priv->pm.irqs_disabled)) |
c67a470b | 155 | return; |
c67a470b | 156 | |
1ec14ad3 CW |
157 | if ((dev_priv->irq_mask & mask) != mask) { |
158 | dev_priv->irq_mask |= mask; | |
159 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 160 | POSTING_READ(DEIMR); |
036a4a7d ZW |
161 | } |
162 | } | |
163 | ||
43eaea13 PZ |
164 | /** |
165 | * ilk_update_gt_irq - update GTIMR | |
166 | * @dev_priv: driver private | |
167 | * @interrupt_mask: mask of interrupt bits to update | |
168 | * @enabled_irq_mask: mask of interrupt bits to enable | |
169 | */ | |
170 | static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, | |
171 | uint32_t interrupt_mask, | |
172 | uint32_t enabled_irq_mask) | |
173 | { | |
174 | assert_spin_locked(&dev_priv->irq_lock); | |
175 | ||
730488b2 | 176 | if (WARN_ON(dev_priv->pm.irqs_disabled)) |
c67a470b | 177 | return; |
c67a470b | 178 | |
43eaea13 PZ |
179 | dev_priv->gt_irq_mask &= ~interrupt_mask; |
180 | dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); | |
181 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
182 | POSTING_READ(GTIMR); | |
183 | } | |
184 | ||
185 | void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
186 | { | |
187 | ilk_update_gt_irq(dev_priv, mask, mask); | |
188 | } | |
189 | ||
190 | void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
191 | { | |
192 | ilk_update_gt_irq(dev_priv, mask, 0); | |
193 | } | |
194 | ||
edbfdb45 PZ |
195 | /** |
196 | * snb_update_pm_irq - update GEN6_PMIMR | |
197 | * @dev_priv: driver private | |
198 | * @interrupt_mask: mask of interrupt bits to update | |
199 | * @enabled_irq_mask: mask of interrupt bits to enable | |
200 | */ | |
201 | static void snb_update_pm_irq(struct drm_i915_private *dev_priv, | |
202 | uint32_t interrupt_mask, | |
203 | uint32_t enabled_irq_mask) | |
204 | { | |
605cd25b | 205 | uint32_t new_val; |
edbfdb45 PZ |
206 | |
207 | assert_spin_locked(&dev_priv->irq_lock); | |
208 | ||
730488b2 | 209 | if (WARN_ON(dev_priv->pm.irqs_disabled)) |
c67a470b | 210 | return; |
c67a470b | 211 | |
605cd25b | 212 | new_val = dev_priv->pm_irq_mask; |
f52ecbcf PZ |
213 | new_val &= ~interrupt_mask; |
214 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
215 | ||
605cd25b PZ |
216 | if (new_val != dev_priv->pm_irq_mask) { |
217 | dev_priv->pm_irq_mask = new_val; | |
218 | I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask); | |
f52ecbcf PZ |
219 | POSTING_READ(GEN6_PMIMR); |
220 | } | |
edbfdb45 PZ |
221 | } |
222 | ||
223 | void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
224 | { | |
225 | snb_update_pm_irq(dev_priv, mask, mask); | |
226 | } | |
227 | ||
228 | void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
229 | { | |
230 | snb_update_pm_irq(dev_priv, mask, 0); | |
231 | } | |
232 | ||
8664281b PZ |
233 | static bool ivb_can_enable_err_int(struct drm_device *dev) |
234 | { | |
235 | struct drm_i915_private *dev_priv = dev->dev_private; | |
236 | struct intel_crtc *crtc; | |
237 | enum pipe pipe; | |
238 | ||
4bc9d430 DV |
239 | assert_spin_locked(&dev_priv->irq_lock); |
240 | ||
8664281b PZ |
241 | for_each_pipe(pipe) { |
242 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
243 | ||
244 | if (crtc->cpu_fifo_underrun_disabled) | |
245 | return false; | |
246 | } | |
247 | ||
248 | return true; | |
249 | } | |
250 | ||
251 | static bool cpt_can_enable_serr_int(struct drm_device *dev) | |
252 | { | |
253 | struct drm_i915_private *dev_priv = dev->dev_private; | |
254 | enum pipe pipe; | |
255 | struct intel_crtc *crtc; | |
256 | ||
fee884ed DV |
257 | assert_spin_locked(&dev_priv->irq_lock); |
258 | ||
8664281b PZ |
259 | for_each_pipe(pipe) { |
260 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
261 | ||
262 | if (crtc->pch_fifo_underrun_disabled) | |
263 | return false; | |
264 | } | |
265 | ||
266 | return true; | |
267 | } | |
268 | ||
2d9d2b0b VS |
269 | static void i9xx_clear_fifo_underrun(struct drm_device *dev, enum pipe pipe) |
270 | { | |
271 | struct drm_i915_private *dev_priv = dev->dev_private; | |
272 | u32 reg = PIPESTAT(pipe); | |
273 | u32 pipestat = I915_READ(reg) & 0x7fff0000; | |
274 | ||
275 | assert_spin_locked(&dev_priv->irq_lock); | |
276 | ||
277 | I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS); | |
278 | POSTING_READ(reg); | |
279 | } | |
280 | ||
8664281b PZ |
281 | static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev, |
282 | enum pipe pipe, bool enable) | |
283 | { | |
284 | struct drm_i915_private *dev_priv = dev->dev_private; | |
285 | uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN : | |
286 | DE_PIPEB_FIFO_UNDERRUN; | |
287 | ||
288 | if (enable) | |
289 | ironlake_enable_display_irq(dev_priv, bit); | |
290 | else | |
291 | ironlake_disable_display_irq(dev_priv, bit); | |
292 | } | |
293 | ||
294 | static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev, | |
7336df65 | 295 | enum pipe pipe, bool enable) |
8664281b PZ |
296 | { |
297 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8664281b | 298 | if (enable) { |
7336df65 DV |
299 | I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); |
300 | ||
8664281b PZ |
301 | if (!ivb_can_enable_err_int(dev)) |
302 | return; | |
303 | ||
8664281b PZ |
304 | ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB); |
305 | } else { | |
7336df65 DV |
306 | bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB); |
307 | ||
308 | /* Change the state _after_ we've read out the current one. */ | |
8664281b | 309 | ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB); |
7336df65 DV |
310 | |
311 | if (!was_enabled && | |
312 | (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) { | |
313 | DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n", | |
314 | pipe_name(pipe)); | |
315 | } | |
8664281b PZ |
316 | } |
317 | } | |
318 | ||
38d83c96 DV |
319 | static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev, |
320 | enum pipe pipe, bool enable) | |
321 | { | |
322 | struct drm_i915_private *dev_priv = dev->dev_private; | |
323 | ||
324 | assert_spin_locked(&dev_priv->irq_lock); | |
325 | ||
326 | if (enable) | |
327 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN; | |
328 | else | |
329 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN; | |
330 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
331 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
332 | } | |
333 | ||
fee884ed DV |
334 | /** |
335 | * ibx_display_interrupt_update - update SDEIMR | |
336 | * @dev_priv: driver private | |
337 | * @interrupt_mask: mask of interrupt bits to update | |
338 | * @enabled_irq_mask: mask of interrupt bits to enable | |
339 | */ | |
340 | static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, | |
341 | uint32_t interrupt_mask, | |
342 | uint32_t enabled_irq_mask) | |
343 | { | |
344 | uint32_t sdeimr = I915_READ(SDEIMR); | |
345 | sdeimr &= ~interrupt_mask; | |
346 | sdeimr |= (~enabled_irq_mask & interrupt_mask); | |
347 | ||
348 | assert_spin_locked(&dev_priv->irq_lock); | |
349 | ||
730488b2 | 350 | if (WARN_ON(dev_priv->pm.irqs_disabled)) |
c67a470b | 351 | return; |
c67a470b | 352 | |
fee884ed DV |
353 | I915_WRITE(SDEIMR, sdeimr); |
354 | POSTING_READ(SDEIMR); | |
355 | } | |
356 | #define ibx_enable_display_interrupt(dev_priv, bits) \ | |
357 | ibx_display_interrupt_update((dev_priv), (bits), (bits)) | |
358 | #define ibx_disable_display_interrupt(dev_priv, bits) \ | |
359 | ibx_display_interrupt_update((dev_priv), (bits), 0) | |
360 | ||
de28075d DV |
361 | static void ibx_set_fifo_underrun_reporting(struct drm_device *dev, |
362 | enum transcoder pch_transcoder, | |
8664281b PZ |
363 | bool enable) |
364 | { | |
8664281b | 365 | struct drm_i915_private *dev_priv = dev->dev_private; |
de28075d DV |
366 | uint32_t bit = (pch_transcoder == TRANSCODER_A) ? |
367 | SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER; | |
8664281b PZ |
368 | |
369 | if (enable) | |
fee884ed | 370 | ibx_enable_display_interrupt(dev_priv, bit); |
8664281b | 371 | else |
fee884ed | 372 | ibx_disable_display_interrupt(dev_priv, bit); |
8664281b PZ |
373 | } |
374 | ||
375 | static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, | |
376 | enum transcoder pch_transcoder, | |
377 | bool enable) | |
378 | { | |
379 | struct drm_i915_private *dev_priv = dev->dev_private; | |
380 | ||
381 | if (enable) { | |
1dd246fb DV |
382 | I915_WRITE(SERR_INT, |
383 | SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); | |
384 | ||
8664281b PZ |
385 | if (!cpt_can_enable_serr_int(dev)) |
386 | return; | |
387 | ||
fee884ed | 388 | ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
8664281b | 389 | } else { |
1dd246fb DV |
390 | uint32_t tmp = I915_READ(SERR_INT); |
391 | bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT); | |
392 | ||
393 | /* Change the state _after_ we've read out the current one. */ | |
fee884ed | 394 | ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
1dd246fb DV |
395 | |
396 | if (!was_enabled && | |
397 | (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) { | |
398 | DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n", | |
399 | transcoder_name(pch_transcoder)); | |
400 | } | |
8664281b | 401 | } |
8664281b PZ |
402 | } |
403 | ||
404 | /** | |
405 | * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages | |
406 | * @dev: drm device | |
407 | * @pipe: pipe | |
408 | * @enable: true if we want to report FIFO underrun errors, false otherwise | |
409 | * | |
410 | * This function makes us disable or enable CPU fifo underruns for a specific | |
411 | * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun | |
412 | * reporting for one pipe may also disable all the other CPU error interruts for | |
413 | * the other pipes, due to the fact that there's just one interrupt mask/enable | |
414 | * bit for all the pipes. | |
415 | * | |
416 | * Returns the previous state of underrun reporting. | |
417 | */ | |
f88d42f1 ID |
418 | bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, |
419 | enum pipe pipe, bool enable) | |
8664281b PZ |
420 | { |
421 | struct drm_i915_private *dev_priv = dev->dev_private; | |
422 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
423 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8664281b PZ |
424 | bool ret; |
425 | ||
77961eb9 ID |
426 | assert_spin_locked(&dev_priv->irq_lock); |
427 | ||
8664281b PZ |
428 | ret = !intel_crtc->cpu_fifo_underrun_disabled; |
429 | ||
430 | if (enable == ret) | |
431 | goto done; | |
432 | ||
433 | intel_crtc->cpu_fifo_underrun_disabled = !enable; | |
434 | ||
2d9d2b0b VS |
435 | if (enable && (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))) |
436 | i9xx_clear_fifo_underrun(dev, pipe); | |
437 | else if (IS_GEN5(dev) || IS_GEN6(dev)) | |
8664281b PZ |
438 | ironlake_set_fifo_underrun_reporting(dev, pipe, enable); |
439 | else if (IS_GEN7(dev)) | |
7336df65 | 440 | ivybridge_set_fifo_underrun_reporting(dev, pipe, enable); |
38d83c96 DV |
441 | else if (IS_GEN8(dev)) |
442 | broadwell_set_fifo_underrun_reporting(dev, pipe, enable); | |
8664281b PZ |
443 | |
444 | done: | |
f88d42f1 ID |
445 | return ret; |
446 | } | |
447 | ||
448 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, | |
449 | enum pipe pipe, bool enable) | |
450 | { | |
451 | struct drm_i915_private *dev_priv = dev->dev_private; | |
452 | unsigned long flags; | |
453 | bool ret; | |
454 | ||
455 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
456 | ret = __intel_set_cpu_fifo_underrun_reporting(dev, pipe, enable); | |
8664281b | 457 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
f88d42f1 | 458 | |
8664281b PZ |
459 | return ret; |
460 | } | |
461 | ||
91d181dd ID |
462 | static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev, |
463 | enum pipe pipe) | |
464 | { | |
465 | struct drm_i915_private *dev_priv = dev->dev_private; | |
466 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
467 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
468 | ||
469 | return !intel_crtc->cpu_fifo_underrun_disabled; | |
470 | } | |
471 | ||
8664281b PZ |
472 | /** |
473 | * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages | |
474 | * @dev: drm device | |
475 | * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) | |
476 | * @enable: true if we want to report FIFO underrun errors, false otherwise | |
477 | * | |
478 | * This function makes us disable or enable PCH fifo underruns for a specific | |
479 | * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO | |
480 | * underrun reporting for one transcoder may also disable all the other PCH | |
481 | * error interruts for the other transcoders, due to the fact that there's just | |
482 | * one interrupt mask/enable bit for all the transcoders. | |
483 | * | |
484 | * Returns the previous state of underrun reporting. | |
485 | */ | |
486 | bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, | |
487 | enum transcoder pch_transcoder, | |
488 | bool enable) | |
489 | { | |
490 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de28075d DV |
491 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder]; |
492 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8664281b PZ |
493 | unsigned long flags; |
494 | bool ret; | |
495 | ||
de28075d DV |
496 | /* |
497 | * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT | |
498 | * has only one pch transcoder A that all pipes can use. To avoid racy | |
499 | * pch transcoder -> pipe lookups from interrupt code simply store the | |
500 | * underrun statistics in crtc A. Since we never expose this anywhere | |
501 | * nor use it outside of the fifo underrun code here using the "wrong" | |
502 | * crtc on LPT won't cause issues. | |
503 | */ | |
8664281b PZ |
504 | |
505 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
506 | ||
507 | ret = !intel_crtc->pch_fifo_underrun_disabled; | |
508 | ||
509 | if (enable == ret) | |
510 | goto done; | |
511 | ||
512 | intel_crtc->pch_fifo_underrun_disabled = !enable; | |
513 | ||
514 | if (HAS_PCH_IBX(dev)) | |
de28075d | 515 | ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable); |
8664281b PZ |
516 | else |
517 | cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable); | |
518 | ||
519 | done: | |
520 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
521 | return ret; | |
522 | } | |
523 | ||
524 | ||
b5ea642a | 525 | static void |
755e9019 ID |
526 | __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
527 | u32 enable_mask, u32 status_mask) | |
7c463586 | 528 | { |
46c06a30 | 529 | u32 reg = PIPESTAT(pipe); |
755e9019 | 530 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 531 | |
b79480ba DV |
532 | assert_spin_locked(&dev_priv->irq_lock); |
533 | ||
04feced9 VS |
534 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
535 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
536 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
537 | pipe_name(pipe), enable_mask, status_mask)) | |
755e9019 ID |
538 | return; |
539 | ||
540 | if ((pipestat & enable_mask) == enable_mask) | |
46c06a30 VS |
541 | return; |
542 | ||
91d181dd ID |
543 | dev_priv->pipestat_irq_mask[pipe] |= status_mask; |
544 | ||
46c06a30 | 545 | /* Enable the interrupt, clear any pending status */ |
755e9019 | 546 | pipestat |= enable_mask | status_mask; |
46c06a30 VS |
547 | I915_WRITE(reg, pipestat); |
548 | POSTING_READ(reg); | |
7c463586 KP |
549 | } |
550 | ||
b5ea642a | 551 | static void |
755e9019 ID |
552 | __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
553 | u32 enable_mask, u32 status_mask) | |
7c463586 | 554 | { |
46c06a30 | 555 | u32 reg = PIPESTAT(pipe); |
755e9019 | 556 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 557 | |
b79480ba DV |
558 | assert_spin_locked(&dev_priv->irq_lock); |
559 | ||
04feced9 VS |
560 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
561 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
562 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
563 | pipe_name(pipe), enable_mask, status_mask)) | |
46c06a30 VS |
564 | return; |
565 | ||
755e9019 ID |
566 | if ((pipestat & enable_mask) == 0) |
567 | return; | |
568 | ||
91d181dd ID |
569 | dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; |
570 | ||
755e9019 | 571 | pipestat &= ~enable_mask; |
46c06a30 VS |
572 | I915_WRITE(reg, pipestat); |
573 | POSTING_READ(reg); | |
7c463586 KP |
574 | } |
575 | ||
10c59c51 ID |
576 | static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask) |
577 | { | |
578 | u32 enable_mask = status_mask << 16; | |
579 | ||
580 | /* | |
581 | * On pipe A we don't support the PSR interrupt yet, on pipe B the | |
582 | * same bit MBZ. | |
583 | */ | |
584 | if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV)) | |
585 | return 0; | |
586 | ||
587 | enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | | |
588 | SPRITE0_FLIP_DONE_INT_EN_VLV | | |
589 | SPRITE1_FLIP_DONE_INT_EN_VLV); | |
590 | if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV) | |
591 | enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV; | |
592 | if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV) | |
593 | enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; | |
594 | ||
595 | return enable_mask; | |
596 | } | |
597 | ||
755e9019 ID |
598 | void |
599 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
600 | u32 status_mask) | |
601 | { | |
602 | u32 enable_mask; | |
603 | ||
10c59c51 ID |
604 | if (IS_VALLEYVIEW(dev_priv->dev)) |
605 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, | |
606 | status_mask); | |
607 | else | |
608 | enable_mask = status_mask << 16; | |
755e9019 ID |
609 | __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
610 | } | |
611 | ||
612 | void | |
613 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
614 | u32 status_mask) | |
615 | { | |
616 | u32 enable_mask; | |
617 | ||
10c59c51 ID |
618 | if (IS_VALLEYVIEW(dev_priv->dev)) |
619 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, | |
620 | status_mask); | |
621 | else | |
622 | enable_mask = status_mask << 16; | |
755e9019 ID |
623 | __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
624 | } | |
625 | ||
01c66889 | 626 | /** |
f49e38dd | 627 | * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion |
01c66889 | 628 | */ |
f49e38dd | 629 | static void i915_enable_asle_pipestat(struct drm_device *dev) |
01c66889 | 630 | { |
2d1013dd | 631 | struct drm_i915_private *dev_priv = dev->dev_private; |
1ec14ad3 CW |
632 | unsigned long irqflags; |
633 | ||
f49e38dd JN |
634 | if (!dev_priv->opregion.asle || !IS_MOBILE(dev)) |
635 | return; | |
636 | ||
1ec14ad3 | 637 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
01c66889 | 638 | |
755e9019 | 639 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); |
f898780b | 640 | if (INTEL_INFO(dev)->gen >= 4) |
3b6c42e8 | 641 | i915_enable_pipestat(dev_priv, PIPE_A, |
755e9019 | 642 | PIPE_LEGACY_BLC_EVENT_STATUS); |
1ec14ad3 CW |
643 | |
644 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
01c66889 ZY |
645 | } |
646 | ||
0a3e67a4 JB |
647 | /** |
648 | * i915_pipe_enabled - check if a pipe is enabled | |
649 | * @dev: DRM device | |
650 | * @pipe: pipe to check | |
651 | * | |
652 | * Reading certain registers when the pipe is disabled can hang the chip. | |
653 | * Use this routine to make sure the PLL is running and the pipe is active | |
654 | * before reading such registers if unsure. | |
655 | */ | |
656 | static int | |
657 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
658 | { | |
2d1013dd | 659 | struct drm_i915_private *dev_priv = dev->dev_private; |
702e7a56 | 660 | |
a01025af DV |
661 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
662 | /* Locking is horribly broken here, but whatever. */ | |
663 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
664 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
71f8ba6b | 665 | |
a01025af DV |
666 | return intel_crtc->active; |
667 | } else { | |
668 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; | |
669 | } | |
0a3e67a4 JB |
670 | } |
671 | ||
4cdb83ec VS |
672 | static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe) |
673 | { | |
674 | /* Gen2 doesn't have a hardware frame counter */ | |
675 | return 0; | |
676 | } | |
677 | ||
42f52ef8 KP |
678 | /* Called from drm generic code, passed a 'crtc', which |
679 | * we use as a pipe index | |
680 | */ | |
f71d4af4 | 681 | static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
0a3e67a4 | 682 | { |
2d1013dd | 683 | struct drm_i915_private *dev_priv = dev->dev_private; |
0a3e67a4 JB |
684 | unsigned long high_frame; |
685 | unsigned long low_frame; | |
391f75e2 | 686 | u32 high1, high2, low, pixel, vbl_start; |
0a3e67a4 JB |
687 | |
688 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 689 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 690 | "pipe %c\n", pipe_name(pipe)); |
0a3e67a4 JB |
691 | return 0; |
692 | } | |
693 | ||
391f75e2 VS |
694 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
695 | struct intel_crtc *intel_crtc = | |
696 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
697 | const struct drm_display_mode *mode = | |
698 | &intel_crtc->config.adjusted_mode; | |
699 | ||
700 | vbl_start = mode->crtc_vblank_start * mode->crtc_htotal; | |
701 | } else { | |
a2d213dd | 702 | enum transcoder cpu_transcoder = (enum transcoder) pipe; |
391f75e2 VS |
703 | u32 htotal; |
704 | ||
705 | htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1; | |
706 | vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1; | |
707 | ||
708 | vbl_start *= htotal; | |
709 | } | |
710 | ||
9db4a9c7 JB |
711 | high_frame = PIPEFRAME(pipe); |
712 | low_frame = PIPEFRAMEPIXEL(pipe); | |
5eddb70b | 713 | |
0a3e67a4 JB |
714 | /* |
715 | * High & low register fields aren't synchronized, so make sure | |
716 | * we get a low value that's stable across two reads of the high | |
717 | * register. | |
718 | */ | |
719 | do { | |
5eddb70b | 720 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
391f75e2 | 721 | low = I915_READ(low_frame); |
5eddb70b | 722 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
0a3e67a4 JB |
723 | } while (high1 != high2); |
724 | ||
5eddb70b | 725 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
391f75e2 | 726 | pixel = low & PIPE_PIXEL_MASK; |
5eddb70b | 727 | low >>= PIPE_FRAME_LOW_SHIFT; |
391f75e2 VS |
728 | |
729 | /* | |
730 | * The frame counter increments at beginning of active. | |
731 | * Cook up a vblank counter by also checking the pixel | |
732 | * counter against vblank start. | |
733 | */ | |
edc08d0a | 734 | return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; |
0a3e67a4 JB |
735 | } |
736 | ||
f71d4af4 | 737 | static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
9880b7a5 | 738 | { |
2d1013dd | 739 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 740 | int reg = PIPE_FRMCOUNT_GM45(pipe); |
9880b7a5 JB |
741 | |
742 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 743 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 744 | "pipe %c\n", pipe_name(pipe)); |
9880b7a5 JB |
745 | return 0; |
746 | } | |
747 | ||
748 | return I915_READ(reg); | |
749 | } | |
750 | ||
ad3543ed MK |
751 | /* raw reads, only for fast reads of display block, no need for forcewake etc. */ |
752 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) | |
ad3543ed | 753 | |
a225f079 VS |
754 | static int __intel_get_crtc_scanline(struct intel_crtc *crtc) |
755 | { | |
756 | struct drm_device *dev = crtc->base.dev; | |
757 | struct drm_i915_private *dev_priv = dev->dev_private; | |
758 | const struct drm_display_mode *mode = &crtc->config.adjusted_mode; | |
759 | enum pipe pipe = crtc->pipe; | |
760 | int vtotal = mode->crtc_vtotal; | |
761 | int position; | |
762 | ||
763 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
764 | vtotal /= 2; | |
765 | ||
766 | if (IS_GEN2(dev)) | |
767 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; | |
768 | else | |
769 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; | |
770 | ||
771 | /* | |
772 | * Scanline counter increments at leading edge of hsync, and | |
773 | * it starts counting from vtotal-1 on the first active line. | |
774 | * That means the scanline counter value is always one less | |
775 | * than what we would expect. Ie. just after start of vblank, | |
776 | * which also occurs at start of hsync (on the last active line), | |
777 | * the scanline counter will read vblank_start-1. | |
778 | */ | |
779 | return (position + 1) % vtotal; | |
780 | } | |
781 | ||
f71d4af4 | 782 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
abca9e45 VS |
783 | unsigned int flags, int *vpos, int *hpos, |
784 | ktime_t *stime, ktime_t *etime) | |
0af7e4df | 785 | { |
c2baf4b7 VS |
786 | struct drm_i915_private *dev_priv = dev->dev_private; |
787 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
788 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
789 | const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; | |
3aa18df8 | 790 | int position; |
78e8fc6b | 791 | int vbl_start, vbl_end, hsync_start, htotal, vtotal; |
0af7e4df MK |
792 | bool in_vbl = true; |
793 | int ret = 0; | |
ad3543ed | 794 | unsigned long irqflags; |
0af7e4df | 795 | |
c2baf4b7 | 796 | if (!intel_crtc->active) { |
0af7e4df | 797 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
9db4a9c7 | 798 | "pipe %c\n", pipe_name(pipe)); |
0af7e4df MK |
799 | return 0; |
800 | } | |
801 | ||
c2baf4b7 | 802 | htotal = mode->crtc_htotal; |
78e8fc6b | 803 | hsync_start = mode->crtc_hsync_start; |
c2baf4b7 VS |
804 | vtotal = mode->crtc_vtotal; |
805 | vbl_start = mode->crtc_vblank_start; | |
806 | vbl_end = mode->crtc_vblank_end; | |
0af7e4df | 807 | |
d31faf65 VS |
808 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
809 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
810 | vbl_end /= 2; | |
811 | vtotal /= 2; | |
812 | } | |
813 | ||
c2baf4b7 VS |
814 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; |
815 | ||
ad3543ed MK |
816 | /* |
817 | * Lock uncore.lock, as we will do multiple timing critical raw | |
818 | * register reads, potentially with preemption disabled, so the | |
819 | * following code must not block on uncore.lock. | |
820 | */ | |
821 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
78e8fc6b | 822 | |
ad3543ed MK |
823 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ |
824 | ||
825 | /* Get optional system timestamp before query. */ | |
826 | if (stime) | |
827 | *stime = ktime_get(); | |
828 | ||
7c06b08a | 829 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
0af7e4df MK |
830 | /* No obvious pixelcount register. Only query vertical |
831 | * scanout position from Display scan line register. | |
832 | */ | |
a225f079 | 833 | position = __intel_get_crtc_scanline(intel_crtc); |
0af7e4df MK |
834 | } else { |
835 | /* Have access to pixelcount since start of frame. | |
836 | * We can split this into vertical and horizontal | |
837 | * scanout position. | |
838 | */ | |
ad3543ed | 839 | position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; |
0af7e4df | 840 | |
3aa18df8 VS |
841 | /* convert to pixel counts */ |
842 | vbl_start *= htotal; | |
843 | vbl_end *= htotal; | |
844 | vtotal *= htotal; | |
78e8fc6b VS |
845 | |
846 | /* | |
847 | * Start of vblank interrupt is triggered at start of hsync, | |
848 | * just prior to the first active line of vblank. However we | |
849 | * consider lines to start at the leading edge of horizontal | |
850 | * active. So, should we get here before we've crossed into | |
851 | * the horizontal active of the first line in vblank, we would | |
852 | * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that, | |
853 | * always add htotal-hsync_start to the current pixel position. | |
854 | */ | |
855 | position = (position + htotal - hsync_start) % vtotal; | |
0af7e4df MK |
856 | } |
857 | ||
ad3543ed MK |
858 | /* Get optional system timestamp after query. */ |
859 | if (etime) | |
860 | *etime = ktime_get(); | |
861 | ||
862 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ | |
863 | ||
864 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
865 | ||
3aa18df8 VS |
866 | in_vbl = position >= vbl_start && position < vbl_end; |
867 | ||
868 | /* | |
869 | * While in vblank, position will be negative | |
870 | * counting up towards 0 at vbl_end. And outside | |
871 | * vblank, position will be positive counting | |
872 | * up since vbl_end. | |
873 | */ | |
874 | if (position >= vbl_start) | |
875 | position -= vbl_end; | |
876 | else | |
877 | position += vtotal - vbl_end; | |
0af7e4df | 878 | |
7c06b08a | 879 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
3aa18df8 VS |
880 | *vpos = position; |
881 | *hpos = 0; | |
882 | } else { | |
883 | *vpos = position / htotal; | |
884 | *hpos = position - (*vpos * htotal); | |
885 | } | |
0af7e4df | 886 | |
0af7e4df MK |
887 | /* In vblank? */ |
888 | if (in_vbl) | |
889 | ret |= DRM_SCANOUTPOS_INVBL; | |
890 | ||
891 | return ret; | |
892 | } | |
893 | ||
a225f079 VS |
894 | int intel_get_crtc_scanline(struct intel_crtc *crtc) |
895 | { | |
896 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
897 | unsigned long irqflags; | |
898 | int position; | |
899 | ||
900 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
901 | position = __intel_get_crtc_scanline(crtc); | |
902 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
903 | ||
904 | return position; | |
905 | } | |
906 | ||
f71d4af4 | 907 | static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
0af7e4df MK |
908 | int *max_error, |
909 | struct timeval *vblank_time, | |
910 | unsigned flags) | |
911 | { | |
4041b853 | 912 | struct drm_crtc *crtc; |
0af7e4df | 913 | |
7eb552ae | 914 | if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { |
4041b853 | 915 | DRM_ERROR("Invalid crtc %d\n", pipe); |
0af7e4df MK |
916 | return -EINVAL; |
917 | } | |
918 | ||
919 | /* Get drm_crtc to timestamp: */ | |
4041b853 CW |
920 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
921 | if (crtc == NULL) { | |
922 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
923 | return -EINVAL; | |
924 | } | |
925 | ||
926 | if (!crtc->enabled) { | |
927 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); | |
928 | return -EBUSY; | |
929 | } | |
0af7e4df MK |
930 | |
931 | /* Helper routine in DRM core does all the work: */ | |
4041b853 CW |
932 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
933 | vblank_time, flags, | |
7da903ef VS |
934 | crtc, |
935 | &to_intel_crtc(crtc)->config.adjusted_mode); | |
0af7e4df MK |
936 | } |
937 | ||
67c347ff JN |
938 | static bool intel_hpd_irq_event(struct drm_device *dev, |
939 | struct drm_connector *connector) | |
321a1b30 EE |
940 | { |
941 | enum drm_connector_status old_status; | |
942 | ||
943 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); | |
944 | old_status = connector->status; | |
945 | ||
946 | connector->status = connector->funcs->detect(connector, false); | |
67c347ff JN |
947 | if (old_status == connector->status) |
948 | return false; | |
949 | ||
950 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n", | |
321a1b30 EE |
951 | connector->base.id, |
952 | drm_get_connector_name(connector), | |
67c347ff JN |
953 | drm_get_connector_status_name(old_status), |
954 | drm_get_connector_status_name(connector->status)); | |
955 | ||
956 | return true; | |
321a1b30 EE |
957 | } |
958 | ||
5ca58282 JB |
959 | /* |
960 | * Handle hotplug events outside the interrupt handler proper. | |
961 | */ | |
ac4c16c5 EE |
962 | #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000) |
963 | ||
5ca58282 JB |
964 | static void i915_hotplug_work_func(struct work_struct *work) |
965 | { | |
2d1013dd JN |
966 | struct drm_i915_private *dev_priv = |
967 | container_of(work, struct drm_i915_private, hotplug_work); | |
5ca58282 | 968 | struct drm_device *dev = dev_priv->dev; |
c31c4ba3 | 969 | struct drm_mode_config *mode_config = &dev->mode_config; |
cd569aed EE |
970 | struct intel_connector *intel_connector; |
971 | struct intel_encoder *intel_encoder; | |
972 | struct drm_connector *connector; | |
973 | unsigned long irqflags; | |
974 | bool hpd_disabled = false; | |
321a1b30 | 975 | bool changed = false; |
142e2398 | 976 | u32 hpd_event_bits; |
4ef69c7a | 977 | |
52d7eced DV |
978 | /* HPD irq before everything is fully set up. */ |
979 | if (!dev_priv->enable_hotplug_processing) | |
980 | return; | |
981 | ||
a65e34c7 | 982 | mutex_lock(&mode_config->mutex); |
e67189ab JB |
983 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); |
984 | ||
cd569aed | 985 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
142e2398 EE |
986 | |
987 | hpd_event_bits = dev_priv->hpd_event_bits; | |
988 | dev_priv->hpd_event_bits = 0; | |
cd569aed EE |
989 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
990 | intel_connector = to_intel_connector(connector); | |
991 | intel_encoder = intel_connector->encoder; | |
992 | if (intel_encoder->hpd_pin > HPD_NONE && | |
993 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED && | |
994 | connector->polled == DRM_CONNECTOR_POLL_HPD) { | |
995 | DRM_INFO("HPD interrupt storm detected on connector %s: " | |
996 | "switching from hotplug detection to polling\n", | |
997 | drm_get_connector_name(connector)); | |
998 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED; | |
999 | connector->polled = DRM_CONNECTOR_POLL_CONNECT | |
1000 | | DRM_CONNECTOR_POLL_DISCONNECT; | |
1001 | hpd_disabled = true; | |
1002 | } | |
142e2398 EE |
1003 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { |
1004 | DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n", | |
1005 | drm_get_connector_name(connector), intel_encoder->hpd_pin); | |
1006 | } | |
cd569aed EE |
1007 | } |
1008 | /* if there were no outputs to poll, poll was disabled, | |
1009 | * therefore make sure it's enabled when disabling HPD on | |
1010 | * some connectors */ | |
ac4c16c5 | 1011 | if (hpd_disabled) { |
cd569aed | 1012 | drm_kms_helper_poll_enable(dev); |
ac4c16c5 EE |
1013 | mod_timer(&dev_priv->hotplug_reenable_timer, |
1014 | jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY)); | |
1015 | } | |
cd569aed EE |
1016 | |
1017 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
1018 | ||
321a1b30 EE |
1019 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
1020 | intel_connector = to_intel_connector(connector); | |
1021 | intel_encoder = intel_connector->encoder; | |
1022 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { | |
1023 | if (intel_encoder->hot_plug) | |
1024 | intel_encoder->hot_plug(intel_encoder); | |
1025 | if (intel_hpd_irq_event(dev, connector)) | |
1026 | changed = true; | |
1027 | } | |
1028 | } | |
40ee3381 KP |
1029 | mutex_unlock(&mode_config->mutex); |
1030 | ||
321a1b30 EE |
1031 | if (changed) |
1032 | drm_kms_helper_hotplug_event(dev); | |
5ca58282 JB |
1033 | } |
1034 | ||
3ca1cced VS |
1035 | static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv) |
1036 | { | |
1037 | del_timer_sync(&dev_priv->hotplug_reenable_timer); | |
1038 | } | |
1039 | ||
d0ecd7e2 | 1040 | static void ironlake_rps_change_irq_handler(struct drm_device *dev) |
f97108d1 | 1041 | { |
2d1013dd | 1042 | struct drm_i915_private *dev_priv = dev->dev_private; |
b5b72e89 | 1043 | u32 busy_up, busy_down, max_avg, min_avg; |
9270388e | 1044 | u8 new_delay; |
9270388e | 1045 | |
d0ecd7e2 | 1046 | spin_lock(&mchdev_lock); |
f97108d1 | 1047 | |
73edd18f DV |
1048 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
1049 | ||
20e4d407 | 1050 | new_delay = dev_priv->ips.cur_delay; |
9270388e | 1051 | |
7648fa99 | 1052 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
1053 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
1054 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
1055 | max_avg = I915_READ(RCBMAXAVG); |
1056 | min_avg = I915_READ(RCBMINAVG); | |
1057 | ||
1058 | /* Handle RCS change request from hw */ | |
b5b72e89 | 1059 | if (busy_up > max_avg) { |
20e4d407 DV |
1060 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
1061 | new_delay = dev_priv->ips.cur_delay - 1; | |
1062 | if (new_delay < dev_priv->ips.max_delay) | |
1063 | new_delay = dev_priv->ips.max_delay; | |
b5b72e89 | 1064 | } else if (busy_down < min_avg) { |
20e4d407 DV |
1065 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
1066 | new_delay = dev_priv->ips.cur_delay + 1; | |
1067 | if (new_delay > dev_priv->ips.min_delay) | |
1068 | new_delay = dev_priv->ips.min_delay; | |
f97108d1 JB |
1069 | } |
1070 | ||
7648fa99 | 1071 | if (ironlake_set_drps(dev, new_delay)) |
20e4d407 | 1072 | dev_priv->ips.cur_delay = new_delay; |
f97108d1 | 1073 | |
d0ecd7e2 | 1074 | spin_unlock(&mchdev_lock); |
9270388e | 1075 | |
f97108d1 JB |
1076 | return; |
1077 | } | |
1078 | ||
549f7365 CW |
1079 | static void notify_ring(struct drm_device *dev, |
1080 | struct intel_ring_buffer *ring) | |
1081 | { | |
475553de CW |
1082 | if (ring->obj == NULL) |
1083 | return; | |
1084 | ||
814e9b57 | 1085 | trace_i915_gem_request_complete(ring); |
9862e600 | 1086 | |
549f7365 | 1087 | wake_up_all(&ring->irq_queue); |
10cd45b6 | 1088 | i915_queue_hangcheck(dev); |
549f7365 CW |
1089 | } |
1090 | ||
4912d041 | 1091 | static void gen6_pm_rps_work(struct work_struct *work) |
3b8d8d91 | 1092 | { |
2d1013dd JN |
1093 | struct drm_i915_private *dev_priv = |
1094 | container_of(work, struct drm_i915_private, rps.work); | |
edbfdb45 | 1095 | u32 pm_iir; |
dd75fdc8 | 1096 | int new_delay, adj; |
4912d041 | 1097 | |
59cdb63d | 1098 | spin_lock_irq(&dev_priv->irq_lock); |
c6a828d3 DV |
1099 | pm_iir = dev_priv->rps.pm_iir; |
1100 | dev_priv->rps.pm_iir = 0; | |
4848405c | 1101 | /* Make sure not to corrupt PMIMR state used by ringbuffer code */ |
a6706b45 | 1102 | snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
59cdb63d | 1103 | spin_unlock_irq(&dev_priv->irq_lock); |
3b8d8d91 | 1104 | |
60611c13 | 1105 | /* Make sure we didn't queue anything we're not going to process. */ |
a6706b45 | 1106 | WARN_ON(pm_iir & ~dev_priv->pm_rps_events); |
60611c13 | 1107 | |
a6706b45 | 1108 | if ((pm_iir & dev_priv->pm_rps_events) == 0) |
3b8d8d91 JB |
1109 | return; |
1110 | ||
4fc688ce | 1111 | mutex_lock(&dev_priv->rps.hw_lock); |
7b9e0ae6 | 1112 | |
dd75fdc8 | 1113 | adj = dev_priv->rps.last_adj; |
7425034a | 1114 | if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { |
dd75fdc8 CW |
1115 | if (adj > 0) |
1116 | adj *= 2; | |
1117 | else | |
1118 | adj = 1; | |
b39fb297 | 1119 | new_delay = dev_priv->rps.cur_freq + adj; |
7425034a VS |
1120 | |
1121 | /* | |
1122 | * For better performance, jump directly | |
1123 | * to RPe if we're below it. | |
1124 | */ | |
b39fb297 BW |
1125 | if (new_delay < dev_priv->rps.efficient_freq) |
1126 | new_delay = dev_priv->rps.efficient_freq; | |
dd75fdc8 | 1127 | } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { |
b39fb297 BW |
1128 | if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq) |
1129 | new_delay = dev_priv->rps.efficient_freq; | |
dd75fdc8 | 1130 | else |
b39fb297 | 1131 | new_delay = dev_priv->rps.min_freq_softlimit; |
dd75fdc8 CW |
1132 | adj = 0; |
1133 | } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { | |
1134 | if (adj < 0) | |
1135 | adj *= 2; | |
1136 | else | |
1137 | adj = -1; | |
b39fb297 | 1138 | new_delay = dev_priv->rps.cur_freq + adj; |
dd75fdc8 | 1139 | } else { /* unknown event */ |
b39fb297 | 1140 | new_delay = dev_priv->rps.cur_freq; |
dd75fdc8 | 1141 | } |
3b8d8d91 | 1142 | |
79249636 BW |
1143 | /* sysfs frequency interfaces may have snuck in while servicing the |
1144 | * interrupt | |
1145 | */ | |
1272e7b8 | 1146 | new_delay = clamp_t(int, new_delay, |
b39fb297 BW |
1147 | dev_priv->rps.min_freq_softlimit, |
1148 | dev_priv->rps.max_freq_softlimit); | |
27544369 | 1149 | |
b39fb297 | 1150 | dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq; |
dd75fdc8 CW |
1151 | |
1152 | if (IS_VALLEYVIEW(dev_priv->dev)) | |
1153 | valleyview_set_rps(dev_priv->dev, new_delay); | |
1154 | else | |
1155 | gen6_set_rps(dev_priv->dev, new_delay); | |
3b8d8d91 | 1156 | |
4fc688ce | 1157 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 JB |
1158 | } |
1159 | ||
e3689190 BW |
1160 | |
1161 | /** | |
1162 | * ivybridge_parity_work - Workqueue called when a parity error interrupt | |
1163 | * occurred. | |
1164 | * @work: workqueue struct | |
1165 | * | |
1166 | * Doesn't actually do anything except notify userspace. As a consequence of | |
1167 | * this event, userspace should try to remap the bad rows since statistically | |
1168 | * it is likely the same row is more likely to go bad again. | |
1169 | */ | |
1170 | static void ivybridge_parity_work(struct work_struct *work) | |
1171 | { | |
2d1013dd JN |
1172 | struct drm_i915_private *dev_priv = |
1173 | container_of(work, struct drm_i915_private, l3_parity.error_work); | |
e3689190 | 1174 | u32 error_status, row, bank, subbank; |
35a85ac6 | 1175 | char *parity_event[6]; |
e3689190 BW |
1176 | uint32_t misccpctl; |
1177 | unsigned long flags; | |
35a85ac6 | 1178 | uint8_t slice = 0; |
e3689190 BW |
1179 | |
1180 | /* We must turn off DOP level clock gating to access the L3 registers. | |
1181 | * In order to prevent a get/put style interface, acquire struct mutex | |
1182 | * any time we access those registers. | |
1183 | */ | |
1184 | mutex_lock(&dev_priv->dev->struct_mutex); | |
1185 | ||
35a85ac6 BW |
1186 | /* If we've screwed up tracking, just let the interrupt fire again */ |
1187 | if (WARN_ON(!dev_priv->l3_parity.which_slice)) | |
1188 | goto out; | |
1189 | ||
e3689190 BW |
1190 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
1191 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
1192 | POSTING_READ(GEN7_MISCCPCTL); | |
1193 | ||
35a85ac6 BW |
1194 | while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { |
1195 | u32 reg; | |
e3689190 | 1196 | |
35a85ac6 BW |
1197 | slice--; |
1198 | if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev))) | |
1199 | break; | |
e3689190 | 1200 | |
35a85ac6 | 1201 | dev_priv->l3_parity.which_slice &= ~(1<<slice); |
e3689190 | 1202 | |
35a85ac6 | 1203 | reg = GEN7_L3CDERRST1 + (slice * 0x200); |
e3689190 | 1204 | |
35a85ac6 BW |
1205 | error_status = I915_READ(reg); |
1206 | row = GEN7_PARITY_ERROR_ROW(error_status); | |
1207 | bank = GEN7_PARITY_ERROR_BANK(error_status); | |
1208 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); | |
1209 | ||
1210 | I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); | |
1211 | POSTING_READ(reg); | |
1212 | ||
1213 | parity_event[0] = I915_L3_PARITY_UEVENT "=1"; | |
1214 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); | |
1215 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); | |
1216 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); | |
1217 | parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); | |
1218 | parity_event[5] = NULL; | |
1219 | ||
5bdebb18 | 1220 | kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj, |
35a85ac6 | 1221 | KOBJ_CHANGE, parity_event); |
e3689190 | 1222 | |
35a85ac6 BW |
1223 | DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", |
1224 | slice, row, bank, subbank); | |
e3689190 | 1225 | |
35a85ac6 BW |
1226 | kfree(parity_event[4]); |
1227 | kfree(parity_event[3]); | |
1228 | kfree(parity_event[2]); | |
1229 | kfree(parity_event[1]); | |
1230 | } | |
e3689190 | 1231 | |
35a85ac6 | 1232 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
e3689190 | 1233 | |
35a85ac6 BW |
1234 | out: |
1235 | WARN_ON(dev_priv->l3_parity.which_slice); | |
1236 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1237 | ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev)); | |
1238 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1239 | ||
1240 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
e3689190 BW |
1241 | } |
1242 | ||
35a85ac6 | 1243 | static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir) |
e3689190 | 1244 | { |
2d1013dd | 1245 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3689190 | 1246 | |
040d2baa | 1247 | if (!HAS_L3_DPF(dev)) |
e3689190 BW |
1248 | return; |
1249 | ||
d0ecd7e2 | 1250 | spin_lock(&dev_priv->irq_lock); |
35a85ac6 | 1251 | ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev)); |
d0ecd7e2 | 1252 | spin_unlock(&dev_priv->irq_lock); |
e3689190 | 1253 | |
35a85ac6 BW |
1254 | iir &= GT_PARITY_ERROR(dev); |
1255 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) | |
1256 | dev_priv->l3_parity.which_slice |= 1 << 1; | |
1257 | ||
1258 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) | |
1259 | dev_priv->l3_parity.which_slice |= 1 << 0; | |
1260 | ||
a4da4fa4 | 1261 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
e3689190 BW |
1262 | } |
1263 | ||
f1af8fc1 PZ |
1264 | static void ilk_gt_irq_handler(struct drm_device *dev, |
1265 | struct drm_i915_private *dev_priv, | |
1266 | u32 gt_iir) | |
1267 | { | |
1268 | if (gt_iir & | |
1269 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
1270 | notify_ring(dev, &dev_priv->ring[RCS]); | |
1271 | if (gt_iir & ILK_BSD_USER_INTERRUPT) | |
1272 | notify_ring(dev, &dev_priv->ring[VCS]); | |
1273 | } | |
1274 | ||
e7b4c6b1 DV |
1275 | static void snb_gt_irq_handler(struct drm_device *dev, |
1276 | struct drm_i915_private *dev_priv, | |
1277 | u32 gt_iir) | |
1278 | { | |
1279 | ||
cc609d5d BW |
1280 | if (gt_iir & |
1281 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
e7b4c6b1 | 1282 | notify_ring(dev, &dev_priv->ring[RCS]); |
cc609d5d | 1283 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
e7b4c6b1 | 1284 | notify_ring(dev, &dev_priv->ring[VCS]); |
cc609d5d | 1285 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
e7b4c6b1 DV |
1286 | notify_ring(dev, &dev_priv->ring[BCS]); |
1287 | ||
cc609d5d BW |
1288 | if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | |
1289 | GT_BSD_CS_ERROR_INTERRUPT | | |
1290 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) { | |
58174462 MK |
1291 | i915_handle_error(dev, false, "GT error interrupt 0x%08x", |
1292 | gt_iir); | |
e7b4c6b1 | 1293 | } |
e3689190 | 1294 | |
35a85ac6 BW |
1295 | if (gt_iir & GT_PARITY_ERROR(dev)) |
1296 | ivybridge_parity_error_irq_handler(dev, gt_iir); | |
e7b4c6b1 DV |
1297 | } |
1298 | ||
abd58f01 BW |
1299 | static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev, |
1300 | struct drm_i915_private *dev_priv, | |
1301 | u32 master_ctl) | |
1302 | { | |
1303 | u32 rcs, bcs, vcs; | |
1304 | uint32_t tmp = 0; | |
1305 | irqreturn_t ret = IRQ_NONE; | |
1306 | ||
1307 | if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { | |
1308 | tmp = I915_READ(GEN8_GT_IIR(0)); | |
1309 | if (tmp) { | |
1310 | ret = IRQ_HANDLED; | |
1311 | rcs = tmp >> GEN8_RCS_IRQ_SHIFT; | |
1312 | bcs = tmp >> GEN8_BCS_IRQ_SHIFT; | |
1313 | if (rcs & GT_RENDER_USER_INTERRUPT) | |
1314 | notify_ring(dev, &dev_priv->ring[RCS]); | |
1315 | if (bcs & GT_RENDER_USER_INTERRUPT) | |
1316 | notify_ring(dev, &dev_priv->ring[BCS]); | |
1317 | I915_WRITE(GEN8_GT_IIR(0), tmp); | |
1318 | } else | |
1319 | DRM_ERROR("The master control interrupt lied (GT0)!\n"); | |
1320 | } | |
1321 | ||
85f9b5f9 | 1322 | if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) { |
abd58f01 BW |
1323 | tmp = I915_READ(GEN8_GT_IIR(1)); |
1324 | if (tmp) { | |
1325 | ret = IRQ_HANDLED; | |
1326 | vcs = tmp >> GEN8_VCS1_IRQ_SHIFT; | |
1327 | if (vcs & GT_RENDER_USER_INTERRUPT) | |
1328 | notify_ring(dev, &dev_priv->ring[VCS]); | |
85f9b5f9 ZY |
1329 | vcs = tmp >> GEN8_VCS2_IRQ_SHIFT; |
1330 | if (vcs & GT_RENDER_USER_INTERRUPT) | |
1331 | notify_ring(dev, &dev_priv->ring[VCS2]); | |
abd58f01 BW |
1332 | I915_WRITE(GEN8_GT_IIR(1), tmp); |
1333 | } else | |
1334 | DRM_ERROR("The master control interrupt lied (GT1)!\n"); | |
1335 | } | |
1336 | ||
1337 | if (master_ctl & GEN8_GT_VECS_IRQ) { | |
1338 | tmp = I915_READ(GEN8_GT_IIR(3)); | |
1339 | if (tmp) { | |
1340 | ret = IRQ_HANDLED; | |
1341 | vcs = tmp >> GEN8_VECS_IRQ_SHIFT; | |
1342 | if (vcs & GT_RENDER_USER_INTERRUPT) | |
1343 | notify_ring(dev, &dev_priv->ring[VECS]); | |
1344 | I915_WRITE(GEN8_GT_IIR(3), tmp); | |
1345 | } else | |
1346 | DRM_ERROR("The master control interrupt lied (GT3)!\n"); | |
1347 | } | |
1348 | ||
1349 | return ret; | |
1350 | } | |
1351 | ||
b543fb04 EE |
1352 | #define HPD_STORM_DETECT_PERIOD 1000 |
1353 | #define HPD_STORM_THRESHOLD 5 | |
1354 | ||
10a504de | 1355 | static inline void intel_hpd_irq_handler(struct drm_device *dev, |
22062dba DV |
1356 | u32 hotplug_trigger, |
1357 | const u32 *hpd) | |
b543fb04 | 1358 | { |
2d1013dd | 1359 | struct drm_i915_private *dev_priv = dev->dev_private; |
b543fb04 | 1360 | int i; |
10a504de | 1361 | bool storm_detected = false; |
b543fb04 | 1362 | |
91d131d2 DV |
1363 | if (!hotplug_trigger) |
1364 | return; | |
1365 | ||
cc9bd499 ID |
1366 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
1367 | hotplug_trigger); | |
1368 | ||
b5ea2d56 | 1369 | spin_lock(&dev_priv->irq_lock); |
b543fb04 | 1370 | for (i = 1; i < HPD_NUM_PINS; i++) { |
821450c6 | 1371 | |
3ff04a16 DV |
1372 | if (hpd[i] & hotplug_trigger && |
1373 | dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) { | |
1374 | /* | |
1375 | * On GMCH platforms the interrupt mask bits only | |
1376 | * prevent irq generation, not the setting of the | |
1377 | * hotplug bits itself. So only WARN about unexpected | |
1378 | * interrupts on saner platforms. | |
1379 | */ | |
1380 | WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev), | |
1381 | "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n", | |
1382 | hotplug_trigger, i, hpd[i]); | |
1383 | ||
1384 | continue; | |
1385 | } | |
b8f102e8 | 1386 | |
b543fb04 EE |
1387 | if (!(hpd[i] & hotplug_trigger) || |
1388 | dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED) | |
1389 | continue; | |
1390 | ||
bc5ead8c | 1391 | dev_priv->hpd_event_bits |= (1 << i); |
b543fb04 EE |
1392 | if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies, |
1393 | dev_priv->hpd_stats[i].hpd_last_jiffies | |
1394 | + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) { | |
1395 | dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies; | |
1396 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
b8f102e8 | 1397 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i); |
b543fb04 EE |
1398 | } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) { |
1399 | dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED; | |
142e2398 | 1400 | dev_priv->hpd_event_bits &= ~(1 << i); |
b543fb04 | 1401 | DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i); |
10a504de | 1402 | storm_detected = true; |
b543fb04 EE |
1403 | } else { |
1404 | dev_priv->hpd_stats[i].hpd_cnt++; | |
b8f102e8 EE |
1405 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i, |
1406 | dev_priv->hpd_stats[i].hpd_cnt); | |
b543fb04 EE |
1407 | } |
1408 | } | |
1409 | ||
10a504de DV |
1410 | if (storm_detected) |
1411 | dev_priv->display.hpd_irq_setup(dev); | |
b5ea2d56 | 1412 | spin_unlock(&dev_priv->irq_lock); |
5876fa0d | 1413 | |
645416f5 DV |
1414 | /* |
1415 | * Our hotplug handler can grab modeset locks (by calling down into the | |
1416 | * fb helpers). Hence it must not be run on our own dev-priv->wq work | |
1417 | * queue for otherwise the flush_work in the pageflip code will | |
1418 | * deadlock. | |
1419 | */ | |
1420 | schedule_work(&dev_priv->hotplug_work); | |
b543fb04 EE |
1421 | } |
1422 | ||
515ac2bb DV |
1423 | static void gmbus_irq_handler(struct drm_device *dev) |
1424 | { | |
2d1013dd | 1425 | struct drm_i915_private *dev_priv = dev->dev_private; |
28c70f16 | 1426 | |
28c70f16 | 1427 | wake_up_all(&dev_priv->gmbus_wait_queue); |
515ac2bb DV |
1428 | } |
1429 | ||
ce99c256 DV |
1430 | static void dp_aux_irq_handler(struct drm_device *dev) |
1431 | { | |
2d1013dd | 1432 | struct drm_i915_private *dev_priv = dev->dev_private; |
9ee32fea | 1433 | |
9ee32fea | 1434 | wake_up_all(&dev_priv->gmbus_wait_queue); |
ce99c256 DV |
1435 | } |
1436 | ||
8bf1e9f1 | 1437 | #if defined(CONFIG_DEBUG_FS) |
277de95e DV |
1438 | static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, |
1439 | uint32_t crc0, uint32_t crc1, | |
1440 | uint32_t crc2, uint32_t crc3, | |
1441 | uint32_t crc4) | |
8bf1e9f1 SH |
1442 | { |
1443 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1444 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; | |
1445 | struct intel_pipe_crc_entry *entry; | |
ac2300d4 | 1446 | int head, tail; |
b2c88f5b | 1447 | |
d538bbdf DL |
1448 | spin_lock(&pipe_crc->lock); |
1449 | ||
0c912c79 | 1450 | if (!pipe_crc->entries) { |
d538bbdf | 1451 | spin_unlock(&pipe_crc->lock); |
0c912c79 DL |
1452 | DRM_ERROR("spurious interrupt\n"); |
1453 | return; | |
1454 | } | |
1455 | ||
d538bbdf DL |
1456 | head = pipe_crc->head; |
1457 | tail = pipe_crc->tail; | |
b2c88f5b DL |
1458 | |
1459 | if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { | |
d538bbdf | 1460 | spin_unlock(&pipe_crc->lock); |
b2c88f5b DL |
1461 | DRM_ERROR("CRC buffer overflowing\n"); |
1462 | return; | |
1463 | } | |
1464 | ||
1465 | entry = &pipe_crc->entries[head]; | |
8bf1e9f1 | 1466 | |
8bc5e955 | 1467 | entry->frame = dev->driver->get_vblank_counter(dev, pipe); |
eba94eb9 DV |
1468 | entry->crc[0] = crc0; |
1469 | entry->crc[1] = crc1; | |
1470 | entry->crc[2] = crc2; | |
1471 | entry->crc[3] = crc3; | |
1472 | entry->crc[4] = crc4; | |
b2c88f5b DL |
1473 | |
1474 | head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
d538bbdf DL |
1475 | pipe_crc->head = head; |
1476 | ||
1477 | spin_unlock(&pipe_crc->lock); | |
07144428 DL |
1478 | |
1479 | wake_up_interruptible(&pipe_crc->wq); | |
8bf1e9f1 | 1480 | } |
277de95e DV |
1481 | #else |
1482 | static inline void | |
1483 | display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, | |
1484 | uint32_t crc0, uint32_t crc1, | |
1485 | uint32_t crc2, uint32_t crc3, | |
1486 | uint32_t crc4) {} | |
1487 | #endif | |
1488 | ||
eba94eb9 | 1489 | |
277de95e | 1490 | static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5a69b89f DV |
1491 | { |
1492 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1493 | ||
277de95e DV |
1494 | display_pipe_crc_irq_handler(dev, pipe, |
1495 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1496 | 0, 0, 0, 0); | |
5a69b89f DV |
1497 | } |
1498 | ||
277de95e | 1499 | static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
eba94eb9 DV |
1500 | { |
1501 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1502 | ||
277de95e DV |
1503 | display_pipe_crc_irq_handler(dev, pipe, |
1504 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1505 | I915_READ(PIPE_CRC_RES_2_IVB(pipe)), | |
1506 | I915_READ(PIPE_CRC_RES_3_IVB(pipe)), | |
1507 | I915_READ(PIPE_CRC_RES_4_IVB(pipe)), | |
1508 | I915_READ(PIPE_CRC_RES_5_IVB(pipe))); | |
eba94eb9 | 1509 | } |
5b3a856b | 1510 | |
277de95e | 1511 | static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5b3a856b DV |
1512 | { |
1513 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0b5c5ed0 DV |
1514 | uint32_t res1, res2; |
1515 | ||
1516 | if (INTEL_INFO(dev)->gen >= 3) | |
1517 | res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); | |
1518 | else | |
1519 | res1 = 0; | |
1520 | ||
1521 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
1522 | res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); | |
1523 | else | |
1524 | res2 = 0; | |
5b3a856b | 1525 | |
277de95e DV |
1526 | display_pipe_crc_irq_handler(dev, pipe, |
1527 | I915_READ(PIPE_CRC_RES_RED(pipe)), | |
1528 | I915_READ(PIPE_CRC_RES_GREEN(pipe)), | |
1529 | I915_READ(PIPE_CRC_RES_BLUE(pipe)), | |
1530 | res1, res2); | |
5b3a856b | 1531 | } |
8bf1e9f1 | 1532 | |
1403c0d4 PZ |
1533 | /* The RPS events need forcewake, so we add them to a work queue and mask their |
1534 | * IMR bits until the work is done. Other interrupts can be processed without | |
1535 | * the work queue. */ | |
1536 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) | |
baf02a1f | 1537 | { |
a6706b45 | 1538 | if (pm_iir & dev_priv->pm_rps_events) { |
59cdb63d | 1539 | spin_lock(&dev_priv->irq_lock); |
a6706b45 D |
1540 | dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; |
1541 | snb_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); | |
59cdb63d | 1542 | spin_unlock(&dev_priv->irq_lock); |
2adbee62 DV |
1543 | |
1544 | queue_work(dev_priv->wq, &dev_priv->rps.work); | |
baf02a1f | 1545 | } |
baf02a1f | 1546 | |
1403c0d4 PZ |
1547 | if (HAS_VEBOX(dev_priv->dev)) { |
1548 | if (pm_iir & PM_VEBOX_USER_INTERRUPT) | |
1549 | notify_ring(dev_priv->dev, &dev_priv->ring[VECS]); | |
12638c57 | 1550 | |
1403c0d4 | 1551 | if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) { |
58174462 MK |
1552 | i915_handle_error(dev_priv->dev, false, |
1553 | "VEBOX CS error interrupt 0x%08x", | |
1554 | pm_iir); | |
1403c0d4 | 1555 | } |
12638c57 | 1556 | } |
baf02a1f BW |
1557 | } |
1558 | ||
8d7849db VS |
1559 | static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe) |
1560 | { | |
1561 | struct intel_crtc *crtc; | |
1562 | ||
1563 | if (!drm_handle_vblank(dev, pipe)) | |
1564 | return false; | |
1565 | ||
1566 | crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
1567 | wake_up(&crtc->vbl_wait); | |
1568 | ||
1569 | return true; | |
1570 | } | |
1571 | ||
c1874ed7 ID |
1572 | static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir) |
1573 | { | |
1574 | struct drm_i915_private *dev_priv = dev->dev_private; | |
91d181dd | 1575 | u32 pipe_stats[I915_MAX_PIPES] = { }; |
c1874ed7 ID |
1576 | int pipe; |
1577 | ||
58ead0d7 | 1578 | spin_lock(&dev_priv->irq_lock); |
c1874ed7 | 1579 | for_each_pipe(pipe) { |
91d181dd | 1580 | int reg; |
bbb5eebf | 1581 | u32 mask, iir_bit = 0; |
91d181dd | 1582 | |
bbb5eebf DV |
1583 | /* |
1584 | * PIPESTAT bits get signalled even when the interrupt is | |
1585 | * disabled with the mask bits, and some of the status bits do | |
1586 | * not generate interrupts at all (like the underrun bit). Hence | |
1587 | * we need to be careful that we only handle what we want to | |
1588 | * handle. | |
1589 | */ | |
1590 | mask = 0; | |
1591 | if (__cpu_fifo_underrun_reporting_enabled(dev, pipe)) | |
1592 | mask |= PIPE_FIFO_UNDERRUN_STATUS; | |
1593 | ||
1594 | switch (pipe) { | |
1595 | case PIPE_A: | |
1596 | iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; | |
1597 | break; | |
1598 | case PIPE_B: | |
1599 | iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
1600 | break; | |
1601 | } | |
1602 | if (iir & iir_bit) | |
1603 | mask |= dev_priv->pipestat_irq_mask[pipe]; | |
1604 | ||
1605 | if (!mask) | |
91d181dd ID |
1606 | continue; |
1607 | ||
1608 | reg = PIPESTAT(pipe); | |
bbb5eebf DV |
1609 | mask |= PIPESTAT_INT_ENABLE_MASK; |
1610 | pipe_stats[pipe] = I915_READ(reg) & mask; | |
c1874ed7 ID |
1611 | |
1612 | /* | |
1613 | * Clear the PIPE*STAT regs before the IIR | |
1614 | */ | |
91d181dd ID |
1615 | if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS | |
1616 | PIPESTAT_INT_STATUS_MASK)) | |
c1874ed7 ID |
1617 | I915_WRITE(reg, pipe_stats[pipe]); |
1618 | } | |
58ead0d7 | 1619 | spin_unlock(&dev_priv->irq_lock); |
c1874ed7 ID |
1620 | |
1621 | for_each_pipe(pipe) { | |
1622 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) | |
8d7849db | 1623 | intel_pipe_handle_vblank(dev, pipe); |
c1874ed7 | 1624 | |
579a9b0e | 1625 | if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) { |
c1874ed7 ID |
1626 | intel_prepare_page_flip(dev, pipe); |
1627 | intel_finish_page_flip(dev, pipe); | |
1628 | } | |
1629 | ||
1630 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
1631 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
1632 | ||
1633 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && | |
1634 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
1635 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); | |
1636 | } | |
1637 | ||
1638 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) | |
1639 | gmbus_irq_handler(dev); | |
1640 | } | |
1641 | ||
16c6c56b VS |
1642 | static void i9xx_hpd_irq_handler(struct drm_device *dev) |
1643 | { | |
1644 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1645 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
1646 | ||
1647 | if (IS_G4X(dev)) { | |
1648 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; | |
1649 | ||
1650 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_g4x); | |
1651 | } else { | |
1652 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; | |
1653 | ||
1654 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); | |
1655 | } | |
1656 | ||
1657 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && | |
1658 | hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) | |
1659 | dp_aux_irq_handler(dev); | |
1660 | ||
1661 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
1662 | /* | |
1663 | * Make sure hotplug status is cleared before we clear IIR, or else we | |
1664 | * may miss hotplug events. | |
1665 | */ | |
1666 | POSTING_READ(PORT_HOTPLUG_STAT); | |
1667 | } | |
1668 | ||
ff1f525e | 1669 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
7e231dbe JB |
1670 | { |
1671 | struct drm_device *dev = (struct drm_device *) arg; | |
2d1013dd | 1672 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
1673 | u32 iir, gt_iir, pm_iir; |
1674 | irqreturn_t ret = IRQ_NONE; | |
7e231dbe | 1675 | |
7e231dbe JB |
1676 | while (true) { |
1677 | iir = I915_READ(VLV_IIR); | |
1678 | gt_iir = I915_READ(GTIIR); | |
1679 | pm_iir = I915_READ(GEN6_PMIIR); | |
1680 | ||
1681 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) | |
1682 | goto out; | |
1683 | ||
1684 | ret = IRQ_HANDLED; | |
1685 | ||
e7b4c6b1 | 1686 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
7e231dbe | 1687 | |
c1874ed7 | 1688 | valleyview_pipestat_irq_handler(dev, iir); |
31acc7f5 | 1689 | |
7e231dbe | 1690 | /* Consume port. Then clear IIR or we'll miss events */ |
16c6c56b VS |
1691 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
1692 | i9xx_hpd_irq_handler(dev); | |
7e231dbe | 1693 | |
60611c13 | 1694 | if (pm_iir) |
d0ecd7e2 | 1695 | gen6_rps_irq_handler(dev_priv, pm_iir); |
7e231dbe JB |
1696 | |
1697 | I915_WRITE(GTIIR, gt_iir); | |
1698 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
1699 | I915_WRITE(VLV_IIR, iir); | |
1700 | } | |
1701 | ||
1702 | out: | |
1703 | return ret; | |
1704 | } | |
1705 | ||
23e81d69 | 1706 | static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) |
776ad806 | 1707 | { |
2d1013dd | 1708 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 1709 | int pipe; |
b543fb04 | 1710 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; |
776ad806 | 1711 | |
91d131d2 DV |
1712 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx); |
1713 | ||
cfc33bf7 VS |
1714 | if (pch_iir & SDE_AUDIO_POWER_MASK) { |
1715 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> | |
1716 | SDE_AUDIO_POWER_SHIFT); | |
776ad806 | 1717 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
cfc33bf7 VS |
1718 | port_name(port)); |
1719 | } | |
776ad806 | 1720 | |
ce99c256 DV |
1721 | if (pch_iir & SDE_AUX_MASK) |
1722 | dp_aux_irq_handler(dev); | |
1723 | ||
776ad806 | 1724 | if (pch_iir & SDE_GMBUS) |
515ac2bb | 1725 | gmbus_irq_handler(dev); |
776ad806 JB |
1726 | |
1727 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
1728 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
1729 | ||
1730 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
1731 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
1732 | ||
1733 | if (pch_iir & SDE_POISON) | |
1734 | DRM_ERROR("PCH poison interrupt\n"); | |
1735 | ||
9db4a9c7 JB |
1736 | if (pch_iir & SDE_FDI_MASK) |
1737 | for_each_pipe(pipe) | |
1738 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", | |
1739 | pipe_name(pipe), | |
1740 | I915_READ(FDI_RX_IIR(pipe))); | |
776ad806 JB |
1741 | |
1742 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
1743 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
1744 | ||
1745 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
1746 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
1747 | ||
776ad806 | 1748 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
8664281b PZ |
1749 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, |
1750 | false)) | |
fc2c807b | 1751 | DRM_ERROR("PCH transcoder A FIFO underrun\n"); |
8664281b PZ |
1752 | |
1753 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
1754 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, | |
1755 | false)) | |
fc2c807b | 1756 | DRM_ERROR("PCH transcoder B FIFO underrun\n"); |
8664281b PZ |
1757 | } |
1758 | ||
1759 | static void ivb_err_int_handler(struct drm_device *dev) | |
1760 | { | |
1761 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1762 | u32 err_int = I915_READ(GEN7_ERR_INT); | |
5a69b89f | 1763 | enum pipe pipe; |
8664281b | 1764 | |
de032bf4 PZ |
1765 | if (err_int & ERR_INT_POISON) |
1766 | DRM_ERROR("Poison interrupt\n"); | |
1767 | ||
5a69b89f DV |
1768 | for_each_pipe(pipe) { |
1769 | if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) { | |
1770 | if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, | |
1771 | false)) | |
fc2c807b VS |
1772 | DRM_ERROR("Pipe %c FIFO underrun\n", |
1773 | pipe_name(pipe)); | |
5a69b89f | 1774 | } |
8bf1e9f1 | 1775 | |
5a69b89f DV |
1776 | if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { |
1777 | if (IS_IVYBRIDGE(dev)) | |
277de95e | 1778 | ivb_pipe_crc_irq_handler(dev, pipe); |
5a69b89f | 1779 | else |
277de95e | 1780 | hsw_pipe_crc_irq_handler(dev, pipe); |
5a69b89f DV |
1781 | } |
1782 | } | |
8bf1e9f1 | 1783 | |
8664281b PZ |
1784 | I915_WRITE(GEN7_ERR_INT, err_int); |
1785 | } | |
1786 | ||
1787 | static void cpt_serr_int_handler(struct drm_device *dev) | |
1788 | { | |
1789 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1790 | u32 serr_int = I915_READ(SERR_INT); | |
1791 | ||
de032bf4 PZ |
1792 | if (serr_int & SERR_INT_POISON) |
1793 | DRM_ERROR("PCH poison interrupt\n"); | |
1794 | ||
8664281b PZ |
1795 | if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) |
1796 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, | |
1797 | false)) | |
fc2c807b | 1798 | DRM_ERROR("PCH transcoder A FIFO underrun\n"); |
8664281b PZ |
1799 | |
1800 | if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) | |
1801 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, | |
1802 | false)) | |
fc2c807b | 1803 | DRM_ERROR("PCH transcoder B FIFO underrun\n"); |
8664281b PZ |
1804 | |
1805 | if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) | |
1806 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C, | |
1807 | false)) | |
fc2c807b | 1808 | DRM_ERROR("PCH transcoder C FIFO underrun\n"); |
8664281b PZ |
1809 | |
1810 | I915_WRITE(SERR_INT, serr_int); | |
776ad806 JB |
1811 | } |
1812 | ||
23e81d69 AJ |
1813 | static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) |
1814 | { | |
2d1013dd | 1815 | struct drm_i915_private *dev_priv = dev->dev_private; |
23e81d69 | 1816 | int pipe; |
b543fb04 | 1817 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; |
23e81d69 | 1818 | |
91d131d2 DV |
1819 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt); |
1820 | ||
cfc33bf7 VS |
1821 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { |
1822 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> | |
1823 | SDE_AUDIO_POWER_SHIFT_CPT); | |
1824 | DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", | |
1825 | port_name(port)); | |
1826 | } | |
23e81d69 AJ |
1827 | |
1828 | if (pch_iir & SDE_AUX_MASK_CPT) | |
ce99c256 | 1829 | dp_aux_irq_handler(dev); |
23e81d69 AJ |
1830 | |
1831 | if (pch_iir & SDE_GMBUS_CPT) | |
515ac2bb | 1832 | gmbus_irq_handler(dev); |
23e81d69 AJ |
1833 | |
1834 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) | |
1835 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); | |
1836 | ||
1837 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) | |
1838 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); | |
1839 | ||
1840 | if (pch_iir & SDE_FDI_MASK_CPT) | |
1841 | for_each_pipe(pipe) | |
1842 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", | |
1843 | pipe_name(pipe), | |
1844 | I915_READ(FDI_RX_IIR(pipe))); | |
8664281b PZ |
1845 | |
1846 | if (pch_iir & SDE_ERROR_CPT) | |
1847 | cpt_serr_int_handler(dev); | |
23e81d69 AJ |
1848 | } |
1849 | ||
c008bc6e PZ |
1850 | static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) |
1851 | { | |
1852 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40da17c2 | 1853 | enum pipe pipe; |
c008bc6e PZ |
1854 | |
1855 | if (de_iir & DE_AUX_CHANNEL_A) | |
1856 | dp_aux_irq_handler(dev); | |
1857 | ||
1858 | if (de_iir & DE_GSE) | |
1859 | intel_opregion_asle_intr(dev); | |
1860 | ||
c008bc6e PZ |
1861 | if (de_iir & DE_POISON) |
1862 | DRM_ERROR("Poison interrupt\n"); | |
1863 | ||
40da17c2 DV |
1864 | for_each_pipe(pipe) { |
1865 | if (de_iir & DE_PIPE_VBLANK(pipe)) | |
8d7849db | 1866 | intel_pipe_handle_vblank(dev, pipe); |
5b3a856b | 1867 | |
40da17c2 DV |
1868 | if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) |
1869 | if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
fc2c807b VS |
1870 | DRM_ERROR("Pipe %c FIFO underrun\n", |
1871 | pipe_name(pipe)); | |
5b3a856b | 1872 | |
40da17c2 DV |
1873 | if (de_iir & DE_PIPE_CRC_DONE(pipe)) |
1874 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
c008bc6e | 1875 | |
40da17c2 DV |
1876 | /* plane/pipes map 1:1 on ilk+ */ |
1877 | if (de_iir & DE_PLANE_FLIP_DONE(pipe)) { | |
1878 | intel_prepare_page_flip(dev, pipe); | |
1879 | intel_finish_page_flip_plane(dev, pipe); | |
1880 | } | |
c008bc6e PZ |
1881 | } |
1882 | ||
1883 | /* check event from PCH */ | |
1884 | if (de_iir & DE_PCH_EVENT) { | |
1885 | u32 pch_iir = I915_READ(SDEIIR); | |
1886 | ||
1887 | if (HAS_PCH_CPT(dev)) | |
1888 | cpt_irq_handler(dev, pch_iir); | |
1889 | else | |
1890 | ibx_irq_handler(dev, pch_iir); | |
1891 | ||
1892 | /* should clear PCH hotplug event before clear CPU irq */ | |
1893 | I915_WRITE(SDEIIR, pch_iir); | |
1894 | } | |
1895 | ||
1896 | if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) | |
1897 | ironlake_rps_change_irq_handler(dev); | |
1898 | } | |
1899 | ||
9719fb98 PZ |
1900 | static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir) |
1901 | { | |
1902 | struct drm_i915_private *dev_priv = dev->dev_private; | |
07d27e20 | 1903 | enum pipe pipe; |
9719fb98 PZ |
1904 | |
1905 | if (de_iir & DE_ERR_INT_IVB) | |
1906 | ivb_err_int_handler(dev); | |
1907 | ||
1908 | if (de_iir & DE_AUX_CHANNEL_A_IVB) | |
1909 | dp_aux_irq_handler(dev); | |
1910 | ||
1911 | if (de_iir & DE_GSE_IVB) | |
1912 | intel_opregion_asle_intr(dev); | |
1913 | ||
07d27e20 DL |
1914 | for_each_pipe(pipe) { |
1915 | if (de_iir & (DE_PIPE_VBLANK_IVB(pipe))) | |
8d7849db | 1916 | intel_pipe_handle_vblank(dev, pipe); |
40da17c2 DV |
1917 | |
1918 | /* plane/pipes map 1:1 on ilk+ */ | |
07d27e20 DL |
1919 | if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) { |
1920 | intel_prepare_page_flip(dev, pipe); | |
1921 | intel_finish_page_flip_plane(dev, pipe); | |
9719fb98 PZ |
1922 | } |
1923 | } | |
1924 | ||
1925 | /* check event from PCH */ | |
1926 | if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) { | |
1927 | u32 pch_iir = I915_READ(SDEIIR); | |
1928 | ||
1929 | cpt_irq_handler(dev, pch_iir); | |
1930 | ||
1931 | /* clear PCH hotplug event before clear CPU irq */ | |
1932 | I915_WRITE(SDEIIR, pch_iir); | |
1933 | } | |
1934 | } | |
1935 | ||
f1af8fc1 | 1936 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
b1f14ad0 JB |
1937 | { |
1938 | struct drm_device *dev = (struct drm_device *) arg; | |
2d1013dd | 1939 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1af8fc1 | 1940 | u32 de_iir, gt_iir, de_ier, sde_ier = 0; |
0e43406b | 1941 | irqreturn_t ret = IRQ_NONE; |
b1f14ad0 | 1942 | |
8664281b PZ |
1943 | /* We get interrupts on unclaimed registers, so check for this before we |
1944 | * do any I915_{READ,WRITE}. */ | |
907b28c5 | 1945 | intel_uncore_check_errors(dev); |
8664281b | 1946 | |
b1f14ad0 JB |
1947 | /* disable master interrupt before clearing iir */ |
1948 | de_ier = I915_READ(DEIER); | |
1949 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
23a78516 | 1950 | POSTING_READ(DEIER); |
b1f14ad0 | 1951 | |
44498aea PZ |
1952 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
1953 | * interrupts will will be stored on its back queue, and then we'll be | |
1954 | * able to process them after we restore SDEIER (as soon as we restore | |
1955 | * it, we'll get an interrupt if SDEIIR still has something to process | |
1956 | * due to its back queue). */ | |
ab5c608b BW |
1957 | if (!HAS_PCH_NOP(dev)) { |
1958 | sde_ier = I915_READ(SDEIER); | |
1959 | I915_WRITE(SDEIER, 0); | |
1960 | POSTING_READ(SDEIER); | |
1961 | } | |
44498aea | 1962 | |
b1f14ad0 | 1963 | gt_iir = I915_READ(GTIIR); |
0e43406b | 1964 | if (gt_iir) { |
d8fc8a47 | 1965 | if (INTEL_INFO(dev)->gen >= 6) |
f1af8fc1 | 1966 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
d8fc8a47 PZ |
1967 | else |
1968 | ilk_gt_irq_handler(dev, dev_priv, gt_iir); | |
0e43406b CW |
1969 | I915_WRITE(GTIIR, gt_iir); |
1970 | ret = IRQ_HANDLED; | |
b1f14ad0 JB |
1971 | } |
1972 | ||
0e43406b CW |
1973 | de_iir = I915_READ(DEIIR); |
1974 | if (de_iir) { | |
f1af8fc1 PZ |
1975 | if (INTEL_INFO(dev)->gen >= 7) |
1976 | ivb_display_irq_handler(dev, de_iir); | |
1977 | else | |
1978 | ilk_display_irq_handler(dev, de_iir); | |
0e43406b CW |
1979 | I915_WRITE(DEIIR, de_iir); |
1980 | ret = IRQ_HANDLED; | |
b1f14ad0 JB |
1981 | } |
1982 | ||
f1af8fc1 PZ |
1983 | if (INTEL_INFO(dev)->gen >= 6) { |
1984 | u32 pm_iir = I915_READ(GEN6_PMIIR); | |
1985 | if (pm_iir) { | |
1403c0d4 | 1986 | gen6_rps_irq_handler(dev_priv, pm_iir); |
f1af8fc1 PZ |
1987 | I915_WRITE(GEN6_PMIIR, pm_iir); |
1988 | ret = IRQ_HANDLED; | |
1989 | } | |
0e43406b | 1990 | } |
b1f14ad0 | 1991 | |
b1f14ad0 JB |
1992 | I915_WRITE(DEIER, de_ier); |
1993 | POSTING_READ(DEIER); | |
ab5c608b BW |
1994 | if (!HAS_PCH_NOP(dev)) { |
1995 | I915_WRITE(SDEIER, sde_ier); | |
1996 | POSTING_READ(SDEIER); | |
1997 | } | |
b1f14ad0 JB |
1998 | |
1999 | return ret; | |
2000 | } | |
2001 | ||
abd58f01 BW |
2002 | static irqreturn_t gen8_irq_handler(int irq, void *arg) |
2003 | { | |
2004 | struct drm_device *dev = arg; | |
2005 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2006 | u32 master_ctl; | |
2007 | irqreturn_t ret = IRQ_NONE; | |
2008 | uint32_t tmp = 0; | |
c42664cc | 2009 | enum pipe pipe; |
abd58f01 | 2010 | |
abd58f01 BW |
2011 | master_ctl = I915_READ(GEN8_MASTER_IRQ); |
2012 | master_ctl &= ~GEN8_MASTER_IRQ_CONTROL; | |
2013 | if (!master_ctl) | |
2014 | return IRQ_NONE; | |
2015 | ||
2016 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
2017 | POSTING_READ(GEN8_MASTER_IRQ); | |
2018 | ||
2019 | ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl); | |
2020 | ||
2021 | if (master_ctl & GEN8_DE_MISC_IRQ) { | |
2022 | tmp = I915_READ(GEN8_DE_MISC_IIR); | |
2023 | if (tmp & GEN8_DE_MISC_GSE) | |
2024 | intel_opregion_asle_intr(dev); | |
2025 | else if (tmp) | |
2026 | DRM_ERROR("Unexpected DE Misc interrupt\n"); | |
2027 | else | |
2028 | DRM_ERROR("The master control interrupt lied (DE MISC)!\n"); | |
2029 | ||
2030 | if (tmp) { | |
2031 | I915_WRITE(GEN8_DE_MISC_IIR, tmp); | |
2032 | ret = IRQ_HANDLED; | |
2033 | } | |
2034 | } | |
2035 | ||
6d766f02 DV |
2036 | if (master_ctl & GEN8_DE_PORT_IRQ) { |
2037 | tmp = I915_READ(GEN8_DE_PORT_IIR); | |
2038 | if (tmp & GEN8_AUX_CHANNEL_A) | |
2039 | dp_aux_irq_handler(dev); | |
2040 | else if (tmp) | |
2041 | DRM_ERROR("Unexpected DE Port interrupt\n"); | |
2042 | else | |
2043 | DRM_ERROR("The master control interrupt lied (DE PORT)!\n"); | |
2044 | ||
2045 | if (tmp) { | |
2046 | I915_WRITE(GEN8_DE_PORT_IIR, tmp); | |
2047 | ret = IRQ_HANDLED; | |
2048 | } | |
2049 | } | |
2050 | ||
c42664cc DV |
2051 | for_each_pipe(pipe) { |
2052 | uint32_t pipe_iir; | |
abd58f01 | 2053 | |
c42664cc DV |
2054 | if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) |
2055 | continue; | |
abd58f01 | 2056 | |
c42664cc DV |
2057 | pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); |
2058 | if (pipe_iir & GEN8_PIPE_VBLANK) | |
8d7849db | 2059 | intel_pipe_handle_vblank(dev, pipe); |
abd58f01 | 2060 | |
d0e1f1cb | 2061 | if (pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE) { |
c42664cc DV |
2062 | intel_prepare_page_flip(dev, pipe); |
2063 | intel_finish_page_flip_plane(dev, pipe); | |
abd58f01 | 2064 | } |
c42664cc | 2065 | |
0fbe7870 DV |
2066 | if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE) |
2067 | hsw_pipe_crc_irq_handler(dev, pipe); | |
2068 | ||
38d83c96 DV |
2069 | if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) { |
2070 | if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, | |
2071 | false)) | |
fc2c807b VS |
2072 | DRM_ERROR("Pipe %c FIFO underrun\n", |
2073 | pipe_name(pipe)); | |
38d83c96 DV |
2074 | } |
2075 | ||
30100f2b DV |
2076 | if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) { |
2077 | DRM_ERROR("Fault errors on pipe %c\n: 0x%08x", | |
2078 | pipe_name(pipe), | |
2079 | pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS); | |
2080 | } | |
c42664cc DV |
2081 | |
2082 | if (pipe_iir) { | |
2083 | ret = IRQ_HANDLED; | |
2084 | I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir); | |
2085 | } else | |
abd58f01 BW |
2086 | DRM_ERROR("The master control interrupt lied (DE PIPE)!\n"); |
2087 | } | |
2088 | ||
92d03a80 DV |
2089 | if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) { |
2090 | /* | |
2091 | * FIXME(BDW): Assume for now that the new interrupt handling | |
2092 | * scheme also closed the SDE interrupt handling race we've seen | |
2093 | * on older pch-split platforms. But this needs testing. | |
2094 | */ | |
2095 | u32 pch_iir = I915_READ(SDEIIR); | |
2096 | ||
2097 | cpt_irq_handler(dev, pch_iir); | |
2098 | ||
2099 | if (pch_iir) { | |
2100 | I915_WRITE(SDEIIR, pch_iir); | |
2101 | ret = IRQ_HANDLED; | |
2102 | } | |
2103 | } | |
2104 | ||
abd58f01 BW |
2105 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
2106 | POSTING_READ(GEN8_MASTER_IRQ); | |
2107 | ||
2108 | return ret; | |
2109 | } | |
2110 | ||
17e1df07 DV |
2111 | static void i915_error_wake_up(struct drm_i915_private *dev_priv, |
2112 | bool reset_completed) | |
2113 | { | |
2114 | struct intel_ring_buffer *ring; | |
2115 | int i; | |
2116 | ||
2117 | /* | |
2118 | * Notify all waiters for GPU completion events that reset state has | |
2119 | * been changed, and that they need to restart their wait after | |
2120 | * checking for potential errors (and bail out to drop locks if there is | |
2121 | * a gpu reset pending so that i915_error_work_func can acquire them). | |
2122 | */ | |
2123 | ||
2124 | /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */ | |
2125 | for_each_ring(ring, dev_priv, i) | |
2126 | wake_up_all(&ring->irq_queue); | |
2127 | ||
2128 | /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */ | |
2129 | wake_up_all(&dev_priv->pending_flip_queue); | |
2130 | ||
2131 | /* | |
2132 | * Signal tasks blocked in i915_gem_wait_for_error that the pending | |
2133 | * reset state is cleared. | |
2134 | */ | |
2135 | if (reset_completed) | |
2136 | wake_up_all(&dev_priv->gpu_error.reset_queue); | |
2137 | } | |
2138 | ||
8a905236 JB |
2139 | /** |
2140 | * i915_error_work_func - do process context error handling work | |
2141 | * @work: work struct | |
2142 | * | |
2143 | * Fire an error uevent so userspace can see that a hang or error | |
2144 | * was detected. | |
2145 | */ | |
2146 | static void i915_error_work_func(struct work_struct *work) | |
2147 | { | |
1f83fee0 DV |
2148 | struct i915_gpu_error *error = container_of(work, struct i915_gpu_error, |
2149 | work); | |
2d1013dd JN |
2150 | struct drm_i915_private *dev_priv = |
2151 | container_of(error, struct drm_i915_private, gpu_error); | |
8a905236 | 2152 | struct drm_device *dev = dev_priv->dev; |
cce723ed BW |
2153 | char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; |
2154 | char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; | |
2155 | char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; | |
17e1df07 | 2156 | int ret; |
8a905236 | 2157 | |
5bdebb18 | 2158 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event); |
f316a42c | 2159 | |
7db0ba24 DV |
2160 | /* |
2161 | * Note that there's only one work item which does gpu resets, so we | |
2162 | * need not worry about concurrent gpu resets potentially incrementing | |
2163 | * error->reset_counter twice. We only need to take care of another | |
2164 | * racing irq/hangcheck declaring the gpu dead for a second time. A | |
2165 | * quick check for that is good enough: schedule_work ensures the | |
2166 | * correct ordering between hang detection and this work item, and since | |
2167 | * the reset in-progress bit is only ever set by code outside of this | |
2168 | * work we don't need to worry about any other races. | |
2169 | */ | |
2170 | if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) { | |
f803aa55 | 2171 | DRM_DEBUG_DRIVER("resetting chip\n"); |
5bdebb18 | 2172 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, |
7db0ba24 | 2173 | reset_event); |
1f83fee0 | 2174 | |
f454c694 ID |
2175 | /* |
2176 | * In most cases it's guaranteed that we get here with an RPM | |
2177 | * reference held, for example because there is a pending GPU | |
2178 | * request that won't finish until the reset is done. This | |
2179 | * isn't the case at least when we get here by doing a | |
2180 | * simulated reset via debugs, so get an RPM reference. | |
2181 | */ | |
2182 | intel_runtime_pm_get(dev_priv); | |
17e1df07 DV |
2183 | /* |
2184 | * All state reset _must_ be completed before we update the | |
2185 | * reset counter, for otherwise waiters might miss the reset | |
2186 | * pending state and not properly drop locks, resulting in | |
2187 | * deadlocks with the reset work. | |
2188 | */ | |
f69061be DV |
2189 | ret = i915_reset(dev); |
2190 | ||
17e1df07 DV |
2191 | intel_display_handle_reset(dev); |
2192 | ||
f454c694 ID |
2193 | intel_runtime_pm_put(dev_priv); |
2194 | ||
f69061be DV |
2195 | if (ret == 0) { |
2196 | /* | |
2197 | * After all the gem state is reset, increment the reset | |
2198 | * counter and wake up everyone waiting for the reset to | |
2199 | * complete. | |
2200 | * | |
2201 | * Since unlock operations are a one-sided barrier only, | |
2202 | * we need to insert a barrier here to order any seqno | |
2203 | * updates before | |
2204 | * the counter increment. | |
2205 | */ | |
2206 | smp_mb__before_atomic_inc(); | |
2207 | atomic_inc(&dev_priv->gpu_error.reset_counter); | |
2208 | ||
5bdebb18 | 2209 | kobject_uevent_env(&dev->primary->kdev->kobj, |
f69061be | 2210 | KOBJ_CHANGE, reset_done_event); |
1f83fee0 | 2211 | } else { |
2ac0f450 | 2212 | atomic_set_mask(I915_WEDGED, &error->reset_counter); |
f316a42c | 2213 | } |
1f83fee0 | 2214 | |
17e1df07 DV |
2215 | /* |
2216 | * Note: The wake_up also serves as a memory barrier so that | |
2217 | * waiters see the update value of the reset counter atomic_t. | |
2218 | */ | |
2219 | i915_error_wake_up(dev_priv, true); | |
f316a42c | 2220 | } |
8a905236 JB |
2221 | } |
2222 | ||
35aed2e6 | 2223 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
2224 | { |
2225 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bd9854f9 | 2226 | uint32_t instdone[I915_NUM_INSTDONE_REG]; |
8a905236 | 2227 | u32 eir = I915_READ(EIR); |
050ee91f | 2228 | int pipe, i; |
8a905236 | 2229 | |
35aed2e6 CW |
2230 | if (!eir) |
2231 | return; | |
8a905236 | 2232 | |
a70491cc | 2233 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
8a905236 | 2234 | |
bd9854f9 BW |
2235 | i915_get_extra_instdone(dev, instdone); |
2236 | ||
8a905236 JB |
2237 | if (IS_G4X(dev)) { |
2238 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
2239 | u32 ipeir = I915_READ(IPEIR_I965); | |
2240 | ||
a70491cc JP |
2241 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2242 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
050ee91f BW |
2243 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2244 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a70491cc | 2245 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2246 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2247 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2248 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2249 | } |
2250 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
2251 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2252 | pr_err("page table error\n"); |
2253 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2254 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2255 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2256 | } |
2257 | } | |
2258 | ||
a6c45cf0 | 2259 | if (!IS_GEN2(dev)) { |
8a905236 JB |
2260 | if (eir & I915_ERROR_PAGE_TABLE) { |
2261 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2262 | pr_err("page table error\n"); |
2263 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2264 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2265 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2266 | } |
2267 | } | |
2268 | ||
2269 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
a70491cc | 2270 | pr_err("memory refresh error:\n"); |
9db4a9c7 | 2271 | for_each_pipe(pipe) |
a70491cc | 2272 | pr_err("pipe %c stat: 0x%08x\n", |
9db4a9c7 | 2273 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
8a905236 JB |
2274 | /* pipestat has already been acked */ |
2275 | } | |
2276 | if (eir & I915_ERROR_INSTRUCTION) { | |
a70491cc JP |
2277 | pr_err("instruction error\n"); |
2278 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); | |
050ee91f BW |
2279 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2280 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a6c45cf0 | 2281 | if (INTEL_INFO(dev)->gen < 4) { |
8a905236 JB |
2282 | u32 ipeir = I915_READ(IPEIR); |
2283 | ||
a70491cc JP |
2284 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
2285 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); | |
a70491cc | 2286 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); |
8a905236 | 2287 | I915_WRITE(IPEIR, ipeir); |
3143a2bf | 2288 | POSTING_READ(IPEIR); |
8a905236 JB |
2289 | } else { |
2290 | u32 ipeir = I915_READ(IPEIR_I965); | |
2291 | ||
a70491cc JP |
2292 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2293 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
a70491cc | 2294 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2295 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2296 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2297 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2298 | } |
2299 | } | |
2300 | ||
2301 | I915_WRITE(EIR, eir); | |
3143a2bf | 2302 | POSTING_READ(EIR); |
8a905236 JB |
2303 | eir = I915_READ(EIR); |
2304 | if (eir) { | |
2305 | /* | |
2306 | * some errors might have become stuck, | |
2307 | * mask them. | |
2308 | */ | |
2309 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
2310 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
2311 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2312 | } | |
35aed2e6 CW |
2313 | } |
2314 | ||
2315 | /** | |
2316 | * i915_handle_error - handle an error interrupt | |
2317 | * @dev: drm device | |
2318 | * | |
2319 | * Do some basic checking of regsiter state at error interrupt time and | |
2320 | * dump it to the syslog. Also call i915_capture_error_state() to make | |
2321 | * sure we get a record and make it available in debugfs. Fire a uevent | |
2322 | * so userspace knows something bad happened (should trigger collection | |
2323 | * of a ring dump etc.). | |
2324 | */ | |
58174462 MK |
2325 | void i915_handle_error(struct drm_device *dev, bool wedged, |
2326 | const char *fmt, ...) | |
35aed2e6 CW |
2327 | { |
2328 | struct drm_i915_private *dev_priv = dev->dev_private; | |
58174462 MK |
2329 | va_list args; |
2330 | char error_msg[80]; | |
35aed2e6 | 2331 | |
58174462 MK |
2332 | va_start(args, fmt); |
2333 | vscnprintf(error_msg, sizeof(error_msg), fmt, args); | |
2334 | va_end(args); | |
2335 | ||
2336 | i915_capture_error_state(dev, wedged, error_msg); | |
35aed2e6 | 2337 | i915_report_and_clear_eir(dev); |
8a905236 | 2338 | |
ba1234d1 | 2339 | if (wedged) { |
f69061be DV |
2340 | atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG, |
2341 | &dev_priv->gpu_error.reset_counter); | |
ba1234d1 | 2342 | |
11ed50ec | 2343 | /* |
17e1df07 DV |
2344 | * Wakeup waiting processes so that the reset work function |
2345 | * i915_error_work_func doesn't deadlock trying to grab various | |
2346 | * locks. By bumping the reset counter first, the woken | |
2347 | * processes will see a reset in progress and back off, | |
2348 | * releasing their locks and then wait for the reset completion. | |
2349 | * We must do this for _all_ gpu waiters that might hold locks | |
2350 | * that the reset work needs to acquire. | |
2351 | * | |
2352 | * Note: The wake_up serves as the required memory barrier to | |
2353 | * ensure that the waiters see the updated value of the reset | |
2354 | * counter atomic_t. | |
11ed50ec | 2355 | */ |
17e1df07 | 2356 | i915_error_wake_up(dev_priv, false); |
11ed50ec BG |
2357 | } |
2358 | ||
122f46ba DV |
2359 | /* |
2360 | * Our reset work can grab modeset locks (since it needs to reset the | |
2361 | * state of outstanding pagelips). Hence it must not be run on our own | |
2362 | * dev-priv->wq work queue for otherwise the flush_work in the pageflip | |
2363 | * code will deadlock. | |
2364 | */ | |
2365 | schedule_work(&dev_priv->gpu_error.work); | |
8a905236 JB |
2366 | } |
2367 | ||
21ad8330 | 2368 | static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe) |
4e5359cd | 2369 | { |
2d1013dd | 2370 | struct drm_i915_private *dev_priv = dev->dev_private; |
4e5359cd SF |
2371 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
2372 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 2373 | struct drm_i915_gem_object *obj; |
4e5359cd SF |
2374 | struct intel_unpin_work *work; |
2375 | unsigned long flags; | |
2376 | bool stall_detected; | |
2377 | ||
2378 | /* Ignore early vblank irqs */ | |
2379 | if (intel_crtc == NULL) | |
2380 | return; | |
2381 | ||
2382 | spin_lock_irqsave(&dev->event_lock, flags); | |
2383 | work = intel_crtc->unpin_work; | |
2384 | ||
e7d841ca CW |
2385 | if (work == NULL || |
2386 | atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE || | |
2387 | !work->enable_stall_check) { | |
4e5359cd SF |
2388 | /* Either the pending flip IRQ arrived, or we're too early. Don't check */ |
2389 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2390 | return; | |
2391 | } | |
2392 | ||
2393 | /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ | |
05394f39 | 2394 | obj = work->pending_flip_obj; |
a6c45cf0 | 2395 | if (INTEL_INFO(dev)->gen >= 4) { |
9db4a9c7 | 2396 | int dspsurf = DSPSURF(intel_crtc->plane); |
446f2545 | 2397 | stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) == |
f343c5f6 | 2398 | i915_gem_obj_ggtt_offset(obj); |
4e5359cd | 2399 | } else { |
9db4a9c7 | 2400 | int dspaddr = DSPADDR(intel_crtc->plane); |
f343c5f6 | 2401 | stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) + |
f4510a27 MR |
2402 | crtc->y * crtc->primary->fb->pitches[0] + |
2403 | crtc->x * crtc->primary->fb->bits_per_pixel/8); | |
4e5359cd SF |
2404 | } |
2405 | ||
2406 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2407 | ||
2408 | if (stall_detected) { | |
2409 | DRM_DEBUG_DRIVER("Pageflip stall detected\n"); | |
2410 | intel_prepare_page_flip(dev, intel_crtc->plane); | |
2411 | } | |
2412 | } | |
2413 | ||
42f52ef8 KP |
2414 | /* Called from drm generic code, passed 'crtc' which |
2415 | * we use as a pipe index | |
2416 | */ | |
f71d4af4 | 2417 | static int i915_enable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 | 2418 | { |
2d1013dd | 2419 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2420 | unsigned long irqflags; |
71e0ffa5 | 2421 | |
5eddb70b | 2422 | if (!i915_pipe_enabled(dev, pipe)) |
71e0ffa5 | 2423 | return -EINVAL; |
0a3e67a4 | 2424 | |
1ec14ad3 | 2425 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2426 | if (INTEL_INFO(dev)->gen >= 4) |
7c463586 | 2427 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2428 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
e9d21d7f | 2429 | else |
7c463586 | 2430 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2431 | PIPE_VBLANK_INTERRUPT_STATUS); |
8692d00e CW |
2432 | |
2433 | /* maintain vblank delivery even in deep C-states */ | |
3d13ef2e | 2434 | if (INTEL_INFO(dev)->gen == 3) |
6b26c86d | 2435 | I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS)); |
1ec14ad3 | 2436 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
8692d00e | 2437 | |
0a3e67a4 JB |
2438 | return 0; |
2439 | } | |
2440 | ||
f71d4af4 | 2441 | static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
f796cf8f | 2442 | { |
2d1013dd | 2443 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2444 | unsigned long irqflags; |
b518421f | 2445 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2446 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2447 | |
2448 | if (!i915_pipe_enabled(dev, pipe)) | |
2449 | return -EINVAL; | |
2450 | ||
2451 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 2452 | ironlake_enable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2453 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2454 | ||
2455 | return 0; | |
2456 | } | |
2457 | ||
7e231dbe JB |
2458 | static int valleyview_enable_vblank(struct drm_device *dev, int pipe) |
2459 | { | |
2d1013dd | 2460 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2461 | unsigned long irqflags; |
7e231dbe JB |
2462 | |
2463 | if (!i915_pipe_enabled(dev, pipe)) | |
2464 | return -EINVAL; | |
2465 | ||
2466 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 | 2467 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2468 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2469 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2470 | ||
2471 | return 0; | |
2472 | } | |
2473 | ||
abd58f01 BW |
2474 | static int gen8_enable_vblank(struct drm_device *dev, int pipe) |
2475 | { | |
2476 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2477 | unsigned long irqflags; | |
abd58f01 BW |
2478 | |
2479 | if (!i915_pipe_enabled(dev, pipe)) | |
2480 | return -EINVAL; | |
2481 | ||
2482 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
7167d7c6 DV |
2483 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK; |
2484 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2485 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2486 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2487 | return 0; | |
2488 | } | |
2489 | ||
42f52ef8 KP |
2490 | /* Called from drm generic code, passed 'crtc' which |
2491 | * we use as a pipe index | |
2492 | */ | |
f71d4af4 | 2493 | static void i915_disable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 | 2494 | { |
2d1013dd | 2495 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2496 | unsigned long irqflags; |
0a3e67a4 | 2497 | |
1ec14ad3 | 2498 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
3d13ef2e | 2499 | if (INTEL_INFO(dev)->gen == 3) |
6b26c86d | 2500 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS)); |
8692d00e | 2501 | |
f796cf8f | 2502 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 ID |
2503 | PIPE_VBLANK_INTERRUPT_STATUS | |
2504 | PIPE_START_VBLANK_INTERRUPT_STATUS); | |
f796cf8f JB |
2505 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2506 | } | |
2507 | ||
f71d4af4 | 2508 | static void ironlake_disable_vblank(struct drm_device *dev, int pipe) |
f796cf8f | 2509 | { |
2d1013dd | 2510 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2511 | unsigned long irqflags; |
b518421f | 2512 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2513 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2514 | |
2515 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 2516 | ironlake_disable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2517 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2518 | } | |
2519 | ||
7e231dbe JB |
2520 | static void valleyview_disable_vblank(struct drm_device *dev, int pipe) |
2521 | { | |
2d1013dd | 2522 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2523 | unsigned long irqflags; |
7e231dbe JB |
2524 | |
2525 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 | 2526 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 | 2527 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2528 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2529 | } | |
2530 | ||
abd58f01 BW |
2531 | static void gen8_disable_vblank(struct drm_device *dev, int pipe) |
2532 | { | |
2533 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2534 | unsigned long irqflags; | |
abd58f01 BW |
2535 | |
2536 | if (!i915_pipe_enabled(dev, pipe)) | |
2537 | return; | |
2538 | ||
2539 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
7167d7c6 DV |
2540 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK; |
2541 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2542 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2543 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2544 | } | |
2545 | ||
893eead0 CW |
2546 | static u32 |
2547 | ring_last_seqno(struct intel_ring_buffer *ring) | |
852835f3 | 2548 | { |
893eead0 CW |
2549 | return list_entry(ring->request_list.prev, |
2550 | struct drm_i915_gem_request, list)->seqno; | |
2551 | } | |
2552 | ||
9107e9d2 CW |
2553 | static bool |
2554 | ring_idle(struct intel_ring_buffer *ring, u32 seqno) | |
2555 | { | |
2556 | return (list_empty(&ring->request_list) || | |
2557 | i915_seqno_passed(seqno, ring_last_seqno(ring))); | |
f65d9421 BG |
2558 | } |
2559 | ||
a028c4b0 DV |
2560 | static bool |
2561 | ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr) | |
2562 | { | |
2563 | if (INTEL_INFO(dev)->gen >= 8) { | |
2564 | /* | |
2565 | * FIXME: gen8 semaphore support - currently we don't emit | |
2566 | * semaphores on bdw anyway, but this needs to be addressed when | |
2567 | * we merge that code. | |
2568 | */ | |
2569 | return false; | |
2570 | } else { | |
2571 | ipehr &= ~MI_SEMAPHORE_SYNC_MASK; | |
2572 | return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | | |
2573 | MI_SEMAPHORE_REGISTER); | |
2574 | } | |
2575 | } | |
2576 | ||
921d42ea DV |
2577 | static struct intel_ring_buffer * |
2578 | semaphore_wait_to_signaller_ring(struct intel_ring_buffer *ring, u32 ipehr) | |
2579 | { | |
2580 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
2581 | struct intel_ring_buffer *signaller; | |
2582 | int i; | |
2583 | ||
2584 | if (INTEL_INFO(dev_priv->dev)->gen >= 8) { | |
2585 | /* | |
2586 | * FIXME: gen8 semaphore support - currently we don't emit | |
2587 | * semaphores on bdw anyway, but this needs to be addressed when | |
2588 | * we merge that code. | |
2589 | */ | |
2590 | return NULL; | |
2591 | } else { | |
2592 | u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK; | |
2593 | ||
2594 | for_each_ring(signaller, dev_priv, i) { | |
2595 | if(ring == signaller) | |
2596 | continue; | |
2597 | ||
ebc348b2 | 2598 | if (sync_bits == signaller->semaphore.mbox.wait[ring->id]) |
921d42ea DV |
2599 | return signaller; |
2600 | } | |
2601 | } | |
2602 | ||
2603 | DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x\n", | |
2604 | ring->id, ipehr); | |
2605 | ||
2606 | return NULL; | |
2607 | } | |
2608 | ||
6274f212 CW |
2609 | static struct intel_ring_buffer * |
2610 | semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno) | |
a24a11e6 CW |
2611 | { |
2612 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
88fe429d DV |
2613 | u32 cmd, ipehr, head; |
2614 | int i; | |
a24a11e6 CW |
2615 | |
2616 | ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); | |
a028c4b0 | 2617 | if (!ipehr_is_semaphore_wait(ring->dev, ipehr)) |
6274f212 | 2618 | return NULL; |
a24a11e6 | 2619 | |
88fe429d DV |
2620 | /* |
2621 | * HEAD is likely pointing to the dword after the actual command, | |
2622 | * so scan backwards until we find the MBOX. But limit it to just 3 | |
2623 | * dwords. Note that we don't care about ACTHD here since that might | |
2624 | * point at at batch, and semaphores are always emitted into the | |
2625 | * ringbuffer itself. | |
a24a11e6 | 2626 | */ |
88fe429d DV |
2627 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
2628 | ||
2629 | for (i = 4; i; --i) { | |
2630 | /* | |
2631 | * Be paranoid and presume the hw has gone off into the wild - | |
2632 | * our ring is smaller than what the hardware (and hence | |
2633 | * HEAD_ADDR) allows. Also handles wrap-around. | |
2634 | */ | |
2635 | head &= ring->size - 1; | |
2636 | ||
2637 | /* This here seems to blow up */ | |
2638 | cmd = ioread32(ring->virtual_start + head); | |
a24a11e6 CW |
2639 | if (cmd == ipehr) |
2640 | break; | |
2641 | ||
88fe429d DV |
2642 | head -= 4; |
2643 | } | |
a24a11e6 | 2644 | |
88fe429d DV |
2645 | if (!i) |
2646 | return NULL; | |
a24a11e6 | 2647 | |
88fe429d | 2648 | *seqno = ioread32(ring->virtual_start + head + 4) + 1; |
921d42ea | 2649 | return semaphore_wait_to_signaller_ring(ring, ipehr); |
a24a11e6 CW |
2650 | } |
2651 | ||
6274f212 CW |
2652 | static int semaphore_passed(struct intel_ring_buffer *ring) |
2653 | { | |
2654 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
2655 | struct intel_ring_buffer *signaller; | |
2656 | u32 seqno, ctl; | |
2657 | ||
2658 | ring->hangcheck.deadlock = true; | |
2659 | ||
2660 | signaller = semaphore_waits_for(ring, &seqno); | |
2661 | if (signaller == NULL || signaller->hangcheck.deadlock) | |
2662 | return -1; | |
2663 | ||
2664 | /* cursory check for an unkickable deadlock */ | |
2665 | ctl = I915_READ_CTL(signaller); | |
2666 | if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0) | |
2667 | return -1; | |
2668 | ||
2669 | return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno); | |
2670 | } | |
2671 | ||
2672 | static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) | |
2673 | { | |
2674 | struct intel_ring_buffer *ring; | |
2675 | int i; | |
2676 | ||
2677 | for_each_ring(ring, dev_priv, i) | |
2678 | ring->hangcheck.deadlock = false; | |
2679 | } | |
2680 | ||
ad8beaea | 2681 | static enum intel_ring_hangcheck_action |
50877445 | 2682 | ring_stuck(struct intel_ring_buffer *ring, u64 acthd) |
1ec14ad3 CW |
2683 | { |
2684 | struct drm_device *dev = ring->dev; | |
2685 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9107e9d2 CW |
2686 | u32 tmp; |
2687 | ||
6274f212 | 2688 | if (ring->hangcheck.acthd != acthd) |
f2f4d82f | 2689 | return HANGCHECK_ACTIVE; |
6274f212 | 2690 | |
9107e9d2 | 2691 | if (IS_GEN2(dev)) |
f2f4d82f | 2692 | return HANGCHECK_HUNG; |
9107e9d2 CW |
2693 | |
2694 | /* Is the chip hanging on a WAIT_FOR_EVENT? | |
2695 | * If so we can simply poke the RB_WAIT bit | |
2696 | * and break the hang. This should work on | |
2697 | * all but the second generation chipsets. | |
2698 | */ | |
2699 | tmp = I915_READ_CTL(ring); | |
1ec14ad3 | 2700 | if (tmp & RING_WAIT) { |
58174462 MK |
2701 | i915_handle_error(dev, false, |
2702 | "Kicking stuck wait on %s", | |
2703 | ring->name); | |
1ec14ad3 | 2704 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2705 | return HANGCHECK_KICK; |
6274f212 CW |
2706 | } |
2707 | ||
2708 | if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { | |
2709 | switch (semaphore_passed(ring)) { | |
2710 | default: | |
f2f4d82f | 2711 | return HANGCHECK_HUNG; |
6274f212 | 2712 | case 1: |
58174462 MK |
2713 | i915_handle_error(dev, false, |
2714 | "Kicking stuck semaphore on %s", | |
2715 | ring->name); | |
6274f212 | 2716 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2717 | return HANGCHECK_KICK; |
6274f212 | 2718 | case 0: |
f2f4d82f | 2719 | return HANGCHECK_WAIT; |
6274f212 | 2720 | } |
9107e9d2 | 2721 | } |
ed5cbb03 | 2722 | |
f2f4d82f | 2723 | return HANGCHECK_HUNG; |
ed5cbb03 MK |
2724 | } |
2725 | ||
f65d9421 BG |
2726 | /** |
2727 | * This is called when the chip hasn't reported back with completed | |
05407ff8 MK |
2728 | * batchbuffers in a long time. We keep track per ring seqno progress and |
2729 | * if there are no progress, hangcheck score for that ring is increased. | |
2730 | * Further, acthd is inspected to see if the ring is stuck. On stuck case | |
2731 | * we kick the ring. If we see no progress on three subsequent calls | |
2732 | * we assume chip is wedged and try to fix it by resetting the chip. | |
f65d9421 | 2733 | */ |
a658b5d2 | 2734 | static void i915_hangcheck_elapsed(unsigned long data) |
f65d9421 BG |
2735 | { |
2736 | struct drm_device *dev = (struct drm_device *)data; | |
2d1013dd | 2737 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 2738 | struct intel_ring_buffer *ring; |
b4519513 | 2739 | int i; |
05407ff8 | 2740 | int busy_count = 0, rings_hung = 0; |
9107e9d2 CW |
2741 | bool stuck[I915_NUM_RINGS] = { 0 }; |
2742 | #define BUSY 1 | |
2743 | #define KICK 5 | |
2744 | #define HUNG 20 | |
893eead0 | 2745 | |
d330a953 | 2746 | if (!i915.enable_hangcheck) |
3e0dc6b0 BW |
2747 | return; |
2748 | ||
b4519513 | 2749 | for_each_ring(ring, dev_priv, i) { |
50877445 CW |
2750 | u64 acthd; |
2751 | u32 seqno; | |
9107e9d2 | 2752 | bool busy = true; |
05407ff8 | 2753 | |
6274f212 CW |
2754 | semaphore_clear_deadlocks(dev_priv); |
2755 | ||
05407ff8 MK |
2756 | seqno = ring->get_seqno(ring, false); |
2757 | acthd = intel_ring_get_active_head(ring); | |
b4519513 | 2758 | |
9107e9d2 CW |
2759 | if (ring->hangcheck.seqno == seqno) { |
2760 | if (ring_idle(ring, seqno)) { | |
da661464 MK |
2761 | ring->hangcheck.action = HANGCHECK_IDLE; |
2762 | ||
9107e9d2 CW |
2763 | if (waitqueue_active(&ring->irq_queue)) { |
2764 | /* Issue a wake-up to catch stuck h/w. */ | |
094f9a54 | 2765 | if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) { |
f4adcd24 DV |
2766 | if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring))) |
2767 | DRM_ERROR("Hangcheck timer elapsed... %s idle\n", | |
2768 | ring->name); | |
2769 | else | |
2770 | DRM_INFO("Fake missed irq on %s\n", | |
2771 | ring->name); | |
094f9a54 CW |
2772 | wake_up_all(&ring->irq_queue); |
2773 | } | |
2774 | /* Safeguard against driver failure */ | |
2775 | ring->hangcheck.score += BUSY; | |
9107e9d2 CW |
2776 | } else |
2777 | busy = false; | |
05407ff8 | 2778 | } else { |
6274f212 CW |
2779 | /* We always increment the hangcheck score |
2780 | * if the ring is busy and still processing | |
2781 | * the same request, so that no single request | |
2782 | * can run indefinitely (such as a chain of | |
2783 | * batches). The only time we do not increment | |
2784 | * the hangcheck score on this ring, if this | |
2785 | * ring is in a legitimate wait for another | |
2786 | * ring. In that case the waiting ring is a | |
2787 | * victim and we want to be sure we catch the | |
2788 | * right culprit. Then every time we do kick | |
2789 | * the ring, add a small increment to the | |
2790 | * score so that we can catch a batch that is | |
2791 | * being repeatedly kicked and so responsible | |
2792 | * for stalling the machine. | |
2793 | */ | |
ad8beaea MK |
2794 | ring->hangcheck.action = ring_stuck(ring, |
2795 | acthd); | |
2796 | ||
2797 | switch (ring->hangcheck.action) { | |
da661464 | 2798 | case HANGCHECK_IDLE: |
f2f4d82f | 2799 | case HANGCHECK_WAIT: |
6274f212 | 2800 | break; |
f2f4d82f | 2801 | case HANGCHECK_ACTIVE: |
ea04cb31 | 2802 | ring->hangcheck.score += BUSY; |
6274f212 | 2803 | break; |
f2f4d82f | 2804 | case HANGCHECK_KICK: |
ea04cb31 | 2805 | ring->hangcheck.score += KICK; |
6274f212 | 2806 | break; |
f2f4d82f | 2807 | case HANGCHECK_HUNG: |
ea04cb31 | 2808 | ring->hangcheck.score += HUNG; |
6274f212 CW |
2809 | stuck[i] = true; |
2810 | break; | |
2811 | } | |
05407ff8 | 2812 | } |
9107e9d2 | 2813 | } else { |
da661464 MK |
2814 | ring->hangcheck.action = HANGCHECK_ACTIVE; |
2815 | ||
9107e9d2 CW |
2816 | /* Gradually reduce the count so that we catch DoS |
2817 | * attempts across multiple batches. | |
2818 | */ | |
2819 | if (ring->hangcheck.score > 0) | |
2820 | ring->hangcheck.score--; | |
d1e61e7f CW |
2821 | } |
2822 | ||
05407ff8 MK |
2823 | ring->hangcheck.seqno = seqno; |
2824 | ring->hangcheck.acthd = acthd; | |
9107e9d2 | 2825 | busy_count += busy; |
893eead0 | 2826 | } |
b9201c14 | 2827 | |
92cab734 | 2828 | for_each_ring(ring, dev_priv, i) { |
b6b0fac0 | 2829 | if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) { |
b8d88d1d DV |
2830 | DRM_INFO("%s on %s\n", |
2831 | stuck[i] ? "stuck" : "no progress", | |
2832 | ring->name); | |
a43adf07 | 2833 | rings_hung++; |
92cab734 MK |
2834 | } |
2835 | } | |
2836 | ||
05407ff8 | 2837 | if (rings_hung) |
58174462 | 2838 | return i915_handle_error(dev, true, "Ring hung"); |
f65d9421 | 2839 | |
05407ff8 MK |
2840 | if (busy_count) |
2841 | /* Reset timer case chip hangs without another request | |
2842 | * being added */ | |
10cd45b6 MK |
2843 | i915_queue_hangcheck(dev); |
2844 | } | |
2845 | ||
2846 | void i915_queue_hangcheck(struct drm_device *dev) | |
2847 | { | |
2848 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d330a953 | 2849 | if (!i915.enable_hangcheck) |
10cd45b6 MK |
2850 | return; |
2851 | ||
2852 | mod_timer(&dev_priv->gpu_error.hangcheck_timer, | |
2853 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); | |
f65d9421 BG |
2854 | } |
2855 | ||
1c69eb42 | 2856 | static void ibx_irq_reset(struct drm_device *dev) |
91738a95 PZ |
2857 | { |
2858 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2859 | ||
2860 | if (HAS_PCH_NOP(dev)) | |
2861 | return; | |
2862 | ||
f86f3fb0 | 2863 | GEN5_IRQ_RESET(SDE); |
105b122e PZ |
2864 | |
2865 | if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) | |
2866 | I915_WRITE(SERR_INT, 0xffffffff); | |
622364b6 | 2867 | } |
105b122e | 2868 | |
622364b6 PZ |
2869 | /* |
2870 | * SDEIER is also touched by the interrupt handler to work around missed PCH | |
2871 | * interrupts. Hence we can't update it after the interrupt handler is enabled - | |
2872 | * instead we unconditionally enable all PCH interrupt sources here, but then | |
2873 | * only unmask them as needed with SDEIMR. | |
2874 | * | |
2875 | * This function needs to be called before interrupts are enabled. | |
2876 | */ | |
2877 | static void ibx_irq_pre_postinstall(struct drm_device *dev) | |
2878 | { | |
2879 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2880 | ||
2881 | if (HAS_PCH_NOP(dev)) | |
2882 | return; | |
2883 | ||
2884 | WARN_ON(I915_READ(SDEIER) != 0); | |
91738a95 PZ |
2885 | I915_WRITE(SDEIER, 0xffffffff); |
2886 | POSTING_READ(SDEIER); | |
2887 | } | |
2888 | ||
7c4d664e | 2889 | static void gen5_gt_irq_reset(struct drm_device *dev) |
d18ea1b5 DV |
2890 | { |
2891 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2892 | ||
f86f3fb0 | 2893 | GEN5_IRQ_RESET(GT); |
a9d356a6 | 2894 | if (INTEL_INFO(dev)->gen >= 6) |
f86f3fb0 | 2895 | GEN5_IRQ_RESET(GEN6_PM); |
d18ea1b5 DV |
2896 | } |
2897 | ||
1da177e4 LT |
2898 | /* drm_dma.h hooks |
2899 | */ | |
be30b29f | 2900 | static void ironlake_irq_reset(struct drm_device *dev) |
036a4a7d | 2901 | { |
2d1013dd | 2902 | struct drm_i915_private *dev_priv = dev->dev_private; |
036a4a7d | 2903 | |
0c841212 | 2904 | I915_WRITE(HWSTAM, 0xffffffff); |
bdfcdb63 | 2905 | |
f86f3fb0 | 2906 | GEN5_IRQ_RESET(DE); |
c6d954c1 PZ |
2907 | if (IS_GEN7(dev)) |
2908 | I915_WRITE(GEN7_ERR_INT, 0xffffffff); | |
036a4a7d | 2909 | |
7c4d664e | 2910 | gen5_gt_irq_reset(dev); |
c650156a | 2911 | |
1c69eb42 | 2912 | ibx_irq_reset(dev); |
7d99163d | 2913 | } |
c650156a | 2914 | |
be30b29f PZ |
2915 | static void ironlake_irq_preinstall(struct drm_device *dev) |
2916 | { | |
be30b29f | 2917 | ironlake_irq_reset(dev); |
7d99163d BW |
2918 | } |
2919 | ||
7e231dbe JB |
2920 | static void valleyview_irq_preinstall(struct drm_device *dev) |
2921 | { | |
2d1013dd | 2922 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
2923 | int pipe; |
2924 | ||
7e231dbe JB |
2925 | /* VLV magic */ |
2926 | I915_WRITE(VLV_IMR, 0); | |
2927 | I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); | |
2928 | I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); | |
2929 | I915_WRITE(RING_IMR(BLT_RING_BASE), 0); | |
2930 | ||
7e231dbe JB |
2931 | /* and GT */ |
2932 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
2933 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
d18ea1b5 | 2934 | |
7c4d664e | 2935 | gen5_gt_irq_reset(dev); |
7e231dbe JB |
2936 | |
2937 | I915_WRITE(DPINVGTT, 0xff); | |
2938 | ||
2939 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
2940 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
2941 | for_each_pipe(pipe) | |
2942 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
2943 | I915_WRITE(VLV_IIR, 0xffffffff); | |
2944 | I915_WRITE(VLV_IMR, 0xffffffff); | |
2945 | I915_WRITE(VLV_IER, 0x0); | |
2946 | POSTING_READ(VLV_IER); | |
2947 | } | |
2948 | ||
823f6b38 | 2949 | static void gen8_irq_reset(struct drm_device *dev) |
abd58f01 BW |
2950 | { |
2951 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2952 | int pipe; | |
2953 | ||
abd58f01 BW |
2954 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
2955 | POSTING_READ(GEN8_MASTER_IRQ); | |
2956 | ||
f86f3fb0 PZ |
2957 | GEN8_IRQ_RESET_NDX(GT, 0); |
2958 | GEN8_IRQ_RESET_NDX(GT, 1); | |
2959 | GEN8_IRQ_RESET_NDX(GT, 2); | |
2960 | GEN8_IRQ_RESET_NDX(GT, 3); | |
abd58f01 | 2961 | |
823f6b38 | 2962 | for_each_pipe(pipe) |
f86f3fb0 | 2963 | GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); |
abd58f01 | 2964 | |
f86f3fb0 PZ |
2965 | GEN5_IRQ_RESET(GEN8_DE_PORT_); |
2966 | GEN5_IRQ_RESET(GEN8_DE_MISC_); | |
2967 | GEN5_IRQ_RESET(GEN8_PCU_); | |
abd58f01 | 2968 | |
1c69eb42 | 2969 | ibx_irq_reset(dev); |
abd58f01 | 2970 | } |
09f2344d | 2971 | |
823f6b38 PZ |
2972 | static void gen8_irq_preinstall(struct drm_device *dev) |
2973 | { | |
2974 | gen8_irq_reset(dev); | |
abd58f01 BW |
2975 | } |
2976 | ||
82a28bcf | 2977 | static void ibx_hpd_irq_setup(struct drm_device *dev) |
7fe0b973 | 2978 | { |
2d1013dd | 2979 | struct drm_i915_private *dev_priv = dev->dev_private; |
82a28bcf DV |
2980 | struct drm_mode_config *mode_config = &dev->mode_config; |
2981 | struct intel_encoder *intel_encoder; | |
fee884ed | 2982 | u32 hotplug_irqs, hotplug, enabled_irqs = 0; |
82a28bcf DV |
2983 | |
2984 | if (HAS_PCH_IBX(dev)) { | |
fee884ed | 2985 | hotplug_irqs = SDE_HOTPLUG_MASK; |
82a28bcf | 2986 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
cd569aed | 2987 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
fee884ed | 2988 | enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin]; |
82a28bcf | 2989 | } else { |
fee884ed | 2990 | hotplug_irqs = SDE_HOTPLUG_MASK_CPT; |
82a28bcf | 2991 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
cd569aed | 2992 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
fee884ed | 2993 | enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin]; |
82a28bcf | 2994 | } |
7fe0b973 | 2995 | |
fee884ed | 2996 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); |
82a28bcf DV |
2997 | |
2998 | /* | |
2999 | * Enable digital hotplug on the PCH, and configure the DP short pulse | |
3000 | * duration to 2ms (which is the minimum in the Display Port spec) | |
3001 | * | |
3002 | * This register is the same on all known PCH chips. | |
3003 | */ | |
7fe0b973 KP |
3004 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
3005 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); | |
3006 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; | |
3007 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; | |
3008 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; | |
3009 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); | |
3010 | } | |
3011 | ||
d46da437 PZ |
3012 | static void ibx_irq_postinstall(struct drm_device *dev) |
3013 | { | |
2d1013dd | 3014 | struct drm_i915_private *dev_priv = dev->dev_private; |
82a28bcf | 3015 | u32 mask; |
e5868a31 | 3016 | |
692a04cf DV |
3017 | if (HAS_PCH_NOP(dev)) |
3018 | return; | |
3019 | ||
105b122e | 3020 | if (HAS_PCH_IBX(dev)) |
5c673b60 | 3021 | mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; |
105b122e | 3022 | else |
5c673b60 | 3023 | mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; |
8664281b | 3024 | |
337ba017 | 3025 | GEN5_ASSERT_IIR_IS_ZERO(SDEIIR); |
d46da437 | 3026 | I915_WRITE(SDEIMR, ~mask); |
d46da437 PZ |
3027 | } |
3028 | ||
0a9a8c91 DV |
3029 | static void gen5_gt_irq_postinstall(struct drm_device *dev) |
3030 | { | |
3031 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3032 | u32 pm_irqs, gt_irqs; | |
3033 | ||
3034 | pm_irqs = gt_irqs = 0; | |
3035 | ||
3036 | dev_priv->gt_irq_mask = ~0; | |
040d2baa | 3037 | if (HAS_L3_DPF(dev)) { |
0a9a8c91 | 3038 | /* L3 parity interrupt is always unmasked. */ |
35a85ac6 BW |
3039 | dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev); |
3040 | gt_irqs |= GT_PARITY_ERROR(dev); | |
0a9a8c91 DV |
3041 | } |
3042 | ||
3043 | gt_irqs |= GT_RENDER_USER_INTERRUPT; | |
3044 | if (IS_GEN5(dev)) { | |
3045 | gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | | |
3046 | ILK_BSD_USER_INTERRUPT; | |
3047 | } else { | |
3048 | gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; | |
3049 | } | |
3050 | ||
35079899 | 3051 | GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); |
0a9a8c91 DV |
3052 | |
3053 | if (INTEL_INFO(dev)->gen >= 6) { | |
a6706b45 | 3054 | pm_irqs |= dev_priv->pm_rps_events; |
0a9a8c91 DV |
3055 | |
3056 | if (HAS_VEBOX(dev)) | |
3057 | pm_irqs |= PM_VEBOX_USER_INTERRUPT; | |
3058 | ||
605cd25b | 3059 | dev_priv->pm_irq_mask = 0xffffffff; |
35079899 | 3060 | GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs); |
0a9a8c91 DV |
3061 | } |
3062 | } | |
3063 | ||
f71d4af4 | 3064 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d | 3065 | { |
4bc9d430 | 3066 | unsigned long irqflags; |
2d1013dd | 3067 | struct drm_i915_private *dev_priv = dev->dev_private; |
8e76f8dc PZ |
3068 | u32 display_mask, extra_mask; |
3069 | ||
3070 | if (INTEL_INFO(dev)->gen >= 7) { | |
3071 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | | |
3072 | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | | |
3073 | DE_PLANEB_FLIP_DONE_IVB | | |
5c673b60 | 3074 | DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB); |
8e76f8dc | 3075 | extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | |
5c673b60 | 3076 | DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB); |
8e76f8dc PZ |
3077 | } else { |
3078 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | | |
3079 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | | |
5b3a856b | 3080 | DE_AUX_CHANNEL_A | |
5b3a856b DV |
3081 | DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE | |
3082 | DE_POISON); | |
5c673b60 DV |
3083 | extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT | |
3084 | DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN; | |
8e76f8dc | 3085 | } |
036a4a7d | 3086 | |
1ec14ad3 | 3087 | dev_priv->irq_mask = ~display_mask; |
036a4a7d | 3088 | |
0c841212 PZ |
3089 | I915_WRITE(HWSTAM, 0xeffe); |
3090 | ||
622364b6 PZ |
3091 | ibx_irq_pre_postinstall(dev); |
3092 | ||
35079899 | 3093 | GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); |
036a4a7d | 3094 | |
0a9a8c91 | 3095 | gen5_gt_irq_postinstall(dev); |
036a4a7d | 3096 | |
d46da437 | 3097 | ibx_irq_postinstall(dev); |
7fe0b973 | 3098 | |
f97108d1 | 3099 | if (IS_IRONLAKE_M(dev)) { |
6005ce42 DV |
3100 | /* Enable PCU event interrupts |
3101 | * | |
3102 | * spinlocking not required here for correctness since interrupt | |
4bc9d430 DV |
3103 | * setup is guaranteed to run in single-threaded context. But we |
3104 | * need it to make the assert_spin_locked happy. */ | |
3105 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
f97108d1 | 3106 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); |
4bc9d430 | 3107 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
f97108d1 JB |
3108 | } |
3109 | ||
036a4a7d ZW |
3110 | return 0; |
3111 | } | |
3112 | ||
f8b79e58 ID |
3113 | static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv) |
3114 | { | |
3115 | u32 pipestat_mask; | |
3116 | u32 iir_mask; | |
3117 | ||
3118 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | | |
3119 | PIPE_FIFO_UNDERRUN_STATUS; | |
3120 | ||
3121 | I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask); | |
3122 | I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask); | |
3123 | POSTING_READ(PIPESTAT(PIPE_A)); | |
3124 | ||
3125 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3126 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3127 | ||
3128 | i915_enable_pipestat(dev_priv, PIPE_A, pipestat_mask | | |
3129 | PIPE_GMBUS_INTERRUPT_STATUS); | |
3130 | i915_enable_pipestat(dev_priv, PIPE_B, pipestat_mask); | |
3131 | ||
3132 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3133 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3134 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
3135 | dev_priv->irq_mask &= ~iir_mask; | |
3136 | ||
3137 | I915_WRITE(VLV_IIR, iir_mask); | |
3138 | I915_WRITE(VLV_IIR, iir_mask); | |
3139 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); | |
3140 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); | |
3141 | POSTING_READ(VLV_IER); | |
3142 | } | |
3143 | ||
3144 | static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv) | |
3145 | { | |
3146 | u32 pipestat_mask; | |
3147 | u32 iir_mask; | |
3148 | ||
3149 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3150 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
6c7fba04 | 3151 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; |
f8b79e58 ID |
3152 | |
3153 | dev_priv->irq_mask |= iir_mask; | |
3154 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); | |
3155 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); | |
3156 | I915_WRITE(VLV_IIR, iir_mask); | |
3157 | I915_WRITE(VLV_IIR, iir_mask); | |
3158 | POSTING_READ(VLV_IIR); | |
3159 | ||
3160 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3161 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3162 | ||
3163 | i915_disable_pipestat(dev_priv, PIPE_A, pipestat_mask | | |
3164 | PIPE_GMBUS_INTERRUPT_STATUS); | |
3165 | i915_disable_pipestat(dev_priv, PIPE_B, pipestat_mask); | |
3166 | ||
3167 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | | |
3168 | PIPE_FIFO_UNDERRUN_STATUS; | |
3169 | I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask); | |
3170 | I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask); | |
3171 | POSTING_READ(PIPESTAT(PIPE_A)); | |
3172 | } | |
3173 | ||
3174 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) | |
3175 | { | |
3176 | assert_spin_locked(&dev_priv->irq_lock); | |
3177 | ||
3178 | if (dev_priv->display_irqs_enabled) | |
3179 | return; | |
3180 | ||
3181 | dev_priv->display_irqs_enabled = true; | |
3182 | ||
3183 | if (dev_priv->dev->irq_enabled) | |
3184 | valleyview_display_irqs_install(dev_priv); | |
3185 | } | |
3186 | ||
3187 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) | |
3188 | { | |
3189 | assert_spin_locked(&dev_priv->irq_lock); | |
3190 | ||
3191 | if (!dev_priv->display_irqs_enabled) | |
3192 | return; | |
3193 | ||
3194 | dev_priv->display_irqs_enabled = false; | |
3195 | ||
3196 | if (dev_priv->dev->irq_enabled) | |
3197 | valleyview_display_irqs_uninstall(dev_priv); | |
3198 | } | |
3199 | ||
7e231dbe JB |
3200 | static int valleyview_irq_postinstall(struct drm_device *dev) |
3201 | { | |
2d1013dd | 3202 | struct drm_i915_private *dev_priv = dev->dev_private; |
b79480ba | 3203 | unsigned long irqflags; |
7e231dbe | 3204 | |
f8b79e58 | 3205 | dev_priv->irq_mask = ~0; |
7e231dbe | 3206 | |
20afbda2 DV |
3207 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3208 | POSTING_READ(PORT_HOTPLUG_EN); | |
3209 | ||
7e231dbe | 3210 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
f8b79e58 | 3211 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); |
7e231dbe | 3212 | I915_WRITE(VLV_IIR, 0xffffffff); |
7e231dbe JB |
3213 | POSTING_READ(VLV_IER); |
3214 | ||
b79480ba DV |
3215 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3216 | * just to make the assert_spin_locked check happy. */ | |
3217 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
f8b79e58 ID |
3218 | if (dev_priv->display_irqs_enabled) |
3219 | valleyview_display_irqs_install(dev_priv); | |
b79480ba | 3220 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
31acc7f5 | 3221 | |
7e231dbe JB |
3222 | I915_WRITE(VLV_IIR, 0xffffffff); |
3223 | I915_WRITE(VLV_IIR, 0xffffffff); | |
3224 | ||
0a9a8c91 | 3225 | gen5_gt_irq_postinstall(dev); |
7e231dbe JB |
3226 | |
3227 | /* ack & enable invalid PTE error interrupts */ | |
3228 | #if 0 /* FIXME: add support to irq handler for checking these bits */ | |
3229 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); | |
3230 | I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); | |
3231 | #endif | |
3232 | ||
3233 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); | |
20afbda2 DV |
3234 | |
3235 | return 0; | |
3236 | } | |
3237 | ||
abd58f01 BW |
3238 | static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) |
3239 | { | |
3240 | int i; | |
3241 | ||
3242 | /* These are interrupts we'll toggle with the ring mask register */ | |
3243 | uint32_t gt_interrupts[] = { | |
3244 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | | |
3245 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT | | |
3246 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT, | |
3247 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | | |
3248 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT, | |
3249 | 0, | |
3250 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
3251 | }; | |
3252 | ||
337ba017 | 3253 | for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) |
35079899 | 3254 | GEN8_IRQ_INIT_NDX(GT, i, ~gt_interrupts[i], gt_interrupts[i]); |
abd58f01 BW |
3255 | } |
3256 | ||
3257 | static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) | |
3258 | { | |
3259 | struct drm_device *dev = dev_priv->dev; | |
d0e1f1cb | 3260 | uint32_t de_pipe_masked = GEN8_PIPE_PRIMARY_FLIP_DONE | |
13b3a0a7 | 3261 | GEN8_PIPE_CDCLK_CRC_DONE | |
13b3a0a7 | 3262 | GEN8_DE_PIPE_IRQ_FAULT_ERRORS; |
5c673b60 DV |
3263 | uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | |
3264 | GEN8_PIPE_FIFO_UNDERRUN; | |
abd58f01 | 3265 | int pipe; |
13b3a0a7 DV |
3266 | dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; |
3267 | dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; | |
3268 | dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; | |
abd58f01 | 3269 | |
337ba017 | 3270 | for_each_pipe(pipe) |
35079899 PZ |
3271 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, dev_priv->de_irq_mask[pipe], |
3272 | de_pipe_enables); | |
abd58f01 | 3273 | |
35079899 | 3274 | GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A); |
abd58f01 BW |
3275 | } |
3276 | ||
3277 | static int gen8_irq_postinstall(struct drm_device *dev) | |
3278 | { | |
3279 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3280 | ||
622364b6 PZ |
3281 | ibx_irq_pre_postinstall(dev); |
3282 | ||
abd58f01 BW |
3283 | gen8_gt_irq_postinstall(dev_priv); |
3284 | gen8_de_irq_postinstall(dev_priv); | |
3285 | ||
3286 | ibx_irq_postinstall(dev); | |
3287 | ||
3288 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); | |
3289 | POSTING_READ(GEN8_MASTER_IRQ); | |
3290 | ||
3291 | return 0; | |
3292 | } | |
3293 | ||
3294 | static void gen8_irq_uninstall(struct drm_device *dev) | |
3295 | { | |
3296 | struct drm_i915_private *dev_priv = dev->dev_private; | |
abd58f01 BW |
3297 | |
3298 | if (!dev_priv) | |
3299 | return; | |
3300 | ||
d4eb6b10 | 3301 | intel_hpd_irq_uninstall(dev_priv); |
abd58f01 | 3302 | |
823f6b38 | 3303 | gen8_irq_reset(dev); |
abd58f01 BW |
3304 | } |
3305 | ||
7e231dbe JB |
3306 | static void valleyview_irq_uninstall(struct drm_device *dev) |
3307 | { | |
2d1013dd | 3308 | struct drm_i915_private *dev_priv = dev->dev_private; |
f8b79e58 | 3309 | unsigned long irqflags; |
7e231dbe JB |
3310 | int pipe; |
3311 | ||
3312 | if (!dev_priv) | |
3313 | return; | |
3314 | ||
843d0e7d ID |
3315 | I915_WRITE(VLV_MASTER_IER, 0); |
3316 | ||
3ca1cced | 3317 | intel_hpd_irq_uninstall(dev_priv); |
ac4c16c5 | 3318 | |
7e231dbe JB |
3319 | for_each_pipe(pipe) |
3320 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
3321 | ||
3322 | I915_WRITE(HWSTAM, 0xffffffff); | |
3323 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3324 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
f8b79e58 ID |
3325 | |
3326 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3327 | if (dev_priv->display_irqs_enabled) | |
3328 | valleyview_display_irqs_uninstall(dev_priv); | |
3329 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3330 | ||
3331 | dev_priv->irq_mask = 0; | |
3332 | ||
7e231dbe JB |
3333 | I915_WRITE(VLV_IIR, 0xffffffff); |
3334 | I915_WRITE(VLV_IMR, 0xffffffff); | |
3335 | I915_WRITE(VLV_IER, 0x0); | |
3336 | POSTING_READ(VLV_IER); | |
3337 | } | |
3338 | ||
f71d4af4 | 3339 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d | 3340 | { |
2d1013dd | 3341 | struct drm_i915_private *dev_priv = dev->dev_private; |
4697995b JB |
3342 | |
3343 | if (!dev_priv) | |
3344 | return; | |
3345 | ||
3ca1cced | 3346 | intel_hpd_irq_uninstall(dev_priv); |
ac4c16c5 | 3347 | |
be30b29f | 3348 | ironlake_irq_reset(dev); |
036a4a7d ZW |
3349 | } |
3350 | ||
a266c7d5 | 3351 | static void i8xx_irq_preinstall(struct drm_device * dev) |
1da177e4 | 3352 | { |
2d1013dd | 3353 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 3354 | int pipe; |
91e3738e | 3355 | |
9db4a9c7 JB |
3356 | for_each_pipe(pipe) |
3357 | I915_WRITE(PIPESTAT(pipe), 0); | |
a266c7d5 CW |
3358 | I915_WRITE16(IMR, 0xffff); |
3359 | I915_WRITE16(IER, 0x0); | |
3360 | POSTING_READ16(IER); | |
c2798b19 CW |
3361 | } |
3362 | ||
3363 | static int i8xx_irq_postinstall(struct drm_device *dev) | |
3364 | { | |
2d1013dd | 3365 | struct drm_i915_private *dev_priv = dev->dev_private; |
379ef82d | 3366 | unsigned long irqflags; |
c2798b19 | 3367 | |
c2798b19 CW |
3368 | I915_WRITE16(EMR, |
3369 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); | |
3370 | ||
3371 | /* Unmask the interrupts that we always want on. */ | |
3372 | dev_priv->irq_mask = | |
3373 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3374 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3375 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3376 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3377 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3378 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
3379 | ||
3380 | I915_WRITE16(IER, | |
3381 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3382 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3383 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
3384 | I915_USER_INTERRUPT); | |
3385 | POSTING_READ16(IER); | |
3386 | ||
379ef82d DV |
3387 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3388 | * just to make the assert_spin_locked check happy. */ | |
3389 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
755e9019 ID |
3390 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3391 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
379ef82d DV |
3392 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
3393 | ||
c2798b19 CW |
3394 | return 0; |
3395 | } | |
3396 | ||
90a72f87 VS |
3397 | /* |
3398 | * Returns true when a page flip has completed. | |
3399 | */ | |
3400 | static bool i8xx_handle_vblank(struct drm_device *dev, | |
1f1c2e24 | 3401 | int plane, int pipe, u32 iir) |
90a72f87 | 3402 | { |
2d1013dd | 3403 | struct drm_i915_private *dev_priv = dev->dev_private; |
1f1c2e24 | 3404 | u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
90a72f87 | 3405 | |
8d7849db | 3406 | if (!intel_pipe_handle_vblank(dev, pipe)) |
90a72f87 VS |
3407 | return false; |
3408 | ||
3409 | if ((iir & flip_pending) == 0) | |
3410 | return false; | |
3411 | ||
1f1c2e24 | 3412 | intel_prepare_page_flip(dev, plane); |
90a72f87 VS |
3413 | |
3414 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
3415 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3416 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3417 | * the flip is completed (no longer pending). Since this doesn't raise | |
3418 | * an interrupt per se, we watch for the change at vblank. | |
3419 | */ | |
3420 | if (I915_READ16(ISR) & flip_pending) | |
3421 | return false; | |
3422 | ||
3423 | intel_finish_page_flip(dev, pipe); | |
3424 | ||
3425 | return true; | |
3426 | } | |
3427 | ||
ff1f525e | 3428 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
c2798b19 CW |
3429 | { |
3430 | struct drm_device *dev = (struct drm_device *) arg; | |
2d1013dd | 3431 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
3432 | u16 iir, new_iir; |
3433 | u32 pipe_stats[2]; | |
3434 | unsigned long irqflags; | |
c2798b19 CW |
3435 | int pipe; |
3436 | u16 flip_mask = | |
3437 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3438 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
3439 | ||
c2798b19 CW |
3440 | iir = I915_READ16(IIR); |
3441 | if (iir == 0) | |
3442 | return IRQ_NONE; | |
3443 | ||
3444 | while (iir & ~flip_mask) { | |
3445 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3446 | * have been cleared after the pipestat interrupt was received. | |
3447 | * It doesn't set the bit in iir again, but it still produces | |
3448 | * interrupts (for non-MSI). | |
3449 | */ | |
3450 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3451 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
58174462 MK |
3452 | i915_handle_error(dev, false, |
3453 | "Command parser error, iir 0x%08x", | |
3454 | iir); | |
c2798b19 CW |
3455 | |
3456 | for_each_pipe(pipe) { | |
3457 | int reg = PIPESTAT(pipe); | |
3458 | pipe_stats[pipe] = I915_READ(reg); | |
3459 | ||
3460 | /* | |
3461 | * Clear the PIPE*STAT regs before the IIR | |
3462 | */ | |
2d9d2b0b | 3463 | if (pipe_stats[pipe] & 0x8000ffff) |
c2798b19 | 3464 | I915_WRITE(reg, pipe_stats[pipe]); |
c2798b19 CW |
3465 | } |
3466 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3467 | ||
3468 | I915_WRITE16(IIR, iir & ~flip_mask); | |
3469 | new_iir = I915_READ16(IIR); /* Flush posted writes */ | |
3470 | ||
d05c617e | 3471 | i915_update_dri1_breadcrumb(dev); |
c2798b19 CW |
3472 | |
3473 | if (iir & I915_USER_INTERRUPT) | |
3474 | notify_ring(dev, &dev_priv->ring[RCS]); | |
3475 | ||
4356d586 | 3476 | for_each_pipe(pipe) { |
1f1c2e24 | 3477 | int plane = pipe; |
3a77c4c4 | 3478 | if (HAS_FBC(dev)) |
1f1c2e24 VS |
3479 | plane = !plane; |
3480 | ||
4356d586 | 3481 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
1f1c2e24 VS |
3482 | i8xx_handle_vblank(dev, plane, pipe, iir)) |
3483 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
c2798b19 | 3484 | |
4356d586 | 3485 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
277de95e | 3486 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b VS |
3487 | |
3488 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && | |
3489 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
fc2c807b | 3490 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); |
4356d586 | 3491 | } |
c2798b19 CW |
3492 | |
3493 | iir = new_iir; | |
3494 | } | |
3495 | ||
3496 | return IRQ_HANDLED; | |
3497 | } | |
3498 | ||
3499 | static void i8xx_irq_uninstall(struct drm_device * dev) | |
3500 | { | |
2d1013dd | 3501 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
3502 | int pipe; |
3503 | ||
c2798b19 CW |
3504 | for_each_pipe(pipe) { |
3505 | /* Clear enable bits; then clear status bits */ | |
3506 | I915_WRITE(PIPESTAT(pipe), 0); | |
3507 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); | |
3508 | } | |
3509 | I915_WRITE16(IMR, 0xffff); | |
3510 | I915_WRITE16(IER, 0x0); | |
3511 | I915_WRITE16(IIR, I915_READ16(IIR)); | |
3512 | } | |
3513 | ||
a266c7d5 CW |
3514 | static void i915_irq_preinstall(struct drm_device * dev) |
3515 | { | |
2d1013dd | 3516 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3517 | int pipe; |
3518 | ||
a266c7d5 CW |
3519 | if (I915_HAS_HOTPLUG(dev)) { |
3520 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3521 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3522 | } | |
3523 | ||
00d98ebd | 3524 | I915_WRITE16(HWSTAM, 0xeffe); |
a266c7d5 CW |
3525 | for_each_pipe(pipe) |
3526 | I915_WRITE(PIPESTAT(pipe), 0); | |
3527 | I915_WRITE(IMR, 0xffffffff); | |
3528 | I915_WRITE(IER, 0x0); | |
3529 | POSTING_READ(IER); | |
3530 | } | |
3531 | ||
3532 | static int i915_irq_postinstall(struct drm_device *dev) | |
3533 | { | |
2d1013dd | 3534 | struct drm_i915_private *dev_priv = dev->dev_private; |
38bde180 | 3535 | u32 enable_mask; |
379ef82d | 3536 | unsigned long irqflags; |
a266c7d5 | 3537 | |
38bde180 CW |
3538 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
3539 | ||
3540 | /* Unmask the interrupts that we always want on. */ | |
3541 | dev_priv->irq_mask = | |
3542 | ~(I915_ASLE_INTERRUPT | | |
3543 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3544 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3545 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3546 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3547 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3548 | ||
3549 | enable_mask = | |
3550 | I915_ASLE_INTERRUPT | | |
3551 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3552 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3553 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
3554 | I915_USER_INTERRUPT; | |
3555 | ||
a266c7d5 | 3556 | if (I915_HAS_HOTPLUG(dev)) { |
20afbda2 DV |
3557 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3558 | POSTING_READ(PORT_HOTPLUG_EN); | |
3559 | ||
a266c7d5 CW |
3560 | /* Enable in IER... */ |
3561 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
3562 | /* and unmask in IMR */ | |
3563 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; | |
3564 | } | |
3565 | ||
a266c7d5 CW |
3566 | I915_WRITE(IMR, dev_priv->irq_mask); |
3567 | I915_WRITE(IER, enable_mask); | |
3568 | POSTING_READ(IER); | |
3569 | ||
f49e38dd | 3570 | i915_enable_asle_pipestat(dev); |
20afbda2 | 3571 | |
379ef82d DV |
3572 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3573 | * just to make the assert_spin_locked check happy. */ | |
3574 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
755e9019 ID |
3575 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3576 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
379ef82d DV |
3577 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
3578 | ||
20afbda2 DV |
3579 | return 0; |
3580 | } | |
3581 | ||
90a72f87 VS |
3582 | /* |
3583 | * Returns true when a page flip has completed. | |
3584 | */ | |
3585 | static bool i915_handle_vblank(struct drm_device *dev, | |
3586 | int plane, int pipe, u32 iir) | |
3587 | { | |
2d1013dd | 3588 | struct drm_i915_private *dev_priv = dev->dev_private; |
90a72f87 VS |
3589 | u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
3590 | ||
8d7849db | 3591 | if (!intel_pipe_handle_vblank(dev, pipe)) |
90a72f87 VS |
3592 | return false; |
3593 | ||
3594 | if ((iir & flip_pending) == 0) | |
3595 | return false; | |
3596 | ||
3597 | intel_prepare_page_flip(dev, plane); | |
3598 | ||
3599 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
3600 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3601 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3602 | * the flip is completed (no longer pending). Since this doesn't raise | |
3603 | * an interrupt per se, we watch for the change at vblank. | |
3604 | */ | |
3605 | if (I915_READ(ISR) & flip_pending) | |
3606 | return false; | |
3607 | ||
3608 | intel_finish_page_flip(dev, pipe); | |
3609 | ||
3610 | return true; | |
3611 | } | |
3612 | ||
ff1f525e | 3613 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
a266c7d5 CW |
3614 | { |
3615 | struct drm_device *dev = (struct drm_device *) arg; | |
2d1013dd | 3616 | struct drm_i915_private *dev_priv = dev->dev_private; |
8291ee90 | 3617 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
a266c7d5 | 3618 | unsigned long irqflags; |
38bde180 CW |
3619 | u32 flip_mask = |
3620 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3621 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
38bde180 | 3622 | int pipe, ret = IRQ_NONE; |
a266c7d5 | 3623 | |
a266c7d5 | 3624 | iir = I915_READ(IIR); |
38bde180 CW |
3625 | do { |
3626 | bool irq_received = (iir & ~flip_mask) != 0; | |
8291ee90 | 3627 | bool blc_event = false; |
a266c7d5 CW |
3628 | |
3629 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3630 | * have been cleared after the pipestat interrupt was received. | |
3631 | * It doesn't set the bit in iir again, but it still produces | |
3632 | * interrupts (for non-MSI). | |
3633 | */ | |
3634 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3635 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
58174462 MK |
3636 | i915_handle_error(dev, false, |
3637 | "Command parser error, iir 0x%08x", | |
3638 | iir); | |
a266c7d5 CW |
3639 | |
3640 | for_each_pipe(pipe) { | |
3641 | int reg = PIPESTAT(pipe); | |
3642 | pipe_stats[pipe] = I915_READ(reg); | |
3643 | ||
38bde180 | 3644 | /* Clear the PIPE*STAT regs before the IIR */ |
a266c7d5 | 3645 | if (pipe_stats[pipe] & 0x8000ffff) { |
a266c7d5 | 3646 | I915_WRITE(reg, pipe_stats[pipe]); |
38bde180 | 3647 | irq_received = true; |
a266c7d5 CW |
3648 | } |
3649 | } | |
3650 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3651 | ||
3652 | if (!irq_received) | |
3653 | break; | |
3654 | ||
a266c7d5 | 3655 | /* Consume port. Then clear IIR or we'll miss events */ |
16c6c56b VS |
3656 | if (I915_HAS_HOTPLUG(dev) && |
3657 | iir & I915_DISPLAY_PORT_INTERRUPT) | |
3658 | i9xx_hpd_irq_handler(dev); | |
a266c7d5 | 3659 | |
38bde180 | 3660 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
3661 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
3662 | ||
a266c7d5 CW |
3663 | if (iir & I915_USER_INTERRUPT) |
3664 | notify_ring(dev, &dev_priv->ring[RCS]); | |
a266c7d5 | 3665 | |
a266c7d5 | 3666 | for_each_pipe(pipe) { |
38bde180 | 3667 | int plane = pipe; |
3a77c4c4 | 3668 | if (HAS_FBC(dev)) |
38bde180 | 3669 | plane = !plane; |
90a72f87 | 3670 | |
8291ee90 | 3671 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
3672 | i915_handle_vblank(dev, plane, pipe, iir)) |
3673 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
a266c7d5 CW |
3674 | |
3675 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
3676 | blc_event = true; | |
4356d586 DV |
3677 | |
3678 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 3679 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b VS |
3680 | |
3681 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && | |
3682 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
fc2c807b | 3683 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); |
a266c7d5 CW |
3684 | } |
3685 | ||
a266c7d5 CW |
3686 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
3687 | intel_opregion_asle_intr(dev); | |
3688 | ||
3689 | /* With MSI, interrupts are only generated when iir | |
3690 | * transitions from zero to nonzero. If another bit got | |
3691 | * set while we were handling the existing iir bits, then | |
3692 | * we would never get another interrupt. | |
3693 | * | |
3694 | * This is fine on non-MSI as well, as if we hit this path | |
3695 | * we avoid exiting the interrupt handler only to generate | |
3696 | * another one. | |
3697 | * | |
3698 | * Note that for MSI this could cause a stray interrupt report | |
3699 | * if an interrupt landed in the time between writing IIR and | |
3700 | * the posting read. This should be rare enough to never | |
3701 | * trigger the 99% of 100,000 interrupts test for disabling | |
3702 | * stray interrupts. | |
3703 | */ | |
38bde180 | 3704 | ret = IRQ_HANDLED; |
a266c7d5 | 3705 | iir = new_iir; |
38bde180 | 3706 | } while (iir & ~flip_mask); |
a266c7d5 | 3707 | |
d05c617e | 3708 | i915_update_dri1_breadcrumb(dev); |
8291ee90 | 3709 | |
a266c7d5 CW |
3710 | return ret; |
3711 | } | |
3712 | ||
3713 | static void i915_irq_uninstall(struct drm_device * dev) | |
3714 | { | |
2d1013dd | 3715 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3716 | int pipe; |
3717 | ||
3ca1cced | 3718 | intel_hpd_irq_uninstall(dev_priv); |
ac4c16c5 | 3719 | |
a266c7d5 CW |
3720 | if (I915_HAS_HOTPLUG(dev)) { |
3721 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3722 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3723 | } | |
3724 | ||
00d98ebd | 3725 | I915_WRITE16(HWSTAM, 0xffff); |
55b39755 CW |
3726 | for_each_pipe(pipe) { |
3727 | /* Clear enable bits; then clear status bits */ | |
a266c7d5 | 3728 | I915_WRITE(PIPESTAT(pipe), 0); |
55b39755 CW |
3729 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
3730 | } | |
a266c7d5 CW |
3731 | I915_WRITE(IMR, 0xffffffff); |
3732 | I915_WRITE(IER, 0x0); | |
3733 | ||
a266c7d5 CW |
3734 | I915_WRITE(IIR, I915_READ(IIR)); |
3735 | } | |
3736 | ||
3737 | static void i965_irq_preinstall(struct drm_device * dev) | |
3738 | { | |
2d1013dd | 3739 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3740 | int pipe; |
3741 | ||
adca4730 CW |
3742 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3743 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
3744 | |
3745 | I915_WRITE(HWSTAM, 0xeffe); | |
3746 | for_each_pipe(pipe) | |
3747 | I915_WRITE(PIPESTAT(pipe), 0); | |
3748 | I915_WRITE(IMR, 0xffffffff); | |
3749 | I915_WRITE(IER, 0x0); | |
3750 | POSTING_READ(IER); | |
3751 | } | |
3752 | ||
3753 | static int i965_irq_postinstall(struct drm_device *dev) | |
3754 | { | |
2d1013dd | 3755 | struct drm_i915_private *dev_priv = dev->dev_private; |
bbba0a97 | 3756 | u32 enable_mask; |
a266c7d5 | 3757 | u32 error_mask; |
b79480ba | 3758 | unsigned long irqflags; |
a266c7d5 | 3759 | |
a266c7d5 | 3760 | /* Unmask the interrupts that we always want on. */ |
bbba0a97 | 3761 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
adca4730 | 3762 | I915_DISPLAY_PORT_INTERRUPT | |
bbba0a97 CW |
3763 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
3764 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3765 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3766 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3767 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3768 | ||
3769 | enable_mask = ~dev_priv->irq_mask; | |
21ad8330 VS |
3770 | enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
3771 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); | |
bbba0a97 CW |
3772 | enable_mask |= I915_USER_INTERRUPT; |
3773 | ||
3774 | if (IS_G4X(dev)) | |
3775 | enable_mask |= I915_BSD_USER_INTERRUPT; | |
a266c7d5 | 3776 | |
b79480ba DV |
3777 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3778 | * just to make the assert_spin_locked check happy. */ | |
3779 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
755e9019 ID |
3780 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
3781 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
3782 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
b79480ba | 3783 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
a266c7d5 | 3784 | |
a266c7d5 CW |
3785 | /* |
3786 | * Enable some error detection, note the instruction error mask | |
3787 | * bit is reserved, so we leave it masked. | |
3788 | */ | |
3789 | if (IS_G4X(dev)) { | |
3790 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
3791 | GM45_ERROR_MEM_PRIV | | |
3792 | GM45_ERROR_CP_PRIV | | |
3793 | I915_ERROR_MEMORY_REFRESH); | |
3794 | } else { | |
3795 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
3796 | I915_ERROR_MEMORY_REFRESH); | |
3797 | } | |
3798 | I915_WRITE(EMR, error_mask); | |
3799 | ||
3800 | I915_WRITE(IMR, dev_priv->irq_mask); | |
3801 | I915_WRITE(IER, enable_mask); | |
3802 | POSTING_READ(IER); | |
3803 | ||
20afbda2 DV |
3804 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3805 | POSTING_READ(PORT_HOTPLUG_EN); | |
3806 | ||
f49e38dd | 3807 | i915_enable_asle_pipestat(dev); |
20afbda2 DV |
3808 | |
3809 | return 0; | |
3810 | } | |
3811 | ||
bac56d5b | 3812 | static void i915_hpd_irq_setup(struct drm_device *dev) |
20afbda2 | 3813 | { |
2d1013dd | 3814 | struct drm_i915_private *dev_priv = dev->dev_private; |
e5868a31 | 3815 | struct drm_mode_config *mode_config = &dev->mode_config; |
cd569aed | 3816 | struct intel_encoder *intel_encoder; |
20afbda2 DV |
3817 | u32 hotplug_en; |
3818 | ||
b5ea2d56 DV |
3819 | assert_spin_locked(&dev_priv->irq_lock); |
3820 | ||
bac56d5b EE |
3821 | if (I915_HAS_HOTPLUG(dev)) { |
3822 | hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
3823 | hotplug_en &= ~HOTPLUG_INT_EN_MASK; | |
3824 | /* Note HDMI and DP share hotplug bits */ | |
e5868a31 | 3825 | /* enable bits are the same for all generations */ |
cd569aed EE |
3826 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
3827 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) | |
3828 | hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin]; | |
bac56d5b EE |
3829 | /* Programming the CRT detection parameters tends |
3830 | to generate a spurious hotplug event about three | |
3831 | seconds later. So just do it once. | |
3832 | */ | |
3833 | if (IS_G4X(dev)) | |
3834 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
85fc95ba | 3835 | hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK; |
bac56d5b | 3836 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
a266c7d5 | 3837 | |
bac56d5b EE |
3838 | /* Ignore TV since it's buggy */ |
3839 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
3840 | } | |
a266c7d5 CW |
3841 | } |
3842 | ||
ff1f525e | 3843 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
a266c7d5 CW |
3844 | { |
3845 | struct drm_device *dev = (struct drm_device *) arg; | |
2d1013dd | 3846 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3847 | u32 iir, new_iir; |
3848 | u32 pipe_stats[I915_MAX_PIPES]; | |
a266c7d5 | 3849 | unsigned long irqflags; |
a266c7d5 | 3850 | int ret = IRQ_NONE, pipe; |
21ad8330 VS |
3851 | u32 flip_mask = |
3852 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3853 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
a266c7d5 | 3854 | |
a266c7d5 CW |
3855 | iir = I915_READ(IIR); |
3856 | ||
a266c7d5 | 3857 | for (;;) { |
501e01d7 | 3858 | bool irq_received = (iir & ~flip_mask) != 0; |
2c8ba29f CW |
3859 | bool blc_event = false; |
3860 | ||
a266c7d5 CW |
3861 | /* Can't rely on pipestat interrupt bit in iir as it might |
3862 | * have been cleared after the pipestat interrupt was received. | |
3863 | * It doesn't set the bit in iir again, but it still produces | |
3864 | * interrupts (for non-MSI). | |
3865 | */ | |
3866 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3867 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
58174462 MK |
3868 | i915_handle_error(dev, false, |
3869 | "Command parser error, iir 0x%08x", | |
3870 | iir); | |
a266c7d5 CW |
3871 | |
3872 | for_each_pipe(pipe) { | |
3873 | int reg = PIPESTAT(pipe); | |
3874 | pipe_stats[pipe] = I915_READ(reg); | |
3875 | ||
3876 | /* | |
3877 | * Clear the PIPE*STAT regs before the IIR | |
3878 | */ | |
3879 | if (pipe_stats[pipe] & 0x8000ffff) { | |
a266c7d5 | 3880 | I915_WRITE(reg, pipe_stats[pipe]); |
501e01d7 | 3881 | irq_received = true; |
a266c7d5 CW |
3882 | } |
3883 | } | |
3884 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3885 | ||
3886 | if (!irq_received) | |
3887 | break; | |
3888 | ||
3889 | ret = IRQ_HANDLED; | |
3890 | ||
3891 | /* Consume port. Then clear IIR or we'll miss events */ | |
16c6c56b VS |
3892 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
3893 | i9xx_hpd_irq_handler(dev); | |
a266c7d5 | 3894 | |
21ad8330 | 3895 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
3896 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
3897 | ||
a266c7d5 CW |
3898 | if (iir & I915_USER_INTERRUPT) |
3899 | notify_ring(dev, &dev_priv->ring[RCS]); | |
3900 | if (iir & I915_BSD_USER_INTERRUPT) | |
3901 | notify_ring(dev, &dev_priv->ring[VCS]); | |
3902 | ||
a266c7d5 | 3903 | for_each_pipe(pipe) { |
2c8ba29f | 3904 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
3905 | i915_handle_vblank(dev, pipe, pipe, iir)) |
3906 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); | |
a266c7d5 CW |
3907 | |
3908 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
3909 | blc_event = true; | |
4356d586 DV |
3910 | |
3911 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 3912 | i9xx_pipe_crc_irq_handler(dev, pipe); |
a266c7d5 | 3913 | |
2d9d2b0b VS |
3914 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && |
3915 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
fc2c807b | 3916 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); |
2d9d2b0b | 3917 | } |
a266c7d5 CW |
3918 | |
3919 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | |
3920 | intel_opregion_asle_intr(dev); | |
3921 | ||
515ac2bb DV |
3922 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
3923 | gmbus_irq_handler(dev); | |
3924 | ||
a266c7d5 CW |
3925 | /* With MSI, interrupts are only generated when iir |
3926 | * transitions from zero to nonzero. If another bit got | |
3927 | * set while we were handling the existing iir bits, then | |
3928 | * we would never get another interrupt. | |
3929 | * | |
3930 | * This is fine on non-MSI as well, as if we hit this path | |
3931 | * we avoid exiting the interrupt handler only to generate | |
3932 | * another one. | |
3933 | * | |
3934 | * Note that for MSI this could cause a stray interrupt report | |
3935 | * if an interrupt landed in the time between writing IIR and | |
3936 | * the posting read. This should be rare enough to never | |
3937 | * trigger the 99% of 100,000 interrupts test for disabling | |
3938 | * stray interrupts. | |
3939 | */ | |
3940 | iir = new_iir; | |
3941 | } | |
3942 | ||
d05c617e | 3943 | i915_update_dri1_breadcrumb(dev); |
2c8ba29f | 3944 | |
a266c7d5 CW |
3945 | return ret; |
3946 | } | |
3947 | ||
3948 | static void i965_irq_uninstall(struct drm_device * dev) | |
3949 | { | |
2d1013dd | 3950 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3951 | int pipe; |
3952 | ||
3953 | if (!dev_priv) | |
3954 | return; | |
3955 | ||
3ca1cced | 3956 | intel_hpd_irq_uninstall(dev_priv); |
ac4c16c5 | 3957 | |
adca4730 CW |
3958 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3959 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
3960 | |
3961 | I915_WRITE(HWSTAM, 0xffffffff); | |
3962 | for_each_pipe(pipe) | |
3963 | I915_WRITE(PIPESTAT(pipe), 0); | |
3964 | I915_WRITE(IMR, 0xffffffff); | |
3965 | I915_WRITE(IER, 0x0); | |
3966 | ||
3967 | for_each_pipe(pipe) | |
3968 | I915_WRITE(PIPESTAT(pipe), | |
3969 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); | |
3970 | I915_WRITE(IIR, I915_READ(IIR)); | |
3971 | } | |
3972 | ||
3ca1cced | 3973 | static void intel_hpd_irq_reenable(unsigned long data) |
ac4c16c5 | 3974 | { |
2d1013dd | 3975 | struct drm_i915_private *dev_priv = (struct drm_i915_private *)data; |
ac4c16c5 EE |
3976 | struct drm_device *dev = dev_priv->dev; |
3977 | struct drm_mode_config *mode_config = &dev->mode_config; | |
3978 | unsigned long irqflags; | |
3979 | int i; | |
3980 | ||
3981 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3982 | for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) { | |
3983 | struct drm_connector *connector; | |
3984 | ||
3985 | if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED) | |
3986 | continue; | |
3987 | ||
3988 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
3989 | ||
3990 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
3991 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
3992 | ||
3993 | if (intel_connector->encoder->hpd_pin == i) { | |
3994 | if (connector->polled != intel_connector->polled) | |
3995 | DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n", | |
3996 | drm_get_connector_name(connector)); | |
3997 | connector->polled = intel_connector->polled; | |
3998 | if (!connector->polled) | |
3999 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
4000 | } | |
4001 | } | |
4002 | } | |
4003 | if (dev_priv->display.hpd_irq_setup) | |
4004 | dev_priv->display.hpd_irq_setup(dev); | |
4005 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
4006 | } | |
4007 | ||
f71d4af4 JB |
4008 | void intel_irq_init(struct drm_device *dev) |
4009 | { | |
8b2e326d CW |
4010 | struct drm_i915_private *dev_priv = dev->dev_private; |
4011 | ||
4012 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); | |
99584db3 | 4013 | INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func); |
c6a828d3 | 4014 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
a4da4fa4 | 4015 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
8b2e326d | 4016 | |
a6706b45 D |
4017 | /* Let's track the enabled rps events */ |
4018 | dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; | |
4019 | ||
99584db3 DV |
4020 | setup_timer(&dev_priv->gpu_error.hangcheck_timer, |
4021 | i915_hangcheck_elapsed, | |
61bac78e | 4022 | (unsigned long) dev); |
3ca1cced | 4023 | setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable, |
ac4c16c5 | 4024 | (unsigned long) dev_priv); |
61bac78e | 4025 | |
97a19a24 | 4026 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); |
9ee32fea | 4027 | |
4cdb83ec VS |
4028 | if (IS_GEN2(dev)) { |
4029 | dev->max_vblank_count = 0; | |
4030 | dev->driver->get_vblank_counter = i8xx_get_vblank_counter; | |
4031 | } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { | |
f71d4af4 JB |
4032 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
4033 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; | |
391f75e2 VS |
4034 | } else { |
4035 | dev->driver->get_vblank_counter = i915_get_vblank_counter; | |
4036 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
f71d4af4 JB |
4037 | } |
4038 | ||
c2baf4b7 | 4039 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
c3613de9 | 4040 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; |
c2baf4b7 VS |
4041 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; |
4042 | } | |
f71d4af4 | 4043 | |
7e231dbe JB |
4044 | if (IS_VALLEYVIEW(dev)) { |
4045 | dev->driver->irq_handler = valleyview_irq_handler; | |
4046 | dev->driver->irq_preinstall = valleyview_irq_preinstall; | |
4047 | dev->driver->irq_postinstall = valleyview_irq_postinstall; | |
4048 | dev->driver->irq_uninstall = valleyview_irq_uninstall; | |
4049 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4050 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
fa00abe0 | 4051 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
abd58f01 BW |
4052 | } else if (IS_GEN8(dev)) { |
4053 | dev->driver->irq_handler = gen8_irq_handler; | |
4054 | dev->driver->irq_preinstall = gen8_irq_preinstall; | |
4055 | dev->driver->irq_postinstall = gen8_irq_postinstall; | |
4056 | dev->driver->irq_uninstall = gen8_irq_uninstall; | |
4057 | dev->driver->enable_vblank = gen8_enable_vblank; | |
4058 | dev->driver->disable_vblank = gen8_disable_vblank; | |
4059 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; | |
f71d4af4 JB |
4060 | } else if (HAS_PCH_SPLIT(dev)) { |
4061 | dev->driver->irq_handler = ironlake_irq_handler; | |
4062 | dev->driver->irq_preinstall = ironlake_irq_preinstall; | |
4063 | dev->driver->irq_postinstall = ironlake_irq_postinstall; | |
4064 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
4065 | dev->driver->enable_vblank = ironlake_enable_vblank; | |
4066 | dev->driver->disable_vblank = ironlake_disable_vblank; | |
82a28bcf | 4067 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; |
f71d4af4 | 4068 | } else { |
c2798b19 CW |
4069 | if (INTEL_INFO(dev)->gen == 2) { |
4070 | dev->driver->irq_preinstall = i8xx_irq_preinstall; | |
4071 | dev->driver->irq_postinstall = i8xx_irq_postinstall; | |
4072 | dev->driver->irq_handler = i8xx_irq_handler; | |
4073 | dev->driver->irq_uninstall = i8xx_irq_uninstall; | |
a266c7d5 CW |
4074 | } else if (INTEL_INFO(dev)->gen == 3) { |
4075 | dev->driver->irq_preinstall = i915_irq_preinstall; | |
4076 | dev->driver->irq_postinstall = i915_irq_postinstall; | |
4077 | dev->driver->irq_uninstall = i915_irq_uninstall; | |
4078 | dev->driver->irq_handler = i915_irq_handler; | |
20afbda2 | 4079 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
c2798b19 | 4080 | } else { |
a266c7d5 CW |
4081 | dev->driver->irq_preinstall = i965_irq_preinstall; |
4082 | dev->driver->irq_postinstall = i965_irq_postinstall; | |
4083 | dev->driver->irq_uninstall = i965_irq_uninstall; | |
4084 | dev->driver->irq_handler = i965_irq_handler; | |
bac56d5b | 4085 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
c2798b19 | 4086 | } |
f71d4af4 JB |
4087 | dev->driver->enable_vblank = i915_enable_vblank; |
4088 | dev->driver->disable_vblank = i915_disable_vblank; | |
4089 | } | |
4090 | } | |
20afbda2 DV |
4091 | |
4092 | void intel_hpd_init(struct drm_device *dev) | |
4093 | { | |
4094 | struct drm_i915_private *dev_priv = dev->dev_private; | |
821450c6 EE |
4095 | struct drm_mode_config *mode_config = &dev->mode_config; |
4096 | struct drm_connector *connector; | |
b5ea2d56 | 4097 | unsigned long irqflags; |
821450c6 | 4098 | int i; |
20afbda2 | 4099 | |
821450c6 EE |
4100 | for (i = 1; i < HPD_NUM_PINS; i++) { |
4101 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
4102 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
4103 | } | |
4104 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
4105 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4106 | connector->polled = intel_connector->polled; | |
4107 | if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE) | |
4108 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
4109 | } | |
b5ea2d56 DV |
4110 | |
4111 | /* Interrupt setup is already guaranteed to be single-threaded, this is | |
4112 | * just to make the assert_spin_locked checks happy. */ | |
4113 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
20afbda2 DV |
4114 | if (dev_priv->display.hpd_irq_setup) |
4115 | dev_priv->display.hpd_irq_setup(dev); | |
b5ea2d56 | 4116 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
20afbda2 | 4117 | } |
c67a470b | 4118 | |
5d584b2e | 4119 | /* Disable interrupts so we can allow runtime PM. */ |
730488b2 | 4120 | void intel_runtime_pm_disable_interrupts(struct drm_device *dev) |
c67a470b PZ |
4121 | { |
4122 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c67a470b | 4123 | |
730488b2 | 4124 | dev->driver->irq_uninstall(dev); |
5d584b2e | 4125 | dev_priv->pm.irqs_disabled = true; |
c67a470b PZ |
4126 | } |
4127 | ||
5d584b2e | 4128 | /* Restore interrupts so we can recover from runtime PM. */ |
730488b2 | 4129 | void intel_runtime_pm_restore_interrupts(struct drm_device *dev) |
c67a470b PZ |
4130 | { |
4131 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c67a470b | 4132 | |
5d584b2e | 4133 | dev_priv->pm.irqs_disabled = false; |
730488b2 PZ |
4134 | dev->driver->irq_preinstall(dev); |
4135 | dev->driver->irq_postinstall(dev); | |
c67a470b | 4136 | } |