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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
63eeaf38 | 29 | #include <linux/sysrq.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
1da177e4 LT |
31 | #include "drmP.h" |
32 | #include "drm.h" | |
33 | #include "i915_drm.h" | |
34 | #include "i915_drv.h" | |
1c5d22f7 | 35 | #include "i915_trace.h" |
79e53945 | 36 | #include "intel_drv.h" |
1da177e4 | 37 | |
1da177e4 | 38 | #define MAX_NOPID ((u32)~0) |
1da177e4 | 39 | |
7c463586 KP |
40 | /** |
41 | * Interrupts that are always left unmasked. | |
42 | * | |
43 | * Since pipe events are edge-triggered from the PIPESTAT register to IIR, | |
44 | * we leave them always unmasked in IMR and then control enabling them through | |
45 | * PIPESTAT alone. | |
46 | */ | |
6b95a207 KH |
47 | #define I915_INTERRUPT_ENABLE_FIX \ |
48 | (I915_ASLE_INTERRUPT | \ | |
49 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ | |
50 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \ | |
51 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \ | |
52 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \ | |
53 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
7c463586 KP |
54 | |
55 | /** Interrupts that we mask and unmask at runtime. */ | |
d1b851fc | 56 | #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT) |
7c463586 | 57 | |
79e53945 JB |
58 | #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\ |
59 | PIPE_VBLANK_INTERRUPT_STATUS) | |
60 | ||
61 | #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\ | |
62 | PIPE_VBLANK_INTERRUPT_ENABLE) | |
63 | ||
64 | #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \ | |
65 | DRM_I915_VBLANK_PIPE_B) | |
66 | ||
036a4a7d | 67 | /* For display hotplug interrupt */ |
995b6762 | 68 | static void |
f2b115e6 | 69 | ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d | 70 | { |
1ec14ad3 CW |
71 | if ((dev_priv->irq_mask & mask) != 0) { |
72 | dev_priv->irq_mask &= ~mask; | |
73 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 74 | POSTING_READ(DEIMR); |
036a4a7d ZW |
75 | } |
76 | } | |
77 | ||
78 | static inline void | |
f2b115e6 | 79 | ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d | 80 | { |
1ec14ad3 CW |
81 | if ((dev_priv->irq_mask & mask) != mask) { |
82 | dev_priv->irq_mask |= mask; | |
83 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 84 | POSTING_READ(DEIMR); |
036a4a7d ZW |
85 | } |
86 | } | |
87 | ||
7c463586 KP |
88 | void |
89 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
90 | { | |
91 | if ((dev_priv->pipestat[pipe] & mask) != mask) { | |
9db4a9c7 | 92 | u32 reg = PIPESTAT(pipe); |
7c463586 KP |
93 | |
94 | dev_priv->pipestat[pipe] |= mask; | |
95 | /* Enable the interrupt, clear any pending status */ | |
96 | I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); | |
3143a2bf | 97 | POSTING_READ(reg); |
7c463586 KP |
98 | } |
99 | } | |
100 | ||
101 | void | |
102 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
103 | { | |
104 | if ((dev_priv->pipestat[pipe] & mask) != 0) { | |
9db4a9c7 | 105 | u32 reg = PIPESTAT(pipe); |
7c463586 KP |
106 | |
107 | dev_priv->pipestat[pipe] &= ~mask; | |
108 | I915_WRITE(reg, dev_priv->pipestat[pipe]); | |
3143a2bf | 109 | POSTING_READ(reg); |
7c463586 KP |
110 | } |
111 | } | |
112 | ||
01c66889 ZY |
113 | /** |
114 | * intel_enable_asle - enable ASLE interrupt for OpRegion | |
115 | */ | |
1ec14ad3 | 116 | void intel_enable_asle(struct drm_device *dev) |
01c66889 | 117 | { |
1ec14ad3 CW |
118 | drm_i915_private_t *dev_priv = dev->dev_private; |
119 | unsigned long irqflags; | |
120 | ||
121 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
01c66889 | 122 | |
c619eed4 | 123 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 124 | ironlake_enable_display_irq(dev_priv, DE_GSE); |
edcb49ca | 125 | else { |
01c66889 | 126 | i915_enable_pipestat(dev_priv, 1, |
d874bcff | 127 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
a6c45cf0 | 128 | if (INTEL_INFO(dev)->gen >= 4) |
edcb49ca | 129 | i915_enable_pipestat(dev_priv, 0, |
d874bcff | 130 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
edcb49ca | 131 | } |
1ec14ad3 CW |
132 | |
133 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
01c66889 ZY |
134 | } |
135 | ||
0a3e67a4 JB |
136 | /** |
137 | * i915_pipe_enabled - check if a pipe is enabled | |
138 | * @dev: DRM device | |
139 | * @pipe: pipe to check | |
140 | * | |
141 | * Reading certain registers when the pipe is disabled can hang the chip. | |
142 | * Use this routine to make sure the PLL is running and the pipe is active | |
143 | * before reading such registers if unsure. | |
144 | */ | |
145 | static int | |
146 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
147 | { | |
148 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
5eddb70b | 149 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; |
0a3e67a4 JB |
150 | } |
151 | ||
42f52ef8 KP |
152 | /* Called from drm generic code, passed a 'crtc', which |
153 | * we use as a pipe index | |
154 | */ | |
f71d4af4 | 155 | static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
0a3e67a4 JB |
156 | { |
157 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
158 | unsigned long high_frame; | |
159 | unsigned long low_frame; | |
5eddb70b | 160 | u32 high1, high2, low; |
0a3e67a4 JB |
161 | |
162 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 163 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 164 | "pipe %c\n", pipe_name(pipe)); |
0a3e67a4 JB |
165 | return 0; |
166 | } | |
167 | ||
9db4a9c7 JB |
168 | high_frame = PIPEFRAME(pipe); |
169 | low_frame = PIPEFRAMEPIXEL(pipe); | |
5eddb70b | 170 | |
0a3e67a4 JB |
171 | /* |
172 | * High & low register fields aren't synchronized, so make sure | |
173 | * we get a low value that's stable across two reads of the high | |
174 | * register. | |
175 | */ | |
176 | do { | |
5eddb70b CW |
177 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
178 | low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK; | |
179 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; | |
0a3e67a4 JB |
180 | } while (high1 != high2); |
181 | ||
5eddb70b CW |
182 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
183 | low >>= PIPE_FRAME_LOW_SHIFT; | |
184 | return (high1 << 8) | low; | |
0a3e67a4 JB |
185 | } |
186 | ||
f71d4af4 | 187 | static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
9880b7a5 JB |
188 | { |
189 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 190 | int reg = PIPE_FRMCOUNT_GM45(pipe); |
9880b7a5 JB |
191 | |
192 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 193 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 194 | "pipe %c\n", pipe_name(pipe)); |
9880b7a5 JB |
195 | return 0; |
196 | } | |
197 | ||
198 | return I915_READ(reg); | |
199 | } | |
200 | ||
f71d4af4 | 201 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
0af7e4df MK |
202 | int *vpos, int *hpos) |
203 | { | |
204 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
205 | u32 vbl = 0, position = 0; | |
206 | int vbl_start, vbl_end, htotal, vtotal; | |
207 | bool in_vbl = true; | |
208 | int ret = 0; | |
209 | ||
210 | if (!i915_pipe_enabled(dev, pipe)) { | |
211 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " | |
9db4a9c7 | 212 | "pipe %c\n", pipe_name(pipe)); |
0af7e4df MK |
213 | return 0; |
214 | } | |
215 | ||
216 | /* Get vtotal. */ | |
217 | vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff); | |
218 | ||
219 | if (INTEL_INFO(dev)->gen >= 4) { | |
220 | /* No obvious pixelcount register. Only query vertical | |
221 | * scanout position from Display scan line register. | |
222 | */ | |
223 | position = I915_READ(PIPEDSL(pipe)); | |
224 | ||
225 | /* Decode into vertical scanout position. Don't have | |
226 | * horizontal scanout position. | |
227 | */ | |
228 | *vpos = position & 0x1fff; | |
229 | *hpos = 0; | |
230 | } else { | |
231 | /* Have access to pixelcount since start of frame. | |
232 | * We can split this into vertical and horizontal | |
233 | * scanout position. | |
234 | */ | |
235 | position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; | |
236 | ||
237 | htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff); | |
238 | *vpos = position / htotal; | |
239 | *hpos = position - (*vpos * htotal); | |
240 | } | |
241 | ||
242 | /* Query vblank area. */ | |
243 | vbl = I915_READ(VBLANK(pipe)); | |
244 | ||
245 | /* Test position against vblank region. */ | |
246 | vbl_start = vbl & 0x1fff; | |
247 | vbl_end = (vbl >> 16) & 0x1fff; | |
248 | ||
249 | if ((*vpos < vbl_start) || (*vpos > vbl_end)) | |
250 | in_vbl = false; | |
251 | ||
252 | /* Inside "upper part" of vblank area? Apply corrective offset: */ | |
253 | if (in_vbl && (*vpos >= vbl_start)) | |
254 | *vpos = *vpos - vtotal; | |
255 | ||
256 | /* Readouts valid? */ | |
257 | if (vbl > 0) | |
258 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; | |
259 | ||
260 | /* In vblank? */ | |
261 | if (in_vbl) | |
262 | ret |= DRM_SCANOUTPOS_INVBL; | |
263 | ||
264 | return ret; | |
265 | } | |
266 | ||
f71d4af4 | 267 | static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
0af7e4df MK |
268 | int *max_error, |
269 | struct timeval *vblank_time, | |
270 | unsigned flags) | |
271 | { | |
4041b853 CW |
272 | struct drm_i915_private *dev_priv = dev->dev_private; |
273 | struct drm_crtc *crtc; | |
0af7e4df | 274 | |
4041b853 CW |
275 | if (pipe < 0 || pipe >= dev_priv->num_pipe) { |
276 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
0af7e4df MK |
277 | return -EINVAL; |
278 | } | |
279 | ||
280 | /* Get drm_crtc to timestamp: */ | |
4041b853 CW |
281 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
282 | if (crtc == NULL) { | |
283 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
284 | return -EINVAL; | |
285 | } | |
286 | ||
287 | if (!crtc->enabled) { | |
288 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); | |
289 | return -EBUSY; | |
290 | } | |
0af7e4df MK |
291 | |
292 | /* Helper routine in DRM core does all the work: */ | |
4041b853 CW |
293 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
294 | vblank_time, flags, | |
295 | crtc); | |
0af7e4df MK |
296 | } |
297 | ||
5ca58282 JB |
298 | /* |
299 | * Handle hotplug events outside the interrupt handler proper. | |
300 | */ | |
301 | static void i915_hotplug_work_func(struct work_struct *work) | |
302 | { | |
303 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
304 | hotplug_work); | |
305 | struct drm_device *dev = dev_priv->dev; | |
c31c4ba3 | 306 | struct drm_mode_config *mode_config = &dev->mode_config; |
4ef69c7a CW |
307 | struct intel_encoder *encoder; |
308 | ||
a65e34c7 | 309 | mutex_lock(&mode_config->mutex); |
e67189ab JB |
310 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); |
311 | ||
4ef69c7a CW |
312 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) |
313 | if (encoder->hot_plug) | |
314 | encoder->hot_plug(encoder); | |
315 | ||
40ee3381 KP |
316 | mutex_unlock(&mode_config->mutex); |
317 | ||
5ca58282 | 318 | /* Just fire off a uevent and let userspace tell us what to do */ |
eb1f8e4f | 319 | drm_helper_hpd_irq_event(dev); |
5ca58282 JB |
320 | } |
321 | ||
f97108d1 JB |
322 | static void i915_handle_rps_change(struct drm_device *dev) |
323 | { | |
324 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b5b72e89 | 325 | u32 busy_up, busy_down, max_avg, min_avg; |
f97108d1 JB |
326 | u8 new_delay = dev_priv->cur_delay; |
327 | ||
7648fa99 | 328 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
329 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
330 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
331 | max_avg = I915_READ(RCBMAXAVG); |
332 | min_avg = I915_READ(RCBMINAVG); | |
333 | ||
334 | /* Handle RCS change request from hw */ | |
b5b72e89 | 335 | if (busy_up > max_avg) { |
f97108d1 JB |
336 | if (dev_priv->cur_delay != dev_priv->max_delay) |
337 | new_delay = dev_priv->cur_delay - 1; | |
338 | if (new_delay < dev_priv->max_delay) | |
339 | new_delay = dev_priv->max_delay; | |
b5b72e89 | 340 | } else if (busy_down < min_avg) { |
f97108d1 JB |
341 | if (dev_priv->cur_delay != dev_priv->min_delay) |
342 | new_delay = dev_priv->cur_delay + 1; | |
343 | if (new_delay > dev_priv->min_delay) | |
344 | new_delay = dev_priv->min_delay; | |
345 | } | |
346 | ||
7648fa99 JB |
347 | if (ironlake_set_drps(dev, new_delay)) |
348 | dev_priv->cur_delay = new_delay; | |
f97108d1 JB |
349 | |
350 | return; | |
351 | } | |
352 | ||
549f7365 CW |
353 | static void notify_ring(struct drm_device *dev, |
354 | struct intel_ring_buffer *ring) | |
355 | { | |
356 | struct drm_i915_private *dev_priv = dev->dev_private; | |
475553de | 357 | u32 seqno; |
9862e600 | 358 | |
475553de CW |
359 | if (ring->obj == NULL) |
360 | return; | |
361 | ||
362 | seqno = ring->get_seqno(ring); | |
db53a302 | 363 | trace_i915_gem_request_complete(ring, seqno); |
9862e600 CW |
364 | |
365 | ring->irq_seqno = seqno; | |
549f7365 | 366 | wake_up_all(&ring->irq_queue); |
3e0dc6b0 BW |
367 | if (i915_enable_hangcheck) { |
368 | dev_priv->hangcheck_count = 0; | |
369 | mod_timer(&dev_priv->hangcheck_timer, | |
370 | jiffies + | |
371 | msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
372 | } | |
549f7365 CW |
373 | } |
374 | ||
4912d041 | 375 | static void gen6_pm_rps_work(struct work_struct *work) |
3b8d8d91 | 376 | { |
4912d041 BW |
377 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
378 | rps_work); | |
3b8d8d91 | 379 | u8 new_delay = dev_priv->cur_delay; |
4912d041 BW |
380 | u32 pm_iir, pm_imr; |
381 | ||
382 | spin_lock_irq(&dev_priv->rps_lock); | |
383 | pm_iir = dev_priv->pm_iir; | |
384 | dev_priv->pm_iir = 0; | |
385 | pm_imr = I915_READ(GEN6_PMIMR); | |
a9e2641d | 386 | I915_WRITE(GEN6_PMIMR, 0); |
4912d041 | 387 | spin_unlock_irq(&dev_priv->rps_lock); |
3b8d8d91 | 388 | |
3b8d8d91 JB |
389 | if (!pm_iir) |
390 | return; | |
391 | ||
4912d041 | 392 | mutex_lock(&dev_priv->dev->struct_mutex); |
3b8d8d91 JB |
393 | if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { |
394 | if (dev_priv->cur_delay != dev_priv->max_delay) | |
395 | new_delay = dev_priv->cur_delay + 1; | |
396 | if (new_delay > dev_priv->max_delay) | |
397 | new_delay = dev_priv->max_delay; | |
398 | } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) { | |
4912d041 | 399 | gen6_gt_force_wake_get(dev_priv); |
3b8d8d91 JB |
400 | if (dev_priv->cur_delay != dev_priv->min_delay) |
401 | new_delay = dev_priv->cur_delay - 1; | |
402 | if (new_delay < dev_priv->min_delay) { | |
403 | new_delay = dev_priv->min_delay; | |
404 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
405 | I915_READ(GEN6_RP_INTERRUPT_LIMITS) | | |
406 | ((new_delay << 16) & 0x3f0000)); | |
407 | } else { | |
408 | /* Make sure we continue to get down interrupts | |
409 | * until we hit the minimum frequency */ | |
410 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
411 | I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000); | |
412 | } | |
4912d041 | 413 | gen6_gt_force_wake_put(dev_priv); |
3b8d8d91 JB |
414 | } |
415 | ||
4912d041 | 416 | gen6_set_rps(dev_priv->dev, new_delay); |
3b8d8d91 JB |
417 | dev_priv->cur_delay = new_delay; |
418 | ||
4912d041 BW |
419 | /* |
420 | * rps_lock not held here because clearing is non-destructive. There is | |
421 | * an *extremely* unlikely race with gen6_rps_enable() that is prevented | |
422 | * by holding struct_mutex for the duration of the write. | |
423 | */ | |
4912d041 | 424 | mutex_unlock(&dev_priv->dev->struct_mutex); |
3b8d8d91 JB |
425 | } |
426 | ||
776ad806 JB |
427 | static void pch_irq_handler(struct drm_device *dev) |
428 | { | |
429 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
430 | u32 pch_iir; | |
9db4a9c7 | 431 | int pipe; |
776ad806 JB |
432 | |
433 | pch_iir = I915_READ(SDEIIR); | |
434 | ||
435 | if (pch_iir & SDE_AUDIO_POWER_MASK) | |
436 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", | |
437 | (pch_iir & SDE_AUDIO_POWER_MASK) >> | |
438 | SDE_AUDIO_POWER_SHIFT); | |
439 | ||
440 | if (pch_iir & SDE_GMBUS) | |
441 | DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n"); | |
442 | ||
443 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
444 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
445 | ||
446 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
447 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
448 | ||
449 | if (pch_iir & SDE_POISON) | |
450 | DRM_ERROR("PCH poison interrupt\n"); | |
451 | ||
9db4a9c7 JB |
452 | if (pch_iir & SDE_FDI_MASK) |
453 | for_each_pipe(pipe) | |
454 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", | |
455 | pipe_name(pipe), | |
456 | I915_READ(FDI_RX_IIR(pipe))); | |
776ad806 JB |
457 | |
458 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
459 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
460 | ||
461 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
462 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
463 | ||
464 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
465 | DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n"); | |
466 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) | |
467 | DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n"); | |
468 | } | |
469 | ||
f71d4af4 | 470 | static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS) |
b1f14ad0 JB |
471 | { |
472 | struct drm_device *dev = (struct drm_device *) arg; | |
473 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
474 | int ret = IRQ_NONE; | |
475 | u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir; | |
476 | struct drm_i915_master_private *master_priv; | |
477 | ||
478 | atomic_inc(&dev_priv->irq_received); | |
479 | ||
480 | /* disable master interrupt before clearing iir */ | |
481 | de_ier = I915_READ(DEIER); | |
482 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
483 | POSTING_READ(DEIER); | |
484 | ||
485 | de_iir = I915_READ(DEIIR); | |
486 | gt_iir = I915_READ(GTIIR); | |
487 | pch_iir = I915_READ(SDEIIR); | |
488 | pm_iir = I915_READ(GEN6_PMIIR); | |
489 | ||
490 | if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && pm_iir == 0) | |
491 | goto done; | |
492 | ||
493 | ret = IRQ_HANDLED; | |
494 | ||
495 | if (dev->primary->master) { | |
496 | master_priv = dev->primary->master->driver_priv; | |
497 | if (master_priv->sarea_priv) | |
498 | master_priv->sarea_priv->last_dispatch = | |
499 | READ_BREADCRUMB(dev_priv); | |
500 | } | |
501 | ||
502 | if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY)) | |
503 | notify_ring(dev, &dev_priv->ring[RCS]); | |
504 | if (gt_iir & GT_GEN6_BSD_USER_INTERRUPT) | |
505 | notify_ring(dev, &dev_priv->ring[VCS]); | |
506 | if (gt_iir & GT_BLT_USER_INTERRUPT) | |
507 | notify_ring(dev, &dev_priv->ring[BCS]); | |
508 | ||
509 | if (de_iir & DE_GSE_IVB) | |
510 | intel_opregion_gse_intr(dev); | |
511 | ||
512 | if (de_iir & DE_PLANEA_FLIP_DONE_IVB) { | |
513 | intel_prepare_page_flip(dev, 0); | |
514 | intel_finish_page_flip_plane(dev, 0); | |
515 | } | |
516 | ||
517 | if (de_iir & DE_PLANEB_FLIP_DONE_IVB) { | |
518 | intel_prepare_page_flip(dev, 1); | |
519 | intel_finish_page_flip_plane(dev, 1); | |
520 | } | |
521 | ||
522 | if (de_iir & DE_PIPEA_VBLANK_IVB) | |
523 | drm_handle_vblank(dev, 0); | |
524 | ||
f6b07f45 | 525 | if (de_iir & DE_PIPEB_VBLANK_IVB) |
b1f14ad0 JB |
526 | drm_handle_vblank(dev, 1); |
527 | ||
528 | /* check event from PCH */ | |
529 | if (de_iir & DE_PCH_EVENT_IVB) { | |
530 | if (pch_iir & SDE_HOTPLUG_MASK_CPT) | |
531 | queue_work(dev_priv->wq, &dev_priv->hotplug_work); | |
532 | pch_irq_handler(dev); | |
533 | } | |
534 | ||
535 | if (pm_iir & GEN6_PM_DEFERRED_EVENTS) { | |
536 | unsigned long flags; | |
537 | spin_lock_irqsave(&dev_priv->rps_lock, flags); | |
538 | WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n"); | |
b1f14ad0 | 539 | dev_priv->pm_iir |= pm_iir; |
4fb066ab DV |
540 | I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir); |
541 | POSTING_READ(GEN6_PMIMR); | |
b1f14ad0 JB |
542 | spin_unlock_irqrestore(&dev_priv->rps_lock, flags); |
543 | queue_work(dev_priv->wq, &dev_priv->rps_work); | |
544 | } | |
545 | ||
546 | /* should clear PCH hotplug event before clear CPU irq */ | |
547 | I915_WRITE(SDEIIR, pch_iir); | |
548 | I915_WRITE(GTIIR, gt_iir); | |
549 | I915_WRITE(DEIIR, de_iir); | |
550 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
551 | ||
552 | done: | |
553 | I915_WRITE(DEIER, de_ier); | |
554 | POSTING_READ(DEIER); | |
555 | ||
556 | return ret; | |
557 | } | |
558 | ||
f71d4af4 | 559 | static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS) |
036a4a7d | 560 | { |
4697995b | 561 | struct drm_device *dev = (struct drm_device *) arg; |
036a4a7d ZW |
562 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
563 | int ret = IRQ_NONE; | |
3b8d8d91 | 564 | u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir; |
2d7b8366 | 565 | u32 hotplug_mask; |
036a4a7d | 566 | struct drm_i915_master_private *master_priv; |
881f47b6 XH |
567 | u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT; |
568 | ||
4697995b JB |
569 | atomic_inc(&dev_priv->irq_received); |
570 | ||
881f47b6 XH |
571 | if (IS_GEN6(dev)) |
572 | bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT; | |
036a4a7d | 573 | |
2d109a84 ZN |
574 | /* disable master interrupt before clearing iir */ |
575 | de_ier = I915_READ(DEIER); | |
576 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
3143a2bf | 577 | POSTING_READ(DEIER); |
2d109a84 | 578 | |
036a4a7d ZW |
579 | de_iir = I915_READ(DEIIR); |
580 | gt_iir = I915_READ(GTIIR); | |
c650156a | 581 | pch_iir = I915_READ(SDEIIR); |
3b8d8d91 | 582 | pm_iir = I915_READ(GEN6_PMIIR); |
036a4a7d | 583 | |
3b8d8d91 JB |
584 | if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && |
585 | (!IS_GEN6(dev) || pm_iir == 0)) | |
c7c85101 | 586 | goto done; |
036a4a7d | 587 | |
2d7b8366 YL |
588 | if (HAS_PCH_CPT(dev)) |
589 | hotplug_mask = SDE_HOTPLUG_MASK_CPT; | |
590 | else | |
591 | hotplug_mask = SDE_HOTPLUG_MASK; | |
592 | ||
c7c85101 | 593 | ret = IRQ_HANDLED; |
036a4a7d | 594 | |
c7c85101 ZN |
595 | if (dev->primary->master) { |
596 | master_priv = dev->primary->master->driver_priv; | |
597 | if (master_priv->sarea_priv) | |
598 | master_priv->sarea_priv->last_dispatch = | |
599 | READ_BREADCRUMB(dev_priv); | |
600 | } | |
036a4a7d | 601 | |
c6df541c | 602 | if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY)) |
1ec14ad3 | 603 | notify_ring(dev, &dev_priv->ring[RCS]); |
881f47b6 | 604 | if (gt_iir & bsd_usr_interrupt) |
1ec14ad3 CW |
605 | notify_ring(dev, &dev_priv->ring[VCS]); |
606 | if (gt_iir & GT_BLT_USER_INTERRUPT) | |
607 | notify_ring(dev, &dev_priv->ring[BCS]); | |
01c66889 | 608 | |
c7c85101 | 609 | if (de_iir & DE_GSE) |
3b617967 | 610 | intel_opregion_gse_intr(dev); |
c650156a | 611 | |
f072d2e7 | 612 | if (de_iir & DE_PLANEA_FLIP_DONE) { |
013d5aa2 | 613 | intel_prepare_page_flip(dev, 0); |
2bbda389 | 614 | intel_finish_page_flip_plane(dev, 0); |
f072d2e7 | 615 | } |
013d5aa2 | 616 | |
f072d2e7 | 617 | if (de_iir & DE_PLANEB_FLIP_DONE) { |
013d5aa2 | 618 | intel_prepare_page_flip(dev, 1); |
2bbda389 | 619 | intel_finish_page_flip_plane(dev, 1); |
f072d2e7 | 620 | } |
013d5aa2 | 621 | |
f072d2e7 | 622 | if (de_iir & DE_PIPEA_VBLANK) |
c062df61 LP |
623 | drm_handle_vblank(dev, 0); |
624 | ||
f072d2e7 | 625 | if (de_iir & DE_PIPEB_VBLANK) |
c062df61 LP |
626 | drm_handle_vblank(dev, 1); |
627 | ||
c7c85101 | 628 | /* check event from PCH */ |
776ad806 JB |
629 | if (de_iir & DE_PCH_EVENT) { |
630 | if (pch_iir & hotplug_mask) | |
631 | queue_work(dev_priv->wq, &dev_priv->hotplug_work); | |
632 | pch_irq_handler(dev); | |
633 | } | |
036a4a7d | 634 | |
f97108d1 | 635 | if (de_iir & DE_PCU_EVENT) { |
7648fa99 | 636 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
f97108d1 JB |
637 | i915_handle_rps_change(dev); |
638 | } | |
639 | ||
4912d041 BW |
640 | if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS) { |
641 | /* | |
642 | * IIR bits should never already be set because IMR should | |
643 | * prevent an interrupt from being shown in IIR. The warning | |
644 | * displays a case where we've unsafely cleared | |
645 | * dev_priv->pm_iir. Although missing an interrupt of the same | |
646 | * type is not a problem, it displays a problem in the logic. | |
647 | * | |
648 | * The mask bit in IMR is cleared by rps_work. | |
649 | */ | |
650 | unsigned long flags; | |
651 | spin_lock_irqsave(&dev_priv->rps_lock, flags); | |
652 | WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n"); | |
4912d041 | 653 | dev_priv->pm_iir |= pm_iir; |
4fb066ab DV |
654 | I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir); |
655 | POSTING_READ(GEN6_PMIMR); | |
4912d041 BW |
656 | spin_unlock_irqrestore(&dev_priv->rps_lock, flags); |
657 | queue_work(dev_priv->wq, &dev_priv->rps_work); | |
658 | } | |
3b8d8d91 | 659 | |
c7c85101 ZN |
660 | /* should clear PCH hotplug event before clear CPU irq */ |
661 | I915_WRITE(SDEIIR, pch_iir); | |
662 | I915_WRITE(GTIIR, gt_iir); | |
663 | I915_WRITE(DEIIR, de_iir); | |
4912d041 | 664 | I915_WRITE(GEN6_PMIIR, pm_iir); |
c7c85101 ZN |
665 | |
666 | done: | |
2d109a84 | 667 | I915_WRITE(DEIER, de_ier); |
3143a2bf | 668 | POSTING_READ(DEIER); |
2d109a84 | 669 | |
036a4a7d ZW |
670 | return ret; |
671 | } | |
672 | ||
8a905236 JB |
673 | /** |
674 | * i915_error_work_func - do process context error handling work | |
675 | * @work: work struct | |
676 | * | |
677 | * Fire an error uevent so userspace can see that a hang or error | |
678 | * was detected. | |
679 | */ | |
680 | static void i915_error_work_func(struct work_struct *work) | |
681 | { | |
682 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
683 | error_work); | |
684 | struct drm_device *dev = dev_priv->dev; | |
f316a42c BG |
685 | char *error_event[] = { "ERROR=1", NULL }; |
686 | char *reset_event[] = { "RESET=1", NULL }; | |
687 | char *reset_done_event[] = { "ERROR=0", NULL }; | |
8a905236 | 688 | |
f316a42c BG |
689 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); |
690 | ||
ba1234d1 | 691 | if (atomic_read(&dev_priv->mm.wedged)) { |
f803aa55 CW |
692 | DRM_DEBUG_DRIVER("resetting chip\n"); |
693 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); | |
694 | if (!i915_reset(dev, GRDOM_RENDER)) { | |
695 | atomic_set(&dev_priv->mm.wedged, 0); | |
696 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); | |
f316a42c | 697 | } |
30dbf0c0 | 698 | complete_all(&dev_priv->error_completion); |
f316a42c | 699 | } |
8a905236 JB |
700 | } |
701 | ||
3bd3c932 | 702 | #ifdef CONFIG_DEBUG_FS |
9df30794 | 703 | static struct drm_i915_error_object * |
bcfb2e28 | 704 | i915_error_object_create(struct drm_i915_private *dev_priv, |
05394f39 | 705 | struct drm_i915_gem_object *src) |
9df30794 CW |
706 | { |
707 | struct drm_i915_error_object *dst; | |
9df30794 | 708 | int page, page_count; |
e56660dd | 709 | u32 reloc_offset; |
9df30794 | 710 | |
05394f39 | 711 | if (src == NULL || src->pages == NULL) |
9df30794 CW |
712 | return NULL; |
713 | ||
05394f39 | 714 | page_count = src->base.size / PAGE_SIZE; |
9df30794 | 715 | |
0206e353 | 716 | dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC); |
9df30794 CW |
717 | if (dst == NULL) |
718 | return NULL; | |
719 | ||
05394f39 | 720 | reloc_offset = src->gtt_offset; |
9df30794 | 721 | for (page = 0; page < page_count; page++) { |
788885ae | 722 | unsigned long flags; |
e56660dd | 723 | void *d; |
788885ae | 724 | |
e56660dd | 725 | d = kmalloc(PAGE_SIZE, GFP_ATOMIC); |
9df30794 CW |
726 | if (d == NULL) |
727 | goto unwind; | |
e56660dd | 728 | |
788885ae | 729 | local_irq_save(flags); |
172975aa CW |
730 | if (reloc_offset < dev_priv->mm.gtt_mappable_end) { |
731 | void __iomem *s; | |
732 | ||
733 | /* Simply ignore tiling or any overlapping fence. | |
734 | * It's part of the error state, and this hopefully | |
735 | * captures what the GPU read. | |
736 | */ | |
737 | ||
738 | s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, | |
739 | reloc_offset); | |
740 | memcpy_fromio(d, s, PAGE_SIZE); | |
741 | io_mapping_unmap_atomic(s); | |
742 | } else { | |
743 | void *s; | |
744 | ||
745 | drm_clflush_pages(&src->pages[page], 1); | |
746 | ||
747 | s = kmap_atomic(src->pages[page]); | |
748 | memcpy(d, s, PAGE_SIZE); | |
749 | kunmap_atomic(s); | |
750 | ||
751 | drm_clflush_pages(&src->pages[page], 1); | |
752 | } | |
788885ae | 753 | local_irq_restore(flags); |
e56660dd | 754 | |
9df30794 | 755 | dst->pages[page] = d; |
e56660dd CW |
756 | |
757 | reloc_offset += PAGE_SIZE; | |
9df30794 CW |
758 | } |
759 | dst->page_count = page_count; | |
05394f39 | 760 | dst->gtt_offset = src->gtt_offset; |
9df30794 CW |
761 | |
762 | return dst; | |
763 | ||
764 | unwind: | |
765 | while (page--) | |
766 | kfree(dst->pages[page]); | |
767 | kfree(dst); | |
768 | return NULL; | |
769 | } | |
770 | ||
771 | static void | |
772 | i915_error_object_free(struct drm_i915_error_object *obj) | |
773 | { | |
774 | int page; | |
775 | ||
776 | if (obj == NULL) | |
777 | return; | |
778 | ||
779 | for (page = 0; page < obj->page_count; page++) | |
780 | kfree(obj->pages[page]); | |
781 | ||
782 | kfree(obj); | |
783 | } | |
784 | ||
785 | static void | |
786 | i915_error_state_free(struct drm_device *dev, | |
787 | struct drm_i915_error_state *error) | |
788 | { | |
e2f973d5 CW |
789 | int i; |
790 | ||
52d39a21 CW |
791 | for (i = 0; i < ARRAY_SIZE(error->ring); i++) { |
792 | i915_error_object_free(error->ring[i].batchbuffer); | |
793 | i915_error_object_free(error->ring[i].ringbuffer); | |
794 | kfree(error->ring[i].requests); | |
795 | } | |
e2f973d5 | 796 | |
9df30794 | 797 | kfree(error->active_bo); |
6ef3d427 | 798 | kfree(error->overlay); |
9df30794 CW |
799 | kfree(error); |
800 | } | |
801 | ||
c724e8a9 CW |
802 | static u32 capture_bo_list(struct drm_i915_error_buffer *err, |
803 | int count, | |
804 | struct list_head *head) | |
805 | { | |
806 | struct drm_i915_gem_object *obj; | |
807 | int i = 0; | |
808 | ||
809 | list_for_each_entry(obj, head, mm_list) { | |
810 | err->size = obj->base.size; | |
811 | err->name = obj->base.name; | |
812 | err->seqno = obj->last_rendering_seqno; | |
813 | err->gtt_offset = obj->gtt_offset; | |
814 | err->read_domains = obj->base.read_domains; | |
815 | err->write_domain = obj->base.write_domain; | |
816 | err->fence_reg = obj->fence_reg; | |
817 | err->pinned = 0; | |
818 | if (obj->pin_count > 0) | |
819 | err->pinned = 1; | |
820 | if (obj->user_pin_count > 0) | |
821 | err->pinned = -1; | |
822 | err->tiling = obj->tiling_mode; | |
823 | err->dirty = obj->dirty; | |
824 | err->purgeable = obj->madv != I915_MADV_WILLNEED; | |
96154f2f | 825 | err->ring = obj->ring ? obj->ring->id : -1; |
93dfb40c | 826 | err->cache_level = obj->cache_level; |
c724e8a9 CW |
827 | |
828 | if (++i == count) | |
829 | break; | |
830 | ||
831 | err++; | |
832 | } | |
833 | ||
834 | return i; | |
835 | } | |
836 | ||
748ebc60 CW |
837 | static void i915_gem_record_fences(struct drm_device *dev, |
838 | struct drm_i915_error_state *error) | |
839 | { | |
840 | struct drm_i915_private *dev_priv = dev->dev_private; | |
841 | int i; | |
842 | ||
843 | /* Fences */ | |
844 | switch (INTEL_INFO(dev)->gen) { | |
775d17b6 | 845 | case 7: |
748ebc60 CW |
846 | case 6: |
847 | for (i = 0; i < 16; i++) | |
848 | error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); | |
849 | break; | |
850 | case 5: | |
851 | case 4: | |
852 | for (i = 0; i < 16; i++) | |
853 | error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); | |
854 | break; | |
855 | case 3: | |
856 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
857 | for (i = 0; i < 8; i++) | |
858 | error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); | |
859 | case 2: | |
860 | for (i = 0; i < 8; i++) | |
861 | error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); | |
862 | break; | |
863 | ||
864 | } | |
865 | } | |
866 | ||
bcfb2e28 CW |
867 | static struct drm_i915_error_object * |
868 | i915_error_first_batchbuffer(struct drm_i915_private *dev_priv, | |
869 | struct intel_ring_buffer *ring) | |
870 | { | |
871 | struct drm_i915_gem_object *obj; | |
872 | u32 seqno; | |
873 | ||
874 | if (!ring->get_seqno) | |
875 | return NULL; | |
876 | ||
877 | seqno = ring->get_seqno(ring); | |
878 | list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) { | |
879 | if (obj->ring != ring) | |
880 | continue; | |
881 | ||
c37d9a5d | 882 | if (i915_seqno_passed(seqno, obj->last_rendering_seqno)) |
bcfb2e28 CW |
883 | continue; |
884 | ||
885 | if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0) | |
886 | continue; | |
887 | ||
888 | /* We need to copy these to an anonymous buffer as the simplest | |
889 | * method to avoid being overwritten by userspace. | |
890 | */ | |
891 | return i915_error_object_create(dev_priv, obj); | |
892 | } | |
893 | ||
894 | return NULL; | |
895 | } | |
896 | ||
d27b1e0e DV |
897 | static void i915_record_ring_state(struct drm_device *dev, |
898 | struct drm_i915_error_state *error, | |
899 | struct intel_ring_buffer *ring) | |
900 | { | |
901 | struct drm_i915_private *dev_priv = dev->dev_private; | |
902 | ||
33f3f518 | 903 | if (INTEL_INFO(dev)->gen >= 6) { |
c1cd90ed | 904 | error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base)); |
33f3f518 | 905 | error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring)); |
7e3b8737 DV |
906 | error->semaphore_mboxes[ring->id][0] |
907 | = I915_READ(RING_SYNC_0(ring->mmio_base)); | |
908 | error->semaphore_mboxes[ring->id][1] | |
909 | = I915_READ(RING_SYNC_1(ring->mmio_base)); | |
33f3f518 | 910 | } |
c1cd90ed | 911 | |
d27b1e0e DV |
912 | if (INTEL_INFO(dev)->gen >= 4) { |
913 | error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base)); | |
914 | error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base)); | |
915 | error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base)); | |
c1cd90ed | 916 | error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base)); |
d27b1e0e | 917 | if (ring->id == RCS) { |
d27b1e0e DV |
918 | error->instdone1 = I915_READ(INSTDONE1); |
919 | error->bbaddr = I915_READ64(BB_ADDR); | |
920 | } | |
921 | } else { | |
922 | error->ipeir[ring->id] = I915_READ(IPEIR); | |
923 | error->ipehr[ring->id] = I915_READ(IPEHR); | |
924 | error->instdone[ring->id] = I915_READ(INSTDONE); | |
d27b1e0e DV |
925 | } |
926 | ||
c1cd90ed | 927 | error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base)); |
d27b1e0e DV |
928 | error->seqno[ring->id] = ring->get_seqno(ring); |
929 | error->acthd[ring->id] = intel_ring_get_active_head(ring); | |
c1cd90ed DV |
930 | error->head[ring->id] = I915_READ_HEAD(ring); |
931 | error->tail[ring->id] = I915_READ_TAIL(ring); | |
7e3b8737 DV |
932 | |
933 | error->cpu_ring_head[ring->id] = ring->head; | |
934 | error->cpu_ring_tail[ring->id] = ring->tail; | |
d27b1e0e DV |
935 | } |
936 | ||
52d39a21 CW |
937 | static void i915_gem_record_rings(struct drm_device *dev, |
938 | struct drm_i915_error_state *error) | |
939 | { | |
940 | struct drm_i915_private *dev_priv = dev->dev_private; | |
941 | struct drm_i915_gem_request *request; | |
942 | int i, count; | |
943 | ||
944 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
945 | struct intel_ring_buffer *ring = &dev_priv->ring[i]; | |
946 | ||
947 | if (ring->obj == NULL) | |
948 | continue; | |
949 | ||
950 | i915_record_ring_state(dev, error, ring); | |
951 | ||
952 | error->ring[i].batchbuffer = | |
953 | i915_error_first_batchbuffer(dev_priv, ring); | |
954 | ||
955 | error->ring[i].ringbuffer = | |
956 | i915_error_object_create(dev_priv, ring->obj); | |
957 | ||
958 | count = 0; | |
959 | list_for_each_entry(request, &ring->request_list, list) | |
960 | count++; | |
961 | ||
962 | error->ring[i].num_requests = count; | |
963 | error->ring[i].requests = | |
964 | kmalloc(count*sizeof(struct drm_i915_error_request), | |
965 | GFP_ATOMIC); | |
966 | if (error->ring[i].requests == NULL) { | |
967 | error->ring[i].num_requests = 0; | |
968 | continue; | |
969 | } | |
970 | ||
971 | count = 0; | |
972 | list_for_each_entry(request, &ring->request_list, list) { | |
973 | struct drm_i915_error_request *erq; | |
974 | ||
975 | erq = &error->ring[i].requests[count++]; | |
976 | erq->seqno = request->seqno; | |
977 | erq->jiffies = request->emitted_jiffies; | |
978 | } | |
979 | } | |
980 | } | |
981 | ||
8a905236 JB |
982 | /** |
983 | * i915_capture_error_state - capture an error record for later analysis | |
984 | * @dev: drm device | |
985 | * | |
986 | * Should be called when an error is detected (either a hang or an error | |
987 | * interrupt) to capture error state from the time of the error. Fills | |
988 | * out a structure which becomes available in debugfs for user level tools | |
989 | * to pick up. | |
990 | */ | |
63eeaf38 JB |
991 | static void i915_capture_error_state(struct drm_device *dev) |
992 | { | |
993 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 994 | struct drm_i915_gem_object *obj; |
63eeaf38 JB |
995 | struct drm_i915_error_state *error; |
996 | unsigned long flags; | |
9db4a9c7 | 997 | int i, pipe; |
63eeaf38 JB |
998 | |
999 | spin_lock_irqsave(&dev_priv->error_lock, flags); | |
9df30794 CW |
1000 | error = dev_priv->first_error; |
1001 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); | |
1002 | if (error) | |
1003 | return; | |
63eeaf38 | 1004 | |
9db4a9c7 | 1005 | /* Account for pipe specific data like PIPE*STAT */ |
33f3f518 | 1006 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
63eeaf38 | 1007 | if (!error) { |
9df30794 CW |
1008 | DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); |
1009 | return; | |
63eeaf38 JB |
1010 | } |
1011 | ||
b6f7833b CW |
1012 | DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n", |
1013 | dev->primary->index); | |
2fa772f3 | 1014 | |
63eeaf38 JB |
1015 | error->eir = I915_READ(EIR); |
1016 | error->pgtbl_er = I915_READ(PGTBL_ER); | |
9db4a9c7 JB |
1017 | for_each_pipe(pipe) |
1018 | error->pipestat[pipe] = I915_READ(PIPESTAT(pipe)); | |
d27b1e0e | 1019 | |
33f3f518 | 1020 | if (INTEL_INFO(dev)->gen >= 6) { |
f406839f | 1021 | error->error = I915_READ(ERROR_GEN6); |
33f3f518 DV |
1022 | error->done_reg = I915_READ(DONE_REG); |
1023 | } | |
d27b1e0e | 1024 | |
748ebc60 | 1025 | i915_gem_record_fences(dev, error); |
52d39a21 | 1026 | i915_gem_record_rings(dev, error); |
9df30794 | 1027 | |
c724e8a9 | 1028 | /* Record buffers on the active and pinned lists. */ |
9df30794 | 1029 | error->active_bo = NULL; |
c724e8a9 | 1030 | error->pinned_bo = NULL; |
9df30794 | 1031 | |
bcfb2e28 CW |
1032 | i = 0; |
1033 | list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) | |
1034 | i++; | |
1035 | error->active_bo_count = i; | |
05394f39 | 1036 | list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list) |
bcfb2e28 CW |
1037 | i++; |
1038 | error->pinned_bo_count = i - error->active_bo_count; | |
c724e8a9 | 1039 | |
8e934dbf CW |
1040 | error->active_bo = NULL; |
1041 | error->pinned_bo = NULL; | |
bcfb2e28 CW |
1042 | if (i) { |
1043 | error->active_bo = kmalloc(sizeof(*error->active_bo)*i, | |
9df30794 | 1044 | GFP_ATOMIC); |
c724e8a9 CW |
1045 | if (error->active_bo) |
1046 | error->pinned_bo = | |
1047 | error->active_bo + error->active_bo_count; | |
9df30794 CW |
1048 | } |
1049 | ||
c724e8a9 CW |
1050 | if (error->active_bo) |
1051 | error->active_bo_count = | |
1052 | capture_bo_list(error->active_bo, | |
1053 | error->active_bo_count, | |
1054 | &dev_priv->mm.active_list); | |
1055 | ||
1056 | if (error->pinned_bo) | |
1057 | error->pinned_bo_count = | |
1058 | capture_bo_list(error->pinned_bo, | |
1059 | error->pinned_bo_count, | |
1060 | &dev_priv->mm.pinned_list); | |
1061 | ||
9df30794 CW |
1062 | do_gettimeofday(&error->time); |
1063 | ||
6ef3d427 | 1064 | error->overlay = intel_overlay_capture_error_state(dev); |
c4a1d9e4 | 1065 | error->display = intel_display_capture_error_state(dev); |
6ef3d427 | 1066 | |
9df30794 CW |
1067 | spin_lock_irqsave(&dev_priv->error_lock, flags); |
1068 | if (dev_priv->first_error == NULL) { | |
1069 | dev_priv->first_error = error; | |
1070 | error = NULL; | |
1071 | } | |
63eeaf38 | 1072 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); |
9df30794 CW |
1073 | |
1074 | if (error) | |
1075 | i915_error_state_free(dev, error); | |
1076 | } | |
1077 | ||
1078 | void i915_destroy_error_state(struct drm_device *dev) | |
1079 | { | |
1080 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1081 | struct drm_i915_error_state *error; | |
6dc0e816 | 1082 | unsigned long flags; |
9df30794 | 1083 | |
6dc0e816 | 1084 | spin_lock_irqsave(&dev_priv->error_lock, flags); |
9df30794 CW |
1085 | error = dev_priv->first_error; |
1086 | dev_priv->first_error = NULL; | |
6dc0e816 | 1087 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); |
9df30794 CW |
1088 | |
1089 | if (error) | |
1090 | i915_error_state_free(dev, error); | |
63eeaf38 | 1091 | } |
3bd3c932 CW |
1092 | #else |
1093 | #define i915_capture_error_state(x) | |
1094 | #endif | |
63eeaf38 | 1095 | |
35aed2e6 | 1096 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
1097 | { |
1098 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1099 | u32 eir = I915_READ(EIR); | |
9db4a9c7 | 1100 | int pipe; |
8a905236 | 1101 | |
35aed2e6 CW |
1102 | if (!eir) |
1103 | return; | |
8a905236 JB |
1104 | |
1105 | printk(KERN_ERR "render error detected, EIR: 0x%08x\n", | |
1106 | eir); | |
1107 | ||
1108 | if (IS_G4X(dev)) { | |
1109 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
1110 | u32 ipeir = I915_READ(IPEIR_I965); | |
1111 | ||
1112 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
1113 | I915_READ(IPEIR_I965)); | |
1114 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
1115 | I915_READ(IPEHR_I965)); | |
1116 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
1117 | I915_READ(INSTDONE_I965)); | |
1118 | printk(KERN_ERR " INSTPS: 0x%08x\n", | |
1119 | I915_READ(INSTPS)); | |
1120 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", | |
1121 | I915_READ(INSTDONE1)); | |
1122 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
1123 | I915_READ(ACTHD_I965)); | |
1124 | I915_WRITE(IPEIR_I965, ipeir); | |
3143a2bf | 1125 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
1126 | } |
1127 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
1128 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
1129 | printk(KERN_ERR "page table error\n"); | |
1130 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", | |
1131 | pgtbl_err); | |
1132 | I915_WRITE(PGTBL_ER, pgtbl_err); | |
3143a2bf | 1133 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
1134 | } |
1135 | } | |
1136 | ||
a6c45cf0 | 1137 | if (!IS_GEN2(dev)) { |
8a905236 JB |
1138 | if (eir & I915_ERROR_PAGE_TABLE) { |
1139 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
1140 | printk(KERN_ERR "page table error\n"); | |
1141 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", | |
1142 | pgtbl_err); | |
1143 | I915_WRITE(PGTBL_ER, pgtbl_err); | |
3143a2bf | 1144 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
1145 | } |
1146 | } | |
1147 | ||
1148 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
9db4a9c7 JB |
1149 | printk(KERN_ERR "memory refresh error:\n"); |
1150 | for_each_pipe(pipe) | |
1151 | printk(KERN_ERR "pipe %c stat: 0x%08x\n", | |
1152 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); | |
8a905236 JB |
1153 | /* pipestat has already been acked */ |
1154 | } | |
1155 | if (eir & I915_ERROR_INSTRUCTION) { | |
1156 | printk(KERN_ERR "instruction error\n"); | |
1157 | printk(KERN_ERR " INSTPM: 0x%08x\n", | |
1158 | I915_READ(INSTPM)); | |
a6c45cf0 | 1159 | if (INTEL_INFO(dev)->gen < 4) { |
8a905236 JB |
1160 | u32 ipeir = I915_READ(IPEIR); |
1161 | ||
1162 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
1163 | I915_READ(IPEIR)); | |
1164 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
1165 | I915_READ(IPEHR)); | |
1166 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
1167 | I915_READ(INSTDONE)); | |
1168 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
1169 | I915_READ(ACTHD)); | |
1170 | I915_WRITE(IPEIR, ipeir); | |
3143a2bf | 1171 | POSTING_READ(IPEIR); |
8a905236 JB |
1172 | } else { |
1173 | u32 ipeir = I915_READ(IPEIR_I965); | |
1174 | ||
1175 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
1176 | I915_READ(IPEIR_I965)); | |
1177 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
1178 | I915_READ(IPEHR_I965)); | |
1179 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
1180 | I915_READ(INSTDONE_I965)); | |
1181 | printk(KERN_ERR " INSTPS: 0x%08x\n", | |
1182 | I915_READ(INSTPS)); | |
1183 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", | |
1184 | I915_READ(INSTDONE1)); | |
1185 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
1186 | I915_READ(ACTHD_I965)); | |
1187 | I915_WRITE(IPEIR_I965, ipeir); | |
3143a2bf | 1188 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
1189 | } |
1190 | } | |
1191 | ||
1192 | I915_WRITE(EIR, eir); | |
3143a2bf | 1193 | POSTING_READ(EIR); |
8a905236 JB |
1194 | eir = I915_READ(EIR); |
1195 | if (eir) { | |
1196 | /* | |
1197 | * some errors might have become stuck, | |
1198 | * mask them. | |
1199 | */ | |
1200 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
1201 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
1202 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
1203 | } | |
35aed2e6 CW |
1204 | } |
1205 | ||
1206 | /** | |
1207 | * i915_handle_error - handle an error interrupt | |
1208 | * @dev: drm device | |
1209 | * | |
1210 | * Do some basic checking of regsiter state at error interrupt time and | |
1211 | * dump it to the syslog. Also call i915_capture_error_state() to make | |
1212 | * sure we get a record and make it available in debugfs. Fire a uevent | |
1213 | * so userspace knows something bad happened (should trigger collection | |
1214 | * of a ring dump etc.). | |
1215 | */ | |
527f9e90 | 1216 | void i915_handle_error(struct drm_device *dev, bool wedged) |
35aed2e6 CW |
1217 | { |
1218 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1219 | ||
1220 | i915_capture_error_state(dev); | |
1221 | i915_report_and_clear_eir(dev); | |
8a905236 | 1222 | |
ba1234d1 | 1223 | if (wedged) { |
30dbf0c0 | 1224 | INIT_COMPLETION(dev_priv->error_completion); |
ba1234d1 BG |
1225 | atomic_set(&dev_priv->mm.wedged, 1); |
1226 | ||
11ed50ec BG |
1227 | /* |
1228 | * Wakeup waiting processes so they don't hang | |
1229 | */ | |
1ec14ad3 | 1230 | wake_up_all(&dev_priv->ring[RCS].irq_queue); |
f787a5f5 | 1231 | if (HAS_BSD(dev)) |
1ec14ad3 | 1232 | wake_up_all(&dev_priv->ring[VCS].irq_queue); |
549f7365 | 1233 | if (HAS_BLT(dev)) |
1ec14ad3 | 1234 | wake_up_all(&dev_priv->ring[BCS].irq_queue); |
11ed50ec BG |
1235 | } |
1236 | ||
9c9fe1f8 | 1237 | queue_work(dev_priv->wq, &dev_priv->error_work); |
8a905236 JB |
1238 | } |
1239 | ||
4e5359cd SF |
1240 | static void i915_pageflip_stall_check(struct drm_device *dev, int pipe) |
1241 | { | |
1242 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1243 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1244 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 1245 | struct drm_i915_gem_object *obj; |
4e5359cd SF |
1246 | struct intel_unpin_work *work; |
1247 | unsigned long flags; | |
1248 | bool stall_detected; | |
1249 | ||
1250 | /* Ignore early vblank irqs */ | |
1251 | if (intel_crtc == NULL) | |
1252 | return; | |
1253 | ||
1254 | spin_lock_irqsave(&dev->event_lock, flags); | |
1255 | work = intel_crtc->unpin_work; | |
1256 | ||
1257 | if (work == NULL || work->pending || !work->enable_stall_check) { | |
1258 | /* Either the pending flip IRQ arrived, or we're too early. Don't check */ | |
1259 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
1260 | return; | |
1261 | } | |
1262 | ||
1263 | /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ | |
05394f39 | 1264 | obj = work->pending_flip_obj; |
a6c45cf0 | 1265 | if (INTEL_INFO(dev)->gen >= 4) { |
9db4a9c7 | 1266 | int dspsurf = DSPSURF(intel_crtc->plane); |
05394f39 | 1267 | stall_detected = I915_READ(dspsurf) == obj->gtt_offset; |
4e5359cd | 1268 | } else { |
9db4a9c7 | 1269 | int dspaddr = DSPADDR(intel_crtc->plane); |
05394f39 | 1270 | stall_detected = I915_READ(dspaddr) == (obj->gtt_offset + |
01f2c773 | 1271 | crtc->y * crtc->fb->pitches[0] + |
4e5359cd SF |
1272 | crtc->x * crtc->fb->bits_per_pixel/8); |
1273 | } | |
1274 | ||
1275 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
1276 | ||
1277 | if (stall_detected) { | |
1278 | DRM_DEBUG_DRIVER("Pageflip stall detected\n"); | |
1279 | intel_prepare_page_flip(dev, intel_crtc->plane); | |
1280 | } | |
1281 | } | |
1282 | ||
f71d4af4 | 1283 | static irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) |
1da177e4 | 1284 | { |
84b1fd10 | 1285 | struct drm_device *dev = (struct drm_device *) arg; |
1da177e4 | 1286 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 1287 | struct drm_i915_master_private *master_priv; |
cdfbc41f | 1288 | u32 iir, new_iir; |
9db4a9c7 | 1289 | u32 pipe_stats[I915_MAX_PIPES]; |
05eff845 | 1290 | u32 vblank_status; |
0a3e67a4 | 1291 | int vblank = 0; |
7c463586 | 1292 | unsigned long irqflags; |
05eff845 | 1293 | int irq_received; |
9db4a9c7 JB |
1294 | int ret = IRQ_NONE, pipe; |
1295 | bool blc_event = false; | |
6e5fca53 | 1296 | |
630681d9 EA |
1297 | atomic_inc(&dev_priv->irq_received); |
1298 | ||
ed4cb414 | 1299 | iir = I915_READ(IIR); |
a6b54f3f | 1300 | |
a6c45cf0 | 1301 | if (INTEL_INFO(dev)->gen >= 4) |
d874bcff | 1302 | vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS; |
e25e6601 | 1303 | else |
d874bcff | 1304 | vblank_status = PIPE_VBLANK_INTERRUPT_STATUS; |
af6061af | 1305 | |
05eff845 KP |
1306 | for (;;) { |
1307 | irq_received = iir != 0; | |
1308 | ||
1309 | /* Can't rely on pipestat interrupt bit in iir as it might | |
1310 | * have been cleared after the pipestat interrupt was received. | |
1311 | * It doesn't set the bit in iir again, but it still produces | |
1312 | * interrupts (for non-MSI). | |
1313 | */ | |
1ec14ad3 | 1314 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
8a905236 | 1315 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
ba1234d1 | 1316 | i915_handle_error(dev, false); |
8a905236 | 1317 | |
9db4a9c7 JB |
1318 | for_each_pipe(pipe) { |
1319 | int reg = PIPESTAT(pipe); | |
1320 | pipe_stats[pipe] = I915_READ(reg); | |
1321 | ||
1322 | /* | |
1323 | * Clear the PIPE*STAT regs before the IIR | |
1324 | */ | |
1325 | if (pipe_stats[pipe] & 0x8000ffff) { | |
1326 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | |
1327 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | |
1328 | pipe_name(pipe)); | |
1329 | I915_WRITE(reg, pipe_stats[pipe]); | |
1330 | irq_received = 1; | |
1331 | } | |
cdfbc41f | 1332 | } |
1ec14ad3 | 1333 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
05eff845 KP |
1334 | |
1335 | if (!irq_received) | |
1336 | break; | |
1337 | ||
1338 | ret = IRQ_HANDLED; | |
8ee1c3db | 1339 | |
5ca58282 JB |
1340 | /* Consume port. Then clear IIR or we'll miss events */ |
1341 | if ((I915_HAS_HOTPLUG(dev)) && | |
1342 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { | |
1343 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
1344 | ||
44d98a61 | 1345 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
5ca58282 JB |
1346 | hotplug_status); |
1347 | if (hotplug_status & dev_priv->hotplug_supported_mask) | |
9c9fe1f8 EA |
1348 | queue_work(dev_priv->wq, |
1349 | &dev_priv->hotplug_work); | |
5ca58282 JB |
1350 | |
1351 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
1352 | I915_READ(PORT_HOTPLUG_STAT); | |
1353 | } | |
1354 | ||
cdfbc41f EA |
1355 | I915_WRITE(IIR, iir); |
1356 | new_iir = I915_READ(IIR); /* Flush posted writes */ | |
7c463586 | 1357 | |
7c1c2871 DA |
1358 | if (dev->primary->master) { |
1359 | master_priv = dev->primary->master->driver_priv; | |
1360 | if (master_priv->sarea_priv) | |
1361 | master_priv->sarea_priv->last_dispatch = | |
1362 | READ_BREADCRUMB(dev_priv); | |
1363 | } | |
0a3e67a4 | 1364 | |
549f7365 | 1365 | if (iir & I915_USER_INTERRUPT) |
1ec14ad3 CW |
1366 | notify_ring(dev, &dev_priv->ring[RCS]); |
1367 | if (iir & I915_BSD_USER_INTERRUPT) | |
1368 | notify_ring(dev, &dev_priv->ring[VCS]); | |
d1b851fc | 1369 | |
1afe3e9d | 1370 | if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) { |
6b95a207 | 1371 | intel_prepare_page_flip(dev, 0); |
1afe3e9d JB |
1372 | if (dev_priv->flip_pending_is_done) |
1373 | intel_finish_page_flip_plane(dev, 0); | |
1374 | } | |
6b95a207 | 1375 | |
1afe3e9d | 1376 | if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) { |
70565d00 | 1377 | intel_prepare_page_flip(dev, 1); |
1afe3e9d JB |
1378 | if (dev_priv->flip_pending_is_done) |
1379 | intel_finish_page_flip_plane(dev, 1); | |
1afe3e9d | 1380 | } |
6b95a207 | 1381 | |
9db4a9c7 JB |
1382 | for_each_pipe(pipe) { |
1383 | if (pipe_stats[pipe] & vblank_status && | |
1384 | drm_handle_vblank(dev, pipe)) { | |
1385 | vblank++; | |
1386 | if (!dev_priv->flip_pending_is_done) { | |
1387 | i915_pageflip_stall_check(dev, pipe); | |
1388 | intel_finish_page_flip(dev, pipe); | |
1389 | } | |
4e5359cd | 1390 | } |
7c463586 | 1391 | |
9db4a9c7 JB |
1392 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) |
1393 | blc_event = true; | |
cdfbc41f | 1394 | } |
7c463586 | 1395 | |
9db4a9c7 JB |
1396 | |
1397 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | |
3b617967 | 1398 | intel_opregion_asle_intr(dev); |
cdfbc41f EA |
1399 | |
1400 | /* With MSI, interrupts are only generated when iir | |
1401 | * transitions from zero to nonzero. If another bit got | |
1402 | * set while we were handling the existing iir bits, then | |
1403 | * we would never get another interrupt. | |
1404 | * | |
1405 | * This is fine on non-MSI as well, as if we hit this path | |
1406 | * we avoid exiting the interrupt handler only to generate | |
1407 | * another one. | |
1408 | * | |
1409 | * Note that for MSI this could cause a stray interrupt report | |
1410 | * if an interrupt landed in the time between writing IIR and | |
1411 | * the posting read. This should be rare enough to never | |
1412 | * trigger the 99% of 100,000 interrupts test for disabling | |
1413 | * stray interrupts. | |
1414 | */ | |
1415 | iir = new_iir; | |
05eff845 | 1416 | } |
0a3e67a4 | 1417 | |
05eff845 | 1418 | return ret; |
1da177e4 LT |
1419 | } |
1420 | ||
af6061af | 1421 | static int i915_emit_irq(struct drm_device * dev) |
1da177e4 LT |
1422 | { |
1423 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 1424 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 LT |
1425 | |
1426 | i915_kernel_lost_context(dev); | |
1427 | ||
44d98a61 | 1428 | DRM_DEBUG_DRIVER("\n"); |
1da177e4 | 1429 | |
c99b058f | 1430 | dev_priv->counter++; |
c29b669c | 1431 | if (dev_priv->counter > 0x7FFFFFFFUL) |
c99b058f | 1432 | dev_priv->counter = 1; |
7c1c2871 DA |
1433 | if (master_priv->sarea_priv) |
1434 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; | |
c29b669c | 1435 | |
e1f99ce6 CW |
1436 | if (BEGIN_LP_RING(4) == 0) { |
1437 | OUT_RING(MI_STORE_DWORD_INDEX); | |
1438 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1439 | OUT_RING(dev_priv->counter); | |
1440 | OUT_RING(MI_USER_INTERRUPT); | |
1441 | ADVANCE_LP_RING(); | |
1442 | } | |
bc5f4523 | 1443 | |
c29b669c | 1444 | return dev_priv->counter; |
1da177e4 LT |
1445 | } |
1446 | ||
84b1fd10 | 1447 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) |
1da177e4 LT |
1448 | { |
1449 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
7c1c2871 | 1450 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 1451 | int ret = 0; |
1ec14ad3 | 1452 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
1da177e4 | 1453 | |
44d98a61 | 1454 | DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr, |
1da177e4 LT |
1455 | READ_BREADCRUMB(dev_priv)); |
1456 | ||
ed4cb414 | 1457 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { |
7c1c2871 DA |
1458 | if (master_priv->sarea_priv) |
1459 | master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); | |
1da177e4 | 1460 | return 0; |
ed4cb414 | 1461 | } |
1da177e4 | 1462 | |
7c1c2871 DA |
1463 | if (master_priv->sarea_priv) |
1464 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1da177e4 | 1465 | |
b13c2b96 CW |
1466 | if (ring->irq_get(ring)) { |
1467 | DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ, | |
1468 | READ_BREADCRUMB(dev_priv) >= irq_nr); | |
1469 | ring->irq_put(ring); | |
5a9a8d1a CW |
1470 | } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000)) |
1471 | ret = -EBUSY; | |
1da177e4 | 1472 | |
20caafa6 | 1473 | if (ret == -EBUSY) { |
3e684eae | 1474 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", |
1da177e4 LT |
1475 | READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); |
1476 | } | |
1477 | ||
af6061af DA |
1478 | return ret; |
1479 | } | |
1480 | ||
1da177e4 LT |
1481 | /* Needs the lock as it touches the ring. |
1482 | */ | |
c153f45f EA |
1483 | int i915_irq_emit(struct drm_device *dev, void *data, |
1484 | struct drm_file *file_priv) | |
1da177e4 | 1485 | { |
1da177e4 | 1486 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1487 | drm_i915_irq_emit_t *emit = data; |
1da177e4 LT |
1488 | int result; |
1489 | ||
1ec14ad3 | 1490 | if (!dev_priv || !LP_RING(dev_priv)->virtual_start) { |
3e684eae | 1491 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1492 | return -EINVAL; |
1da177e4 | 1493 | } |
299eb93c EA |
1494 | |
1495 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); | |
1496 | ||
546b0974 | 1497 | mutex_lock(&dev->struct_mutex); |
1da177e4 | 1498 | result = i915_emit_irq(dev); |
546b0974 | 1499 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 1500 | |
c153f45f | 1501 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { |
1da177e4 | 1502 | DRM_ERROR("copy_to_user\n"); |
20caafa6 | 1503 | return -EFAULT; |
1da177e4 LT |
1504 | } |
1505 | ||
1506 | return 0; | |
1507 | } | |
1508 | ||
1509 | /* Doesn't need the hardware lock. | |
1510 | */ | |
c153f45f EA |
1511 | int i915_irq_wait(struct drm_device *dev, void *data, |
1512 | struct drm_file *file_priv) | |
1da177e4 | 1513 | { |
1da177e4 | 1514 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1515 | drm_i915_irq_wait_t *irqwait = data; |
1da177e4 LT |
1516 | |
1517 | if (!dev_priv) { | |
3e684eae | 1518 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1519 | return -EINVAL; |
1da177e4 LT |
1520 | } |
1521 | ||
c153f45f | 1522 | return i915_wait_irq(dev, irqwait->irq_seq); |
1da177e4 LT |
1523 | } |
1524 | ||
42f52ef8 KP |
1525 | /* Called from drm generic code, passed 'crtc' which |
1526 | * we use as a pipe index | |
1527 | */ | |
f71d4af4 | 1528 | static int i915_enable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 JB |
1529 | { |
1530 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 1531 | unsigned long irqflags; |
71e0ffa5 | 1532 | |
5eddb70b | 1533 | if (!i915_pipe_enabled(dev, pipe)) |
71e0ffa5 | 1534 | return -EINVAL; |
0a3e67a4 | 1535 | |
1ec14ad3 | 1536 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 1537 | if (INTEL_INFO(dev)->gen >= 4) |
7c463586 KP |
1538 | i915_enable_pipestat(dev_priv, pipe, |
1539 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 1540 | else |
7c463586 KP |
1541 | i915_enable_pipestat(dev_priv, pipe, |
1542 | PIPE_VBLANK_INTERRUPT_ENABLE); | |
8692d00e CW |
1543 | |
1544 | /* maintain vblank delivery even in deep C-states */ | |
1545 | if (dev_priv->info->gen == 3) | |
1546 | I915_WRITE(INSTPM, INSTPM_AGPBUSY_DIS << 16); | |
1ec14ad3 | 1547 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
8692d00e | 1548 | |
0a3e67a4 JB |
1549 | return 0; |
1550 | } | |
1551 | ||
f71d4af4 | 1552 | static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
f796cf8f JB |
1553 | { |
1554 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1555 | unsigned long irqflags; | |
1556 | ||
1557 | if (!i915_pipe_enabled(dev, pipe)) | |
1558 | return -EINVAL; | |
1559 | ||
1560 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
1561 | ironlake_enable_display_irq(dev_priv, (pipe == 0) ? | |
0206e353 | 1562 | DE_PIPEA_VBLANK : DE_PIPEB_VBLANK); |
f796cf8f JB |
1563 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
1564 | ||
1565 | return 0; | |
1566 | } | |
1567 | ||
f71d4af4 | 1568 | static int ivybridge_enable_vblank(struct drm_device *dev, int pipe) |
b1f14ad0 JB |
1569 | { |
1570 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1571 | unsigned long irqflags; | |
1572 | ||
1573 | if (!i915_pipe_enabled(dev, pipe)) | |
1574 | return -EINVAL; | |
1575 | ||
1576 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
1577 | ironlake_enable_display_irq(dev_priv, (pipe == 0) ? | |
1578 | DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB); | |
1579 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
1580 | ||
1581 | return 0; | |
1582 | } | |
1583 | ||
42f52ef8 KP |
1584 | /* Called from drm generic code, passed 'crtc' which |
1585 | * we use as a pipe index | |
1586 | */ | |
f71d4af4 | 1587 | static void i915_disable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 JB |
1588 | { |
1589 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 1590 | unsigned long irqflags; |
0a3e67a4 | 1591 | |
1ec14ad3 | 1592 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
8692d00e CW |
1593 | if (dev_priv->info->gen == 3) |
1594 | I915_WRITE(INSTPM, | |
1595 | INSTPM_AGPBUSY_DIS << 16 | INSTPM_AGPBUSY_DIS); | |
1596 | ||
f796cf8f JB |
1597 | i915_disable_pipestat(dev_priv, pipe, |
1598 | PIPE_VBLANK_INTERRUPT_ENABLE | | |
1599 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
1600 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
1601 | } | |
1602 | ||
f71d4af4 | 1603 | static void ironlake_disable_vblank(struct drm_device *dev, int pipe) |
f796cf8f JB |
1604 | { |
1605 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1606 | unsigned long irqflags; | |
1607 | ||
1608 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
1609 | ironlake_disable_display_irq(dev_priv, (pipe == 0) ? | |
0206e353 | 1610 | DE_PIPEA_VBLANK : DE_PIPEB_VBLANK); |
1ec14ad3 | 1611 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
0a3e67a4 JB |
1612 | } |
1613 | ||
f71d4af4 | 1614 | static void ivybridge_disable_vblank(struct drm_device *dev, int pipe) |
b1f14ad0 JB |
1615 | { |
1616 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1617 | unsigned long irqflags; | |
1618 | ||
1619 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
1620 | ironlake_disable_display_irq(dev_priv, (pipe == 0) ? | |
1621 | DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB); | |
1622 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
1623 | } | |
1624 | ||
702880f2 DA |
1625 | /* Set the vblank monitor pipe |
1626 | */ | |
c153f45f EA |
1627 | int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
1628 | struct drm_file *file_priv) | |
702880f2 | 1629 | { |
702880f2 | 1630 | drm_i915_private_t *dev_priv = dev->dev_private; |
702880f2 DA |
1631 | |
1632 | if (!dev_priv) { | |
3e684eae | 1633 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1634 | return -EINVAL; |
702880f2 DA |
1635 | } |
1636 | ||
5b51694a | 1637 | return 0; |
702880f2 DA |
1638 | } |
1639 | ||
c153f45f EA |
1640 | int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
1641 | struct drm_file *file_priv) | |
702880f2 | 1642 | { |
702880f2 | 1643 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1644 | drm_i915_vblank_pipe_t *pipe = data; |
702880f2 DA |
1645 | |
1646 | if (!dev_priv) { | |
3e684eae | 1647 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1648 | return -EINVAL; |
702880f2 DA |
1649 | } |
1650 | ||
0a3e67a4 | 1651 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
c153f45f | 1652 | |
702880f2 DA |
1653 | return 0; |
1654 | } | |
1655 | ||
a6b54f3f MD |
1656 | /** |
1657 | * Schedule buffer swap at given vertical blank. | |
1658 | */ | |
c153f45f EA |
1659 | int i915_vblank_swap(struct drm_device *dev, void *data, |
1660 | struct drm_file *file_priv) | |
a6b54f3f | 1661 | { |
bd95e0a4 EA |
1662 | /* The delayed swap mechanism was fundamentally racy, and has been |
1663 | * removed. The model was that the client requested a delayed flip/swap | |
1664 | * from the kernel, then waited for vblank before continuing to perform | |
1665 | * rendering. The problem was that the kernel might wake the client | |
1666 | * up before it dispatched the vblank swap (since the lock has to be | |
1667 | * held while touching the ringbuffer), in which case the client would | |
1668 | * clear and start the next frame before the swap occurred, and | |
1669 | * flicker would occur in addition to likely missing the vblank. | |
1670 | * | |
1671 | * In the absence of this ioctl, userland falls back to a correct path | |
1672 | * of waiting for a vblank, then dispatching the swap on its own. | |
1673 | * Context switching to userland and back is plenty fast enough for | |
1674 | * meeting the requirements of vblank swapping. | |
0a3e67a4 | 1675 | */ |
bd95e0a4 | 1676 | return -EINVAL; |
a6b54f3f MD |
1677 | } |
1678 | ||
893eead0 CW |
1679 | static u32 |
1680 | ring_last_seqno(struct intel_ring_buffer *ring) | |
852835f3 | 1681 | { |
893eead0 CW |
1682 | return list_entry(ring->request_list.prev, |
1683 | struct drm_i915_gem_request, list)->seqno; | |
1684 | } | |
1685 | ||
1686 | static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err) | |
1687 | { | |
1688 | if (list_empty(&ring->request_list) || | |
1689 | i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) { | |
1690 | /* Issue a wake-up to catch stuck h/w. */ | |
b2223497 | 1691 | if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) { |
893eead0 CW |
1692 | DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n", |
1693 | ring->name, | |
b2223497 | 1694 | ring->waiting_seqno, |
893eead0 CW |
1695 | ring->get_seqno(ring)); |
1696 | wake_up_all(&ring->irq_queue); | |
1697 | *err = true; | |
1698 | } | |
1699 | return true; | |
1700 | } | |
1701 | return false; | |
f65d9421 BG |
1702 | } |
1703 | ||
1ec14ad3 CW |
1704 | static bool kick_ring(struct intel_ring_buffer *ring) |
1705 | { | |
1706 | struct drm_device *dev = ring->dev; | |
1707 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1708 | u32 tmp = I915_READ_CTL(ring); | |
1709 | if (tmp & RING_WAIT) { | |
1710 | DRM_ERROR("Kicking stuck wait on %s\n", | |
1711 | ring->name); | |
1712 | I915_WRITE_CTL(ring, tmp); | |
1713 | return true; | |
1714 | } | |
1ec14ad3 CW |
1715 | return false; |
1716 | } | |
1717 | ||
f65d9421 BG |
1718 | /** |
1719 | * This is called when the chip hasn't reported back with completed | |
1720 | * batchbuffers in a long time. The first time this is called we simply record | |
1721 | * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses | |
1722 | * again, we assume the chip is wedged and try to fix it. | |
1723 | */ | |
1724 | void i915_hangcheck_elapsed(unsigned long data) | |
1725 | { | |
1726 | struct drm_device *dev = (struct drm_device *)data; | |
1727 | drm_i915_private_t *dev_priv = dev->dev_private; | |
097354eb | 1728 | uint32_t acthd, instdone, instdone1, acthd_bsd, acthd_blt; |
893eead0 CW |
1729 | bool err = false; |
1730 | ||
3e0dc6b0 BW |
1731 | if (!i915_enable_hangcheck) |
1732 | return; | |
1733 | ||
893eead0 | 1734 | /* If all work is done then ACTHD clearly hasn't advanced. */ |
1ec14ad3 CW |
1735 | if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) && |
1736 | i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) && | |
1737 | i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) { | |
893eead0 CW |
1738 | dev_priv->hangcheck_count = 0; |
1739 | if (err) | |
1740 | goto repeat; | |
1741 | return; | |
1742 | } | |
b9201c14 | 1743 | |
a6c45cf0 | 1744 | if (INTEL_INFO(dev)->gen < 4) { |
cbb465e7 CW |
1745 | instdone = I915_READ(INSTDONE); |
1746 | instdone1 = 0; | |
1747 | } else { | |
cbb465e7 CW |
1748 | instdone = I915_READ(INSTDONE_I965); |
1749 | instdone1 = I915_READ(INSTDONE1); | |
1750 | } | |
097354eb DV |
1751 | acthd = intel_ring_get_active_head(&dev_priv->ring[RCS]); |
1752 | acthd_bsd = HAS_BSD(dev) ? | |
1753 | intel_ring_get_active_head(&dev_priv->ring[VCS]) : 0; | |
1754 | acthd_blt = HAS_BLT(dev) ? | |
1755 | intel_ring_get_active_head(&dev_priv->ring[BCS]) : 0; | |
f65d9421 | 1756 | |
cbb465e7 | 1757 | if (dev_priv->last_acthd == acthd && |
097354eb DV |
1758 | dev_priv->last_acthd_bsd == acthd_bsd && |
1759 | dev_priv->last_acthd_blt == acthd_blt && | |
cbb465e7 CW |
1760 | dev_priv->last_instdone == instdone && |
1761 | dev_priv->last_instdone1 == instdone1) { | |
1762 | if (dev_priv->hangcheck_count++ > 1) { | |
1763 | DRM_ERROR("Hangcheck timer elapsed... GPU hung\n"); | |
653d7bed | 1764 | i915_handle_error(dev, true); |
8c80b59b CW |
1765 | |
1766 | if (!IS_GEN2(dev)) { | |
1767 | /* Is the chip hanging on a WAIT_FOR_EVENT? | |
1768 | * If so we can simply poke the RB_WAIT bit | |
1769 | * and break the hang. This should work on | |
1770 | * all but the second generation chipsets. | |
1771 | */ | |
1ec14ad3 CW |
1772 | if (kick_ring(&dev_priv->ring[RCS])) |
1773 | goto repeat; | |
1774 | ||
1775 | if (HAS_BSD(dev) && | |
1776 | kick_ring(&dev_priv->ring[VCS])) | |
1777 | goto repeat; | |
1778 | ||
1779 | if (HAS_BLT(dev) && | |
1780 | kick_ring(&dev_priv->ring[BCS])) | |
893eead0 | 1781 | goto repeat; |
8c80b59b CW |
1782 | } |
1783 | ||
cbb465e7 CW |
1784 | return; |
1785 | } | |
1786 | } else { | |
1787 | dev_priv->hangcheck_count = 0; | |
1788 | ||
1789 | dev_priv->last_acthd = acthd; | |
097354eb DV |
1790 | dev_priv->last_acthd_bsd = acthd_bsd; |
1791 | dev_priv->last_acthd_blt = acthd_blt; | |
cbb465e7 CW |
1792 | dev_priv->last_instdone = instdone; |
1793 | dev_priv->last_instdone1 = instdone1; | |
1794 | } | |
f65d9421 | 1795 | |
893eead0 | 1796 | repeat: |
f65d9421 | 1797 | /* Reset timer case chip hangs without another request being added */ |
b3b079db CW |
1798 | mod_timer(&dev_priv->hangcheck_timer, |
1799 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
f65d9421 BG |
1800 | } |
1801 | ||
1da177e4 LT |
1802 | /* drm_dma.h hooks |
1803 | */ | |
f71d4af4 | 1804 | static void ironlake_irq_preinstall(struct drm_device *dev) |
036a4a7d ZW |
1805 | { |
1806 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1807 | ||
4697995b JB |
1808 | atomic_set(&dev_priv->irq_received, 0); |
1809 | ||
1810 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); | |
1811 | INIT_WORK(&dev_priv->error_work, i915_error_work_func); | |
9e3c256d JB |
1812 | if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
1813 | INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work); | |
4697995b | 1814 | |
036a4a7d | 1815 | I915_WRITE(HWSTAM, 0xeffe); |
bdfcdb63 | 1816 | |
036a4a7d ZW |
1817 | /* XXX hotplug from PCH */ |
1818 | ||
1819 | I915_WRITE(DEIMR, 0xffffffff); | |
1820 | I915_WRITE(DEIER, 0x0); | |
3143a2bf | 1821 | POSTING_READ(DEIER); |
036a4a7d ZW |
1822 | |
1823 | /* and GT */ | |
1824 | I915_WRITE(GTIMR, 0xffffffff); | |
1825 | I915_WRITE(GTIER, 0x0); | |
3143a2bf | 1826 | POSTING_READ(GTIER); |
c650156a ZW |
1827 | |
1828 | /* south display irq */ | |
1829 | I915_WRITE(SDEIMR, 0xffffffff); | |
1830 | I915_WRITE(SDEIER, 0x0); | |
3143a2bf | 1831 | POSTING_READ(SDEIER); |
036a4a7d ZW |
1832 | } |
1833 | ||
7fe0b973 KP |
1834 | /* |
1835 | * Enable digital hotplug on the PCH, and configure the DP short pulse | |
1836 | * duration to 2ms (which is the minimum in the Display Port spec) | |
1837 | * | |
1838 | * This register is the same on all known PCH chips. | |
1839 | */ | |
1840 | ||
1841 | static void ironlake_enable_pch_hotplug(struct drm_device *dev) | |
1842 | { | |
1843 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1844 | u32 hotplug; | |
1845 | ||
1846 | hotplug = I915_READ(PCH_PORT_HOTPLUG); | |
1847 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); | |
1848 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; | |
1849 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; | |
1850 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; | |
1851 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); | |
1852 | } | |
1853 | ||
f71d4af4 | 1854 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d ZW |
1855 | { |
1856 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1857 | /* enable kind of interrupts always enabled */ | |
013d5aa2 JB |
1858 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | |
1859 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; | |
1ec14ad3 | 1860 | u32 render_irqs; |
2d7b8366 | 1861 | u32 hotplug_mask; |
036a4a7d | 1862 | |
4697995b JB |
1863 | DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue); |
1864 | if (HAS_BSD(dev)) | |
1865 | DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue); | |
1866 | if (HAS_BLT(dev)) | |
1867 | DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue); | |
1868 | ||
1869 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; | |
1ec14ad3 | 1870 | dev_priv->irq_mask = ~display_mask; |
036a4a7d ZW |
1871 | |
1872 | /* should always can generate irq */ | |
1873 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1ec14ad3 CW |
1874 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
1875 | I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK); | |
3143a2bf | 1876 | POSTING_READ(DEIER); |
036a4a7d | 1877 | |
1ec14ad3 | 1878 | dev_priv->gt_irq_mask = ~0; |
036a4a7d ZW |
1879 | |
1880 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1ec14ad3 | 1881 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
881f47b6 | 1882 | |
1ec14ad3 CW |
1883 | if (IS_GEN6(dev)) |
1884 | render_irqs = | |
1885 | GT_USER_INTERRUPT | | |
1886 | GT_GEN6_BSD_USER_INTERRUPT | | |
1887 | GT_BLT_USER_INTERRUPT; | |
1888 | else | |
1889 | render_irqs = | |
88f23b8f | 1890 | GT_USER_INTERRUPT | |
c6df541c | 1891 | GT_PIPE_NOTIFY | |
1ec14ad3 CW |
1892 | GT_BSD_USER_INTERRUPT; |
1893 | I915_WRITE(GTIER, render_irqs); | |
3143a2bf | 1894 | POSTING_READ(GTIER); |
036a4a7d | 1895 | |
2d7b8366 | 1896 | if (HAS_PCH_CPT(dev)) { |
9035a97a CW |
1897 | hotplug_mask = (SDE_CRT_HOTPLUG_CPT | |
1898 | SDE_PORTB_HOTPLUG_CPT | | |
1899 | SDE_PORTC_HOTPLUG_CPT | | |
1900 | SDE_PORTD_HOTPLUG_CPT); | |
2d7b8366 | 1901 | } else { |
9035a97a CW |
1902 | hotplug_mask = (SDE_CRT_HOTPLUG | |
1903 | SDE_PORTB_HOTPLUG | | |
1904 | SDE_PORTC_HOTPLUG | | |
1905 | SDE_PORTD_HOTPLUG | | |
1906 | SDE_AUX_MASK); | |
2d7b8366 YL |
1907 | } |
1908 | ||
1ec14ad3 | 1909 | dev_priv->pch_irq_mask = ~hotplug_mask; |
c650156a ZW |
1910 | |
1911 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | |
1ec14ad3 CW |
1912 | I915_WRITE(SDEIMR, dev_priv->pch_irq_mask); |
1913 | I915_WRITE(SDEIER, hotplug_mask); | |
3143a2bf | 1914 | POSTING_READ(SDEIER); |
c650156a | 1915 | |
7fe0b973 KP |
1916 | ironlake_enable_pch_hotplug(dev); |
1917 | ||
f97108d1 JB |
1918 | if (IS_IRONLAKE_M(dev)) { |
1919 | /* Clear & enable PCU event interrupts */ | |
1920 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
1921 | I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT); | |
1922 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); | |
1923 | } | |
1924 | ||
036a4a7d ZW |
1925 | return 0; |
1926 | } | |
1927 | ||
f71d4af4 | 1928 | static int ivybridge_irq_postinstall(struct drm_device *dev) |
b1f14ad0 JB |
1929 | { |
1930 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1931 | /* enable kind of interrupts always enabled */ | |
1932 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | | |
1933 | DE_PCH_EVENT_IVB | DE_PLANEA_FLIP_DONE_IVB | | |
1934 | DE_PLANEB_FLIP_DONE_IVB; | |
1935 | u32 render_irqs; | |
1936 | u32 hotplug_mask; | |
1937 | ||
1938 | DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue); | |
1939 | if (HAS_BSD(dev)) | |
1940 | DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue); | |
1941 | if (HAS_BLT(dev)) | |
1942 | DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue); | |
1943 | ||
1944 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; | |
1945 | dev_priv->irq_mask = ~display_mask; | |
1946 | ||
1947 | /* should always can generate irq */ | |
1948 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1949 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
1950 | I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK_IVB | | |
1951 | DE_PIPEB_VBLANK_IVB); | |
1952 | POSTING_READ(DEIER); | |
1953 | ||
1954 | dev_priv->gt_irq_mask = ~0; | |
1955 | ||
1956 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1957 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
1958 | ||
1959 | render_irqs = GT_USER_INTERRUPT | GT_GEN6_BSD_USER_INTERRUPT | | |
1960 | GT_BLT_USER_INTERRUPT; | |
1961 | I915_WRITE(GTIER, render_irqs); | |
1962 | POSTING_READ(GTIER); | |
1963 | ||
1964 | hotplug_mask = (SDE_CRT_HOTPLUG_CPT | | |
1965 | SDE_PORTB_HOTPLUG_CPT | | |
1966 | SDE_PORTC_HOTPLUG_CPT | | |
1967 | SDE_PORTD_HOTPLUG_CPT); | |
1968 | dev_priv->pch_irq_mask = ~hotplug_mask; | |
1969 | ||
1970 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | |
1971 | I915_WRITE(SDEIMR, dev_priv->pch_irq_mask); | |
1972 | I915_WRITE(SDEIER, hotplug_mask); | |
1973 | POSTING_READ(SDEIER); | |
1974 | ||
7fe0b973 KP |
1975 | ironlake_enable_pch_hotplug(dev); |
1976 | ||
b1f14ad0 JB |
1977 | return 0; |
1978 | } | |
1979 | ||
f71d4af4 | 1980 | static void i915_driver_irq_preinstall(struct drm_device * dev) |
1da177e4 LT |
1981 | { |
1982 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 1983 | int pipe; |
1da177e4 | 1984 | |
79e53945 JB |
1985 | atomic_set(&dev_priv->irq_received, 0); |
1986 | ||
036a4a7d | 1987 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); |
8a905236 | 1988 | INIT_WORK(&dev_priv->error_work, i915_error_work_func); |
036a4a7d | 1989 | |
5ca58282 JB |
1990 | if (I915_HAS_HOTPLUG(dev)) { |
1991 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
1992 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
1993 | } | |
1994 | ||
0a3e67a4 | 1995 | I915_WRITE(HWSTAM, 0xeffe); |
9db4a9c7 JB |
1996 | for_each_pipe(pipe) |
1997 | I915_WRITE(PIPESTAT(pipe), 0); | |
0a3e67a4 | 1998 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 1999 | I915_WRITE(IER, 0x0); |
3143a2bf | 2000 | POSTING_READ(IER); |
1da177e4 LT |
2001 | } |
2002 | ||
b01f2c3a JB |
2003 | /* |
2004 | * Must be called after intel_modeset_init or hotplug interrupts won't be | |
2005 | * enabled correctly. | |
2006 | */ | |
f71d4af4 | 2007 | static int i915_driver_irq_postinstall(struct drm_device *dev) |
1da177e4 LT |
2008 | { |
2009 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
5ca58282 | 2010 | u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR; |
63eeaf38 | 2011 | u32 error_mask; |
0a3e67a4 JB |
2012 | |
2013 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; | |
0a3e67a4 | 2014 | |
7c463586 | 2015 | /* Unmask the interrupts that we always want on. */ |
1ec14ad3 | 2016 | dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX; |
7c463586 KP |
2017 | |
2018 | dev_priv->pipestat[0] = 0; | |
2019 | dev_priv->pipestat[1] = 0; | |
2020 | ||
5ca58282 | 2021 | if (I915_HAS_HOTPLUG(dev)) { |
5ca58282 JB |
2022 | /* Enable in IER... */ |
2023 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
2024 | /* and unmask in IMR */ | |
1ec14ad3 | 2025 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; |
5ca58282 JB |
2026 | } |
2027 | ||
63eeaf38 JB |
2028 | /* |
2029 | * Enable some error detection, note the instruction error mask | |
2030 | * bit is reserved, so we leave it masked. | |
2031 | */ | |
2032 | if (IS_G4X(dev)) { | |
2033 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
2034 | GM45_ERROR_MEM_PRIV | | |
2035 | GM45_ERROR_CP_PRIV | | |
2036 | I915_ERROR_MEMORY_REFRESH); | |
2037 | } else { | |
2038 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
2039 | I915_ERROR_MEMORY_REFRESH); | |
2040 | } | |
2041 | I915_WRITE(EMR, error_mask); | |
2042 | ||
1ec14ad3 | 2043 | I915_WRITE(IMR, dev_priv->irq_mask); |
c496fa1f | 2044 | I915_WRITE(IER, enable_mask); |
3143a2bf | 2045 | POSTING_READ(IER); |
ed4cb414 | 2046 | |
c496fa1f AJ |
2047 | if (I915_HAS_HOTPLUG(dev)) { |
2048 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
2049 | ||
2050 | /* Note HDMI and DP share bits */ | |
2051 | if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) | |
2052 | hotplug_en |= HDMIB_HOTPLUG_INT_EN; | |
2053 | if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) | |
2054 | hotplug_en |= HDMIC_HOTPLUG_INT_EN; | |
2055 | if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) | |
2056 | hotplug_en |= HDMID_HOTPLUG_INT_EN; | |
2057 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS) | |
2058 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; | |
2059 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS) | |
2060 | hotplug_en |= SDVOB_HOTPLUG_INT_EN; | |
2d1c9752 | 2061 | if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { |
c496fa1f | 2062 | hotplug_en |= CRT_HOTPLUG_INT_EN; |
2d1c9752 AL |
2063 | |
2064 | /* Programming the CRT detection parameters tends | |
2065 | to generate a spurious hotplug event about three | |
2066 | seconds later. So just do it once. | |
2067 | */ | |
2068 | if (IS_G4X(dev)) | |
2069 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
2070 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; | |
2071 | } | |
2072 | ||
c496fa1f AJ |
2073 | /* Ignore TV since it's buggy */ |
2074 | ||
2075 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
2076 | } | |
2077 | ||
3b617967 | 2078 | intel_opregion_enable_asle(dev); |
0a3e67a4 JB |
2079 | |
2080 | return 0; | |
1da177e4 LT |
2081 | } |
2082 | ||
f71d4af4 | 2083 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d ZW |
2084 | { |
2085 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
4697995b JB |
2086 | |
2087 | if (!dev_priv) | |
2088 | return; | |
2089 | ||
2090 | dev_priv->vblank_pipe = 0; | |
2091 | ||
036a4a7d ZW |
2092 | I915_WRITE(HWSTAM, 0xffffffff); |
2093 | ||
2094 | I915_WRITE(DEIMR, 0xffffffff); | |
2095 | I915_WRITE(DEIER, 0x0); | |
2096 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
2097 | ||
2098 | I915_WRITE(GTIMR, 0xffffffff); | |
2099 | I915_WRITE(GTIER, 0x0); | |
2100 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
192aac1f KP |
2101 | |
2102 | I915_WRITE(SDEIMR, 0xffffffff); | |
2103 | I915_WRITE(SDEIER, 0x0); | |
2104 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | |
036a4a7d ZW |
2105 | } |
2106 | ||
f71d4af4 | 2107 | static void i915_driver_irq_uninstall(struct drm_device * dev) |
1da177e4 LT |
2108 | { |
2109 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 2110 | int pipe; |
91e3738e | 2111 | |
1da177e4 LT |
2112 | if (!dev_priv) |
2113 | return; | |
2114 | ||
0a3e67a4 JB |
2115 | dev_priv->vblank_pipe = 0; |
2116 | ||
5ca58282 JB |
2117 | if (I915_HAS_HOTPLUG(dev)) { |
2118 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
2119 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
2120 | } | |
2121 | ||
0a3e67a4 | 2122 | I915_WRITE(HWSTAM, 0xffffffff); |
9db4a9c7 JB |
2123 | for_each_pipe(pipe) |
2124 | I915_WRITE(PIPESTAT(pipe), 0); | |
0a3e67a4 | 2125 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 2126 | I915_WRITE(IER, 0x0); |
af6061af | 2127 | |
9db4a9c7 JB |
2128 | for_each_pipe(pipe) |
2129 | I915_WRITE(PIPESTAT(pipe), | |
2130 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); | |
7c463586 | 2131 | I915_WRITE(IIR, I915_READ(IIR)); |
1da177e4 | 2132 | } |
f71d4af4 JB |
2133 | |
2134 | void intel_irq_init(struct drm_device *dev) | |
2135 | { | |
2136 | dev->driver->get_vblank_counter = i915_get_vblank_counter; | |
2137 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
2138 | if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) { | |
2139 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ | |
2140 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; | |
2141 | } | |
2142 | ||
c3613de9 KP |
2143 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
2144 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; | |
2145 | else | |
2146 | dev->driver->get_vblank_timestamp = NULL; | |
f71d4af4 JB |
2147 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; |
2148 | ||
2149 | if (IS_IVYBRIDGE(dev)) { | |
2150 | /* Share pre & uninstall handlers with ILK/SNB */ | |
2151 | dev->driver->irq_handler = ivybridge_irq_handler; | |
2152 | dev->driver->irq_preinstall = ironlake_irq_preinstall; | |
2153 | dev->driver->irq_postinstall = ivybridge_irq_postinstall; | |
2154 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
2155 | dev->driver->enable_vblank = ivybridge_enable_vblank; | |
2156 | dev->driver->disable_vblank = ivybridge_disable_vblank; | |
2157 | } else if (HAS_PCH_SPLIT(dev)) { | |
2158 | dev->driver->irq_handler = ironlake_irq_handler; | |
2159 | dev->driver->irq_preinstall = ironlake_irq_preinstall; | |
2160 | dev->driver->irq_postinstall = ironlake_irq_postinstall; | |
2161 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
2162 | dev->driver->enable_vblank = ironlake_enable_vblank; | |
2163 | dev->driver->disable_vblank = ironlake_disable_vblank; | |
2164 | } else { | |
2165 | dev->driver->irq_preinstall = i915_driver_irq_preinstall; | |
2166 | dev->driver->irq_postinstall = i915_driver_irq_postinstall; | |
2167 | dev->driver->irq_uninstall = i915_driver_irq_uninstall; | |
2168 | dev->driver->irq_handler = i915_driver_irq_handler; | |
2169 | dev->driver->enable_vblank = i915_enable_vblank; | |
2170 | dev->driver->disable_vblank = i915_disable_vblank; | |
2171 | } | |
2172 | } |