]>
Commit | Line | Data |
---|---|---|
0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 LT |
28 | |
29 | #include "drmP.h" | |
30 | #include "drm.h" | |
31 | #include "i915_drm.h" | |
32 | #include "i915_drv.h" | |
33 | ||
1da177e4 | 34 | #define MAX_NOPID ((u32)~0) |
1da177e4 | 35 | |
ed4cb414 EA |
36 | /** These are the interrupts used by the driver */ |
37 | #define I915_INTERRUPT_ENABLE_MASK (I915_USER_INTERRUPT | \ | |
8ee1c3db | 38 | I915_ASLE_INTERRUPT | \ |
0a3e67a4 | 39 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ |
8ee1c3db | 40 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) |
ed4cb414 | 41 | |
8ee1c3db | 42 | void |
ed4cb414 EA |
43 | i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
44 | { | |
45 | if ((dev_priv->irq_mask_reg & mask) != 0) { | |
46 | dev_priv->irq_mask_reg &= ~mask; | |
47 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
48 | (void) I915_READ(IMR); | |
49 | } | |
50 | } | |
51 | ||
52 | static inline void | |
53 | i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) | |
54 | { | |
55 | if ((dev_priv->irq_mask_reg & mask) != mask) { | |
56 | dev_priv->irq_mask_reg |= mask; | |
57 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
58 | (void) I915_READ(IMR); | |
59 | } | |
60 | } | |
61 | ||
0a3e67a4 JB |
62 | /** |
63 | * i915_get_pipe - return the the pipe associated with a given plane | |
64 | * @dev: DRM device | |
65 | * @plane: plane to look for | |
66 | * | |
67 | * The Intel Mesa & 2D drivers call the vblank routines with a plane number | |
68 | * rather than a pipe number, since they may not always be equal. This routine | |
69 | * maps the given @plane back to a pipe number. | |
70 | */ | |
71 | static int | |
72 | i915_get_pipe(struct drm_device *dev, int plane) | |
73 | { | |
74 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
75 | u32 dspcntr; | |
76 | ||
77 | dspcntr = plane ? I915_READ(DSPBCNTR) : I915_READ(DSPACNTR); | |
78 | ||
79 | return dspcntr & DISPPLANE_SEL_PIPE_MASK ? 1 : 0; | |
80 | } | |
81 | ||
82 | /** | |
83 | * i915_get_plane - return the the plane associated with a given pipe | |
84 | * @dev: DRM device | |
85 | * @pipe: pipe to look for | |
86 | * | |
87 | * The Intel Mesa & 2D drivers call the vblank routines with a plane number | |
88 | * rather than a plane number, since they may not always be equal. This routine | |
89 | * maps the given @pipe back to a plane number. | |
90 | */ | |
91 | static int | |
92 | i915_get_plane(struct drm_device *dev, int pipe) | |
93 | { | |
94 | if (i915_get_pipe(dev, 0) == pipe) | |
95 | return 0; | |
96 | return 1; | |
97 | } | |
98 | ||
99 | /** | |
100 | * i915_pipe_enabled - check if a pipe is enabled | |
101 | * @dev: DRM device | |
102 | * @pipe: pipe to check | |
103 | * | |
104 | * Reading certain registers when the pipe is disabled can hang the chip. | |
105 | * Use this routine to make sure the PLL is running and the pipe is active | |
106 | * before reading such registers if unsure. | |
107 | */ | |
108 | static int | |
109 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
110 | { | |
111 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
112 | unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF; | |
113 | ||
114 | if (I915_READ(pipeconf) & PIPEACONF_ENABLE) | |
115 | return 1; | |
116 | ||
117 | return 0; | |
118 | } | |
119 | ||
a6b54f3f MD |
120 | /** |
121 | * Emit blits for scheduled buffer swaps. | |
122 | * | |
123 | * This function will be called with the HW lock held. | |
124 | */ | |
84b1fd10 | 125 | static void i915_vblank_tasklet(struct drm_device *dev) |
a6b54f3f MD |
126 | { |
127 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
af6061af | 128 | unsigned long irqflags; |
3188a24c | 129 | struct list_head *list, *tmp, hits, *hit; |
af6061af | 130 | int nhits, nrects, slice[2], upper[2], lower[2], i; |
0a3e67a4 | 131 | unsigned counter[2]; |
c60ce623 | 132 | struct drm_drawable_info *drw; |
3188a24c | 133 | drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv; |
af6061af | 134 | u32 cpp = dev_priv->cpp; |
3188a24c MD |
135 | u32 cmd = (cpp == 4) ? (XY_SRC_COPY_BLT_CMD | |
136 | XY_SRC_COPY_BLT_WRITE_ALPHA | | |
137 | XY_SRC_COPY_BLT_WRITE_RGB) | |
138 | : XY_SRC_COPY_BLT_CMD; | |
7b832b56 KP |
139 | u32 src_pitch = sarea_priv->pitch * cpp; |
140 | u32 dst_pitch = sarea_priv->pitch * cpp; | |
141 | u32 ropcpp = (0xcc << 16) | ((cpp - 1) << 24); | |
3188a24c | 142 | RING_LOCALS; |
a6b54f3f | 143 | |
3d25802e | 144 | if (IS_I965G(dev) && sarea_priv->front_tiled) { |
7b832b56 KP |
145 | cmd |= XY_SRC_COPY_BLT_DST_TILED; |
146 | dst_pitch >>= 2; | |
147 | } | |
3d25802e | 148 | if (IS_I965G(dev) && sarea_priv->back_tiled) { |
7b832b56 KP |
149 | cmd |= XY_SRC_COPY_BLT_SRC_TILED; |
150 | src_pitch >>= 2; | |
151 | } | |
152 | ||
0a3e67a4 JB |
153 | counter[0] = drm_vblank_count(dev, 0); |
154 | counter[1] = drm_vblank_count(dev, 1); | |
155 | ||
a6b54f3f MD |
156 | DRM_DEBUG("\n"); |
157 | ||
3188a24c MD |
158 | INIT_LIST_HEAD(&hits); |
159 | ||
160 | nhits = nrects = 0; | |
161 | ||
af6061af | 162 | spin_lock_irqsave(&dev_priv->swaps_lock, irqflags); |
a6b54f3f | 163 | |
3188a24c | 164 | /* Find buffer swaps scheduled for this vertical blank */ |
a6b54f3f MD |
165 | list_for_each_safe(list, tmp, &dev_priv->vbl_swaps.head) { |
166 | drm_i915_vbl_swap_t *vbl_swap = | |
167 | list_entry(list, drm_i915_vbl_swap_t, head); | |
0a3e67a4 | 168 | int pipe = i915_get_pipe(dev, vbl_swap->plane); |
a6b54f3f | 169 | |
0a3e67a4 | 170 | if ((counter[pipe] - vbl_swap->sequence) > (1<<23)) |
3188a24c MD |
171 | continue; |
172 | ||
173 | list_del(list); | |
174 | dev_priv->swaps_pending--; | |
0a3e67a4 | 175 | drm_vblank_put(dev, pipe); |
3188a24c MD |
176 | |
177 | spin_unlock(&dev_priv->swaps_lock); | |
178 | spin_lock(&dev->drw_lock); | |
a6b54f3f | 179 | |
3188a24c | 180 | drw = drm_get_drawable_info(dev, vbl_swap->drw_id); |
a6b54f3f | 181 | |
3188a24c MD |
182 | if (!drw) { |
183 | spin_unlock(&dev->drw_lock); | |
184 | drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER); | |
185 | spin_lock(&dev_priv->swaps_lock); | |
186 | continue; | |
187 | } | |
a6b54f3f | 188 | |
3188a24c MD |
189 | list_for_each(hit, &hits) { |
190 | drm_i915_vbl_swap_t *swap_cmp = | |
191 | list_entry(hit, drm_i915_vbl_swap_t, head); | |
c60ce623 | 192 | struct drm_drawable_info *drw_cmp = |
3188a24c | 193 | drm_get_drawable_info(dev, swap_cmp->drw_id); |
a6b54f3f | 194 | |
3188a24c MD |
195 | if (drw_cmp && |
196 | drw_cmp->rects[0].y1 > drw->rects[0].y1) { | |
197 | list_add_tail(list, hit); | |
198 | break; | |
a6b54f3f | 199 | } |
3188a24c | 200 | } |
a6b54f3f | 201 | |
3188a24c | 202 | spin_unlock(&dev->drw_lock); |
a6b54f3f | 203 | |
3188a24c MD |
204 | /* List of hits was empty, or we reached the end of it */ |
205 | if (hit == &hits) | |
206 | list_add_tail(list, hits.prev); | |
a6b54f3f | 207 | |
3188a24c | 208 | nhits++; |
a6b54f3f | 209 | |
3188a24c MD |
210 | spin_lock(&dev_priv->swaps_lock); |
211 | } | |
212 | ||
af6061af DA |
213 | if (nhits == 0) { |
214 | spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags); | |
ac741ab7 | 215 | return; |
af6061af DA |
216 | } |
217 | ||
218 | spin_unlock(&dev_priv->swaps_lock); | |
3188a24c | 219 | |
ac741ab7 | 220 | i915_kernel_lost_context(dev); |
3188a24c | 221 | |
af6061af DA |
222 | if (IS_I965G(dev)) { |
223 | BEGIN_LP_RING(4); | |
224 | ||
225 | OUT_RING(GFX_OP_DRAWRECT_INFO_I965); | |
226 | OUT_RING(0); | |
227 | OUT_RING(((sarea_priv->width - 1) & 0xffff) | ((sarea_priv->height - 1) << 16)); | |
228 | OUT_RING(0); | |
229 | ADVANCE_LP_RING(); | |
230 | } else { | |
231 | BEGIN_LP_RING(6); | |
ac741ab7 | 232 | |
af6061af DA |
233 | OUT_RING(GFX_OP_DRAWRECT_INFO); |
234 | OUT_RING(0); | |
235 | OUT_RING(0); | |
236 | OUT_RING(sarea_priv->width | sarea_priv->height << 16); | |
237 | OUT_RING(sarea_priv->width | sarea_priv->height << 16); | |
238 | OUT_RING(0); | |
239 | ||
240 | ADVANCE_LP_RING(); | |
241 | } | |
242 | ||
243 | sarea_priv->ctxOwner = DRM_KERNEL_CONTEXT; | |
244 | ||
245 | upper[0] = upper[1] = 0; | |
246 | slice[0] = max(sarea_priv->pipeA_h / nhits, 1); | |
247 | slice[1] = max(sarea_priv->pipeB_h / nhits, 1); | |
248 | lower[0] = sarea_priv->pipeA_y + slice[0]; | |
249 | lower[1] = sarea_priv->pipeB_y + slice[0]; | |
3188a24c MD |
250 | |
251 | spin_lock(&dev->drw_lock); | |
252 | ||
253 | /* Emit blits for buffer swaps, partitioning both outputs into as many | |
254 | * slices as there are buffer swaps scheduled in order to avoid tearing | |
255 | * (based on the assumption that a single buffer swap would always | |
256 | * complete before scanout starts). | |
257 | */ | |
258 | for (i = 0; i++ < nhits; | |
259 | upper[0] = lower[0], lower[0] += slice[0], | |
260 | upper[1] = lower[1], lower[1] += slice[1]) { | |
261 | if (i == nhits) | |
262 | lower[0] = lower[1] = sarea_priv->height; | |
263 | ||
264 | list_for_each(hit, &hits) { | |
265 | drm_i915_vbl_swap_t *swap_hit = | |
266 | list_entry(hit, drm_i915_vbl_swap_t, head); | |
c60ce623 | 267 | struct drm_clip_rect *rect; |
0a3e67a4 | 268 | int num_rects, plane; |
3188a24c MD |
269 | unsigned short top, bottom; |
270 | ||
271 | drw = drm_get_drawable_info(dev, swap_hit->drw_id); | |
272 | ||
273 | if (!drw) | |
274 | continue; | |
275 | ||
276 | rect = drw->rects; | |
0a3e67a4 JB |
277 | plane = swap_hit->plane; |
278 | top = upper[plane]; | |
279 | bottom = lower[plane]; | |
3188a24c MD |
280 | |
281 | for (num_rects = drw->num_rects; num_rects--; rect++) { | |
282 | int y1 = max(rect->y1, top); | |
283 | int y2 = min(rect->y2, bottom); | |
284 | ||
285 | if (y1 >= y2) | |
286 | continue; | |
287 | ||
288 | BEGIN_LP_RING(8); | |
289 | ||
290 | OUT_RING(cmd); | |
7b832b56 | 291 | OUT_RING(ropcpp | dst_pitch); |
3188a24c MD |
292 | OUT_RING((y1 << 16) | rect->x1); |
293 | OUT_RING((y2 << 16) | rect->x2); | |
af6061af | 294 | OUT_RING(sarea_priv->front_offset); |
3188a24c | 295 | OUT_RING((y1 << 16) | rect->x1); |
7b832b56 | 296 | OUT_RING(src_pitch); |
af6061af | 297 | OUT_RING(sarea_priv->back_offset); |
3188a24c MD |
298 | |
299 | ADVANCE_LP_RING(); | |
300 | } | |
a6b54f3f MD |
301 | } |
302 | } | |
303 | ||
af6061af | 304 | spin_unlock_irqrestore(&dev->drw_lock, irqflags); |
3188a24c MD |
305 | |
306 | list_for_each_safe(hit, tmp, &hits) { | |
307 | drm_i915_vbl_swap_t *swap_hit = | |
308 | list_entry(hit, drm_i915_vbl_swap_t, head); | |
309 | ||
310 | list_del(hit); | |
311 | ||
312 | drm_free(swap_hit, sizeof(*swap_hit), DRM_MEM_DRIVER); | |
313 | } | |
a6b54f3f MD |
314 | } |
315 | ||
0a3e67a4 JB |
316 | u32 i915_get_vblank_counter(struct drm_device *dev, int plane) |
317 | { | |
318 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
319 | unsigned long high_frame; | |
320 | unsigned long low_frame; | |
321 | u32 high1, high2, low, count; | |
322 | int pipe; | |
323 | ||
324 | pipe = i915_get_pipe(dev, plane); | |
325 | high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH; | |
326 | low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL; | |
327 | ||
328 | if (!i915_pipe_enabled(dev, pipe)) { | |
329 | DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe); | |
330 | return 0; | |
331 | } | |
332 | ||
333 | /* | |
334 | * High & low register fields aren't synchronized, so make sure | |
335 | * we get a low value that's stable across two reads of the high | |
336 | * register. | |
337 | */ | |
338 | do { | |
339 | high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> | |
340 | PIPE_FRAME_HIGH_SHIFT); | |
341 | low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >> | |
342 | PIPE_FRAME_LOW_SHIFT); | |
343 | high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> | |
344 | PIPE_FRAME_HIGH_SHIFT); | |
345 | } while (high1 != high2); | |
346 | ||
347 | count = (high1 << 8) | low; | |
348 | ||
349 | return count; | |
350 | } | |
351 | ||
546b0974 EA |
352 | void |
353 | i915_gem_vblank_work_handler(struct work_struct *work) | |
354 | { | |
355 | drm_i915_private_t *dev_priv; | |
356 | struct drm_device *dev; | |
357 | ||
358 | dev_priv = container_of(work, drm_i915_private_t, | |
359 | mm.vblank_work); | |
360 | dev = dev_priv->dev; | |
361 | ||
362 | mutex_lock(&dev->struct_mutex); | |
363 | i915_vblank_tasklet(dev); | |
364 | mutex_unlock(&dev->struct_mutex); | |
365 | } | |
366 | ||
1da177e4 LT |
367 | irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) |
368 | { | |
84b1fd10 | 369 | struct drm_device *dev = (struct drm_device *) arg; |
1da177e4 | 370 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
ed4cb414 | 371 | u32 iir; |
0a3e67a4 JB |
372 | u32 pipea_stats, pipeb_stats; |
373 | int vblank = 0; | |
6e5fca53 | 374 | |
ed4cb414 EA |
375 | if (dev->pdev->msi_enabled) |
376 | I915_WRITE(IMR, ~0); | |
377 | iir = I915_READ(IIR); | |
a6b54f3f | 378 | |
ed4cb414 EA |
379 | if (iir == 0) { |
380 | if (dev->pdev->msi_enabled) { | |
381 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
382 | (void) I915_READ(IMR); | |
383 | } | |
af6061af | 384 | return IRQ_NONE; |
ed4cb414 | 385 | } |
af6061af | 386 | |
0a3e67a4 JB |
387 | /* |
388 | * Clear the PIPE(A|B)STAT regs before the IIR otherwise | |
389 | * we may get extra interrupts. | |
390 | */ | |
391 | if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) { | |
392 | pipea_stats = I915_READ(PIPEASTAT); | |
393 | if (!(dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_A)) | |
394 | pipea_stats &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE | | |
395 | PIPE_VBLANK_INTERRUPT_ENABLE); | |
396 | else if (pipea_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS| | |
397 | PIPE_VBLANK_INTERRUPT_STATUS)) { | |
398 | vblank++; | |
399 | drm_handle_vblank(dev, i915_get_plane(dev, 0)); | |
400 | } | |
af6061af | 401 | |
0a3e67a4 JB |
402 | I915_WRITE(PIPEASTAT, pipea_stats); |
403 | } | |
404 | if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) { | |
405 | pipeb_stats = I915_READ(PIPEBSTAT); | |
406 | /* Ack the event */ | |
407 | I915_WRITE(PIPEBSTAT, pipeb_stats); | |
408 | ||
409 | /* The vblank interrupt gets enabled even if we didn't ask for | |
410 | it, so make sure it's shut down again */ | |
411 | if (!(dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B)) | |
412 | pipeb_stats &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE | | |
413 | PIPE_VBLANK_INTERRUPT_ENABLE); | |
414 | else if (pipeb_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS| | |
415 | PIPE_VBLANK_INTERRUPT_STATUS)) { | |
416 | vblank++; | |
417 | drm_handle_vblank(dev, i915_get_plane(dev, 1)); | |
418 | } | |
af6061af | 419 | |
0a3e67a4 JB |
420 | if (pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) |
421 | opregion_asle_intr(dev); | |
422 | I915_WRITE(PIPEBSTAT, pipeb_stats); | |
0d6aa60b | 423 | } |
1da177e4 | 424 | |
673a394b EA |
425 | I915_WRITE(IIR, iir); |
426 | if (dev->pdev->msi_enabled) | |
427 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
428 | (void) I915_READ(IIR); /* Flush posted writes */ | |
8ee1c3db | 429 | |
0a3e67a4 JB |
430 | dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
431 | ||
673a394b EA |
432 | if (iir & I915_USER_INTERRUPT) { |
433 | dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev); | |
434 | DRM_WAKEUP(&dev_priv->irq_queue); | |
435 | } | |
436 | ||
437 | if (iir & I915_ASLE_INTERRUPT) | |
438 | opregion_asle_intr(dev); | |
0a3e67a4 | 439 | |
546b0974 EA |
440 | if (vblank && dev_priv->swaps_pending > 0) { |
441 | if (dev_priv->ring.ring_obj == NULL) | |
442 | drm_locked_tasklet(dev, i915_vblank_tasklet); | |
443 | else | |
444 | schedule_work(&dev_priv->mm.vblank_work); | |
445 | } | |
8ee1c3db | 446 | |
1da177e4 LT |
447 | return IRQ_HANDLED; |
448 | } | |
449 | ||
af6061af | 450 | static int i915_emit_irq(struct drm_device * dev) |
1da177e4 LT |
451 | { |
452 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1da177e4 LT |
453 | RING_LOCALS; |
454 | ||
455 | i915_kernel_lost_context(dev); | |
456 | ||
3e684eae | 457 | DRM_DEBUG("\n"); |
1da177e4 | 458 | |
c29b669c | 459 | dev_priv->sarea_priv->last_enqueue = ++dev_priv->counter; |
1da177e4 | 460 | |
c29b669c AH |
461 | if (dev_priv->counter > 0x7FFFFFFFUL) |
462 | dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1; | |
463 | ||
464 | BEGIN_LP_RING(6); | |
585fb111 JB |
465 | OUT_RING(MI_STORE_DWORD_INDEX); |
466 | OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT); | |
c29b669c AH |
467 | OUT_RING(dev_priv->counter); |
468 | OUT_RING(0); | |
1da177e4 | 469 | OUT_RING(0); |
585fb111 | 470 | OUT_RING(MI_USER_INTERRUPT); |
1da177e4 | 471 | ADVANCE_LP_RING(); |
bc5f4523 | 472 | |
c29b669c | 473 | return dev_priv->counter; |
1da177e4 LT |
474 | } |
475 | ||
673a394b | 476 | void i915_user_irq_get(struct drm_device *dev) |
ed4cb414 EA |
477 | { |
478 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
479 | ||
480 | spin_lock(&dev_priv->user_irq_lock); | |
481 | if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) | |
482 | i915_enable_irq(dev_priv, I915_USER_INTERRUPT); | |
483 | spin_unlock(&dev_priv->user_irq_lock); | |
484 | } | |
485 | ||
0a3e67a4 | 486 | void i915_user_irq_put(struct drm_device *dev) |
ed4cb414 EA |
487 | { |
488 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
489 | ||
490 | spin_lock(&dev_priv->user_irq_lock); | |
491 | BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0); | |
492 | if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) | |
493 | i915_disable_irq(dev_priv, I915_USER_INTERRUPT); | |
494 | spin_unlock(&dev_priv->user_irq_lock); | |
495 | } | |
496 | ||
84b1fd10 | 497 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) |
1da177e4 LT |
498 | { |
499 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
500 | int ret = 0; | |
501 | ||
3e684eae | 502 | DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr, |
1da177e4 LT |
503 | READ_BREADCRUMB(dev_priv)); |
504 | ||
ed4cb414 EA |
505 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { |
506 | dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); | |
1da177e4 | 507 | return 0; |
ed4cb414 | 508 | } |
1da177e4 LT |
509 | |
510 | dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
511 | ||
ed4cb414 | 512 | i915_user_irq_get(dev); |
1da177e4 LT |
513 | DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ, |
514 | READ_BREADCRUMB(dev_priv) >= irq_nr); | |
ed4cb414 | 515 | i915_user_irq_put(dev); |
1da177e4 | 516 | |
20caafa6 | 517 | if (ret == -EBUSY) { |
3e684eae | 518 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", |
1da177e4 LT |
519 | READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); |
520 | } | |
521 | ||
af6061af | 522 | dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
af6061af DA |
523 | |
524 | return ret; | |
525 | } | |
526 | ||
1da177e4 LT |
527 | /* Needs the lock as it touches the ring. |
528 | */ | |
c153f45f EA |
529 | int i915_irq_emit(struct drm_device *dev, void *data, |
530 | struct drm_file *file_priv) | |
1da177e4 | 531 | { |
1da177e4 | 532 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 533 | drm_i915_irq_emit_t *emit = data; |
1da177e4 LT |
534 | int result; |
535 | ||
546b0974 | 536 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 LT |
537 | |
538 | if (!dev_priv) { | |
3e684eae | 539 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 540 | return -EINVAL; |
1da177e4 | 541 | } |
546b0974 | 542 | mutex_lock(&dev->struct_mutex); |
1da177e4 | 543 | result = i915_emit_irq(dev); |
546b0974 | 544 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 545 | |
c153f45f | 546 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { |
1da177e4 | 547 | DRM_ERROR("copy_to_user\n"); |
20caafa6 | 548 | return -EFAULT; |
1da177e4 LT |
549 | } |
550 | ||
551 | return 0; | |
552 | } | |
553 | ||
554 | /* Doesn't need the hardware lock. | |
555 | */ | |
c153f45f EA |
556 | int i915_irq_wait(struct drm_device *dev, void *data, |
557 | struct drm_file *file_priv) | |
1da177e4 | 558 | { |
1da177e4 | 559 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 560 | drm_i915_irq_wait_t *irqwait = data; |
1da177e4 LT |
561 | |
562 | if (!dev_priv) { | |
3e684eae | 563 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 564 | return -EINVAL; |
1da177e4 LT |
565 | } |
566 | ||
c153f45f | 567 | return i915_wait_irq(dev, irqwait->irq_seq); |
1da177e4 LT |
568 | } |
569 | ||
0a3e67a4 JB |
570 | int i915_enable_vblank(struct drm_device *dev, int plane) |
571 | { | |
572 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
573 | int pipe = i915_get_pipe(dev, plane); | |
574 | u32 pipestat_reg = 0; | |
575 | u32 pipestat; | |
576 | ||
577 | switch (pipe) { | |
578 | case 0: | |
579 | pipestat_reg = PIPEASTAT; | |
580 | i915_enable_irq(dev_priv, I915_DISPLAY_PIPE_A_EVENT_INTERRUPT); | |
581 | break; | |
582 | case 1: | |
583 | pipestat_reg = PIPEBSTAT; | |
584 | i915_enable_irq(dev_priv, I915_DISPLAY_PIPE_B_EVENT_INTERRUPT); | |
585 | break; | |
586 | default: | |
587 | DRM_ERROR("tried to enable vblank on non-existent pipe %d\n", | |
588 | pipe); | |
589 | break; | |
590 | } | |
591 | ||
592 | if (pipestat_reg) { | |
593 | pipestat = I915_READ(pipestat_reg); | |
594 | if (IS_I965G(dev)) | |
595 | pipestat |= PIPE_START_VBLANK_INTERRUPT_ENABLE; | |
596 | else | |
597 | pipestat |= PIPE_VBLANK_INTERRUPT_ENABLE; | |
598 | /* Clear any stale interrupt status */ | |
599 | pipestat |= (PIPE_START_VBLANK_INTERRUPT_STATUS | | |
600 | PIPE_VBLANK_INTERRUPT_STATUS); | |
601 | I915_WRITE(pipestat_reg, pipestat); | |
602 | } | |
603 | ||
604 | return 0; | |
605 | } | |
606 | ||
607 | void i915_disable_vblank(struct drm_device *dev, int plane) | |
608 | { | |
609 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
610 | int pipe = i915_get_pipe(dev, plane); | |
611 | u32 pipestat_reg = 0; | |
612 | u32 pipestat; | |
613 | ||
614 | switch (pipe) { | |
615 | case 0: | |
616 | pipestat_reg = PIPEASTAT; | |
617 | i915_disable_irq(dev_priv, I915_DISPLAY_PIPE_A_EVENT_INTERRUPT); | |
618 | break; | |
619 | case 1: | |
620 | pipestat_reg = PIPEBSTAT; | |
621 | i915_disable_irq(dev_priv, I915_DISPLAY_PIPE_B_EVENT_INTERRUPT); | |
622 | break; | |
623 | default: | |
624 | DRM_ERROR("tried to disable vblank on non-existent pipe %d\n", | |
625 | pipe); | |
626 | break; | |
627 | } | |
628 | ||
629 | if (pipestat_reg) { | |
630 | pipestat = I915_READ(pipestat_reg); | |
631 | pipestat &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE | | |
632 | PIPE_VBLANK_INTERRUPT_ENABLE); | |
633 | /* Clear any stale interrupt status */ | |
634 | pipestat |= (PIPE_START_VBLANK_INTERRUPT_STATUS | | |
635 | PIPE_VBLANK_INTERRUPT_STATUS); | |
636 | I915_WRITE(pipestat_reg, pipestat); | |
637 | } | |
638 | } | |
639 | ||
702880f2 DA |
640 | /* Set the vblank monitor pipe |
641 | */ | |
c153f45f EA |
642 | int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
643 | struct drm_file *file_priv) | |
702880f2 | 644 | { |
702880f2 | 645 | drm_i915_private_t *dev_priv = dev->dev_private; |
702880f2 DA |
646 | |
647 | if (!dev_priv) { | |
3e684eae | 648 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 649 | return -EINVAL; |
702880f2 DA |
650 | } |
651 | ||
5b51694a | 652 | return 0; |
702880f2 DA |
653 | } |
654 | ||
c153f45f EA |
655 | int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
656 | struct drm_file *file_priv) | |
702880f2 | 657 | { |
702880f2 | 658 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 659 | drm_i915_vblank_pipe_t *pipe = data; |
702880f2 DA |
660 | |
661 | if (!dev_priv) { | |
3e684eae | 662 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 663 | return -EINVAL; |
702880f2 DA |
664 | } |
665 | ||
0a3e67a4 | 666 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
c153f45f | 667 | |
702880f2 DA |
668 | return 0; |
669 | } | |
670 | ||
a6b54f3f MD |
671 | /** |
672 | * Schedule buffer swap at given vertical blank. | |
673 | */ | |
c153f45f EA |
674 | int i915_vblank_swap(struct drm_device *dev, void *data, |
675 | struct drm_file *file_priv) | |
a6b54f3f | 676 | { |
a6b54f3f | 677 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 678 | drm_i915_vblank_swap_t *swap = data; |
a6b54f3f | 679 | drm_i915_vbl_swap_t *vbl_swap; |
0a3e67a4 | 680 | unsigned int pipe, seqtype, curseq, plane; |
a0b136bb | 681 | unsigned long irqflags; |
a6b54f3f | 682 | struct list_head *list; |
0a3e67a4 | 683 | int ret; |
a6b54f3f MD |
684 | |
685 | if (!dev_priv) { | |
686 | DRM_ERROR("%s called with no initialization\n", __func__); | |
20caafa6 | 687 | return -EINVAL; |
a6b54f3f MD |
688 | } |
689 | ||
af6061af | 690 | if (dev_priv->sarea_priv->rotation) { |
a6b54f3f | 691 | DRM_DEBUG("Rotation not supported\n"); |
20caafa6 | 692 | return -EINVAL; |
a6b54f3f MD |
693 | } |
694 | ||
c153f45f | 695 | if (swap->seqtype & ~(_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE | |
af6061af | 696 | _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)) { |
c153f45f | 697 | DRM_ERROR("Invalid sequence type 0x%x\n", swap->seqtype); |
20caafa6 | 698 | return -EINVAL; |
541f29aa MD |
699 | } |
700 | ||
0a3e67a4 JB |
701 | plane = (swap->seqtype & _DRM_VBLANK_SECONDARY) ? 1 : 0; |
702 | pipe = i915_get_pipe(dev, plane); | |
541f29aa | 703 | |
c153f45f | 704 | seqtype = swap->seqtype & (_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE); |
541f29aa | 705 | |
541f29aa MD |
706 | if (!(dev_priv->vblank_pipe & (1 << pipe))) { |
707 | DRM_ERROR("Invalid pipe %d\n", pipe); | |
20caafa6 | 708 | return -EINVAL; |
a6b54f3f MD |
709 | } |
710 | ||
711 | spin_lock_irqsave(&dev->drw_lock, irqflags); | |
712 | ||
c153f45f | 713 | if (!drm_get_drawable_info(dev, swap->drawable)) { |
a6b54f3f | 714 | spin_unlock_irqrestore(&dev->drw_lock, irqflags); |
c153f45f | 715 | DRM_DEBUG("Invalid drawable ID %d\n", swap->drawable); |
20caafa6 | 716 | return -EINVAL; |
a6b54f3f MD |
717 | } |
718 | ||
719 | spin_unlock_irqrestore(&dev->drw_lock, irqflags); | |
720 | ||
0a3e67a4 JB |
721 | /* |
722 | * We take the ref here and put it when the swap actually completes | |
723 | * in the tasklet. | |
724 | */ | |
725 | ret = drm_vblank_get(dev, pipe); | |
726 | if (ret) | |
727 | return ret; | |
728 | curseq = drm_vblank_count(dev, pipe); | |
541f29aa | 729 | |
2228ed67 | 730 | if (seqtype == _DRM_VBLANK_RELATIVE) |
c153f45f | 731 | swap->sequence += curseq; |
2228ed67 | 732 | |
c153f45f EA |
733 | if ((curseq - swap->sequence) <= (1<<23)) { |
734 | if (swap->seqtype & _DRM_VBLANK_NEXTONMISS) { | |
735 | swap->sequence = curseq + 1; | |
2228ed67 | 736 | } else { |
541f29aa | 737 | DRM_DEBUG("Missed target sequence\n"); |
0a3e67a4 | 738 | drm_vblank_put(dev, pipe); |
20caafa6 | 739 | return -EINVAL; |
541f29aa | 740 | } |
541f29aa MD |
741 | } |
742 | ||
2228ed67 MD |
743 | spin_lock_irqsave(&dev_priv->swaps_lock, irqflags); |
744 | ||
a6b54f3f MD |
745 | list_for_each(list, &dev_priv->vbl_swaps.head) { |
746 | vbl_swap = list_entry(list, drm_i915_vbl_swap_t, head); | |
747 | ||
c153f45f | 748 | if (vbl_swap->drw_id == swap->drawable && |
0a3e67a4 | 749 | vbl_swap->plane == plane && |
c153f45f | 750 | vbl_swap->sequence == swap->sequence) { |
a6b54f3f MD |
751 | spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags); |
752 | DRM_DEBUG("Already scheduled\n"); | |
753 | return 0; | |
754 | } | |
755 | } | |
756 | ||
757 | spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags); | |
758 | ||
21fa60ed MD |
759 | if (dev_priv->swaps_pending >= 100) { |
760 | DRM_DEBUG("Too many swaps queued\n"); | |
0a3e67a4 | 761 | drm_vblank_put(dev, pipe); |
20caafa6 | 762 | return -EBUSY; |
21fa60ed MD |
763 | } |
764 | ||
54583bf4 | 765 | vbl_swap = drm_calloc(1, sizeof(*vbl_swap), DRM_MEM_DRIVER); |
a6b54f3f MD |
766 | |
767 | if (!vbl_swap) { | |
768 | DRM_ERROR("Failed to allocate memory to queue swap\n"); | |
0a3e67a4 | 769 | drm_vblank_put(dev, pipe); |
20caafa6 | 770 | return -ENOMEM; |
a6b54f3f MD |
771 | } |
772 | ||
773 | DRM_DEBUG("\n"); | |
774 | ||
c153f45f | 775 | vbl_swap->drw_id = swap->drawable; |
0a3e67a4 | 776 | vbl_swap->plane = plane; |
c153f45f | 777 | vbl_swap->sequence = swap->sequence; |
a6b54f3f MD |
778 | |
779 | spin_lock_irqsave(&dev_priv->swaps_lock, irqflags); | |
780 | ||
d5b0d1b5 | 781 | list_add_tail(&vbl_swap->head, &dev_priv->vbl_swaps.head); |
a6b54f3f MD |
782 | dev_priv->swaps_pending++; |
783 | ||
784 | spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags); | |
785 | ||
786 | return 0; | |
787 | } | |
788 | ||
1da177e4 LT |
789 | /* drm_dma.h hooks |
790 | */ | |
84b1fd10 | 791 | void i915_driver_irq_preinstall(struct drm_device * dev) |
1da177e4 LT |
792 | { |
793 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
794 | ||
0a3e67a4 JB |
795 | I915_WRITE(HWSTAM, 0xeffe); |
796 | I915_WRITE(IMR, 0xffffffff); | |
ed4cb414 | 797 | I915_WRITE(IER, 0x0); |
1da177e4 LT |
798 | } |
799 | ||
0a3e67a4 | 800 | int i915_driver_irq_postinstall(struct drm_device *dev) |
1da177e4 LT |
801 | { |
802 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
0a3e67a4 | 803 | int ret, num_pipes = 2; |
1da177e4 | 804 | |
a6399bdd | 805 | spin_lock_init(&dev_priv->swaps_lock); |
a6b54f3f MD |
806 | INIT_LIST_HEAD(&dev_priv->vbl_swaps.head); |
807 | dev_priv->swaps_pending = 0; | |
808 | ||
ed4cb414 EA |
809 | /* Set initial unmasked IRQs to just the selected vblank pipes. */ |
810 | dev_priv->irq_mask_reg = ~0; | |
0a3e67a4 JB |
811 | |
812 | ret = drm_vblank_init(dev, num_pipes); | |
813 | if (ret) | |
814 | return ret; | |
815 | ||
816 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; | |
817 | dev_priv->irq_mask_reg &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; | |
818 | dev_priv->irq_mask_reg &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; | |
819 | ||
820 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
ed4cb414 | 821 | |
8ee1c3db MG |
822 | dev_priv->irq_mask_reg &= I915_INTERRUPT_ENABLE_MASK; |
823 | ||
ed4cb414 EA |
824 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
825 | I915_WRITE(IER, I915_INTERRUPT_ENABLE_MASK); | |
826 | (void) I915_READ(IER); | |
827 | ||
8ee1c3db | 828 | opregion_enable_asle(dev); |
1da177e4 | 829 | DRM_INIT_WAITQUEUE(&dev_priv->irq_queue); |
0a3e67a4 JB |
830 | |
831 | return 0; | |
1da177e4 LT |
832 | } |
833 | ||
84b1fd10 | 834 | void i915_driver_irq_uninstall(struct drm_device * dev) |
1da177e4 LT |
835 | { |
836 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
0a3e67a4 | 837 | u32 temp; |
91e3738e | 838 | |
1da177e4 LT |
839 | if (!dev_priv) |
840 | return; | |
841 | ||
0a3e67a4 JB |
842 | dev_priv->vblank_pipe = 0; |
843 | ||
844 | I915_WRITE(HWSTAM, 0xffffffff); | |
845 | I915_WRITE(IMR, 0xffffffff); | |
ed4cb414 | 846 | I915_WRITE(IER, 0x0); |
af6061af | 847 | |
0a3e67a4 JB |
848 | temp = I915_READ(PIPEASTAT); |
849 | I915_WRITE(PIPEASTAT, temp); | |
850 | temp = I915_READ(PIPEBSTAT); | |
851 | I915_WRITE(PIPEBSTAT, temp); | |
ed4cb414 EA |
852 | temp = I915_READ(IIR); |
853 | I915_WRITE(IIR, temp); | |
1da177e4 | 854 | } |