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drm/i915: enable semaphores on gen6 if dmar is not active
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
1da177e4
LT		 33#include "drmP.h"
34#include "drm.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
1c5d22f7 37#include "i915_trace.h"
79e53945 38#include "intel_drv.h"
1da177e4 39
036a4a7d 40/* For display hotplug interrupt */
995b6762 41static void
f2b115e6 42ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 43{
1ec14ad3
CW		 44 if ((dev_priv->irq_mask & mask) != 0) {
45 dev_priv->irq_mask &= ~mask;
46 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 47 POSTING_READ(DEIMR);
036a4a7d
ZW		 48 }
49}
50
51static inline void
f2b115e6 52ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 53{
1ec14ad3
CW		 54 if ((dev_priv->irq_mask & mask) != mask) {
55 dev_priv->irq_mask |= mask;
56 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 57 POSTING_READ(DEIMR);
036a4a7d
ZW		 58 }
59}
60
7c463586
KP		 61void
62i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
63{
64 if ((dev_priv->pipestat[pipe] & mask) != mask) {
9db4a9c7 65 u32 reg = PIPESTAT(pipe);
7c463586
KP		 66
67 dev_priv->pipestat[pipe] |= mask;
68 /* Enable the interrupt, clear any pending status */
69 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
3143a2bf 70 POSTING_READ(reg);
7c463586
KP		 71 }
72}
73
74void
75i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
76{
77 if ((dev_priv->pipestat[pipe] & mask) != 0) {
9db4a9c7 78 u32 reg = PIPESTAT(pipe);
7c463586
KP		 79
80 dev_priv->pipestat[pipe] &= ~mask;
81 I915_WRITE(reg, dev_priv->pipestat[pipe]);
3143a2bf 82 POSTING_READ(reg);
7c463586
KP		 83 }
84}
85
01c66889
ZY		 86/**
87 * intel_enable_asle - enable ASLE interrupt for OpRegion
88 */
1ec14ad3 89void intel_enable_asle(struct drm_device *dev)
01c66889 90{
1ec14ad3
CW		 91 drm_i915_private_t *dev_priv = dev->dev_private;
92 unsigned long irqflags;
93
7e231dbe
JB		 94 /* FIXME: opregion/asle for VLV */
95 if (IS_VALLEYVIEW(dev))
96 return;
97
1ec14ad3 98 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 99
c619eed4 100 if (HAS_PCH_SPLIT(dev))
f2b115e6 101 ironlake_enable_display_irq(dev_priv, DE_GSE);
edcb49ca 102 else {
01c66889 103 i915_enable_pipestat(dev_priv, 1,
d874bcff 104 PIPE_LEGACY_BLC_EVENT_ENABLE);
a6c45cf0 105 if (INTEL_INFO(dev)->gen >= 4)
edcb49ca 106 i915_enable_pipestat(dev_priv, 0,
d874bcff 107 PIPE_LEGACY_BLC_EVENT_ENABLE);
edcb49ca 108 }
1ec14ad3
CW		 109
110 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 111}
112
0a3e67a4
JB		 113/**
114 * i915_pipe_enabled - check if a pipe is enabled
115 * @dev: DRM device
116 * @pipe: pipe to check
117 *
118 * Reading certain registers when the pipe is disabled can hang the chip.
119 * Use this routine to make sure the PLL is running and the pipe is active
120 * before reading such registers if unsure.
121 */
122static int
123i915_pipe_enabled(struct drm_device *dev, int pipe)
124{
125 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
5eddb70b 126 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
0a3e67a4
JB		 127}
128
42f52ef8
KP		 129/* Called from drm generic code, passed a 'crtc', which
130 * we use as a pipe index
131 */
f71d4af4 132static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 133{
134 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
135 unsigned long high_frame;
136 unsigned long low_frame;
5eddb70b 137 u32 high1, high2, low;
0a3e67a4
JB		 138
139 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 140 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 141 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 142 return 0;
143 }
144
9db4a9c7
JB		 145 high_frame = PIPEFRAME(pipe);
146 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 147
0a3e67a4
JB		 148 /*
149 * High & low register fields aren't synchronized, so make sure
150 * we get a low value that's stable across two reads of the high
151 * register.
152 */
153 do {
5eddb70b
CW		 154 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
155 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
156 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 157 } while (high1 != high2);
158
5eddb70b
CW		 159 high1 >>= PIPE_FRAME_HIGH_SHIFT;
160 low >>= PIPE_FRAME_LOW_SHIFT;
161 return (high1 << 8) | low;
0a3e67a4
JB		 162}
163
f71d4af4 164static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 165{
166 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 167 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 168
169 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 170 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 171 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 172 return 0;
173 }
174
175 return I915_READ(reg);
176}
177
f71d4af4 178static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 179 int *vpos, int *hpos)
180{
181 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
182 u32 vbl = 0, position = 0;
183 int vbl_start, vbl_end, htotal, vtotal;
184 bool in_vbl = true;
185 int ret = 0;
186
187 if (!i915_pipe_enabled(dev, pipe)) {
188 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 189 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 190 return 0;
191 }
192
193 /* Get vtotal. */
194 vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
195
196 if (INTEL_INFO(dev)->gen >= 4) {
197 /* No obvious pixelcount register. Only query vertical
198 * scanout position from Display scan line register.
199 */
200 position = I915_READ(PIPEDSL(pipe));
201
202 /* Decode into vertical scanout position. Don't have
203 * horizontal scanout position.
204 */
205 *vpos = position & 0x1fff;
206 *hpos = 0;
207 } else {
208 /* Have access to pixelcount since start of frame.
209 * We can split this into vertical and horizontal
210 * scanout position.
211 */
212 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
213
214 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
215 *vpos = position / htotal;
216 *hpos = position - (*vpos * htotal);
217 }
218
219 /* Query vblank area. */
220 vbl = I915_READ(VBLANK(pipe));
221
222 /* Test position against vblank region. */
223 vbl_start = vbl & 0x1fff;
224 vbl_end = (vbl >> 16) & 0x1fff;
225
226 if ((*vpos < vbl_start) || (*vpos > vbl_end))
227 in_vbl = false;
228
229 /* Inside "upper part" of vblank area? Apply corrective offset: */
230 if (in_vbl && (*vpos >= vbl_start))
231 *vpos = *vpos - vtotal;
232
233 /* Readouts valid? */
234 if (vbl > 0)
235 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
236
237 /* In vblank? */
238 if (in_vbl)
239 ret |= DRM_SCANOUTPOS_INVBL;
240
241 return ret;
242}
243
f71d4af4 244static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 245 int *max_error,
246 struct timeval *vblank_time,
247 unsigned flags)
248{
4041b853
CW		 249 struct drm_i915_private *dev_priv = dev->dev_private;
250 struct drm_crtc *crtc;
0af7e4df 251
4041b853
CW		 252 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
253 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 254 return -EINVAL;
255 }
256
257 /* Get drm_crtc to timestamp: */
4041b853
CW		 258 crtc = intel_get_crtc_for_pipe(dev, pipe);
259 if (crtc == NULL) {
260 DRM_ERROR("Invalid crtc %d\n", pipe);
261 return -EINVAL;
262 }
263
264 if (!crtc->enabled) {
265 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
266 return -EBUSY;
267 }
0af7e4df
MK		 268
269 /* Helper routine in DRM core does all the work: */
4041b853
CW		 270 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
271 vblank_time, flags,
272 crtc);
0af7e4df
MK		 273}
274
5ca58282
JB		 275/*
276 * Handle hotplug events outside the interrupt handler proper.
277 */
278static void i915_hotplug_work_func(struct work_struct *work)
279{
280 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
281 hotplug_work);
282 struct drm_device *dev = dev_priv->dev;
c31c4ba3 283 struct drm_mode_config *mode_config = &dev->mode_config;
4ef69c7a
CW		 284 struct intel_encoder *encoder;
285
a65e34c7 286 mutex_lock(&mode_config->mutex);
e67189ab
JB		 287 DRM_DEBUG_KMS("running encoder hotplug functions\n");
288
4ef69c7a
CW		 289 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
290 if (encoder->hot_plug)
291 encoder->hot_plug(encoder);
292
40ee3381
KP		 293 mutex_unlock(&mode_config->mutex);
294
5ca58282 295 /* Just fire off a uevent and let userspace tell us what to do */
eb1f8e4f 296 drm_helper_hpd_irq_event(dev);
5ca58282
JB		 297}
298
f97108d1
JB		 299static void i915_handle_rps_change(struct drm_device *dev)
300{
301 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 302 u32 busy_up, busy_down, max_avg, min_avg;
f97108d1
JB		 303 u8 new_delay = dev_priv->cur_delay;
304
7648fa99 305 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 306 busy_up = I915_READ(RCPREVBSYTUPAVG);
307 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 308 max_avg = I915_READ(RCBMAXAVG);
309 min_avg = I915_READ(RCBMINAVG);
310
311 /* Handle RCS change request from hw */
b5b72e89 312 if (busy_up > max_avg) {
f97108d1
JB		 313 if (dev_priv->cur_delay != dev_priv->max_delay)
314 new_delay = dev_priv->cur_delay - 1;
315 if (new_delay < dev_priv->max_delay)
316 new_delay = dev_priv->max_delay;
b5b72e89 317 } else if (busy_down < min_avg) {
f97108d1
JB		 318 if (dev_priv->cur_delay != dev_priv->min_delay)
319 new_delay = dev_priv->cur_delay + 1;
320 if (new_delay > dev_priv->min_delay)
321 new_delay = dev_priv->min_delay;
322 }
323
7648fa99
JB		 324 if (ironlake_set_drps(dev, new_delay))
325 dev_priv->cur_delay = new_delay;
f97108d1
JB		 326
327 return;
328}
329
549f7365
CW		 330static void notify_ring(struct drm_device *dev,
331 struct intel_ring_buffer *ring)
332{
333 struct drm_i915_private *dev_priv = dev->dev_private;
9862e600 334
475553de
CW		 335 if (ring->obj == NULL)
336 return;
337
6d171cb4 338 trace_i915_gem_request_complete(ring, ring->get_seqno(ring));
9862e600 339
549f7365 340 wake_up_all(&ring->irq_queue);
3e0dc6b0
BW		 341 if (i915_enable_hangcheck) {
342 dev_priv->hangcheck_count = 0;
343 mod_timer(&dev_priv->hangcheck_timer,
344 jiffies +
345 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
346 }
549f7365
CW		 347}
348
4912d041 349static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 350{
4912d041
BW		 351 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
352 rps_work);
3b8d8d91 353 u8 new_delay = dev_priv->cur_delay;
4912d041
BW		 354 u32 pm_iir, pm_imr;
355
356 spin_lock_irq(&dev_priv->rps_lock);
357 pm_iir = dev_priv->pm_iir;
358 dev_priv->pm_iir = 0;
359 pm_imr = I915_READ(GEN6_PMIMR);
a9e2641d 360 I915_WRITE(GEN6_PMIMR, 0);
4912d041 361 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91 362
3b8d8d91
JB		 363 if (!pm_iir)
364 return;
365
4912d041 366 mutex_lock(&dev_priv->dev->struct_mutex);
3b8d8d91
JB		 367 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
368 if (dev_priv->cur_delay != dev_priv->max_delay)
369 new_delay = dev_priv->cur_delay + 1;
370 if (new_delay > dev_priv->max_delay)
371 new_delay = dev_priv->max_delay;
372 } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
4912d041 373 gen6_gt_force_wake_get(dev_priv);
3b8d8d91
JB		 374 if (dev_priv->cur_delay != dev_priv->min_delay)
375 new_delay = dev_priv->cur_delay - 1;
376 if (new_delay < dev_priv->min_delay) {
377 new_delay = dev_priv->min_delay;
378 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
379 I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
380 ((new_delay << 16) & 0x3f0000));
381 } else {
382 /* Make sure we continue to get down interrupts
383 * until we hit the minimum frequency */
384 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
385 I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
386 }
4912d041 387 gen6_gt_force_wake_put(dev_priv);
3b8d8d91
JB		 388 }
389
4912d041 390 gen6_set_rps(dev_priv->dev, new_delay);
3b8d8d91
JB		 391 dev_priv->cur_delay = new_delay;
392
4912d041
BW		 393 /*
394 * rps_lock not held here because clearing is non-destructive. There is
395 * an *extremely* unlikely race with gen6_rps_enable() that is prevented
396 * by holding struct_mutex for the duration of the write.
397 */
4912d041 398 mutex_unlock(&dev_priv->dev->struct_mutex);
3b8d8d91
JB		 399}
400
e7b4c6b1
DV		 401static void snb_gt_irq_handler(struct drm_device *dev,
402 struct drm_i915_private *dev_priv,
403 u32 gt_iir)
404{
405
406 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
407 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
408 notify_ring(dev, &dev_priv->ring[RCS]);
409 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
410 notify_ring(dev, &dev_priv->ring[VCS]);
411 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
412 notify_ring(dev, &dev_priv->ring[BCS]);
413
414 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
415 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
416 GT_RENDER_CS_ERROR_INTERRUPT)) {
417 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
418 i915_handle_error(dev, false);
419 }
420}
421
fc6826d1
CW		 422static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
423 u32 pm_iir)
424{
425 unsigned long flags;
426
427 /*
428 * IIR bits should never already be set because IMR should
429 * prevent an interrupt from being shown in IIR. The warning
430 * displays a case where we've unsafely cleared
431 * dev_priv->pm_iir. Although missing an interrupt of the same
432 * type is not a problem, it displays a problem in the logic.
433 *
434 * The mask bit in IMR is cleared by rps_work.
435 */
436
437 spin_lock_irqsave(&dev_priv->rps_lock, flags);
438 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
439 dev_priv->pm_iir |= pm_iir;
440 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
441 POSTING_READ(GEN6_PMIMR);
442 spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
443
444 queue_work(dev_priv->wq, &dev_priv->rps_work);
445}
446
7e231dbe
JB		 447static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
448{
449 struct drm_device *dev = (struct drm_device *) arg;
450 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
451 u32 iir, gt_iir, pm_iir;
452 irqreturn_t ret = IRQ_NONE;
453 unsigned long irqflags;
454 int pipe;
455 u32 pipe_stats[I915_MAX_PIPES];
456 u32 vblank_status;
457 int vblank = 0;
458 bool blc_event;
459
460 atomic_inc(&dev_priv->irq_received);
461
462 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS |
463 PIPE_VBLANK_INTERRUPT_STATUS;
464
465 while (true) {
466 iir = I915_READ(VLV_IIR);
467 gt_iir = I915_READ(GTIIR);
468 pm_iir = I915_READ(GEN6_PMIIR);
469
470 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
471 goto out;
472
473 ret = IRQ_HANDLED;
474
e7b4c6b1 475 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 476
477 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
478 for_each_pipe(pipe) {
479 int reg = PIPESTAT(pipe);
480 pipe_stats[pipe] = I915_READ(reg);
481
482 /*
483 * Clear the PIPE*STAT regs before the IIR
484 */
485 if (pipe_stats[pipe] & 0x8000ffff) {
486 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
487 DRM_DEBUG_DRIVER("pipe %c underrun\n",
488 pipe_name(pipe));
489 I915_WRITE(reg, pipe_stats[pipe]);
490 }
491 }
492 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
493
494 /* Consume port. Then clear IIR or we'll miss events */
495 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
496 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
497
498 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
499 hotplug_status);
500 if (hotplug_status & dev_priv->hotplug_supported_mask)
501 queue_work(dev_priv->wq,
502 &dev_priv->hotplug_work);
503
504 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
505 I915_READ(PORT_HOTPLUG_STAT);
506 }
507
508
509 if (iir & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) {
510 drm_handle_vblank(dev, 0);
511 vblank++;
e0f608d7 512 intel_finish_page_flip(dev, 0);
7e231dbe
JB		 513 }
514
515 if (iir & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) {
516 drm_handle_vblank(dev, 1);
517 vblank++;
e0f608d7 518 intel_finish_page_flip(dev, 0);
7e231dbe
JB		 519 }
520
521 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
522 blc_event = true;
523
fc6826d1
CW		 524 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
525 gen6_queue_rps_work(dev_priv, pm_iir);
7e231dbe
JB		 526
527 I915_WRITE(GTIIR, gt_iir);
528 I915_WRITE(GEN6_PMIIR, pm_iir);
529 I915_WRITE(VLV_IIR, iir);
530 }
531
532out:
533 return ret;
534}
535
776ad806
JB		 536static void pch_irq_handler(struct drm_device *dev)
537{
538 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
539 u32 pch_iir;
9db4a9c7 540 int pipe;
776ad806
JB		 541
542 pch_iir = I915_READ(SDEIIR);
543
544 if (pch_iir & SDE_AUDIO_POWER_MASK)
545 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
546 (pch_iir & SDE_AUDIO_POWER_MASK) >>
547 SDE_AUDIO_POWER_SHIFT);
548
549 if (pch_iir & SDE_GMBUS)
550 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
551
552 if (pch_iir & SDE_AUDIO_HDCP_MASK)
553 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
554
555 if (pch_iir & SDE_AUDIO_TRANS_MASK)
556 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
557
558 if (pch_iir & SDE_POISON)
559 DRM_ERROR("PCH poison interrupt\n");
560
9db4a9c7
JB		 561 if (pch_iir & SDE_FDI_MASK)
562 for_each_pipe(pipe)
563 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
564 pipe_name(pipe),
565 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 566
567 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
568 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
569
570 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
571 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
572
573 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
574 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
575 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
576 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
577}
578
f71d4af4 579static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
b1f14ad0
JB		 580{
581 struct drm_device *dev = (struct drm_device *) arg;
582 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
583 int ret = IRQ_NONE;
584 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
b1f14ad0
JB		 585
586 atomic_inc(&dev_priv->irq_received);
587
588 /* disable master interrupt before clearing iir */
589 de_ier = I915_READ(DEIER);
590 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
591 POSTING_READ(DEIER);
592
593 de_iir = I915_READ(DEIIR);
594 gt_iir = I915_READ(GTIIR);
595 pch_iir = I915_READ(SDEIIR);
596 pm_iir = I915_READ(GEN6_PMIIR);
597
598 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && pm_iir == 0)
599 goto done;
600
601 ret = IRQ_HANDLED;
602
e7b4c6b1 603 snb_gt_irq_handler(dev, dev_priv, gt_iir);
b1f14ad0
JB		 604
605 if (de_iir & DE_GSE_IVB)
606 intel_opregion_gse_intr(dev);
607
608 if (de_iir & DE_PLANEA_FLIP_DONE_IVB) {
609 intel_prepare_page_flip(dev, 0);
610 intel_finish_page_flip_plane(dev, 0);
611 }
612
613 if (de_iir & DE_PLANEB_FLIP_DONE_IVB) {
614 intel_prepare_page_flip(dev, 1);
615 intel_finish_page_flip_plane(dev, 1);
616 }
617
b615b57a
CW		 618 if (de_iir & DE_PLANEC_FLIP_DONE_IVB) {
619 intel_prepare_page_flip(dev, 2);
620 intel_finish_page_flip_plane(dev, 2);
621 }
622
b1f14ad0
JB		 623 if (de_iir & DE_PIPEA_VBLANK_IVB)
624 drm_handle_vblank(dev, 0);
625
f6b07f45 626 if (de_iir & DE_PIPEB_VBLANK_IVB)
b1f14ad0
JB		 627 drm_handle_vblank(dev, 1);
628
b615b57a
CW		 629 if (de_iir & DE_PIPEC_VBLANK_IVB)
630 drm_handle_vblank(dev, 2);
631
b1f14ad0
JB		 632 /* check event from PCH */
633 if (de_iir & DE_PCH_EVENT_IVB) {
634 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
635 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
636 pch_irq_handler(dev);
637 }
638
fc6826d1
CW		 639 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
640 gen6_queue_rps_work(dev_priv, pm_iir);
b1f14ad0
JB		 641
642 /* should clear PCH hotplug event before clear CPU irq */
643 I915_WRITE(SDEIIR, pch_iir);
644 I915_WRITE(GTIIR, gt_iir);
645 I915_WRITE(DEIIR, de_iir);
646 I915_WRITE(GEN6_PMIIR, pm_iir);
647
648done:
649 I915_WRITE(DEIER, de_ier);
650 POSTING_READ(DEIER);
651
652 return ret;
653}
654
e7b4c6b1
DV		 655static void ilk_gt_irq_handler(struct drm_device *dev,
656 struct drm_i915_private *dev_priv,
657 u32 gt_iir)
658{
659 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
660 notify_ring(dev, &dev_priv->ring[RCS]);
661 if (gt_iir & GT_BSD_USER_INTERRUPT)
662 notify_ring(dev, &dev_priv->ring[VCS]);
663}
664
f71d4af4 665static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
036a4a7d 666{
4697995b 667 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 668 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
669 int ret = IRQ_NONE;
3b8d8d91 670 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
2d7b8366 671 u32 hotplug_mask;
881f47b6 672
4697995b
JB		 673 atomic_inc(&dev_priv->irq_received);
674
2d109a84
ZN		 675 /* disable master interrupt before clearing iir */
676 de_ier = I915_READ(DEIER);
677 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 678 POSTING_READ(DEIER);
2d109a84 679
036a4a7d
ZW		 680 de_iir = I915_READ(DEIIR);
681 gt_iir = I915_READ(GTIIR);
c650156a 682 pch_iir = I915_READ(SDEIIR);
3b8d8d91 683 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 684
3b8d8d91
JB		 685 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
686 (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 687 goto done;
036a4a7d 688
2d7b8366
YL		 689 if (HAS_PCH_CPT(dev))
690 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
691 else
692 hotplug_mask = SDE_HOTPLUG_MASK;
693
c7c85101 694 ret = IRQ_HANDLED;
036a4a7d 695
e7b4c6b1
DV		 696 if (IS_GEN5(dev))
697 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
698 else
699 snb_gt_irq_handler(dev, dev_priv, gt_iir);
01c66889 700
c7c85101 701 if (de_iir & DE_GSE)
3b617967 702 intel_opregion_gse_intr(dev);
c650156a 703
f072d2e7 704 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 705 intel_prepare_page_flip(dev, 0);
2bbda389 706 intel_finish_page_flip_plane(dev, 0);
f072d2e7 707 }
013d5aa2 708
f072d2e7 709 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 710 intel_prepare_page_flip(dev, 1);
2bbda389 711 intel_finish_page_flip_plane(dev, 1);
f072d2e7 712 }
013d5aa2 713
f072d2e7 714 if (de_iir & DE_PIPEA_VBLANK)
c062df61
LP		 715 drm_handle_vblank(dev, 0);
716
f072d2e7 717 if (de_iir & DE_PIPEB_VBLANK)
c062df61
LP		 718 drm_handle_vblank(dev, 1);
719
c7c85101 720 /* check event from PCH */
776ad806
JB		 721 if (de_iir & DE_PCH_EVENT) {
722 if (pch_iir & hotplug_mask)
723 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
724 pch_irq_handler(dev);
725 }
036a4a7d 726
f97108d1 727 if (de_iir & DE_PCU_EVENT) {
7648fa99 728 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
f97108d1
JB		 729 i915_handle_rps_change(dev);
730 }
731
fc6826d1
CW		 732 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
733 gen6_queue_rps_work(dev_priv, pm_iir);
3b8d8d91 734
c7c85101
ZN		 735 /* should clear PCH hotplug event before clear CPU irq */
736 I915_WRITE(SDEIIR, pch_iir);
737 I915_WRITE(GTIIR, gt_iir);
738 I915_WRITE(DEIIR, de_iir);
4912d041 739 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 740
741done:
2d109a84 742 I915_WRITE(DEIER, de_ier);
3143a2bf 743 POSTING_READ(DEIER);
2d109a84 744
036a4a7d
ZW		 745 return ret;
746}
747
8a905236
JB		 748/**
749 * i915_error_work_func - do process context error handling work
750 * @work: work struct
751 *
752 * Fire an error uevent so userspace can see that a hang or error
753 * was detected.
754 */
755static void i915_error_work_func(struct work_struct *work)
756{
757 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
758 error_work);
759 struct drm_device *dev = dev_priv->dev;
f316a42c
BG		 760 char *error_event[] = { "ERROR=1", NULL };
761 char *reset_event[] = { "RESET=1", NULL };
762 char *reset_done_event[] = { "ERROR=0", NULL };
8a905236 763
f316a42c
BG		 764 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
765
ba1234d1 766 if (atomic_read(&dev_priv->mm.wedged)) {
f803aa55
CW		 767 DRM_DEBUG_DRIVER("resetting chip\n");
768 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
d4b8bb2a 769 if (!i915_reset(dev)) {
f803aa55
CW		 770 atomic_set(&dev_priv->mm.wedged, 0);
771 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
f316a42c 772 }
30dbf0c0 773 complete_all(&dev_priv->error_completion);
f316a42c 774 }
8a905236
JB		 775}
776
3bd3c932 777#ifdef CONFIG_DEBUG_FS
9df30794 778static struct drm_i915_error_object *
bcfb2e28 779i915_error_object_create(struct drm_i915_private *dev_priv,
05394f39 780 struct drm_i915_gem_object *src)
9df30794
CW		 781{
782 struct drm_i915_error_object *dst;
9df30794 783 int page, page_count;
e56660dd 784 u32 reloc_offset;
9df30794 785
05394f39 786 if (src == NULL || src->pages == NULL)
9df30794
CW		 787 return NULL;
788
05394f39 789 page_count = src->base.size / PAGE_SIZE;
9df30794 790
0206e353 791 dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
9df30794
CW		 792 if (dst == NULL)
793 return NULL;
794
05394f39 795 reloc_offset = src->gtt_offset;
9df30794 796 for (page = 0; page < page_count; page++) {
788885ae 797 unsigned long flags;
e56660dd 798 void *d;
788885ae 799
e56660dd 800 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 801 if (d == NULL)
802 goto unwind;
e56660dd 803
788885ae 804 local_irq_save(flags);
74898d7e
DV		 805 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
806 src->has_global_gtt_mapping) {
172975aa
CW		 807 void __iomem *s;
808
809 /* Simply ignore tiling or any overlapping fence.
810 * It's part of the error state, and this hopefully
811 * captures what the GPU read.
812 */
813
814 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
815 reloc_offset);
816 memcpy_fromio(d, s, PAGE_SIZE);
817 io_mapping_unmap_atomic(s);
818 } else {
819 void *s;
820
821 drm_clflush_pages(&src->pages[page], 1);
822
823 s = kmap_atomic(src->pages[page]);
824 memcpy(d, s, PAGE_SIZE);
825 kunmap_atomic(s);
826
827 drm_clflush_pages(&src->pages[page], 1);
828 }
788885ae 829 local_irq_restore(flags);
e56660dd 830
9df30794 831 dst->pages[page] = d;
e56660dd
CW		 832
833 reloc_offset += PAGE_SIZE;
9df30794
CW		 834 }
835 dst->page_count = page_count;
05394f39 836 dst->gtt_offset = src->gtt_offset;
9df30794
CW		 837
838 return dst;
839
840unwind:
841 while (page--)
842 kfree(dst->pages[page]);
843 kfree(dst);
844 return NULL;
845}
846
847static void
848i915_error_object_free(struct drm_i915_error_object *obj)
849{
850 int page;
851
852 if (obj == NULL)
853 return;
854
855 for (page = 0; page < obj->page_count; page++)
856 kfree(obj->pages[page]);
857
858 kfree(obj);
859}
860
742cbee8
DV		 861void
862i915_error_state_free(struct kref *error_ref)
9df30794 863{
742cbee8
DV		 864 struct drm_i915_error_state *error = container_of(error_ref,
865 typeof(*error), ref);
e2f973d5
CW		 866 int i;
867
52d39a21
CW		 868 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
869 i915_error_object_free(error->ring[i].batchbuffer);
870 i915_error_object_free(error->ring[i].ringbuffer);
871 kfree(error->ring[i].requests);
872 }
e2f973d5 873
9df30794 874 kfree(error->active_bo);
6ef3d427 875 kfree(error->overlay);
9df30794
CW		 876 kfree(error);
877}
1b50247a
CW		 878static void capture_bo(struct drm_i915_error_buffer *err,
879 struct drm_i915_gem_object *obj)
880{
881 err->size = obj->base.size;
882 err->name = obj->base.name;
883 err->seqno = obj->last_rendering_seqno;
884 err->gtt_offset = obj->gtt_offset;
885 err->read_domains = obj->base.read_domains;
886 err->write_domain = obj->base.write_domain;
887 err->fence_reg = obj->fence_reg;
888 err->pinned = 0;
889 if (obj->pin_count > 0)
890 err->pinned = 1;
891 if (obj->user_pin_count > 0)
892 err->pinned = -1;
893 err->tiling = obj->tiling_mode;
894 err->dirty = obj->dirty;
895 err->purgeable = obj->madv != I915_MADV_WILLNEED;
896 err->ring = obj->ring ? obj->ring->id : -1;
897 err->cache_level = obj->cache_level;
898}
9df30794 899
1b50247a
CW		 900static u32 capture_active_bo(struct drm_i915_error_buffer *err,
901 int count, struct list_head *head)
c724e8a9
CW		 902{
903 struct drm_i915_gem_object *obj;
904 int i = 0;
905
906 list_for_each_entry(obj, head, mm_list) {
1b50247a 907 capture_bo(err++, obj);
c724e8a9
CW		 908 if (++i == count)
909 break;
1b50247a
CW		 910 }
911
912 return i;
913}
914
915static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
916 int count, struct list_head *head)
917{
918 struct drm_i915_gem_object *obj;
919 int i = 0;
920
921 list_for_each_entry(obj, head, gtt_list) {
922 if (obj->pin_count == 0)
923 continue;
c724e8a9 924
1b50247a
CW		 925 capture_bo(err++, obj);
926 if (++i == count)
927 break;
c724e8a9
CW		 928 }
929
930 return i;
931}
932
748ebc60
CW		 933static void i915_gem_record_fences(struct drm_device *dev,
934 struct drm_i915_error_state *error)
935{
936 struct drm_i915_private *dev_priv = dev->dev_private;
937 int i;
938
939 /* Fences */
940 switch (INTEL_INFO(dev)->gen) {
775d17b6 941 case 7:
748ebc60
CW		 942 case 6:
943 for (i = 0; i < 16; i++)
944 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
945 break;
946 case 5:
947 case 4:
948 for (i = 0; i < 16; i++)
949 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
950 break;
951 case 3:
952 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
953 for (i = 0; i < 8; i++)
954 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
955 case 2:
956 for (i = 0; i < 8; i++)
957 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
958 break;
959
960 }
961}
962
bcfb2e28
CW		 963static struct drm_i915_error_object *
964i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
965 struct intel_ring_buffer *ring)
966{
967 struct drm_i915_gem_object *obj;
968 u32 seqno;
969
970 if (!ring->get_seqno)
971 return NULL;
972
973 seqno = ring->get_seqno(ring);
974 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
975 if (obj->ring != ring)
976 continue;
977
c37d9a5d 978 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
bcfb2e28
CW		 979 continue;
980
981 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
982 continue;
983
984 /* We need to copy these to an anonymous buffer as the simplest
985 * method to avoid being overwritten by userspace.
986 */
987 return i915_error_object_create(dev_priv, obj);
988 }
989
990 return NULL;
991}
992
d27b1e0e
DV		 993static void i915_record_ring_state(struct drm_device *dev,
994 struct drm_i915_error_state *error,
995 struct intel_ring_buffer *ring)
996{
997 struct drm_i915_private *dev_priv = dev->dev_private;
998
33f3f518 999 if (INTEL_INFO(dev)->gen >= 6) {
33f3f518 1000 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
7e3b8737
DV		 1001 error->semaphore_mboxes[ring->id][0]
1002 = I915_READ(RING_SYNC_0(ring->mmio_base));
1003 error->semaphore_mboxes[ring->id][1]
1004 = I915_READ(RING_SYNC_1(ring->mmio_base));
33f3f518 1005 }
c1cd90ed 1006
d27b1e0e 1007 if (INTEL_INFO(dev)->gen >= 4) {
9d2f41fa 1008 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
d27b1e0e
DV		 1009 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1010 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1011 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
c1cd90ed 1012 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
d27b1e0e 1013 if (ring->id == RCS) {
d27b1e0e
DV		 1014 error->instdone1 = I915_READ(INSTDONE1);
1015 error->bbaddr = I915_READ64(BB_ADDR);
1016 }
1017 } else {
9d2f41fa 1018 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
d27b1e0e
DV		 1019 error->ipeir[ring->id] = I915_READ(IPEIR);
1020 error->ipehr[ring->id] = I915_READ(IPEHR);
1021 error->instdone[ring->id] = I915_READ(INSTDONE);
d27b1e0e
DV		 1022 }
1023
9574b3fe 1024 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
c1cd90ed 1025 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
d27b1e0e
DV		 1026 error->seqno[ring->id] = ring->get_seqno(ring);
1027 error->acthd[ring->id] = intel_ring_get_active_head(ring);
c1cd90ed
DV		 1028 error->head[ring->id] = I915_READ_HEAD(ring);
1029 error->tail[ring->id] = I915_READ_TAIL(ring);
7e3b8737
DV		 1030
1031 error->cpu_ring_head[ring->id] = ring->head;
1032 error->cpu_ring_tail[ring->id] = ring->tail;
d27b1e0e
DV		 1033}
1034
52d39a21
CW		 1035static void i915_gem_record_rings(struct drm_device *dev,
1036 struct drm_i915_error_state *error)
1037{
1038 struct drm_i915_private *dev_priv = dev->dev_private;
1039 struct drm_i915_gem_request *request;
1040 int i, count;
1041
1042 for (i = 0; i < I915_NUM_RINGS; i++) {
1043 struct intel_ring_buffer *ring = &dev_priv->ring[i];
1044
1045 if (ring->obj == NULL)
1046 continue;
1047
1048 i915_record_ring_state(dev, error, ring);
1049
1050 error->ring[i].batchbuffer =
1051 i915_error_first_batchbuffer(dev_priv, ring);
1052
1053 error->ring[i].ringbuffer =
1054 i915_error_object_create(dev_priv, ring->obj);
1055
1056 count = 0;
1057 list_for_each_entry(request, &ring->request_list, list)
1058 count++;
1059
1060 error->ring[i].num_requests = count;
1061 error->ring[i].requests =
1062 kmalloc(count*sizeof(struct drm_i915_error_request),
1063 GFP_ATOMIC);
1064 if (error->ring[i].requests == NULL) {
1065 error->ring[i].num_requests = 0;
1066 continue;
1067 }
1068
1069 count = 0;
1070 list_for_each_entry(request, &ring->request_list, list) {
1071 struct drm_i915_error_request *erq;
1072
1073 erq = &error->ring[i].requests[count++];
1074 erq->seqno = request->seqno;
1075 erq->jiffies = request->emitted_jiffies;
ee4f42b1 1076 erq->tail = request->tail;
52d39a21
CW		 1077 }
1078 }
1079}
1080
8a905236
JB		 1081/**
1082 * i915_capture_error_state - capture an error record for later analysis
1083 * @dev: drm device
1084 *
1085 * Should be called when an error is detected (either a hang or an error
1086 * interrupt) to capture error state from the time of the error. Fills
1087 * out a structure which becomes available in debugfs for user level tools
1088 * to pick up.
1089 */
63eeaf38
JB		 1090static void i915_capture_error_state(struct drm_device *dev)
1091{
1092 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1093 struct drm_i915_gem_object *obj;
63eeaf38
JB		 1094 struct drm_i915_error_state *error;
1095 unsigned long flags;
9db4a9c7 1096 int i, pipe;
63eeaf38
JB		 1097
1098 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1099 error = dev_priv->first_error;
1100 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1101 if (error)
1102 return;
63eeaf38 1103
9db4a9c7 1104 /* Account for pipe specific data like PIPE*STAT */
33f3f518 1105 error = kzalloc(sizeof(*error), GFP_ATOMIC);
63eeaf38 1106 if (!error) {
9df30794
CW		 1107 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1108 return;
63eeaf38
JB		 1109 }
1110
b6f7833b
CW		 1111 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1112 dev->primary->index);
2fa772f3 1113
742cbee8 1114 kref_init(&error->ref);
63eeaf38
JB		 1115 error->eir = I915_READ(EIR);
1116 error->pgtbl_er = I915_READ(PGTBL_ER);
be998e2e
BW		 1117
1118 if (HAS_PCH_SPLIT(dev))
1119 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1120 else if (IS_VALLEYVIEW(dev))
1121 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1122 else if (IS_GEN2(dev))
1123 error->ier = I915_READ16(IER);
1124 else
1125 error->ier = I915_READ(IER);
1126
9db4a9c7
JB		 1127 for_each_pipe(pipe)
1128 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
d27b1e0e 1129
33f3f518 1130 if (INTEL_INFO(dev)->gen >= 6) {
f406839f 1131 error->error = I915_READ(ERROR_GEN6);
33f3f518
DV		 1132 error->done_reg = I915_READ(DONE_REG);
1133 }
d27b1e0e 1134
748ebc60 1135 i915_gem_record_fences(dev, error);
52d39a21 1136 i915_gem_record_rings(dev, error);
9df30794 1137
c724e8a9 1138 /* Record buffers on the active and pinned lists. */
9df30794 1139 error->active_bo = NULL;
c724e8a9 1140 error->pinned_bo = NULL;
9df30794 1141
bcfb2e28
CW		 1142 i = 0;
1143 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1144 i++;
1145 error->active_bo_count = i;
1b50247a
CW		 1146 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
1147 if (obj->pin_count)
1148 i++;
bcfb2e28 1149 error->pinned_bo_count = i - error->active_bo_count;
c724e8a9 1150
8e934dbf
CW		 1151 error->active_bo = NULL;
1152 error->pinned_bo = NULL;
bcfb2e28
CW		 1153 if (i) {
1154 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
9df30794 1155 GFP_ATOMIC);
c724e8a9
CW		 1156 if (error->active_bo)
1157 error->pinned_bo =
1158 error->active_bo + error->active_bo_count;
9df30794
CW		 1159 }
1160
c724e8a9
CW		 1161 if (error->active_bo)
1162 error->active_bo_count =
1b50247a
CW		 1163 capture_active_bo(error->active_bo,
1164 error->active_bo_count,
1165 &dev_priv->mm.active_list);
c724e8a9
CW		 1166
1167 if (error->pinned_bo)
1168 error->pinned_bo_count =
1b50247a
CW		 1169 capture_pinned_bo(error->pinned_bo,
1170 error->pinned_bo_count,
1171 &dev_priv->mm.gtt_list);
c724e8a9 1172
9df30794
CW		 1173 do_gettimeofday(&error->time);
1174
6ef3d427 1175 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 1176 error->display = intel_display_capture_error_state(dev);
6ef3d427 1177
9df30794
CW		 1178 spin_lock_irqsave(&dev_priv->error_lock, flags);
1179 if (dev_priv->first_error == NULL) {
1180 dev_priv->first_error = error;
1181 error = NULL;
1182 }
63eeaf38 1183 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1184
1185 if (error)
742cbee8 1186 i915_error_state_free(&error->ref);
9df30794
CW		 1187}
1188
1189void i915_destroy_error_state(struct drm_device *dev)
1190{
1191 struct drm_i915_private *dev_priv = dev->dev_private;
1192 struct drm_i915_error_state *error;
6dc0e816 1193 unsigned long flags;
9df30794 1194
6dc0e816 1195 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1196 error = dev_priv->first_error;
1197 dev_priv->first_error = NULL;
6dc0e816 1198 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1199
1200 if (error)
742cbee8 1201 kref_put(&error->ref, i915_error_state_free);
63eeaf38 1202}
3bd3c932
CW		 1203#else
1204#define i915_capture_error_state(x)
1205#endif
63eeaf38 1206
35aed2e6 1207static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1208{
1209 struct drm_i915_private *dev_priv = dev->dev_private;
1210 u32 eir = I915_READ(EIR);
9db4a9c7 1211 int pipe;
8a905236 1212
35aed2e6
CW		 1213 if (!eir)
1214 return;
8a905236 1215
a70491cc 1216 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236
JB		 1217
1218 if (IS_G4X(dev)) {
1219 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1220 u32 ipeir = I915_READ(IPEIR_I965);
1221
a70491cc
JP		 1222 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1223 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1224 pr_err(" INSTDONE: 0x%08x\n",
8a905236 1225 I915_READ(INSTDONE_I965));
a70491cc
JP		 1226 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1227 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1228 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1229 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1230 POSTING_READ(IPEIR_I965);
8a905236
JB		 1231 }
1232 if (eir & GM45_ERROR_PAGE_TABLE) {
1233 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1234 pr_err("page table error\n");
1235 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1236 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1237 POSTING_READ(PGTBL_ER);
8a905236
JB		 1238 }
1239 }
1240
a6c45cf0 1241 if (!IS_GEN2(dev)) {
8a905236
JB		 1242 if (eir & I915_ERROR_PAGE_TABLE) {
1243 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1244 pr_err("page table error\n");
1245 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1246 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1247 POSTING_READ(PGTBL_ER);
8a905236
JB		 1248 }
1249 }
1250
1251 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 1252 pr_err("memory refresh error:\n");
9db4a9c7 1253 for_each_pipe(pipe)
a70491cc 1254 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 1255 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 1256 /* pipestat has already been acked */
1257 }
1258 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 1259 pr_err("instruction error\n");
1260 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
a6c45cf0 1261 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 1262 u32 ipeir = I915_READ(IPEIR);
1263
a70491cc
JP		 1264 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1265 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
1266 pr_err(" INSTDONE: 0x%08x\n", I915_READ(INSTDONE));
1267 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 1268 I915_WRITE(IPEIR, ipeir);
3143a2bf 1269 POSTING_READ(IPEIR);
8a905236
JB		 1270 } else {
1271 u32 ipeir = I915_READ(IPEIR_I965);
1272
a70491cc
JP		 1273 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1274 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1275 pr_err(" INSTDONE: 0x%08x\n",
8a905236 1276 I915_READ(INSTDONE_I965));
a70491cc
JP		 1277 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1278 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1279 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1280 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1281 POSTING_READ(IPEIR_I965);
8a905236
JB		 1282 }
1283 }
1284
1285 I915_WRITE(EIR, eir);
3143a2bf 1286 POSTING_READ(EIR);
8a905236
JB		 1287 eir = I915_READ(EIR);
1288 if (eir) {
1289 /*
1290 * some errors might have become stuck,
1291 * mask them.
1292 */
1293 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1294 I915_WRITE(EMR, I915_READ(EMR) | eir);
1295 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1296 }
35aed2e6
CW		 1297}
1298
1299/**
1300 * i915_handle_error - handle an error interrupt
1301 * @dev: drm device
1302 *
1303 * Do some basic checking of regsiter state at error interrupt time and
1304 * dump it to the syslog. Also call i915_capture_error_state() to make
1305 * sure we get a record and make it available in debugfs. Fire a uevent
1306 * so userspace knows something bad happened (should trigger collection
1307 * of a ring dump etc.).
1308 */
527f9e90 1309void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 1310{
1311 struct drm_i915_private *dev_priv = dev->dev_private;
1312
1313 i915_capture_error_state(dev);
1314 i915_report_and_clear_eir(dev);
8a905236 1315
ba1234d1 1316 if (wedged) {
30dbf0c0 1317 INIT_COMPLETION(dev_priv->error_completion);
ba1234d1
BG		 1318 atomic_set(&dev_priv->mm.wedged, 1);
1319
11ed50ec
BG		 1320 /*
1321 * Wakeup waiting processes so they don't hang
1322 */
1ec14ad3 1323 wake_up_all(&dev_priv->ring[RCS].irq_queue);
f787a5f5 1324 if (HAS_BSD(dev))
1ec14ad3 1325 wake_up_all(&dev_priv->ring[VCS].irq_queue);
549f7365 1326 if (HAS_BLT(dev))
1ec14ad3 1327 wake_up_all(&dev_priv->ring[BCS].irq_queue);
11ed50ec
BG		 1328 }
1329
9c9fe1f8 1330 queue_work(dev_priv->wq, &dev_priv->error_work);
8a905236
JB		 1331}
1332
4e5359cd
SF		 1333static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1334{
1335 drm_i915_private_t *dev_priv = dev->dev_private;
1336 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 1338 struct drm_i915_gem_object *obj;
4e5359cd
SF		 1339 struct intel_unpin_work *work;
1340 unsigned long flags;
1341 bool stall_detected;
1342
1343 /* Ignore early vblank irqs */
1344 if (intel_crtc == NULL)
1345 return;
1346
1347 spin_lock_irqsave(&dev->event_lock, flags);
1348 work = intel_crtc->unpin_work;
1349
1350 if (work == NULL || work->pending || !work->enable_stall_check) {
1351 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1352 spin_unlock_irqrestore(&dev->event_lock, flags);
1353 return;
1354 }
1355
1356 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 1357 obj = work->pending_flip_obj;
a6c45cf0 1358 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 1359 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545
AR		 1360 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1361 obj->gtt_offset;
4e5359cd 1362 } else {
9db4a9c7 1363 int dspaddr = DSPADDR(intel_crtc->plane);
05394f39 1364 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
01f2c773 1365 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 1366 crtc->x * crtc->fb->bits_per_pixel/8);
1367 }
1368
1369 spin_unlock_irqrestore(&dev->event_lock, flags);
1370
1371 if (stall_detected) {
1372 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1373 intel_prepare_page_flip(dev, intel_crtc->plane);
1374 }
1375}
1376
42f52ef8
KP		 1377/* Called from drm generic code, passed 'crtc' which
1378 * we use as a pipe index
1379 */
f71d4af4 1380static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1381{
1382 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1383 unsigned long irqflags;
71e0ffa5 1384
5eddb70b 1385 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 1386 return -EINVAL;
0a3e67a4 1387
1ec14ad3 1388 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 1389 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 1390 i915_enable_pipestat(dev_priv, pipe,
1391 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 1392 else
7c463586
KP		 1393 i915_enable_pipestat(dev_priv, pipe,
1394 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 1395
1396 /* maintain vblank delivery even in deep C-states */
1397 if (dev_priv->info->gen == 3)
6b26c86d 1398 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 1399 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 1400
0a3e67a4
JB		 1401 return 0;
1402}
1403
f71d4af4 1404static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1405{
1406 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1407 unsigned long irqflags;
1408
1409 if (!i915_pipe_enabled(dev, pipe))
1410 return -EINVAL;
1411
1412 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1413 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1414 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
f796cf8f
JB		 1415 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1416
1417 return 0;
1418}
1419
f71d4af4 1420static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1421{
1422 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1423 unsigned long irqflags;
1424
1425 if (!i915_pipe_enabled(dev, pipe))
1426 return -EINVAL;
1427
1428 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1429 ironlake_enable_display_irq(dev_priv,
1430 DE_PIPEA_VBLANK_IVB << (5 * pipe));
b1f14ad0
JB		 1431 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1432
1433 return 0;
1434}
1435
7e231dbe
JB		 1436static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1437{
1438 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1439 unsigned long irqflags;
1440 u32 dpfl, imr;
1441
1442 if (!i915_pipe_enabled(dev, pipe))
1443 return -EINVAL;
1444
1445 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1446 dpfl = I915_READ(VLV_DPFLIPSTAT);
1447 imr = I915_READ(VLV_IMR);
1448 if (pipe == 0) {
1449 dpfl |= PIPEA_VBLANK_INT_EN;
1450 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1451 } else {
1452 dpfl |= PIPEA_VBLANK_INT_EN;
1453 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1454 }
1455 I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1456 I915_WRITE(VLV_IMR, imr);
1457 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1458
1459 return 0;
1460}
1461
42f52ef8
KP		 1462/* Called from drm generic code, passed 'crtc' which
1463 * we use as a pipe index
1464 */
f71d4af4 1465static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1466{
1467 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1468 unsigned long irqflags;
0a3e67a4 1469
1ec14ad3 1470 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 1471 if (dev_priv->info->gen == 3)
6b26c86d 1472 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 1473
f796cf8f
JB		 1474 i915_disable_pipestat(dev_priv, pipe,
1475 PIPE_VBLANK_INTERRUPT_ENABLE |
1476 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1477 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1478}
1479
f71d4af4 1480static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1481{
1482 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1483 unsigned long irqflags;
1484
1485 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1486 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1487 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1ec14ad3 1488 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 1489}
1490
f71d4af4 1491static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1492{
1493 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1494 unsigned long irqflags;
1495
1496 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1497 ironlake_disable_display_irq(dev_priv,
1498 DE_PIPEA_VBLANK_IVB << (pipe * 5));
b1f14ad0
JB		 1499 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1500}
1501
7e231dbe
JB		 1502static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1503{
1504 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1505 unsigned long irqflags;
1506 u32 dpfl, imr;
1507
1508 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1509 dpfl = I915_READ(VLV_DPFLIPSTAT);
1510 imr = I915_READ(VLV_IMR);
1511 if (pipe == 0) {
1512 dpfl &= ~PIPEA_VBLANK_INT_EN;
1513 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1514 } else {
1515 dpfl &= ~PIPEB_VBLANK_INT_EN;
1516 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1517 }
1518 I915_WRITE(VLV_IMR, imr);
1519 I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1520 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1521}
1522
893eead0
CW		 1523static u32
1524ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 1525{
893eead0
CW		 1526 return list_entry(ring->request_list.prev,
1527 struct drm_i915_gem_request, list)->seqno;
1528}
1529
1530static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1531{
9574b3fe
BW		 1532 /* We don't check whether the ring even exists before calling this
1533 * function. Hence check whether it's initialized. */
1534 if (ring->obj == NULL)
1535 return true;
1536
893eead0
CW		 1537 if (list_empty(&ring->request_list) ||
1538 i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1539 /* Issue a wake-up to catch stuck h/w. */
9574b3fe
BW		 1540 if (waitqueue_active(&ring->irq_queue)) {
1541 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1542 ring->name);
893eead0
CW		 1543 wake_up_all(&ring->irq_queue);
1544 *err = true;
1545 }
1546 return true;
1547 }
1548 return false;
f65d9421
BG		 1549}
1550
1ec14ad3
CW		 1551static bool kick_ring(struct intel_ring_buffer *ring)
1552{
1553 struct drm_device *dev = ring->dev;
1554 struct drm_i915_private *dev_priv = dev->dev_private;
1555 u32 tmp = I915_READ_CTL(ring);
1556 if (tmp & RING_WAIT) {
1557 DRM_ERROR("Kicking stuck wait on %s\n",
1558 ring->name);
1559 I915_WRITE_CTL(ring, tmp);
1560 return true;
1561 }
1ec14ad3
CW		 1562 return false;
1563}
1564
d1e61e7f
CW		 1565static bool i915_hangcheck_hung(struct drm_device *dev)
1566{
1567 drm_i915_private_t *dev_priv = dev->dev_private;
1568
1569 if (dev_priv->hangcheck_count++ > 1) {
1570 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1571 i915_handle_error(dev, true);
1572
1573 if (!IS_GEN2(dev)) {
1574 /* Is the chip hanging on a WAIT_FOR_EVENT?
1575 * If so we can simply poke the RB_WAIT bit
1576 * and break the hang. This should work on
1577 * all but the second generation chipsets.
1578 */
1579 if (kick_ring(&dev_priv->ring[RCS]))
1580 return false;
1581
1582 if (HAS_BSD(dev) && kick_ring(&dev_priv->ring[VCS]))
1583 return false;
1584
1585 if (HAS_BLT(dev) && kick_ring(&dev_priv->ring[BCS]))
1586 return false;
1587 }
1588
1589 return true;
1590 }
1591
1592 return false;
1593}
1594
f65d9421
BG		 1595/**
1596 * This is called when the chip hasn't reported back with completed
1597 * batchbuffers in a long time. The first time this is called we simply record
1598 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1599 * again, we assume the chip is wedged and try to fix it.
1600 */
1601void i915_hangcheck_elapsed(unsigned long data)
1602{
1603 struct drm_device *dev = (struct drm_device *)data;
1604 drm_i915_private_t *dev_priv = dev->dev_private;
097354eb 1605 uint32_t acthd, instdone, instdone1, acthd_bsd, acthd_blt;
893eead0
CW		 1606 bool err = false;
1607
3e0dc6b0
BW		 1608 if (!i915_enable_hangcheck)
1609 return;
1610
893eead0 1611 /* If all work is done then ACTHD clearly hasn't advanced. */
1ec14ad3
CW		 1612 if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) &&
1613 i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) &&
1614 i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) {
d1e61e7f
CW		 1615 if (err) {
1616 if (i915_hangcheck_hung(dev))
1617 return;
1618
893eead0 1619 goto repeat;
d1e61e7f
CW		 1620 }
1621
1622 dev_priv->hangcheck_count = 0;
893eead0
CW		 1623 return;
1624 }
b9201c14 1625
a6c45cf0 1626 if (INTEL_INFO(dev)->gen < 4) {
cbb465e7
CW		 1627 instdone = I915_READ(INSTDONE);
1628 instdone1 = 0;
1629 } else {
cbb465e7
CW		 1630 instdone = I915_READ(INSTDONE_I965);
1631 instdone1 = I915_READ(INSTDONE1);
1632 }
097354eb
DV		 1633 acthd = intel_ring_get_active_head(&dev_priv->ring[RCS]);
1634 acthd_bsd = HAS_BSD(dev) ?
1635 intel_ring_get_active_head(&dev_priv->ring[VCS]) : 0;
1636 acthd_blt = HAS_BLT(dev) ?
1637 intel_ring_get_active_head(&dev_priv->ring[BCS]) : 0;
f65d9421 1638
cbb465e7 1639 if (dev_priv->last_acthd == acthd &&
097354eb
DV		 1640 dev_priv->last_acthd_bsd == acthd_bsd &&
1641 dev_priv->last_acthd_blt == acthd_blt &&
cbb465e7
CW		 1642 dev_priv->last_instdone == instdone &&
1643 dev_priv->last_instdone1 == instdone1) {
d1e61e7f 1644 if (i915_hangcheck_hung(dev))
cbb465e7 1645 return;
cbb465e7
CW		 1646 } else {
1647 dev_priv->hangcheck_count = 0;
1648
1649 dev_priv->last_acthd = acthd;
097354eb
DV		 1650 dev_priv->last_acthd_bsd = acthd_bsd;
1651 dev_priv->last_acthd_blt = acthd_blt;
cbb465e7
CW		 1652 dev_priv->last_instdone = instdone;
1653 dev_priv->last_instdone1 = instdone1;
1654 }
f65d9421 1655
893eead0 1656repeat:
f65d9421 1657 /* Reset timer case chip hangs without another request being added */
b3b079db
CW		 1658 mod_timer(&dev_priv->hangcheck_timer,
1659 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
f65d9421
BG		 1660}
1661
1da177e4
LT		 1662/* drm_dma.h hooks
1663*/
f71d4af4 1664static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 1665{
1666 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1667
4697995b
JB		 1668 atomic_set(&dev_priv->irq_received, 0);
1669
4697995b 1670
036a4a7d 1671 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 1672
036a4a7d
ZW		 1673 /* XXX hotplug from PCH */
1674
1675 I915_WRITE(DEIMR, 0xffffffff);
1676 I915_WRITE(DEIER, 0x0);
3143a2bf 1677 POSTING_READ(DEIER);
036a4a7d
ZW		 1678
1679 /* and GT */
1680 I915_WRITE(GTIMR, 0xffffffff);
1681 I915_WRITE(GTIER, 0x0);
3143a2bf 1682 POSTING_READ(GTIER);
c650156a
ZW		 1683
1684 /* south display irq */
1685 I915_WRITE(SDEIMR, 0xffffffff);
1686 I915_WRITE(SDEIER, 0x0);
3143a2bf 1687 POSTING_READ(SDEIER);
036a4a7d
ZW		 1688}
1689
7e231dbe
JB		 1690static void valleyview_irq_preinstall(struct drm_device *dev)
1691{
1692 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1693 int pipe;
1694
1695 atomic_set(&dev_priv->irq_received, 0);
1696
7e231dbe
JB		 1697 /* VLV magic */
1698 I915_WRITE(VLV_IMR, 0);
1699 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1700 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1701 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1702
7e231dbe
JB		 1703 /* and GT */
1704 I915_WRITE(GTIIR, I915_READ(GTIIR));
1705 I915_WRITE(GTIIR, I915_READ(GTIIR));
1706 I915_WRITE(GTIMR, 0xffffffff);
1707 I915_WRITE(GTIER, 0x0);
1708 POSTING_READ(GTIER);
1709
1710 I915_WRITE(DPINVGTT, 0xff);
1711
1712 I915_WRITE(PORT_HOTPLUG_EN, 0);
1713 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1714 for_each_pipe(pipe)
1715 I915_WRITE(PIPESTAT(pipe), 0xffff);
1716 I915_WRITE(VLV_IIR, 0xffffffff);
1717 I915_WRITE(VLV_IMR, 0xffffffff);
1718 I915_WRITE(VLV_IER, 0x0);
1719 POSTING_READ(VLV_IER);
1720}
1721
7fe0b973
KP		 1722/*
1723 * Enable digital hotplug on the PCH, and configure the DP short pulse
1724 * duration to 2ms (which is the minimum in the Display Port spec)
1725 *
1726 * This register is the same on all known PCH chips.
1727 */
1728
1729static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1730{
1731 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1732 u32 hotplug;
1733
1734 hotplug = I915_READ(PCH_PORT_HOTPLUG);
1735 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1736 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1737 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1738 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1739 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1740}
1741
f71d4af4 1742static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d
ZW		 1743{
1744 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1745 /* enable kind of interrupts always enabled */
013d5aa2
JB		 1746 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1747 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1ec14ad3 1748 u32 render_irqs;
2d7b8366 1749 u32 hotplug_mask;
036a4a7d 1750
1ec14ad3 1751 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 1752
1753 /* should always can generate irq */
1754 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3
CW		 1755 I915_WRITE(DEIMR, dev_priv->irq_mask);
1756 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
3143a2bf 1757 POSTING_READ(DEIER);
036a4a7d 1758
1ec14ad3 1759 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 1760
1761 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 1762 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 1763
1ec14ad3
CW		 1764 if (IS_GEN6(dev))
1765 render_irqs =
1766 GT_USER_INTERRUPT |
e2a1e2f0
BW		 1767 GEN6_BSD_USER_INTERRUPT |
1768 GEN6_BLITTER_USER_INTERRUPT;
1ec14ad3
CW		 1769 else
1770 render_irqs =
88f23b8f 1771 GT_USER_INTERRUPT |
c6df541c 1772 GT_PIPE_NOTIFY |
1ec14ad3
CW		 1773 GT_BSD_USER_INTERRUPT;
1774 I915_WRITE(GTIER, render_irqs);
3143a2bf 1775 POSTING_READ(GTIER);
036a4a7d 1776
2d7b8366 1777 if (HAS_PCH_CPT(dev)) {
9035a97a
CW		 1778 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1779 SDE_PORTB_HOTPLUG_CPT |
1780 SDE_PORTC_HOTPLUG_CPT |
1781 SDE_PORTD_HOTPLUG_CPT);
2d7b8366 1782 } else {
9035a97a
CW		 1783 hotplug_mask = (SDE_CRT_HOTPLUG |
1784 SDE_PORTB_HOTPLUG |
1785 SDE_PORTC_HOTPLUG |
1786 SDE_PORTD_HOTPLUG |
1787 SDE_AUX_MASK);
2d7b8366
YL		 1788 }
1789
1ec14ad3 1790 dev_priv->pch_irq_mask = ~hotplug_mask;
c650156a
ZW		 1791
1792 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1ec14ad3
CW		 1793 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1794 I915_WRITE(SDEIER, hotplug_mask);
3143a2bf 1795 POSTING_READ(SDEIER);
c650156a 1796
7fe0b973
KP		 1797 ironlake_enable_pch_hotplug(dev);
1798
f97108d1
JB		 1799 if (IS_IRONLAKE_M(dev)) {
1800 /* Clear & enable PCU event interrupts */
1801 I915_WRITE(DEIIR, DE_PCU_EVENT);
1802 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1803 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1804 }
1805
036a4a7d
ZW		 1806 return 0;
1807}
1808
f71d4af4 1809static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 1810{
1811 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1812 /* enable kind of interrupts always enabled */
b615b57a
CW		 1813 u32 display_mask =
1814 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
1815 DE_PLANEC_FLIP_DONE_IVB |
1816 DE_PLANEB_FLIP_DONE_IVB |
1817 DE_PLANEA_FLIP_DONE_IVB;
b1f14ad0
JB		 1818 u32 render_irqs;
1819 u32 hotplug_mask;
1820
b1f14ad0
JB		 1821 dev_priv->irq_mask = ~display_mask;
1822
1823 /* should always can generate irq */
1824 I915_WRITE(DEIIR, I915_READ(DEIIR));
1825 I915_WRITE(DEIMR, dev_priv->irq_mask);
b615b57a
CW		 1826 I915_WRITE(DEIER,
1827 display_mask |
1828 DE_PIPEC_VBLANK_IVB |
1829 DE_PIPEB_VBLANK_IVB |
1830 DE_PIPEA_VBLANK_IVB);
b1f14ad0
JB		 1831 POSTING_READ(DEIER);
1832
1833 dev_priv->gt_irq_mask = ~0;
1834
1835 I915_WRITE(GTIIR, I915_READ(GTIIR));
1836 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1837
e2a1e2f0
BW		 1838 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
1839 GEN6_BLITTER_USER_INTERRUPT;
b1f14ad0
JB		 1840 I915_WRITE(GTIER, render_irqs);
1841 POSTING_READ(GTIER);
1842
1843 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1844 SDE_PORTB_HOTPLUG_CPT |
1845 SDE_PORTC_HOTPLUG_CPT |
1846 SDE_PORTD_HOTPLUG_CPT);
1847 dev_priv->pch_irq_mask = ~hotplug_mask;
1848
1849 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1850 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1851 I915_WRITE(SDEIER, hotplug_mask);
1852 POSTING_READ(SDEIER);
1853
7fe0b973
KP		 1854 ironlake_enable_pch_hotplug(dev);
1855
b1f14ad0
JB		 1856 return 0;
1857}
1858
7e231dbe
JB		 1859static int valleyview_irq_postinstall(struct drm_device *dev)
1860{
1861 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1862 u32 render_irqs;
1863 u32 enable_mask;
1864 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1865 u16 msid;
1866
1867 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
1868 enable_mask |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1869 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1870
1871 dev_priv->irq_mask = ~enable_mask;
1872
7e231dbe
JB		 1873 dev_priv->pipestat[0] = 0;
1874 dev_priv->pipestat[1] = 0;
1875
7e231dbe
JB		 1876 /* Hack for broken MSIs on VLV */
1877 pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
1878 pci_read_config_word(dev->pdev, 0x98, &msid);
1879 msid &= 0xff; /* mask out delivery bits */
1880 msid |= (1<<14);
1881 pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
1882
1883 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
1884 I915_WRITE(VLV_IER, enable_mask);
1885 I915_WRITE(VLV_IIR, 0xffffffff);
1886 I915_WRITE(PIPESTAT(0), 0xffff);
1887 I915_WRITE(PIPESTAT(1), 0xffff);
1888 POSTING_READ(VLV_IER);
1889
1890 I915_WRITE(VLV_IIR, 0xffffffff);
1891 I915_WRITE(VLV_IIR, 0xffffffff);
1892
1893 render_irqs = GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
1894 GT_GEN6_BLT_CS_ERROR_INTERRUPT |
e2a1e2f0 1895 GT_GEN6_BLT_USER_INTERRUPT |
7e231dbe
JB		 1896 GT_GEN6_BSD_USER_INTERRUPT |
1897 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
1898 GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
1899 GT_PIPE_NOTIFY |
1900 GT_RENDER_CS_ERROR_INTERRUPT |
1901 GT_SYNC_STATUS |
1902 GT_USER_INTERRUPT;
1903
1904 dev_priv->gt_irq_mask = ~render_irqs;
1905
1906 I915_WRITE(GTIIR, I915_READ(GTIIR));
1907 I915_WRITE(GTIIR, I915_READ(GTIIR));
1908 I915_WRITE(GTIMR, 0);
1909 I915_WRITE(GTIER, render_irqs);
1910 POSTING_READ(GTIER);
1911
1912 /* ack & enable invalid PTE error interrupts */
1913#if 0 /* FIXME: add support to irq handler for checking these bits */
1914 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
1915 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
1916#endif
1917
1918 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1919#if 0 /* FIXME: check register definitions; some have moved */
1920 /* Note HDMI and DP share bits */
1921 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1922 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1923 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1924 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1925 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1926 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1927 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1928 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1929 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1930 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1931 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1932 hotplug_en |= CRT_HOTPLUG_INT_EN;
1933 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1934 }
1935#endif
1936
1937 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1938
1939 return 0;
1940}
1941
7e231dbe
JB		 1942static void valleyview_irq_uninstall(struct drm_device *dev)
1943{
1944 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1945 int pipe;
1946
1947 if (!dev_priv)
1948 return;
1949
7e231dbe
JB		 1950 for_each_pipe(pipe)
1951 I915_WRITE(PIPESTAT(pipe), 0xffff);
1952
1953 I915_WRITE(HWSTAM, 0xffffffff);
1954 I915_WRITE(PORT_HOTPLUG_EN, 0);
1955 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1956 for_each_pipe(pipe)
1957 I915_WRITE(PIPESTAT(pipe), 0xffff);
1958 I915_WRITE(VLV_IIR, 0xffffffff);
1959 I915_WRITE(VLV_IMR, 0xffffffff);
1960 I915_WRITE(VLV_IER, 0x0);
1961 POSTING_READ(VLV_IER);
1962}
1963
f71d4af4 1964static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 1965{
1966 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 1967
1968 if (!dev_priv)
1969 return;
1970
036a4a7d
ZW		 1971 I915_WRITE(HWSTAM, 0xffffffff);
1972
1973 I915_WRITE(DEIMR, 0xffffffff);
1974 I915_WRITE(DEIER, 0x0);
1975 I915_WRITE(DEIIR, I915_READ(DEIIR));
1976
1977 I915_WRITE(GTIMR, 0xffffffff);
1978 I915_WRITE(GTIER, 0x0);
1979 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f
KP		 1980
1981 I915_WRITE(SDEIMR, 0xffffffff);
1982 I915_WRITE(SDEIER, 0x0);
1983 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
036a4a7d
ZW		 1984}
1985
a266c7d5 1986static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 1987{
1988 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 1989 int pipe;
91e3738e 1990
a266c7d5 1991 atomic_set(&dev_priv->irq_received, 0);
5ca58282 1992
9db4a9c7
JB		 1993 for_each_pipe(pipe)
1994 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 1995 I915_WRITE16(IMR, 0xffff);
1996 I915_WRITE16(IER, 0x0);
1997 POSTING_READ16(IER);
c2798b19
CW		 1998}
1999
2000static int i8xx_irq_postinstall(struct drm_device *dev)
2001{
2002 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2003
c2798b19
CW		 2004 dev_priv->pipestat[0] = 0;
2005 dev_priv->pipestat[1] = 0;
2006
2007 I915_WRITE16(EMR,
2008 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2009
2010 /* Unmask the interrupts that we always want on. */
2011 dev_priv->irq_mask =
2012 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2013 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2014 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2015 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2016 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2017 I915_WRITE16(IMR, dev_priv->irq_mask);
2018
2019 I915_WRITE16(IER,
2020 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2021 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2022 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2023 I915_USER_INTERRUPT);
2024 POSTING_READ16(IER);
2025
2026 return 0;
2027}
2028
2029static irqreturn_t i8xx_irq_handler(DRM_IRQ_ARGS)
2030{
2031 struct drm_device *dev = (struct drm_device *) arg;
2032 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 2033 u16 iir, new_iir;
2034 u32 pipe_stats[2];
2035 unsigned long irqflags;
2036 int irq_received;
2037 int pipe;
2038 u16 flip_mask =
2039 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2040 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2041
2042 atomic_inc(&dev_priv->irq_received);
2043
2044 iir = I915_READ16(IIR);
2045 if (iir == 0)
2046 return IRQ_NONE;
2047
2048 while (iir & ~flip_mask) {
2049 /* Can't rely on pipestat interrupt bit in iir as it might
2050 * have been cleared after the pipestat interrupt was received.
2051 * It doesn't set the bit in iir again, but it still produces
2052 * interrupts (for non-MSI).
2053 */
2054 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2055 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2056 i915_handle_error(dev, false);
2057
2058 for_each_pipe(pipe) {
2059 int reg = PIPESTAT(pipe);
2060 pipe_stats[pipe] = I915_READ(reg);
2061
2062 /*
2063 * Clear the PIPE*STAT regs before the IIR
2064 */
2065 if (pipe_stats[pipe] & 0x8000ffff) {
2066 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2067 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2068 pipe_name(pipe));
2069 I915_WRITE(reg, pipe_stats[pipe]);
2070 irq_received = 1;
2071 }
2072 }
2073 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2074
2075 I915_WRITE16(IIR, iir & ~flip_mask);
2076 new_iir = I915_READ16(IIR); /* Flush posted writes */
2077
d05c617e 2078 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 2079
2080 if (iir & I915_USER_INTERRUPT)
2081 notify_ring(dev, &dev_priv->ring[RCS]);
2082
2083 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2084 drm_handle_vblank(dev, 0)) {
2085 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2086 intel_prepare_page_flip(dev, 0);
2087 intel_finish_page_flip(dev, 0);
2088 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2089 }
2090 }
2091
2092 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2093 drm_handle_vblank(dev, 1)) {
2094 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2095 intel_prepare_page_flip(dev, 1);
2096 intel_finish_page_flip(dev, 1);
2097 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2098 }
2099 }
2100
2101 iir = new_iir;
2102 }
2103
2104 return IRQ_HANDLED;
2105}
2106
2107static void i8xx_irq_uninstall(struct drm_device * dev)
2108{
2109 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2110 int pipe;
2111
c2798b19
CW		 2112 for_each_pipe(pipe) {
2113 /* Clear enable bits; then clear status bits */
2114 I915_WRITE(PIPESTAT(pipe), 0);
2115 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2116 }
2117 I915_WRITE16(IMR, 0xffff);
2118 I915_WRITE16(IER, 0x0);
2119 I915_WRITE16(IIR, I915_READ16(IIR));
2120}
2121
a266c7d5
CW		 2122static void i915_irq_preinstall(struct drm_device * dev)
2123{
2124 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2125 int pipe;
2126
2127 atomic_set(&dev_priv->irq_received, 0);
2128
2129 if (I915_HAS_HOTPLUG(dev)) {
2130 I915_WRITE(PORT_HOTPLUG_EN, 0);
2131 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2132 }
2133
00d98ebd 2134 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 2135 for_each_pipe(pipe)
2136 I915_WRITE(PIPESTAT(pipe), 0);
2137 I915_WRITE(IMR, 0xffffffff);
2138 I915_WRITE(IER, 0x0);
2139 POSTING_READ(IER);
2140}
2141
2142static int i915_irq_postinstall(struct drm_device *dev)
2143{
2144 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 2145 u32 enable_mask;
a266c7d5 2146
a266c7d5
CW		 2147 dev_priv->pipestat[0] = 0;
2148 dev_priv->pipestat[1] = 0;
2149
38bde180
CW		 2150 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2151
2152 /* Unmask the interrupts that we always want on. */
2153 dev_priv->irq_mask =
2154 ~(I915_ASLE_INTERRUPT |
2155 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2156 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2157 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2158 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2159 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2160
2161 enable_mask =
2162 I915_ASLE_INTERRUPT |
2163 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2164 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2165 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2166 I915_USER_INTERRUPT;
2167
a266c7d5
CW		 2168 if (I915_HAS_HOTPLUG(dev)) {
2169 /* Enable in IER... */
2170 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2171 /* and unmask in IMR */
2172 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2173 }
2174
a266c7d5
CW		 2175 I915_WRITE(IMR, dev_priv->irq_mask);
2176 I915_WRITE(IER, enable_mask);
2177 POSTING_READ(IER);
2178
2179 if (I915_HAS_HOTPLUG(dev)) {
2180 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2181
a266c7d5
CW		 2182 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2183 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2184 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2185 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2186 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2187 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2188 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2189 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2190 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2191 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2192 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2193 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5
CW		 2194 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2195 }
2196
2197 /* Ignore TV since it's buggy */
2198
2199 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2200 }
2201
2202 intel_opregion_enable_asle(dev);
2203
2204 return 0;
2205}
2206
2207static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
2208{
2209 struct drm_device *dev = (struct drm_device *) arg;
2210 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 2211 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 2212 unsigned long irqflags;
38bde180
CW		 2213 u32 flip_mask =
2214 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2215 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2216 u32 flip[2] = {
2217 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2218 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2219 };
2220 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 2221
2222 atomic_inc(&dev_priv->irq_received);
2223
2224 iir = I915_READ(IIR);
38bde180
CW		 2225 do {
2226 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 2227 bool blc_event = false;
a266c7d5
CW		 2228
2229 /* Can't rely on pipestat interrupt bit in iir as it might
2230 * have been cleared after the pipestat interrupt was received.
2231 * It doesn't set the bit in iir again, but it still produces
2232 * interrupts (for non-MSI).
2233 */
2234 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2235 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2236 i915_handle_error(dev, false);
2237
2238 for_each_pipe(pipe) {
2239 int reg = PIPESTAT(pipe);
2240 pipe_stats[pipe] = I915_READ(reg);
2241
38bde180 2242 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 2243 if (pipe_stats[pipe] & 0x8000ffff) {
2244 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2245 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2246 pipe_name(pipe));
2247 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 2248 irq_received = true;
a266c7d5
CW		 2249 }
2250 }
2251 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2252
2253 if (!irq_received)
2254 break;
2255
a266c7d5
CW		 2256 /* Consume port. Then clear IIR or we'll miss events */
2257 if ((I915_HAS_HOTPLUG(dev)) &&
2258 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2259 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2260
2261 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2262 hotplug_status);
2263 if (hotplug_status & dev_priv->hotplug_supported_mask)
2264 queue_work(dev_priv->wq,
2265 &dev_priv->hotplug_work);
2266
2267 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 2268 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 2269 }
2270
38bde180 2271 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2272 new_iir = I915_READ(IIR); /* Flush posted writes */
2273
a266c7d5
CW		 2274 if (iir & I915_USER_INTERRUPT)
2275 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 2276
a266c7d5 2277 for_each_pipe(pipe) {
38bde180
CW		 2278 int plane = pipe;
2279 if (IS_MOBILE(dev))
2280 plane = !plane;
8291ee90 2281 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2282 drm_handle_vblank(dev, pipe)) {
38bde180
CW		 2283 if (iir & flip[plane]) {
2284 intel_prepare_page_flip(dev, plane);
2285 intel_finish_page_flip(dev, pipe);
2286 flip_mask &= ~flip[plane];
2287 }
a266c7d5
CW		 2288 }
2289
2290 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2291 blc_event = true;
2292 }
2293
a266c7d5
CW		 2294 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2295 intel_opregion_asle_intr(dev);
2296
2297 /* With MSI, interrupts are only generated when iir
2298 * transitions from zero to nonzero. If another bit got
2299 * set while we were handling the existing iir bits, then
2300 * we would never get another interrupt.
2301 *
2302 * This is fine on non-MSI as well, as if we hit this path
2303 * we avoid exiting the interrupt handler only to generate
2304 * another one.
2305 *
2306 * Note that for MSI this could cause a stray interrupt report
2307 * if an interrupt landed in the time between writing IIR and
2308 * the posting read. This should be rare enough to never
2309 * trigger the 99% of 100,000 interrupts test for disabling
2310 * stray interrupts.
2311 */
38bde180 2312 ret = IRQ_HANDLED;
a266c7d5 2313 iir = new_iir;
38bde180 2314 } while (iir & ~flip_mask);
a266c7d5 2315
d05c617e 2316 i915_update_dri1_breadcrumb(dev);
8291ee90 2317
a266c7d5
CW		 2318 return ret;
2319}
2320
2321static void i915_irq_uninstall(struct drm_device * dev)
2322{
2323 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2324 int pipe;
2325
a266c7d5
CW		 2326 if (I915_HAS_HOTPLUG(dev)) {
2327 I915_WRITE(PORT_HOTPLUG_EN, 0);
2328 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2329 }
2330
00d98ebd 2331 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 2332 for_each_pipe(pipe) {
2333 /* Clear enable bits; then clear status bits */
a266c7d5 2334 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 2335 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2336 }
a266c7d5
CW		 2337 I915_WRITE(IMR, 0xffffffff);
2338 I915_WRITE(IER, 0x0);
2339
a266c7d5
CW		 2340 I915_WRITE(IIR, I915_READ(IIR));
2341}
2342
2343static void i965_irq_preinstall(struct drm_device * dev)
2344{
2345 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2346 int pipe;
2347
2348 atomic_set(&dev_priv->irq_received, 0);
2349
2350 if (I915_HAS_HOTPLUG(dev)) {
2351 I915_WRITE(PORT_HOTPLUG_EN, 0);
2352 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2353 }
2354
2355 I915_WRITE(HWSTAM, 0xeffe);
2356 for_each_pipe(pipe)
2357 I915_WRITE(PIPESTAT(pipe), 0);
2358 I915_WRITE(IMR, 0xffffffff);
2359 I915_WRITE(IER, 0x0);
2360 POSTING_READ(IER);
2361}
2362
2363static int i965_irq_postinstall(struct drm_device *dev)
2364{
2365 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
bbba0a97 2366 u32 enable_mask;
a266c7d5
CW		 2367 u32 error_mask;
2368
a266c7d5 2369 /* Unmask the interrupts that we always want on. */
bbba0a97
CW		 2370 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2371 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2372 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2373 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2374 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2375 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2376
2377 enable_mask = ~dev_priv->irq_mask;
2378 enable_mask |= I915_USER_INTERRUPT;
2379
2380 if (IS_G4X(dev))
2381 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5
CW		 2382
2383 dev_priv->pipestat[0] = 0;
2384 dev_priv->pipestat[1] = 0;
2385
2386 if (I915_HAS_HOTPLUG(dev)) {
2387 /* Enable in IER... */
2388 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2389 /* and unmask in IMR */
2390 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2391 }
2392
2393 /*
2394 * Enable some error detection, note the instruction error mask
2395 * bit is reserved, so we leave it masked.
2396 */
2397 if (IS_G4X(dev)) {
2398 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2399 GM45_ERROR_MEM_PRIV |
2400 GM45_ERROR_CP_PRIV |
2401 I915_ERROR_MEMORY_REFRESH);
2402 } else {
2403 error_mask = ~(I915_ERROR_PAGE_TABLE |
2404 I915_ERROR_MEMORY_REFRESH);
2405 }
2406 I915_WRITE(EMR, error_mask);
2407
2408 I915_WRITE(IMR, dev_priv->irq_mask);
2409 I915_WRITE(IER, enable_mask);
2410 POSTING_READ(IER);
2411
2412 if (I915_HAS_HOTPLUG(dev)) {
2413 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2414
2415 /* Note HDMI and DP share bits */
2416 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2417 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2418 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2419 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2420 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2421 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2422 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2423 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2424 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2425 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2426 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2427 hotplug_en |= CRT_HOTPLUG_INT_EN;
2428
2429 /* Programming the CRT detection parameters tends
2430 to generate a spurious hotplug event about three
2431 seconds later. So just do it once.
2432 */
2433 if (IS_G4X(dev))
2434 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2435 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2436 }
2437
2438 /* Ignore TV since it's buggy */
2439
2440 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2441 }
2442
2443 intel_opregion_enable_asle(dev);
2444
2445 return 0;
2446}
2447
2448static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS)
2449{
2450 struct drm_device *dev = (struct drm_device *) arg;
2451 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 2452 u32 iir, new_iir;
2453 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 2454 unsigned long irqflags;
2455 int irq_received;
2456 int ret = IRQ_NONE, pipe;
a266c7d5
CW		 2457
2458 atomic_inc(&dev_priv->irq_received);
2459
2460 iir = I915_READ(IIR);
2461
a266c7d5 2462 for (;;) {
2c8ba29f
CW		 2463 bool blc_event = false;
2464
a266c7d5
CW		 2465 irq_received = iir != 0;
2466
2467 /* Can't rely on pipestat interrupt bit in iir as it might
2468 * have been cleared after the pipestat interrupt was received.
2469 * It doesn't set the bit in iir again, but it still produces
2470 * interrupts (for non-MSI).
2471 */
2472 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2473 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2474 i915_handle_error(dev, false);
2475
2476 for_each_pipe(pipe) {
2477 int reg = PIPESTAT(pipe);
2478 pipe_stats[pipe] = I915_READ(reg);
2479
2480 /*
2481 * Clear the PIPE*STAT regs before the IIR
2482 */
2483 if (pipe_stats[pipe] & 0x8000ffff) {
2484 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2485 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2486 pipe_name(pipe));
2487 I915_WRITE(reg, pipe_stats[pipe]);
2488 irq_received = 1;
2489 }
2490 }
2491 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2492
2493 if (!irq_received)
2494 break;
2495
2496 ret = IRQ_HANDLED;
2497
2498 /* Consume port. Then clear IIR or we'll miss events */
2499 if ((I915_HAS_HOTPLUG(dev)) &&
2500 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2501 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2502
2503 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2504 hotplug_status);
2505 if (hotplug_status & dev_priv->hotplug_supported_mask)
2506 queue_work(dev_priv->wq,
2507 &dev_priv->hotplug_work);
2508
2509 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2510 I915_READ(PORT_HOTPLUG_STAT);
2511 }
2512
2513 I915_WRITE(IIR, iir);
2514 new_iir = I915_READ(IIR); /* Flush posted writes */
2515
a266c7d5
CW		 2516 if (iir & I915_USER_INTERRUPT)
2517 notify_ring(dev, &dev_priv->ring[RCS]);
2518 if (iir & I915_BSD_USER_INTERRUPT)
2519 notify_ring(dev, &dev_priv->ring[VCS]);
2520
4f7d1e79 2521 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
a266c7d5 2522 intel_prepare_page_flip(dev, 0);
a266c7d5 2523
4f7d1e79 2524 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
a266c7d5 2525 intel_prepare_page_flip(dev, 1);
a266c7d5
CW		 2526
2527 for_each_pipe(pipe) {
2c8ba29f 2528 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2529 drm_handle_vblank(dev, pipe)) {
4f7d1e79
CW		 2530 i915_pageflip_stall_check(dev, pipe);
2531 intel_finish_page_flip(dev, pipe);
a266c7d5
CW		 2532 }
2533
2534 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2535 blc_event = true;
2536 }
2537
2538
2539 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2540 intel_opregion_asle_intr(dev);
2541
2542 /* With MSI, interrupts are only generated when iir
2543 * transitions from zero to nonzero. If another bit got
2544 * set while we were handling the existing iir bits, then
2545 * we would never get another interrupt.
2546 *
2547 * This is fine on non-MSI as well, as if we hit this path
2548 * we avoid exiting the interrupt handler only to generate
2549 * another one.
2550 *
2551 * Note that for MSI this could cause a stray interrupt report
2552 * if an interrupt landed in the time between writing IIR and
2553 * the posting read. This should be rare enough to never
2554 * trigger the 99% of 100,000 interrupts test for disabling
2555 * stray interrupts.
2556 */
2557 iir = new_iir;
2558 }
2559
d05c617e 2560 i915_update_dri1_breadcrumb(dev);
2c8ba29f 2561
a266c7d5
CW		 2562 return ret;
2563}
2564
2565static void i965_irq_uninstall(struct drm_device * dev)
2566{
2567 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2568 int pipe;
2569
2570 if (!dev_priv)
2571 return;
2572
a266c7d5
CW		 2573 if (I915_HAS_HOTPLUG(dev)) {
2574 I915_WRITE(PORT_HOTPLUG_EN, 0);
2575 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2576 }
2577
2578 I915_WRITE(HWSTAM, 0xffffffff);
2579 for_each_pipe(pipe)
2580 I915_WRITE(PIPESTAT(pipe), 0);
2581 I915_WRITE(IMR, 0xffffffff);
2582 I915_WRITE(IER, 0x0);
2583
2584 for_each_pipe(pipe)
2585 I915_WRITE(PIPESTAT(pipe),
2586 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2587 I915_WRITE(IIR, I915_READ(IIR));
2588}
2589
f71d4af4
JB		 2590void intel_irq_init(struct drm_device *dev)
2591{
8b2e326d
CW		 2592 struct drm_i915_private *dev_priv = dev->dev_private;
2593
2594 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2595 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
2596 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
2597
f71d4af4
JB		 2598 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2599 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7e231dbe
JB		 2600 if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev) ||
2601 IS_VALLEYVIEW(dev)) {
f71d4af4
JB		 2602 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2603 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2604 }
2605
c3613de9
KP		 2606 if (drm_core_check_feature(dev, DRIVER_MODESET))
2607 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2608 else
2609 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 2610 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2611
7e231dbe
JB		 2612 if (IS_VALLEYVIEW(dev)) {
2613 dev->driver->irq_handler = valleyview_irq_handler;
2614 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2615 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2616 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2617 dev->driver->enable_vblank = valleyview_enable_vblank;
2618 dev->driver->disable_vblank = valleyview_disable_vblank;
2619 } else if (IS_IVYBRIDGE(dev)) {
f71d4af4
JB		 2620 /* Share pre & uninstall handlers with ILK/SNB */
2621 dev->driver->irq_handler = ivybridge_irq_handler;
2622 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2623 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2624 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2625 dev->driver->enable_vblank = ivybridge_enable_vblank;
2626 dev->driver->disable_vblank = ivybridge_disable_vblank;
2627 } else if (HAS_PCH_SPLIT(dev)) {
2628 dev->driver->irq_handler = ironlake_irq_handler;
2629 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2630 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2631 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2632 dev->driver->enable_vblank = ironlake_enable_vblank;
2633 dev->driver->disable_vblank = ironlake_disable_vblank;
2634 } else {
c2798b19
CW		 2635 if (INTEL_INFO(dev)->gen == 2) {
2636 dev->driver->irq_preinstall = i8xx_irq_preinstall;
2637 dev->driver->irq_postinstall = i8xx_irq_postinstall;
2638 dev->driver->irq_handler = i8xx_irq_handler;
2639 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5 2640 } else if (INTEL_INFO(dev)->gen == 3) {
4f7d1e79
CW		 2641 /* IIR "flip pending" means done if this bit is set */
2642 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
2643
a266c7d5
CW		 2644 dev->driver->irq_preinstall = i915_irq_preinstall;
2645 dev->driver->irq_postinstall = i915_irq_postinstall;
2646 dev->driver->irq_uninstall = i915_irq_uninstall;
2647 dev->driver->irq_handler = i915_irq_handler;
c2798b19 2648 } else {
a266c7d5
CW		 2649 dev->driver->irq_preinstall = i965_irq_preinstall;
2650 dev->driver->irq_postinstall = i965_irq_postinstall;
2651 dev->driver->irq_uninstall = i965_irq_uninstall;
2652 dev->driver->irq_handler = i965_irq_handler;
c2798b19 2653 }
f71d4af4
JB		 2654 dev->driver->enable_vblank = i915_enable_vblank;
2655 dev->driver->disable_vblank = i915_disable_vblank;
2656 }
2657}
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