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drm/i915: extract gmbus_wait_hw_status
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/i915_drm.h>
1da177e4 35#include "i915_drv.h"
1c5d22f7 36#include "i915_trace.h"
79e53945 37#include "intel_drv.h"
1da177e4 38
036a4a7d 39/* For display hotplug interrupt */
995b6762 40static void
f2b115e6 41ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 42{
1ec14ad3
CW		 43 if ((dev_priv->irq_mask & mask) != 0) {
44 dev_priv->irq_mask &= ~mask;
45 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 46 POSTING_READ(DEIMR);
036a4a7d
ZW		 47 }
48}
49
50static inline void
f2b115e6 51ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 52{
1ec14ad3
CW		 53 if ((dev_priv->irq_mask & mask) != mask) {
54 dev_priv->irq_mask |= mask;
55 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 56 POSTING_READ(DEIMR);
036a4a7d
ZW		 57 }
58}
59
7c463586
KP		 60void
61i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
62{
63 if ((dev_priv->pipestat[pipe] & mask) != mask) {
9db4a9c7 64 u32 reg = PIPESTAT(pipe);
7c463586
KP		 65
66 dev_priv->pipestat[pipe] |= mask;
67 /* Enable the interrupt, clear any pending status */
68 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
3143a2bf 69 POSTING_READ(reg);
7c463586
KP		 70 }
71}
72
73void
74i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
75{
76 if ((dev_priv->pipestat[pipe] & mask) != 0) {
9db4a9c7 77 u32 reg = PIPESTAT(pipe);
7c463586
KP		 78
79 dev_priv->pipestat[pipe] &= ~mask;
80 I915_WRITE(reg, dev_priv->pipestat[pipe]);
3143a2bf 81 POSTING_READ(reg);
7c463586
KP		 82 }
83}
84
01c66889
ZY		 85/**
86 * intel_enable_asle - enable ASLE interrupt for OpRegion
87 */
1ec14ad3 88void intel_enable_asle(struct drm_device *dev)
01c66889 89{
1ec14ad3
CW		 90 drm_i915_private_t *dev_priv = dev->dev_private;
91 unsigned long irqflags;
92
7e231dbe
JB		 93 /* FIXME: opregion/asle for VLV */
94 if (IS_VALLEYVIEW(dev))
95 return;
96
1ec14ad3 97 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 98
c619eed4 99 if (HAS_PCH_SPLIT(dev))
f2b115e6 100 ironlake_enable_display_irq(dev_priv, DE_GSE);
edcb49ca 101 else {
01c66889 102 i915_enable_pipestat(dev_priv, 1,
d874bcff 103 PIPE_LEGACY_BLC_EVENT_ENABLE);
a6c45cf0 104 if (INTEL_INFO(dev)->gen >= 4)
edcb49ca 105 i915_enable_pipestat(dev_priv, 0,
d874bcff 106 PIPE_LEGACY_BLC_EVENT_ENABLE);
edcb49ca 107 }
1ec14ad3
CW		 108
109 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 110}
111
0a3e67a4
JB		 112/**
113 * i915_pipe_enabled - check if a pipe is enabled
114 * @dev: DRM device
115 * @pipe: pipe to check
116 *
117 * Reading certain registers when the pipe is disabled can hang the chip.
118 * Use this routine to make sure the PLL is running and the pipe is active
119 * before reading such registers if unsure.
120 */
121static int
122i915_pipe_enabled(struct drm_device *dev, int pipe)
123{
124 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
702e7a56
PZ		 125 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
126 pipe);
127
128 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
0a3e67a4
JB		 129}
130
42f52ef8
KP		 131/* Called from drm generic code, passed a 'crtc', which
132 * we use as a pipe index
133 */
f71d4af4 134static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 135{
136 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
137 unsigned long high_frame;
138 unsigned long low_frame;
5eddb70b 139 u32 high1, high2, low;
0a3e67a4
JB		 140
141 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 142 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 143 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 144 return 0;
145 }
146
9db4a9c7
JB		 147 high_frame = PIPEFRAME(pipe);
148 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 149
0a3e67a4
JB		 150 /*
151 * High & low register fields aren't synchronized, so make sure
152 * we get a low value that's stable across two reads of the high
153 * register.
154 */
155 do {
5eddb70b
CW		 156 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
157 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
158 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 159 } while (high1 != high2);
160
5eddb70b
CW		 161 high1 >>= PIPE_FRAME_HIGH_SHIFT;
162 low >>= PIPE_FRAME_LOW_SHIFT;
163 return (high1 << 8) | low;
0a3e67a4
JB		 164}
165
f71d4af4 166static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 167{
168 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 169 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 170
171 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 172 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 173 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 174 return 0;
175 }
176
177 return I915_READ(reg);
178}
179
f71d4af4 180static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 181 int *vpos, int *hpos)
182{
183 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
184 u32 vbl = 0, position = 0;
185 int vbl_start, vbl_end, htotal, vtotal;
186 bool in_vbl = true;
187 int ret = 0;
fe2b8f9d
PZ		 188 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
189 pipe);
0af7e4df
MK		 190
191 if (!i915_pipe_enabled(dev, pipe)) {
192 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 193 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 194 return 0;
195 }
196
197 /* Get vtotal. */
fe2b8f9d 198 vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 199
200 if (INTEL_INFO(dev)->gen >= 4) {
201 /* No obvious pixelcount register. Only query vertical
202 * scanout position from Display scan line register.
203 */
204 position = I915_READ(PIPEDSL(pipe));
205
206 /* Decode into vertical scanout position. Don't have
207 * horizontal scanout position.
208 */
209 *vpos = position & 0x1fff;
210 *hpos = 0;
211 } else {
212 /* Have access to pixelcount since start of frame.
213 * We can split this into vertical and horizontal
214 * scanout position.
215 */
216 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
217
fe2b8f9d 218 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 219 *vpos = position / htotal;
220 *hpos = position - (*vpos * htotal);
221 }
222
223 /* Query vblank area. */
fe2b8f9d 224 vbl = I915_READ(VBLANK(cpu_transcoder));
0af7e4df
MK		 225
226 /* Test position against vblank region. */
227 vbl_start = vbl & 0x1fff;
228 vbl_end = (vbl >> 16) & 0x1fff;
229
230 if ((*vpos < vbl_start) || (*vpos > vbl_end))
231 in_vbl = false;
232
233 /* Inside "upper part" of vblank area? Apply corrective offset: */
234 if (in_vbl && (*vpos >= vbl_start))
235 *vpos = *vpos - vtotal;
236
237 /* Readouts valid? */
238 if (vbl > 0)
239 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
240
241 /* In vblank? */
242 if (in_vbl)
243 ret |= DRM_SCANOUTPOS_INVBL;
244
245 return ret;
246}
247
f71d4af4 248static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 249 int *max_error,
250 struct timeval *vblank_time,
251 unsigned flags)
252{
4041b853
CW		 253 struct drm_i915_private *dev_priv = dev->dev_private;
254 struct drm_crtc *crtc;
0af7e4df 255
4041b853
CW		 256 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
257 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 258 return -EINVAL;
259 }
260
261 /* Get drm_crtc to timestamp: */
4041b853
CW		 262 crtc = intel_get_crtc_for_pipe(dev, pipe);
263 if (crtc == NULL) {
264 DRM_ERROR("Invalid crtc %d\n", pipe);
265 return -EINVAL;
266 }
267
268 if (!crtc->enabled) {
269 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
270 return -EBUSY;
271 }
0af7e4df
MK		 272
273 /* Helper routine in DRM core does all the work: */
4041b853
CW		 274 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
275 vblank_time, flags,
276 crtc);
0af7e4df
MK		 277}
278
5ca58282
JB		 279/*
280 * Handle hotplug events outside the interrupt handler proper.
281 */
282static void i915_hotplug_work_func(struct work_struct *work)
283{
284 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
285 hotplug_work);
286 struct drm_device *dev = dev_priv->dev;
c31c4ba3 287 struct drm_mode_config *mode_config = &dev->mode_config;
4ef69c7a
CW		 288 struct intel_encoder *encoder;
289
52d7eced
DV		 290 /* HPD irq before everything is fully set up. */
291 if (!dev_priv->enable_hotplug_processing)
292 return;
293
a65e34c7 294 mutex_lock(&mode_config->mutex);
e67189ab
JB		 295 DRM_DEBUG_KMS("running encoder hotplug functions\n");
296
4ef69c7a
CW		 297 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
298 if (encoder->hot_plug)
299 encoder->hot_plug(encoder);
300
40ee3381
KP		 301 mutex_unlock(&mode_config->mutex);
302
5ca58282 303 /* Just fire off a uevent and let userspace tell us what to do */
eb1f8e4f 304 drm_helper_hpd_irq_event(dev);
5ca58282
JB		 305}
306
73edd18f 307static void ironlake_handle_rps_change(struct drm_device *dev)
f97108d1
JB		 308{
309 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 310 u32 busy_up, busy_down, max_avg, min_avg;
9270388e
DV		 311 u8 new_delay;
312 unsigned long flags;
313
314 spin_lock_irqsave(&mchdev_lock, flags);
f97108d1 315
73edd18f
DV		 316 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
317
20e4d407 318 new_delay = dev_priv->ips.cur_delay;
9270388e 319
7648fa99 320 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 321 busy_up = I915_READ(RCPREVBSYTUPAVG);
322 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 323 max_avg = I915_READ(RCBMAXAVG);
324 min_avg = I915_READ(RCBMINAVG);
325
326 /* Handle RCS change request from hw */
b5b72e89 327 if (busy_up > max_avg) {
20e4d407
DV		 328 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
329 new_delay = dev_priv->ips.cur_delay - 1;
330 if (new_delay < dev_priv->ips.max_delay)
331 new_delay = dev_priv->ips.max_delay;
b5b72e89 332 } else if (busy_down < min_avg) {
20e4d407
DV		 333 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
334 new_delay = dev_priv->ips.cur_delay + 1;
335 if (new_delay > dev_priv->ips.min_delay)
336 new_delay = dev_priv->ips.min_delay;
f97108d1
JB		 337 }
338
7648fa99 339 if (ironlake_set_drps(dev, new_delay))
20e4d407 340 dev_priv->ips.cur_delay = new_delay;
f97108d1 341
9270388e
DV		 342 spin_unlock_irqrestore(&mchdev_lock, flags);
343
f97108d1
JB		 344 return;
345}
346
549f7365
CW		 347static void notify_ring(struct drm_device *dev,
348 struct intel_ring_buffer *ring)
349{
350 struct drm_i915_private *dev_priv = dev->dev_private;
9862e600 351
475553de
CW		 352 if (ring->obj == NULL)
353 return;
354
b2eadbc8 355 trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
9862e600 356
549f7365 357 wake_up_all(&ring->irq_queue);
3e0dc6b0
BW		 358 if (i915_enable_hangcheck) {
359 dev_priv->hangcheck_count = 0;
360 mod_timer(&dev_priv->hangcheck_timer,
cecc21fe 361 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
3e0dc6b0 362 }
549f7365
CW		 363}
364
4912d041 365static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 366{
4912d041 367 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
c6a828d3 368 rps.work);
4912d041 369 u32 pm_iir, pm_imr;
7b9e0ae6 370 u8 new_delay;
4912d041 371
c6a828d3
DV		 372 spin_lock_irq(&dev_priv->rps.lock);
373 pm_iir = dev_priv->rps.pm_iir;
374 dev_priv->rps.pm_iir = 0;
4912d041 375 pm_imr = I915_READ(GEN6_PMIMR);
a9e2641d 376 I915_WRITE(GEN6_PMIMR, 0);
c6a828d3 377 spin_unlock_irq(&dev_priv->rps.lock);
3b8d8d91 378
7b9e0ae6 379 if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
3b8d8d91
JB		 380 return;
381
4fc688ce 382 mutex_lock(&dev_priv->rps.hw_lock);
7b9e0ae6
CW		 383
384 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
c6a828d3 385 new_delay = dev_priv->rps.cur_delay + 1;
7b9e0ae6 386 else
c6a828d3 387 new_delay = dev_priv->rps.cur_delay - 1;
3b8d8d91 388
79249636
BW		 389 /* sysfs frequency interfaces may have snuck in while servicing the
390 * interrupt
391 */
392 if (!(new_delay > dev_priv->rps.max_delay ||
393 new_delay < dev_priv->rps.min_delay)) {
394 gen6_set_rps(dev_priv->dev, new_delay);
395 }
3b8d8d91 396
4fc688ce 397 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91
JB		 398}
399
e3689190
BW		 400
401/**
402 * ivybridge_parity_work - Workqueue called when a parity error interrupt
403 * occurred.
404 * @work: workqueue struct
405 *
406 * Doesn't actually do anything except notify userspace. As a consequence of
407 * this event, userspace should try to remap the bad rows since statistically
408 * it is likely the same row is more likely to go bad again.
409 */
410static void ivybridge_parity_work(struct work_struct *work)
411{
412 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
a4da4fa4 413 l3_parity.error_work);
e3689190
BW		 414 u32 error_status, row, bank, subbank;
415 char *parity_event[5];
416 uint32_t misccpctl;
417 unsigned long flags;
418
419 /* We must turn off DOP level clock gating to access the L3 registers.
420 * In order to prevent a get/put style interface, acquire struct mutex
421 * any time we access those registers.
422 */
423 mutex_lock(&dev_priv->dev->struct_mutex);
424
425 misccpctl = I915_READ(GEN7_MISCCPCTL);
426 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
427 POSTING_READ(GEN7_MISCCPCTL);
428
429 error_status = I915_READ(GEN7_L3CDERRST1);
430 row = GEN7_PARITY_ERROR_ROW(error_status);
431 bank = GEN7_PARITY_ERROR_BANK(error_status);
432 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
433
434 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
435 GEN7_L3CDERRST1_ENABLE);
436 POSTING_READ(GEN7_L3CDERRST1);
437
438 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
439
440 spin_lock_irqsave(&dev_priv->irq_lock, flags);
441 dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
442 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
443 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
444
445 mutex_unlock(&dev_priv->dev->struct_mutex);
446
447 parity_event[0] = "L3_PARITY_ERROR=1";
448 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
449 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
450 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
451 parity_event[4] = NULL;
452
453 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
454 KOBJ_CHANGE, parity_event);
455
456 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
457 row, bank, subbank);
458
459 kfree(parity_event[3]);
460 kfree(parity_event[2]);
461 kfree(parity_event[1]);
462}
463
d2ba8470 464static void ivybridge_handle_parity_error(struct drm_device *dev)
e3689190
BW		 465{
466 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
467 unsigned long flags;
468
e1ef7cc2 469 if (!HAS_L3_GPU_CACHE(dev))
e3689190
BW		 470 return;
471
472 spin_lock_irqsave(&dev_priv->irq_lock, flags);
473 dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
474 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
475 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
476
a4da4fa4 477 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
e3689190
BW		 478}
479
e7b4c6b1
DV		 480static void snb_gt_irq_handler(struct drm_device *dev,
481 struct drm_i915_private *dev_priv,
482 u32 gt_iir)
483{
484
485 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
486 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
487 notify_ring(dev, &dev_priv->ring[RCS]);
488 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
489 notify_ring(dev, &dev_priv->ring[VCS]);
490 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
491 notify_ring(dev, &dev_priv->ring[BCS]);
492
493 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
494 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
495 GT_RENDER_CS_ERROR_INTERRUPT)) {
496 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
497 i915_handle_error(dev, false);
498 }
e3689190
BW		 499
500 if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
501 ivybridge_handle_parity_error(dev);
e7b4c6b1
DV		 502}
503
fc6826d1
CW		 504static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
505 u32 pm_iir)
506{
507 unsigned long flags;
508
509 /*
510 * IIR bits should never already be set because IMR should
511 * prevent an interrupt from being shown in IIR. The warning
512 * displays a case where we've unsafely cleared
c6a828d3 513 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
fc6826d1
CW		 514 * type is not a problem, it displays a problem in the logic.
515 *
c6a828d3 516 * The mask bit in IMR is cleared by dev_priv->rps.work.
fc6826d1
CW		 517 */
518
c6a828d3 519 spin_lock_irqsave(&dev_priv->rps.lock, flags);
c6a828d3
DV		 520 dev_priv->rps.pm_iir |= pm_iir;
521 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
fc6826d1 522 POSTING_READ(GEN6_PMIMR);
c6a828d3 523 spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
fc6826d1 524
c6a828d3 525 queue_work(dev_priv->wq, &dev_priv->rps.work);
fc6826d1
CW		 526}
527
ff1f525e 528static irqreturn_t valleyview_irq_handler(int irq, void *arg)
7e231dbe
JB		 529{
530 struct drm_device *dev = (struct drm_device *) arg;
531 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
532 u32 iir, gt_iir, pm_iir;
533 irqreturn_t ret = IRQ_NONE;
534 unsigned long irqflags;
535 int pipe;
536 u32 pipe_stats[I915_MAX_PIPES];
7e231dbe
JB		 537
538 atomic_inc(&dev_priv->irq_received);
539
7e231dbe
JB		 540 while (true) {
541 iir = I915_READ(VLV_IIR);
542 gt_iir = I915_READ(GTIIR);
543 pm_iir = I915_READ(GEN6_PMIIR);
544
545 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
546 goto out;
547
548 ret = IRQ_HANDLED;
549
e7b4c6b1 550 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 551
552 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
553 for_each_pipe(pipe) {
554 int reg = PIPESTAT(pipe);
555 pipe_stats[pipe] = I915_READ(reg);
556
557 /*
558 * Clear the PIPE*STAT regs before the IIR
559 */
560 if (pipe_stats[pipe] & 0x8000ffff) {
561 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
562 DRM_DEBUG_DRIVER("pipe %c underrun\n",
563 pipe_name(pipe));
564 I915_WRITE(reg, pipe_stats[pipe]);
565 }
566 }
567 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
568
31acc7f5
JB		 569 for_each_pipe(pipe) {
570 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
571 drm_handle_vblank(dev, pipe);
572
573 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
574 intel_prepare_page_flip(dev, pipe);
575 intel_finish_page_flip(dev, pipe);
576 }
577 }
578
7e231dbe
JB		 579 /* Consume port. Then clear IIR or we'll miss events */
580 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
581 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
582
583 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
584 hotplug_status);
585 if (hotplug_status & dev_priv->hotplug_supported_mask)
586 queue_work(dev_priv->wq,
587 &dev_priv->hotplug_work);
588
589 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
590 I915_READ(PORT_HOTPLUG_STAT);
591 }
592
fc6826d1
CW		 593 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
594 gen6_queue_rps_work(dev_priv, pm_iir);
7e231dbe
JB		 595
596 I915_WRITE(GTIIR, gt_iir);
597 I915_WRITE(GEN6_PMIIR, pm_iir);
598 I915_WRITE(VLV_IIR, iir);
599 }
600
601out:
602 return ret;
603}
604
23e81d69 605static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 606{
607 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 608 int pipe;
776ad806 609
76e43830
DV		 610 if (pch_iir & SDE_HOTPLUG_MASK)
611 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
612
776ad806
JB		 613 if (pch_iir & SDE_AUDIO_POWER_MASK)
614 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
615 (pch_iir & SDE_AUDIO_POWER_MASK) >>
616 SDE_AUDIO_POWER_SHIFT);
617
618 if (pch_iir & SDE_GMBUS)
619 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
620
621 if (pch_iir & SDE_AUDIO_HDCP_MASK)
622 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
623
624 if (pch_iir & SDE_AUDIO_TRANS_MASK)
625 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
626
627 if (pch_iir & SDE_POISON)
628 DRM_ERROR("PCH poison interrupt\n");
629
9db4a9c7
JB		 630 if (pch_iir & SDE_FDI_MASK)
631 for_each_pipe(pipe)
632 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
633 pipe_name(pipe),
634 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 635
636 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
637 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
638
639 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
640 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
641
642 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
643 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
644 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
645 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
646}
647
23e81d69
AJ		 648static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
649{
650 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
651 int pipe;
652
76e43830
DV		 653 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
654 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
655
23e81d69
AJ		 656 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
657 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
658 (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
659 SDE_AUDIO_POWER_SHIFT_CPT);
660
661 if (pch_iir & SDE_AUX_MASK_CPT)
662 DRM_DEBUG_DRIVER("AUX channel interrupt\n");
663
664 if (pch_iir & SDE_GMBUS_CPT)
665 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
666
667 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
668 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
669
670 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
671 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
672
673 if (pch_iir & SDE_FDI_MASK_CPT)
674 for_each_pipe(pipe)
675 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
676 pipe_name(pipe),
677 I915_READ(FDI_RX_IIR(pipe)));
678}
679
ff1f525e 680static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
b1f14ad0
JB		 681{
682 struct drm_device *dev = (struct drm_device *) arg;
683 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
0e43406b
CW		 684 u32 de_iir, gt_iir, de_ier, pm_iir;
685 irqreturn_t ret = IRQ_NONE;
686 int i;
b1f14ad0
JB		 687
688 atomic_inc(&dev_priv->irq_received);
689
690 /* disable master interrupt before clearing iir */
691 de_ier = I915_READ(DEIER);
692 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
b1f14ad0 693
b1f14ad0 694 gt_iir = I915_READ(GTIIR);
0e43406b
CW		 695 if (gt_iir) {
696 snb_gt_irq_handler(dev, dev_priv, gt_iir);
697 I915_WRITE(GTIIR, gt_iir);
698 ret = IRQ_HANDLED;
b1f14ad0
JB		 699 }
700
0e43406b
CW		 701 de_iir = I915_READ(DEIIR);
702 if (de_iir) {
703 if (de_iir & DE_GSE_IVB)
704 intel_opregion_gse_intr(dev);
705
706 for (i = 0; i < 3; i++) {
74d44445
DV		 707 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
708 drm_handle_vblank(dev, i);
0e43406b
CW		 709 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
710 intel_prepare_page_flip(dev, i);
711 intel_finish_page_flip_plane(dev, i);
712 }
0e43406b 713 }
b615b57a 714
0e43406b
CW		 715 /* check event from PCH */
716 if (de_iir & DE_PCH_EVENT_IVB) {
717 u32 pch_iir = I915_READ(SDEIIR);
b1f14ad0 718
23e81d69 719 cpt_irq_handler(dev, pch_iir);
b1f14ad0 720
0e43406b
CW		 721 /* clear PCH hotplug event before clear CPU irq */
722 I915_WRITE(SDEIIR, pch_iir);
723 }
b615b57a 724
0e43406b
CW		 725 I915_WRITE(DEIIR, de_iir);
726 ret = IRQ_HANDLED;
b1f14ad0
JB		 727 }
728
0e43406b
CW		 729 pm_iir = I915_READ(GEN6_PMIIR);
730 if (pm_iir) {
731 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
732 gen6_queue_rps_work(dev_priv, pm_iir);
733 I915_WRITE(GEN6_PMIIR, pm_iir);
734 ret = IRQ_HANDLED;
735 }
b1f14ad0 736
b1f14ad0
JB		 737 I915_WRITE(DEIER, de_ier);
738 POSTING_READ(DEIER);
739
740 return ret;
741}
742
e7b4c6b1
DV		 743static void ilk_gt_irq_handler(struct drm_device *dev,
744 struct drm_i915_private *dev_priv,
745 u32 gt_iir)
746{
747 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
748 notify_ring(dev, &dev_priv->ring[RCS]);
749 if (gt_iir & GT_BSD_USER_INTERRUPT)
750 notify_ring(dev, &dev_priv->ring[VCS]);
751}
752
ff1f525e 753static irqreturn_t ironlake_irq_handler(int irq, void *arg)
036a4a7d 754{
4697995b 755 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 756 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
757 int ret = IRQ_NONE;
acd15b6c 758 u32 de_iir, gt_iir, de_ier, pm_iir;
881f47b6 759
4697995b
JB		 760 atomic_inc(&dev_priv->irq_received);
761
2d109a84
ZN		 762 /* disable master interrupt before clearing iir */
763 de_ier = I915_READ(DEIER);
764 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 765 POSTING_READ(DEIER);
2d109a84 766
036a4a7d
ZW		 767 de_iir = I915_READ(DEIIR);
768 gt_iir = I915_READ(GTIIR);
3b8d8d91 769 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 770
acd15b6c 771 if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 772 goto done;
036a4a7d 773
c7c85101 774 ret = IRQ_HANDLED;
036a4a7d 775
e7b4c6b1
DV		 776 if (IS_GEN5(dev))
777 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
778 else
779 snb_gt_irq_handler(dev, dev_priv, gt_iir);
01c66889 780
c7c85101 781 if (de_iir & DE_GSE)
3b617967 782 intel_opregion_gse_intr(dev);
c650156a 783
74d44445
DV		 784 if (de_iir & DE_PIPEA_VBLANK)
785 drm_handle_vblank(dev, 0);
786
787 if (de_iir & DE_PIPEB_VBLANK)
788 drm_handle_vblank(dev, 1);
789
f072d2e7 790 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 791 intel_prepare_page_flip(dev, 0);
2bbda389 792 intel_finish_page_flip_plane(dev, 0);
f072d2e7 793 }
013d5aa2 794
f072d2e7 795 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 796 intel_prepare_page_flip(dev, 1);
2bbda389 797 intel_finish_page_flip_plane(dev, 1);
f072d2e7 798 }
013d5aa2 799
c7c85101 800 /* check event from PCH */
776ad806 801 if (de_iir & DE_PCH_EVENT) {
acd15b6c
DV		 802 u32 pch_iir = I915_READ(SDEIIR);
803
23e81d69
AJ		 804 if (HAS_PCH_CPT(dev))
805 cpt_irq_handler(dev, pch_iir);
806 else
807 ibx_irq_handler(dev, pch_iir);
acd15b6c
DV		 808
809 /* should clear PCH hotplug event before clear CPU irq */
810 I915_WRITE(SDEIIR, pch_iir);
776ad806 811 }
036a4a7d 812
73edd18f
DV		 813 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
814 ironlake_handle_rps_change(dev);
f97108d1 815
fc6826d1
CW		 816 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
817 gen6_queue_rps_work(dev_priv, pm_iir);
3b8d8d91 818
c7c85101
ZN		 819 I915_WRITE(GTIIR, gt_iir);
820 I915_WRITE(DEIIR, de_iir);
4912d041 821 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 822
823done:
2d109a84 824 I915_WRITE(DEIER, de_ier);
3143a2bf 825 POSTING_READ(DEIER);
2d109a84 826
036a4a7d
ZW		 827 return ret;
828}
829
8a905236
JB		 830/**
831 * i915_error_work_func - do process context error handling work
832 * @work: work struct
833 *
834 * Fire an error uevent so userspace can see that a hang or error
835 * was detected.
836 */
837static void i915_error_work_func(struct work_struct *work)
838{
839 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
840 error_work);
841 struct drm_device *dev = dev_priv->dev;
f316a42c
BG		 842 char *error_event[] = { "ERROR=1", NULL };
843 char *reset_event[] = { "RESET=1", NULL };
844 char *reset_done_event[] = { "ERROR=0", NULL };
8a905236 845
f316a42c
BG		 846 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
847
ba1234d1 848 if (atomic_read(&dev_priv->mm.wedged)) {
f803aa55
CW		 849 DRM_DEBUG_DRIVER("resetting chip\n");
850 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
d4b8bb2a 851 if (!i915_reset(dev)) {
f803aa55
CW		 852 atomic_set(&dev_priv->mm.wedged, 0);
853 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
f316a42c 854 }
30dbf0c0 855 complete_all(&dev_priv->error_completion);
f316a42c 856 }
8a905236
JB		 857}
858
85f9e50d
DV		 859/* NB: please notice the memset */
860static void i915_get_extra_instdone(struct drm_device *dev,
861 uint32_t *instdone)
862{
863 struct drm_i915_private *dev_priv = dev->dev_private;
864 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
865
866 switch(INTEL_INFO(dev)->gen) {
867 case 2:
868 case 3:
869 instdone[0] = I915_READ(INSTDONE);
870 break;
871 case 4:
872 case 5:
873 case 6:
874 instdone[0] = I915_READ(INSTDONE_I965);
875 instdone[1] = I915_READ(INSTDONE1);
876 break;
877 default:
878 WARN_ONCE(1, "Unsupported platform\n");
879 case 7:
880 instdone[0] = I915_READ(GEN7_INSTDONE_1);
881 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
882 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
883 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
884 break;
885 }
886}
887
3bd3c932 888#ifdef CONFIG_DEBUG_FS
9df30794 889static struct drm_i915_error_object *
bcfb2e28 890i915_error_object_create(struct drm_i915_private *dev_priv,
05394f39 891 struct drm_i915_gem_object *src)
9df30794
CW		 892{
893 struct drm_i915_error_object *dst;
9da3da66 894 int i, count;
e56660dd 895 u32 reloc_offset;
9df30794 896
05394f39 897 if (src == NULL || src->pages == NULL)
9df30794
CW		 898 return NULL;
899
9da3da66 900 count = src->base.size / PAGE_SIZE;
9df30794 901
9da3da66 902 dst = kmalloc(sizeof(*dst) + count * sizeof(u32 *), GFP_ATOMIC);
9df30794
CW		 903 if (dst == NULL)
904 return NULL;
905
05394f39 906 reloc_offset = src->gtt_offset;
9da3da66 907 for (i = 0; i < count; i++) {
788885ae 908 unsigned long flags;
e56660dd 909 void *d;
788885ae 910
e56660dd 911 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 912 if (d == NULL)
913 goto unwind;
e56660dd 914
788885ae 915 local_irq_save(flags);
74898d7e
DV		 916 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
917 src->has_global_gtt_mapping) {
172975aa
CW		 918 void __iomem *s;
919
920 /* Simply ignore tiling or any overlapping fence.
921 * It's part of the error state, and this hopefully
922 * captures what the GPU read.
923 */
924
925 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
926 reloc_offset);
927 memcpy_fromio(d, s, PAGE_SIZE);
928 io_mapping_unmap_atomic(s);
960e3564
CW		 929 } else if (src->stolen) {
930 unsigned long offset;
931
932 offset = dev_priv->mm.stolen_base;
933 offset += src->stolen->start;
934 offset += i << PAGE_SHIFT;
935
1a240d4d 936 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
172975aa 937 } else {
9da3da66 938 struct page *page;
172975aa
CW		 939 void *s;
940
9da3da66 941 page = i915_gem_object_get_page(src, i);
172975aa 942
9da3da66
CW		 943 drm_clflush_pages(&page, 1);
944
945 s = kmap_atomic(page);
172975aa
CW		 946 memcpy(d, s, PAGE_SIZE);
947 kunmap_atomic(s);
948
9da3da66 949 drm_clflush_pages(&page, 1);
172975aa 950 }
788885ae 951 local_irq_restore(flags);
e56660dd 952
9da3da66 953 dst->pages[i] = d;
e56660dd
CW		 954
955 reloc_offset += PAGE_SIZE;
9df30794 956 }
9da3da66 957 dst->page_count = count;
05394f39 958 dst->gtt_offset = src->gtt_offset;
9df30794
CW		 959
960 return dst;
961
962unwind:
9da3da66
CW		 963 while (i--)
964 kfree(dst->pages[i]);
9df30794
CW		 965 kfree(dst);
966 return NULL;
967}
968
969static void
970i915_error_object_free(struct drm_i915_error_object *obj)
971{
972 int page;
973
974 if (obj == NULL)
975 return;
976
977 for (page = 0; page < obj->page_count; page++)
978 kfree(obj->pages[page]);
979
980 kfree(obj);
981}
982
742cbee8
DV		 983void
984i915_error_state_free(struct kref *error_ref)
9df30794 985{
742cbee8
DV		 986 struct drm_i915_error_state *error = container_of(error_ref,
987 typeof(*error), ref);
e2f973d5
CW		 988 int i;
989
52d39a21
CW		 990 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
991 i915_error_object_free(error->ring[i].batchbuffer);
992 i915_error_object_free(error->ring[i].ringbuffer);
993 kfree(error->ring[i].requests);
994 }
e2f973d5 995
9df30794 996 kfree(error->active_bo);
6ef3d427 997 kfree(error->overlay);
9df30794
CW		 998 kfree(error);
999}
1b50247a
CW		 1000static void capture_bo(struct drm_i915_error_buffer *err,
1001 struct drm_i915_gem_object *obj)
1002{
1003 err->size = obj->base.size;
1004 err->name = obj->base.name;
0201f1ec
CW		 1005 err->rseqno = obj->last_read_seqno;
1006 err->wseqno = obj->last_write_seqno;
1b50247a
CW		 1007 err->gtt_offset = obj->gtt_offset;
1008 err->read_domains = obj->base.read_domains;
1009 err->write_domain = obj->base.write_domain;
1010 err->fence_reg = obj->fence_reg;
1011 err->pinned = 0;
1012 if (obj->pin_count > 0)
1013 err->pinned = 1;
1014 if (obj->user_pin_count > 0)
1015 err->pinned = -1;
1016 err->tiling = obj->tiling_mode;
1017 err->dirty = obj->dirty;
1018 err->purgeable = obj->madv != I915_MADV_WILLNEED;
1019 err->ring = obj->ring ? obj->ring->id : -1;
1020 err->cache_level = obj->cache_level;
1021}
9df30794 1022
1b50247a
CW		 1023static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1024 int count, struct list_head *head)
c724e8a9
CW		 1025{
1026 struct drm_i915_gem_object *obj;
1027 int i = 0;
1028
1029 list_for_each_entry(obj, head, mm_list) {
1b50247a 1030 capture_bo(err++, obj);
c724e8a9
CW		 1031 if (++i == count)
1032 break;
1b50247a
CW		 1033 }
1034
1035 return i;
1036}
1037
1038static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1039 int count, struct list_head *head)
1040{
1041 struct drm_i915_gem_object *obj;
1042 int i = 0;
1043
1044 list_for_each_entry(obj, head, gtt_list) {
1045 if (obj->pin_count == 0)
1046 continue;
c724e8a9 1047
1b50247a
CW		 1048 capture_bo(err++, obj);
1049 if (++i == count)
1050 break;
c724e8a9
CW		 1051 }
1052
1053 return i;
1054}
1055
748ebc60
CW		 1056static void i915_gem_record_fences(struct drm_device *dev,
1057 struct drm_i915_error_state *error)
1058{
1059 struct drm_i915_private *dev_priv = dev->dev_private;
1060 int i;
1061
1062 /* Fences */
1063 switch (INTEL_INFO(dev)->gen) {
775d17b6 1064 case 7:
748ebc60
CW		 1065 case 6:
1066 for (i = 0; i < 16; i++)
1067 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1068 break;
1069 case 5:
1070 case 4:
1071 for (i = 0; i < 16; i++)
1072 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1073 break;
1074 case 3:
1075 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1076 for (i = 0; i < 8; i++)
1077 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1078 case 2:
1079 for (i = 0; i < 8; i++)
1080 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1081 break;
1082
1083 }
1084}
1085
bcfb2e28
CW		 1086static struct drm_i915_error_object *
1087i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1088 struct intel_ring_buffer *ring)
1089{
1090 struct drm_i915_gem_object *obj;
1091 u32 seqno;
1092
1093 if (!ring->get_seqno)
1094 return NULL;
1095
b2eadbc8 1096 seqno = ring->get_seqno(ring, false);
bcfb2e28
CW		 1097 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1098 if (obj->ring != ring)
1099 continue;
1100
0201f1ec 1101 if (i915_seqno_passed(seqno, obj->last_read_seqno))
bcfb2e28
CW		 1102 continue;
1103
1104 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1105 continue;
1106
1107 /* We need to copy these to an anonymous buffer as the simplest
1108 * method to avoid being overwritten by userspace.
1109 */
1110 return i915_error_object_create(dev_priv, obj);
1111 }
1112
1113 return NULL;
1114}
1115
d27b1e0e
DV		 1116static void i915_record_ring_state(struct drm_device *dev,
1117 struct drm_i915_error_state *error,
1118 struct intel_ring_buffer *ring)
1119{
1120 struct drm_i915_private *dev_priv = dev->dev_private;
1121
33f3f518 1122 if (INTEL_INFO(dev)->gen >= 6) {
12f55818 1123 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
33f3f518 1124 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
7e3b8737
DV		 1125 error->semaphore_mboxes[ring->id][0]
1126 = I915_READ(RING_SYNC_0(ring->mmio_base));
1127 error->semaphore_mboxes[ring->id][1]
1128 = I915_READ(RING_SYNC_1(ring->mmio_base));
df2b23d9
CW		 1129 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
1130 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
33f3f518 1131 }
c1cd90ed 1132
d27b1e0e 1133 if (INTEL_INFO(dev)->gen >= 4) {
9d2f41fa 1134 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
d27b1e0e
DV		 1135 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1136 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1137 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
c1cd90ed 1138 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
050ee91f 1139 if (ring->id == RCS)
d27b1e0e 1140 error->bbaddr = I915_READ64(BB_ADDR);
d27b1e0e 1141 } else {
9d2f41fa 1142 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
d27b1e0e
DV		 1143 error->ipeir[ring->id] = I915_READ(IPEIR);
1144 error->ipehr[ring->id] = I915_READ(IPEHR);
1145 error->instdone[ring->id] = I915_READ(INSTDONE);
d27b1e0e
DV		 1146 }
1147
9574b3fe 1148 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
c1cd90ed 1149 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
b2eadbc8 1150 error->seqno[ring->id] = ring->get_seqno(ring, false);
d27b1e0e 1151 error->acthd[ring->id] = intel_ring_get_active_head(ring);
c1cd90ed
DV		 1152 error->head[ring->id] = I915_READ_HEAD(ring);
1153 error->tail[ring->id] = I915_READ_TAIL(ring);
7e3b8737
DV		 1154
1155 error->cpu_ring_head[ring->id] = ring->head;
1156 error->cpu_ring_tail[ring->id] = ring->tail;
d27b1e0e
DV		 1157}
1158
52d39a21
CW		 1159static void i915_gem_record_rings(struct drm_device *dev,
1160 struct drm_i915_error_state *error)
1161{
1162 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 1163 struct intel_ring_buffer *ring;
52d39a21
CW		 1164 struct drm_i915_gem_request *request;
1165 int i, count;
1166
b4519513 1167 for_each_ring(ring, dev_priv, i) {
52d39a21
CW		 1168 i915_record_ring_state(dev, error, ring);
1169
1170 error->ring[i].batchbuffer =
1171 i915_error_first_batchbuffer(dev_priv, ring);
1172
1173 error->ring[i].ringbuffer =
1174 i915_error_object_create(dev_priv, ring->obj);
1175
1176 count = 0;
1177 list_for_each_entry(request, &ring->request_list, list)
1178 count++;
1179
1180 error->ring[i].num_requests = count;
1181 error->ring[i].requests =
1182 kmalloc(count*sizeof(struct drm_i915_error_request),
1183 GFP_ATOMIC);
1184 if (error->ring[i].requests == NULL) {
1185 error->ring[i].num_requests = 0;
1186 continue;
1187 }
1188
1189 count = 0;
1190 list_for_each_entry(request, &ring->request_list, list) {
1191 struct drm_i915_error_request *erq;
1192
1193 erq = &error->ring[i].requests[count++];
1194 erq->seqno = request->seqno;
1195 erq->jiffies = request->emitted_jiffies;
ee4f42b1 1196 erq->tail = request->tail;
52d39a21
CW		 1197 }
1198 }
1199}
1200
8a905236
JB		 1201/**
1202 * i915_capture_error_state - capture an error record for later analysis
1203 * @dev: drm device
1204 *
1205 * Should be called when an error is detected (either a hang or an error
1206 * interrupt) to capture error state from the time of the error. Fills
1207 * out a structure which becomes available in debugfs for user level tools
1208 * to pick up.
1209 */
63eeaf38
JB		 1210static void i915_capture_error_state(struct drm_device *dev)
1211{
1212 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1213 struct drm_i915_gem_object *obj;
63eeaf38
JB		 1214 struct drm_i915_error_state *error;
1215 unsigned long flags;
9db4a9c7 1216 int i, pipe;
63eeaf38
JB		 1217
1218 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1219 error = dev_priv->first_error;
1220 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1221 if (error)
1222 return;
63eeaf38 1223
9db4a9c7 1224 /* Account for pipe specific data like PIPE*STAT */
33f3f518 1225 error = kzalloc(sizeof(*error), GFP_ATOMIC);
63eeaf38 1226 if (!error) {
9df30794
CW		 1227 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1228 return;
63eeaf38
JB		 1229 }
1230
b6f7833b
CW		 1231 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1232 dev->primary->index);
2fa772f3 1233
742cbee8 1234 kref_init(&error->ref);
63eeaf38
JB		 1235 error->eir = I915_READ(EIR);
1236 error->pgtbl_er = I915_READ(PGTBL_ER);
b9a3906b 1237 error->ccid = I915_READ(CCID);
be998e2e
BW		 1238
1239 if (HAS_PCH_SPLIT(dev))
1240 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1241 else if (IS_VALLEYVIEW(dev))
1242 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1243 else if (IS_GEN2(dev))
1244 error->ier = I915_READ16(IER);
1245 else
1246 error->ier = I915_READ(IER);
1247
9db4a9c7
JB		 1248 for_each_pipe(pipe)
1249 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
d27b1e0e 1250
33f3f518 1251 if (INTEL_INFO(dev)->gen >= 6) {
f406839f 1252 error->error = I915_READ(ERROR_GEN6);
33f3f518
DV		 1253 error->done_reg = I915_READ(DONE_REG);
1254 }
d27b1e0e 1255
71e172e8
BW		 1256 if (INTEL_INFO(dev)->gen == 7)
1257 error->err_int = I915_READ(GEN7_ERR_INT);
1258
050ee91f
BW		 1259 i915_get_extra_instdone(dev, error->extra_instdone);
1260
748ebc60 1261 i915_gem_record_fences(dev, error);
52d39a21 1262 i915_gem_record_rings(dev, error);
9df30794 1263
c724e8a9 1264 /* Record buffers on the active and pinned lists. */
9df30794 1265 error->active_bo = NULL;
c724e8a9 1266 error->pinned_bo = NULL;
9df30794 1267
bcfb2e28
CW		 1268 i = 0;
1269 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1270 i++;
1271 error->active_bo_count = i;
6c085a72 1272 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
1b50247a
CW		 1273 if (obj->pin_count)
1274 i++;
bcfb2e28 1275 error->pinned_bo_count = i - error->active_bo_count;
c724e8a9 1276
8e934dbf
CW		 1277 error->active_bo = NULL;
1278 error->pinned_bo = NULL;
bcfb2e28
CW		 1279 if (i) {
1280 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
9df30794 1281 GFP_ATOMIC);
c724e8a9
CW		 1282 if (error->active_bo)
1283 error->pinned_bo =
1284 error->active_bo + error->active_bo_count;
9df30794
CW		 1285 }
1286
c724e8a9
CW		 1287 if (error->active_bo)
1288 error->active_bo_count =
1b50247a
CW		 1289 capture_active_bo(error->active_bo,
1290 error->active_bo_count,
1291 &dev_priv->mm.active_list);
c724e8a9
CW		 1292
1293 if (error->pinned_bo)
1294 error->pinned_bo_count =
1b50247a
CW		 1295 capture_pinned_bo(error->pinned_bo,
1296 error->pinned_bo_count,
6c085a72 1297 &dev_priv->mm.bound_list);
c724e8a9 1298
9df30794
CW		 1299 do_gettimeofday(&error->time);
1300
6ef3d427 1301 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 1302 error->display = intel_display_capture_error_state(dev);
6ef3d427 1303
9df30794
CW		 1304 spin_lock_irqsave(&dev_priv->error_lock, flags);
1305 if (dev_priv->first_error == NULL) {
1306 dev_priv->first_error = error;
1307 error = NULL;
1308 }
63eeaf38 1309 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1310
1311 if (error)
742cbee8 1312 i915_error_state_free(&error->ref);
9df30794
CW		 1313}
1314
1315void i915_destroy_error_state(struct drm_device *dev)
1316{
1317 struct drm_i915_private *dev_priv = dev->dev_private;
1318 struct drm_i915_error_state *error;
6dc0e816 1319 unsigned long flags;
9df30794 1320
6dc0e816 1321 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1322 error = dev_priv->first_error;
1323 dev_priv->first_error = NULL;
6dc0e816 1324 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1325
1326 if (error)
742cbee8 1327 kref_put(&error->ref, i915_error_state_free);
63eeaf38 1328}
3bd3c932
CW		 1329#else
1330#define i915_capture_error_state(x)
1331#endif
63eeaf38 1332
35aed2e6 1333static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1334{
1335 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 1336 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 1337 u32 eir = I915_READ(EIR);
050ee91f 1338 int pipe, i;
8a905236 1339
35aed2e6
CW		 1340 if (!eir)
1341 return;
8a905236 1342
a70491cc 1343 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 1344
bd9854f9
BW		 1345 i915_get_extra_instdone(dev, instdone);
1346
8a905236
JB		 1347 if (IS_G4X(dev)) {
1348 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1349 u32 ipeir = I915_READ(IPEIR_I965);
1350
a70491cc
JP		 1351 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1352 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 1353 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1354 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 1355 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1356 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1357 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1358 POSTING_READ(IPEIR_I965);
8a905236
JB		 1359 }
1360 if (eir & GM45_ERROR_PAGE_TABLE) {
1361 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1362 pr_err("page table error\n");
1363 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1364 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1365 POSTING_READ(PGTBL_ER);
8a905236
JB		 1366 }
1367 }
1368
a6c45cf0 1369 if (!IS_GEN2(dev)) {
8a905236
JB		 1370 if (eir & I915_ERROR_PAGE_TABLE) {
1371 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1372 pr_err("page table error\n");
1373 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1374 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1375 POSTING_READ(PGTBL_ER);
8a905236
JB		 1376 }
1377 }
1378
1379 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 1380 pr_err("memory refresh error:\n");
9db4a9c7 1381 for_each_pipe(pipe)
a70491cc 1382 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 1383 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 1384 /* pipestat has already been acked */
1385 }
1386 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 1387 pr_err("instruction error\n");
1388 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 1389 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1390 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 1391 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 1392 u32 ipeir = I915_READ(IPEIR);
1393
a70491cc
JP		 1394 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1395 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 1396 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 1397 I915_WRITE(IPEIR, ipeir);
3143a2bf 1398 POSTING_READ(IPEIR);
8a905236
JB		 1399 } else {
1400 u32 ipeir = I915_READ(IPEIR_I965);
1401
a70491cc
JP		 1402 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1403 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 1404 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1405 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1406 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1407 POSTING_READ(IPEIR_I965);
8a905236
JB		 1408 }
1409 }
1410
1411 I915_WRITE(EIR, eir);
3143a2bf 1412 POSTING_READ(EIR);
8a905236
JB		 1413 eir = I915_READ(EIR);
1414 if (eir) {
1415 /*
1416 * some errors might have become stuck,
1417 * mask them.
1418 */
1419 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1420 I915_WRITE(EMR, I915_READ(EMR) | eir);
1421 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1422 }
35aed2e6
CW		 1423}
1424
1425/**
1426 * i915_handle_error - handle an error interrupt
1427 * @dev: drm device
1428 *
1429 * Do some basic checking of regsiter state at error interrupt time and
1430 * dump it to the syslog. Also call i915_capture_error_state() to make
1431 * sure we get a record and make it available in debugfs. Fire a uevent
1432 * so userspace knows something bad happened (should trigger collection
1433 * of a ring dump etc.).
1434 */
527f9e90 1435void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 1436{
1437 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513
CW		 1438 struct intel_ring_buffer *ring;
1439 int i;
35aed2e6
CW		 1440
1441 i915_capture_error_state(dev);
1442 i915_report_and_clear_eir(dev);
8a905236 1443
ba1234d1 1444 if (wedged) {
30dbf0c0 1445 INIT_COMPLETION(dev_priv->error_completion);
ba1234d1
BG		 1446 atomic_set(&dev_priv->mm.wedged, 1);
1447
11ed50ec
BG		 1448 /*
1449 * Wakeup waiting processes so they don't hang
1450 */
b4519513
CW		 1451 for_each_ring(ring, dev_priv, i)
1452 wake_up_all(&ring->irq_queue);
11ed50ec
BG		 1453 }
1454
9c9fe1f8 1455 queue_work(dev_priv->wq, &dev_priv->error_work);
8a905236
JB		 1456}
1457
4e5359cd
SF		 1458static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1459{
1460 drm_i915_private_t *dev_priv = dev->dev_private;
1461 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1462 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 1463 struct drm_i915_gem_object *obj;
4e5359cd
SF		 1464 struct intel_unpin_work *work;
1465 unsigned long flags;
1466 bool stall_detected;
1467
1468 /* Ignore early vblank irqs */
1469 if (intel_crtc == NULL)
1470 return;
1471
1472 spin_lock_irqsave(&dev->event_lock, flags);
1473 work = intel_crtc->unpin_work;
1474
1475 if (work == NULL || work->pending || !work->enable_stall_check) {
1476 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1477 spin_unlock_irqrestore(&dev->event_lock, flags);
1478 return;
1479 }
1480
1481 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 1482 obj = work->pending_flip_obj;
a6c45cf0 1483 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 1484 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545
AR		 1485 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1486 obj->gtt_offset;
4e5359cd 1487 } else {
9db4a9c7 1488 int dspaddr = DSPADDR(intel_crtc->plane);
05394f39 1489 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
01f2c773 1490 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 1491 crtc->x * crtc->fb->bits_per_pixel/8);
1492 }
1493
1494 spin_unlock_irqrestore(&dev->event_lock, flags);
1495
1496 if (stall_detected) {
1497 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1498 intel_prepare_page_flip(dev, intel_crtc->plane);
1499 }
1500}
1501
42f52ef8
KP		 1502/* Called from drm generic code, passed 'crtc' which
1503 * we use as a pipe index
1504 */
f71d4af4 1505static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1506{
1507 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1508 unsigned long irqflags;
71e0ffa5 1509
5eddb70b 1510 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 1511 return -EINVAL;
0a3e67a4 1512
1ec14ad3 1513 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 1514 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 1515 i915_enable_pipestat(dev_priv, pipe,
1516 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 1517 else
7c463586
KP		 1518 i915_enable_pipestat(dev_priv, pipe,
1519 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 1520
1521 /* maintain vblank delivery even in deep C-states */
1522 if (dev_priv->info->gen == 3)
6b26c86d 1523 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 1524 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 1525
0a3e67a4
JB		 1526 return 0;
1527}
1528
f71d4af4 1529static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1530{
1531 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1532 unsigned long irqflags;
1533
1534 if (!i915_pipe_enabled(dev, pipe))
1535 return -EINVAL;
1536
1537 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1538 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1539 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
f796cf8f
JB		 1540 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1541
1542 return 0;
1543}
1544
f71d4af4 1545static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1546{
1547 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1548 unsigned long irqflags;
1549
1550 if (!i915_pipe_enabled(dev, pipe))
1551 return -EINVAL;
1552
1553 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1554 ironlake_enable_display_irq(dev_priv,
1555 DE_PIPEA_VBLANK_IVB << (5 * pipe));
b1f14ad0
JB		 1556 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1557
1558 return 0;
1559}
1560
7e231dbe
JB		 1561static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1562{
1563 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1564 unsigned long irqflags;
31acc7f5 1565 u32 imr;
7e231dbe
JB		 1566
1567 if (!i915_pipe_enabled(dev, pipe))
1568 return -EINVAL;
1569
1570 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7e231dbe 1571 imr = I915_READ(VLV_IMR);
31acc7f5 1572 if (pipe == 0)
7e231dbe 1573 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1574 else
7e231dbe 1575 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1576 I915_WRITE(VLV_IMR, imr);
31acc7f5
JB		 1577 i915_enable_pipestat(dev_priv, pipe,
1578 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe
JB		 1579 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1580
1581 return 0;
1582}
1583
42f52ef8
KP		 1584/* Called from drm generic code, passed 'crtc' which
1585 * we use as a pipe index
1586 */
f71d4af4 1587static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1588{
1589 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1590 unsigned long irqflags;
0a3e67a4 1591
1ec14ad3 1592 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 1593 if (dev_priv->info->gen == 3)
6b26c86d 1594 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 1595
f796cf8f
JB		 1596 i915_disable_pipestat(dev_priv, pipe,
1597 PIPE_VBLANK_INTERRUPT_ENABLE |
1598 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1599 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1600}
1601
f71d4af4 1602static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1603{
1604 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1605 unsigned long irqflags;
1606
1607 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1608 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1609 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1ec14ad3 1610 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 1611}
1612
f71d4af4 1613static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1614{
1615 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1616 unsigned long irqflags;
1617
1618 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1619 ironlake_disable_display_irq(dev_priv,
1620 DE_PIPEA_VBLANK_IVB << (pipe * 5));
b1f14ad0
JB		 1621 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1622}
1623
7e231dbe
JB		 1624static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1625{
1626 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1627 unsigned long irqflags;
31acc7f5 1628 u32 imr;
7e231dbe
JB		 1629
1630 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5
JB		 1631 i915_disable_pipestat(dev_priv, pipe,
1632 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe 1633 imr = I915_READ(VLV_IMR);
31acc7f5 1634 if (pipe == 0)
7e231dbe 1635 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1636 else
7e231dbe 1637 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1638 I915_WRITE(VLV_IMR, imr);
7e231dbe
JB		 1639 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1640}
1641
893eead0
CW		 1642static u32
1643ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 1644{
893eead0
CW		 1645 return list_entry(ring->request_list.prev,
1646 struct drm_i915_gem_request, list)->seqno;
1647}
1648
1649static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1650{
1651 if (list_empty(&ring->request_list) ||
b2eadbc8
CW		 1652 i915_seqno_passed(ring->get_seqno(ring, false),
1653 ring_last_seqno(ring))) {
893eead0 1654 /* Issue a wake-up to catch stuck h/w. */
9574b3fe
BW		 1655 if (waitqueue_active(&ring->irq_queue)) {
1656 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1657 ring->name);
893eead0
CW		 1658 wake_up_all(&ring->irq_queue);
1659 *err = true;
1660 }
1661 return true;
1662 }
1663 return false;
f65d9421
BG		 1664}
1665
1ec14ad3
CW		 1666static bool kick_ring(struct intel_ring_buffer *ring)
1667{
1668 struct drm_device *dev = ring->dev;
1669 struct drm_i915_private *dev_priv = dev->dev_private;
1670 u32 tmp = I915_READ_CTL(ring);
1671 if (tmp & RING_WAIT) {
1672 DRM_ERROR("Kicking stuck wait on %s\n",
1673 ring->name);
1674 I915_WRITE_CTL(ring, tmp);
1675 return true;
1676 }
1ec14ad3
CW		 1677 return false;
1678}
1679
d1e61e7f
CW		 1680static bool i915_hangcheck_hung(struct drm_device *dev)
1681{
1682 drm_i915_private_t *dev_priv = dev->dev_private;
1683
1684 if (dev_priv->hangcheck_count++ > 1) {
b4519513
CW		 1685 bool hung = true;
1686
d1e61e7f
CW		 1687 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1688 i915_handle_error(dev, true);
1689
1690 if (!IS_GEN2(dev)) {
b4519513
CW		 1691 struct intel_ring_buffer *ring;
1692 int i;
1693
d1e61e7f
CW		 1694 /* Is the chip hanging on a WAIT_FOR_EVENT?
1695 * If so we can simply poke the RB_WAIT bit
1696 * and break the hang. This should work on
1697 * all but the second generation chipsets.
1698 */
b4519513
CW		 1699 for_each_ring(ring, dev_priv, i)
1700 hung &= !kick_ring(ring);
d1e61e7f
CW		 1701 }
1702
b4519513 1703 return hung;
d1e61e7f
CW		 1704 }
1705
1706 return false;
1707}
1708
f65d9421
BG		 1709/**
1710 * This is called when the chip hasn't reported back with completed
1711 * batchbuffers in a long time. The first time this is called we simply record
1712 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1713 * again, we assume the chip is wedged and try to fix it.
1714 */
1715void i915_hangcheck_elapsed(unsigned long data)
1716{
1717 struct drm_device *dev = (struct drm_device *)data;
1718 drm_i915_private_t *dev_priv = dev->dev_private;
bd9854f9 1719 uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
b4519513
CW		 1720 struct intel_ring_buffer *ring;
1721 bool err = false, idle;
1722 int i;
893eead0 1723
3e0dc6b0
BW		 1724 if (!i915_enable_hangcheck)
1725 return;
1726
b4519513
CW		 1727 memset(acthd, 0, sizeof(acthd));
1728 idle = true;
1729 for_each_ring(ring, dev_priv, i) {
1730 idle &= i915_hangcheck_ring_idle(ring, &err);
1731 acthd[i] = intel_ring_get_active_head(ring);
1732 }
1733
893eead0 1734 /* If all work is done then ACTHD clearly hasn't advanced. */
b4519513 1735 if (idle) {
d1e61e7f
CW		 1736 if (err) {
1737 if (i915_hangcheck_hung(dev))
1738 return;
1739
893eead0 1740 goto repeat;
d1e61e7f
CW		 1741 }
1742
1743 dev_priv->hangcheck_count = 0;
893eead0
CW		 1744 return;
1745 }
b9201c14 1746
bd9854f9 1747 i915_get_extra_instdone(dev, instdone);
b4519513 1748 if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 &&
050ee91f 1749 memcmp(dev_priv->prev_instdone, instdone, sizeof(instdone)) == 0) {
d1e61e7f 1750 if (i915_hangcheck_hung(dev))
cbb465e7 1751 return;
cbb465e7
CW		 1752 } else {
1753 dev_priv->hangcheck_count = 0;
1754
b4519513 1755 memcpy(dev_priv->last_acthd, acthd, sizeof(acthd));
050ee91f 1756 memcpy(dev_priv->prev_instdone, instdone, sizeof(instdone));
cbb465e7 1757 }
f65d9421 1758
893eead0 1759repeat:
f65d9421 1760 /* Reset timer case chip hangs without another request being added */
b3b079db 1761 mod_timer(&dev_priv->hangcheck_timer,
cecc21fe 1762 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
f65d9421
BG		 1763}
1764
1da177e4
LT		 1765/* drm_dma.h hooks
1766*/
f71d4af4 1767static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 1768{
1769 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1770
4697995b
JB		 1771 atomic_set(&dev_priv->irq_received, 0);
1772
036a4a7d 1773 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 1774
036a4a7d
ZW		 1775 /* XXX hotplug from PCH */
1776
1777 I915_WRITE(DEIMR, 0xffffffff);
1778 I915_WRITE(DEIER, 0x0);
3143a2bf 1779 POSTING_READ(DEIER);
036a4a7d
ZW		 1780
1781 /* and GT */
1782 I915_WRITE(GTIMR, 0xffffffff);
1783 I915_WRITE(GTIER, 0x0);
3143a2bf 1784 POSTING_READ(GTIER);
c650156a
ZW		 1785
1786 /* south display irq */
1787 I915_WRITE(SDEIMR, 0xffffffff);
1788 I915_WRITE(SDEIER, 0x0);
3143a2bf 1789 POSTING_READ(SDEIER);
036a4a7d
ZW		 1790}
1791
7e231dbe
JB		 1792static void valleyview_irq_preinstall(struct drm_device *dev)
1793{
1794 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1795 int pipe;
1796
1797 atomic_set(&dev_priv->irq_received, 0);
1798
7e231dbe
JB		 1799 /* VLV magic */
1800 I915_WRITE(VLV_IMR, 0);
1801 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1802 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1803 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1804
7e231dbe
JB		 1805 /* and GT */
1806 I915_WRITE(GTIIR, I915_READ(GTIIR));
1807 I915_WRITE(GTIIR, I915_READ(GTIIR));
1808 I915_WRITE(GTIMR, 0xffffffff);
1809 I915_WRITE(GTIER, 0x0);
1810 POSTING_READ(GTIER);
1811
1812 I915_WRITE(DPINVGTT, 0xff);
1813
1814 I915_WRITE(PORT_HOTPLUG_EN, 0);
1815 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1816 for_each_pipe(pipe)
1817 I915_WRITE(PIPESTAT(pipe), 0xffff);
1818 I915_WRITE(VLV_IIR, 0xffffffff);
1819 I915_WRITE(VLV_IMR, 0xffffffff);
1820 I915_WRITE(VLV_IER, 0x0);
1821 POSTING_READ(VLV_IER);
1822}
1823
7fe0b973
KP		 1824/*
1825 * Enable digital hotplug on the PCH, and configure the DP short pulse
1826 * duration to 2ms (which is the minimum in the Display Port spec)
1827 *
1828 * This register is the same on all known PCH chips.
1829 */
1830
1831static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1832{
1833 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1834 u32 hotplug;
1835
1836 hotplug = I915_READ(PCH_PORT_HOTPLUG);
1837 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1838 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1839 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1840 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1841 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1842}
1843
f71d4af4 1844static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d
ZW		 1845{
1846 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1847 /* enable kind of interrupts always enabled */
013d5aa2
JB		 1848 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1849 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1ec14ad3 1850 u32 render_irqs;
2d7b8366 1851 u32 hotplug_mask;
036a4a7d 1852
1ec14ad3 1853 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 1854
1855 /* should always can generate irq */
1856 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3
CW		 1857 I915_WRITE(DEIMR, dev_priv->irq_mask);
1858 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
3143a2bf 1859 POSTING_READ(DEIER);
036a4a7d 1860
1ec14ad3 1861 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 1862
1863 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 1864 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 1865
1ec14ad3
CW		 1866 if (IS_GEN6(dev))
1867 render_irqs =
1868 GT_USER_INTERRUPT |
e2a1e2f0
BW		 1869 GEN6_BSD_USER_INTERRUPT |
1870 GEN6_BLITTER_USER_INTERRUPT;
1ec14ad3
CW		 1871 else
1872 render_irqs =
88f23b8f 1873 GT_USER_INTERRUPT |
c6df541c 1874 GT_PIPE_NOTIFY |
1ec14ad3
CW		 1875 GT_BSD_USER_INTERRUPT;
1876 I915_WRITE(GTIER, render_irqs);
3143a2bf 1877 POSTING_READ(GTIER);
036a4a7d 1878
2d7b8366 1879 if (HAS_PCH_CPT(dev)) {
9035a97a
CW		 1880 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1881 SDE_PORTB_HOTPLUG_CPT |
1882 SDE_PORTC_HOTPLUG_CPT |
1883 SDE_PORTD_HOTPLUG_CPT);
2d7b8366 1884 } else {
9035a97a
CW		 1885 hotplug_mask = (SDE_CRT_HOTPLUG |
1886 SDE_PORTB_HOTPLUG |
1887 SDE_PORTC_HOTPLUG |
1888 SDE_PORTD_HOTPLUG |
1889 SDE_AUX_MASK);
2d7b8366
YL		 1890 }
1891
1ec14ad3 1892 dev_priv->pch_irq_mask = ~hotplug_mask;
c650156a
ZW		 1893
1894 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1ec14ad3
CW		 1895 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1896 I915_WRITE(SDEIER, hotplug_mask);
3143a2bf 1897 POSTING_READ(SDEIER);
c650156a 1898
7fe0b973
KP		 1899 ironlake_enable_pch_hotplug(dev);
1900
f97108d1
JB		 1901 if (IS_IRONLAKE_M(dev)) {
1902 /* Clear & enable PCU event interrupts */
1903 I915_WRITE(DEIIR, DE_PCU_EVENT);
1904 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1905 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1906 }
1907
036a4a7d
ZW		 1908 return 0;
1909}
1910
f71d4af4 1911static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 1912{
1913 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1914 /* enable kind of interrupts always enabled */
b615b57a
CW		 1915 u32 display_mask =
1916 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
1917 DE_PLANEC_FLIP_DONE_IVB |
1918 DE_PLANEB_FLIP_DONE_IVB |
1919 DE_PLANEA_FLIP_DONE_IVB;
b1f14ad0
JB		 1920 u32 render_irqs;
1921 u32 hotplug_mask;
1922
b1f14ad0
JB		 1923 dev_priv->irq_mask = ~display_mask;
1924
1925 /* should always can generate irq */
1926 I915_WRITE(DEIIR, I915_READ(DEIIR));
1927 I915_WRITE(DEIMR, dev_priv->irq_mask);
b615b57a
CW		 1928 I915_WRITE(DEIER,
1929 display_mask |
1930 DE_PIPEC_VBLANK_IVB |
1931 DE_PIPEB_VBLANK_IVB |
1932 DE_PIPEA_VBLANK_IVB);
b1f14ad0
JB		 1933 POSTING_READ(DEIER);
1934
15b9f80e 1935 dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 1936
1937 I915_WRITE(GTIIR, I915_READ(GTIIR));
1938 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1939
e2a1e2f0 1940 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
15b9f80e 1941 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 1942 I915_WRITE(GTIER, render_irqs);
1943 POSTING_READ(GTIER);
1944
1945 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1946 SDE_PORTB_HOTPLUG_CPT |
1947 SDE_PORTC_HOTPLUG_CPT |
1948 SDE_PORTD_HOTPLUG_CPT);
1949 dev_priv->pch_irq_mask = ~hotplug_mask;
1950
1951 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1952 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1953 I915_WRITE(SDEIER, hotplug_mask);
1954 POSTING_READ(SDEIER);
1955
7fe0b973
KP		 1956 ironlake_enable_pch_hotplug(dev);
1957
b1f14ad0
JB		 1958 return 0;
1959}
1960
7e231dbe
JB		 1961static int valleyview_irq_postinstall(struct drm_device *dev)
1962{
1963 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7e231dbe
JB		 1964 u32 enable_mask;
1965 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
31acc7f5 1966 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
3bcedbe5 1967 u32 render_irqs;
7e231dbe
JB		 1968 u16 msid;
1969
1970 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
31acc7f5
JB		 1971 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
1972 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1973 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
7e231dbe
JB		 1974 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1975
31acc7f5
JB		 1976 /*
1977 *Leave vblank interrupts masked initially. enable/disable will
1978 * toggle them based on usage.
1979 */
1980 dev_priv->irq_mask = (~enable_mask) |
1981 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1982 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1983
7e231dbe
JB		 1984 dev_priv->pipestat[0] = 0;
1985 dev_priv->pipestat[1] = 0;
1986
7e231dbe
JB		 1987 /* Hack for broken MSIs on VLV */
1988 pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
1989 pci_read_config_word(dev->pdev, 0x98, &msid);
1990 msid &= 0xff; /* mask out delivery bits */
1991 msid |= (1<<14);
1992 pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
1993
1994 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
1995 I915_WRITE(VLV_IER, enable_mask);
1996 I915_WRITE(VLV_IIR, 0xffffffff);
1997 I915_WRITE(PIPESTAT(0), 0xffff);
1998 I915_WRITE(PIPESTAT(1), 0xffff);
1999 POSTING_READ(VLV_IER);
2000
31acc7f5
JB		 2001 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
2002 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
2003
7e231dbe
JB		 2004 I915_WRITE(VLV_IIR, 0xffffffff);
2005 I915_WRITE(VLV_IIR, 0xffffffff);
2006
7e231dbe 2007 I915_WRITE(GTIIR, I915_READ(GTIIR));
31acc7f5 2008 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
3bcedbe5
JB		 2009
2010 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2011 GEN6_BLITTER_USER_INTERRUPT;
2012 I915_WRITE(GTIER, render_irqs);
7e231dbe
JB		 2013 POSTING_READ(GTIER);
2014
2015 /* ack & enable invalid PTE error interrupts */
2016#if 0 /* FIXME: add support to irq handler for checking these bits */
2017 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2018 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2019#endif
2020
2021 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
7e231dbe
JB		 2022 /* Note HDMI and DP share bits */
2023 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2024 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2025 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2026 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2027 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2028 hotplug_en |= HDMID_HOTPLUG_INT_EN;
ae33cdcf 2029 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
7e231dbe 2030 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
ae33cdcf 2031 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
7e231dbe
JB		 2032 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2033 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2034 hotplug_en |= CRT_HOTPLUG_INT_EN;
2035 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2036 }
7e231dbe
JB		 2037
2038 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2039
2040 return 0;
2041}
2042
7e231dbe
JB		 2043static void valleyview_irq_uninstall(struct drm_device *dev)
2044{
2045 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2046 int pipe;
2047
2048 if (!dev_priv)
2049 return;
2050
7e231dbe
JB		 2051 for_each_pipe(pipe)
2052 I915_WRITE(PIPESTAT(pipe), 0xffff);
2053
2054 I915_WRITE(HWSTAM, 0xffffffff);
2055 I915_WRITE(PORT_HOTPLUG_EN, 0);
2056 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2057 for_each_pipe(pipe)
2058 I915_WRITE(PIPESTAT(pipe), 0xffff);
2059 I915_WRITE(VLV_IIR, 0xffffffff);
2060 I915_WRITE(VLV_IMR, 0xffffffff);
2061 I915_WRITE(VLV_IER, 0x0);
2062 POSTING_READ(VLV_IER);
2063}
2064
f71d4af4 2065static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 2066{
2067 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 2068
2069 if (!dev_priv)
2070 return;
2071
036a4a7d
ZW		 2072 I915_WRITE(HWSTAM, 0xffffffff);
2073
2074 I915_WRITE(DEIMR, 0xffffffff);
2075 I915_WRITE(DEIER, 0x0);
2076 I915_WRITE(DEIIR, I915_READ(DEIIR));
2077
2078 I915_WRITE(GTIMR, 0xffffffff);
2079 I915_WRITE(GTIER, 0x0);
2080 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f
KP		 2081
2082 I915_WRITE(SDEIMR, 0xffffffff);
2083 I915_WRITE(SDEIER, 0x0);
2084 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
036a4a7d
ZW		 2085}
2086
a266c7d5 2087static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 2088{
2089 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2090 int pipe;
91e3738e 2091
a266c7d5 2092 atomic_set(&dev_priv->irq_received, 0);
5ca58282 2093
9db4a9c7
JB		 2094 for_each_pipe(pipe)
2095 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 2096 I915_WRITE16(IMR, 0xffff);
2097 I915_WRITE16(IER, 0x0);
2098 POSTING_READ16(IER);
c2798b19
CW		 2099}
2100
2101static int i8xx_irq_postinstall(struct drm_device *dev)
2102{
2103 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2104
c2798b19
CW		 2105 dev_priv->pipestat[0] = 0;
2106 dev_priv->pipestat[1] = 0;
2107
2108 I915_WRITE16(EMR,
2109 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2110
2111 /* Unmask the interrupts that we always want on. */
2112 dev_priv->irq_mask =
2113 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2114 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2115 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2116 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2117 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2118 I915_WRITE16(IMR, dev_priv->irq_mask);
2119
2120 I915_WRITE16(IER,
2121 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2122 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2123 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2124 I915_USER_INTERRUPT);
2125 POSTING_READ16(IER);
2126
2127 return 0;
2128}
2129
ff1f525e 2130static irqreturn_t i8xx_irq_handler(int irq, void *arg)
c2798b19
CW		 2131{
2132 struct drm_device *dev = (struct drm_device *) arg;
2133 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 2134 u16 iir, new_iir;
2135 u32 pipe_stats[2];
2136 unsigned long irqflags;
2137 int irq_received;
2138 int pipe;
2139 u16 flip_mask =
2140 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2141 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2142
2143 atomic_inc(&dev_priv->irq_received);
2144
2145 iir = I915_READ16(IIR);
2146 if (iir == 0)
2147 return IRQ_NONE;
2148
2149 while (iir & ~flip_mask) {
2150 /* Can't rely on pipestat interrupt bit in iir as it might
2151 * have been cleared after the pipestat interrupt was received.
2152 * It doesn't set the bit in iir again, but it still produces
2153 * interrupts (for non-MSI).
2154 */
2155 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2156 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2157 i915_handle_error(dev, false);
2158
2159 for_each_pipe(pipe) {
2160 int reg = PIPESTAT(pipe);
2161 pipe_stats[pipe] = I915_READ(reg);
2162
2163 /*
2164 * Clear the PIPE*STAT regs before the IIR
2165 */
2166 if (pipe_stats[pipe] & 0x8000ffff) {
2167 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2168 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2169 pipe_name(pipe));
2170 I915_WRITE(reg, pipe_stats[pipe]);
2171 irq_received = 1;
2172 }
2173 }
2174 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2175
2176 I915_WRITE16(IIR, iir & ~flip_mask);
2177 new_iir = I915_READ16(IIR); /* Flush posted writes */
2178
d05c617e 2179 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 2180
2181 if (iir & I915_USER_INTERRUPT)
2182 notify_ring(dev, &dev_priv->ring[RCS]);
2183
2184 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2185 drm_handle_vblank(dev, 0)) {
2186 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2187 intel_prepare_page_flip(dev, 0);
2188 intel_finish_page_flip(dev, 0);
2189 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2190 }
2191 }
2192
2193 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2194 drm_handle_vblank(dev, 1)) {
2195 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2196 intel_prepare_page_flip(dev, 1);
2197 intel_finish_page_flip(dev, 1);
2198 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2199 }
2200 }
2201
2202 iir = new_iir;
2203 }
2204
2205 return IRQ_HANDLED;
2206}
2207
2208static void i8xx_irq_uninstall(struct drm_device * dev)
2209{
2210 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2211 int pipe;
2212
c2798b19
CW		 2213 for_each_pipe(pipe) {
2214 /* Clear enable bits; then clear status bits */
2215 I915_WRITE(PIPESTAT(pipe), 0);
2216 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2217 }
2218 I915_WRITE16(IMR, 0xffff);
2219 I915_WRITE16(IER, 0x0);
2220 I915_WRITE16(IIR, I915_READ16(IIR));
2221}
2222
a266c7d5
CW		 2223static void i915_irq_preinstall(struct drm_device * dev)
2224{
2225 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2226 int pipe;
2227
2228 atomic_set(&dev_priv->irq_received, 0);
2229
2230 if (I915_HAS_HOTPLUG(dev)) {
2231 I915_WRITE(PORT_HOTPLUG_EN, 0);
2232 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2233 }
2234
00d98ebd 2235 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 2236 for_each_pipe(pipe)
2237 I915_WRITE(PIPESTAT(pipe), 0);
2238 I915_WRITE(IMR, 0xffffffff);
2239 I915_WRITE(IER, 0x0);
2240 POSTING_READ(IER);
2241}
2242
2243static int i915_irq_postinstall(struct drm_device *dev)
2244{
2245 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 2246 u32 enable_mask;
a266c7d5 2247
a266c7d5
CW		 2248 dev_priv->pipestat[0] = 0;
2249 dev_priv->pipestat[1] = 0;
2250
38bde180
CW		 2251 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2252
2253 /* Unmask the interrupts that we always want on. */
2254 dev_priv->irq_mask =
2255 ~(I915_ASLE_INTERRUPT |
2256 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2257 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2258 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2259 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2260 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2261
2262 enable_mask =
2263 I915_ASLE_INTERRUPT |
2264 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2265 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2266 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2267 I915_USER_INTERRUPT;
2268
a266c7d5
CW		 2269 if (I915_HAS_HOTPLUG(dev)) {
2270 /* Enable in IER... */
2271 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2272 /* and unmask in IMR */
2273 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2274 }
2275
a266c7d5
CW		 2276 I915_WRITE(IMR, dev_priv->irq_mask);
2277 I915_WRITE(IER, enable_mask);
2278 POSTING_READ(IER);
2279
2280 if (I915_HAS_HOTPLUG(dev)) {
2281 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2282
a266c7d5
CW		 2283 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2284 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2285 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2286 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2287 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2288 hotplug_en |= HDMID_HOTPLUG_INT_EN;
084b612e 2289 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
a266c7d5 2290 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
084b612e 2291 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
a266c7d5
CW		 2292 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2293 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2294 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5
CW		 2295 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2296 }
2297
2298 /* Ignore TV since it's buggy */
2299
2300 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2301 }
2302
2303 intel_opregion_enable_asle(dev);
2304
2305 return 0;
2306}
2307
ff1f525e 2308static irqreturn_t i915_irq_handler(int irq, void *arg)
a266c7d5
CW		 2309{
2310 struct drm_device *dev = (struct drm_device *) arg;
2311 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 2312 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 2313 unsigned long irqflags;
38bde180
CW		 2314 u32 flip_mask =
2315 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2316 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2317 u32 flip[2] = {
2318 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2319 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2320 };
2321 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 2322
2323 atomic_inc(&dev_priv->irq_received);
2324
2325 iir = I915_READ(IIR);
38bde180
CW		 2326 do {
2327 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 2328 bool blc_event = false;
a266c7d5
CW		 2329
2330 /* Can't rely on pipestat interrupt bit in iir as it might
2331 * have been cleared after the pipestat interrupt was received.
2332 * It doesn't set the bit in iir again, but it still produces
2333 * interrupts (for non-MSI).
2334 */
2335 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2336 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2337 i915_handle_error(dev, false);
2338
2339 for_each_pipe(pipe) {
2340 int reg = PIPESTAT(pipe);
2341 pipe_stats[pipe] = I915_READ(reg);
2342
38bde180 2343 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 2344 if (pipe_stats[pipe] & 0x8000ffff) {
2345 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2346 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2347 pipe_name(pipe));
2348 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 2349 irq_received = true;
a266c7d5
CW		 2350 }
2351 }
2352 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2353
2354 if (!irq_received)
2355 break;
2356
a266c7d5
CW		 2357 /* Consume port. Then clear IIR or we'll miss events */
2358 if ((I915_HAS_HOTPLUG(dev)) &&
2359 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2360 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2361
2362 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2363 hotplug_status);
2364 if (hotplug_status & dev_priv->hotplug_supported_mask)
2365 queue_work(dev_priv->wq,
2366 &dev_priv->hotplug_work);
2367
2368 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 2369 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 2370 }
2371
38bde180 2372 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2373 new_iir = I915_READ(IIR); /* Flush posted writes */
2374
a266c7d5
CW		 2375 if (iir & I915_USER_INTERRUPT)
2376 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 2377
a266c7d5 2378 for_each_pipe(pipe) {
38bde180
CW		 2379 int plane = pipe;
2380 if (IS_MOBILE(dev))
2381 plane = !plane;
8291ee90 2382 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2383 drm_handle_vblank(dev, pipe)) {
38bde180
CW		 2384 if (iir & flip[plane]) {
2385 intel_prepare_page_flip(dev, plane);
2386 intel_finish_page_flip(dev, pipe);
2387 flip_mask &= ~flip[plane];
2388 }
a266c7d5
CW		 2389 }
2390
2391 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2392 blc_event = true;
2393 }
2394
a266c7d5
CW		 2395 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2396 intel_opregion_asle_intr(dev);
2397
2398 /* With MSI, interrupts are only generated when iir
2399 * transitions from zero to nonzero. If another bit got
2400 * set while we were handling the existing iir bits, then
2401 * we would never get another interrupt.
2402 *
2403 * This is fine on non-MSI as well, as if we hit this path
2404 * we avoid exiting the interrupt handler only to generate
2405 * another one.
2406 *
2407 * Note that for MSI this could cause a stray interrupt report
2408 * if an interrupt landed in the time between writing IIR and
2409 * the posting read. This should be rare enough to never
2410 * trigger the 99% of 100,000 interrupts test for disabling
2411 * stray interrupts.
2412 */
38bde180 2413 ret = IRQ_HANDLED;
a266c7d5 2414 iir = new_iir;
38bde180 2415 } while (iir & ~flip_mask);
a266c7d5 2416
d05c617e 2417 i915_update_dri1_breadcrumb(dev);
8291ee90 2418
a266c7d5
CW		 2419 return ret;
2420}
2421
2422static void i915_irq_uninstall(struct drm_device * dev)
2423{
2424 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2425 int pipe;
2426
a266c7d5
CW		 2427 if (I915_HAS_HOTPLUG(dev)) {
2428 I915_WRITE(PORT_HOTPLUG_EN, 0);
2429 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2430 }
2431
00d98ebd 2432 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 2433 for_each_pipe(pipe) {
2434 /* Clear enable bits; then clear status bits */
a266c7d5 2435 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 2436 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2437 }
a266c7d5
CW		 2438 I915_WRITE(IMR, 0xffffffff);
2439 I915_WRITE(IER, 0x0);
2440
a266c7d5
CW		 2441 I915_WRITE(IIR, I915_READ(IIR));
2442}
2443
2444static void i965_irq_preinstall(struct drm_device * dev)
2445{
2446 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2447 int pipe;
2448
2449 atomic_set(&dev_priv->irq_received, 0);
2450
adca4730
CW		 2451 I915_WRITE(PORT_HOTPLUG_EN, 0);
2452 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2453
2454 I915_WRITE(HWSTAM, 0xeffe);
2455 for_each_pipe(pipe)
2456 I915_WRITE(PIPESTAT(pipe), 0);
2457 I915_WRITE(IMR, 0xffffffff);
2458 I915_WRITE(IER, 0x0);
2459 POSTING_READ(IER);
2460}
2461
2462static int i965_irq_postinstall(struct drm_device *dev)
2463{
2464 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
adca4730 2465 u32 hotplug_en;
bbba0a97 2466 u32 enable_mask;
a266c7d5
CW		 2467 u32 error_mask;
2468
a266c7d5 2469 /* Unmask the interrupts that we always want on. */
bbba0a97 2470 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 2471 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 2472 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2473 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2474 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2475 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2476 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2477
2478 enable_mask = ~dev_priv->irq_mask;
2479 enable_mask |= I915_USER_INTERRUPT;
2480
2481 if (IS_G4X(dev))
2482 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5
CW		 2483
2484 dev_priv->pipestat[0] = 0;
2485 dev_priv->pipestat[1] = 0;
2486
a266c7d5
CW		 2487 /*
2488 * Enable some error detection, note the instruction error mask
2489 * bit is reserved, so we leave it masked.
2490 */
2491 if (IS_G4X(dev)) {
2492 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2493 GM45_ERROR_MEM_PRIV |
2494 GM45_ERROR_CP_PRIV |
2495 I915_ERROR_MEMORY_REFRESH);
2496 } else {
2497 error_mask = ~(I915_ERROR_PAGE_TABLE |
2498 I915_ERROR_MEMORY_REFRESH);
2499 }
2500 I915_WRITE(EMR, error_mask);
2501
2502 I915_WRITE(IMR, dev_priv->irq_mask);
2503 I915_WRITE(IER, enable_mask);
2504 POSTING_READ(IER);
2505
adca4730
CW		 2506 /* Note HDMI and DP share hotplug bits */
2507 hotplug_en = 0;
2508 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2509 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2510 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2511 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2512 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2513 hotplug_en |= HDMID_HOTPLUG_INT_EN;
084b612e
CW		 2514 if (IS_G4X(dev)) {
2515 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
2516 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2517 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
2518 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2519 } else {
2520 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
2521 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2522 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
2523 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2524 }
adca4730
CW		 2525 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2526 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5 2527
adca4730
CW		 2528 /* Programming the CRT detection parameters tends
2529 to generate a spurious hotplug event about three
2530 seconds later. So just do it once.
2531 */
2532 if (IS_G4X(dev))
2533 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2534 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2535 }
a266c7d5 2536
adca4730 2537 /* Ignore TV since it's buggy */
a266c7d5 2538
adca4730 2539 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
a266c7d5
CW		 2540
2541 intel_opregion_enable_asle(dev);
2542
2543 return 0;
2544}
2545
ff1f525e 2546static irqreturn_t i965_irq_handler(int irq, void *arg)
a266c7d5
CW		 2547{
2548 struct drm_device *dev = (struct drm_device *) arg;
2549 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 2550 u32 iir, new_iir;
2551 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 2552 unsigned long irqflags;
2553 int irq_received;
2554 int ret = IRQ_NONE, pipe;
a266c7d5
CW		 2555
2556 atomic_inc(&dev_priv->irq_received);
2557
2558 iir = I915_READ(IIR);
2559
a266c7d5 2560 for (;;) {
2c8ba29f
CW		 2561 bool blc_event = false;
2562
a266c7d5
CW		 2563 irq_received = iir != 0;
2564
2565 /* Can't rely on pipestat interrupt bit in iir as it might
2566 * have been cleared after the pipestat interrupt was received.
2567 * It doesn't set the bit in iir again, but it still produces
2568 * interrupts (for non-MSI).
2569 */
2570 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2571 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2572 i915_handle_error(dev, false);
2573
2574 for_each_pipe(pipe) {
2575 int reg = PIPESTAT(pipe);
2576 pipe_stats[pipe] = I915_READ(reg);
2577
2578 /*
2579 * Clear the PIPE*STAT regs before the IIR
2580 */
2581 if (pipe_stats[pipe] & 0x8000ffff) {
2582 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2583 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2584 pipe_name(pipe));
2585 I915_WRITE(reg, pipe_stats[pipe]);
2586 irq_received = 1;
2587 }
2588 }
2589 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2590
2591 if (!irq_received)
2592 break;
2593
2594 ret = IRQ_HANDLED;
2595
2596 /* Consume port. Then clear IIR or we'll miss events */
adca4730 2597 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
a266c7d5
CW		 2598 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2599
2600 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2601 hotplug_status);
2602 if (hotplug_status & dev_priv->hotplug_supported_mask)
2603 queue_work(dev_priv->wq,
2604 &dev_priv->hotplug_work);
2605
2606 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2607 I915_READ(PORT_HOTPLUG_STAT);
2608 }
2609
2610 I915_WRITE(IIR, iir);
2611 new_iir = I915_READ(IIR); /* Flush posted writes */
2612
a266c7d5
CW		 2613 if (iir & I915_USER_INTERRUPT)
2614 notify_ring(dev, &dev_priv->ring[RCS]);
2615 if (iir & I915_BSD_USER_INTERRUPT)
2616 notify_ring(dev, &dev_priv->ring[VCS]);
2617
4f7d1e79 2618 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
a266c7d5 2619 intel_prepare_page_flip(dev, 0);
a266c7d5 2620
4f7d1e79 2621 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
a266c7d5 2622 intel_prepare_page_flip(dev, 1);
a266c7d5
CW		 2623
2624 for_each_pipe(pipe) {
2c8ba29f 2625 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2626 drm_handle_vblank(dev, pipe)) {
4f7d1e79
CW		 2627 i915_pageflip_stall_check(dev, pipe);
2628 intel_finish_page_flip(dev, pipe);
a266c7d5
CW		 2629 }
2630
2631 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2632 blc_event = true;
2633 }
2634
2635
2636 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2637 intel_opregion_asle_intr(dev);
2638
2639 /* With MSI, interrupts are only generated when iir
2640 * transitions from zero to nonzero. If another bit got
2641 * set while we were handling the existing iir bits, then
2642 * we would never get another interrupt.
2643 *
2644 * This is fine on non-MSI as well, as if we hit this path
2645 * we avoid exiting the interrupt handler only to generate
2646 * another one.
2647 *
2648 * Note that for MSI this could cause a stray interrupt report
2649 * if an interrupt landed in the time between writing IIR and
2650 * the posting read. This should be rare enough to never
2651 * trigger the 99% of 100,000 interrupts test for disabling
2652 * stray interrupts.
2653 */
2654 iir = new_iir;
2655 }
2656
d05c617e 2657 i915_update_dri1_breadcrumb(dev);
2c8ba29f 2658
a266c7d5
CW		 2659 return ret;
2660}
2661
2662static void i965_irq_uninstall(struct drm_device * dev)
2663{
2664 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2665 int pipe;
2666
2667 if (!dev_priv)
2668 return;
2669
adca4730
CW		 2670 I915_WRITE(PORT_HOTPLUG_EN, 0);
2671 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2672
2673 I915_WRITE(HWSTAM, 0xffffffff);
2674 for_each_pipe(pipe)
2675 I915_WRITE(PIPESTAT(pipe), 0);
2676 I915_WRITE(IMR, 0xffffffff);
2677 I915_WRITE(IER, 0x0);
2678
2679 for_each_pipe(pipe)
2680 I915_WRITE(PIPESTAT(pipe),
2681 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2682 I915_WRITE(IIR, I915_READ(IIR));
2683}
2684
f71d4af4
JB		 2685void intel_irq_init(struct drm_device *dev)
2686{
8b2e326d
CW		 2687 struct drm_i915_private *dev_priv = dev->dev_private;
2688
2689 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2690 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
c6a828d3 2691 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
a4da4fa4 2692 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
8b2e326d 2693
61bac78e
DV		 2694 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
2695 (unsigned long) dev);
2696
f71d4af4
JB		 2697 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2698 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7d4e146f 2699 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 2700 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2701 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2702 }
2703
c3613de9
KP		 2704 if (drm_core_check_feature(dev, DRIVER_MODESET))
2705 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2706 else
2707 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 2708 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2709
7e231dbe
JB		 2710 if (IS_VALLEYVIEW(dev)) {
2711 dev->driver->irq_handler = valleyview_irq_handler;
2712 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2713 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2714 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2715 dev->driver->enable_vblank = valleyview_enable_vblank;
2716 dev->driver->disable_vblank = valleyview_disable_vblank;
4a06e201 2717 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
f71d4af4
JB		 2718 /* Share pre & uninstall handlers with ILK/SNB */
2719 dev->driver->irq_handler = ivybridge_irq_handler;
2720 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2721 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2722 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2723 dev->driver->enable_vblank = ivybridge_enable_vblank;
2724 dev->driver->disable_vblank = ivybridge_disable_vblank;
2725 } else if (HAS_PCH_SPLIT(dev)) {
2726 dev->driver->irq_handler = ironlake_irq_handler;
2727 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2728 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2729 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2730 dev->driver->enable_vblank = ironlake_enable_vblank;
2731 dev->driver->disable_vblank = ironlake_disable_vblank;
2732 } else {
c2798b19
CW		 2733 if (INTEL_INFO(dev)->gen == 2) {
2734 dev->driver->irq_preinstall = i8xx_irq_preinstall;
2735 dev->driver->irq_postinstall = i8xx_irq_postinstall;
2736 dev->driver->irq_handler = i8xx_irq_handler;
2737 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5
CW		 2738 } else if (INTEL_INFO(dev)->gen == 3) {
2739 dev->driver->irq_preinstall = i915_irq_preinstall;
2740 dev->driver->irq_postinstall = i915_irq_postinstall;
2741 dev->driver->irq_uninstall = i915_irq_uninstall;
2742 dev->driver->irq_handler = i915_irq_handler;
c2798b19 2743 } else {
a266c7d5
CW		 2744 dev->driver->irq_preinstall = i965_irq_preinstall;
2745 dev->driver->irq_postinstall = i965_irq_postinstall;
2746 dev->driver->irq_uninstall = i965_irq_uninstall;
2747 dev->driver->irq_handler = i965_irq_handler;
c2798b19 2748 }
f71d4af4
JB		 2749 dev->driver->enable_vblank = i915_enable_vblank;
2750 dev->driver->disable_vblank = i915_disable_vblank;
2751 }
2752}
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