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drm/i915: setup the hangcheck timer early
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/i915_drm.h>
1da177e4 35#include "i915_drv.h"
1c5d22f7 36#include "i915_trace.h"
79e53945 37#include "intel_drv.h"
1da177e4 38
036a4a7d 39/* For display hotplug interrupt */
995b6762 40static void
f2b115e6 41ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 42{
1ec14ad3
CW		 43 if ((dev_priv->irq_mask & mask) != 0) {
44 dev_priv->irq_mask &= ~mask;
45 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 46 POSTING_READ(DEIMR);
036a4a7d
ZW		 47 }
48}
49
50static inline void
f2b115e6 51ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 52{
1ec14ad3
CW		 53 if ((dev_priv->irq_mask & mask) != mask) {
54 dev_priv->irq_mask |= mask;
55 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 56 POSTING_READ(DEIMR);
036a4a7d
ZW		 57 }
58}
59
7c463586
KP		 60void
61i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
62{
63 if ((dev_priv->pipestat[pipe] & mask) != mask) {
9db4a9c7 64 u32 reg = PIPESTAT(pipe);
7c463586
KP		 65
66 dev_priv->pipestat[pipe] |= mask;
67 /* Enable the interrupt, clear any pending status */
68 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
3143a2bf 69 POSTING_READ(reg);
7c463586
KP		 70 }
71}
72
73void
74i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
75{
76 if ((dev_priv->pipestat[pipe] & mask) != 0) {
9db4a9c7 77 u32 reg = PIPESTAT(pipe);
7c463586
KP		 78
79 dev_priv->pipestat[pipe] &= ~mask;
80 I915_WRITE(reg, dev_priv->pipestat[pipe]);
3143a2bf 81 POSTING_READ(reg);
7c463586
KP		 82 }
83}
84
01c66889
ZY		 85/**
86 * intel_enable_asle - enable ASLE interrupt for OpRegion
87 */
1ec14ad3 88void intel_enable_asle(struct drm_device *dev)
01c66889 89{
1ec14ad3
CW		 90 drm_i915_private_t *dev_priv = dev->dev_private;
91 unsigned long irqflags;
92
7e231dbe
JB		 93 /* FIXME: opregion/asle for VLV */
94 if (IS_VALLEYVIEW(dev))
95 return;
96
1ec14ad3 97 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 98
c619eed4 99 if (HAS_PCH_SPLIT(dev))
f2b115e6 100 ironlake_enable_display_irq(dev_priv, DE_GSE);
edcb49ca 101 else {
01c66889 102 i915_enable_pipestat(dev_priv, 1,
d874bcff 103 PIPE_LEGACY_BLC_EVENT_ENABLE);
a6c45cf0 104 if (INTEL_INFO(dev)->gen >= 4)
edcb49ca 105 i915_enable_pipestat(dev_priv, 0,
d874bcff 106 PIPE_LEGACY_BLC_EVENT_ENABLE);
edcb49ca 107 }
1ec14ad3
CW		 108
109 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 110}
111
0a3e67a4
JB		 112/**
113 * i915_pipe_enabled - check if a pipe is enabled
114 * @dev: DRM device
115 * @pipe: pipe to check
116 *
117 * Reading certain registers when the pipe is disabled can hang the chip.
118 * Use this routine to make sure the PLL is running and the pipe is active
119 * before reading such registers if unsure.
120 */
121static int
122i915_pipe_enabled(struct drm_device *dev, int pipe)
123{
124 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
702e7a56
PZ		 125 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
126 pipe);
127
128 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
0a3e67a4
JB		 129}
130
42f52ef8
KP		 131/* Called from drm generic code, passed a 'crtc', which
132 * we use as a pipe index
133 */
f71d4af4 134static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 135{
136 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
137 unsigned long high_frame;
138 unsigned long low_frame;
5eddb70b 139 u32 high1, high2, low;
0a3e67a4
JB		 140
141 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 142 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 143 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 144 return 0;
145 }
146
9db4a9c7
JB		 147 high_frame = PIPEFRAME(pipe);
148 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 149
0a3e67a4
JB		 150 /*
151 * High & low register fields aren't synchronized, so make sure
152 * we get a low value that's stable across two reads of the high
153 * register.
154 */
155 do {
5eddb70b
CW		 156 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
157 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
158 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 159 } while (high1 != high2);
160
5eddb70b
CW		 161 high1 >>= PIPE_FRAME_HIGH_SHIFT;
162 low >>= PIPE_FRAME_LOW_SHIFT;
163 return (high1 << 8) | low;
0a3e67a4
JB		 164}
165
f71d4af4 166static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 167{
168 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 169 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 170
171 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 172 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 173 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 174 return 0;
175 }
176
177 return I915_READ(reg);
178}
179
f71d4af4 180static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 181 int *vpos, int *hpos)
182{
183 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
184 u32 vbl = 0, position = 0;
185 int vbl_start, vbl_end, htotal, vtotal;
186 bool in_vbl = true;
187 int ret = 0;
fe2b8f9d
PZ		 188 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
189 pipe);
0af7e4df
MK		 190
191 if (!i915_pipe_enabled(dev, pipe)) {
192 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 193 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 194 return 0;
195 }
196
197 /* Get vtotal. */
fe2b8f9d 198 vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 199
200 if (INTEL_INFO(dev)->gen >= 4) {
201 /* No obvious pixelcount register. Only query vertical
202 * scanout position from Display scan line register.
203 */
204 position = I915_READ(PIPEDSL(pipe));
205
206 /* Decode into vertical scanout position. Don't have
207 * horizontal scanout position.
208 */
209 *vpos = position & 0x1fff;
210 *hpos = 0;
211 } else {
212 /* Have access to pixelcount since start of frame.
213 * We can split this into vertical and horizontal
214 * scanout position.
215 */
216 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
217
fe2b8f9d 218 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 219 *vpos = position / htotal;
220 *hpos = position - (*vpos * htotal);
221 }
222
223 /* Query vblank area. */
fe2b8f9d 224 vbl = I915_READ(VBLANK(cpu_transcoder));
0af7e4df
MK		 225
226 /* Test position against vblank region. */
227 vbl_start = vbl & 0x1fff;
228 vbl_end = (vbl >> 16) & 0x1fff;
229
230 if ((*vpos < vbl_start) || (*vpos > vbl_end))
231 in_vbl = false;
232
233 /* Inside "upper part" of vblank area? Apply corrective offset: */
234 if (in_vbl && (*vpos >= vbl_start))
235 *vpos = *vpos - vtotal;
236
237 /* Readouts valid? */
238 if (vbl > 0)
239 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
240
241 /* In vblank? */
242 if (in_vbl)
243 ret |= DRM_SCANOUTPOS_INVBL;
244
245 return ret;
246}
247
f71d4af4 248static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 249 int *max_error,
250 struct timeval *vblank_time,
251 unsigned flags)
252{
4041b853
CW		 253 struct drm_i915_private *dev_priv = dev->dev_private;
254 struct drm_crtc *crtc;
0af7e4df 255
4041b853
CW		 256 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
257 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 258 return -EINVAL;
259 }
260
261 /* Get drm_crtc to timestamp: */
4041b853
CW		 262 crtc = intel_get_crtc_for_pipe(dev, pipe);
263 if (crtc == NULL) {
264 DRM_ERROR("Invalid crtc %d\n", pipe);
265 return -EINVAL;
266 }
267
268 if (!crtc->enabled) {
269 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
270 return -EBUSY;
271 }
0af7e4df
MK		 272
273 /* Helper routine in DRM core does all the work: */
4041b853
CW		 274 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
275 vblank_time, flags,
276 crtc);
0af7e4df
MK		 277}
278
5ca58282
JB		 279/*
280 * Handle hotplug events outside the interrupt handler proper.
281 */
282static void i915_hotplug_work_func(struct work_struct *work)
283{
284 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
285 hotplug_work);
286 struct drm_device *dev = dev_priv->dev;
c31c4ba3 287 struct drm_mode_config *mode_config = &dev->mode_config;
4ef69c7a
CW		 288 struct intel_encoder *encoder;
289
a65e34c7 290 mutex_lock(&mode_config->mutex);
e67189ab
JB		 291 DRM_DEBUG_KMS("running encoder hotplug functions\n");
292
4ef69c7a
CW		 293 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
294 if (encoder->hot_plug)
295 encoder->hot_plug(encoder);
296
40ee3381
KP		 297 mutex_unlock(&mode_config->mutex);
298
5ca58282 299 /* Just fire off a uevent and let userspace tell us what to do */
eb1f8e4f 300 drm_helper_hpd_irq_event(dev);
5ca58282
JB		 301}
302
73edd18f 303static void ironlake_handle_rps_change(struct drm_device *dev)
f97108d1
JB		 304{
305 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 306 u32 busy_up, busy_down, max_avg, min_avg;
9270388e
DV		 307 u8 new_delay;
308 unsigned long flags;
309
310 spin_lock_irqsave(&mchdev_lock, flags);
f97108d1 311
73edd18f
DV		 312 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
313
20e4d407 314 new_delay = dev_priv->ips.cur_delay;
9270388e 315
7648fa99 316 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 317 busy_up = I915_READ(RCPREVBSYTUPAVG);
318 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 319 max_avg = I915_READ(RCBMAXAVG);
320 min_avg = I915_READ(RCBMINAVG);
321
322 /* Handle RCS change request from hw */
b5b72e89 323 if (busy_up > max_avg) {
20e4d407
DV		 324 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
325 new_delay = dev_priv->ips.cur_delay - 1;
326 if (new_delay < dev_priv->ips.max_delay)
327 new_delay = dev_priv->ips.max_delay;
b5b72e89 328 } else if (busy_down < min_avg) {
20e4d407
DV		 329 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
330 new_delay = dev_priv->ips.cur_delay + 1;
331 if (new_delay > dev_priv->ips.min_delay)
332 new_delay = dev_priv->ips.min_delay;
f97108d1
JB		 333 }
334
7648fa99 335 if (ironlake_set_drps(dev, new_delay))
20e4d407 336 dev_priv->ips.cur_delay = new_delay;
f97108d1 337
9270388e
DV		 338 spin_unlock_irqrestore(&mchdev_lock, flags);
339
f97108d1
JB		 340 return;
341}
342
549f7365
CW		 343static void notify_ring(struct drm_device *dev,
344 struct intel_ring_buffer *ring)
345{
346 struct drm_i915_private *dev_priv = dev->dev_private;
9862e600 347
475553de
CW		 348 if (ring->obj == NULL)
349 return;
350
b2eadbc8 351 trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
9862e600 352
549f7365 353 wake_up_all(&ring->irq_queue);
3e0dc6b0
BW		 354 if (i915_enable_hangcheck) {
355 dev_priv->hangcheck_count = 0;
356 mod_timer(&dev_priv->hangcheck_timer,
cecc21fe 357 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
3e0dc6b0 358 }
549f7365
CW		 359}
360
4912d041 361static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 362{
4912d041 363 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
c6a828d3 364 rps.work);
4912d041 365 u32 pm_iir, pm_imr;
7b9e0ae6 366 u8 new_delay;
4912d041 367
c6a828d3
DV		 368 spin_lock_irq(&dev_priv->rps.lock);
369 pm_iir = dev_priv->rps.pm_iir;
370 dev_priv->rps.pm_iir = 0;
4912d041 371 pm_imr = I915_READ(GEN6_PMIMR);
a9e2641d 372 I915_WRITE(GEN6_PMIMR, 0);
c6a828d3 373 spin_unlock_irq(&dev_priv->rps.lock);
3b8d8d91 374
7b9e0ae6 375 if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
3b8d8d91
JB		 376 return;
377
4fc688ce 378 mutex_lock(&dev_priv->rps.hw_lock);
7b9e0ae6
CW		 379
380 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
c6a828d3 381 new_delay = dev_priv->rps.cur_delay + 1;
7b9e0ae6 382 else
c6a828d3 383 new_delay = dev_priv->rps.cur_delay - 1;
3b8d8d91 384
79249636
BW		 385 /* sysfs frequency interfaces may have snuck in while servicing the
386 * interrupt
387 */
388 if (!(new_delay > dev_priv->rps.max_delay ||
389 new_delay < dev_priv->rps.min_delay)) {
390 gen6_set_rps(dev_priv->dev, new_delay);
391 }
3b8d8d91 392
4fc688ce 393 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91
JB		 394}
395
e3689190
BW		 396
397/**
398 * ivybridge_parity_work - Workqueue called when a parity error interrupt
399 * occurred.
400 * @work: workqueue struct
401 *
402 * Doesn't actually do anything except notify userspace. As a consequence of
403 * this event, userspace should try to remap the bad rows since statistically
404 * it is likely the same row is more likely to go bad again.
405 */
406static void ivybridge_parity_work(struct work_struct *work)
407{
408 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
a4da4fa4 409 l3_parity.error_work);
e3689190
BW		 410 u32 error_status, row, bank, subbank;
411 char *parity_event[5];
412 uint32_t misccpctl;
413 unsigned long flags;
414
415 /* We must turn off DOP level clock gating to access the L3 registers.
416 * In order to prevent a get/put style interface, acquire struct mutex
417 * any time we access those registers.
418 */
419 mutex_lock(&dev_priv->dev->struct_mutex);
420
421 misccpctl = I915_READ(GEN7_MISCCPCTL);
422 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
423 POSTING_READ(GEN7_MISCCPCTL);
424
425 error_status = I915_READ(GEN7_L3CDERRST1);
426 row = GEN7_PARITY_ERROR_ROW(error_status);
427 bank = GEN7_PARITY_ERROR_BANK(error_status);
428 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
429
430 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
431 GEN7_L3CDERRST1_ENABLE);
432 POSTING_READ(GEN7_L3CDERRST1);
433
434 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
435
436 spin_lock_irqsave(&dev_priv->irq_lock, flags);
437 dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
438 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
439 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
440
441 mutex_unlock(&dev_priv->dev->struct_mutex);
442
443 parity_event[0] = "L3_PARITY_ERROR=1";
444 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
445 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
446 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
447 parity_event[4] = NULL;
448
449 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
450 KOBJ_CHANGE, parity_event);
451
452 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
453 row, bank, subbank);
454
455 kfree(parity_event[3]);
456 kfree(parity_event[2]);
457 kfree(parity_event[1]);
458}
459
d2ba8470 460static void ivybridge_handle_parity_error(struct drm_device *dev)
e3689190
BW		 461{
462 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
463 unsigned long flags;
464
e1ef7cc2 465 if (!HAS_L3_GPU_CACHE(dev))
e3689190
BW		 466 return;
467
468 spin_lock_irqsave(&dev_priv->irq_lock, flags);
469 dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
470 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
471 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
472
a4da4fa4 473 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
e3689190
BW		 474}
475
e7b4c6b1
DV		 476static void snb_gt_irq_handler(struct drm_device *dev,
477 struct drm_i915_private *dev_priv,
478 u32 gt_iir)
479{
480
481 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
482 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
483 notify_ring(dev, &dev_priv->ring[RCS]);
484 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
485 notify_ring(dev, &dev_priv->ring[VCS]);
486 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
487 notify_ring(dev, &dev_priv->ring[BCS]);
488
489 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
490 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
491 GT_RENDER_CS_ERROR_INTERRUPT)) {
492 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
493 i915_handle_error(dev, false);
494 }
e3689190
BW		 495
496 if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
497 ivybridge_handle_parity_error(dev);
e7b4c6b1
DV		 498}
499
fc6826d1
CW		 500static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
501 u32 pm_iir)
502{
503 unsigned long flags;
504
505 /*
506 * IIR bits should never already be set because IMR should
507 * prevent an interrupt from being shown in IIR. The warning
508 * displays a case where we've unsafely cleared
c6a828d3 509 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
fc6826d1
CW		 510 * type is not a problem, it displays a problem in the logic.
511 *
c6a828d3 512 * The mask bit in IMR is cleared by dev_priv->rps.work.
fc6826d1
CW		 513 */
514
c6a828d3 515 spin_lock_irqsave(&dev_priv->rps.lock, flags);
c6a828d3
DV		 516 dev_priv->rps.pm_iir |= pm_iir;
517 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
fc6826d1 518 POSTING_READ(GEN6_PMIMR);
c6a828d3 519 spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
fc6826d1 520
c6a828d3 521 queue_work(dev_priv->wq, &dev_priv->rps.work);
fc6826d1
CW		 522}
523
ff1f525e 524static irqreturn_t valleyview_irq_handler(int irq, void *arg)
7e231dbe
JB		 525{
526 struct drm_device *dev = (struct drm_device *) arg;
527 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
528 u32 iir, gt_iir, pm_iir;
529 irqreturn_t ret = IRQ_NONE;
530 unsigned long irqflags;
531 int pipe;
532 u32 pipe_stats[I915_MAX_PIPES];
7e231dbe
JB		 533
534 atomic_inc(&dev_priv->irq_received);
535
7e231dbe
JB		 536 while (true) {
537 iir = I915_READ(VLV_IIR);
538 gt_iir = I915_READ(GTIIR);
539 pm_iir = I915_READ(GEN6_PMIIR);
540
541 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
542 goto out;
543
544 ret = IRQ_HANDLED;
545
e7b4c6b1 546 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 547
548 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
549 for_each_pipe(pipe) {
550 int reg = PIPESTAT(pipe);
551 pipe_stats[pipe] = I915_READ(reg);
552
553 /*
554 * Clear the PIPE*STAT regs before the IIR
555 */
556 if (pipe_stats[pipe] & 0x8000ffff) {
557 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
558 DRM_DEBUG_DRIVER("pipe %c underrun\n",
559 pipe_name(pipe));
560 I915_WRITE(reg, pipe_stats[pipe]);
561 }
562 }
563 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
564
31acc7f5
JB		 565 for_each_pipe(pipe) {
566 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
567 drm_handle_vblank(dev, pipe);
568
569 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
570 intel_prepare_page_flip(dev, pipe);
571 intel_finish_page_flip(dev, pipe);
572 }
573 }
574
7e231dbe
JB		 575 /* Consume port. Then clear IIR or we'll miss events */
576 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
577 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
578
579 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
580 hotplug_status);
581 if (hotplug_status & dev_priv->hotplug_supported_mask)
582 queue_work(dev_priv->wq,
583 &dev_priv->hotplug_work);
584
585 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
586 I915_READ(PORT_HOTPLUG_STAT);
587 }
588
fc6826d1
CW		 589 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
590 gen6_queue_rps_work(dev_priv, pm_iir);
7e231dbe
JB		 591
592 I915_WRITE(GTIIR, gt_iir);
593 I915_WRITE(GEN6_PMIIR, pm_iir);
594 I915_WRITE(VLV_IIR, iir);
595 }
596
597out:
598 return ret;
599}
600
23e81d69 601static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 602{
603 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 604 int pipe;
776ad806 605
76e43830
DV		 606 if (pch_iir & SDE_HOTPLUG_MASK)
607 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
608
776ad806
JB		 609 if (pch_iir & SDE_AUDIO_POWER_MASK)
610 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
611 (pch_iir & SDE_AUDIO_POWER_MASK) >>
612 SDE_AUDIO_POWER_SHIFT);
613
614 if (pch_iir & SDE_GMBUS)
615 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
616
617 if (pch_iir & SDE_AUDIO_HDCP_MASK)
618 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
619
620 if (pch_iir & SDE_AUDIO_TRANS_MASK)
621 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
622
623 if (pch_iir & SDE_POISON)
624 DRM_ERROR("PCH poison interrupt\n");
625
9db4a9c7
JB		 626 if (pch_iir & SDE_FDI_MASK)
627 for_each_pipe(pipe)
628 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
629 pipe_name(pipe),
630 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 631
632 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
633 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
634
635 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
636 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
637
638 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
639 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
640 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
641 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
642}
643
23e81d69
AJ		 644static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
645{
646 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
647 int pipe;
648
76e43830
DV		 649 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
650 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
651
23e81d69
AJ		 652 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
653 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
654 (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
655 SDE_AUDIO_POWER_SHIFT_CPT);
656
657 if (pch_iir & SDE_AUX_MASK_CPT)
658 DRM_DEBUG_DRIVER("AUX channel interrupt\n");
659
660 if (pch_iir & SDE_GMBUS_CPT)
661 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
662
663 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
664 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
665
666 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
667 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
668
669 if (pch_iir & SDE_FDI_MASK_CPT)
670 for_each_pipe(pipe)
671 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
672 pipe_name(pipe),
673 I915_READ(FDI_RX_IIR(pipe)));
674}
675
ff1f525e 676static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
b1f14ad0
JB		 677{
678 struct drm_device *dev = (struct drm_device *) arg;
679 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
0e43406b
CW		 680 u32 de_iir, gt_iir, de_ier, pm_iir;
681 irqreturn_t ret = IRQ_NONE;
682 int i;
b1f14ad0
JB		 683
684 atomic_inc(&dev_priv->irq_received);
685
686 /* disable master interrupt before clearing iir */
687 de_ier = I915_READ(DEIER);
688 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
b1f14ad0 689
b1f14ad0 690 gt_iir = I915_READ(GTIIR);
0e43406b
CW		 691 if (gt_iir) {
692 snb_gt_irq_handler(dev, dev_priv, gt_iir);
693 I915_WRITE(GTIIR, gt_iir);
694 ret = IRQ_HANDLED;
b1f14ad0
JB		 695 }
696
0e43406b
CW		 697 de_iir = I915_READ(DEIIR);
698 if (de_iir) {
699 if (de_iir & DE_GSE_IVB)
700 intel_opregion_gse_intr(dev);
701
702 for (i = 0; i < 3; i++) {
74d44445
DV		 703 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
704 drm_handle_vblank(dev, i);
0e43406b
CW		 705 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
706 intel_prepare_page_flip(dev, i);
707 intel_finish_page_flip_plane(dev, i);
708 }
0e43406b 709 }
b615b57a 710
0e43406b
CW		 711 /* check event from PCH */
712 if (de_iir & DE_PCH_EVENT_IVB) {
713 u32 pch_iir = I915_READ(SDEIIR);
b1f14ad0 714
23e81d69 715 cpt_irq_handler(dev, pch_iir);
b1f14ad0 716
0e43406b
CW		 717 /* clear PCH hotplug event before clear CPU irq */
718 I915_WRITE(SDEIIR, pch_iir);
719 }
b615b57a 720
0e43406b
CW		 721 I915_WRITE(DEIIR, de_iir);
722 ret = IRQ_HANDLED;
b1f14ad0
JB		 723 }
724
0e43406b
CW		 725 pm_iir = I915_READ(GEN6_PMIIR);
726 if (pm_iir) {
727 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
728 gen6_queue_rps_work(dev_priv, pm_iir);
729 I915_WRITE(GEN6_PMIIR, pm_iir);
730 ret = IRQ_HANDLED;
731 }
b1f14ad0 732
b1f14ad0
JB		 733 I915_WRITE(DEIER, de_ier);
734 POSTING_READ(DEIER);
735
736 return ret;
737}
738
e7b4c6b1
DV		 739static void ilk_gt_irq_handler(struct drm_device *dev,
740 struct drm_i915_private *dev_priv,
741 u32 gt_iir)
742{
743 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
744 notify_ring(dev, &dev_priv->ring[RCS]);
745 if (gt_iir & GT_BSD_USER_INTERRUPT)
746 notify_ring(dev, &dev_priv->ring[VCS]);
747}
748
ff1f525e 749static irqreturn_t ironlake_irq_handler(int irq, void *arg)
036a4a7d 750{
4697995b 751 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 752 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
753 int ret = IRQ_NONE;
acd15b6c 754 u32 de_iir, gt_iir, de_ier, pm_iir;
881f47b6 755
4697995b
JB		 756 atomic_inc(&dev_priv->irq_received);
757
2d109a84
ZN		 758 /* disable master interrupt before clearing iir */
759 de_ier = I915_READ(DEIER);
760 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 761 POSTING_READ(DEIER);
2d109a84 762
036a4a7d
ZW		 763 de_iir = I915_READ(DEIIR);
764 gt_iir = I915_READ(GTIIR);
3b8d8d91 765 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 766
acd15b6c 767 if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 768 goto done;
036a4a7d 769
c7c85101 770 ret = IRQ_HANDLED;
036a4a7d 771
e7b4c6b1
DV		 772 if (IS_GEN5(dev))
773 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
774 else
775 snb_gt_irq_handler(dev, dev_priv, gt_iir);
01c66889 776
c7c85101 777 if (de_iir & DE_GSE)
3b617967 778 intel_opregion_gse_intr(dev);
c650156a 779
74d44445
DV		 780 if (de_iir & DE_PIPEA_VBLANK)
781 drm_handle_vblank(dev, 0);
782
783 if (de_iir & DE_PIPEB_VBLANK)
784 drm_handle_vblank(dev, 1);
785
f072d2e7 786 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 787 intel_prepare_page_flip(dev, 0);
2bbda389 788 intel_finish_page_flip_plane(dev, 0);
f072d2e7 789 }
013d5aa2 790
f072d2e7 791 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 792 intel_prepare_page_flip(dev, 1);
2bbda389 793 intel_finish_page_flip_plane(dev, 1);
f072d2e7 794 }
013d5aa2 795
c7c85101 796 /* check event from PCH */
776ad806 797 if (de_iir & DE_PCH_EVENT) {
acd15b6c
DV		 798 u32 pch_iir = I915_READ(SDEIIR);
799
23e81d69
AJ		 800 if (HAS_PCH_CPT(dev))
801 cpt_irq_handler(dev, pch_iir);
802 else
803 ibx_irq_handler(dev, pch_iir);
acd15b6c
DV		 804
805 /* should clear PCH hotplug event before clear CPU irq */
806 I915_WRITE(SDEIIR, pch_iir);
776ad806 807 }
036a4a7d 808
73edd18f
DV		 809 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
810 ironlake_handle_rps_change(dev);
f97108d1 811
fc6826d1
CW		 812 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
813 gen6_queue_rps_work(dev_priv, pm_iir);
3b8d8d91 814
c7c85101
ZN		 815 I915_WRITE(GTIIR, gt_iir);
816 I915_WRITE(DEIIR, de_iir);
4912d041 817 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 818
819done:
2d109a84 820 I915_WRITE(DEIER, de_ier);
3143a2bf 821 POSTING_READ(DEIER);
2d109a84 822
036a4a7d
ZW		 823 return ret;
824}
825
8a905236
JB		 826/**
827 * i915_error_work_func - do process context error handling work
828 * @work: work struct
829 *
830 * Fire an error uevent so userspace can see that a hang or error
831 * was detected.
832 */
833static void i915_error_work_func(struct work_struct *work)
834{
835 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
836 error_work);
837 struct drm_device *dev = dev_priv->dev;
f316a42c
BG		 838 char *error_event[] = { "ERROR=1", NULL };
839 char *reset_event[] = { "RESET=1", NULL };
840 char *reset_done_event[] = { "ERROR=0", NULL };
8a905236 841
f316a42c
BG		 842 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
843
ba1234d1 844 if (atomic_read(&dev_priv->mm.wedged)) {
f803aa55
CW		 845 DRM_DEBUG_DRIVER("resetting chip\n");
846 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
d4b8bb2a 847 if (!i915_reset(dev)) {
f803aa55
CW		 848 atomic_set(&dev_priv->mm.wedged, 0);
849 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
f316a42c 850 }
30dbf0c0 851 complete_all(&dev_priv->error_completion);
f316a42c 852 }
8a905236
JB		 853}
854
85f9e50d
DV		 855/* NB: please notice the memset */
856static void i915_get_extra_instdone(struct drm_device *dev,
857 uint32_t *instdone)
858{
859 struct drm_i915_private *dev_priv = dev->dev_private;
860 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
861
862 switch(INTEL_INFO(dev)->gen) {
863 case 2:
864 case 3:
865 instdone[0] = I915_READ(INSTDONE);
866 break;
867 case 4:
868 case 5:
869 case 6:
870 instdone[0] = I915_READ(INSTDONE_I965);
871 instdone[1] = I915_READ(INSTDONE1);
872 break;
873 default:
874 WARN_ONCE(1, "Unsupported platform\n");
875 case 7:
876 instdone[0] = I915_READ(GEN7_INSTDONE_1);
877 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
878 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
879 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
880 break;
881 }
882}
883
3bd3c932 884#ifdef CONFIG_DEBUG_FS
9df30794 885static struct drm_i915_error_object *
bcfb2e28 886i915_error_object_create(struct drm_i915_private *dev_priv,
05394f39 887 struct drm_i915_gem_object *src)
9df30794
CW		 888{
889 struct drm_i915_error_object *dst;
9da3da66 890 int i, count;
e56660dd 891 u32 reloc_offset;
9df30794 892
05394f39 893 if (src == NULL || src->pages == NULL)
9df30794
CW		 894 return NULL;
895
9da3da66 896 count = src->base.size / PAGE_SIZE;
9df30794 897
9da3da66 898 dst = kmalloc(sizeof(*dst) + count * sizeof(u32 *), GFP_ATOMIC);
9df30794
CW		 899 if (dst == NULL)
900 return NULL;
901
05394f39 902 reloc_offset = src->gtt_offset;
9da3da66 903 for (i = 0; i < count; i++) {
788885ae 904 unsigned long flags;
e56660dd 905 void *d;
788885ae 906
e56660dd 907 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 908 if (d == NULL)
909 goto unwind;
e56660dd 910
788885ae 911 local_irq_save(flags);
74898d7e
DV		 912 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
913 src->has_global_gtt_mapping) {
172975aa
CW		 914 void __iomem *s;
915
916 /* Simply ignore tiling or any overlapping fence.
917 * It's part of the error state, and this hopefully
918 * captures what the GPU read.
919 */
920
921 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
922 reloc_offset);
923 memcpy_fromio(d, s, PAGE_SIZE);
924 io_mapping_unmap_atomic(s);
960e3564
CW		 925 } else if (src->stolen) {
926 unsigned long offset;
927
928 offset = dev_priv->mm.stolen_base;
929 offset += src->stolen->start;
930 offset += i << PAGE_SHIFT;
931
1a240d4d 932 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
172975aa 933 } else {
9da3da66 934 struct page *page;
172975aa
CW		 935 void *s;
936
9da3da66 937 page = i915_gem_object_get_page(src, i);
172975aa 938
9da3da66
CW		 939 drm_clflush_pages(&page, 1);
940
941 s = kmap_atomic(page);
172975aa
CW		 942 memcpy(d, s, PAGE_SIZE);
943 kunmap_atomic(s);
944
9da3da66 945 drm_clflush_pages(&page, 1);
172975aa 946 }
788885ae 947 local_irq_restore(flags);
e56660dd 948
9da3da66 949 dst->pages[i] = d;
e56660dd
CW		 950
951 reloc_offset += PAGE_SIZE;
9df30794 952 }
9da3da66 953 dst->page_count = count;
05394f39 954 dst->gtt_offset = src->gtt_offset;
9df30794
CW		 955
956 return dst;
957
958unwind:
9da3da66
CW		 959 while (i--)
960 kfree(dst->pages[i]);
9df30794
CW		 961 kfree(dst);
962 return NULL;
963}
964
965static void
966i915_error_object_free(struct drm_i915_error_object *obj)
967{
968 int page;
969
970 if (obj == NULL)
971 return;
972
973 for (page = 0; page < obj->page_count; page++)
974 kfree(obj->pages[page]);
975
976 kfree(obj);
977}
978
742cbee8
DV		 979void
980i915_error_state_free(struct kref *error_ref)
9df30794 981{
742cbee8
DV		 982 struct drm_i915_error_state *error = container_of(error_ref,
983 typeof(*error), ref);
e2f973d5
CW		 984 int i;
985
52d39a21
CW		 986 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
987 i915_error_object_free(error->ring[i].batchbuffer);
988 i915_error_object_free(error->ring[i].ringbuffer);
989 kfree(error->ring[i].requests);
990 }
e2f973d5 991
9df30794 992 kfree(error->active_bo);
6ef3d427 993 kfree(error->overlay);
9df30794
CW		 994 kfree(error);
995}
1b50247a
CW		 996static void capture_bo(struct drm_i915_error_buffer *err,
997 struct drm_i915_gem_object *obj)
998{
999 err->size = obj->base.size;
1000 err->name = obj->base.name;
0201f1ec
CW		 1001 err->rseqno = obj->last_read_seqno;
1002 err->wseqno = obj->last_write_seqno;
1b50247a
CW		 1003 err->gtt_offset = obj->gtt_offset;
1004 err->read_domains = obj->base.read_domains;
1005 err->write_domain = obj->base.write_domain;
1006 err->fence_reg = obj->fence_reg;
1007 err->pinned = 0;
1008 if (obj->pin_count > 0)
1009 err->pinned = 1;
1010 if (obj->user_pin_count > 0)
1011 err->pinned = -1;
1012 err->tiling = obj->tiling_mode;
1013 err->dirty = obj->dirty;
1014 err->purgeable = obj->madv != I915_MADV_WILLNEED;
1015 err->ring = obj->ring ? obj->ring->id : -1;
1016 err->cache_level = obj->cache_level;
1017}
9df30794 1018
1b50247a
CW		 1019static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1020 int count, struct list_head *head)
c724e8a9
CW		 1021{
1022 struct drm_i915_gem_object *obj;
1023 int i = 0;
1024
1025 list_for_each_entry(obj, head, mm_list) {
1b50247a 1026 capture_bo(err++, obj);
c724e8a9
CW		 1027 if (++i == count)
1028 break;
1b50247a
CW		 1029 }
1030
1031 return i;
1032}
1033
1034static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1035 int count, struct list_head *head)
1036{
1037 struct drm_i915_gem_object *obj;
1038 int i = 0;
1039
1040 list_for_each_entry(obj, head, gtt_list) {
1041 if (obj->pin_count == 0)
1042 continue;
c724e8a9 1043
1b50247a
CW		 1044 capture_bo(err++, obj);
1045 if (++i == count)
1046 break;
c724e8a9
CW		 1047 }
1048
1049 return i;
1050}
1051
748ebc60
CW		 1052static void i915_gem_record_fences(struct drm_device *dev,
1053 struct drm_i915_error_state *error)
1054{
1055 struct drm_i915_private *dev_priv = dev->dev_private;
1056 int i;
1057
1058 /* Fences */
1059 switch (INTEL_INFO(dev)->gen) {
775d17b6 1060 case 7:
748ebc60
CW		 1061 case 6:
1062 for (i = 0; i < 16; i++)
1063 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1064 break;
1065 case 5:
1066 case 4:
1067 for (i = 0; i < 16; i++)
1068 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1069 break;
1070 case 3:
1071 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1072 for (i = 0; i < 8; i++)
1073 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1074 case 2:
1075 for (i = 0; i < 8; i++)
1076 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1077 break;
1078
1079 }
1080}
1081
bcfb2e28
CW		 1082static struct drm_i915_error_object *
1083i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1084 struct intel_ring_buffer *ring)
1085{
1086 struct drm_i915_gem_object *obj;
1087 u32 seqno;
1088
1089 if (!ring->get_seqno)
1090 return NULL;
1091
b2eadbc8 1092 seqno = ring->get_seqno(ring, false);
bcfb2e28
CW		 1093 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1094 if (obj->ring != ring)
1095 continue;
1096
0201f1ec 1097 if (i915_seqno_passed(seqno, obj->last_read_seqno))
bcfb2e28
CW		 1098 continue;
1099
1100 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1101 continue;
1102
1103 /* We need to copy these to an anonymous buffer as the simplest
1104 * method to avoid being overwritten by userspace.
1105 */
1106 return i915_error_object_create(dev_priv, obj);
1107 }
1108
1109 return NULL;
1110}
1111
d27b1e0e
DV		 1112static void i915_record_ring_state(struct drm_device *dev,
1113 struct drm_i915_error_state *error,
1114 struct intel_ring_buffer *ring)
1115{
1116 struct drm_i915_private *dev_priv = dev->dev_private;
1117
33f3f518 1118 if (INTEL_INFO(dev)->gen >= 6) {
12f55818 1119 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
33f3f518 1120 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
7e3b8737
DV		 1121 error->semaphore_mboxes[ring->id][0]
1122 = I915_READ(RING_SYNC_0(ring->mmio_base));
1123 error->semaphore_mboxes[ring->id][1]
1124 = I915_READ(RING_SYNC_1(ring->mmio_base));
df2b23d9
CW		 1125 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
1126 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
33f3f518 1127 }
c1cd90ed 1128
d27b1e0e 1129 if (INTEL_INFO(dev)->gen >= 4) {
9d2f41fa 1130 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
d27b1e0e
DV		 1131 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1132 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1133 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
c1cd90ed 1134 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
050ee91f 1135 if (ring->id == RCS)
d27b1e0e 1136 error->bbaddr = I915_READ64(BB_ADDR);
d27b1e0e 1137 } else {
9d2f41fa 1138 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
d27b1e0e
DV		 1139 error->ipeir[ring->id] = I915_READ(IPEIR);
1140 error->ipehr[ring->id] = I915_READ(IPEHR);
1141 error->instdone[ring->id] = I915_READ(INSTDONE);
d27b1e0e
DV		 1142 }
1143
9574b3fe 1144 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
c1cd90ed 1145 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
b2eadbc8 1146 error->seqno[ring->id] = ring->get_seqno(ring, false);
d27b1e0e 1147 error->acthd[ring->id] = intel_ring_get_active_head(ring);
c1cd90ed
DV		 1148 error->head[ring->id] = I915_READ_HEAD(ring);
1149 error->tail[ring->id] = I915_READ_TAIL(ring);
7e3b8737
DV		 1150
1151 error->cpu_ring_head[ring->id] = ring->head;
1152 error->cpu_ring_tail[ring->id] = ring->tail;
d27b1e0e
DV		 1153}
1154
52d39a21
CW		 1155static void i915_gem_record_rings(struct drm_device *dev,
1156 struct drm_i915_error_state *error)
1157{
1158 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 1159 struct intel_ring_buffer *ring;
52d39a21
CW		 1160 struct drm_i915_gem_request *request;
1161 int i, count;
1162
b4519513 1163 for_each_ring(ring, dev_priv, i) {
52d39a21
CW		 1164 i915_record_ring_state(dev, error, ring);
1165
1166 error->ring[i].batchbuffer =
1167 i915_error_first_batchbuffer(dev_priv, ring);
1168
1169 error->ring[i].ringbuffer =
1170 i915_error_object_create(dev_priv, ring->obj);
1171
1172 count = 0;
1173 list_for_each_entry(request, &ring->request_list, list)
1174 count++;
1175
1176 error->ring[i].num_requests = count;
1177 error->ring[i].requests =
1178 kmalloc(count*sizeof(struct drm_i915_error_request),
1179 GFP_ATOMIC);
1180 if (error->ring[i].requests == NULL) {
1181 error->ring[i].num_requests = 0;
1182 continue;
1183 }
1184
1185 count = 0;
1186 list_for_each_entry(request, &ring->request_list, list) {
1187 struct drm_i915_error_request *erq;
1188
1189 erq = &error->ring[i].requests[count++];
1190 erq->seqno = request->seqno;
1191 erq->jiffies = request->emitted_jiffies;
ee4f42b1 1192 erq->tail = request->tail;
52d39a21
CW		 1193 }
1194 }
1195}
1196
8a905236
JB		 1197/**
1198 * i915_capture_error_state - capture an error record for later analysis
1199 * @dev: drm device
1200 *
1201 * Should be called when an error is detected (either a hang or an error
1202 * interrupt) to capture error state from the time of the error. Fills
1203 * out a structure which becomes available in debugfs for user level tools
1204 * to pick up.
1205 */
63eeaf38
JB		 1206static void i915_capture_error_state(struct drm_device *dev)
1207{
1208 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1209 struct drm_i915_gem_object *obj;
63eeaf38
JB		 1210 struct drm_i915_error_state *error;
1211 unsigned long flags;
9db4a9c7 1212 int i, pipe;
63eeaf38
JB		 1213
1214 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1215 error = dev_priv->first_error;
1216 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1217 if (error)
1218 return;
63eeaf38 1219
9db4a9c7 1220 /* Account for pipe specific data like PIPE*STAT */
33f3f518 1221 error = kzalloc(sizeof(*error), GFP_ATOMIC);
63eeaf38 1222 if (!error) {
9df30794
CW		 1223 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1224 return;
63eeaf38
JB		 1225 }
1226
b6f7833b
CW		 1227 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1228 dev->primary->index);
2fa772f3 1229
742cbee8 1230 kref_init(&error->ref);
63eeaf38
JB		 1231 error->eir = I915_READ(EIR);
1232 error->pgtbl_er = I915_READ(PGTBL_ER);
b9a3906b 1233 error->ccid = I915_READ(CCID);
be998e2e
BW		 1234
1235 if (HAS_PCH_SPLIT(dev))
1236 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1237 else if (IS_VALLEYVIEW(dev))
1238 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1239 else if (IS_GEN2(dev))
1240 error->ier = I915_READ16(IER);
1241 else
1242 error->ier = I915_READ(IER);
1243
9db4a9c7
JB		 1244 for_each_pipe(pipe)
1245 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
d27b1e0e 1246
33f3f518 1247 if (INTEL_INFO(dev)->gen >= 6) {
f406839f 1248 error->error = I915_READ(ERROR_GEN6);
33f3f518
DV		 1249 error->done_reg = I915_READ(DONE_REG);
1250 }
d27b1e0e 1251
71e172e8
BW		 1252 if (INTEL_INFO(dev)->gen == 7)
1253 error->err_int = I915_READ(GEN7_ERR_INT);
1254
050ee91f
BW		 1255 i915_get_extra_instdone(dev, error->extra_instdone);
1256
748ebc60 1257 i915_gem_record_fences(dev, error);
52d39a21 1258 i915_gem_record_rings(dev, error);
9df30794 1259
c724e8a9 1260 /* Record buffers on the active and pinned lists. */
9df30794 1261 error->active_bo = NULL;
c724e8a9 1262 error->pinned_bo = NULL;
9df30794 1263
bcfb2e28
CW		 1264 i = 0;
1265 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1266 i++;
1267 error->active_bo_count = i;
6c085a72 1268 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
1b50247a
CW		 1269 if (obj->pin_count)
1270 i++;
bcfb2e28 1271 error->pinned_bo_count = i - error->active_bo_count;
c724e8a9 1272
8e934dbf
CW		 1273 error->active_bo = NULL;
1274 error->pinned_bo = NULL;
bcfb2e28
CW		 1275 if (i) {
1276 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
9df30794 1277 GFP_ATOMIC);
c724e8a9
CW		 1278 if (error->active_bo)
1279 error->pinned_bo =
1280 error->active_bo + error->active_bo_count;
9df30794
CW		 1281 }
1282
c724e8a9
CW		 1283 if (error->active_bo)
1284 error->active_bo_count =
1b50247a
CW		 1285 capture_active_bo(error->active_bo,
1286 error->active_bo_count,
1287 &dev_priv->mm.active_list);
c724e8a9
CW		 1288
1289 if (error->pinned_bo)
1290 error->pinned_bo_count =
1b50247a
CW		 1291 capture_pinned_bo(error->pinned_bo,
1292 error->pinned_bo_count,
6c085a72 1293 &dev_priv->mm.bound_list);
c724e8a9 1294
9df30794
CW		 1295 do_gettimeofday(&error->time);
1296
6ef3d427 1297 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 1298 error->display = intel_display_capture_error_state(dev);
6ef3d427 1299
9df30794
CW		 1300 spin_lock_irqsave(&dev_priv->error_lock, flags);
1301 if (dev_priv->first_error == NULL) {
1302 dev_priv->first_error = error;
1303 error = NULL;
1304 }
63eeaf38 1305 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1306
1307 if (error)
742cbee8 1308 i915_error_state_free(&error->ref);
9df30794
CW		 1309}
1310
1311void i915_destroy_error_state(struct drm_device *dev)
1312{
1313 struct drm_i915_private *dev_priv = dev->dev_private;
1314 struct drm_i915_error_state *error;
6dc0e816 1315 unsigned long flags;
9df30794 1316
6dc0e816 1317 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1318 error = dev_priv->first_error;
1319 dev_priv->first_error = NULL;
6dc0e816 1320 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1321
1322 if (error)
742cbee8 1323 kref_put(&error->ref, i915_error_state_free);
63eeaf38 1324}
3bd3c932
CW		 1325#else
1326#define i915_capture_error_state(x)
1327#endif
63eeaf38 1328
35aed2e6 1329static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1330{
1331 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 1332 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 1333 u32 eir = I915_READ(EIR);
050ee91f 1334 int pipe, i;
8a905236 1335
35aed2e6
CW		 1336 if (!eir)
1337 return;
8a905236 1338
a70491cc 1339 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 1340
bd9854f9
BW		 1341 i915_get_extra_instdone(dev, instdone);
1342
8a905236
JB		 1343 if (IS_G4X(dev)) {
1344 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1345 u32 ipeir = I915_READ(IPEIR_I965);
1346
a70491cc
JP		 1347 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1348 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 1349 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1350 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 1351 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1352 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1353 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1354 POSTING_READ(IPEIR_I965);
8a905236
JB		 1355 }
1356 if (eir & GM45_ERROR_PAGE_TABLE) {
1357 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1358 pr_err("page table error\n");
1359 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1360 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1361 POSTING_READ(PGTBL_ER);
8a905236
JB		 1362 }
1363 }
1364
a6c45cf0 1365 if (!IS_GEN2(dev)) {
8a905236
JB		 1366 if (eir & I915_ERROR_PAGE_TABLE) {
1367 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1368 pr_err("page table error\n");
1369 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1370 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1371 POSTING_READ(PGTBL_ER);
8a905236
JB		 1372 }
1373 }
1374
1375 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 1376 pr_err("memory refresh error:\n");
9db4a9c7 1377 for_each_pipe(pipe)
a70491cc 1378 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 1379 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 1380 /* pipestat has already been acked */
1381 }
1382 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 1383 pr_err("instruction error\n");
1384 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 1385 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1386 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 1387 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 1388 u32 ipeir = I915_READ(IPEIR);
1389
a70491cc
JP		 1390 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1391 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 1392 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 1393 I915_WRITE(IPEIR, ipeir);
3143a2bf 1394 POSTING_READ(IPEIR);
8a905236
JB		 1395 } else {
1396 u32 ipeir = I915_READ(IPEIR_I965);
1397
a70491cc
JP		 1398 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1399 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 1400 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1401 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1402 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1403 POSTING_READ(IPEIR_I965);
8a905236
JB		 1404 }
1405 }
1406
1407 I915_WRITE(EIR, eir);
3143a2bf 1408 POSTING_READ(EIR);
8a905236
JB		 1409 eir = I915_READ(EIR);
1410 if (eir) {
1411 /*
1412 * some errors might have become stuck,
1413 * mask them.
1414 */
1415 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1416 I915_WRITE(EMR, I915_READ(EMR) | eir);
1417 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1418 }
35aed2e6
CW		 1419}
1420
1421/**
1422 * i915_handle_error - handle an error interrupt
1423 * @dev: drm device
1424 *
1425 * Do some basic checking of regsiter state at error interrupt time and
1426 * dump it to the syslog. Also call i915_capture_error_state() to make
1427 * sure we get a record and make it available in debugfs. Fire a uevent
1428 * so userspace knows something bad happened (should trigger collection
1429 * of a ring dump etc.).
1430 */
527f9e90 1431void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 1432{
1433 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513
CW		 1434 struct intel_ring_buffer *ring;
1435 int i;
35aed2e6
CW		 1436
1437 i915_capture_error_state(dev);
1438 i915_report_and_clear_eir(dev);
8a905236 1439
ba1234d1 1440 if (wedged) {
30dbf0c0 1441 INIT_COMPLETION(dev_priv->error_completion);
ba1234d1
BG		 1442 atomic_set(&dev_priv->mm.wedged, 1);
1443
11ed50ec
BG		 1444 /*
1445 * Wakeup waiting processes so they don't hang
1446 */
b4519513
CW		 1447 for_each_ring(ring, dev_priv, i)
1448 wake_up_all(&ring->irq_queue);
11ed50ec
BG		 1449 }
1450
9c9fe1f8 1451 queue_work(dev_priv->wq, &dev_priv->error_work);
8a905236
JB		 1452}
1453
4e5359cd
SF		 1454static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1455{
1456 drm_i915_private_t *dev_priv = dev->dev_private;
1457 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1458 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 1459 struct drm_i915_gem_object *obj;
4e5359cd
SF		 1460 struct intel_unpin_work *work;
1461 unsigned long flags;
1462 bool stall_detected;
1463
1464 /* Ignore early vblank irqs */
1465 if (intel_crtc == NULL)
1466 return;
1467
1468 spin_lock_irqsave(&dev->event_lock, flags);
1469 work = intel_crtc->unpin_work;
1470
1471 if (work == NULL || work->pending || !work->enable_stall_check) {
1472 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1473 spin_unlock_irqrestore(&dev->event_lock, flags);
1474 return;
1475 }
1476
1477 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 1478 obj = work->pending_flip_obj;
a6c45cf0 1479 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 1480 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545
AR		 1481 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1482 obj->gtt_offset;
4e5359cd 1483 } else {
9db4a9c7 1484 int dspaddr = DSPADDR(intel_crtc->plane);
05394f39 1485 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
01f2c773 1486 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 1487 crtc->x * crtc->fb->bits_per_pixel/8);
1488 }
1489
1490 spin_unlock_irqrestore(&dev->event_lock, flags);
1491
1492 if (stall_detected) {
1493 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1494 intel_prepare_page_flip(dev, intel_crtc->plane);
1495 }
1496}
1497
42f52ef8
KP		 1498/* Called from drm generic code, passed 'crtc' which
1499 * we use as a pipe index
1500 */
f71d4af4 1501static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1502{
1503 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1504 unsigned long irqflags;
71e0ffa5 1505
5eddb70b 1506 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 1507 return -EINVAL;
0a3e67a4 1508
1ec14ad3 1509 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 1510 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 1511 i915_enable_pipestat(dev_priv, pipe,
1512 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 1513 else
7c463586
KP		 1514 i915_enable_pipestat(dev_priv, pipe,
1515 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 1516
1517 /* maintain vblank delivery even in deep C-states */
1518 if (dev_priv->info->gen == 3)
6b26c86d 1519 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 1520 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 1521
0a3e67a4
JB		 1522 return 0;
1523}
1524
f71d4af4 1525static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1526{
1527 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1528 unsigned long irqflags;
1529
1530 if (!i915_pipe_enabled(dev, pipe))
1531 return -EINVAL;
1532
1533 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1534 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1535 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
f796cf8f
JB		 1536 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1537
1538 return 0;
1539}
1540
f71d4af4 1541static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1542{
1543 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1544 unsigned long irqflags;
1545
1546 if (!i915_pipe_enabled(dev, pipe))
1547 return -EINVAL;
1548
1549 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1550 ironlake_enable_display_irq(dev_priv,
1551 DE_PIPEA_VBLANK_IVB << (5 * pipe));
b1f14ad0
JB		 1552 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1553
1554 return 0;
1555}
1556
7e231dbe
JB		 1557static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1558{
1559 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1560 unsigned long irqflags;
31acc7f5 1561 u32 imr;
7e231dbe
JB		 1562
1563 if (!i915_pipe_enabled(dev, pipe))
1564 return -EINVAL;
1565
1566 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7e231dbe 1567 imr = I915_READ(VLV_IMR);
31acc7f5 1568 if (pipe == 0)
7e231dbe 1569 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1570 else
7e231dbe 1571 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1572 I915_WRITE(VLV_IMR, imr);
31acc7f5
JB		 1573 i915_enable_pipestat(dev_priv, pipe,
1574 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe
JB		 1575 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1576
1577 return 0;
1578}
1579
42f52ef8
KP		 1580/* Called from drm generic code, passed 'crtc' which
1581 * we use as a pipe index
1582 */
f71d4af4 1583static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1584{
1585 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1586 unsigned long irqflags;
0a3e67a4 1587
1ec14ad3 1588 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 1589 if (dev_priv->info->gen == 3)
6b26c86d 1590 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 1591
f796cf8f
JB		 1592 i915_disable_pipestat(dev_priv, pipe,
1593 PIPE_VBLANK_INTERRUPT_ENABLE |
1594 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1595 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1596}
1597
f71d4af4 1598static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1599{
1600 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1601 unsigned long irqflags;
1602
1603 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1604 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1605 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1ec14ad3 1606 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 1607}
1608
f71d4af4 1609static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1610{
1611 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1612 unsigned long irqflags;
1613
1614 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1615 ironlake_disable_display_irq(dev_priv,
1616 DE_PIPEA_VBLANK_IVB << (pipe * 5));
b1f14ad0
JB		 1617 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1618}
1619
7e231dbe
JB		 1620static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1621{
1622 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1623 unsigned long irqflags;
31acc7f5 1624 u32 imr;
7e231dbe
JB		 1625
1626 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5
JB		 1627 i915_disable_pipestat(dev_priv, pipe,
1628 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe 1629 imr = I915_READ(VLV_IMR);
31acc7f5 1630 if (pipe == 0)
7e231dbe 1631 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1632 else
7e231dbe 1633 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1634 I915_WRITE(VLV_IMR, imr);
7e231dbe
JB		 1635 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1636}
1637
893eead0
CW		 1638static u32
1639ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 1640{
893eead0
CW		 1641 return list_entry(ring->request_list.prev,
1642 struct drm_i915_gem_request, list)->seqno;
1643}
1644
1645static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1646{
1647 if (list_empty(&ring->request_list) ||
b2eadbc8
CW		 1648 i915_seqno_passed(ring->get_seqno(ring, false),
1649 ring_last_seqno(ring))) {
893eead0 1650 /* Issue a wake-up to catch stuck h/w. */
9574b3fe
BW		 1651 if (waitqueue_active(&ring->irq_queue)) {
1652 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1653 ring->name);
893eead0
CW		 1654 wake_up_all(&ring->irq_queue);
1655 *err = true;
1656 }
1657 return true;
1658 }
1659 return false;
f65d9421
BG		 1660}
1661
1ec14ad3
CW		 1662static bool kick_ring(struct intel_ring_buffer *ring)
1663{
1664 struct drm_device *dev = ring->dev;
1665 struct drm_i915_private *dev_priv = dev->dev_private;
1666 u32 tmp = I915_READ_CTL(ring);
1667 if (tmp & RING_WAIT) {
1668 DRM_ERROR("Kicking stuck wait on %s\n",
1669 ring->name);
1670 I915_WRITE_CTL(ring, tmp);
1671 return true;
1672 }
1ec14ad3
CW		 1673 return false;
1674}
1675
d1e61e7f
CW		 1676static bool i915_hangcheck_hung(struct drm_device *dev)
1677{
1678 drm_i915_private_t *dev_priv = dev->dev_private;
1679
1680 if (dev_priv->hangcheck_count++ > 1) {
b4519513
CW		 1681 bool hung = true;
1682
d1e61e7f
CW		 1683 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1684 i915_handle_error(dev, true);
1685
1686 if (!IS_GEN2(dev)) {
b4519513
CW		 1687 struct intel_ring_buffer *ring;
1688 int i;
1689
d1e61e7f
CW		 1690 /* Is the chip hanging on a WAIT_FOR_EVENT?
1691 * If so we can simply poke the RB_WAIT bit
1692 * and break the hang. This should work on
1693 * all but the second generation chipsets.
1694 */
b4519513
CW		 1695 for_each_ring(ring, dev_priv, i)
1696 hung &= !kick_ring(ring);
d1e61e7f
CW		 1697 }
1698
b4519513 1699 return hung;
d1e61e7f
CW		 1700 }
1701
1702 return false;
1703}
1704
f65d9421
BG		 1705/**
1706 * This is called when the chip hasn't reported back with completed
1707 * batchbuffers in a long time. The first time this is called we simply record
1708 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1709 * again, we assume the chip is wedged and try to fix it.
1710 */
1711void i915_hangcheck_elapsed(unsigned long data)
1712{
1713 struct drm_device *dev = (struct drm_device *)data;
1714 drm_i915_private_t *dev_priv = dev->dev_private;
bd9854f9 1715 uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
b4519513
CW		 1716 struct intel_ring_buffer *ring;
1717 bool err = false, idle;
1718 int i;
893eead0 1719
3e0dc6b0
BW		 1720 if (!i915_enable_hangcheck)
1721 return;
1722
b4519513
CW		 1723 memset(acthd, 0, sizeof(acthd));
1724 idle = true;
1725 for_each_ring(ring, dev_priv, i) {
1726 idle &= i915_hangcheck_ring_idle(ring, &err);
1727 acthd[i] = intel_ring_get_active_head(ring);
1728 }
1729
893eead0 1730 /* If all work is done then ACTHD clearly hasn't advanced. */
b4519513 1731 if (idle) {
d1e61e7f
CW		 1732 if (err) {
1733 if (i915_hangcheck_hung(dev))
1734 return;
1735
893eead0 1736 goto repeat;
d1e61e7f
CW		 1737 }
1738
1739 dev_priv->hangcheck_count = 0;
893eead0
CW		 1740 return;
1741 }
b9201c14 1742
bd9854f9 1743 i915_get_extra_instdone(dev, instdone);
b4519513 1744 if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 &&
050ee91f 1745 memcmp(dev_priv->prev_instdone, instdone, sizeof(instdone)) == 0) {
d1e61e7f 1746 if (i915_hangcheck_hung(dev))
cbb465e7 1747 return;
cbb465e7
CW		 1748 } else {
1749 dev_priv->hangcheck_count = 0;
1750
b4519513 1751 memcpy(dev_priv->last_acthd, acthd, sizeof(acthd));
050ee91f 1752 memcpy(dev_priv->prev_instdone, instdone, sizeof(instdone));
cbb465e7 1753 }
f65d9421 1754
893eead0 1755repeat:
f65d9421 1756 /* Reset timer case chip hangs without another request being added */
b3b079db 1757 mod_timer(&dev_priv->hangcheck_timer,
cecc21fe 1758 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
f65d9421
BG		 1759}
1760
1da177e4
LT		 1761/* drm_dma.h hooks
1762*/
f71d4af4 1763static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 1764{
1765 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1766
4697995b
JB		 1767 atomic_set(&dev_priv->irq_received, 0);
1768
036a4a7d 1769 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 1770
036a4a7d
ZW		 1771 /* XXX hotplug from PCH */
1772
1773 I915_WRITE(DEIMR, 0xffffffff);
1774 I915_WRITE(DEIER, 0x0);
3143a2bf 1775 POSTING_READ(DEIER);
036a4a7d
ZW		 1776
1777 /* and GT */
1778 I915_WRITE(GTIMR, 0xffffffff);
1779 I915_WRITE(GTIER, 0x0);
3143a2bf 1780 POSTING_READ(GTIER);
c650156a
ZW		 1781
1782 /* south display irq */
1783 I915_WRITE(SDEIMR, 0xffffffff);
1784 I915_WRITE(SDEIER, 0x0);
3143a2bf 1785 POSTING_READ(SDEIER);
036a4a7d
ZW		 1786}
1787
7e231dbe
JB		 1788static void valleyview_irq_preinstall(struct drm_device *dev)
1789{
1790 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1791 int pipe;
1792
1793 atomic_set(&dev_priv->irq_received, 0);
1794
7e231dbe
JB		 1795 /* VLV magic */
1796 I915_WRITE(VLV_IMR, 0);
1797 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1798 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1799 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1800
7e231dbe
JB		 1801 /* and GT */
1802 I915_WRITE(GTIIR, I915_READ(GTIIR));
1803 I915_WRITE(GTIIR, I915_READ(GTIIR));
1804 I915_WRITE(GTIMR, 0xffffffff);
1805 I915_WRITE(GTIER, 0x0);
1806 POSTING_READ(GTIER);
1807
1808 I915_WRITE(DPINVGTT, 0xff);
1809
1810 I915_WRITE(PORT_HOTPLUG_EN, 0);
1811 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1812 for_each_pipe(pipe)
1813 I915_WRITE(PIPESTAT(pipe), 0xffff);
1814 I915_WRITE(VLV_IIR, 0xffffffff);
1815 I915_WRITE(VLV_IMR, 0xffffffff);
1816 I915_WRITE(VLV_IER, 0x0);
1817 POSTING_READ(VLV_IER);
1818}
1819
7fe0b973
KP		 1820/*
1821 * Enable digital hotplug on the PCH, and configure the DP short pulse
1822 * duration to 2ms (which is the minimum in the Display Port spec)
1823 *
1824 * This register is the same on all known PCH chips.
1825 */
1826
1827static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1828{
1829 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1830 u32 hotplug;
1831
1832 hotplug = I915_READ(PCH_PORT_HOTPLUG);
1833 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1834 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1835 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1836 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1837 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1838}
1839
f71d4af4 1840static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d
ZW		 1841{
1842 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1843 /* enable kind of interrupts always enabled */
013d5aa2
JB		 1844 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1845 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1ec14ad3 1846 u32 render_irqs;
2d7b8366 1847 u32 hotplug_mask;
036a4a7d 1848
1ec14ad3 1849 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 1850
1851 /* should always can generate irq */
1852 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3
CW		 1853 I915_WRITE(DEIMR, dev_priv->irq_mask);
1854 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
3143a2bf 1855 POSTING_READ(DEIER);
036a4a7d 1856
1ec14ad3 1857 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 1858
1859 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 1860 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 1861
1ec14ad3
CW		 1862 if (IS_GEN6(dev))
1863 render_irqs =
1864 GT_USER_INTERRUPT |
e2a1e2f0
BW		 1865 GEN6_BSD_USER_INTERRUPT |
1866 GEN6_BLITTER_USER_INTERRUPT;
1ec14ad3
CW		 1867 else
1868 render_irqs =
88f23b8f 1869 GT_USER_INTERRUPT |
c6df541c 1870 GT_PIPE_NOTIFY |
1ec14ad3
CW		 1871 GT_BSD_USER_INTERRUPT;
1872 I915_WRITE(GTIER, render_irqs);
3143a2bf 1873 POSTING_READ(GTIER);
036a4a7d 1874
2d7b8366 1875 if (HAS_PCH_CPT(dev)) {
9035a97a
CW		 1876 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1877 SDE_PORTB_HOTPLUG_CPT |
1878 SDE_PORTC_HOTPLUG_CPT |
1879 SDE_PORTD_HOTPLUG_CPT);
2d7b8366 1880 } else {
9035a97a
CW		 1881 hotplug_mask = (SDE_CRT_HOTPLUG |
1882 SDE_PORTB_HOTPLUG |
1883 SDE_PORTC_HOTPLUG |
1884 SDE_PORTD_HOTPLUG |
1885 SDE_AUX_MASK);
2d7b8366
YL		 1886 }
1887
1ec14ad3 1888 dev_priv->pch_irq_mask = ~hotplug_mask;
c650156a
ZW		 1889
1890 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1ec14ad3
CW		 1891 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1892 I915_WRITE(SDEIER, hotplug_mask);
3143a2bf 1893 POSTING_READ(SDEIER);
c650156a 1894
7fe0b973
KP		 1895 ironlake_enable_pch_hotplug(dev);
1896
f97108d1
JB		 1897 if (IS_IRONLAKE_M(dev)) {
1898 /* Clear & enable PCU event interrupts */
1899 I915_WRITE(DEIIR, DE_PCU_EVENT);
1900 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1901 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1902 }
1903
036a4a7d
ZW		 1904 return 0;
1905}
1906
f71d4af4 1907static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 1908{
1909 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1910 /* enable kind of interrupts always enabled */
b615b57a
CW		 1911 u32 display_mask =
1912 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
1913 DE_PLANEC_FLIP_DONE_IVB |
1914 DE_PLANEB_FLIP_DONE_IVB |
1915 DE_PLANEA_FLIP_DONE_IVB;
b1f14ad0
JB		 1916 u32 render_irqs;
1917 u32 hotplug_mask;
1918
b1f14ad0
JB		 1919 dev_priv->irq_mask = ~display_mask;
1920
1921 /* should always can generate irq */
1922 I915_WRITE(DEIIR, I915_READ(DEIIR));
1923 I915_WRITE(DEIMR, dev_priv->irq_mask);
b615b57a
CW		 1924 I915_WRITE(DEIER,
1925 display_mask |
1926 DE_PIPEC_VBLANK_IVB |
1927 DE_PIPEB_VBLANK_IVB |
1928 DE_PIPEA_VBLANK_IVB);
b1f14ad0
JB		 1929 POSTING_READ(DEIER);
1930
15b9f80e 1931 dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 1932
1933 I915_WRITE(GTIIR, I915_READ(GTIIR));
1934 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1935
e2a1e2f0 1936 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
15b9f80e 1937 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 1938 I915_WRITE(GTIER, render_irqs);
1939 POSTING_READ(GTIER);
1940
1941 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1942 SDE_PORTB_HOTPLUG_CPT |
1943 SDE_PORTC_HOTPLUG_CPT |
1944 SDE_PORTD_HOTPLUG_CPT);
1945 dev_priv->pch_irq_mask = ~hotplug_mask;
1946
1947 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1948 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1949 I915_WRITE(SDEIER, hotplug_mask);
1950 POSTING_READ(SDEIER);
1951
7fe0b973
KP		 1952 ironlake_enable_pch_hotplug(dev);
1953
b1f14ad0
JB		 1954 return 0;
1955}
1956
7e231dbe
JB		 1957static int valleyview_irq_postinstall(struct drm_device *dev)
1958{
1959 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7e231dbe
JB		 1960 u32 enable_mask;
1961 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
31acc7f5 1962 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
3bcedbe5 1963 u32 render_irqs;
7e231dbe
JB		 1964 u16 msid;
1965
1966 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
31acc7f5
JB		 1967 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
1968 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1969 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
7e231dbe
JB		 1970 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1971
31acc7f5
JB		 1972 /*
1973 *Leave vblank interrupts masked initially. enable/disable will
1974 * toggle them based on usage.
1975 */
1976 dev_priv->irq_mask = (~enable_mask) |
1977 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1978 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1979
7e231dbe
JB		 1980 dev_priv->pipestat[0] = 0;
1981 dev_priv->pipestat[1] = 0;
1982
7e231dbe
JB		 1983 /* Hack for broken MSIs on VLV */
1984 pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
1985 pci_read_config_word(dev->pdev, 0x98, &msid);
1986 msid &= 0xff; /* mask out delivery bits */
1987 msid |= (1<<14);
1988 pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
1989
1990 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
1991 I915_WRITE(VLV_IER, enable_mask);
1992 I915_WRITE(VLV_IIR, 0xffffffff);
1993 I915_WRITE(PIPESTAT(0), 0xffff);
1994 I915_WRITE(PIPESTAT(1), 0xffff);
1995 POSTING_READ(VLV_IER);
1996
31acc7f5
JB		 1997 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
1998 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
1999
7e231dbe
JB		 2000 I915_WRITE(VLV_IIR, 0xffffffff);
2001 I915_WRITE(VLV_IIR, 0xffffffff);
2002
7e231dbe 2003 I915_WRITE(GTIIR, I915_READ(GTIIR));
31acc7f5 2004 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
3bcedbe5
JB		 2005
2006 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2007 GEN6_BLITTER_USER_INTERRUPT;
2008 I915_WRITE(GTIER, render_irqs);
7e231dbe
JB		 2009 POSTING_READ(GTIER);
2010
2011 /* ack & enable invalid PTE error interrupts */
2012#if 0 /* FIXME: add support to irq handler for checking these bits */
2013 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2014 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2015#endif
2016
2017 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
7e231dbe
JB		 2018 /* Note HDMI and DP share bits */
2019 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2020 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2021 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2022 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2023 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2024 hotplug_en |= HDMID_HOTPLUG_INT_EN;
ae33cdcf 2025 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
7e231dbe 2026 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
ae33cdcf 2027 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
7e231dbe
JB		 2028 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2029 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2030 hotplug_en |= CRT_HOTPLUG_INT_EN;
2031 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2032 }
7e231dbe
JB		 2033
2034 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2035
2036 return 0;
2037}
2038
7e231dbe
JB		 2039static void valleyview_irq_uninstall(struct drm_device *dev)
2040{
2041 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2042 int pipe;
2043
2044 if (!dev_priv)
2045 return;
2046
7e231dbe
JB		 2047 for_each_pipe(pipe)
2048 I915_WRITE(PIPESTAT(pipe), 0xffff);
2049
2050 I915_WRITE(HWSTAM, 0xffffffff);
2051 I915_WRITE(PORT_HOTPLUG_EN, 0);
2052 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2053 for_each_pipe(pipe)
2054 I915_WRITE(PIPESTAT(pipe), 0xffff);
2055 I915_WRITE(VLV_IIR, 0xffffffff);
2056 I915_WRITE(VLV_IMR, 0xffffffff);
2057 I915_WRITE(VLV_IER, 0x0);
2058 POSTING_READ(VLV_IER);
2059}
2060
f71d4af4 2061static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 2062{
2063 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 2064
2065 if (!dev_priv)
2066 return;
2067
036a4a7d
ZW		 2068 I915_WRITE(HWSTAM, 0xffffffff);
2069
2070 I915_WRITE(DEIMR, 0xffffffff);
2071 I915_WRITE(DEIER, 0x0);
2072 I915_WRITE(DEIIR, I915_READ(DEIIR));
2073
2074 I915_WRITE(GTIMR, 0xffffffff);
2075 I915_WRITE(GTIER, 0x0);
2076 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f
KP		 2077
2078 I915_WRITE(SDEIMR, 0xffffffff);
2079 I915_WRITE(SDEIER, 0x0);
2080 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
036a4a7d
ZW		 2081}
2082
a266c7d5 2083static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 2084{
2085 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2086 int pipe;
91e3738e 2087
a266c7d5 2088 atomic_set(&dev_priv->irq_received, 0);
5ca58282 2089
9db4a9c7
JB		 2090 for_each_pipe(pipe)
2091 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 2092 I915_WRITE16(IMR, 0xffff);
2093 I915_WRITE16(IER, 0x0);
2094 POSTING_READ16(IER);
c2798b19
CW		 2095}
2096
2097static int i8xx_irq_postinstall(struct drm_device *dev)
2098{
2099 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2100
c2798b19
CW		 2101 dev_priv->pipestat[0] = 0;
2102 dev_priv->pipestat[1] = 0;
2103
2104 I915_WRITE16(EMR,
2105 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2106
2107 /* Unmask the interrupts that we always want on. */
2108 dev_priv->irq_mask =
2109 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2110 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2111 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2112 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2113 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2114 I915_WRITE16(IMR, dev_priv->irq_mask);
2115
2116 I915_WRITE16(IER,
2117 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2118 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2119 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2120 I915_USER_INTERRUPT);
2121 POSTING_READ16(IER);
2122
2123 return 0;
2124}
2125
ff1f525e 2126static irqreturn_t i8xx_irq_handler(int irq, void *arg)
c2798b19
CW		 2127{
2128 struct drm_device *dev = (struct drm_device *) arg;
2129 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 2130 u16 iir, new_iir;
2131 u32 pipe_stats[2];
2132 unsigned long irqflags;
2133 int irq_received;
2134 int pipe;
2135 u16 flip_mask =
2136 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2137 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2138
2139 atomic_inc(&dev_priv->irq_received);
2140
2141 iir = I915_READ16(IIR);
2142 if (iir == 0)
2143 return IRQ_NONE;
2144
2145 while (iir & ~flip_mask) {
2146 /* Can't rely on pipestat interrupt bit in iir as it might
2147 * have been cleared after the pipestat interrupt was received.
2148 * It doesn't set the bit in iir again, but it still produces
2149 * interrupts (for non-MSI).
2150 */
2151 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2152 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2153 i915_handle_error(dev, false);
2154
2155 for_each_pipe(pipe) {
2156 int reg = PIPESTAT(pipe);
2157 pipe_stats[pipe] = I915_READ(reg);
2158
2159 /*
2160 * Clear the PIPE*STAT regs before the IIR
2161 */
2162 if (pipe_stats[pipe] & 0x8000ffff) {
2163 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2164 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2165 pipe_name(pipe));
2166 I915_WRITE(reg, pipe_stats[pipe]);
2167 irq_received = 1;
2168 }
2169 }
2170 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2171
2172 I915_WRITE16(IIR, iir & ~flip_mask);
2173 new_iir = I915_READ16(IIR); /* Flush posted writes */
2174
d05c617e 2175 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 2176
2177 if (iir & I915_USER_INTERRUPT)
2178 notify_ring(dev, &dev_priv->ring[RCS]);
2179
2180 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2181 drm_handle_vblank(dev, 0)) {
2182 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2183 intel_prepare_page_flip(dev, 0);
2184 intel_finish_page_flip(dev, 0);
2185 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2186 }
2187 }
2188
2189 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2190 drm_handle_vblank(dev, 1)) {
2191 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2192 intel_prepare_page_flip(dev, 1);
2193 intel_finish_page_flip(dev, 1);
2194 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2195 }
2196 }
2197
2198 iir = new_iir;
2199 }
2200
2201 return IRQ_HANDLED;
2202}
2203
2204static void i8xx_irq_uninstall(struct drm_device * dev)
2205{
2206 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2207 int pipe;
2208
c2798b19
CW		 2209 for_each_pipe(pipe) {
2210 /* Clear enable bits; then clear status bits */
2211 I915_WRITE(PIPESTAT(pipe), 0);
2212 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2213 }
2214 I915_WRITE16(IMR, 0xffff);
2215 I915_WRITE16(IER, 0x0);
2216 I915_WRITE16(IIR, I915_READ16(IIR));
2217}
2218
a266c7d5
CW		 2219static void i915_irq_preinstall(struct drm_device * dev)
2220{
2221 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2222 int pipe;
2223
2224 atomic_set(&dev_priv->irq_received, 0);
2225
2226 if (I915_HAS_HOTPLUG(dev)) {
2227 I915_WRITE(PORT_HOTPLUG_EN, 0);
2228 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2229 }
2230
00d98ebd 2231 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 2232 for_each_pipe(pipe)
2233 I915_WRITE(PIPESTAT(pipe), 0);
2234 I915_WRITE(IMR, 0xffffffff);
2235 I915_WRITE(IER, 0x0);
2236 POSTING_READ(IER);
2237}
2238
2239static int i915_irq_postinstall(struct drm_device *dev)
2240{
2241 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 2242 u32 enable_mask;
a266c7d5 2243
a266c7d5
CW		 2244 dev_priv->pipestat[0] = 0;
2245 dev_priv->pipestat[1] = 0;
2246
38bde180
CW		 2247 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2248
2249 /* Unmask the interrupts that we always want on. */
2250 dev_priv->irq_mask =
2251 ~(I915_ASLE_INTERRUPT |
2252 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2253 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2254 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2255 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2256 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2257
2258 enable_mask =
2259 I915_ASLE_INTERRUPT |
2260 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2261 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2262 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2263 I915_USER_INTERRUPT;
2264
a266c7d5
CW		 2265 if (I915_HAS_HOTPLUG(dev)) {
2266 /* Enable in IER... */
2267 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2268 /* and unmask in IMR */
2269 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2270 }
2271
a266c7d5
CW		 2272 I915_WRITE(IMR, dev_priv->irq_mask);
2273 I915_WRITE(IER, enable_mask);
2274 POSTING_READ(IER);
2275
2276 if (I915_HAS_HOTPLUG(dev)) {
2277 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2278
a266c7d5
CW		 2279 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2280 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2281 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2282 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2283 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2284 hotplug_en |= HDMID_HOTPLUG_INT_EN;
084b612e 2285 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
a266c7d5 2286 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
084b612e 2287 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
a266c7d5
CW		 2288 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2289 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2290 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5
CW		 2291 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2292 }
2293
2294 /* Ignore TV since it's buggy */
2295
2296 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2297 }
2298
2299 intel_opregion_enable_asle(dev);
2300
2301 return 0;
2302}
2303
ff1f525e 2304static irqreturn_t i915_irq_handler(int irq, void *arg)
a266c7d5
CW		 2305{
2306 struct drm_device *dev = (struct drm_device *) arg;
2307 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 2308 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 2309 unsigned long irqflags;
38bde180
CW		 2310 u32 flip_mask =
2311 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2312 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2313 u32 flip[2] = {
2314 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2315 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2316 };
2317 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 2318
2319 atomic_inc(&dev_priv->irq_received);
2320
2321 iir = I915_READ(IIR);
38bde180
CW		 2322 do {
2323 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 2324 bool blc_event = false;
a266c7d5
CW		 2325
2326 /* Can't rely on pipestat interrupt bit in iir as it might
2327 * have been cleared after the pipestat interrupt was received.
2328 * It doesn't set the bit in iir again, but it still produces
2329 * interrupts (for non-MSI).
2330 */
2331 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2332 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2333 i915_handle_error(dev, false);
2334
2335 for_each_pipe(pipe) {
2336 int reg = PIPESTAT(pipe);
2337 pipe_stats[pipe] = I915_READ(reg);
2338
38bde180 2339 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 2340 if (pipe_stats[pipe] & 0x8000ffff) {
2341 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2342 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2343 pipe_name(pipe));
2344 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 2345 irq_received = true;
a266c7d5
CW		 2346 }
2347 }
2348 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2349
2350 if (!irq_received)
2351 break;
2352
a266c7d5
CW		 2353 /* Consume port. Then clear IIR or we'll miss events */
2354 if ((I915_HAS_HOTPLUG(dev)) &&
2355 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2356 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2357
2358 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2359 hotplug_status);
2360 if (hotplug_status & dev_priv->hotplug_supported_mask)
2361 queue_work(dev_priv->wq,
2362 &dev_priv->hotplug_work);
2363
2364 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 2365 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 2366 }
2367
38bde180 2368 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2369 new_iir = I915_READ(IIR); /* Flush posted writes */
2370
a266c7d5
CW		 2371 if (iir & I915_USER_INTERRUPT)
2372 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 2373
a266c7d5 2374 for_each_pipe(pipe) {
38bde180
CW		 2375 int plane = pipe;
2376 if (IS_MOBILE(dev))
2377 plane = !plane;
8291ee90 2378 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2379 drm_handle_vblank(dev, pipe)) {
38bde180
CW		 2380 if (iir & flip[plane]) {
2381 intel_prepare_page_flip(dev, plane);
2382 intel_finish_page_flip(dev, pipe);
2383 flip_mask &= ~flip[plane];
2384 }
a266c7d5
CW		 2385 }
2386
2387 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2388 blc_event = true;
2389 }
2390
a266c7d5
CW		 2391 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2392 intel_opregion_asle_intr(dev);
2393
2394 /* With MSI, interrupts are only generated when iir
2395 * transitions from zero to nonzero. If another bit got
2396 * set while we were handling the existing iir bits, then
2397 * we would never get another interrupt.
2398 *
2399 * This is fine on non-MSI as well, as if we hit this path
2400 * we avoid exiting the interrupt handler only to generate
2401 * another one.
2402 *
2403 * Note that for MSI this could cause a stray interrupt report
2404 * if an interrupt landed in the time between writing IIR and
2405 * the posting read. This should be rare enough to never
2406 * trigger the 99% of 100,000 interrupts test for disabling
2407 * stray interrupts.
2408 */
38bde180 2409 ret = IRQ_HANDLED;
a266c7d5 2410 iir = new_iir;
38bde180 2411 } while (iir & ~flip_mask);
a266c7d5 2412
d05c617e 2413 i915_update_dri1_breadcrumb(dev);
8291ee90 2414
a266c7d5
CW		 2415 return ret;
2416}
2417
2418static void i915_irq_uninstall(struct drm_device * dev)
2419{
2420 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2421 int pipe;
2422
a266c7d5
CW		 2423 if (I915_HAS_HOTPLUG(dev)) {
2424 I915_WRITE(PORT_HOTPLUG_EN, 0);
2425 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2426 }
2427
00d98ebd 2428 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 2429 for_each_pipe(pipe) {
2430 /* Clear enable bits; then clear status bits */
a266c7d5 2431 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 2432 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2433 }
a266c7d5
CW		 2434 I915_WRITE(IMR, 0xffffffff);
2435 I915_WRITE(IER, 0x0);
2436
a266c7d5
CW		 2437 I915_WRITE(IIR, I915_READ(IIR));
2438}
2439
2440static void i965_irq_preinstall(struct drm_device * dev)
2441{
2442 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2443 int pipe;
2444
2445 atomic_set(&dev_priv->irq_received, 0);
2446
adca4730
CW		 2447 I915_WRITE(PORT_HOTPLUG_EN, 0);
2448 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2449
2450 I915_WRITE(HWSTAM, 0xeffe);
2451 for_each_pipe(pipe)
2452 I915_WRITE(PIPESTAT(pipe), 0);
2453 I915_WRITE(IMR, 0xffffffff);
2454 I915_WRITE(IER, 0x0);
2455 POSTING_READ(IER);
2456}
2457
2458static int i965_irq_postinstall(struct drm_device *dev)
2459{
2460 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
adca4730 2461 u32 hotplug_en;
bbba0a97 2462 u32 enable_mask;
a266c7d5
CW		 2463 u32 error_mask;
2464
a266c7d5 2465 /* Unmask the interrupts that we always want on. */
bbba0a97 2466 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 2467 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 2468 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2469 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2470 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2471 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2472 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2473
2474 enable_mask = ~dev_priv->irq_mask;
2475 enable_mask |= I915_USER_INTERRUPT;
2476
2477 if (IS_G4X(dev))
2478 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5
CW		 2479
2480 dev_priv->pipestat[0] = 0;
2481 dev_priv->pipestat[1] = 0;
2482
a266c7d5
CW		 2483 /*
2484 * Enable some error detection, note the instruction error mask
2485 * bit is reserved, so we leave it masked.
2486 */
2487 if (IS_G4X(dev)) {
2488 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2489 GM45_ERROR_MEM_PRIV |
2490 GM45_ERROR_CP_PRIV |
2491 I915_ERROR_MEMORY_REFRESH);
2492 } else {
2493 error_mask = ~(I915_ERROR_PAGE_TABLE |
2494 I915_ERROR_MEMORY_REFRESH);
2495 }
2496 I915_WRITE(EMR, error_mask);
2497
2498 I915_WRITE(IMR, dev_priv->irq_mask);
2499 I915_WRITE(IER, enable_mask);
2500 POSTING_READ(IER);
2501
adca4730
CW		 2502 /* Note HDMI and DP share hotplug bits */
2503 hotplug_en = 0;
2504 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2505 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2506 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2507 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2508 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2509 hotplug_en |= HDMID_HOTPLUG_INT_EN;
084b612e
CW		 2510 if (IS_G4X(dev)) {
2511 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
2512 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2513 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
2514 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2515 } else {
2516 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
2517 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2518 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
2519 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2520 }
adca4730
CW		 2521 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2522 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5 2523
adca4730
CW		 2524 /* Programming the CRT detection parameters tends
2525 to generate a spurious hotplug event about three
2526 seconds later. So just do it once.
2527 */
2528 if (IS_G4X(dev))
2529 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2530 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2531 }
a266c7d5 2532
adca4730 2533 /* Ignore TV since it's buggy */
a266c7d5 2534
adca4730 2535 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
a266c7d5
CW		 2536
2537 intel_opregion_enable_asle(dev);
2538
2539 return 0;
2540}
2541
ff1f525e 2542static irqreturn_t i965_irq_handler(int irq, void *arg)
a266c7d5
CW		 2543{
2544 struct drm_device *dev = (struct drm_device *) arg;
2545 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 2546 u32 iir, new_iir;
2547 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 2548 unsigned long irqflags;
2549 int irq_received;
2550 int ret = IRQ_NONE, pipe;
a266c7d5
CW		 2551
2552 atomic_inc(&dev_priv->irq_received);
2553
2554 iir = I915_READ(IIR);
2555
a266c7d5 2556 for (;;) {
2c8ba29f
CW		 2557 bool blc_event = false;
2558
a266c7d5
CW		 2559 irq_received = iir != 0;
2560
2561 /* Can't rely on pipestat interrupt bit in iir as it might
2562 * have been cleared after the pipestat interrupt was received.
2563 * It doesn't set the bit in iir again, but it still produces
2564 * interrupts (for non-MSI).
2565 */
2566 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2567 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2568 i915_handle_error(dev, false);
2569
2570 for_each_pipe(pipe) {
2571 int reg = PIPESTAT(pipe);
2572 pipe_stats[pipe] = I915_READ(reg);
2573
2574 /*
2575 * Clear the PIPE*STAT regs before the IIR
2576 */
2577 if (pipe_stats[pipe] & 0x8000ffff) {
2578 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2579 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2580 pipe_name(pipe));
2581 I915_WRITE(reg, pipe_stats[pipe]);
2582 irq_received = 1;
2583 }
2584 }
2585 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2586
2587 if (!irq_received)
2588 break;
2589
2590 ret = IRQ_HANDLED;
2591
2592 /* Consume port. Then clear IIR or we'll miss events */
adca4730 2593 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
a266c7d5
CW		 2594 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2595
2596 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2597 hotplug_status);
2598 if (hotplug_status & dev_priv->hotplug_supported_mask)
2599 queue_work(dev_priv->wq,
2600 &dev_priv->hotplug_work);
2601
2602 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2603 I915_READ(PORT_HOTPLUG_STAT);
2604 }
2605
2606 I915_WRITE(IIR, iir);
2607 new_iir = I915_READ(IIR); /* Flush posted writes */
2608
a266c7d5
CW		 2609 if (iir & I915_USER_INTERRUPT)
2610 notify_ring(dev, &dev_priv->ring[RCS]);
2611 if (iir & I915_BSD_USER_INTERRUPT)
2612 notify_ring(dev, &dev_priv->ring[VCS]);
2613
4f7d1e79 2614 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
a266c7d5 2615 intel_prepare_page_flip(dev, 0);
a266c7d5 2616
4f7d1e79 2617 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
a266c7d5 2618 intel_prepare_page_flip(dev, 1);
a266c7d5
CW		 2619
2620 for_each_pipe(pipe) {
2c8ba29f 2621 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2622 drm_handle_vblank(dev, pipe)) {
4f7d1e79
CW		 2623 i915_pageflip_stall_check(dev, pipe);
2624 intel_finish_page_flip(dev, pipe);
a266c7d5
CW		 2625 }
2626
2627 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2628 blc_event = true;
2629 }
2630
2631
2632 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2633 intel_opregion_asle_intr(dev);
2634
2635 /* With MSI, interrupts are only generated when iir
2636 * transitions from zero to nonzero. If another bit got
2637 * set while we were handling the existing iir bits, then
2638 * we would never get another interrupt.
2639 *
2640 * This is fine on non-MSI as well, as if we hit this path
2641 * we avoid exiting the interrupt handler only to generate
2642 * another one.
2643 *
2644 * Note that for MSI this could cause a stray interrupt report
2645 * if an interrupt landed in the time between writing IIR and
2646 * the posting read. This should be rare enough to never
2647 * trigger the 99% of 100,000 interrupts test for disabling
2648 * stray interrupts.
2649 */
2650 iir = new_iir;
2651 }
2652
d05c617e 2653 i915_update_dri1_breadcrumb(dev);
2c8ba29f 2654
a266c7d5
CW		 2655 return ret;
2656}
2657
2658static void i965_irq_uninstall(struct drm_device * dev)
2659{
2660 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2661 int pipe;
2662
2663 if (!dev_priv)
2664 return;
2665
adca4730
CW		 2666 I915_WRITE(PORT_HOTPLUG_EN, 0);
2667 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2668
2669 I915_WRITE(HWSTAM, 0xffffffff);
2670 for_each_pipe(pipe)
2671 I915_WRITE(PIPESTAT(pipe), 0);
2672 I915_WRITE(IMR, 0xffffffff);
2673 I915_WRITE(IER, 0x0);
2674
2675 for_each_pipe(pipe)
2676 I915_WRITE(PIPESTAT(pipe),
2677 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2678 I915_WRITE(IIR, I915_READ(IIR));
2679}
2680
f71d4af4
JB		 2681void intel_irq_init(struct drm_device *dev)
2682{
8b2e326d
CW		 2683 struct drm_i915_private *dev_priv = dev->dev_private;
2684
2685 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2686 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
c6a828d3 2687 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
a4da4fa4 2688 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
8b2e326d 2689
61bac78e
DV		 2690 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
2691 (unsigned long) dev);
2692
f71d4af4
JB		 2693 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2694 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7d4e146f 2695 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 2696 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2697 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2698 }
2699
c3613de9
KP		 2700 if (drm_core_check_feature(dev, DRIVER_MODESET))
2701 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2702 else
2703 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 2704 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2705
7e231dbe
JB		 2706 if (IS_VALLEYVIEW(dev)) {
2707 dev->driver->irq_handler = valleyview_irq_handler;
2708 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2709 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2710 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2711 dev->driver->enable_vblank = valleyview_enable_vblank;
2712 dev->driver->disable_vblank = valleyview_disable_vblank;
4a06e201 2713 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
f71d4af4
JB		 2714 /* Share pre & uninstall handlers with ILK/SNB */
2715 dev->driver->irq_handler = ivybridge_irq_handler;
2716 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2717 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2718 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2719 dev->driver->enable_vblank = ivybridge_enable_vblank;
2720 dev->driver->disable_vblank = ivybridge_disable_vblank;
2721 } else if (HAS_PCH_SPLIT(dev)) {
2722 dev->driver->irq_handler = ironlake_irq_handler;
2723 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2724 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2725 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2726 dev->driver->enable_vblank = ironlake_enable_vblank;
2727 dev->driver->disable_vblank = ironlake_disable_vblank;
2728 } else {
c2798b19
CW		 2729 if (INTEL_INFO(dev)->gen == 2) {
2730 dev->driver->irq_preinstall = i8xx_irq_preinstall;
2731 dev->driver->irq_postinstall = i8xx_irq_postinstall;
2732 dev->driver->irq_handler = i8xx_irq_handler;
2733 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5
CW		 2734 } else if (INTEL_INFO(dev)->gen == 3) {
2735 dev->driver->irq_preinstall = i915_irq_preinstall;
2736 dev->driver->irq_postinstall = i915_irq_postinstall;
2737 dev->driver->irq_uninstall = i915_irq_uninstall;
2738 dev->driver->irq_handler = i915_irq_handler;
c2798b19 2739 } else {
a266c7d5
CW		 2740 dev->driver->irq_preinstall = i965_irq_preinstall;
2741 dev->driver->irq_postinstall = i965_irq_postinstall;
2742 dev->driver->irq_uninstall = i965_irq_uninstall;
2743 dev->driver->irq_handler = i965_irq_handler;
c2798b19 2744 }
f71d4af4
JB		 2745 dev->driver->enable_vblank = i915_enable_vblank;
2746 dev->driver->disable_vblank = i915_disable_vblank;
2747 }
2748}
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