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drm/i915: s/mdelay/msleep/ in the sdvo detect function
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_irq.c
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0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
1da177e4
LT		 33#include "drmP.h"
34#include "drm.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
1c5d22f7 37#include "i915_trace.h"
79e53945 38#include "intel_drv.h"
1da177e4 39
036a4a7d 40/* For display hotplug interrupt */
995b6762 41static void
f2b115e6 42ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 43{
1ec14ad3
CW		 44 if ((dev_priv->irq_mask & mask) != 0) {
45 dev_priv->irq_mask &= ~mask;
46 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 47 POSTING_READ(DEIMR);
036a4a7d
ZW		 48 }
49}
50
51static inline void
f2b115e6 52ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 53{
1ec14ad3
CW		 54 if ((dev_priv->irq_mask & mask) != mask) {
55 dev_priv->irq_mask |= mask;
56 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 57 POSTING_READ(DEIMR);
036a4a7d
ZW		 58 }
59}
60
7c463586
KP		 61void
62i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
63{
64 if ((dev_priv->pipestat[pipe] & mask) != mask) {
9db4a9c7 65 u32 reg = PIPESTAT(pipe);
7c463586
KP		 66
67 dev_priv->pipestat[pipe] |= mask;
68 /* Enable the interrupt, clear any pending status */
69 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
3143a2bf 70 POSTING_READ(reg);
7c463586
KP		 71 }
72}
73
74void
75i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
76{
77 if ((dev_priv->pipestat[pipe] & mask) != 0) {
9db4a9c7 78 u32 reg = PIPESTAT(pipe);
7c463586
KP		 79
80 dev_priv->pipestat[pipe] &= ~mask;
81 I915_WRITE(reg, dev_priv->pipestat[pipe]);
3143a2bf 82 POSTING_READ(reg);
7c463586
KP		 83 }
84}
85
01c66889
ZY		 86/**
87 * intel_enable_asle - enable ASLE interrupt for OpRegion
88 */
1ec14ad3 89void intel_enable_asle(struct drm_device *dev)
01c66889 90{
1ec14ad3
CW		 91 drm_i915_private_t *dev_priv = dev->dev_private;
92 unsigned long irqflags;
93
7e231dbe
JB		 94 /* FIXME: opregion/asle for VLV */
95 if (IS_VALLEYVIEW(dev))
96 return;
97
1ec14ad3 98 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 99
c619eed4 100 if (HAS_PCH_SPLIT(dev))
f2b115e6 101 ironlake_enable_display_irq(dev_priv, DE_GSE);
edcb49ca 102 else {
01c66889 103 i915_enable_pipestat(dev_priv, 1,
d874bcff 104 PIPE_LEGACY_BLC_EVENT_ENABLE);
a6c45cf0 105 if (INTEL_INFO(dev)->gen >= 4)
edcb49ca 106 i915_enable_pipestat(dev_priv, 0,
d874bcff 107 PIPE_LEGACY_BLC_EVENT_ENABLE);
edcb49ca 108 }
1ec14ad3
CW		 109
110 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 111}
112
0a3e67a4
JB		 113/**
114 * i915_pipe_enabled - check if a pipe is enabled
115 * @dev: DRM device
116 * @pipe: pipe to check
117 *
118 * Reading certain registers when the pipe is disabled can hang the chip.
119 * Use this routine to make sure the PLL is running and the pipe is active
120 * before reading such registers if unsure.
121 */
122static int
123i915_pipe_enabled(struct drm_device *dev, int pipe)
124{
125 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
5eddb70b 126 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
0a3e67a4
JB		 127}
128
42f52ef8
KP		 129/* Called from drm generic code, passed a 'crtc', which
130 * we use as a pipe index
131 */
f71d4af4 132static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 133{
134 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
135 unsigned long high_frame;
136 unsigned long low_frame;
5eddb70b 137 u32 high1, high2, low;
0a3e67a4
JB		 138
139 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 140 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 141 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 142 return 0;
143 }
144
9db4a9c7
JB		 145 high_frame = PIPEFRAME(pipe);
146 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 147
0a3e67a4
JB		 148 /*
149 * High & low register fields aren't synchronized, so make sure
150 * we get a low value that's stable across two reads of the high
151 * register.
152 */
153 do {
5eddb70b
CW		 154 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
155 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
156 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 157 } while (high1 != high2);
158
5eddb70b
CW		 159 high1 >>= PIPE_FRAME_HIGH_SHIFT;
160 low >>= PIPE_FRAME_LOW_SHIFT;
161 return (high1 << 8) | low;
0a3e67a4
JB		 162}
163
f71d4af4 164static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 165{
166 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 167 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 168
169 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 170 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 171 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 172 return 0;
173 }
174
175 return I915_READ(reg);
176}
177
f71d4af4 178static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 179 int *vpos, int *hpos)
180{
181 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
182 u32 vbl = 0, position = 0;
183 int vbl_start, vbl_end, htotal, vtotal;
184 bool in_vbl = true;
185 int ret = 0;
186
187 if (!i915_pipe_enabled(dev, pipe)) {
188 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 189 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 190 return 0;
191 }
192
193 /* Get vtotal. */
194 vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
195
196 if (INTEL_INFO(dev)->gen >= 4) {
197 /* No obvious pixelcount register. Only query vertical
198 * scanout position from Display scan line register.
199 */
200 position = I915_READ(PIPEDSL(pipe));
201
202 /* Decode into vertical scanout position. Don't have
203 * horizontal scanout position.
204 */
205 *vpos = position & 0x1fff;
206 *hpos = 0;
207 } else {
208 /* Have access to pixelcount since start of frame.
209 * We can split this into vertical and horizontal
210 * scanout position.
211 */
212 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
213
214 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
215 *vpos = position / htotal;
216 *hpos = position - (*vpos * htotal);
217 }
218
219 /* Query vblank area. */
220 vbl = I915_READ(VBLANK(pipe));
221
222 /* Test position against vblank region. */
223 vbl_start = vbl & 0x1fff;
224 vbl_end = (vbl >> 16) & 0x1fff;
225
226 if ((*vpos < vbl_start) || (*vpos > vbl_end))
227 in_vbl = false;
228
229 /* Inside "upper part" of vblank area? Apply corrective offset: */
230 if (in_vbl && (*vpos >= vbl_start))
231 *vpos = *vpos - vtotal;
232
233 /* Readouts valid? */
234 if (vbl > 0)
235 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
236
237 /* In vblank? */
238 if (in_vbl)
239 ret |= DRM_SCANOUTPOS_INVBL;
240
241 return ret;
242}
243
f71d4af4 244static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 245 int *max_error,
246 struct timeval *vblank_time,
247 unsigned flags)
248{
4041b853
CW		 249 struct drm_i915_private *dev_priv = dev->dev_private;
250 struct drm_crtc *crtc;
0af7e4df 251
4041b853
CW		 252 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
253 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 254 return -EINVAL;
255 }
256
257 /* Get drm_crtc to timestamp: */
4041b853
CW		 258 crtc = intel_get_crtc_for_pipe(dev, pipe);
259 if (crtc == NULL) {
260 DRM_ERROR("Invalid crtc %d\n", pipe);
261 return -EINVAL;
262 }
263
264 if (!crtc->enabled) {
265 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
266 return -EBUSY;
267 }
0af7e4df
MK		 268
269 /* Helper routine in DRM core does all the work: */
4041b853
CW		 270 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
271 vblank_time, flags,
272 crtc);
0af7e4df
MK		 273}
274
5ca58282
JB		 275/*
276 * Handle hotplug events outside the interrupt handler proper.
277 */
278static void i915_hotplug_work_func(struct work_struct *work)
279{
280 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
281 hotplug_work);
282 struct drm_device *dev = dev_priv->dev;
c31c4ba3 283 struct drm_mode_config *mode_config = &dev->mode_config;
4ef69c7a
CW		 284 struct intel_encoder *encoder;
285
a65e34c7 286 mutex_lock(&mode_config->mutex);
e67189ab
JB		 287 DRM_DEBUG_KMS("running encoder hotplug functions\n");
288
4ef69c7a
CW		 289 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
290 if (encoder->hot_plug)
291 encoder->hot_plug(encoder);
292
40ee3381
KP		 293 mutex_unlock(&mode_config->mutex);
294
5ca58282 295 /* Just fire off a uevent and let userspace tell us what to do */
eb1f8e4f 296 drm_helper_hpd_irq_event(dev);
5ca58282
JB		 297}
298
f97108d1
JB		 299static void i915_handle_rps_change(struct drm_device *dev)
300{
301 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 302 u32 busy_up, busy_down, max_avg, min_avg;
f97108d1
JB		 303 u8 new_delay = dev_priv->cur_delay;
304
7648fa99 305 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 306 busy_up = I915_READ(RCPREVBSYTUPAVG);
307 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 308 max_avg = I915_READ(RCBMAXAVG);
309 min_avg = I915_READ(RCBMINAVG);
310
311 /* Handle RCS change request from hw */
b5b72e89 312 if (busy_up > max_avg) {
f97108d1
JB		 313 if (dev_priv->cur_delay != dev_priv->max_delay)
314 new_delay = dev_priv->cur_delay - 1;
315 if (new_delay < dev_priv->max_delay)
316 new_delay = dev_priv->max_delay;
b5b72e89 317 } else if (busy_down < min_avg) {
f97108d1
JB		 318 if (dev_priv->cur_delay != dev_priv->min_delay)
319 new_delay = dev_priv->cur_delay + 1;
320 if (new_delay > dev_priv->min_delay)
321 new_delay = dev_priv->min_delay;
322 }
323
7648fa99
JB		 324 if (ironlake_set_drps(dev, new_delay))
325 dev_priv->cur_delay = new_delay;
f97108d1
JB		 326
327 return;
328}
329
549f7365
CW		 330static void notify_ring(struct drm_device *dev,
331 struct intel_ring_buffer *ring)
332{
333 struct drm_i915_private *dev_priv = dev->dev_private;
9862e600 334
475553de
CW		 335 if (ring->obj == NULL)
336 return;
337
6d171cb4 338 trace_i915_gem_request_complete(ring, ring->get_seqno(ring));
9862e600 339
549f7365 340 wake_up_all(&ring->irq_queue);
3e0dc6b0
BW		 341 if (i915_enable_hangcheck) {
342 dev_priv->hangcheck_count = 0;
343 mod_timer(&dev_priv->hangcheck_timer,
344 jiffies +
345 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
346 }
549f7365
CW		 347}
348
4912d041 349static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 350{
4912d041
BW		 351 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
352 rps_work);
3b8d8d91 353 u8 new_delay = dev_priv->cur_delay;
4912d041
BW		 354 u32 pm_iir, pm_imr;
355
356 spin_lock_irq(&dev_priv->rps_lock);
357 pm_iir = dev_priv->pm_iir;
358 dev_priv->pm_iir = 0;
359 pm_imr = I915_READ(GEN6_PMIMR);
a9e2641d 360 I915_WRITE(GEN6_PMIMR, 0);
4912d041 361 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91 362
3b8d8d91
JB		 363 if (!pm_iir)
364 return;
365
4912d041 366 mutex_lock(&dev_priv->dev->struct_mutex);
3b8d8d91
JB		 367 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
368 if (dev_priv->cur_delay != dev_priv->max_delay)
369 new_delay = dev_priv->cur_delay + 1;
370 if (new_delay > dev_priv->max_delay)
371 new_delay = dev_priv->max_delay;
372 } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
4912d041 373 gen6_gt_force_wake_get(dev_priv);
3b8d8d91
JB		 374 if (dev_priv->cur_delay != dev_priv->min_delay)
375 new_delay = dev_priv->cur_delay - 1;
376 if (new_delay < dev_priv->min_delay) {
377 new_delay = dev_priv->min_delay;
378 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
379 I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
380 ((new_delay << 16) & 0x3f0000));
381 } else {
382 /* Make sure we continue to get down interrupts
383 * until we hit the minimum frequency */
384 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
385 I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
386 }
4912d041 387 gen6_gt_force_wake_put(dev_priv);
3b8d8d91
JB		 388 }
389
4912d041 390 gen6_set_rps(dev_priv->dev, new_delay);
3b8d8d91
JB		 391 dev_priv->cur_delay = new_delay;
392
4912d041
BW		 393 /*
394 * rps_lock not held here because clearing is non-destructive. There is
395 * an *extremely* unlikely race with gen6_rps_enable() that is prevented
396 * by holding struct_mutex for the duration of the write.
397 */
4912d041 398 mutex_unlock(&dev_priv->dev->struct_mutex);
3b8d8d91
JB		 399}
400
e7b4c6b1
DV		 401static void snb_gt_irq_handler(struct drm_device *dev,
402 struct drm_i915_private *dev_priv,
403 u32 gt_iir)
404{
405
406 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
407 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
408 notify_ring(dev, &dev_priv->ring[RCS]);
409 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
410 notify_ring(dev, &dev_priv->ring[VCS]);
411 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
412 notify_ring(dev, &dev_priv->ring[BCS]);
413
414 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
415 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
416 GT_RENDER_CS_ERROR_INTERRUPT)) {
417 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
418 i915_handle_error(dev, false);
419 }
420}
421
fc6826d1
CW		 422static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
423 u32 pm_iir)
424{
425 unsigned long flags;
426
427 /*
428 * IIR bits should never already be set because IMR should
429 * prevent an interrupt from being shown in IIR. The warning
430 * displays a case where we've unsafely cleared
431 * dev_priv->pm_iir. Although missing an interrupt of the same
432 * type is not a problem, it displays a problem in the logic.
433 *
434 * The mask bit in IMR is cleared by rps_work.
435 */
436
437 spin_lock_irqsave(&dev_priv->rps_lock, flags);
438 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
439 dev_priv->pm_iir |= pm_iir;
440 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
441 POSTING_READ(GEN6_PMIMR);
442 spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
443
444 queue_work(dev_priv->wq, &dev_priv->rps_work);
445}
446
7e231dbe
JB		 447static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
448{
449 struct drm_device *dev = (struct drm_device *) arg;
450 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
451 u32 iir, gt_iir, pm_iir;
452 irqreturn_t ret = IRQ_NONE;
453 unsigned long irqflags;
454 int pipe;
455 u32 pipe_stats[I915_MAX_PIPES];
456 u32 vblank_status;
457 int vblank = 0;
458 bool blc_event;
459
460 atomic_inc(&dev_priv->irq_received);
461
462 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS |
463 PIPE_VBLANK_INTERRUPT_STATUS;
464
465 while (true) {
466 iir = I915_READ(VLV_IIR);
467 gt_iir = I915_READ(GTIIR);
468 pm_iir = I915_READ(GEN6_PMIIR);
469
470 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
471 goto out;
472
473 ret = IRQ_HANDLED;
474
e7b4c6b1 475 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 476
477 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
478 for_each_pipe(pipe) {
479 int reg = PIPESTAT(pipe);
480 pipe_stats[pipe] = I915_READ(reg);
481
482 /*
483 * Clear the PIPE*STAT regs before the IIR
484 */
485 if (pipe_stats[pipe] & 0x8000ffff) {
486 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
487 DRM_DEBUG_DRIVER("pipe %c underrun\n",
488 pipe_name(pipe));
489 I915_WRITE(reg, pipe_stats[pipe]);
490 }
491 }
492 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
493
494 /* Consume port. Then clear IIR or we'll miss events */
495 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
496 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
497
498 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
499 hotplug_status);
500 if (hotplug_status & dev_priv->hotplug_supported_mask)
501 queue_work(dev_priv->wq,
502 &dev_priv->hotplug_work);
503
504 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
505 I915_READ(PORT_HOTPLUG_STAT);
506 }
507
508
509 if (iir & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) {
510 drm_handle_vblank(dev, 0);
511 vblank++;
e0f608d7 512 intel_finish_page_flip(dev, 0);
7e231dbe
JB		 513 }
514
515 if (iir & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) {
516 drm_handle_vblank(dev, 1);
517 vblank++;
e0f608d7 518 intel_finish_page_flip(dev, 0);
7e231dbe
JB		 519 }
520
521 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
522 blc_event = true;
523
fc6826d1
CW		 524 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
525 gen6_queue_rps_work(dev_priv, pm_iir);
7e231dbe
JB		 526
527 I915_WRITE(GTIIR, gt_iir);
528 I915_WRITE(GEN6_PMIIR, pm_iir);
529 I915_WRITE(VLV_IIR, iir);
530 }
531
532out:
533 return ret;
534}
535
9adab8b5 536static void pch_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 537{
538 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 539 int pipe;
776ad806 540
776ad806
JB		 541 if (pch_iir & SDE_AUDIO_POWER_MASK)
542 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
543 (pch_iir & SDE_AUDIO_POWER_MASK) >>
544 SDE_AUDIO_POWER_SHIFT);
545
546 if (pch_iir & SDE_GMBUS)
547 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
548
549 if (pch_iir & SDE_AUDIO_HDCP_MASK)
550 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
551
552 if (pch_iir & SDE_AUDIO_TRANS_MASK)
553 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
554
555 if (pch_iir & SDE_POISON)
556 DRM_ERROR("PCH poison interrupt\n");
557
9db4a9c7
JB		 558 if (pch_iir & SDE_FDI_MASK)
559 for_each_pipe(pipe)
560 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
561 pipe_name(pipe),
562 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 563
564 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
565 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
566
567 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
568 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
569
570 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
571 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
572 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
573 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
574}
575
f71d4af4 576static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
b1f14ad0
JB		 577{
578 struct drm_device *dev = (struct drm_device *) arg;
579 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
0e43406b
CW		 580 u32 de_iir, gt_iir, de_ier, pm_iir;
581 irqreturn_t ret = IRQ_NONE;
582 int i;
b1f14ad0
JB		 583
584 atomic_inc(&dev_priv->irq_received);
585
586 /* disable master interrupt before clearing iir */
587 de_ier = I915_READ(DEIER);
588 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
b1f14ad0 589
b1f14ad0 590 gt_iir = I915_READ(GTIIR);
0e43406b
CW		 591 if (gt_iir) {
592 snb_gt_irq_handler(dev, dev_priv, gt_iir);
593 I915_WRITE(GTIIR, gt_iir);
594 ret = IRQ_HANDLED;
b1f14ad0
JB		 595 }
596
0e43406b
CW		 597 de_iir = I915_READ(DEIIR);
598 if (de_iir) {
599 if (de_iir & DE_GSE_IVB)
600 intel_opregion_gse_intr(dev);
601
602 for (i = 0; i < 3; i++) {
603 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
604 intel_prepare_page_flip(dev, i);
605 intel_finish_page_flip_plane(dev, i);
606 }
607 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
608 drm_handle_vblank(dev, i);
609 }
b615b57a 610
0e43406b
CW		 611 /* check event from PCH */
612 if (de_iir & DE_PCH_EVENT_IVB) {
613 u32 pch_iir = I915_READ(SDEIIR);
b1f14ad0 614
0e43406b
CW		 615 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
616 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
617 pch_irq_handler(dev, pch_iir);
b1f14ad0 618
0e43406b
CW		 619 /* clear PCH hotplug event before clear CPU irq */
620 I915_WRITE(SDEIIR, pch_iir);
621 }
b615b57a 622
0e43406b
CW		 623 I915_WRITE(DEIIR, de_iir);
624 ret = IRQ_HANDLED;
b1f14ad0
JB		 625 }
626
0e43406b
CW		 627 pm_iir = I915_READ(GEN6_PMIIR);
628 if (pm_iir) {
629 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
630 gen6_queue_rps_work(dev_priv, pm_iir);
631 I915_WRITE(GEN6_PMIIR, pm_iir);
632 ret = IRQ_HANDLED;
633 }
b1f14ad0 634
b1f14ad0
JB		 635 I915_WRITE(DEIER, de_ier);
636 POSTING_READ(DEIER);
637
638 return ret;
639}
640
e7b4c6b1
DV		 641static void ilk_gt_irq_handler(struct drm_device *dev,
642 struct drm_i915_private *dev_priv,
643 u32 gt_iir)
644{
645 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
646 notify_ring(dev, &dev_priv->ring[RCS]);
647 if (gt_iir & GT_BSD_USER_INTERRUPT)
648 notify_ring(dev, &dev_priv->ring[VCS]);
649}
650
f71d4af4 651static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
036a4a7d 652{
4697995b 653 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 654 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
655 int ret = IRQ_NONE;
3b8d8d91 656 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
2d7b8366 657 u32 hotplug_mask;
881f47b6 658
4697995b
JB		 659 atomic_inc(&dev_priv->irq_received);
660
2d109a84
ZN		 661 /* disable master interrupt before clearing iir */
662 de_ier = I915_READ(DEIER);
663 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 664 POSTING_READ(DEIER);
2d109a84 665
036a4a7d
ZW		 666 de_iir = I915_READ(DEIIR);
667 gt_iir = I915_READ(GTIIR);
c650156a 668 pch_iir = I915_READ(SDEIIR);
3b8d8d91 669 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 670
3b8d8d91
JB		 671 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
672 (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 673 goto done;
036a4a7d 674
2d7b8366
YL		 675 if (HAS_PCH_CPT(dev))
676 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
677 else
678 hotplug_mask = SDE_HOTPLUG_MASK;
679
c7c85101 680 ret = IRQ_HANDLED;
036a4a7d 681
e7b4c6b1
DV		 682 if (IS_GEN5(dev))
683 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
684 else
685 snb_gt_irq_handler(dev, dev_priv, gt_iir);
01c66889 686
c7c85101 687 if (de_iir & DE_GSE)
3b617967 688 intel_opregion_gse_intr(dev);
c650156a 689
f072d2e7 690 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 691 intel_prepare_page_flip(dev, 0);
2bbda389 692 intel_finish_page_flip_plane(dev, 0);
f072d2e7 693 }
013d5aa2 694
f072d2e7 695 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 696 intel_prepare_page_flip(dev, 1);
2bbda389 697 intel_finish_page_flip_plane(dev, 1);
f072d2e7 698 }
013d5aa2 699
f072d2e7 700 if (de_iir & DE_PIPEA_VBLANK)
c062df61
LP		 701 drm_handle_vblank(dev, 0);
702
f072d2e7 703 if (de_iir & DE_PIPEB_VBLANK)
c062df61
LP		 704 drm_handle_vblank(dev, 1);
705
c7c85101 706 /* check event from PCH */
776ad806
JB		 707 if (de_iir & DE_PCH_EVENT) {
708 if (pch_iir & hotplug_mask)
709 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
9adab8b5 710 pch_irq_handler(dev, pch_iir);
776ad806 711 }
036a4a7d 712
f97108d1 713 if (de_iir & DE_PCU_EVENT) {
7648fa99 714 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
f97108d1
JB		 715 i915_handle_rps_change(dev);
716 }
717
fc6826d1
CW		 718 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
719 gen6_queue_rps_work(dev_priv, pm_iir);
3b8d8d91 720
c7c85101
ZN		 721 /* should clear PCH hotplug event before clear CPU irq */
722 I915_WRITE(SDEIIR, pch_iir);
723 I915_WRITE(GTIIR, gt_iir);
724 I915_WRITE(DEIIR, de_iir);
4912d041 725 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 726
727done:
2d109a84 728 I915_WRITE(DEIER, de_ier);
3143a2bf 729 POSTING_READ(DEIER);
2d109a84 730
036a4a7d
ZW		 731 return ret;
732}
733
8a905236
JB		 734/**
735 * i915_error_work_func - do process context error handling work
736 * @work: work struct
737 *
738 * Fire an error uevent so userspace can see that a hang or error
739 * was detected.
740 */
741static void i915_error_work_func(struct work_struct *work)
742{
743 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
744 error_work);
745 struct drm_device *dev = dev_priv->dev;
f316a42c
BG		 746 char *error_event[] = { "ERROR=1", NULL };
747 char *reset_event[] = { "RESET=1", NULL };
748 char *reset_done_event[] = { "ERROR=0", NULL };
8a905236 749
f316a42c
BG		 750 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
751
ba1234d1 752 if (atomic_read(&dev_priv->mm.wedged)) {
f803aa55
CW		 753 DRM_DEBUG_DRIVER("resetting chip\n");
754 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
d4b8bb2a 755 if (!i915_reset(dev)) {
f803aa55
CW		 756 atomic_set(&dev_priv->mm.wedged, 0);
757 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
f316a42c 758 }
30dbf0c0 759 complete_all(&dev_priv->error_completion);
f316a42c 760 }
8a905236
JB		 761}
762
3bd3c932 763#ifdef CONFIG_DEBUG_FS
9df30794 764static struct drm_i915_error_object *
bcfb2e28 765i915_error_object_create(struct drm_i915_private *dev_priv,
05394f39 766 struct drm_i915_gem_object *src)
9df30794
CW		 767{
768 struct drm_i915_error_object *dst;
9df30794 769 int page, page_count;
e56660dd 770 u32 reloc_offset;
9df30794 771
05394f39 772 if (src == NULL || src->pages == NULL)
9df30794
CW		 773 return NULL;
774
05394f39 775 page_count = src->base.size / PAGE_SIZE;
9df30794 776
0206e353 777 dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
9df30794
CW		 778 if (dst == NULL)
779 return NULL;
780
05394f39 781 reloc_offset = src->gtt_offset;
9df30794 782 for (page = 0; page < page_count; page++) {
788885ae 783 unsigned long flags;
e56660dd 784 void *d;
788885ae 785
e56660dd 786 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 787 if (d == NULL)
788 goto unwind;
e56660dd 789
788885ae 790 local_irq_save(flags);
74898d7e
DV		 791 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
792 src->has_global_gtt_mapping) {
172975aa
CW		 793 void __iomem *s;
794
795 /* Simply ignore tiling or any overlapping fence.
796 * It's part of the error state, and this hopefully
797 * captures what the GPU read.
798 */
799
800 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
801 reloc_offset);
802 memcpy_fromio(d, s, PAGE_SIZE);
803 io_mapping_unmap_atomic(s);
804 } else {
805 void *s;
806
807 drm_clflush_pages(&src->pages[page], 1);
808
809 s = kmap_atomic(src->pages[page]);
810 memcpy(d, s, PAGE_SIZE);
811 kunmap_atomic(s);
812
813 drm_clflush_pages(&src->pages[page], 1);
814 }
788885ae 815 local_irq_restore(flags);
e56660dd 816
9df30794 817 dst->pages[page] = d;
e56660dd
CW		 818
819 reloc_offset += PAGE_SIZE;
9df30794
CW		 820 }
821 dst->page_count = page_count;
05394f39 822 dst->gtt_offset = src->gtt_offset;
9df30794
CW		 823
824 return dst;
825
826unwind:
827 while (page--)
828 kfree(dst->pages[page]);
829 kfree(dst);
830 return NULL;
831}
832
833static void
834i915_error_object_free(struct drm_i915_error_object *obj)
835{
836 int page;
837
838 if (obj == NULL)
839 return;
840
841 for (page = 0; page < obj->page_count; page++)
842 kfree(obj->pages[page]);
843
844 kfree(obj);
845}
846
742cbee8
DV		 847void
848i915_error_state_free(struct kref *error_ref)
9df30794 849{
742cbee8
DV		 850 struct drm_i915_error_state *error = container_of(error_ref,
851 typeof(*error), ref);
e2f973d5
CW		 852 int i;
853
52d39a21
CW		 854 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
855 i915_error_object_free(error->ring[i].batchbuffer);
856 i915_error_object_free(error->ring[i].ringbuffer);
857 kfree(error->ring[i].requests);
858 }
e2f973d5 859
9df30794 860 kfree(error->active_bo);
6ef3d427 861 kfree(error->overlay);
9df30794
CW		 862 kfree(error);
863}
1b50247a
CW		 864static void capture_bo(struct drm_i915_error_buffer *err,
865 struct drm_i915_gem_object *obj)
866{
867 err->size = obj->base.size;
868 err->name = obj->base.name;
869 err->seqno = obj->last_rendering_seqno;
870 err->gtt_offset = obj->gtt_offset;
871 err->read_domains = obj->base.read_domains;
872 err->write_domain = obj->base.write_domain;
873 err->fence_reg = obj->fence_reg;
874 err->pinned = 0;
875 if (obj->pin_count > 0)
876 err->pinned = 1;
877 if (obj->user_pin_count > 0)
878 err->pinned = -1;
879 err->tiling = obj->tiling_mode;
880 err->dirty = obj->dirty;
881 err->purgeable = obj->madv != I915_MADV_WILLNEED;
882 err->ring = obj->ring ? obj->ring->id : -1;
883 err->cache_level = obj->cache_level;
884}
9df30794 885
1b50247a
CW		 886static u32 capture_active_bo(struct drm_i915_error_buffer *err,
887 int count, struct list_head *head)
c724e8a9
CW		 888{
889 struct drm_i915_gem_object *obj;
890 int i = 0;
891
892 list_for_each_entry(obj, head, mm_list) {
1b50247a 893 capture_bo(err++, obj);
c724e8a9
CW		 894 if (++i == count)
895 break;
1b50247a
CW		 896 }
897
898 return i;
899}
900
901static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
902 int count, struct list_head *head)
903{
904 struct drm_i915_gem_object *obj;
905 int i = 0;
906
907 list_for_each_entry(obj, head, gtt_list) {
908 if (obj->pin_count == 0)
909 continue;
c724e8a9 910
1b50247a
CW		 911 capture_bo(err++, obj);
912 if (++i == count)
913 break;
c724e8a9
CW		 914 }
915
916 return i;
917}
918
748ebc60
CW		 919static void i915_gem_record_fences(struct drm_device *dev,
920 struct drm_i915_error_state *error)
921{
922 struct drm_i915_private *dev_priv = dev->dev_private;
923 int i;
924
925 /* Fences */
926 switch (INTEL_INFO(dev)->gen) {
775d17b6 927 case 7:
748ebc60
CW		 928 case 6:
929 for (i = 0; i < 16; i++)
930 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
931 break;
932 case 5:
933 case 4:
934 for (i = 0; i < 16; i++)
935 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
936 break;
937 case 3:
938 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
939 for (i = 0; i < 8; i++)
940 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
941 case 2:
942 for (i = 0; i < 8; i++)
943 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
944 break;
945
946 }
947}
948
bcfb2e28
CW		 949static struct drm_i915_error_object *
950i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
951 struct intel_ring_buffer *ring)
952{
953 struct drm_i915_gem_object *obj;
954 u32 seqno;
955
956 if (!ring->get_seqno)
957 return NULL;
958
959 seqno = ring->get_seqno(ring);
960 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
961 if (obj->ring != ring)
962 continue;
963
c37d9a5d 964 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
bcfb2e28
CW		 965 continue;
966
967 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
968 continue;
969
970 /* We need to copy these to an anonymous buffer as the simplest
971 * method to avoid being overwritten by userspace.
972 */
973 return i915_error_object_create(dev_priv, obj);
974 }
975
976 return NULL;
977}
978
d27b1e0e
DV		 979static void i915_record_ring_state(struct drm_device *dev,
980 struct drm_i915_error_state *error,
981 struct intel_ring_buffer *ring)
982{
983 struct drm_i915_private *dev_priv = dev->dev_private;
984
33f3f518 985 if (INTEL_INFO(dev)->gen >= 6) {
33f3f518 986 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
7e3b8737
DV		 987 error->semaphore_mboxes[ring->id][0]
988 = I915_READ(RING_SYNC_0(ring->mmio_base));
989 error->semaphore_mboxes[ring->id][1]
990 = I915_READ(RING_SYNC_1(ring->mmio_base));
33f3f518 991 }
c1cd90ed 992
d27b1e0e 993 if (INTEL_INFO(dev)->gen >= 4) {
9d2f41fa 994 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
d27b1e0e
DV		 995 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
996 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
997 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
c1cd90ed 998 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
d27b1e0e 999 if (ring->id == RCS) {
d27b1e0e
DV		 1000 error->instdone1 = I915_READ(INSTDONE1);
1001 error->bbaddr = I915_READ64(BB_ADDR);
1002 }
1003 } else {
9d2f41fa 1004 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
d27b1e0e
DV		 1005 error->ipeir[ring->id] = I915_READ(IPEIR);
1006 error->ipehr[ring->id] = I915_READ(IPEHR);
1007 error->instdone[ring->id] = I915_READ(INSTDONE);
d27b1e0e
DV		 1008 }
1009
9574b3fe 1010 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
c1cd90ed 1011 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
d27b1e0e
DV		 1012 error->seqno[ring->id] = ring->get_seqno(ring);
1013 error->acthd[ring->id] = intel_ring_get_active_head(ring);
c1cd90ed
DV		 1014 error->head[ring->id] = I915_READ_HEAD(ring);
1015 error->tail[ring->id] = I915_READ_TAIL(ring);
7e3b8737
DV		 1016
1017 error->cpu_ring_head[ring->id] = ring->head;
1018 error->cpu_ring_tail[ring->id] = ring->tail;
d27b1e0e
DV		 1019}
1020
52d39a21
CW		 1021static void i915_gem_record_rings(struct drm_device *dev,
1022 struct drm_i915_error_state *error)
1023{
1024 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 1025 struct intel_ring_buffer *ring;
52d39a21
CW		 1026 struct drm_i915_gem_request *request;
1027 int i, count;
1028
b4519513 1029 for_each_ring(ring, dev_priv, i) {
52d39a21
CW		 1030 i915_record_ring_state(dev, error, ring);
1031
1032 error->ring[i].batchbuffer =
1033 i915_error_first_batchbuffer(dev_priv, ring);
1034
1035 error->ring[i].ringbuffer =
1036 i915_error_object_create(dev_priv, ring->obj);
1037
1038 count = 0;
1039 list_for_each_entry(request, &ring->request_list, list)
1040 count++;
1041
1042 error->ring[i].num_requests = count;
1043 error->ring[i].requests =
1044 kmalloc(count*sizeof(struct drm_i915_error_request),
1045 GFP_ATOMIC);
1046 if (error->ring[i].requests == NULL) {
1047 error->ring[i].num_requests = 0;
1048 continue;
1049 }
1050
1051 count = 0;
1052 list_for_each_entry(request, &ring->request_list, list) {
1053 struct drm_i915_error_request *erq;
1054
1055 erq = &error->ring[i].requests[count++];
1056 erq->seqno = request->seqno;
1057 erq->jiffies = request->emitted_jiffies;
ee4f42b1 1058 erq->tail = request->tail;
52d39a21
CW		 1059 }
1060 }
1061}
1062
8a905236
JB		 1063/**
1064 * i915_capture_error_state - capture an error record for later analysis
1065 * @dev: drm device
1066 *
1067 * Should be called when an error is detected (either a hang or an error
1068 * interrupt) to capture error state from the time of the error. Fills
1069 * out a structure which becomes available in debugfs for user level tools
1070 * to pick up.
1071 */
63eeaf38
JB		 1072static void i915_capture_error_state(struct drm_device *dev)
1073{
1074 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1075 struct drm_i915_gem_object *obj;
63eeaf38
JB		 1076 struct drm_i915_error_state *error;
1077 unsigned long flags;
9db4a9c7 1078 int i, pipe;
63eeaf38
JB		 1079
1080 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1081 error = dev_priv->first_error;
1082 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1083 if (error)
1084 return;
63eeaf38 1085
9db4a9c7 1086 /* Account for pipe specific data like PIPE*STAT */
33f3f518 1087 error = kzalloc(sizeof(*error), GFP_ATOMIC);
63eeaf38 1088 if (!error) {
9df30794
CW		 1089 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1090 return;
63eeaf38
JB		 1091 }
1092
b6f7833b
CW		 1093 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1094 dev->primary->index);
2fa772f3 1095
742cbee8 1096 kref_init(&error->ref);
63eeaf38
JB		 1097 error->eir = I915_READ(EIR);
1098 error->pgtbl_er = I915_READ(PGTBL_ER);
be998e2e
BW		 1099
1100 if (HAS_PCH_SPLIT(dev))
1101 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1102 else if (IS_VALLEYVIEW(dev))
1103 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1104 else if (IS_GEN2(dev))
1105 error->ier = I915_READ16(IER);
1106 else
1107 error->ier = I915_READ(IER);
1108
9db4a9c7
JB		 1109 for_each_pipe(pipe)
1110 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
d27b1e0e 1111
33f3f518 1112 if (INTEL_INFO(dev)->gen >= 6) {
f406839f 1113 error->error = I915_READ(ERROR_GEN6);
33f3f518
DV		 1114 error->done_reg = I915_READ(DONE_REG);
1115 }
d27b1e0e 1116
748ebc60 1117 i915_gem_record_fences(dev, error);
52d39a21 1118 i915_gem_record_rings(dev, error);
9df30794 1119
c724e8a9 1120 /* Record buffers on the active and pinned lists. */
9df30794 1121 error->active_bo = NULL;
c724e8a9 1122 error->pinned_bo = NULL;
9df30794 1123
bcfb2e28
CW		 1124 i = 0;
1125 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1126 i++;
1127 error->active_bo_count = i;
1b50247a
CW		 1128 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
1129 if (obj->pin_count)
1130 i++;
bcfb2e28 1131 error->pinned_bo_count = i - error->active_bo_count;
c724e8a9 1132
8e934dbf
CW		 1133 error->active_bo = NULL;
1134 error->pinned_bo = NULL;
bcfb2e28
CW		 1135 if (i) {
1136 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
9df30794 1137 GFP_ATOMIC);
c724e8a9
CW		 1138 if (error->active_bo)
1139 error->pinned_bo =
1140 error->active_bo + error->active_bo_count;
9df30794
CW		 1141 }
1142
c724e8a9
CW		 1143 if (error->active_bo)
1144 error->active_bo_count =
1b50247a
CW		 1145 capture_active_bo(error->active_bo,
1146 error->active_bo_count,
1147 &dev_priv->mm.active_list);
c724e8a9
CW		 1148
1149 if (error->pinned_bo)
1150 error->pinned_bo_count =
1b50247a
CW		 1151 capture_pinned_bo(error->pinned_bo,
1152 error->pinned_bo_count,
1153 &dev_priv->mm.gtt_list);
c724e8a9 1154
9df30794
CW		 1155 do_gettimeofday(&error->time);
1156
6ef3d427 1157 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 1158 error->display = intel_display_capture_error_state(dev);
6ef3d427 1159
9df30794
CW		 1160 spin_lock_irqsave(&dev_priv->error_lock, flags);
1161 if (dev_priv->first_error == NULL) {
1162 dev_priv->first_error = error;
1163 error = NULL;
1164 }
63eeaf38 1165 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1166
1167 if (error)
742cbee8 1168 i915_error_state_free(&error->ref);
9df30794
CW		 1169}
1170
1171void i915_destroy_error_state(struct drm_device *dev)
1172{
1173 struct drm_i915_private *dev_priv = dev->dev_private;
1174 struct drm_i915_error_state *error;
6dc0e816 1175 unsigned long flags;
9df30794 1176
6dc0e816 1177 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1178 error = dev_priv->first_error;
1179 dev_priv->first_error = NULL;
6dc0e816 1180 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1181
1182 if (error)
742cbee8 1183 kref_put(&error->ref, i915_error_state_free);
63eeaf38 1184}
3bd3c932
CW		 1185#else
1186#define i915_capture_error_state(x)
1187#endif
63eeaf38 1188
35aed2e6 1189static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1190{
1191 struct drm_i915_private *dev_priv = dev->dev_private;
1192 u32 eir = I915_READ(EIR);
9db4a9c7 1193 int pipe;
8a905236 1194
35aed2e6
CW		 1195 if (!eir)
1196 return;
8a905236 1197
a70491cc 1198 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236
JB		 1199
1200 if (IS_G4X(dev)) {
1201 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1202 u32 ipeir = I915_READ(IPEIR_I965);
1203
a70491cc
JP		 1204 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1205 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1206 pr_err(" INSTDONE: 0x%08x\n",
8a905236 1207 I915_READ(INSTDONE_I965));
a70491cc
JP		 1208 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1209 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1210 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1211 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1212 POSTING_READ(IPEIR_I965);
8a905236
JB		 1213 }
1214 if (eir & GM45_ERROR_PAGE_TABLE) {
1215 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1216 pr_err("page table error\n");
1217 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1218 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1219 POSTING_READ(PGTBL_ER);
8a905236
JB		 1220 }
1221 }
1222
a6c45cf0 1223 if (!IS_GEN2(dev)) {
8a905236
JB		 1224 if (eir & I915_ERROR_PAGE_TABLE) {
1225 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1226 pr_err("page table error\n");
1227 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1228 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1229 POSTING_READ(PGTBL_ER);
8a905236
JB		 1230 }
1231 }
1232
1233 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 1234 pr_err("memory refresh error:\n");
9db4a9c7 1235 for_each_pipe(pipe)
a70491cc 1236 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 1237 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 1238 /* pipestat has already been acked */
1239 }
1240 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 1241 pr_err("instruction error\n");
1242 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
a6c45cf0 1243 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 1244 u32 ipeir = I915_READ(IPEIR);
1245
a70491cc
JP		 1246 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1247 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
1248 pr_err(" INSTDONE: 0x%08x\n", I915_READ(INSTDONE));
1249 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 1250 I915_WRITE(IPEIR, ipeir);
3143a2bf 1251 POSTING_READ(IPEIR);
8a905236
JB		 1252 } else {
1253 u32 ipeir = I915_READ(IPEIR_I965);
1254
a70491cc
JP		 1255 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1256 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1257 pr_err(" INSTDONE: 0x%08x\n",
8a905236 1258 I915_READ(INSTDONE_I965));
a70491cc
JP		 1259 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1260 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1261 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1262 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1263 POSTING_READ(IPEIR_I965);
8a905236
JB		 1264 }
1265 }
1266
1267 I915_WRITE(EIR, eir);
3143a2bf 1268 POSTING_READ(EIR);
8a905236
JB		 1269 eir = I915_READ(EIR);
1270 if (eir) {
1271 /*
1272 * some errors might have become stuck,
1273 * mask them.
1274 */
1275 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1276 I915_WRITE(EMR, I915_READ(EMR) | eir);
1277 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1278 }
35aed2e6
CW		 1279}
1280
1281/**
1282 * i915_handle_error - handle an error interrupt
1283 * @dev: drm device
1284 *
1285 * Do some basic checking of regsiter state at error interrupt time and
1286 * dump it to the syslog. Also call i915_capture_error_state() to make
1287 * sure we get a record and make it available in debugfs. Fire a uevent
1288 * so userspace knows something bad happened (should trigger collection
1289 * of a ring dump etc.).
1290 */
527f9e90 1291void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 1292{
1293 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513
CW		 1294 struct intel_ring_buffer *ring;
1295 int i;
35aed2e6
CW		 1296
1297 i915_capture_error_state(dev);
1298 i915_report_and_clear_eir(dev);
8a905236 1299
ba1234d1 1300 if (wedged) {
30dbf0c0 1301 INIT_COMPLETION(dev_priv->error_completion);
ba1234d1
BG		 1302 atomic_set(&dev_priv->mm.wedged, 1);
1303
11ed50ec
BG		 1304 /*
1305 * Wakeup waiting processes so they don't hang
1306 */
b4519513
CW		 1307 for_each_ring(ring, dev_priv, i)
1308 wake_up_all(&ring->irq_queue);
11ed50ec
BG		 1309 }
1310
9c9fe1f8 1311 queue_work(dev_priv->wq, &dev_priv->error_work);
8a905236
JB		 1312}
1313
4e5359cd
SF		 1314static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1315{
1316 drm_i915_private_t *dev_priv = dev->dev_private;
1317 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1318 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 1319 struct drm_i915_gem_object *obj;
4e5359cd
SF		 1320 struct intel_unpin_work *work;
1321 unsigned long flags;
1322 bool stall_detected;
1323
1324 /* Ignore early vblank irqs */
1325 if (intel_crtc == NULL)
1326 return;
1327
1328 spin_lock_irqsave(&dev->event_lock, flags);
1329 work = intel_crtc->unpin_work;
1330
1331 if (work == NULL || work->pending || !work->enable_stall_check) {
1332 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1333 spin_unlock_irqrestore(&dev->event_lock, flags);
1334 return;
1335 }
1336
1337 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 1338 obj = work->pending_flip_obj;
a6c45cf0 1339 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 1340 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545
AR		 1341 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1342 obj->gtt_offset;
4e5359cd 1343 } else {
9db4a9c7 1344 int dspaddr = DSPADDR(intel_crtc->plane);
05394f39 1345 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
01f2c773 1346 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 1347 crtc->x * crtc->fb->bits_per_pixel/8);
1348 }
1349
1350 spin_unlock_irqrestore(&dev->event_lock, flags);
1351
1352 if (stall_detected) {
1353 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1354 intel_prepare_page_flip(dev, intel_crtc->plane);
1355 }
1356}
1357
42f52ef8
KP		 1358/* Called from drm generic code, passed 'crtc' which
1359 * we use as a pipe index
1360 */
f71d4af4 1361static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1362{
1363 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1364 unsigned long irqflags;
71e0ffa5 1365
5eddb70b 1366 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 1367 return -EINVAL;
0a3e67a4 1368
1ec14ad3 1369 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 1370 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 1371 i915_enable_pipestat(dev_priv, pipe,
1372 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 1373 else
7c463586
KP		 1374 i915_enable_pipestat(dev_priv, pipe,
1375 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 1376
1377 /* maintain vblank delivery even in deep C-states */
1378 if (dev_priv->info->gen == 3)
6b26c86d 1379 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 1380 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 1381
0a3e67a4
JB		 1382 return 0;
1383}
1384
f71d4af4 1385static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1386{
1387 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1388 unsigned long irqflags;
1389
1390 if (!i915_pipe_enabled(dev, pipe))
1391 return -EINVAL;
1392
1393 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1394 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1395 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
f796cf8f
JB		 1396 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1397
1398 return 0;
1399}
1400
f71d4af4 1401static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1402{
1403 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1404 unsigned long irqflags;
1405
1406 if (!i915_pipe_enabled(dev, pipe))
1407 return -EINVAL;
1408
1409 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1410 ironlake_enable_display_irq(dev_priv,
1411 DE_PIPEA_VBLANK_IVB << (5 * pipe));
b1f14ad0
JB		 1412 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1413
1414 return 0;
1415}
1416
7e231dbe
JB		 1417static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1418{
1419 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1420 unsigned long irqflags;
1421 u32 dpfl, imr;
1422
1423 if (!i915_pipe_enabled(dev, pipe))
1424 return -EINVAL;
1425
1426 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1427 dpfl = I915_READ(VLV_DPFLIPSTAT);
1428 imr = I915_READ(VLV_IMR);
1429 if (pipe == 0) {
1430 dpfl |= PIPEA_VBLANK_INT_EN;
1431 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1432 } else {
1433 dpfl |= PIPEA_VBLANK_INT_EN;
1434 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1435 }
1436 I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1437 I915_WRITE(VLV_IMR, imr);
1438 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1439
1440 return 0;
1441}
1442
42f52ef8
KP		 1443/* Called from drm generic code, passed 'crtc' which
1444 * we use as a pipe index
1445 */
f71d4af4 1446static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1447{
1448 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1449 unsigned long irqflags;
0a3e67a4 1450
1ec14ad3 1451 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 1452 if (dev_priv->info->gen == 3)
6b26c86d 1453 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 1454
f796cf8f
JB		 1455 i915_disable_pipestat(dev_priv, pipe,
1456 PIPE_VBLANK_INTERRUPT_ENABLE |
1457 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1458 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1459}
1460
f71d4af4 1461static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1462{
1463 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1464 unsigned long irqflags;
1465
1466 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1467 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1468 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1ec14ad3 1469 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 1470}
1471
f71d4af4 1472static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1473{
1474 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1475 unsigned long irqflags;
1476
1477 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1478 ironlake_disable_display_irq(dev_priv,
1479 DE_PIPEA_VBLANK_IVB << (pipe * 5));
b1f14ad0
JB		 1480 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1481}
1482
7e231dbe
JB		 1483static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1484{
1485 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1486 unsigned long irqflags;
1487 u32 dpfl, imr;
1488
1489 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1490 dpfl = I915_READ(VLV_DPFLIPSTAT);
1491 imr = I915_READ(VLV_IMR);
1492 if (pipe == 0) {
1493 dpfl &= ~PIPEA_VBLANK_INT_EN;
1494 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1495 } else {
1496 dpfl &= ~PIPEB_VBLANK_INT_EN;
1497 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1498 }
1499 I915_WRITE(VLV_IMR, imr);
1500 I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1501 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1502}
1503
893eead0
CW		 1504static u32
1505ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 1506{
893eead0
CW		 1507 return list_entry(ring->request_list.prev,
1508 struct drm_i915_gem_request, list)->seqno;
1509}
1510
1511static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1512{
1513 if (list_empty(&ring->request_list) ||
1514 i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1515 /* Issue a wake-up to catch stuck h/w. */
9574b3fe
BW		 1516 if (waitqueue_active(&ring->irq_queue)) {
1517 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1518 ring->name);
893eead0
CW		 1519 wake_up_all(&ring->irq_queue);
1520 *err = true;
1521 }
1522 return true;
1523 }
1524 return false;
f65d9421
BG		 1525}
1526
1ec14ad3
CW		 1527static bool kick_ring(struct intel_ring_buffer *ring)
1528{
1529 struct drm_device *dev = ring->dev;
1530 struct drm_i915_private *dev_priv = dev->dev_private;
1531 u32 tmp = I915_READ_CTL(ring);
1532 if (tmp & RING_WAIT) {
1533 DRM_ERROR("Kicking stuck wait on %s\n",
1534 ring->name);
1535 I915_WRITE_CTL(ring, tmp);
1536 return true;
1537 }
1ec14ad3
CW		 1538 return false;
1539}
1540
d1e61e7f
CW		 1541static bool i915_hangcheck_hung(struct drm_device *dev)
1542{
1543 drm_i915_private_t *dev_priv = dev->dev_private;
1544
1545 if (dev_priv->hangcheck_count++ > 1) {
b4519513
CW		 1546 bool hung = true;
1547
d1e61e7f
CW		 1548 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1549 i915_handle_error(dev, true);
1550
1551 if (!IS_GEN2(dev)) {
b4519513
CW		 1552 struct intel_ring_buffer *ring;
1553 int i;
1554
d1e61e7f
CW		 1555 /* Is the chip hanging on a WAIT_FOR_EVENT?
1556 * If so we can simply poke the RB_WAIT bit
1557 * and break the hang. This should work on
1558 * all but the second generation chipsets.
1559 */
b4519513
CW		 1560 for_each_ring(ring, dev_priv, i)
1561 hung &= !kick_ring(ring);
d1e61e7f
CW		 1562 }
1563
b4519513 1564 return hung;
d1e61e7f
CW		 1565 }
1566
1567 return false;
1568}
1569
f65d9421
BG		 1570/**
1571 * This is called when the chip hasn't reported back with completed
1572 * batchbuffers in a long time. The first time this is called we simply record
1573 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1574 * again, we assume the chip is wedged and try to fix it.
1575 */
1576void i915_hangcheck_elapsed(unsigned long data)
1577{
1578 struct drm_device *dev = (struct drm_device *)data;
1579 drm_i915_private_t *dev_priv = dev->dev_private;
b4519513
CW		 1580 uint32_t acthd[I915_NUM_RINGS], instdone, instdone1;
1581 struct intel_ring_buffer *ring;
1582 bool err = false, idle;
1583 int i;
893eead0 1584
3e0dc6b0
BW		 1585 if (!i915_enable_hangcheck)
1586 return;
1587
b4519513
CW		 1588 memset(acthd, 0, sizeof(acthd));
1589 idle = true;
1590 for_each_ring(ring, dev_priv, i) {
1591 idle &= i915_hangcheck_ring_idle(ring, &err);
1592 acthd[i] = intel_ring_get_active_head(ring);
1593 }
1594
893eead0 1595 /* If all work is done then ACTHD clearly hasn't advanced. */
b4519513 1596 if (idle) {
d1e61e7f
CW		 1597 if (err) {
1598 if (i915_hangcheck_hung(dev))
1599 return;
1600
893eead0 1601 goto repeat;
d1e61e7f
CW		 1602 }
1603
1604 dev_priv->hangcheck_count = 0;
893eead0
CW		 1605 return;
1606 }
b9201c14 1607
a6c45cf0 1608 if (INTEL_INFO(dev)->gen < 4) {
cbb465e7
CW		 1609 instdone = I915_READ(INSTDONE);
1610 instdone1 = 0;
1611 } else {
cbb465e7
CW		 1612 instdone = I915_READ(INSTDONE_I965);
1613 instdone1 = I915_READ(INSTDONE1);
1614 }
b4519513
CW		 1615
1616 if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 &&
cbb465e7
CW		 1617 dev_priv->last_instdone == instdone &&
1618 dev_priv->last_instdone1 == instdone1) {
d1e61e7f 1619 if (i915_hangcheck_hung(dev))
cbb465e7 1620 return;
cbb465e7
CW		 1621 } else {
1622 dev_priv->hangcheck_count = 0;
1623
b4519513 1624 memcpy(dev_priv->last_acthd, acthd, sizeof(acthd));
cbb465e7
CW		 1625 dev_priv->last_instdone = instdone;
1626 dev_priv->last_instdone1 = instdone1;
1627 }
f65d9421 1628
893eead0 1629repeat:
f65d9421 1630 /* Reset timer case chip hangs without another request being added */
b3b079db
CW		 1631 mod_timer(&dev_priv->hangcheck_timer,
1632 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
f65d9421
BG		 1633}
1634
1da177e4
LT		 1635/* drm_dma.h hooks
1636*/
f71d4af4 1637static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 1638{
1639 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1640
4697995b
JB		 1641 atomic_set(&dev_priv->irq_received, 0);
1642
4697995b 1643
036a4a7d 1644 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 1645
036a4a7d
ZW		 1646 /* XXX hotplug from PCH */
1647
1648 I915_WRITE(DEIMR, 0xffffffff);
1649 I915_WRITE(DEIER, 0x0);
3143a2bf 1650 POSTING_READ(DEIER);
036a4a7d
ZW		 1651
1652 /* and GT */
1653 I915_WRITE(GTIMR, 0xffffffff);
1654 I915_WRITE(GTIER, 0x0);
3143a2bf 1655 POSTING_READ(GTIER);
c650156a
ZW		 1656
1657 /* south display irq */
1658 I915_WRITE(SDEIMR, 0xffffffff);
1659 I915_WRITE(SDEIER, 0x0);
3143a2bf 1660 POSTING_READ(SDEIER);
036a4a7d
ZW		 1661}
1662
7e231dbe
JB		 1663static void valleyview_irq_preinstall(struct drm_device *dev)
1664{
1665 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1666 int pipe;
1667
1668 atomic_set(&dev_priv->irq_received, 0);
1669
7e231dbe
JB		 1670 /* VLV magic */
1671 I915_WRITE(VLV_IMR, 0);
1672 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1673 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1674 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1675
7e231dbe
JB		 1676 /* and GT */
1677 I915_WRITE(GTIIR, I915_READ(GTIIR));
1678 I915_WRITE(GTIIR, I915_READ(GTIIR));
1679 I915_WRITE(GTIMR, 0xffffffff);
1680 I915_WRITE(GTIER, 0x0);
1681 POSTING_READ(GTIER);
1682
1683 I915_WRITE(DPINVGTT, 0xff);
1684
1685 I915_WRITE(PORT_HOTPLUG_EN, 0);
1686 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1687 for_each_pipe(pipe)
1688 I915_WRITE(PIPESTAT(pipe), 0xffff);
1689 I915_WRITE(VLV_IIR, 0xffffffff);
1690 I915_WRITE(VLV_IMR, 0xffffffff);
1691 I915_WRITE(VLV_IER, 0x0);
1692 POSTING_READ(VLV_IER);
1693}
1694
7fe0b973
KP		 1695/*
1696 * Enable digital hotplug on the PCH, and configure the DP short pulse
1697 * duration to 2ms (which is the minimum in the Display Port spec)
1698 *
1699 * This register is the same on all known PCH chips.
1700 */
1701
1702static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1703{
1704 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1705 u32 hotplug;
1706
1707 hotplug = I915_READ(PCH_PORT_HOTPLUG);
1708 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1709 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1710 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1711 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1712 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1713}
1714
f71d4af4 1715static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d
ZW		 1716{
1717 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1718 /* enable kind of interrupts always enabled */
013d5aa2
JB		 1719 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1720 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1ec14ad3 1721 u32 render_irqs;
2d7b8366 1722 u32 hotplug_mask;
036a4a7d 1723
1ec14ad3 1724 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 1725
1726 /* should always can generate irq */
1727 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3
CW		 1728 I915_WRITE(DEIMR, dev_priv->irq_mask);
1729 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
3143a2bf 1730 POSTING_READ(DEIER);
036a4a7d 1731
1ec14ad3 1732 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 1733
1734 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 1735 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 1736
1ec14ad3
CW		 1737 if (IS_GEN6(dev))
1738 render_irqs =
1739 GT_USER_INTERRUPT |
e2a1e2f0
BW		 1740 GEN6_BSD_USER_INTERRUPT |
1741 GEN6_BLITTER_USER_INTERRUPT;
1ec14ad3
CW		 1742 else
1743 render_irqs =
88f23b8f 1744 GT_USER_INTERRUPT |
c6df541c 1745 GT_PIPE_NOTIFY |
1ec14ad3
CW		 1746 GT_BSD_USER_INTERRUPT;
1747 I915_WRITE(GTIER, render_irqs);
3143a2bf 1748 POSTING_READ(GTIER);
036a4a7d 1749
2d7b8366 1750 if (HAS_PCH_CPT(dev)) {
9035a97a
CW		 1751 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1752 SDE_PORTB_HOTPLUG_CPT |
1753 SDE_PORTC_HOTPLUG_CPT |
1754 SDE_PORTD_HOTPLUG_CPT);
2d7b8366 1755 } else {
9035a97a
CW		 1756 hotplug_mask = (SDE_CRT_HOTPLUG |
1757 SDE_PORTB_HOTPLUG |
1758 SDE_PORTC_HOTPLUG |
1759 SDE_PORTD_HOTPLUG |
1760 SDE_AUX_MASK);
2d7b8366
YL		 1761 }
1762
1ec14ad3 1763 dev_priv->pch_irq_mask = ~hotplug_mask;
c650156a
ZW		 1764
1765 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1ec14ad3
CW		 1766 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1767 I915_WRITE(SDEIER, hotplug_mask);
3143a2bf 1768 POSTING_READ(SDEIER);
c650156a 1769
7fe0b973
KP		 1770 ironlake_enable_pch_hotplug(dev);
1771
f97108d1
JB		 1772 if (IS_IRONLAKE_M(dev)) {
1773 /* Clear & enable PCU event interrupts */
1774 I915_WRITE(DEIIR, DE_PCU_EVENT);
1775 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1776 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1777 }
1778
036a4a7d
ZW		 1779 return 0;
1780}
1781
f71d4af4 1782static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 1783{
1784 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1785 /* enable kind of interrupts always enabled */
b615b57a
CW		 1786 u32 display_mask =
1787 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
1788 DE_PLANEC_FLIP_DONE_IVB |
1789 DE_PLANEB_FLIP_DONE_IVB |
1790 DE_PLANEA_FLIP_DONE_IVB;
b1f14ad0
JB		 1791 u32 render_irqs;
1792 u32 hotplug_mask;
1793
b1f14ad0
JB		 1794 dev_priv->irq_mask = ~display_mask;
1795
1796 /* should always can generate irq */
1797 I915_WRITE(DEIIR, I915_READ(DEIIR));
1798 I915_WRITE(DEIMR, dev_priv->irq_mask);
b615b57a
CW		 1799 I915_WRITE(DEIER,
1800 display_mask |
1801 DE_PIPEC_VBLANK_IVB |
1802 DE_PIPEB_VBLANK_IVB |
1803 DE_PIPEA_VBLANK_IVB);
b1f14ad0
JB		 1804 POSTING_READ(DEIER);
1805
1806 dev_priv->gt_irq_mask = ~0;
1807
1808 I915_WRITE(GTIIR, I915_READ(GTIIR));
1809 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1810
e2a1e2f0
BW		 1811 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
1812 GEN6_BLITTER_USER_INTERRUPT;
b1f14ad0
JB		 1813 I915_WRITE(GTIER, render_irqs);
1814 POSTING_READ(GTIER);
1815
1816 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1817 SDE_PORTB_HOTPLUG_CPT |
1818 SDE_PORTC_HOTPLUG_CPT |
1819 SDE_PORTD_HOTPLUG_CPT);
1820 dev_priv->pch_irq_mask = ~hotplug_mask;
1821
1822 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1823 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1824 I915_WRITE(SDEIER, hotplug_mask);
1825 POSTING_READ(SDEIER);
1826
7fe0b973
KP		 1827 ironlake_enable_pch_hotplug(dev);
1828
b1f14ad0
JB		 1829 return 0;
1830}
1831
7e231dbe
JB		 1832static int valleyview_irq_postinstall(struct drm_device *dev)
1833{
1834 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1835 u32 render_irqs;
1836 u32 enable_mask;
1837 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1838 u16 msid;
1839
1840 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
1841 enable_mask |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1842 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1843
1844 dev_priv->irq_mask = ~enable_mask;
1845
7e231dbe
JB		 1846 dev_priv->pipestat[0] = 0;
1847 dev_priv->pipestat[1] = 0;
1848
7e231dbe
JB		 1849 /* Hack for broken MSIs on VLV */
1850 pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
1851 pci_read_config_word(dev->pdev, 0x98, &msid);
1852 msid &= 0xff; /* mask out delivery bits */
1853 msid |= (1<<14);
1854 pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
1855
1856 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
1857 I915_WRITE(VLV_IER, enable_mask);
1858 I915_WRITE(VLV_IIR, 0xffffffff);
1859 I915_WRITE(PIPESTAT(0), 0xffff);
1860 I915_WRITE(PIPESTAT(1), 0xffff);
1861 POSTING_READ(VLV_IER);
1862
1863 I915_WRITE(VLV_IIR, 0xffffffff);
1864 I915_WRITE(VLV_IIR, 0xffffffff);
1865
1866 render_irqs = GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
1867 GT_GEN6_BLT_CS_ERROR_INTERRUPT |
e2a1e2f0 1868 GT_GEN6_BLT_USER_INTERRUPT |
7e231dbe
JB		 1869 GT_GEN6_BSD_USER_INTERRUPT |
1870 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
1871 GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
1872 GT_PIPE_NOTIFY |
1873 GT_RENDER_CS_ERROR_INTERRUPT |
1874 GT_SYNC_STATUS |
1875 GT_USER_INTERRUPT;
1876
1877 dev_priv->gt_irq_mask = ~render_irqs;
1878
1879 I915_WRITE(GTIIR, I915_READ(GTIIR));
1880 I915_WRITE(GTIIR, I915_READ(GTIIR));
1881 I915_WRITE(GTIMR, 0);
1882 I915_WRITE(GTIER, render_irqs);
1883 POSTING_READ(GTIER);
1884
1885 /* ack & enable invalid PTE error interrupts */
1886#if 0 /* FIXME: add support to irq handler for checking these bits */
1887 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
1888 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
1889#endif
1890
1891 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1892#if 0 /* FIXME: check register definitions; some have moved */
1893 /* Note HDMI and DP share bits */
1894 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1895 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1896 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1897 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1898 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1899 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1900 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1901 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1902 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1903 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1904 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1905 hotplug_en |= CRT_HOTPLUG_INT_EN;
1906 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1907 }
1908#endif
1909
1910 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1911
1912 return 0;
1913}
1914
7e231dbe
JB		 1915static void valleyview_irq_uninstall(struct drm_device *dev)
1916{
1917 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1918 int pipe;
1919
1920 if (!dev_priv)
1921 return;
1922
7e231dbe
JB		 1923 for_each_pipe(pipe)
1924 I915_WRITE(PIPESTAT(pipe), 0xffff);
1925
1926 I915_WRITE(HWSTAM, 0xffffffff);
1927 I915_WRITE(PORT_HOTPLUG_EN, 0);
1928 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1929 for_each_pipe(pipe)
1930 I915_WRITE(PIPESTAT(pipe), 0xffff);
1931 I915_WRITE(VLV_IIR, 0xffffffff);
1932 I915_WRITE(VLV_IMR, 0xffffffff);
1933 I915_WRITE(VLV_IER, 0x0);
1934 POSTING_READ(VLV_IER);
1935}
1936
f71d4af4 1937static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 1938{
1939 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 1940
1941 if (!dev_priv)
1942 return;
1943
036a4a7d
ZW		 1944 I915_WRITE(HWSTAM, 0xffffffff);
1945
1946 I915_WRITE(DEIMR, 0xffffffff);
1947 I915_WRITE(DEIER, 0x0);
1948 I915_WRITE(DEIIR, I915_READ(DEIIR));
1949
1950 I915_WRITE(GTIMR, 0xffffffff);
1951 I915_WRITE(GTIER, 0x0);
1952 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f
KP		 1953
1954 I915_WRITE(SDEIMR, 0xffffffff);
1955 I915_WRITE(SDEIER, 0x0);
1956 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
036a4a7d
ZW		 1957}
1958
a266c7d5 1959static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 1960{
1961 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 1962 int pipe;
91e3738e 1963
a266c7d5 1964 atomic_set(&dev_priv->irq_received, 0);
5ca58282 1965
9db4a9c7
JB		 1966 for_each_pipe(pipe)
1967 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 1968 I915_WRITE16(IMR, 0xffff);
1969 I915_WRITE16(IER, 0x0);
1970 POSTING_READ16(IER);
c2798b19
CW		 1971}
1972
1973static int i8xx_irq_postinstall(struct drm_device *dev)
1974{
1975 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1976
c2798b19
CW		 1977 dev_priv->pipestat[0] = 0;
1978 dev_priv->pipestat[1] = 0;
1979
1980 I915_WRITE16(EMR,
1981 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
1982
1983 /* Unmask the interrupts that we always want on. */
1984 dev_priv->irq_mask =
1985 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
1986 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
1987 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
1988 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
1989 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1990 I915_WRITE16(IMR, dev_priv->irq_mask);
1991
1992 I915_WRITE16(IER,
1993 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
1994 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
1995 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
1996 I915_USER_INTERRUPT);
1997 POSTING_READ16(IER);
1998
1999 return 0;
2000}
2001
2002static irqreturn_t i8xx_irq_handler(DRM_IRQ_ARGS)
2003{
2004 struct drm_device *dev = (struct drm_device *) arg;
2005 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 2006 u16 iir, new_iir;
2007 u32 pipe_stats[2];
2008 unsigned long irqflags;
2009 int irq_received;
2010 int pipe;
2011 u16 flip_mask =
2012 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2013 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2014
2015 atomic_inc(&dev_priv->irq_received);
2016
2017 iir = I915_READ16(IIR);
2018 if (iir == 0)
2019 return IRQ_NONE;
2020
2021 while (iir & ~flip_mask) {
2022 /* Can't rely on pipestat interrupt bit in iir as it might
2023 * have been cleared after the pipestat interrupt was received.
2024 * It doesn't set the bit in iir again, but it still produces
2025 * interrupts (for non-MSI).
2026 */
2027 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2028 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2029 i915_handle_error(dev, false);
2030
2031 for_each_pipe(pipe) {
2032 int reg = PIPESTAT(pipe);
2033 pipe_stats[pipe] = I915_READ(reg);
2034
2035 /*
2036 * Clear the PIPE*STAT regs before the IIR
2037 */
2038 if (pipe_stats[pipe] & 0x8000ffff) {
2039 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2040 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2041 pipe_name(pipe));
2042 I915_WRITE(reg, pipe_stats[pipe]);
2043 irq_received = 1;
2044 }
2045 }
2046 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2047
2048 I915_WRITE16(IIR, iir & ~flip_mask);
2049 new_iir = I915_READ16(IIR); /* Flush posted writes */
2050
d05c617e 2051 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 2052
2053 if (iir & I915_USER_INTERRUPT)
2054 notify_ring(dev, &dev_priv->ring[RCS]);
2055
2056 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2057 drm_handle_vblank(dev, 0)) {
2058 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2059 intel_prepare_page_flip(dev, 0);
2060 intel_finish_page_flip(dev, 0);
2061 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2062 }
2063 }
2064
2065 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2066 drm_handle_vblank(dev, 1)) {
2067 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2068 intel_prepare_page_flip(dev, 1);
2069 intel_finish_page_flip(dev, 1);
2070 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2071 }
2072 }
2073
2074 iir = new_iir;
2075 }
2076
2077 return IRQ_HANDLED;
2078}
2079
2080static void i8xx_irq_uninstall(struct drm_device * dev)
2081{
2082 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2083 int pipe;
2084
c2798b19
CW		 2085 for_each_pipe(pipe) {
2086 /* Clear enable bits; then clear status bits */
2087 I915_WRITE(PIPESTAT(pipe), 0);
2088 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2089 }
2090 I915_WRITE16(IMR, 0xffff);
2091 I915_WRITE16(IER, 0x0);
2092 I915_WRITE16(IIR, I915_READ16(IIR));
2093}
2094
a266c7d5
CW		 2095static void i915_irq_preinstall(struct drm_device * dev)
2096{
2097 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2098 int pipe;
2099
2100 atomic_set(&dev_priv->irq_received, 0);
2101
2102 if (I915_HAS_HOTPLUG(dev)) {
2103 I915_WRITE(PORT_HOTPLUG_EN, 0);
2104 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2105 }
2106
00d98ebd 2107 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 2108 for_each_pipe(pipe)
2109 I915_WRITE(PIPESTAT(pipe), 0);
2110 I915_WRITE(IMR, 0xffffffff);
2111 I915_WRITE(IER, 0x0);
2112 POSTING_READ(IER);
2113}
2114
2115static int i915_irq_postinstall(struct drm_device *dev)
2116{
2117 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 2118 u32 enable_mask;
a266c7d5 2119
a266c7d5
CW		 2120 dev_priv->pipestat[0] = 0;
2121 dev_priv->pipestat[1] = 0;
2122
38bde180
CW		 2123 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2124
2125 /* Unmask the interrupts that we always want on. */
2126 dev_priv->irq_mask =
2127 ~(I915_ASLE_INTERRUPT |
2128 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2129 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2130 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2131 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2132 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2133
2134 enable_mask =
2135 I915_ASLE_INTERRUPT |
2136 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2137 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2138 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2139 I915_USER_INTERRUPT;
2140
a266c7d5
CW		 2141 if (I915_HAS_HOTPLUG(dev)) {
2142 /* Enable in IER... */
2143 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2144 /* and unmask in IMR */
2145 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2146 }
2147
a266c7d5
CW		 2148 I915_WRITE(IMR, dev_priv->irq_mask);
2149 I915_WRITE(IER, enable_mask);
2150 POSTING_READ(IER);
2151
2152 if (I915_HAS_HOTPLUG(dev)) {
2153 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2154
a266c7d5
CW		 2155 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2156 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2157 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2158 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2159 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2160 hotplug_en |= HDMID_HOTPLUG_INT_EN;
084b612e 2161 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
a266c7d5 2162 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
084b612e 2163 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
a266c7d5
CW		 2164 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2165 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2166 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5
CW		 2167 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2168 }
2169
2170 /* Ignore TV since it's buggy */
2171
2172 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2173 }
2174
2175 intel_opregion_enable_asle(dev);
2176
2177 return 0;
2178}
2179
2180static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
2181{
2182 struct drm_device *dev = (struct drm_device *) arg;
2183 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 2184 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 2185 unsigned long irqflags;
38bde180
CW		 2186 u32 flip_mask =
2187 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2188 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2189 u32 flip[2] = {
2190 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2191 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2192 };
2193 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 2194
2195 atomic_inc(&dev_priv->irq_received);
2196
2197 iir = I915_READ(IIR);
38bde180
CW		 2198 do {
2199 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 2200 bool blc_event = false;
a266c7d5
CW		 2201
2202 /* Can't rely on pipestat interrupt bit in iir as it might
2203 * have been cleared after the pipestat interrupt was received.
2204 * It doesn't set the bit in iir again, but it still produces
2205 * interrupts (for non-MSI).
2206 */
2207 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2208 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2209 i915_handle_error(dev, false);
2210
2211 for_each_pipe(pipe) {
2212 int reg = PIPESTAT(pipe);
2213 pipe_stats[pipe] = I915_READ(reg);
2214
38bde180 2215 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 2216 if (pipe_stats[pipe] & 0x8000ffff) {
2217 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2218 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2219 pipe_name(pipe));
2220 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 2221 irq_received = true;
a266c7d5
CW		 2222 }
2223 }
2224 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2225
2226 if (!irq_received)
2227 break;
2228
a266c7d5
CW		 2229 /* Consume port. Then clear IIR or we'll miss events */
2230 if ((I915_HAS_HOTPLUG(dev)) &&
2231 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2232 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2233
2234 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2235 hotplug_status);
2236 if (hotplug_status & dev_priv->hotplug_supported_mask)
2237 queue_work(dev_priv->wq,
2238 &dev_priv->hotplug_work);
2239
2240 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 2241 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 2242 }
2243
38bde180 2244 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2245 new_iir = I915_READ(IIR); /* Flush posted writes */
2246
a266c7d5
CW		 2247 if (iir & I915_USER_INTERRUPT)
2248 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 2249
a266c7d5 2250 for_each_pipe(pipe) {
38bde180
CW		 2251 int plane = pipe;
2252 if (IS_MOBILE(dev))
2253 plane = !plane;
8291ee90 2254 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2255 drm_handle_vblank(dev, pipe)) {
38bde180
CW		 2256 if (iir & flip[plane]) {
2257 intel_prepare_page_flip(dev, plane);
2258 intel_finish_page_flip(dev, pipe);
2259 flip_mask &= ~flip[plane];
2260 }
a266c7d5
CW		 2261 }
2262
2263 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2264 blc_event = true;
2265 }
2266
a266c7d5
CW		 2267 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2268 intel_opregion_asle_intr(dev);
2269
2270 /* With MSI, interrupts are only generated when iir
2271 * transitions from zero to nonzero. If another bit got
2272 * set while we were handling the existing iir bits, then
2273 * we would never get another interrupt.
2274 *
2275 * This is fine on non-MSI as well, as if we hit this path
2276 * we avoid exiting the interrupt handler only to generate
2277 * another one.
2278 *
2279 * Note that for MSI this could cause a stray interrupt report
2280 * if an interrupt landed in the time between writing IIR and
2281 * the posting read. This should be rare enough to never
2282 * trigger the 99% of 100,000 interrupts test for disabling
2283 * stray interrupts.
2284 */
38bde180 2285 ret = IRQ_HANDLED;
a266c7d5 2286 iir = new_iir;
38bde180 2287 } while (iir & ~flip_mask);
a266c7d5 2288
d05c617e 2289 i915_update_dri1_breadcrumb(dev);
8291ee90 2290
a266c7d5
CW		 2291 return ret;
2292}
2293
2294static void i915_irq_uninstall(struct drm_device * dev)
2295{
2296 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2297 int pipe;
2298
a266c7d5
CW		 2299 if (I915_HAS_HOTPLUG(dev)) {
2300 I915_WRITE(PORT_HOTPLUG_EN, 0);
2301 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2302 }
2303
00d98ebd 2304 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 2305 for_each_pipe(pipe) {
2306 /* Clear enable bits; then clear status bits */
a266c7d5 2307 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 2308 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2309 }
a266c7d5
CW		 2310 I915_WRITE(IMR, 0xffffffff);
2311 I915_WRITE(IER, 0x0);
2312
a266c7d5
CW		 2313 I915_WRITE(IIR, I915_READ(IIR));
2314}
2315
2316static void i965_irq_preinstall(struct drm_device * dev)
2317{
2318 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2319 int pipe;
2320
2321 atomic_set(&dev_priv->irq_received, 0);
2322
adca4730
CW		 2323 I915_WRITE(PORT_HOTPLUG_EN, 0);
2324 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2325
2326 I915_WRITE(HWSTAM, 0xeffe);
2327 for_each_pipe(pipe)
2328 I915_WRITE(PIPESTAT(pipe), 0);
2329 I915_WRITE(IMR, 0xffffffff);
2330 I915_WRITE(IER, 0x0);
2331 POSTING_READ(IER);
2332}
2333
2334static int i965_irq_postinstall(struct drm_device *dev)
2335{
2336 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
adca4730 2337 u32 hotplug_en;
bbba0a97 2338 u32 enable_mask;
a266c7d5
CW		 2339 u32 error_mask;
2340
a266c7d5 2341 /* Unmask the interrupts that we always want on. */
bbba0a97 2342 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 2343 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 2344 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2345 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2346 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2347 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2348 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2349
2350 enable_mask = ~dev_priv->irq_mask;
2351 enable_mask |= I915_USER_INTERRUPT;
2352
2353 if (IS_G4X(dev))
2354 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5
CW		 2355
2356 dev_priv->pipestat[0] = 0;
2357 dev_priv->pipestat[1] = 0;
2358
a266c7d5
CW		 2359 /*
2360 * Enable some error detection, note the instruction error mask
2361 * bit is reserved, so we leave it masked.
2362 */
2363 if (IS_G4X(dev)) {
2364 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2365 GM45_ERROR_MEM_PRIV |
2366 GM45_ERROR_CP_PRIV |
2367 I915_ERROR_MEMORY_REFRESH);
2368 } else {
2369 error_mask = ~(I915_ERROR_PAGE_TABLE |
2370 I915_ERROR_MEMORY_REFRESH);
2371 }
2372 I915_WRITE(EMR, error_mask);
2373
2374 I915_WRITE(IMR, dev_priv->irq_mask);
2375 I915_WRITE(IER, enable_mask);
2376 POSTING_READ(IER);
2377
adca4730
CW		 2378 /* Note HDMI and DP share hotplug bits */
2379 hotplug_en = 0;
2380 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2381 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2382 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2383 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2384 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2385 hotplug_en |= HDMID_HOTPLUG_INT_EN;
084b612e
CW		 2386 if (IS_G4X(dev)) {
2387 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
2388 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2389 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
2390 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2391 } else {
2392 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
2393 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2394 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
2395 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2396 }
adca4730
CW		 2397 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2398 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5 2399
adca4730
CW		 2400 /* Programming the CRT detection parameters tends
2401 to generate a spurious hotplug event about three
2402 seconds later. So just do it once.
2403 */
2404 if (IS_G4X(dev))
2405 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2406 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2407 }
a266c7d5 2408
adca4730 2409 /* Ignore TV since it's buggy */
a266c7d5 2410
adca4730 2411 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
a266c7d5
CW		 2412
2413 intel_opregion_enable_asle(dev);
2414
2415 return 0;
2416}
2417
2418static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS)
2419{
2420 struct drm_device *dev = (struct drm_device *) arg;
2421 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 2422 u32 iir, new_iir;
2423 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 2424 unsigned long irqflags;
2425 int irq_received;
2426 int ret = IRQ_NONE, pipe;
a266c7d5
CW		 2427
2428 atomic_inc(&dev_priv->irq_received);
2429
2430 iir = I915_READ(IIR);
2431
a266c7d5 2432 for (;;) {
2c8ba29f
CW		 2433 bool blc_event = false;
2434
a266c7d5
CW		 2435 irq_received = iir != 0;
2436
2437 /* Can't rely on pipestat interrupt bit in iir as it might
2438 * have been cleared after the pipestat interrupt was received.
2439 * It doesn't set the bit in iir again, but it still produces
2440 * interrupts (for non-MSI).
2441 */
2442 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2443 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2444 i915_handle_error(dev, false);
2445
2446 for_each_pipe(pipe) {
2447 int reg = PIPESTAT(pipe);
2448 pipe_stats[pipe] = I915_READ(reg);
2449
2450 /*
2451 * Clear the PIPE*STAT regs before the IIR
2452 */
2453 if (pipe_stats[pipe] & 0x8000ffff) {
2454 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2455 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2456 pipe_name(pipe));
2457 I915_WRITE(reg, pipe_stats[pipe]);
2458 irq_received = 1;
2459 }
2460 }
2461 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2462
2463 if (!irq_received)
2464 break;
2465
2466 ret = IRQ_HANDLED;
2467
2468 /* Consume port. Then clear IIR or we'll miss events */
adca4730 2469 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
a266c7d5
CW		 2470 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2471
2472 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2473 hotplug_status);
2474 if (hotplug_status & dev_priv->hotplug_supported_mask)
2475 queue_work(dev_priv->wq,
2476 &dev_priv->hotplug_work);
2477
2478 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2479 I915_READ(PORT_HOTPLUG_STAT);
2480 }
2481
2482 I915_WRITE(IIR, iir);
2483 new_iir = I915_READ(IIR); /* Flush posted writes */
2484
a266c7d5
CW		 2485 if (iir & I915_USER_INTERRUPT)
2486 notify_ring(dev, &dev_priv->ring[RCS]);
2487 if (iir & I915_BSD_USER_INTERRUPT)
2488 notify_ring(dev, &dev_priv->ring[VCS]);
2489
4f7d1e79 2490 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
a266c7d5 2491 intel_prepare_page_flip(dev, 0);
a266c7d5 2492
4f7d1e79 2493 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
a266c7d5 2494 intel_prepare_page_flip(dev, 1);
a266c7d5
CW		 2495
2496 for_each_pipe(pipe) {
2c8ba29f 2497 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2498 drm_handle_vblank(dev, pipe)) {
4f7d1e79
CW		 2499 i915_pageflip_stall_check(dev, pipe);
2500 intel_finish_page_flip(dev, pipe);
a266c7d5
CW		 2501 }
2502
2503 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2504 blc_event = true;
2505 }
2506
2507
2508 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2509 intel_opregion_asle_intr(dev);
2510
2511 /* With MSI, interrupts are only generated when iir
2512 * transitions from zero to nonzero. If another bit got
2513 * set while we were handling the existing iir bits, then
2514 * we would never get another interrupt.
2515 *
2516 * This is fine on non-MSI as well, as if we hit this path
2517 * we avoid exiting the interrupt handler only to generate
2518 * another one.
2519 *
2520 * Note that for MSI this could cause a stray interrupt report
2521 * if an interrupt landed in the time between writing IIR and
2522 * the posting read. This should be rare enough to never
2523 * trigger the 99% of 100,000 interrupts test for disabling
2524 * stray interrupts.
2525 */
2526 iir = new_iir;
2527 }
2528
d05c617e 2529 i915_update_dri1_breadcrumb(dev);
2c8ba29f 2530
a266c7d5
CW		 2531 return ret;
2532}
2533
2534static void i965_irq_uninstall(struct drm_device * dev)
2535{
2536 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2537 int pipe;
2538
2539 if (!dev_priv)
2540 return;
2541
adca4730
CW		 2542 I915_WRITE(PORT_HOTPLUG_EN, 0);
2543 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2544
2545 I915_WRITE(HWSTAM, 0xffffffff);
2546 for_each_pipe(pipe)
2547 I915_WRITE(PIPESTAT(pipe), 0);
2548 I915_WRITE(IMR, 0xffffffff);
2549 I915_WRITE(IER, 0x0);
2550
2551 for_each_pipe(pipe)
2552 I915_WRITE(PIPESTAT(pipe),
2553 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2554 I915_WRITE(IIR, I915_READ(IIR));
2555}
2556
f71d4af4
JB		 2557void intel_irq_init(struct drm_device *dev)
2558{
8b2e326d
CW		 2559 struct drm_i915_private *dev_priv = dev->dev_private;
2560
2561 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2562 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
2563 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
2564
f71d4af4
JB		 2565 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2566 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7d4e146f 2567 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 2568 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2569 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2570 }
2571
c3613de9
KP		 2572 if (drm_core_check_feature(dev, DRIVER_MODESET))
2573 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2574 else
2575 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 2576 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2577
7e231dbe
JB		 2578 if (IS_VALLEYVIEW(dev)) {
2579 dev->driver->irq_handler = valleyview_irq_handler;
2580 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2581 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2582 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2583 dev->driver->enable_vblank = valleyview_enable_vblank;
2584 dev->driver->disable_vblank = valleyview_disable_vblank;
2585 } else if (IS_IVYBRIDGE(dev)) {
f71d4af4
JB		 2586 /* Share pre & uninstall handlers with ILK/SNB */
2587 dev->driver->irq_handler = ivybridge_irq_handler;
2588 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2589 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2590 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2591 dev->driver->enable_vblank = ivybridge_enable_vblank;
2592 dev->driver->disable_vblank = ivybridge_disable_vblank;
7d4e146f
ED		 2593 } else if (IS_HASWELL(dev)) {
2594 /* Share interrupts handling with IVB */
2595 dev->driver->irq_handler = ivybridge_irq_handler;
2596 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2597 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2598 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2599 dev->driver->enable_vblank = ivybridge_enable_vblank;
2600 dev->driver->disable_vblank = ivybridge_disable_vblank;
f71d4af4
JB		 2601 } else if (HAS_PCH_SPLIT(dev)) {
2602 dev->driver->irq_handler = ironlake_irq_handler;
2603 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2604 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2605 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2606 dev->driver->enable_vblank = ironlake_enable_vblank;
2607 dev->driver->disable_vblank = ironlake_disable_vblank;
2608 } else {
c2798b19
CW		 2609 if (INTEL_INFO(dev)->gen == 2) {
2610 dev->driver->irq_preinstall = i8xx_irq_preinstall;
2611 dev->driver->irq_postinstall = i8xx_irq_postinstall;
2612 dev->driver->irq_handler = i8xx_irq_handler;
2613 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5 2614 } else if (INTEL_INFO(dev)->gen == 3) {
4f7d1e79
CW		 2615 /* IIR "flip pending" means done if this bit is set */
2616 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
2617
a266c7d5
CW		 2618 dev->driver->irq_preinstall = i915_irq_preinstall;
2619 dev->driver->irq_postinstall = i915_irq_postinstall;
2620 dev->driver->irq_uninstall = i915_irq_uninstall;
2621 dev->driver->irq_handler = i915_irq_handler;
c2798b19 2622 } else {
a266c7d5
CW		 2623 dev->driver->irq_preinstall = i965_irq_preinstall;
2624 dev->driver->irq_postinstall = i965_irq_postinstall;
2625 dev->driver->irq_uninstall = i965_irq_uninstall;
2626 dev->driver->irq_handler = i965_irq_handler;
c2798b19 2627 }
f71d4af4
JB		 2628 dev->driver->enable_vblank = i915_enable_vblank;
2629 dev->driver->disable_vblank = i915_disable_vblank;
2630 }
2631}
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