]> git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/blame - drivers/gpu/drm/i915/i915_irq.c
projects / mirror_ubuntu-eoan-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
UAPI: (Scripted) Convert #include "..." to #include <path/...> in drivers/gpu/
[mirror_ubuntu-eoan-kernel.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/i915_drm.h>
1da177e4 35#include "i915_drv.h"
1c5d22f7 36#include "i915_trace.h"
79e53945 37#include "intel_drv.h"
1da177e4 38
036a4a7d 39/* For display hotplug interrupt */
995b6762 40static void
f2b115e6 41ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 42{
1ec14ad3
CW		 43 if ((dev_priv->irq_mask & mask) != 0) {
44 dev_priv->irq_mask &= ~mask;
45 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 46 POSTING_READ(DEIMR);
036a4a7d
ZW		 47 }
48}
49
50static inline void
f2b115e6 51ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 52{
1ec14ad3
CW		 53 if ((dev_priv->irq_mask & mask) != mask) {
54 dev_priv->irq_mask |= mask;
55 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 56 POSTING_READ(DEIMR);
036a4a7d
ZW		 57 }
58}
59
7c463586
KP		 60void
61i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
62{
63 if ((dev_priv->pipestat[pipe] & mask) != mask) {
9db4a9c7 64 u32 reg = PIPESTAT(pipe);
7c463586
KP		 65
66 dev_priv->pipestat[pipe] |= mask;
67 /* Enable the interrupt, clear any pending status */
68 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
3143a2bf 69 POSTING_READ(reg);
7c463586
KP		 70 }
71}
72
73void
74i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
75{
76 if ((dev_priv->pipestat[pipe] & mask) != 0) {
9db4a9c7 77 u32 reg = PIPESTAT(pipe);
7c463586
KP		 78
79 dev_priv->pipestat[pipe] &= ~mask;
80 I915_WRITE(reg, dev_priv->pipestat[pipe]);
3143a2bf 81 POSTING_READ(reg);
7c463586
KP		 82 }
83}
84
01c66889
ZY		 85/**
86 * intel_enable_asle - enable ASLE interrupt for OpRegion
87 */
1ec14ad3 88void intel_enable_asle(struct drm_device *dev)
01c66889 89{
1ec14ad3
CW		 90 drm_i915_private_t *dev_priv = dev->dev_private;
91 unsigned long irqflags;
92
7e231dbe
JB		 93 /* FIXME: opregion/asle for VLV */
94 if (IS_VALLEYVIEW(dev))
95 return;
96
1ec14ad3 97 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 98
c619eed4 99 if (HAS_PCH_SPLIT(dev))
f2b115e6 100 ironlake_enable_display_irq(dev_priv, DE_GSE);
edcb49ca 101 else {
01c66889 102 i915_enable_pipestat(dev_priv, 1,
d874bcff 103 PIPE_LEGACY_BLC_EVENT_ENABLE);
a6c45cf0 104 if (INTEL_INFO(dev)->gen >= 4)
edcb49ca 105 i915_enable_pipestat(dev_priv, 0,
d874bcff 106 PIPE_LEGACY_BLC_EVENT_ENABLE);
edcb49ca 107 }
1ec14ad3
CW		 108
109 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 110}
111
0a3e67a4
JB		 112/**
113 * i915_pipe_enabled - check if a pipe is enabled
114 * @dev: DRM device
115 * @pipe: pipe to check
116 *
117 * Reading certain registers when the pipe is disabled can hang the chip.
118 * Use this routine to make sure the PLL is running and the pipe is active
119 * before reading such registers if unsure.
120 */
121static int
122i915_pipe_enabled(struct drm_device *dev, int pipe)
123{
124 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
5eddb70b 125 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
0a3e67a4
JB		 126}
127
42f52ef8
KP		 128/* Called from drm generic code, passed a 'crtc', which
129 * we use as a pipe index
130 */
f71d4af4 131static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 132{
133 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
134 unsigned long high_frame;
135 unsigned long low_frame;
5eddb70b 136 u32 high1, high2, low;
0a3e67a4
JB		 137
138 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 139 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 140 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 141 return 0;
142 }
143
9db4a9c7
JB		 144 high_frame = PIPEFRAME(pipe);
145 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 146
0a3e67a4
JB		 147 /*
148 * High & low register fields aren't synchronized, so make sure
149 * we get a low value that's stable across two reads of the high
150 * register.
151 */
152 do {
5eddb70b
CW		 153 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
154 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
155 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 156 } while (high1 != high2);
157
5eddb70b
CW		 158 high1 >>= PIPE_FRAME_HIGH_SHIFT;
159 low >>= PIPE_FRAME_LOW_SHIFT;
160 return (high1 << 8) | low;
0a3e67a4
JB		 161}
162
f71d4af4 163static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 164{
165 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 166 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 167
168 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 169 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 170 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 171 return 0;
172 }
173
174 return I915_READ(reg);
175}
176
f71d4af4 177static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 178 int *vpos, int *hpos)
179{
180 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
181 u32 vbl = 0, position = 0;
182 int vbl_start, vbl_end, htotal, vtotal;
183 bool in_vbl = true;
184 int ret = 0;
185
186 if (!i915_pipe_enabled(dev, pipe)) {
187 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 188 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 189 return 0;
190 }
191
192 /* Get vtotal. */
193 vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
194
195 if (INTEL_INFO(dev)->gen >= 4) {
196 /* No obvious pixelcount register. Only query vertical
197 * scanout position from Display scan line register.
198 */
199 position = I915_READ(PIPEDSL(pipe));
200
201 /* Decode into vertical scanout position. Don't have
202 * horizontal scanout position.
203 */
204 *vpos = position & 0x1fff;
205 *hpos = 0;
206 } else {
207 /* Have access to pixelcount since start of frame.
208 * We can split this into vertical and horizontal
209 * scanout position.
210 */
211 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
212
213 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
214 *vpos = position / htotal;
215 *hpos = position - (*vpos * htotal);
216 }
217
218 /* Query vblank area. */
219 vbl = I915_READ(VBLANK(pipe));
220
221 /* Test position against vblank region. */
222 vbl_start = vbl & 0x1fff;
223 vbl_end = (vbl >> 16) & 0x1fff;
224
225 if ((*vpos < vbl_start) || (*vpos > vbl_end))
226 in_vbl = false;
227
228 /* Inside "upper part" of vblank area? Apply corrective offset: */
229 if (in_vbl && (*vpos >= vbl_start))
230 *vpos = *vpos - vtotal;
231
232 /* Readouts valid? */
233 if (vbl > 0)
234 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
235
236 /* In vblank? */
237 if (in_vbl)
238 ret |= DRM_SCANOUTPOS_INVBL;
239
240 return ret;
241}
242
f71d4af4 243static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 244 int *max_error,
245 struct timeval *vblank_time,
246 unsigned flags)
247{
4041b853
CW		 248 struct drm_i915_private *dev_priv = dev->dev_private;
249 struct drm_crtc *crtc;
0af7e4df 250
4041b853
CW		 251 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
252 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 253 return -EINVAL;
254 }
255
256 /* Get drm_crtc to timestamp: */
4041b853
CW		 257 crtc = intel_get_crtc_for_pipe(dev, pipe);
258 if (crtc == NULL) {
259 DRM_ERROR("Invalid crtc %d\n", pipe);
260 return -EINVAL;
261 }
262
263 if (!crtc->enabled) {
264 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
265 return -EBUSY;
266 }
0af7e4df
MK		 267
268 /* Helper routine in DRM core does all the work: */
4041b853
CW		 269 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
270 vblank_time, flags,
271 crtc);
0af7e4df
MK		 272}
273
5ca58282
JB		 274/*
275 * Handle hotplug events outside the interrupt handler proper.
276 */
277static void i915_hotplug_work_func(struct work_struct *work)
278{
279 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
280 hotplug_work);
281 struct drm_device *dev = dev_priv->dev;
c31c4ba3 282 struct drm_mode_config *mode_config = &dev->mode_config;
4ef69c7a
CW		 283 struct intel_encoder *encoder;
284
a65e34c7 285 mutex_lock(&mode_config->mutex);
e67189ab
JB		 286 DRM_DEBUG_KMS("running encoder hotplug functions\n");
287
4ef69c7a
CW		 288 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
289 if (encoder->hot_plug)
290 encoder->hot_plug(encoder);
291
40ee3381
KP		 292 mutex_unlock(&mode_config->mutex);
293
5ca58282 294 /* Just fire off a uevent and let userspace tell us what to do */
eb1f8e4f 295 drm_helper_hpd_irq_event(dev);
5ca58282
JB		 296}
297
f97108d1
JB		 298static void i915_handle_rps_change(struct drm_device *dev)
299{
300 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 301 u32 busy_up, busy_down, max_avg, min_avg;
f97108d1
JB		 302 u8 new_delay = dev_priv->cur_delay;
303
7648fa99 304 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 305 busy_up = I915_READ(RCPREVBSYTUPAVG);
306 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 307 max_avg = I915_READ(RCBMAXAVG);
308 min_avg = I915_READ(RCBMINAVG);
309
310 /* Handle RCS change request from hw */
b5b72e89 311 if (busy_up > max_avg) {
f97108d1
JB		 312 if (dev_priv->cur_delay != dev_priv->max_delay)
313 new_delay = dev_priv->cur_delay - 1;
314 if (new_delay < dev_priv->max_delay)
315 new_delay = dev_priv->max_delay;
b5b72e89 316 } else if (busy_down < min_avg) {
f97108d1
JB		 317 if (dev_priv->cur_delay != dev_priv->min_delay)
318 new_delay = dev_priv->cur_delay + 1;
319 if (new_delay > dev_priv->min_delay)
320 new_delay = dev_priv->min_delay;
321 }
322
7648fa99
JB		 323 if (ironlake_set_drps(dev, new_delay))
324 dev_priv->cur_delay = new_delay;
f97108d1
JB		 325
326 return;
327}
328
549f7365
CW		 329static void notify_ring(struct drm_device *dev,
330 struct intel_ring_buffer *ring)
331{
332 struct drm_i915_private *dev_priv = dev->dev_private;
9862e600 333
475553de
CW		 334 if (ring->obj == NULL)
335 return;
336
6d171cb4 337 trace_i915_gem_request_complete(ring, ring->get_seqno(ring));
9862e600 338
549f7365 339 wake_up_all(&ring->irq_queue);
3e0dc6b0
BW		 340 if (i915_enable_hangcheck) {
341 dev_priv->hangcheck_count = 0;
342 mod_timer(&dev_priv->hangcheck_timer,
343 jiffies +
344 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
345 }
549f7365
CW		 346}
347
4912d041 348static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 349{
4912d041
BW		 350 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
351 rps_work);
4912d041 352 u32 pm_iir, pm_imr;
7b9e0ae6 353 u8 new_delay;
4912d041
BW		 354
355 spin_lock_irq(&dev_priv->rps_lock);
356 pm_iir = dev_priv->pm_iir;
357 dev_priv->pm_iir = 0;
358 pm_imr = I915_READ(GEN6_PMIMR);
a9e2641d 359 I915_WRITE(GEN6_PMIMR, 0);
4912d041 360 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91 361
7b9e0ae6 362 if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
3b8d8d91
JB		 363 return;
364
4912d041 365 mutex_lock(&dev_priv->dev->struct_mutex);
7b9e0ae6
CW		 366
367 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
368 new_delay = dev_priv->cur_delay + 1;
369 else
370 new_delay = dev_priv->cur_delay - 1;
3b8d8d91 371
4912d041 372 gen6_set_rps(dev_priv->dev, new_delay);
3b8d8d91 373
4912d041 374 mutex_unlock(&dev_priv->dev->struct_mutex);
3b8d8d91
JB		 375}
376
e3689190
BW		 377
378/**
379 * ivybridge_parity_work - Workqueue called when a parity error interrupt
380 * occurred.
381 * @work: workqueue struct
382 *
383 * Doesn't actually do anything except notify userspace. As a consequence of
384 * this event, userspace should try to remap the bad rows since statistically
385 * it is likely the same row is more likely to go bad again.
386 */
387static void ivybridge_parity_work(struct work_struct *work)
388{
389 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
390 parity_error_work);
391 u32 error_status, row, bank, subbank;
392 char *parity_event[5];
393 uint32_t misccpctl;
394 unsigned long flags;
395
396 /* We must turn off DOP level clock gating to access the L3 registers.
397 * In order to prevent a get/put style interface, acquire struct mutex
398 * any time we access those registers.
399 */
400 mutex_lock(&dev_priv->dev->struct_mutex);
401
402 misccpctl = I915_READ(GEN7_MISCCPCTL);
403 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
404 POSTING_READ(GEN7_MISCCPCTL);
405
406 error_status = I915_READ(GEN7_L3CDERRST1);
407 row = GEN7_PARITY_ERROR_ROW(error_status);
408 bank = GEN7_PARITY_ERROR_BANK(error_status);
409 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
410
411 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
412 GEN7_L3CDERRST1_ENABLE);
413 POSTING_READ(GEN7_L3CDERRST1);
414
415 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
416
417 spin_lock_irqsave(&dev_priv->irq_lock, flags);
418 dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
419 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
420 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
421
422 mutex_unlock(&dev_priv->dev->struct_mutex);
423
424 parity_event[0] = "L3_PARITY_ERROR=1";
425 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
426 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
427 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
428 parity_event[4] = NULL;
429
430 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
431 KOBJ_CHANGE, parity_event);
432
433 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
434 row, bank, subbank);
435
436 kfree(parity_event[3]);
437 kfree(parity_event[2]);
438 kfree(parity_event[1]);
439}
440
d2ba8470 441static void ivybridge_handle_parity_error(struct drm_device *dev)
e3689190
BW		 442{
443 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
444 unsigned long flags;
445
446 if (!IS_IVYBRIDGE(dev))
447 return;
448
449 spin_lock_irqsave(&dev_priv->irq_lock, flags);
450 dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
451 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
452 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
453
454 queue_work(dev_priv->wq, &dev_priv->parity_error_work);
455}
456
e7b4c6b1
DV		 457static void snb_gt_irq_handler(struct drm_device *dev,
458 struct drm_i915_private *dev_priv,
459 u32 gt_iir)
460{
461
462 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
463 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
464 notify_ring(dev, &dev_priv->ring[RCS]);
465 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
466 notify_ring(dev, &dev_priv->ring[VCS]);
467 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
468 notify_ring(dev, &dev_priv->ring[BCS]);
469
470 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
471 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
472 GT_RENDER_CS_ERROR_INTERRUPT)) {
473 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
474 i915_handle_error(dev, false);
475 }
e3689190
BW		 476
477 if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
478 ivybridge_handle_parity_error(dev);
e7b4c6b1
DV		 479}
480
fc6826d1
CW		 481static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
482 u32 pm_iir)
483{
484 unsigned long flags;
485
486 /*
487 * IIR bits should never already be set because IMR should
488 * prevent an interrupt from being shown in IIR. The warning
489 * displays a case where we've unsafely cleared
490 * dev_priv->pm_iir. Although missing an interrupt of the same
491 * type is not a problem, it displays a problem in the logic.
492 *
493 * The mask bit in IMR is cleared by rps_work.
494 */
495
496 spin_lock_irqsave(&dev_priv->rps_lock, flags);
fc6826d1
CW		 497 dev_priv->pm_iir |= pm_iir;
498 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
499 POSTING_READ(GEN6_PMIMR);
500 spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
501
502 queue_work(dev_priv->wq, &dev_priv->rps_work);
503}
504
7e231dbe
JB		 505static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
506{
507 struct drm_device *dev = (struct drm_device *) arg;
508 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
509 u32 iir, gt_iir, pm_iir;
510 irqreturn_t ret = IRQ_NONE;
511 unsigned long irqflags;
512 int pipe;
513 u32 pipe_stats[I915_MAX_PIPES];
7e231dbe
JB		 514 bool blc_event;
515
516 atomic_inc(&dev_priv->irq_received);
517
7e231dbe
JB		 518 while (true) {
519 iir = I915_READ(VLV_IIR);
520 gt_iir = I915_READ(GTIIR);
521 pm_iir = I915_READ(GEN6_PMIIR);
522
523 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
524 goto out;
525
526 ret = IRQ_HANDLED;
527
e7b4c6b1 528 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 529
530 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
531 for_each_pipe(pipe) {
532 int reg = PIPESTAT(pipe);
533 pipe_stats[pipe] = I915_READ(reg);
534
535 /*
536 * Clear the PIPE*STAT regs before the IIR
537 */
538 if (pipe_stats[pipe] & 0x8000ffff) {
539 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
540 DRM_DEBUG_DRIVER("pipe %c underrun\n",
541 pipe_name(pipe));
542 I915_WRITE(reg, pipe_stats[pipe]);
543 }
544 }
545 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
546
31acc7f5
JB		 547 for_each_pipe(pipe) {
548 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
549 drm_handle_vblank(dev, pipe);
550
551 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
552 intel_prepare_page_flip(dev, pipe);
553 intel_finish_page_flip(dev, pipe);
554 }
555 }
556
7e231dbe
JB		 557 /* Consume port. Then clear IIR or we'll miss events */
558 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
559 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
560
561 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
562 hotplug_status);
563 if (hotplug_status & dev_priv->hotplug_supported_mask)
564 queue_work(dev_priv->wq,
565 &dev_priv->hotplug_work);
566
567 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
568 I915_READ(PORT_HOTPLUG_STAT);
569 }
570
7e231dbe
JB		 571 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
572 blc_event = true;
573
fc6826d1
CW		 574 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
575 gen6_queue_rps_work(dev_priv, pm_iir);
7e231dbe
JB		 576
577 I915_WRITE(GTIIR, gt_iir);
578 I915_WRITE(GEN6_PMIIR, pm_iir);
579 I915_WRITE(VLV_IIR, iir);
580 }
581
582out:
583 return ret;
584}
585
23e81d69 586static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 587{
588 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 589 int pipe;
776ad806 590
776ad806
JB		 591 if (pch_iir & SDE_AUDIO_POWER_MASK)
592 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
593 (pch_iir & SDE_AUDIO_POWER_MASK) >>
594 SDE_AUDIO_POWER_SHIFT);
595
596 if (pch_iir & SDE_GMBUS)
597 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
598
599 if (pch_iir & SDE_AUDIO_HDCP_MASK)
600 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
601
602 if (pch_iir & SDE_AUDIO_TRANS_MASK)
603 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
604
605 if (pch_iir & SDE_POISON)
606 DRM_ERROR("PCH poison interrupt\n");
607
9db4a9c7
JB		 608 if (pch_iir & SDE_FDI_MASK)
609 for_each_pipe(pipe)
610 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
611 pipe_name(pipe),
612 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 613
614 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
615 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
616
617 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
618 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
619
620 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
621 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
622 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
623 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
624}
625
23e81d69
AJ		 626static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
627{
628 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
629 int pipe;
630
631 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
632 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
633 (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
634 SDE_AUDIO_POWER_SHIFT_CPT);
635
636 if (pch_iir & SDE_AUX_MASK_CPT)
637 DRM_DEBUG_DRIVER("AUX channel interrupt\n");
638
639 if (pch_iir & SDE_GMBUS_CPT)
640 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
641
642 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
643 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
644
645 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
646 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
647
648 if (pch_iir & SDE_FDI_MASK_CPT)
649 for_each_pipe(pipe)
650 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
651 pipe_name(pipe),
652 I915_READ(FDI_RX_IIR(pipe)));
653}
654
f71d4af4 655static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
b1f14ad0
JB		 656{
657 struct drm_device *dev = (struct drm_device *) arg;
658 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
0e43406b
CW		 659 u32 de_iir, gt_iir, de_ier, pm_iir;
660 irqreturn_t ret = IRQ_NONE;
661 int i;
b1f14ad0
JB		 662
663 atomic_inc(&dev_priv->irq_received);
664
665 /* disable master interrupt before clearing iir */
666 de_ier = I915_READ(DEIER);
667 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
b1f14ad0 668
b1f14ad0 669 gt_iir = I915_READ(GTIIR);
0e43406b
CW		 670 if (gt_iir) {
671 snb_gt_irq_handler(dev, dev_priv, gt_iir);
672 I915_WRITE(GTIIR, gt_iir);
673 ret = IRQ_HANDLED;
b1f14ad0
JB		 674 }
675
0e43406b
CW		 676 de_iir = I915_READ(DEIIR);
677 if (de_iir) {
678 if (de_iir & DE_GSE_IVB)
679 intel_opregion_gse_intr(dev);
680
681 for (i = 0; i < 3; i++) {
682 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
683 intel_prepare_page_flip(dev, i);
684 intel_finish_page_flip_plane(dev, i);
685 }
686 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
687 drm_handle_vblank(dev, i);
688 }
b615b57a 689
0e43406b
CW		 690 /* check event from PCH */
691 if (de_iir & DE_PCH_EVENT_IVB) {
692 u32 pch_iir = I915_READ(SDEIIR);
b1f14ad0 693
0e43406b
CW		 694 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
695 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
23e81d69 696 cpt_irq_handler(dev, pch_iir);
b1f14ad0 697
0e43406b
CW		 698 /* clear PCH hotplug event before clear CPU irq */
699 I915_WRITE(SDEIIR, pch_iir);
700 }
b615b57a 701
0e43406b
CW		 702 I915_WRITE(DEIIR, de_iir);
703 ret = IRQ_HANDLED;
b1f14ad0
JB		 704 }
705
0e43406b
CW		 706 pm_iir = I915_READ(GEN6_PMIIR);
707 if (pm_iir) {
708 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
709 gen6_queue_rps_work(dev_priv, pm_iir);
710 I915_WRITE(GEN6_PMIIR, pm_iir);
711 ret = IRQ_HANDLED;
712 }
b1f14ad0 713
b1f14ad0
JB		 714 I915_WRITE(DEIER, de_ier);
715 POSTING_READ(DEIER);
716
717 return ret;
718}
719
e7b4c6b1
DV		 720static void ilk_gt_irq_handler(struct drm_device *dev,
721 struct drm_i915_private *dev_priv,
722 u32 gt_iir)
723{
724 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
725 notify_ring(dev, &dev_priv->ring[RCS]);
726 if (gt_iir & GT_BSD_USER_INTERRUPT)
727 notify_ring(dev, &dev_priv->ring[VCS]);
728}
729
f71d4af4 730static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
036a4a7d 731{
4697995b 732 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 733 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
734 int ret = IRQ_NONE;
3b8d8d91 735 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
2d7b8366 736 u32 hotplug_mask;
881f47b6 737
4697995b
JB		 738 atomic_inc(&dev_priv->irq_received);
739
2d109a84
ZN		 740 /* disable master interrupt before clearing iir */
741 de_ier = I915_READ(DEIER);
742 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 743 POSTING_READ(DEIER);
2d109a84 744
036a4a7d
ZW		 745 de_iir = I915_READ(DEIIR);
746 gt_iir = I915_READ(GTIIR);
c650156a 747 pch_iir = I915_READ(SDEIIR);
3b8d8d91 748 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 749
3b8d8d91
JB		 750 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
751 (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 752 goto done;
036a4a7d 753
2d7b8366
YL		 754 if (HAS_PCH_CPT(dev))
755 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
756 else
757 hotplug_mask = SDE_HOTPLUG_MASK;
758
c7c85101 759 ret = IRQ_HANDLED;
036a4a7d 760
e7b4c6b1
DV		 761 if (IS_GEN5(dev))
762 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
763 else
764 snb_gt_irq_handler(dev, dev_priv, gt_iir);
01c66889 765
c7c85101 766 if (de_iir & DE_GSE)
3b617967 767 intel_opregion_gse_intr(dev);
c650156a 768
f072d2e7 769 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 770 intel_prepare_page_flip(dev, 0);
2bbda389 771 intel_finish_page_flip_plane(dev, 0);
f072d2e7 772 }
013d5aa2 773
f072d2e7 774 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 775 intel_prepare_page_flip(dev, 1);
2bbda389 776 intel_finish_page_flip_plane(dev, 1);
f072d2e7 777 }
013d5aa2 778
f072d2e7 779 if (de_iir & DE_PIPEA_VBLANK)
c062df61
LP		 780 drm_handle_vblank(dev, 0);
781
f072d2e7 782 if (de_iir & DE_PIPEB_VBLANK)
c062df61
LP		 783 drm_handle_vblank(dev, 1);
784
c7c85101 785 /* check event from PCH */
776ad806
JB		 786 if (de_iir & DE_PCH_EVENT) {
787 if (pch_iir & hotplug_mask)
788 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
23e81d69
AJ		 789 if (HAS_PCH_CPT(dev))
790 cpt_irq_handler(dev, pch_iir);
791 else
792 ibx_irq_handler(dev, pch_iir);
776ad806 793 }
036a4a7d 794
f97108d1 795 if (de_iir & DE_PCU_EVENT) {
7648fa99 796 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
f97108d1
JB		 797 i915_handle_rps_change(dev);
798 }
799
fc6826d1
CW		 800 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
801 gen6_queue_rps_work(dev_priv, pm_iir);
3b8d8d91 802
c7c85101
ZN		 803 /* should clear PCH hotplug event before clear CPU irq */
804 I915_WRITE(SDEIIR, pch_iir);
805 I915_WRITE(GTIIR, gt_iir);
806 I915_WRITE(DEIIR, de_iir);
4912d041 807 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 808
809done:
2d109a84 810 I915_WRITE(DEIER, de_ier);
3143a2bf 811 POSTING_READ(DEIER);
2d109a84 812
036a4a7d
ZW		 813 return ret;
814}
815
8a905236
JB		 816/**
817 * i915_error_work_func - do process context error handling work
818 * @work: work struct
819 *
820 * Fire an error uevent so userspace can see that a hang or error
821 * was detected.
822 */
823static void i915_error_work_func(struct work_struct *work)
824{
825 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
826 error_work);
827 struct drm_device *dev = dev_priv->dev;
f316a42c
BG		 828 char *error_event[] = { "ERROR=1", NULL };
829 char *reset_event[] = { "RESET=1", NULL };
830 char *reset_done_event[] = { "ERROR=0", NULL };
8a905236 831
f316a42c
BG		 832 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
833
ba1234d1 834 if (atomic_read(&dev_priv->mm.wedged)) {
f803aa55
CW		 835 DRM_DEBUG_DRIVER("resetting chip\n");
836 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
d4b8bb2a 837 if (!i915_reset(dev)) {
f803aa55
CW		 838 atomic_set(&dev_priv->mm.wedged, 0);
839 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
f316a42c 840 }
30dbf0c0 841 complete_all(&dev_priv->error_completion);
f316a42c 842 }
8a905236
JB		 843}
844
3bd3c932 845#ifdef CONFIG_DEBUG_FS
9df30794 846static struct drm_i915_error_object *
bcfb2e28 847i915_error_object_create(struct drm_i915_private *dev_priv,
05394f39 848 struct drm_i915_gem_object *src)
9df30794
CW		 849{
850 struct drm_i915_error_object *dst;
9df30794 851 int page, page_count;
e56660dd 852 u32 reloc_offset;
9df30794 853
05394f39 854 if (src == NULL || src->pages == NULL)
9df30794
CW		 855 return NULL;
856
05394f39 857 page_count = src->base.size / PAGE_SIZE;
9df30794 858
0206e353 859 dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
9df30794
CW		 860 if (dst == NULL)
861 return NULL;
862
05394f39 863 reloc_offset = src->gtt_offset;
9df30794 864 for (page = 0; page < page_count; page++) {
788885ae 865 unsigned long flags;
e56660dd 866 void *d;
788885ae 867
e56660dd 868 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 869 if (d == NULL)
870 goto unwind;
e56660dd 871
788885ae 872 local_irq_save(flags);
74898d7e
DV		 873 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
874 src->has_global_gtt_mapping) {
172975aa
CW		 875 void __iomem *s;
876
877 /* Simply ignore tiling or any overlapping fence.
878 * It's part of the error state, and this hopefully
879 * captures what the GPU read.
880 */
881
882 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
883 reloc_offset);
884 memcpy_fromio(d, s, PAGE_SIZE);
885 io_mapping_unmap_atomic(s);
886 } else {
887 void *s;
888
889 drm_clflush_pages(&src->pages[page], 1);
890
891 s = kmap_atomic(src->pages[page]);
892 memcpy(d, s, PAGE_SIZE);
893 kunmap_atomic(s);
894
895 drm_clflush_pages(&src->pages[page], 1);
896 }
788885ae 897 local_irq_restore(flags);
e56660dd 898
9df30794 899 dst->pages[page] = d;
e56660dd
CW		 900
901 reloc_offset += PAGE_SIZE;
9df30794
CW		 902 }
903 dst->page_count = page_count;
05394f39 904 dst->gtt_offset = src->gtt_offset;
9df30794
CW		 905
906 return dst;
907
908unwind:
909 while (page--)
910 kfree(dst->pages[page]);
911 kfree(dst);
912 return NULL;
913}
914
915static void
916i915_error_object_free(struct drm_i915_error_object *obj)
917{
918 int page;
919
920 if (obj == NULL)
921 return;
922
923 for (page = 0; page < obj->page_count; page++)
924 kfree(obj->pages[page]);
925
926 kfree(obj);
927}
928
742cbee8
DV		 929void
930i915_error_state_free(struct kref *error_ref)
9df30794 931{
742cbee8
DV		 932 struct drm_i915_error_state *error = container_of(error_ref,
933 typeof(*error), ref);
e2f973d5
CW		 934 int i;
935
52d39a21
CW		 936 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
937 i915_error_object_free(error->ring[i].batchbuffer);
938 i915_error_object_free(error->ring[i].ringbuffer);
939 kfree(error->ring[i].requests);
940 }
e2f973d5 941
9df30794 942 kfree(error->active_bo);
6ef3d427 943 kfree(error->overlay);
9df30794
CW		 944 kfree(error);
945}
1b50247a
CW		 946static void capture_bo(struct drm_i915_error_buffer *err,
947 struct drm_i915_gem_object *obj)
948{
949 err->size = obj->base.size;
950 err->name = obj->base.name;
951 err->seqno = obj->last_rendering_seqno;
952 err->gtt_offset = obj->gtt_offset;
953 err->read_domains = obj->base.read_domains;
954 err->write_domain = obj->base.write_domain;
955 err->fence_reg = obj->fence_reg;
956 err->pinned = 0;
957 if (obj->pin_count > 0)
958 err->pinned = 1;
959 if (obj->user_pin_count > 0)
960 err->pinned = -1;
961 err->tiling = obj->tiling_mode;
962 err->dirty = obj->dirty;
963 err->purgeable = obj->madv != I915_MADV_WILLNEED;
964 err->ring = obj->ring ? obj->ring->id : -1;
965 err->cache_level = obj->cache_level;
966}
9df30794 967
1b50247a
CW		 968static u32 capture_active_bo(struct drm_i915_error_buffer *err,
969 int count, struct list_head *head)
c724e8a9
CW		 970{
971 struct drm_i915_gem_object *obj;
972 int i = 0;
973
974 list_for_each_entry(obj, head, mm_list) {
1b50247a 975 capture_bo(err++, obj);
c724e8a9
CW		 976 if (++i == count)
977 break;
1b50247a
CW		 978 }
979
980 return i;
981}
982
983static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
984 int count, struct list_head *head)
985{
986 struct drm_i915_gem_object *obj;
987 int i = 0;
988
989 list_for_each_entry(obj, head, gtt_list) {
990 if (obj->pin_count == 0)
991 continue;
c724e8a9 992
1b50247a
CW		 993 capture_bo(err++, obj);
994 if (++i == count)
995 break;
c724e8a9
CW		 996 }
997
998 return i;
999}
1000
748ebc60
CW		 1001static void i915_gem_record_fences(struct drm_device *dev,
1002 struct drm_i915_error_state *error)
1003{
1004 struct drm_i915_private *dev_priv = dev->dev_private;
1005 int i;
1006
1007 /* Fences */
1008 switch (INTEL_INFO(dev)->gen) {
775d17b6 1009 case 7:
748ebc60
CW		 1010 case 6:
1011 for (i = 0; i < 16; i++)
1012 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1013 break;
1014 case 5:
1015 case 4:
1016 for (i = 0; i < 16; i++)
1017 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1018 break;
1019 case 3:
1020 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1021 for (i = 0; i < 8; i++)
1022 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1023 case 2:
1024 for (i = 0; i < 8; i++)
1025 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1026 break;
1027
1028 }
1029}
1030
bcfb2e28
CW		 1031static struct drm_i915_error_object *
1032i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1033 struct intel_ring_buffer *ring)
1034{
1035 struct drm_i915_gem_object *obj;
1036 u32 seqno;
1037
1038 if (!ring->get_seqno)
1039 return NULL;
1040
1041 seqno = ring->get_seqno(ring);
1042 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1043 if (obj->ring != ring)
1044 continue;
1045
c37d9a5d 1046 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
bcfb2e28
CW		 1047 continue;
1048
1049 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1050 continue;
1051
1052 /* We need to copy these to an anonymous buffer as the simplest
1053 * method to avoid being overwritten by userspace.
1054 */
1055 return i915_error_object_create(dev_priv, obj);
1056 }
1057
1058 return NULL;
1059}
1060
d27b1e0e
DV		 1061static void i915_record_ring_state(struct drm_device *dev,
1062 struct drm_i915_error_state *error,
1063 struct intel_ring_buffer *ring)
1064{
1065 struct drm_i915_private *dev_priv = dev->dev_private;
1066
33f3f518 1067 if (INTEL_INFO(dev)->gen >= 6) {
12f55818 1068 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
33f3f518 1069 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
7e3b8737
DV		 1070 error->semaphore_mboxes[ring->id][0]
1071 = I915_READ(RING_SYNC_0(ring->mmio_base));
1072 error->semaphore_mboxes[ring->id][1]
1073 = I915_READ(RING_SYNC_1(ring->mmio_base));
33f3f518 1074 }
c1cd90ed 1075
d27b1e0e 1076 if (INTEL_INFO(dev)->gen >= 4) {
9d2f41fa 1077 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
d27b1e0e
DV		 1078 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1079 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1080 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
c1cd90ed 1081 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
d27b1e0e 1082 if (ring->id == RCS) {
d27b1e0e
DV		 1083 error->instdone1 = I915_READ(INSTDONE1);
1084 error->bbaddr = I915_READ64(BB_ADDR);
1085 }
1086 } else {
9d2f41fa 1087 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
d27b1e0e
DV		 1088 error->ipeir[ring->id] = I915_READ(IPEIR);
1089 error->ipehr[ring->id] = I915_READ(IPEHR);
1090 error->instdone[ring->id] = I915_READ(INSTDONE);
d27b1e0e
DV		 1091 }
1092
9574b3fe 1093 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
c1cd90ed 1094 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
d27b1e0e
DV		 1095 error->seqno[ring->id] = ring->get_seqno(ring);
1096 error->acthd[ring->id] = intel_ring_get_active_head(ring);
c1cd90ed
DV		 1097 error->head[ring->id] = I915_READ_HEAD(ring);
1098 error->tail[ring->id] = I915_READ_TAIL(ring);
7e3b8737
DV		 1099
1100 error->cpu_ring_head[ring->id] = ring->head;
1101 error->cpu_ring_tail[ring->id] = ring->tail;
d27b1e0e
DV		 1102}
1103
52d39a21
CW		 1104static void i915_gem_record_rings(struct drm_device *dev,
1105 struct drm_i915_error_state *error)
1106{
1107 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 1108 struct intel_ring_buffer *ring;
52d39a21
CW		 1109 struct drm_i915_gem_request *request;
1110 int i, count;
1111
b4519513 1112 for_each_ring(ring, dev_priv, i) {
52d39a21
CW		 1113 i915_record_ring_state(dev, error, ring);
1114
1115 error->ring[i].batchbuffer =
1116 i915_error_first_batchbuffer(dev_priv, ring);
1117
1118 error->ring[i].ringbuffer =
1119 i915_error_object_create(dev_priv, ring->obj);
1120
1121 count = 0;
1122 list_for_each_entry(request, &ring->request_list, list)
1123 count++;
1124
1125 error->ring[i].num_requests = count;
1126 error->ring[i].requests =
1127 kmalloc(count*sizeof(struct drm_i915_error_request),
1128 GFP_ATOMIC);
1129 if (error->ring[i].requests == NULL) {
1130 error->ring[i].num_requests = 0;
1131 continue;
1132 }
1133
1134 count = 0;
1135 list_for_each_entry(request, &ring->request_list, list) {
1136 struct drm_i915_error_request *erq;
1137
1138 erq = &error->ring[i].requests[count++];
1139 erq->seqno = request->seqno;
1140 erq->jiffies = request->emitted_jiffies;
ee4f42b1 1141 erq->tail = request->tail;
52d39a21
CW		 1142 }
1143 }
1144}
1145
8a905236
JB		 1146/**
1147 * i915_capture_error_state - capture an error record for later analysis
1148 * @dev: drm device
1149 *
1150 * Should be called when an error is detected (either a hang or an error
1151 * interrupt) to capture error state from the time of the error. Fills
1152 * out a structure which becomes available in debugfs for user level tools
1153 * to pick up.
1154 */
63eeaf38
JB		 1155static void i915_capture_error_state(struct drm_device *dev)
1156{
1157 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1158 struct drm_i915_gem_object *obj;
63eeaf38
JB		 1159 struct drm_i915_error_state *error;
1160 unsigned long flags;
9db4a9c7 1161 int i, pipe;
63eeaf38
JB		 1162
1163 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1164 error = dev_priv->first_error;
1165 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1166 if (error)
1167 return;
63eeaf38 1168
9db4a9c7 1169 /* Account for pipe specific data like PIPE*STAT */
33f3f518 1170 error = kzalloc(sizeof(*error), GFP_ATOMIC);
63eeaf38 1171 if (!error) {
9df30794
CW		 1172 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1173 return;
63eeaf38
JB		 1174 }
1175
b6f7833b
CW		 1176 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1177 dev->primary->index);
2fa772f3 1178
742cbee8 1179 kref_init(&error->ref);
63eeaf38
JB		 1180 error->eir = I915_READ(EIR);
1181 error->pgtbl_er = I915_READ(PGTBL_ER);
b9a3906b 1182 error->ccid = I915_READ(CCID);
be998e2e
BW		 1183
1184 if (HAS_PCH_SPLIT(dev))
1185 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1186 else if (IS_VALLEYVIEW(dev))
1187 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1188 else if (IS_GEN2(dev))
1189 error->ier = I915_READ16(IER);
1190 else
1191 error->ier = I915_READ(IER);
1192
9db4a9c7
JB		 1193 for_each_pipe(pipe)
1194 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
d27b1e0e 1195
33f3f518 1196 if (INTEL_INFO(dev)->gen >= 6) {
f406839f 1197 error->error = I915_READ(ERROR_GEN6);
33f3f518
DV		 1198 error->done_reg = I915_READ(DONE_REG);
1199 }
d27b1e0e 1200
748ebc60 1201 i915_gem_record_fences(dev, error);
52d39a21 1202 i915_gem_record_rings(dev, error);
9df30794 1203
c724e8a9 1204 /* Record buffers on the active and pinned lists. */
9df30794 1205 error->active_bo = NULL;
c724e8a9 1206 error->pinned_bo = NULL;
9df30794 1207
bcfb2e28
CW		 1208 i = 0;
1209 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1210 i++;
1211 error->active_bo_count = i;
1b50247a
CW		 1212 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
1213 if (obj->pin_count)
1214 i++;
bcfb2e28 1215 error->pinned_bo_count = i - error->active_bo_count;
c724e8a9 1216
8e934dbf
CW		 1217 error->active_bo = NULL;
1218 error->pinned_bo = NULL;
bcfb2e28
CW		 1219 if (i) {
1220 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
9df30794 1221 GFP_ATOMIC);
c724e8a9
CW		 1222 if (error->active_bo)
1223 error->pinned_bo =
1224 error->active_bo + error->active_bo_count;
9df30794
CW		 1225 }
1226
c724e8a9
CW		 1227 if (error->active_bo)
1228 error->active_bo_count =
1b50247a
CW		 1229 capture_active_bo(error->active_bo,
1230 error->active_bo_count,
1231 &dev_priv->mm.active_list);
c724e8a9
CW		 1232
1233 if (error->pinned_bo)
1234 error->pinned_bo_count =
1b50247a
CW		 1235 capture_pinned_bo(error->pinned_bo,
1236 error->pinned_bo_count,
1237 &dev_priv->mm.gtt_list);
c724e8a9 1238
9df30794
CW		 1239 do_gettimeofday(&error->time);
1240
6ef3d427 1241 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 1242 error->display = intel_display_capture_error_state(dev);
6ef3d427 1243
9df30794
CW		 1244 spin_lock_irqsave(&dev_priv->error_lock, flags);
1245 if (dev_priv->first_error == NULL) {
1246 dev_priv->first_error = error;
1247 error = NULL;
1248 }
63eeaf38 1249 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1250
1251 if (error)
742cbee8 1252 i915_error_state_free(&error->ref);
9df30794
CW		 1253}
1254
1255void i915_destroy_error_state(struct drm_device *dev)
1256{
1257 struct drm_i915_private *dev_priv = dev->dev_private;
1258 struct drm_i915_error_state *error;
6dc0e816 1259 unsigned long flags;
9df30794 1260
6dc0e816 1261 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1262 error = dev_priv->first_error;
1263 dev_priv->first_error = NULL;
6dc0e816 1264 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1265
1266 if (error)
742cbee8 1267 kref_put(&error->ref, i915_error_state_free);
63eeaf38 1268}
3bd3c932
CW		 1269#else
1270#define i915_capture_error_state(x)
1271#endif
63eeaf38 1272
35aed2e6 1273static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1274{
1275 struct drm_i915_private *dev_priv = dev->dev_private;
1276 u32 eir = I915_READ(EIR);
9db4a9c7 1277 int pipe;
8a905236 1278
35aed2e6
CW		 1279 if (!eir)
1280 return;
8a905236 1281
a70491cc 1282 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236
JB		 1283
1284 if (IS_G4X(dev)) {
1285 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1286 u32 ipeir = I915_READ(IPEIR_I965);
1287
a70491cc
JP		 1288 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1289 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1290 pr_err(" INSTDONE: 0x%08x\n",
8a905236 1291 I915_READ(INSTDONE_I965));
a70491cc
JP		 1292 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1293 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1294 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1295 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1296 POSTING_READ(IPEIR_I965);
8a905236
JB		 1297 }
1298 if (eir & GM45_ERROR_PAGE_TABLE) {
1299 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1300 pr_err("page table error\n");
1301 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1302 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1303 POSTING_READ(PGTBL_ER);
8a905236
JB		 1304 }
1305 }
1306
a6c45cf0 1307 if (!IS_GEN2(dev)) {
8a905236
JB		 1308 if (eir & I915_ERROR_PAGE_TABLE) {
1309 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1310 pr_err("page table error\n");
1311 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1312 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1313 POSTING_READ(PGTBL_ER);
8a905236
JB		 1314 }
1315 }
1316
1317 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 1318 pr_err("memory refresh error:\n");
9db4a9c7 1319 for_each_pipe(pipe)
a70491cc 1320 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 1321 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 1322 /* pipestat has already been acked */
1323 }
1324 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 1325 pr_err("instruction error\n");
1326 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
a6c45cf0 1327 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 1328 u32 ipeir = I915_READ(IPEIR);
1329
a70491cc
JP		 1330 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1331 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
1332 pr_err(" INSTDONE: 0x%08x\n", I915_READ(INSTDONE));
1333 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 1334 I915_WRITE(IPEIR, ipeir);
3143a2bf 1335 POSTING_READ(IPEIR);
8a905236
JB		 1336 } else {
1337 u32 ipeir = I915_READ(IPEIR_I965);
1338
a70491cc
JP		 1339 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1340 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1341 pr_err(" INSTDONE: 0x%08x\n",
8a905236 1342 I915_READ(INSTDONE_I965));
a70491cc
JP		 1343 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1344 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1345 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1346 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1347 POSTING_READ(IPEIR_I965);
8a905236
JB		 1348 }
1349 }
1350
1351 I915_WRITE(EIR, eir);
3143a2bf 1352 POSTING_READ(EIR);
8a905236
JB		 1353 eir = I915_READ(EIR);
1354 if (eir) {
1355 /*
1356 * some errors might have become stuck,
1357 * mask them.
1358 */
1359 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1360 I915_WRITE(EMR, I915_READ(EMR) | eir);
1361 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1362 }
35aed2e6
CW		 1363}
1364
1365/**
1366 * i915_handle_error - handle an error interrupt
1367 * @dev: drm device
1368 *
1369 * Do some basic checking of regsiter state at error interrupt time and
1370 * dump it to the syslog. Also call i915_capture_error_state() to make
1371 * sure we get a record and make it available in debugfs. Fire a uevent
1372 * so userspace knows something bad happened (should trigger collection
1373 * of a ring dump etc.).
1374 */
527f9e90 1375void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 1376{
1377 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513
CW		 1378 struct intel_ring_buffer *ring;
1379 int i;
35aed2e6
CW		 1380
1381 i915_capture_error_state(dev);
1382 i915_report_and_clear_eir(dev);
8a905236 1383
ba1234d1 1384 if (wedged) {
30dbf0c0 1385 INIT_COMPLETION(dev_priv->error_completion);
ba1234d1
BG		 1386 atomic_set(&dev_priv->mm.wedged, 1);
1387
11ed50ec
BG		 1388 /*
1389 * Wakeup waiting processes so they don't hang
1390 */
b4519513
CW		 1391 for_each_ring(ring, dev_priv, i)
1392 wake_up_all(&ring->irq_queue);
11ed50ec
BG		 1393 }
1394
9c9fe1f8 1395 queue_work(dev_priv->wq, &dev_priv->error_work);
8a905236
JB		 1396}
1397
4e5359cd
SF		 1398static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1399{
1400 drm_i915_private_t *dev_priv = dev->dev_private;
1401 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 1403 struct drm_i915_gem_object *obj;
4e5359cd
SF		 1404 struct intel_unpin_work *work;
1405 unsigned long flags;
1406 bool stall_detected;
1407
1408 /* Ignore early vblank irqs */
1409 if (intel_crtc == NULL)
1410 return;
1411
1412 spin_lock_irqsave(&dev->event_lock, flags);
1413 work = intel_crtc->unpin_work;
1414
1415 if (work == NULL || work->pending || !work->enable_stall_check) {
1416 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1417 spin_unlock_irqrestore(&dev->event_lock, flags);
1418 return;
1419 }
1420
1421 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 1422 obj = work->pending_flip_obj;
a6c45cf0 1423 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 1424 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545
AR		 1425 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1426 obj->gtt_offset;
4e5359cd 1427 } else {
9db4a9c7 1428 int dspaddr = DSPADDR(intel_crtc->plane);
05394f39 1429 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
01f2c773 1430 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 1431 crtc->x * crtc->fb->bits_per_pixel/8);
1432 }
1433
1434 spin_unlock_irqrestore(&dev->event_lock, flags);
1435
1436 if (stall_detected) {
1437 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1438 intel_prepare_page_flip(dev, intel_crtc->plane);
1439 }
1440}
1441
42f52ef8
KP		 1442/* Called from drm generic code, passed 'crtc' which
1443 * we use as a pipe index
1444 */
f71d4af4 1445static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1446{
1447 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1448 unsigned long irqflags;
71e0ffa5 1449
5eddb70b 1450 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 1451 return -EINVAL;
0a3e67a4 1452
1ec14ad3 1453 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 1454 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 1455 i915_enable_pipestat(dev_priv, pipe,
1456 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 1457 else
7c463586
KP		 1458 i915_enable_pipestat(dev_priv, pipe,
1459 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 1460
1461 /* maintain vblank delivery even in deep C-states */
1462 if (dev_priv->info->gen == 3)
6b26c86d 1463 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 1464 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 1465
0a3e67a4
JB		 1466 return 0;
1467}
1468
f71d4af4 1469static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1470{
1471 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1472 unsigned long irqflags;
1473
1474 if (!i915_pipe_enabled(dev, pipe))
1475 return -EINVAL;
1476
1477 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1478 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1479 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
f796cf8f
JB		 1480 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1481
1482 return 0;
1483}
1484
f71d4af4 1485static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1486{
1487 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1488 unsigned long irqflags;
1489
1490 if (!i915_pipe_enabled(dev, pipe))
1491 return -EINVAL;
1492
1493 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1494 ironlake_enable_display_irq(dev_priv,
1495 DE_PIPEA_VBLANK_IVB << (5 * pipe));
b1f14ad0
JB		 1496 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1497
1498 return 0;
1499}
1500
7e231dbe
JB		 1501static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1502{
1503 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1504 unsigned long irqflags;
31acc7f5 1505 u32 imr;
7e231dbe
JB		 1506
1507 if (!i915_pipe_enabled(dev, pipe))
1508 return -EINVAL;
1509
1510 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7e231dbe 1511 imr = I915_READ(VLV_IMR);
31acc7f5 1512 if (pipe == 0)
7e231dbe 1513 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1514 else
7e231dbe 1515 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1516 I915_WRITE(VLV_IMR, imr);
31acc7f5
JB		 1517 i915_enable_pipestat(dev_priv, pipe,
1518 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe
JB		 1519 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1520
1521 return 0;
1522}
1523
42f52ef8
KP		 1524/* Called from drm generic code, passed 'crtc' which
1525 * we use as a pipe index
1526 */
f71d4af4 1527static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1528{
1529 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1530 unsigned long irqflags;
0a3e67a4 1531
1ec14ad3 1532 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 1533 if (dev_priv->info->gen == 3)
6b26c86d 1534 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 1535
f796cf8f
JB		 1536 i915_disable_pipestat(dev_priv, pipe,
1537 PIPE_VBLANK_INTERRUPT_ENABLE |
1538 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1539 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1540}
1541
f71d4af4 1542static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1543{
1544 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1545 unsigned long irqflags;
1546
1547 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1548 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1549 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1ec14ad3 1550 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 1551}
1552
f71d4af4 1553static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1554{
1555 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1556 unsigned long irqflags;
1557
1558 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1559 ironlake_disable_display_irq(dev_priv,
1560 DE_PIPEA_VBLANK_IVB << (pipe * 5));
b1f14ad0
JB		 1561 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1562}
1563
7e231dbe
JB		 1564static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1565{
1566 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1567 unsigned long irqflags;
31acc7f5 1568 u32 imr;
7e231dbe
JB		 1569
1570 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5
JB		 1571 i915_disable_pipestat(dev_priv, pipe,
1572 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe 1573 imr = I915_READ(VLV_IMR);
31acc7f5 1574 if (pipe == 0)
7e231dbe 1575 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1576 else
7e231dbe 1577 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1578 I915_WRITE(VLV_IMR, imr);
7e231dbe
JB		 1579 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1580}
1581
893eead0
CW		 1582static u32
1583ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 1584{
893eead0
CW		 1585 return list_entry(ring->request_list.prev,
1586 struct drm_i915_gem_request, list)->seqno;
1587}
1588
1589static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1590{
1591 if (list_empty(&ring->request_list) ||
1592 i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1593 /* Issue a wake-up to catch stuck h/w. */
9574b3fe
BW		 1594 if (waitqueue_active(&ring->irq_queue)) {
1595 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1596 ring->name);
893eead0
CW		 1597 wake_up_all(&ring->irq_queue);
1598 *err = true;
1599 }
1600 return true;
1601 }
1602 return false;
f65d9421
BG		 1603}
1604
1ec14ad3
CW		 1605static bool kick_ring(struct intel_ring_buffer *ring)
1606{
1607 struct drm_device *dev = ring->dev;
1608 struct drm_i915_private *dev_priv = dev->dev_private;
1609 u32 tmp = I915_READ_CTL(ring);
1610 if (tmp & RING_WAIT) {
1611 DRM_ERROR("Kicking stuck wait on %s\n",
1612 ring->name);
1613 I915_WRITE_CTL(ring, tmp);
1614 return true;
1615 }
1ec14ad3
CW		 1616 return false;
1617}
1618
d1e61e7f
CW		 1619static bool i915_hangcheck_hung(struct drm_device *dev)
1620{
1621 drm_i915_private_t *dev_priv = dev->dev_private;
1622
1623 if (dev_priv->hangcheck_count++ > 1) {
b4519513
CW		 1624 bool hung = true;
1625
d1e61e7f
CW		 1626 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1627 i915_handle_error(dev, true);
1628
1629 if (!IS_GEN2(dev)) {
b4519513
CW		 1630 struct intel_ring_buffer *ring;
1631 int i;
1632
d1e61e7f
CW		 1633 /* Is the chip hanging on a WAIT_FOR_EVENT?
1634 * If so we can simply poke the RB_WAIT bit
1635 * and break the hang. This should work on
1636 * all but the second generation chipsets.
1637 */
b4519513
CW		 1638 for_each_ring(ring, dev_priv, i)
1639 hung &= !kick_ring(ring);
d1e61e7f
CW		 1640 }
1641
b4519513 1642 return hung;
d1e61e7f
CW		 1643 }
1644
1645 return false;
1646}
1647
f65d9421
BG		 1648/**
1649 * This is called when the chip hasn't reported back with completed
1650 * batchbuffers in a long time. The first time this is called we simply record
1651 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1652 * again, we assume the chip is wedged and try to fix it.
1653 */
1654void i915_hangcheck_elapsed(unsigned long data)
1655{
1656 struct drm_device *dev = (struct drm_device *)data;
1657 drm_i915_private_t *dev_priv = dev->dev_private;
b4519513
CW		 1658 uint32_t acthd[I915_NUM_RINGS], instdone, instdone1;
1659 struct intel_ring_buffer *ring;
1660 bool err = false, idle;
1661 int i;
893eead0 1662
3e0dc6b0
BW		 1663 if (!i915_enable_hangcheck)
1664 return;
1665
b4519513
CW		 1666 memset(acthd, 0, sizeof(acthd));
1667 idle = true;
1668 for_each_ring(ring, dev_priv, i) {
1669 idle &= i915_hangcheck_ring_idle(ring, &err);
1670 acthd[i] = intel_ring_get_active_head(ring);
1671 }
1672
893eead0 1673 /* If all work is done then ACTHD clearly hasn't advanced. */
b4519513 1674 if (idle) {
d1e61e7f
CW		 1675 if (err) {
1676 if (i915_hangcheck_hung(dev))
1677 return;
1678
893eead0 1679 goto repeat;
d1e61e7f
CW		 1680 }
1681
1682 dev_priv->hangcheck_count = 0;
893eead0
CW		 1683 return;
1684 }
b9201c14 1685
a6c45cf0 1686 if (INTEL_INFO(dev)->gen < 4) {
cbb465e7
CW		 1687 instdone = I915_READ(INSTDONE);
1688 instdone1 = 0;
1689 } else {
cbb465e7
CW		 1690 instdone = I915_READ(INSTDONE_I965);
1691 instdone1 = I915_READ(INSTDONE1);
1692 }
b4519513
CW		 1693
1694 if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 &&
cbb465e7
CW		 1695 dev_priv->last_instdone == instdone &&
1696 dev_priv->last_instdone1 == instdone1) {
d1e61e7f 1697 if (i915_hangcheck_hung(dev))
cbb465e7 1698 return;
cbb465e7
CW		 1699 } else {
1700 dev_priv->hangcheck_count = 0;
1701
b4519513 1702 memcpy(dev_priv->last_acthd, acthd, sizeof(acthd));
cbb465e7
CW		 1703 dev_priv->last_instdone = instdone;
1704 dev_priv->last_instdone1 = instdone1;
1705 }
f65d9421 1706
893eead0 1707repeat:
f65d9421 1708 /* Reset timer case chip hangs without another request being added */
b3b079db
CW		 1709 mod_timer(&dev_priv->hangcheck_timer,
1710 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
f65d9421
BG		 1711}
1712
1da177e4
LT		 1713/* drm_dma.h hooks
1714*/
f71d4af4 1715static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 1716{
1717 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1718
4697995b
JB		 1719 atomic_set(&dev_priv->irq_received, 0);
1720
036a4a7d 1721 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 1722
036a4a7d
ZW		 1723 /* XXX hotplug from PCH */
1724
1725 I915_WRITE(DEIMR, 0xffffffff);
1726 I915_WRITE(DEIER, 0x0);
3143a2bf 1727 POSTING_READ(DEIER);
036a4a7d
ZW		 1728
1729 /* and GT */
1730 I915_WRITE(GTIMR, 0xffffffff);
1731 I915_WRITE(GTIER, 0x0);
3143a2bf 1732 POSTING_READ(GTIER);
c650156a
ZW		 1733
1734 /* south display irq */
1735 I915_WRITE(SDEIMR, 0xffffffff);
1736 I915_WRITE(SDEIER, 0x0);
3143a2bf 1737 POSTING_READ(SDEIER);
036a4a7d
ZW		 1738}
1739
7e231dbe
JB		 1740static void valleyview_irq_preinstall(struct drm_device *dev)
1741{
1742 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1743 int pipe;
1744
1745 atomic_set(&dev_priv->irq_received, 0);
1746
7e231dbe
JB		 1747 /* VLV magic */
1748 I915_WRITE(VLV_IMR, 0);
1749 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1750 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1751 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1752
7e231dbe
JB		 1753 /* and GT */
1754 I915_WRITE(GTIIR, I915_READ(GTIIR));
1755 I915_WRITE(GTIIR, I915_READ(GTIIR));
1756 I915_WRITE(GTIMR, 0xffffffff);
1757 I915_WRITE(GTIER, 0x0);
1758 POSTING_READ(GTIER);
1759
1760 I915_WRITE(DPINVGTT, 0xff);
1761
1762 I915_WRITE(PORT_HOTPLUG_EN, 0);
1763 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1764 for_each_pipe(pipe)
1765 I915_WRITE(PIPESTAT(pipe), 0xffff);
1766 I915_WRITE(VLV_IIR, 0xffffffff);
1767 I915_WRITE(VLV_IMR, 0xffffffff);
1768 I915_WRITE(VLV_IER, 0x0);
1769 POSTING_READ(VLV_IER);
1770}
1771
7fe0b973
KP		 1772/*
1773 * Enable digital hotplug on the PCH, and configure the DP short pulse
1774 * duration to 2ms (which is the minimum in the Display Port spec)
1775 *
1776 * This register is the same on all known PCH chips.
1777 */
1778
1779static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1780{
1781 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1782 u32 hotplug;
1783
1784 hotplug = I915_READ(PCH_PORT_HOTPLUG);
1785 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1786 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1787 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1788 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1789 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1790}
1791
f71d4af4 1792static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d
ZW		 1793{
1794 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1795 /* enable kind of interrupts always enabled */
013d5aa2
JB		 1796 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1797 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1ec14ad3 1798 u32 render_irqs;
2d7b8366 1799 u32 hotplug_mask;
036a4a7d 1800
1ec14ad3 1801 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 1802
1803 /* should always can generate irq */
1804 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3
CW		 1805 I915_WRITE(DEIMR, dev_priv->irq_mask);
1806 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
3143a2bf 1807 POSTING_READ(DEIER);
036a4a7d 1808
1ec14ad3 1809 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 1810
1811 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 1812 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 1813
1ec14ad3
CW		 1814 if (IS_GEN6(dev))
1815 render_irqs =
1816 GT_USER_INTERRUPT |
e2a1e2f0
BW		 1817 GEN6_BSD_USER_INTERRUPT |
1818 GEN6_BLITTER_USER_INTERRUPT;
1ec14ad3
CW		 1819 else
1820 render_irqs =
88f23b8f 1821 GT_USER_INTERRUPT |
c6df541c 1822 GT_PIPE_NOTIFY |
1ec14ad3
CW		 1823 GT_BSD_USER_INTERRUPT;
1824 I915_WRITE(GTIER, render_irqs);
3143a2bf 1825 POSTING_READ(GTIER);
036a4a7d 1826
2d7b8366 1827 if (HAS_PCH_CPT(dev)) {
9035a97a
CW		 1828 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1829 SDE_PORTB_HOTPLUG_CPT |
1830 SDE_PORTC_HOTPLUG_CPT |
1831 SDE_PORTD_HOTPLUG_CPT);
2d7b8366 1832 } else {
9035a97a
CW		 1833 hotplug_mask = (SDE_CRT_HOTPLUG |
1834 SDE_PORTB_HOTPLUG |
1835 SDE_PORTC_HOTPLUG |
1836 SDE_PORTD_HOTPLUG |
1837 SDE_AUX_MASK);
2d7b8366
YL		 1838 }
1839
1ec14ad3 1840 dev_priv->pch_irq_mask = ~hotplug_mask;
c650156a
ZW		 1841
1842 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1ec14ad3
CW		 1843 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1844 I915_WRITE(SDEIER, hotplug_mask);
3143a2bf 1845 POSTING_READ(SDEIER);
c650156a 1846
7fe0b973
KP		 1847 ironlake_enable_pch_hotplug(dev);
1848
f97108d1
JB		 1849 if (IS_IRONLAKE_M(dev)) {
1850 /* Clear & enable PCU event interrupts */
1851 I915_WRITE(DEIIR, DE_PCU_EVENT);
1852 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1853 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1854 }
1855
036a4a7d
ZW		 1856 return 0;
1857}
1858
f71d4af4 1859static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 1860{
1861 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1862 /* enable kind of interrupts always enabled */
b615b57a
CW		 1863 u32 display_mask =
1864 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
1865 DE_PLANEC_FLIP_DONE_IVB |
1866 DE_PLANEB_FLIP_DONE_IVB |
1867 DE_PLANEA_FLIP_DONE_IVB;
b1f14ad0
JB		 1868 u32 render_irqs;
1869 u32 hotplug_mask;
1870
b1f14ad0
JB		 1871 dev_priv->irq_mask = ~display_mask;
1872
1873 /* should always can generate irq */
1874 I915_WRITE(DEIIR, I915_READ(DEIIR));
1875 I915_WRITE(DEIMR, dev_priv->irq_mask);
b615b57a
CW		 1876 I915_WRITE(DEIER,
1877 display_mask |
1878 DE_PIPEC_VBLANK_IVB |
1879 DE_PIPEB_VBLANK_IVB |
1880 DE_PIPEA_VBLANK_IVB);
b1f14ad0
JB		 1881 POSTING_READ(DEIER);
1882
15b9f80e 1883 dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 1884
1885 I915_WRITE(GTIIR, I915_READ(GTIIR));
1886 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1887
e2a1e2f0 1888 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
15b9f80e 1889 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 1890 I915_WRITE(GTIER, render_irqs);
1891 POSTING_READ(GTIER);
1892
1893 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1894 SDE_PORTB_HOTPLUG_CPT |
1895 SDE_PORTC_HOTPLUG_CPT |
1896 SDE_PORTD_HOTPLUG_CPT);
1897 dev_priv->pch_irq_mask = ~hotplug_mask;
1898
1899 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1900 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1901 I915_WRITE(SDEIER, hotplug_mask);
1902 POSTING_READ(SDEIER);
1903
7fe0b973
KP		 1904 ironlake_enable_pch_hotplug(dev);
1905
b1f14ad0
JB		 1906 return 0;
1907}
1908
7e231dbe
JB		 1909static int valleyview_irq_postinstall(struct drm_device *dev)
1910{
1911 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7e231dbe
JB		 1912 u32 enable_mask;
1913 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
31acc7f5 1914 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
7e231dbe
JB		 1915 u16 msid;
1916
1917 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
31acc7f5
JB		 1918 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
1919 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1920 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
7e231dbe
JB		 1921 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1922
31acc7f5
JB		 1923 /*
1924 *Leave vblank interrupts masked initially. enable/disable will
1925 * toggle them based on usage.
1926 */
1927 dev_priv->irq_mask = (~enable_mask) |
1928 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1929 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1930
7e231dbe
JB		 1931 dev_priv->pipestat[0] = 0;
1932 dev_priv->pipestat[1] = 0;
1933
7e231dbe
JB		 1934 /* Hack for broken MSIs on VLV */
1935 pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
1936 pci_read_config_word(dev->pdev, 0x98, &msid);
1937 msid &= 0xff; /* mask out delivery bits */
1938 msid |= (1<<14);
1939 pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
1940
1941 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
1942 I915_WRITE(VLV_IER, enable_mask);
1943 I915_WRITE(VLV_IIR, 0xffffffff);
1944 I915_WRITE(PIPESTAT(0), 0xffff);
1945 I915_WRITE(PIPESTAT(1), 0xffff);
1946 POSTING_READ(VLV_IER);
1947
31acc7f5
JB		 1948 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
1949 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
1950
7e231dbe
JB		 1951 I915_WRITE(VLV_IIR, 0xffffffff);
1952 I915_WRITE(VLV_IIR, 0xffffffff);
1953
31acc7f5 1954 dev_priv->gt_irq_mask = ~0;
7e231dbe
JB		 1955
1956 I915_WRITE(GTIIR, I915_READ(GTIIR));
1957 I915_WRITE(GTIIR, I915_READ(GTIIR));
31acc7f5
JB		 1958 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1959 I915_WRITE(GTIER, GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
1960 GT_GEN6_BLT_CS_ERROR_INTERRUPT |
1961 GT_GEN6_BLT_USER_INTERRUPT |
1962 GT_GEN6_BSD_USER_INTERRUPT |
1963 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
1964 GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
1965 GT_PIPE_NOTIFY |
1966 GT_RENDER_CS_ERROR_INTERRUPT |
1967 GT_SYNC_STATUS |
1968 GT_USER_INTERRUPT);
7e231dbe
JB		 1969 POSTING_READ(GTIER);
1970
1971 /* ack & enable invalid PTE error interrupts */
1972#if 0 /* FIXME: add support to irq handler for checking these bits */
1973 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
1974 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
1975#endif
1976
1977 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1978#if 0 /* FIXME: check register definitions; some have moved */
1979 /* Note HDMI and DP share bits */
1980 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1981 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1982 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1983 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1984 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1985 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1986 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1987 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1988 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1989 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1990 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1991 hotplug_en |= CRT_HOTPLUG_INT_EN;
1992 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1993 }
1994#endif
1995
1996 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1997
1998 return 0;
1999}
2000
7e231dbe
JB		 2001static void valleyview_irq_uninstall(struct drm_device *dev)
2002{
2003 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2004 int pipe;
2005
2006 if (!dev_priv)
2007 return;
2008
7e231dbe
JB		 2009 for_each_pipe(pipe)
2010 I915_WRITE(PIPESTAT(pipe), 0xffff);
2011
2012 I915_WRITE(HWSTAM, 0xffffffff);
2013 I915_WRITE(PORT_HOTPLUG_EN, 0);
2014 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2015 for_each_pipe(pipe)
2016 I915_WRITE(PIPESTAT(pipe), 0xffff);
2017 I915_WRITE(VLV_IIR, 0xffffffff);
2018 I915_WRITE(VLV_IMR, 0xffffffff);
2019 I915_WRITE(VLV_IER, 0x0);
2020 POSTING_READ(VLV_IER);
2021}
2022
f71d4af4 2023static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 2024{
2025 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 2026
2027 if (!dev_priv)
2028 return;
2029
036a4a7d
ZW		 2030 I915_WRITE(HWSTAM, 0xffffffff);
2031
2032 I915_WRITE(DEIMR, 0xffffffff);
2033 I915_WRITE(DEIER, 0x0);
2034 I915_WRITE(DEIIR, I915_READ(DEIIR));
2035
2036 I915_WRITE(GTIMR, 0xffffffff);
2037 I915_WRITE(GTIER, 0x0);
2038 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f
KP		 2039
2040 I915_WRITE(SDEIMR, 0xffffffff);
2041 I915_WRITE(SDEIER, 0x0);
2042 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
036a4a7d
ZW		 2043}
2044
a266c7d5 2045static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 2046{
2047 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2048 int pipe;
91e3738e 2049
a266c7d5 2050 atomic_set(&dev_priv->irq_received, 0);
5ca58282 2051
9db4a9c7
JB		 2052 for_each_pipe(pipe)
2053 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 2054 I915_WRITE16(IMR, 0xffff);
2055 I915_WRITE16(IER, 0x0);
2056 POSTING_READ16(IER);
c2798b19
CW		 2057}
2058
2059static int i8xx_irq_postinstall(struct drm_device *dev)
2060{
2061 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2062
c2798b19
CW		 2063 dev_priv->pipestat[0] = 0;
2064 dev_priv->pipestat[1] = 0;
2065
2066 I915_WRITE16(EMR,
2067 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2068
2069 /* Unmask the interrupts that we always want on. */
2070 dev_priv->irq_mask =
2071 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2072 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2073 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2074 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2075 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2076 I915_WRITE16(IMR, dev_priv->irq_mask);
2077
2078 I915_WRITE16(IER,
2079 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2080 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2081 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2082 I915_USER_INTERRUPT);
2083 POSTING_READ16(IER);
2084
2085 return 0;
2086}
2087
2088static irqreturn_t i8xx_irq_handler(DRM_IRQ_ARGS)
2089{
2090 struct drm_device *dev = (struct drm_device *) arg;
2091 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 2092 u16 iir, new_iir;
2093 u32 pipe_stats[2];
2094 unsigned long irqflags;
2095 int irq_received;
2096 int pipe;
2097 u16 flip_mask =
2098 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2099 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2100
2101 atomic_inc(&dev_priv->irq_received);
2102
2103 iir = I915_READ16(IIR);
2104 if (iir == 0)
2105 return IRQ_NONE;
2106
2107 while (iir & ~flip_mask) {
2108 /* Can't rely on pipestat interrupt bit in iir as it might
2109 * have been cleared after the pipestat interrupt was received.
2110 * It doesn't set the bit in iir again, but it still produces
2111 * interrupts (for non-MSI).
2112 */
2113 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2114 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2115 i915_handle_error(dev, false);
2116
2117 for_each_pipe(pipe) {
2118 int reg = PIPESTAT(pipe);
2119 pipe_stats[pipe] = I915_READ(reg);
2120
2121 /*
2122 * Clear the PIPE*STAT regs before the IIR
2123 */
2124 if (pipe_stats[pipe] & 0x8000ffff) {
2125 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2126 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2127 pipe_name(pipe));
2128 I915_WRITE(reg, pipe_stats[pipe]);
2129 irq_received = 1;
2130 }
2131 }
2132 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2133
2134 I915_WRITE16(IIR, iir & ~flip_mask);
2135 new_iir = I915_READ16(IIR); /* Flush posted writes */
2136
d05c617e 2137 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 2138
2139 if (iir & I915_USER_INTERRUPT)
2140 notify_ring(dev, &dev_priv->ring[RCS]);
2141
2142 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2143 drm_handle_vblank(dev, 0)) {
2144 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2145 intel_prepare_page_flip(dev, 0);
2146 intel_finish_page_flip(dev, 0);
2147 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2148 }
2149 }
2150
2151 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2152 drm_handle_vblank(dev, 1)) {
2153 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2154 intel_prepare_page_flip(dev, 1);
2155 intel_finish_page_flip(dev, 1);
2156 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2157 }
2158 }
2159
2160 iir = new_iir;
2161 }
2162
2163 return IRQ_HANDLED;
2164}
2165
2166static void i8xx_irq_uninstall(struct drm_device * dev)
2167{
2168 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2169 int pipe;
2170
c2798b19
CW		 2171 for_each_pipe(pipe) {
2172 /* Clear enable bits; then clear status bits */
2173 I915_WRITE(PIPESTAT(pipe), 0);
2174 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2175 }
2176 I915_WRITE16(IMR, 0xffff);
2177 I915_WRITE16(IER, 0x0);
2178 I915_WRITE16(IIR, I915_READ16(IIR));
2179}
2180
a266c7d5
CW		 2181static void i915_irq_preinstall(struct drm_device * dev)
2182{
2183 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2184 int pipe;
2185
2186 atomic_set(&dev_priv->irq_received, 0);
2187
2188 if (I915_HAS_HOTPLUG(dev)) {
2189 I915_WRITE(PORT_HOTPLUG_EN, 0);
2190 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2191 }
2192
00d98ebd 2193 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 2194 for_each_pipe(pipe)
2195 I915_WRITE(PIPESTAT(pipe), 0);
2196 I915_WRITE(IMR, 0xffffffff);
2197 I915_WRITE(IER, 0x0);
2198 POSTING_READ(IER);
2199}
2200
2201static int i915_irq_postinstall(struct drm_device *dev)
2202{
2203 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 2204 u32 enable_mask;
a266c7d5 2205
a266c7d5
CW		 2206 dev_priv->pipestat[0] = 0;
2207 dev_priv->pipestat[1] = 0;
2208
38bde180
CW		 2209 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2210
2211 /* Unmask the interrupts that we always want on. */
2212 dev_priv->irq_mask =
2213 ~(I915_ASLE_INTERRUPT |
2214 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2215 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2216 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2217 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2218 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2219
2220 enable_mask =
2221 I915_ASLE_INTERRUPT |
2222 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2223 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2224 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2225 I915_USER_INTERRUPT;
2226
a266c7d5
CW		 2227 if (I915_HAS_HOTPLUG(dev)) {
2228 /* Enable in IER... */
2229 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2230 /* and unmask in IMR */
2231 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2232 }
2233
a266c7d5
CW		 2234 I915_WRITE(IMR, dev_priv->irq_mask);
2235 I915_WRITE(IER, enable_mask);
2236 POSTING_READ(IER);
2237
2238 if (I915_HAS_HOTPLUG(dev)) {
2239 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2240
a266c7d5
CW		 2241 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2242 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2243 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2244 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2245 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2246 hotplug_en |= HDMID_HOTPLUG_INT_EN;
084b612e 2247 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
a266c7d5 2248 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
084b612e 2249 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
a266c7d5
CW		 2250 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2251 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2252 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5
CW		 2253 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2254 }
2255
2256 /* Ignore TV since it's buggy */
2257
2258 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2259 }
2260
2261 intel_opregion_enable_asle(dev);
2262
2263 return 0;
2264}
2265
2266static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
2267{
2268 struct drm_device *dev = (struct drm_device *) arg;
2269 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 2270 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 2271 unsigned long irqflags;
38bde180
CW		 2272 u32 flip_mask =
2273 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2274 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2275 u32 flip[2] = {
2276 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2277 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2278 };
2279 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 2280
2281 atomic_inc(&dev_priv->irq_received);
2282
2283 iir = I915_READ(IIR);
38bde180
CW		 2284 do {
2285 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 2286 bool blc_event = false;
a266c7d5
CW		 2287
2288 /* Can't rely on pipestat interrupt bit in iir as it might
2289 * have been cleared after the pipestat interrupt was received.
2290 * It doesn't set the bit in iir again, but it still produces
2291 * interrupts (for non-MSI).
2292 */
2293 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2294 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2295 i915_handle_error(dev, false);
2296
2297 for_each_pipe(pipe) {
2298 int reg = PIPESTAT(pipe);
2299 pipe_stats[pipe] = I915_READ(reg);
2300
38bde180 2301 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 2302 if (pipe_stats[pipe] & 0x8000ffff) {
2303 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2304 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2305 pipe_name(pipe));
2306 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 2307 irq_received = true;
a266c7d5
CW		 2308 }
2309 }
2310 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2311
2312 if (!irq_received)
2313 break;
2314
a266c7d5
CW		 2315 /* Consume port. Then clear IIR or we'll miss events */
2316 if ((I915_HAS_HOTPLUG(dev)) &&
2317 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2318 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2319
2320 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2321 hotplug_status);
2322 if (hotplug_status & dev_priv->hotplug_supported_mask)
2323 queue_work(dev_priv->wq,
2324 &dev_priv->hotplug_work);
2325
2326 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 2327 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 2328 }
2329
38bde180 2330 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2331 new_iir = I915_READ(IIR); /* Flush posted writes */
2332
a266c7d5
CW		 2333 if (iir & I915_USER_INTERRUPT)
2334 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 2335
a266c7d5 2336 for_each_pipe(pipe) {
38bde180
CW		 2337 int plane = pipe;
2338 if (IS_MOBILE(dev))
2339 plane = !plane;
8291ee90 2340 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2341 drm_handle_vblank(dev, pipe)) {
38bde180
CW		 2342 if (iir & flip[plane]) {
2343 intel_prepare_page_flip(dev, plane);
2344 intel_finish_page_flip(dev, pipe);
2345 flip_mask &= ~flip[plane];
2346 }
a266c7d5
CW		 2347 }
2348
2349 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2350 blc_event = true;
2351 }
2352
a266c7d5
CW		 2353 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2354 intel_opregion_asle_intr(dev);
2355
2356 /* With MSI, interrupts are only generated when iir
2357 * transitions from zero to nonzero. If another bit got
2358 * set while we were handling the existing iir bits, then
2359 * we would never get another interrupt.
2360 *
2361 * This is fine on non-MSI as well, as if we hit this path
2362 * we avoid exiting the interrupt handler only to generate
2363 * another one.
2364 *
2365 * Note that for MSI this could cause a stray interrupt report
2366 * if an interrupt landed in the time between writing IIR and
2367 * the posting read. This should be rare enough to never
2368 * trigger the 99% of 100,000 interrupts test for disabling
2369 * stray interrupts.
2370 */
38bde180 2371 ret = IRQ_HANDLED;
a266c7d5 2372 iir = new_iir;
38bde180 2373 } while (iir & ~flip_mask);
a266c7d5 2374
d05c617e 2375 i915_update_dri1_breadcrumb(dev);
8291ee90 2376
a266c7d5
CW		 2377 return ret;
2378}
2379
2380static void i915_irq_uninstall(struct drm_device * dev)
2381{
2382 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2383 int pipe;
2384
a266c7d5
CW		 2385 if (I915_HAS_HOTPLUG(dev)) {
2386 I915_WRITE(PORT_HOTPLUG_EN, 0);
2387 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2388 }
2389
00d98ebd 2390 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 2391 for_each_pipe(pipe) {
2392 /* Clear enable bits; then clear status bits */
a266c7d5 2393 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 2394 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2395 }
a266c7d5
CW		 2396 I915_WRITE(IMR, 0xffffffff);
2397 I915_WRITE(IER, 0x0);
2398
a266c7d5
CW		 2399 I915_WRITE(IIR, I915_READ(IIR));
2400}
2401
2402static void i965_irq_preinstall(struct drm_device * dev)
2403{
2404 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2405 int pipe;
2406
2407 atomic_set(&dev_priv->irq_received, 0);
2408
adca4730
CW		 2409 I915_WRITE(PORT_HOTPLUG_EN, 0);
2410 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2411
2412 I915_WRITE(HWSTAM, 0xeffe);
2413 for_each_pipe(pipe)
2414 I915_WRITE(PIPESTAT(pipe), 0);
2415 I915_WRITE(IMR, 0xffffffff);
2416 I915_WRITE(IER, 0x0);
2417 POSTING_READ(IER);
2418}
2419
2420static int i965_irq_postinstall(struct drm_device *dev)
2421{
2422 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
adca4730 2423 u32 hotplug_en;
bbba0a97 2424 u32 enable_mask;
a266c7d5
CW		 2425 u32 error_mask;
2426
a266c7d5 2427 /* Unmask the interrupts that we always want on. */
bbba0a97 2428 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 2429 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 2430 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2431 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2432 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2433 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2434 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2435
2436 enable_mask = ~dev_priv->irq_mask;
2437 enable_mask |= I915_USER_INTERRUPT;
2438
2439 if (IS_G4X(dev))
2440 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5
CW		 2441
2442 dev_priv->pipestat[0] = 0;
2443 dev_priv->pipestat[1] = 0;
2444
a266c7d5
CW		 2445 /*
2446 * Enable some error detection, note the instruction error mask
2447 * bit is reserved, so we leave it masked.
2448 */
2449 if (IS_G4X(dev)) {
2450 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2451 GM45_ERROR_MEM_PRIV |
2452 GM45_ERROR_CP_PRIV |
2453 I915_ERROR_MEMORY_REFRESH);
2454 } else {
2455 error_mask = ~(I915_ERROR_PAGE_TABLE |
2456 I915_ERROR_MEMORY_REFRESH);
2457 }
2458 I915_WRITE(EMR, error_mask);
2459
2460 I915_WRITE(IMR, dev_priv->irq_mask);
2461 I915_WRITE(IER, enable_mask);
2462 POSTING_READ(IER);
2463
adca4730
CW		 2464 /* Note HDMI and DP share hotplug bits */
2465 hotplug_en = 0;
2466 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2467 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2468 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2469 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2470 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2471 hotplug_en |= HDMID_HOTPLUG_INT_EN;
084b612e
CW		 2472 if (IS_G4X(dev)) {
2473 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
2474 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2475 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
2476 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2477 } else {
2478 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
2479 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2480 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
2481 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2482 }
adca4730
CW		 2483 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2484 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5 2485
adca4730
CW		 2486 /* Programming the CRT detection parameters tends
2487 to generate a spurious hotplug event about three
2488 seconds later. So just do it once.
2489 */
2490 if (IS_G4X(dev))
2491 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2492 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2493 }
a266c7d5 2494
adca4730 2495 /* Ignore TV since it's buggy */
a266c7d5 2496
adca4730 2497 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
a266c7d5
CW		 2498
2499 intel_opregion_enable_asle(dev);
2500
2501 return 0;
2502}
2503
2504static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS)
2505{
2506 struct drm_device *dev = (struct drm_device *) arg;
2507 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 2508 u32 iir, new_iir;
2509 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 2510 unsigned long irqflags;
2511 int irq_received;
2512 int ret = IRQ_NONE, pipe;
a266c7d5
CW		 2513
2514 atomic_inc(&dev_priv->irq_received);
2515
2516 iir = I915_READ(IIR);
2517
a266c7d5 2518 for (;;) {
2c8ba29f
CW		 2519 bool blc_event = false;
2520
a266c7d5
CW		 2521 irq_received = iir != 0;
2522
2523 /* Can't rely on pipestat interrupt bit in iir as it might
2524 * have been cleared after the pipestat interrupt was received.
2525 * It doesn't set the bit in iir again, but it still produces
2526 * interrupts (for non-MSI).
2527 */
2528 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2529 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2530 i915_handle_error(dev, false);
2531
2532 for_each_pipe(pipe) {
2533 int reg = PIPESTAT(pipe);
2534 pipe_stats[pipe] = I915_READ(reg);
2535
2536 /*
2537 * Clear the PIPE*STAT regs before the IIR
2538 */
2539 if (pipe_stats[pipe] & 0x8000ffff) {
2540 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2541 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2542 pipe_name(pipe));
2543 I915_WRITE(reg, pipe_stats[pipe]);
2544 irq_received = 1;
2545 }
2546 }
2547 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2548
2549 if (!irq_received)
2550 break;
2551
2552 ret = IRQ_HANDLED;
2553
2554 /* Consume port. Then clear IIR or we'll miss events */
adca4730 2555 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
a266c7d5
CW		 2556 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2557
2558 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2559 hotplug_status);
2560 if (hotplug_status & dev_priv->hotplug_supported_mask)
2561 queue_work(dev_priv->wq,
2562 &dev_priv->hotplug_work);
2563
2564 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2565 I915_READ(PORT_HOTPLUG_STAT);
2566 }
2567
2568 I915_WRITE(IIR, iir);
2569 new_iir = I915_READ(IIR); /* Flush posted writes */
2570
a266c7d5
CW		 2571 if (iir & I915_USER_INTERRUPT)
2572 notify_ring(dev, &dev_priv->ring[RCS]);
2573 if (iir & I915_BSD_USER_INTERRUPT)
2574 notify_ring(dev, &dev_priv->ring[VCS]);
2575
4f7d1e79 2576 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
a266c7d5 2577 intel_prepare_page_flip(dev, 0);
a266c7d5 2578
4f7d1e79 2579 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
a266c7d5 2580 intel_prepare_page_flip(dev, 1);
a266c7d5
CW		 2581
2582 for_each_pipe(pipe) {
2c8ba29f 2583 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2584 drm_handle_vblank(dev, pipe)) {
4f7d1e79
CW		 2585 i915_pageflip_stall_check(dev, pipe);
2586 intel_finish_page_flip(dev, pipe);
a266c7d5
CW		 2587 }
2588
2589 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2590 blc_event = true;
2591 }
2592
2593
2594 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2595 intel_opregion_asle_intr(dev);
2596
2597 /* With MSI, interrupts are only generated when iir
2598 * transitions from zero to nonzero. If another bit got
2599 * set while we were handling the existing iir bits, then
2600 * we would never get another interrupt.
2601 *
2602 * This is fine on non-MSI as well, as if we hit this path
2603 * we avoid exiting the interrupt handler only to generate
2604 * another one.
2605 *
2606 * Note that for MSI this could cause a stray interrupt report
2607 * if an interrupt landed in the time between writing IIR and
2608 * the posting read. This should be rare enough to never
2609 * trigger the 99% of 100,000 interrupts test for disabling
2610 * stray interrupts.
2611 */
2612 iir = new_iir;
2613 }
2614
d05c617e 2615 i915_update_dri1_breadcrumb(dev);
2c8ba29f 2616
a266c7d5
CW		 2617 return ret;
2618}
2619
2620static void i965_irq_uninstall(struct drm_device * dev)
2621{
2622 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2623 int pipe;
2624
2625 if (!dev_priv)
2626 return;
2627
adca4730
CW		 2628 I915_WRITE(PORT_HOTPLUG_EN, 0);
2629 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2630
2631 I915_WRITE(HWSTAM, 0xffffffff);
2632 for_each_pipe(pipe)
2633 I915_WRITE(PIPESTAT(pipe), 0);
2634 I915_WRITE(IMR, 0xffffffff);
2635 I915_WRITE(IER, 0x0);
2636
2637 for_each_pipe(pipe)
2638 I915_WRITE(PIPESTAT(pipe),
2639 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2640 I915_WRITE(IIR, I915_READ(IIR));
2641}
2642
f71d4af4
JB		 2643void intel_irq_init(struct drm_device *dev)
2644{
8b2e326d
CW		 2645 struct drm_i915_private *dev_priv = dev->dev_private;
2646
2647 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2648 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
2649 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
98fd81cd 2650 INIT_WORK(&dev_priv->parity_error_work, ivybridge_parity_work);
8b2e326d 2651
f71d4af4
JB		 2652 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2653 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7d4e146f 2654 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 2655 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2656 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2657 }
2658
c3613de9
KP		 2659 if (drm_core_check_feature(dev, DRIVER_MODESET))
2660 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2661 else
2662 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 2663 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2664
7e231dbe
JB		 2665 if (IS_VALLEYVIEW(dev)) {
2666 dev->driver->irq_handler = valleyview_irq_handler;
2667 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2668 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2669 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2670 dev->driver->enable_vblank = valleyview_enable_vblank;
2671 dev->driver->disable_vblank = valleyview_disable_vblank;
2672 } else if (IS_IVYBRIDGE(dev)) {
f71d4af4
JB		 2673 /* Share pre & uninstall handlers with ILK/SNB */
2674 dev->driver->irq_handler = ivybridge_irq_handler;
2675 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2676 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2677 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2678 dev->driver->enable_vblank = ivybridge_enable_vblank;
2679 dev->driver->disable_vblank = ivybridge_disable_vblank;
7d4e146f
ED		 2680 } else if (IS_HASWELL(dev)) {
2681 /* Share interrupts handling with IVB */
2682 dev->driver->irq_handler = ivybridge_irq_handler;
2683 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2684 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2685 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2686 dev->driver->enable_vblank = ivybridge_enable_vblank;
2687 dev->driver->disable_vblank = ivybridge_disable_vblank;
f71d4af4
JB		 2688 } else if (HAS_PCH_SPLIT(dev)) {
2689 dev->driver->irq_handler = ironlake_irq_handler;
2690 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2691 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2692 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2693 dev->driver->enable_vblank = ironlake_enable_vblank;
2694 dev->driver->disable_vblank = ironlake_disable_vblank;
2695 } else {
c2798b19
CW		 2696 if (INTEL_INFO(dev)->gen == 2) {
2697 dev->driver->irq_preinstall = i8xx_irq_preinstall;
2698 dev->driver->irq_postinstall = i8xx_irq_postinstall;
2699 dev->driver->irq_handler = i8xx_irq_handler;
2700 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5
CW		 2701 } else if (INTEL_INFO(dev)->gen == 3) {
2702 dev->driver->irq_preinstall = i915_irq_preinstall;
2703 dev->driver->irq_postinstall = i915_irq_postinstall;
2704 dev->driver->irq_uninstall = i915_irq_uninstall;
2705 dev->driver->irq_handler = i915_irq_handler;
c2798b19 2706 } else {
a266c7d5
CW		 2707 dev->driver->irq_preinstall = i965_irq_preinstall;
2708 dev->driver->irq_postinstall = i965_irq_postinstall;
2709 dev->driver->irq_uninstall = i965_irq_uninstall;
2710 dev->driver->irq_handler = i965_irq_handler;
c2798b19 2711 }
f71d4af4
JB		 2712 dev->driver->enable_vblank = i915_enable_vblank;
2713 dev->driver->disable_vblank = i915_disable_vblank;
2714 }
2715}
Ubuntu Eoan Linux kernel mirror