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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
63eeaf38 | 29 | #include <linux/sysrq.h> |
1da177e4 LT |
30 | #include "drmP.h" |
31 | #include "drm.h" | |
32 | #include "i915_drm.h" | |
33 | #include "i915_drv.h" | |
79e53945 | 34 | #include "intel_drv.h" |
1da177e4 | 35 | |
1da177e4 | 36 | #define MAX_NOPID ((u32)~0) |
1da177e4 | 37 | |
7c463586 KP |
38 | /** |
39 | * Interrupts that are always left unmasked. | |
40 | * | |
41 | * Since pipe events are edge-triggered from the PIPESTAT register to IIR, | |
42 | * we leave them always unmasked in IMR and then control enabling them through | |
43 | * PIPESTAT alone. | |
44 | */ | |
63eeaf38 JB |
45 | #define I915_INTERRUPT_ENABLE_FIX (I915_ASLE_INTERRUPT | \ |
46 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ | |
47 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \ | |
48 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
7c463586 KP |
49 | |
50 | /** Interrupts that we mask and unmask at runtime. */ | |
51 | #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT) | |
52 | ||
79e53945 JB |
53 | #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\ |
54 | PIPE_VBLANK_INTERRUPT_STATUS) | |
55 | ||
56 | #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\ | |
57 | PIPE_VBLANK_INTERRUPT_ENABLE) | |
58 | ||
59 | #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \ | |
60 | DRM_I915_VBLANK_PIPE_B) | |
61 | ||
036a4a7d ZW |
62 | void |
63 | igdng_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) | |
64 | { | |
65 | if ((dev_priv->gt_irq_mask_reg & mask) != 0) { | |
66 | dev_priv->gt_irq_mask_reg &= ~mask; | |
67 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); | |
68 | (void) I915_READ(GTIMR); | |
69 | } | |
70 | } | |
71 | ||
72 | static inline void | |
73 | igdng_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) | |
74 | { | |
75 | if ((dev_priv->gt_irq_mask_reg & mask) != mask) { | |
76 | dev_priv->gt_irq_mask_reg |= mask; | |
77 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); | |
78 | (void) I915_READ(GTIMR); | |
79 | } | |
80 | } | |
81 | ||
82 | /* For display hotplug interrupt */ | |
83 | void | |
84 | igdng_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) | |
85 | { | |
86 | if ((dev_priv->irq_mask_reg & mask) != 0) { | |
87 | dev_priv->irq_mask_reg &= ~mask; | |
88 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); | |
89 | (void) I915_READ(DEIMR); | |
90 | } | |
91 | } | |
92 | ||
93 | static inline void | |
94 | igdng_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) | |
95 | { | |
96 | if ((dev_priv->irq_mask_reg & mask) != mask) { | |
97 | dev_priv->irq_mask_reg |= mask; | |
98 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); | |
99 | (void) I915_READ(DEIMR); | |
100 | } | |
101 | } | |
102 | ||
8ee1c3db | 103 | void |
ed4cb414 EA |
104 | i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
105 | { | |
106 | if ((dev_priv->irq_mask_reg & mask) != 0) { | |
107 | dev_priv->irq_mask_reg &= ~mask; | |
108 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
109 | (void) I915_READ(IMR); | |
110 | } | |
111 | } | |
112 | ||
113 | static inline void | |
114 | i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) | |
115 | { | |
116 | if ((dev_priv->irq_mask_reg & mask) != mask) { | |
117 | dev_priv->irq_mask_reg |= mask; | |
118 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
119 | (void) I915_READ(IMR); | |
120 | } | |
121 | } | |
122 | ||
7c463586 KP |
123 | static inline u32 |
124 | i915_pipestat(int pipe) | |
125 | { | |
126 | if (pipe == 0) | |
127 | return PIPEASTAT; | |
128 | if (pipe == 1) | |
129 | return PIPEBSTAT; | |
9c84ba4e | 130 | BUG(); |
7c463586 KP |
131 | } |
132 | ||
133 | void | |
134 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
135 | { | |
136 | if ((dev_priv->pipestat[pipe] & mask) != mask) { | |
137 | u32 reg = i915_pipestat(pipe); | |
138 | ||
139 | dev_priv->pipestat[pipe] |= mask; | |
140 | /* Enable the interrupt, clear any pending status */ | |
141 | I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); | |
142 | (void) I915_READ(reg); | |
143 | } | |
144 | } | |
145 | ||
146 | void | |
147 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
148 | { | |
149 | if ((dev_priv->pipestat[pipe] & mask) != 0) { | |
150 | u32 reg = i915_pipestat(pipe); | |
151 | ||
152 | dev_priv->pipestat[pipe] &= ~mask; | |
153 | I915_WRITE(reg, dev_priv->pipestat[pipe]); | |
154 | (void) I915_READ(reg); | |
155 | } | |
156 | } | |
157 | ||
0a3e67a4 JB |
158 | /** |
159 | * i915_pipe_enabled - check if a pipe is enabled | |
160 | * @dev: DRM device | |
161 | * @pipe: pipe to check | |
162 | * | |
163 | * Reading certain registers when the pipe is disabled can hang the chip. | |
164 | * Use this routine to make sure the PLL is running and the pipe is active | |
165 | * before reading such registers if unsure. | |
166 | */ | |
167 | static int | |
168 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
169 | { | |
170 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
171 | unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF; | |
172 | ||
173 | if (I915_READ(pipeconf) & PIPEACONF_ENABLE) | |
174 | return 1; | |
175 | ||
176 | return 0; | |
177 | } | |
178 | ||
42f52ef8 KP |
179 | /* Called from drm generic code, passed a 'crtc', which |
180 | * we use as a pipe index | |
181 | */ | |
182 | u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
183 | { |
184 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
185 | unsigned long high_frame; | |
186 | unsigned long low_frame; | |
187 | u32 high1, high2, low, count; | |
0a3e67a4 | 188 | |
0a3e67a4 JB |
189 | high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH; |
190 | low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL; | |
191 | ||
192 | if (!i915_pipe_enabled(dev, pipe)) { | |
193 | DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe); | |
194 | return 0; | |
195 | } | |
196 | ||
197 | /* | |
198 | * High & low register fields aren't synchronized, so make sure | |
199 | * we get a low value that's stable across two reads of the high | |
200 | * register. | |
201 | */ | |
202 | do { | |
203 | high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> | |
204 | PIPE_FRAME_HIGH_SHIFT); | |
205 | low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >> | |
206 | PIPE_FRAME_LOW_SHIFT); | |
207 | high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> | |
208 | PIPE_FRAME_HIGH_SHIFT); | |
209 | } while (high1 != high2); | |
210 | ||
211 | count = (high1 << 8) | low; | |
212 | ||
213 | return count; | |
214 | } | |
215 | ||
9880b7a5 JB |
216 | u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
217 | { | |
218 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
219 | int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45; | |
220 | ||
221 | if (!i915_pipe_enabled(dev, pipe)) { | |
222 | DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe); | |
223 | return 0; | |
224 | } | |
225 | ||
226 | return I915_READ(reg); | |
227 | } | |
228 | ||
5ca58282 JB |
229 | /* |
230 | * Handle hotplug events outside the interrupt handler proper. | |
231 | */ | |
232 | static void i915_hotplug_work_func(struct work_struct *work) | |
233 | { | |
234 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
235 | hotplug_work); | |
236 | struct drm_device *dev = dev_priv->dev; | |
c31c4ba3 KP |
237 | struct drm_mode_config *mode_config = &dev->mode_config; |
238 | struct drm_connector *connector; | |
239 | ||
240 | if (mode_config->num_connector) { | |
241 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
242 | struct intel_output *intel_output = to_intel_output(connector); | |
243 | ||
244 | if (intel_output->hot_plug) | |
245 | (*intel_output->hot_plug) (intel_output); | |
246 | } | |
247 | } | |
5ca58282 JB |
248 | /* Just fire off a uevent and let userspace tell us what to do */ |
249 | drm_sysfs_hotplug_event(dev); | |
250 | } | |
251 | ||
036a4a7d ZW |
252 | irqreturn_t igdng_irq_handler(struct drm_device *dev) |
253 | { | |
254 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
255 | int ret = IRQ_NONE; | |
256 | u32 de_iir, gt_iir; | |
257 | u32 new_de_iir, new_gt_iir; | |
258 | struct drm_i915_master_private *master_priv; | |
259 | ||
260 | de_iir = I915_READ(DEIIR); | |
261 | gt_iir = I915_READ(GTIIR); | |
262 | ||
263 | for (;;) { | |
264 | if (de_iir == 0 && gt_iir == 0) | |
265 | break; | |
266 | ||
267 | ret = IRQ_HANDLED; | |
268 | ||
269 | I915_WRITE(DEIIR, de_iir); | |
270 | new_de_iir = I915_READ(DEIIR); | |
271 | I915_WRITE(GTIIR, gt_iir); | |
272 | new_gt_iir = I915_READ(GTIIR); | |
273 | ||
274 | if (dev->primary->master) { | |
275 | master_priv = dev->primary->master->driver_priv; | |
276 | if (master_priv->sarea_priv) | |
277 | master_priv->sarea_priv->last_dispatch = | |
278 | READ_BREADCRUMB(dev_priv); | |
279 | } | |
280 | ||
281 | if (gt_iir & GT_USER_INTERRUPT) { | |
282 | dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev); | |
283 | DRM_WAKEUP(&dev_priv->irq_queue); | |
284 | } | |
285 | ||
286 | de_iir = new_de_iir; | |
287 | gt_iir = new_gt_iir; | |
288 | } | |
289 | ||
290 | return ret; | |
291 | } | |
292 | ||
63eeaf38 JB |
293 | static void i915_capture_error_state(struct drm_device *dev) |
294 | { | |
295 | struct drm_i915_private *dev_priv = dev->dev_private; | |
296 | struct drm_i915_error_state *error; | |
297 | unsigned long flags; | |
298 | ||
299 | spin_lock_irqsave(&dev_priv->error_lock, flags); | |
300 | if (dev_priv->first_error) | |
301 | goto out; | |
302 | ||
303 | error = kmalloc(sizeof(*error), GFP_ATOMIC); | |
304 | if (!error) { | |
305 | DRM_DEBUG("out ot memory, not capturing error state\n"); | |
306 | goto out; | |
307 | } | |
308 | ||
309 | error->eir = I915_READ(EIR); | |
310 | error->pgtbl_er = I915_READ(PGTBL_ER); | |
311 | error->pipeastat = I915_READ(PIPEASTAT); | |
312 | error->pipebstat = I915_READ(PIPEBSTAT); | |
313 | error->instpm = I915_READ(INSTPM); | |
314 | if (!IS_I965G(dev)) { | |
315 | error->ipeir = I915_READ(IPEIR); | |
316 | error->ipehr = I915_READ(IPEHR); | |
317 | error->instdone = I915_READ(INSTDONE); | |
318 | error->acthd = I915_READ(ACTHD); | |
319 | } else { | |
320 | error->ipeir = I915_READ(IPEIR_I965); | |
321 | error->ipehr = I915_READ(IPEHR_I965); | |
322 | error->instdone = I915_READ(INSTDONE_I965); | |
323 | error->instps = I915_READ(INSTPS); | |
324 | error->instdone1 = I915_READ(INSTDONE1); | |
325 | error->acthd = I915_READ(ACTHD_I965); | |
326 | } | |
327 | ||
328 | dev_priv->first_error = error; | |
329 | ||
330 | out: | |
331 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); | |
332 | } | |
333 | ||
1da177e4 LT |
334 | irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) |
335 | { | |
84b1fd10 | 336 | struct drm_device *dev = (struct drm_device *) arg; |
1da177e4 | 337 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 338 | struct drm_i915_master_private *master_priv; |
cdfbc41f EA |
339 | u32 iir, new_iir; |
340 | u32 pipea_stats, pipeb_stats; | |
05eff845 KP |
341 | u32 vblank_status; |
342 | u32 vblank_enable; | |
0a3e67a4 | 343 | int vblank = 0; |
7c463586 | 344 | unsigned long irqflags; |
05eff845 KP |
345 | int irq_received; |
346 | int ret = IRQ_NONE; | |
6e5fca53 | 347 | |
630681d9 EA |
348 | atomic_inc(&dev_priv->irq_received); |
349 | ||
036a4a7d ZW |
350 | if (IS_IGDNG(dev)) |
351 | return igdng_irq_handler(dev); | |
352 | ||
ed4cb414 | 353 | iir = I915_READ(IIR); |
a6b54f3f | 354 | |
05eff845 KP |
355 | if (IS_I965G(dev)) { |
356 | vblank_status = I915_START_VBLANK_INTERRUPT_STATUS; | |
357 | vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE; | |
358 | } else { | |
359 | vblank_status = I915_VBLANK_INTERRUPT_STATUS; | |
360 | vblank_enable = I915_VBLANK_INTERRUPT_ENABLE; | |
361 | } | |
af6061af | 362 | |
05eff845 KP |
363 | for (;;) { |
364 | irq_received = iir != 0; | |
365 | ||
366 | /* Can't rely on pipestat interrupt bit in iir as it might | |
367 | * have been cleared after the pipestat interrupt was received. | |
368 | * It doesn't set the bit in iir again, but it still produces | |
369 | * interrupts (for non-MSI). | |
370 | */ | |
371 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); | |
372 | pipea_stats = I915_READ(PIPEASTAT); | |
373 | pipeb_stats = I915_READ(PIPEBSTAT); | |
79e53945 | 374 | |
cdfbc41f EA |
375 | /* |
376 | * Clear the PIPE(A|B)STAT regs before the IIR | |
377 | */ | |
05eff845 | 378 | if (pipea_stats & 0x8000ffff) { |
7662c8bd SL |
379 | if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS) |
380 | DRM_DEBUG("pipe a underrun\n"); | |
cdfbc41f | 381 | I915_WRITE(PIPEASTAT, pipea_stats); |
05eff845 | 382 | irq_received = 1; |
cdfbc41f | 383 | } |
1da177e4 | 384 | |
05eff845 | 385 | if (pipeb_stats & 0x8000ffff) { |
7662c8bd SL |
386 | if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS) |
387 | DRM_DEBUG("pipe b underrun\n"); | |
cdfbc41f | 388 | I915_WRITE(PIPEBSTAT, pipeb_stats); |
05eff845 | 389 | irq_received = 1; |
cdfbc41f | 390 | } |
05eff845 KP |
391 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
392 | ||
393 | if (!irq_received) | |
394 | break; | |
395 | ||
396 | ret = IRQ_HANDLED; | |
8ee1c3db | 397 | |
5ca58282 JB |
398 | /* Consume port. Then clear IIR or we'll miss events */ |
399 | if ((I915_HAS_HOTPLUG(dev)) && | |
400 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { | |
401 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
402 | ||
403 | DRM_DEBUG("hotplug event received, stat 0x%08x\n", | |
404 | hotplug_status); | |
405 | if (hotplug_status & dev_priv->hotplug_supported_mask) | |
406 | schedule_work(&dev_priv->hotplug_work); | |
407 | ||
408 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
409 | I915_READ(PORT_HOTPLUG_STAT); | |
410 | } | |
411 | ||
63eeaf38 JB |
412 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) { |
413 | u32 eir = I915_READ(EIR); | |
414 | ||
415 | i915_capture_error_state(dev); | |
416 | ||
417 | printk(KERN_ERR "render error detected, EIR: 0x%08x\n", | |
418 | eir); | |
419 | if (eir & I915_ERROR_PAGE_TABLE) { | |
420 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
421 | printk(KERN_ERR "page table error\n"); | |
422 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", | |
423 | pgtbl_err); | |
424 | I915_WRITE(PGTBL_ER, pgtbl_err); | |
425 | (void)I915_READ(PGTBL_ER); | |
426 | } | |
427 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
428 | printk(KERN_ERR "memory refresh error\n"); | |
429 | printk(KERN_ERR "PIPEASTAT: 0x%08x\n", | |
430 | pipea_stats); | |
431 | printk(KERN_ERR "PIPEBSTAT: 0x%08x\n", | |
432 | pipeb_stats); | |
433 | /* pipestat has already been acked */ | |
434 | } | |
435 | if (eir & I915_ERROR_INSTRUCTION) { | |
436 | printk(KERN_ERR "instruction error\n"); | |
437 | printk(KERN_ERR " INSTPM: 0x%08x\n", | |
438 | I915_READ(INSTPM)); | |
439 | if (!IS_I965G(dev)) { | |
440 | u32 ipeir = I915_READ(IPEIR); | |
441 | ||
442 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
443 | I915_READ(IPEIR)); | |
444 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
445 | I915_READ(IPEHR)); | |
446 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
447 | I915_READ(INSTDONE)); | |
448 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
449 | I915_READ(ACTHD)); | |
450 | I915_WRITE(IPEIR, ipeir); | |
451 | (void)I915_READ(IPEIR); | |
452 | } else { | |
453 | u32 ipeir = I915_READ(IPEIR_I965); | |
454 | ||
455 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
456 | I915_READ(IPEIR_I965)); | |
457 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
458 | I915_READ(IPEHR_I965)); | |
459 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
460 | I915_READ(INSTDONE_I965)); | |
461 | printk(KERN_ERR " INSTPS: 0x%08x\n", | |
462 | I915_READ(INSTPS)); | |
463 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", | |
464 | I915_READ(INSTDONE1)); | |
465 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
466 | I915_READ(ACTHD_I965)); | |
467 | I915_WRITE(IPEIR_I965, ipeir); | |
468 | (void)I915_READ(IPEIR_I965); | |
469 | } | |
470 | } | |
471 | ||
472 | I915_WRITE(EIR, eir); | |
473 | (void)I915_READ(EIR); | |
474 | eir = I915_READ(EIR); | |
475 | if (eir) { | |
476 | /* | |
477 | * some errors might have become stuck, | |
478 | * mask them. | |
479 | */ | |
480 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
481 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
482 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
483 | } | |
484 | } | |
485 | ||
cdfbc41f EA |
486 | I915_WRITE(IIR, iir); |
487 | new_iir = I915_READ(IIR); /* Flush posted writes */ | |
7c463586 | 488 | |
7c1c2871 DA |
489 | if (dev->primary->master) { |
490 | master_priv = dev->primary->master->driver_priv; | |
491 | if (master_priv->sarea_priv) | |
492 | master_priv->sarea_priv->last_dispatch = | |
493 | READ_BREADCRUMB(dev_priv); | |
494 | } | |
0a3e67a4 | 495 | |
cdfbc41f EA |
496 | if (iir & I915_USER_INTERRUPT) { |
497 | dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev); | |
498 | DRM_WAKEUP(&dev_priv->irq_queue); | |
499 | } | |
673a394b | 500 | |
05eff845 | 501 | if (pipea_stats & vblank_status) { |
cdfbc41f EA |
502 | vblank++; |
503 | drm_handle_vblank(dev, 0); | |
504 | } | |
7c463586 | 505 | |
05eff845 | 506 | if (pipeb_stats & vblank_status) { |
cdfbc41f EA |
507 | vblank++; |
508 | drm_handle_vblank(dev, 1); | |
509 | } | |
7c463586 | 510 | |
cdfbc41f EA |
511 | if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) || |
512 | (iir & I915_ASLE_INTERRUPT)) | |
513 | opregion_asle_intr(dev); | |
514 | ||
515 | /* With MSI, interrupts are only generated when iir | |
516 | * transitions from zero to nonzero. If another bit got | |
517 | * set while we were handling the existing iir bits, then | |
518 | * we would never get another interrupt. | |
519 | * | |
520 | * This is fine on non-MSI as well, as if we hit this path | |
521 | * we avoid exiting the interrupt handler only to generate | |
522 | * another one. | |
523 | * | |
524 | * Note that for MSI this could cause a stray interrupt report | |
525 | * if an interrupt landed in the time between writing IIR and | |
526 | * the posting read. This should be rare enough to never | |
527 | * trigger the 99% of 100,000 interrupts test for disabling | |
528 | * stray interrupts. | |
529 | */ | |
530 | iir = new_iir; | |
05eff845 | 531 | } |
0a3e67a4 | 532 | |
05eff845 | 533 | return ret; |
1da177e4 LT |
534 | } |
535 | ||
af6061af | 536 | static int i915_emit_irq(struct drm_device * dev) |
1da177e4 LT |
537 | { |
538 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 539 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 LT |
540 | RING_LOCALS; |
541 | ||
542 | i915_kernel_lost_context(dev); | |
543 | ||
3e684eae | 544 | DRM_DEBUG("\n"); |
1da177e4 | 545 | |
c99b058f | 546 | dev_priv->counter++; |
c29b669c | 547 | if (dev_priv->counter > 0x7FFFFFFFUL) |
c99b058f | 548 | dev_priv->counter = 1; |
7c1c2871 DA |
549 | if (master_priv->sarea_priv) |
550 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; | |
c29b669c | 551 | |
0baf823a | 552 | BEGIN_LP_RING(4); |
585fb111 | 553 | OUT_RING(MI_STORE_DWORD_INDEX); |
0baf823a | 554 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
c29b669c | 555 | OUT_RING(dev_priv->counter); |
585fb111 | 556 | OUT_RING(MI_USER_INTERRUPT); |
1da177e4 | 557 | ADVANCE_LP_RING(); |
bc5f4523 | 558 | |
c29b669c | 559 | return dev_priv->counter; |
1da177e4 LT |
560 | } |
561 | ||
673a394b | 562 | void i915_user_irq_get(struct drm_device *dev) |
ed4cb414 EA |
563 | { |
564 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 565 | unsigned long irqflags; |
ed4cb414 | 566 | |
e9d21d7f | 567 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
036a4a7d ZW |
568 | if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) { |
569 | if (IS_IGDNG(dev)) | |
570 | igdng_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT); | |
571 | else | |
572 | i915_enable_irq(dev_priv, I915_USER_INTERRUPT); | |
573 | } | |
e9d21d7f | 574 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
ed4cb414 EA |
575 | } |
576 | ||
0a3e67a4 | 577 | void i915_user_irq_put(struct drm_device *dev) |
ed4cb414 EA |
578 | { |
579 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 580 | unsigned long irqflags; |
ed4cb414 | 581 | |
e9d21d7f | 582 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
ed4cb414 | 583 | BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0); |
036a4a7d ZW |
584 | if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) { |
585 | if (IS_IGDNG(dev)) | |
586 | igdng_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT); | |
587 | else | |
588 | i915_disable_irq(dev_priv, I915_USER_INTERRUPT); | |
589 | } | |
e9d21d7f | 590 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
ed4cb414 EA |
591 | } |
592 | ||
84b1fd10 | 593 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) |
1da177e4 LT |
594 | { |
595 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
7c1c2871 | 596 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 LT |
597 | int ret = 0; |
598 | ||
3e684eae | 599 | DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr, |
1da177e4 LT |
600 | READ_BREADCRUMB(dev_priv)); |
601 | ||
ed4cb414 | 602 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { |
7c1c2871 DA |
603 | if (master_priv->sarea_priv) |
604 | master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); | |
1da177e4 | 605 | return 0; |
ed4cb414 | 606 | } |
1da177e4 | 607 | |
7c1c2871 DA |
608 | if (master_priv->sarea_priv) |
609 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1da177e4 | 610 | |
ed4cb414 | 611 | i915_user_irq_get(dev); |
1da177e4 LT |
612 | DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ, |
613 | READ_BREADCRUMB(dev_priv) >= irq_nr); | |
ed4cb414 | 614 | i915_user_irq_put(dev); |
1da177e4 | 615 | |
20caafa6 | 616 | if (ret == -EBUSY) { |
3e684eae | 617 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", |
1da177e4 LT |
618 | READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); |
619 | } | |
620 | ||
af6061af DA |
621 | return ret; |
622 | } | |
623 | ||
1da177e4 LT |
624 | /* Needs the lock as it touches the ring. |
625 | */ | |
c153f45f EA |
626 | int i915_irq_emit(struct drm_device *dev, void *data, |
627 | struct drm_file *file_priv) | |
1da177e4 | 628 | { |
1da177e4 | 629 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 630 | drm_i915_irq_emit_t *emit = data; |
1da177e4 LT |
631 | int result; |
632 | ||
07f4f8bf | 633 | if (!dev_priv || !dev_priv->ring.virtual_start) { |
3e684eae | 634 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 635 | return -EINVAL; |
1da177e4 | 636 | } |
299eb93c EA |
637 | |
638 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); | |
639 | ||
546b0974 | 640 | mutex_lock(&dev->struct_mutex); |
1da177e4 | 641 | result = i915_emit_irq(dev); |
546b0974 | 642 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 643 | |
c153f45f | 644 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { |
1da177e4 | 645 | DRM_ERROR("copy_to_user\n"); |
20caafa6 | 646 | return -EFAULT; |
1da177e4 LT |
647 | } |
648 | ||
649 | return 0; | |
650 | } | |
651 | ||
652 | /* Doesn't need the hardware lock. | |
653 | */ | |
c153f45f EA |
654 | int i915_irq_wait(struct drm_device *dev, void *data, |
655 | struct drm_file *file_priv) | |
1da177e4 | 656 | { |
1da177e4 | 657 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 658 | drm_i915_irq_wait_t *irqwait = data; |
1da177e4 LT |
659 | |
660 | if (!dev_priv) { | |
3e684eae | 661 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 662 | return -EINVAL; |
1da177e4 LT |
663 | } |
664 | ||
c153f45f | 665 | return i915_wait_irq(dev, irqwait->irq_seq); |
1da177e4 LT |
666 | } |
667 | ||
42f52ef8 KP |
668 | /* Called from drm generic code, passed 'crtc' which |
669 | * we use as a pipe index | |
670 | */ | |
671 | int i915_enable_vblank(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
672 | { |
673 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 674 | unsigned long irqflags; |
71e0ffa5 JB |
675 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; |
676 | u32 pipeconf; | |
677 | ||
678 | pipeconf = I915_READ(pipeconf_reg); | |
679 | if (!(pipeconf & PIPEACONF_ENABLE)) | |
680 | return -EINVAL; | |
0a3e67a4 | 681 | |
036a4a7d ZW |
682 | if (IS_IGDNG(dev)) |
683 | return 0; | |
684 | ||
e9d21d7f | 685 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
e9d21d7f | 686 | if (IS_I965G(dev)) |
7c463586 KP |
687 | i915_enable_pipestat(dev_priv, pipe, |
688 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 689 | else |
7c463586 KP |
690 | i915_enable_pipestat(dev_priv, pipe, |
691 | PIPE_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 692 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
0a3e67a4 JB |
693 | return 0; |
694 | } | |
695 | ||
42f52ef8 KP |
696 | /* Called from drm generic code, passed 'crtc' which |
697 | * we use as a pipe index | |
698 | */ | |
699 | void i915_disable_vblank(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
700 | { |
701 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 702 | unsigned long irqflags; |
0a3e67a4 | 703 | |
036a4a7d ZW |
704 | if (IS_IGDNG(dev)) |
705 | return; | |
706 | ||
e9d21d7f | 707 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
7c463586 KP |
708 | i915_disable_pipestat(dev_priv, pipe, |
709 | PIPE_VBLANK_INTERRUPT_ENABLE | | |
710 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 711 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
0a3e67a4 JB |
712 | } |
713 | ||
79e53945 JB |
714 | void i915_enable_interrupt (struct drm_device *dev) |
715 | { | |
716 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e170b030 ZW |
717 | |
718 | if (!IS_IGDNG(dev)) | |
719 | opregion_enable_asle(dev); | |
79e53945 JB |
720 | dev_priv->irq_enabled = 1; |
721 | } | |
722 | ||
723 | ||
702880f2 DA |
724 | /* Set the vblank monitor pipe |
725 | */ | |
c153f45f EA |
726 | int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
727 | struct drm_file *file_priv) | |
702880f2 | 728 | { |
702880f2 | 729 | drm_i915_private_t *dev_priv = dev->dev_private; |
702880f2 DA |
730 | |
731 | if (!dev_priv) { | |
3e684eae | 732 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 733 | return -EINVAL; |
702880f2 DA |
734 | } |
735 | ||
5b51694a | 736 | return 0; |
702880f2 DA |
737 | } |
738 | ||
c153f45f EA |
739 | int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
740 | struct drm_file *file_priv) | |
702880f2 | 741 | { |
702880f2 | 742 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 743 | drm_i915_vblank_pipe_t *pipe = data; |
702880f2 DA |
744 | |
745 | if (!dev_priv) { | |
3e684eae | 746 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 747 | return -EINVAL; |
702880f2 DA |
748 | } |
749 | ||
0a3e67a4 | 750 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
c153f45f | 751 | |
702880f2 DA |
752 | return 0; |
753 | } | |
754 | ||
a6b54f3f MD |
755 | /** |
756 | * Schedule buffer swap at given vertical blank. | |
757 | */ | |
c153f45f EA |
758 | int i915_vblank_swap(struct drm_device *dev, void *data, |
759 | struct drm_file *file_priv) | |
a6b54f3f | 760 | { |
bd95e0a4 EA |
761 | /* The delayed swap mechanism was fundamentally racy, and has been |
762 | * removed. The model was that the client requested a delayed flip/swap | |
763 | * from the kernel, then waited for vblank before continuing to perform | |
764 | * rendering. The problem was that the kernel might wake the client | |
765 | * up before it dispatched the vblank swap (since the lock has to be | |
766 | * held while touching the ringbuffer), in which case the client would | |
767 | * clear and start the next frame before the swap occurred, and | |
768 | * flicker would occur in addition to likely missing the vblank. | |
769 | * | |
770 | * In the absence of this ioctl, userland falls back to a correct path | |
771 | * of waiting for a vblank, then dispatching the swap on its own. | |
772 | * Context switching to userland and back is plenty fast enough for | |
773 | * meeting the requirements of vblank swapping. | |
0a3e67a4 | 774 | */ |
bd95e0a4 | 775 | return -EINVAL; |
a6b54f3f MD |
776 | } |
777 | ||
1da177e4 LT |
778 | /* drm_dma.h hooks |
779 | */ | |
036a4a7d ZW |
780 | static void igdng_irq_preinstall(struct drm_device *dev) |
781 | { | |
782 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
783 | ||
784 | I915_WRITE(HWSTAM, 0xeffe); | |
785 | ||
786 | /* XXX hotplug from PCH */ | |
787 | ||
788 | I915_WRITE(DEIMR, 0xffffffff); | |
789 | I915_WRITE(DEIER, 0x0); | |
790 | (void) I915_READ(DEIER); | |
791 | ||
792 | /* and GT */ | |
793 | I915_WRITE(GTIMR, 0xffffffff); | |
794 | I915_WRITE(GTIER, 0x0); | |
795 | (void) I915_READ(GTIER); | |
796 | } | |
797 | ||
798 | static int igdng_irq_postinstall(struct drm_device *dev) | |
799 | { | |
800 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
801 | /* enable kind of interrupts always enabled */ | |
802 | u32 display_mask = DE_MASTER_IRQ_CONTROL /*| DE_PCH_EVENT */; | |
803 | u32 render_mask = GT_USER_INTERRUPT; | |
804 | ||
805 | dev_priv->irq_mask_reg = ~display_mask; | |
806 | dev_priv->de_irq_enable_reg = display_mask; | |
807 | ||
808 | /* should always can generate irq */ | |
809 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
810 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); | |
811 | I915_WRITE(DEIER, dev_priv->de_irq_enable_reg); | |
812 | (void) I915_READ(DEIER); | |
813 | ||
814 | /* user interrupt should be enabled, but masked initial */ | |
815 | dev_priv->gt_irq_mask_reg = 0xffffffff; | |
816 | dev_priv->gt_irq_enable_reg = render_mask; | |
817 | ||
818 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
819 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); | |
820 | I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg); | |
821 | (void) I915_READ(GTIER); | |
822 | ||
823 | return 0; | |
824 | } | |
825 | ||
84b1fd10 | 826 | void i915_driver_irq_preinstall(struct drm_device * dev) |
1da177e4 LT |
827 | { |
828 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
829 | ||
79e53945 JB |
830 | atomic_set(&dev_priv->irq_received, 0); |
831 | ||
036a4a7d ZW |
832 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); |
833 | ||
834 | if (IS_IGDNG(dev)) { | |
835 | igdng_irq_preinstall(dev); | |
836 | return; | |
837 | } | |
838 | ||
5ca58282 JB |
839 | if (I915_HAS_HOTPLUG(dev)) { |
840 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
841 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
842 | } | |
843 | ||
0a3e67a4 | 844 | I915_WRITE(HWSTAM, 0xeffe); |
7c463586 KP |
845 | I915_WRITE(PIPEASTAT, 0); |
846 | I915_WRITE(PIPEBSTAT, 0); | |
0a3e67a4 | 847 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 848 | I915_WRITE(IER, 0x0); |
7c463586 | 849 | (void) I915_READ(IER); |
1da177e4 LT |
850 | } |
851 | ||
0a3e67a4 | 852 | int i915_driver_irq_postinstall(struct drm_device *dev) |
1da177e4 LT |
853 | { |
854 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
5ca58282 | 855 | u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR; |
63eeaf38 | 856 | u32 error_mask; |
0a3e67a4 | 857 | |
036a4a7d ZW |
858 | DRM_INIT_WAITQUEUE(&dev_priv->irq_queue); |
859 | ||
0a3e67a4 | 860 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
0a3e67a4 | 861 | |
036a4a7d ZW |
862 | if (IS_IGDNG(dev)) |
863 | return igdng_irq_postinstall(dev); | |
864 | ||
7c463586 KP |
865 | /* Unmask the interrupts that we always want on. */ |
866 | dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX; | |
867 | ||
868 | dev_priv->pipestat[0] = 0; | |
869 | dev_priv->pipestat[1] = 0; | |
870 | ||
5ca58282 JB |
871 | if (I915_HAS_HOTPLUG(dev)) { |
872 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
873 | ||
874 | /* Leave other bits alone */ | |
875 | hotplug_en |= HOTPLUG_EN_MASK; | |
876 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
877 | ||
878 | dev_priv->hotplug_supported_mask = CRT_HOTPLUG_INT_STATUS | | |
879 | TV_HOTPLUG_INT_STATUS | SDVOC_HOTPLUG_INT_STATUS | | |
880 | SDVOB_HOTPLUG_INT_STATUS; | |
881 | if (IS_G4X(dev)) { | |
882 | dev_priv->hotplug_supported_mask |= | |
883 | HDMIB_HOTPLUG_INT_STATUS | | |
884 | HDMIC_HOTPLUG_INT_STATUS | | |
885 | HDMID_HOTPLUG_INT_STATUS; | |
886 | } | |
887 | /* Enable in IER... */ | |
888 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
889 | /* and unmask in IMR */ | |
890 | i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT); | |
891 | } | |
892 | ||
63eeaf38 JB |
893 | /* |
894 | * Enable some error detection, note the instruction error mask | |
895 | * bit is reserved, so we leave it masked. | |
896 | */ | |
897 | if (IS_G4X(dev)) { | |
898 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
899 | GM45_ERROR_MEM_PRIV | | |
900 | GM45_ERROR_CP_PRIV | | |
901 | I915_ERROR_MEMORY_REFRESH); | |
902 | } else { | |
903 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
904 | I915_ERROR_MEMORY_REFRESH); | |
905 | } | |
906 | I915_WRITE(EMR, error_mask); | |
907 | ||
7c463586 KP |
908 | /* Disable pipe interrupt enables, clear pending pipe status */ |
909 | I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); | |
910 | I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); | |
911 | /* Clear pending interrupt status */ | |
912 | I915_WRITE(IIR, I915_READ(IIR)); | |
8ee1c3db | 913 | |
5ca58282 | 914 | I915_WRITE(IER, enable_mask); |
7c463586 | 915 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
ed4cb414 EA |
916 | (void) I915_READ(IER); |
917 | ||
8ee1c3db | 918 | opregion_enable_asle(dev); |
0a3e67a4 JB |
919 | |
920 | return 0; | |
1da177e4 LT |
921 | } |
922 | ||
036a4a7d ZW |
923 | static void igdng_irq_uninstall(struct drm_device *dev) |
924 | { | |
925 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
926 | I915_WRITE(HWSTAM, 0xffffffff); | |
927 | ||
928 | I915_WRITE(DEIMR, 0xffffffff); | |
929 | I915_WRITE(DEIER, 0x0); | |
930 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
931 | ||
932 | I915_WRITE(GTIMR, 0xffffffff); | |
933 | I915_WRITE(GTIER, 0x0); | |
934 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
935 | } | |
936 | ||
84b1fd10 | 937 | void i915_driver_irq_uninstall(struct drm_device * dev) |
1da177e4 LT |
938 | { |
939 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
91e3738e | 940 | |
1da177e4 LT |
941 | if (!dev_priv) |
942 | return; | |
943 | ||
0a3e67a4 JB |
944 | dev_priv->vblank_pipe = 0; |
945 | ||
036a4a7d ZW |
946 | if (IS_IGDNG(dev)) { |
947 | igdng_irq_uninstall(dev); | |
948 | return; | |
949 | } | |
950 | ||
5ca58282 JB |
951 | if (I915_HAS_HOTPLUG(dev)) { |
952 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
953 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
954 | } | |
955 | ||
0a3e67a4 | 956 | I915_WRITE(HWSTAM, 0xffffffff); |
7c463586 KP |
957 | I915_WRITE(PIPEASTAT, 0); |
958 | I915_WRITE(PIPEBSTAT, 0); | |
0a3e67a4 | 959 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 960 | I915_WRITE(IER, 0x0); |
af6061af | 961 | |
7c463586 KP |
962 | I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); |
963 | I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); | |
964 | I915_WRITE(IIR, I915_READ(IIR)); | |
1da177e4 | 965 | } |