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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
63eeaf38 | 31 | #include <linux/sysrq.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
b2c88f5b | 33 | #include <linux/circ_buf.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/i915_drm.h> | |
1da177e4 | 36 | #include "i915_drv.h" |
1c5d22f7 | 37 | #include "i915_trace.h" |
79e53945 | 38 | #include "intel_drv.h" |
1da177e4 | 39 | |
e5868a31 EE |
40 | static const u32 hpd_ibx[] = { |
41 | [HPD_CRT] = SDE_CRT_HOTPLUG, | |
42 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, | |
43 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG, | |
44 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG, | |
45 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG | |
46 | }; | |
47 | ||
48 | static const u32 hpd_cpt[] = { | |
49 | [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, | |
73c352a2 | 50 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, |
e5868a31 EE |
51 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
52 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
53 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT | |
54 | }; | |
55 | ||
56 | static const u32 hpd_mask_i915[] = { | |
57 | [HPD_CRT] = CRT_HOTPLUG_INT_EN, | |
58 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, | |
59 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, | |
60 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, | |
61 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, | |
62 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN | |
63 | }; | |
64 | ||
704cfb87 | 65 | static const u32 hpd_status_g4x[] = { |
e5868a31 EE |
66 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
67 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, | |
68 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, | |
69 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
70 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
71 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
72 | }; | |
73 | ||
e5868a31 EE |
74 | static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ |
75 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, | |
76 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, | |
77 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, | |
78 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
79 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
80 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
81 | }; | |
82 | ||
5c502442 | 83 | /* IIR can theoretically queue up two events. Be paranoid. */ |
f86f3fb0 | 84 | #define GEN8_IRQ_RESET_NDX(type, which) do { \ |
5c502442 PZ |
85 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ |
86 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
87 | I915_WRITE(GEN8_##type##_IER(which), 0); \ | |
88 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
89 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
90 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
91 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
92 | } while (0) | |
93 | ||
f86f3fb0 | 94 | #define GEN5_IRQ_RESET(type) do { \ |
a9d356a6 | 95 | I915_WRITE(type##IMR, 0xffffffff); \ |
5c502442 | 96 | POSTING_READ(type##IMR); \ |
a9d356a6 | 97 | I915_WRITE(type##IER, 0); \ |
5c502442 PZ |
98 | I915_WRITE(type##IIR, 0xffffffff); \ |
99 | POSTING_READ(type##IIR); \ | |
100 | I915_WRITE(type##IIR, 0xffffffff); \ | |
101 | POSTING_READ(type##IIR); \ | |
a9d356a6 PZ |
102 | } while (0) |
103 | ||
337ba017 PZ |
104 | /* |
105 | * We should clear IMR at preinstall/uninstall, and just check at postinstall. | |
106 | */ | |
107 | #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \ | |
108 | u32 val = I915_READ(reg); \ | |
109 | if (val) { \ | |
110 | WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \ | |
111 | (reg), val); \ | |
112 | I915_WRITE((reg), 0xffffffff); \ | |
113 | POSTING_READ(reg); \ | |
114 | I915_WRITE((reg), 0xffffffff); \ | |
115 | POSTING_READ(reg); \ | |
116 | } \ | |
117 | } while (0) | |
118 | ||
35079899 | 119 | #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \ |
337ba017 | 120 | GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \ |
35079899 PZ |
121 | I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \ |
122 | I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \ | |
123 | POSTING_READ(GEN8_##type##_IER(which)); \ | |
124 | } while (0) | |
125 | ||
126 | #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \ | |
337ba017 | 127 | GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \ |
35079899 PZ |
128 | I915_WRITE(type##IMR, (imr_val)); \ |
129 | I915_WRITE(type##IER, (ier_val)); \ | |
130 | POSTING_READ(type##IER); \ | |
131 | } while (0) | |
132 | ||
036a4a7d | 133 | /* For display hotplug interrupt */ |
995b6762 | 134 | static void |
2d1013dd | 135 | ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask) |
036a4a7d | 136 | { |
4bc9d430 DV |
137 | assert_spin_locked(&dev_priv->irq_lock); |
138 | ||
730488b2 | 139 | if (WARN_ON(dev_priv->pm.irqs_disabled)) |
c67a470b | 140 | return; |
c67a470b | 141 | |
1ec14ad3 CW |
142 | if ((dev_priv->irq_mask & mask) != 0) { |
143 | dev_priv->irq_mask &= ~mask; | |
144 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 145 | POSTING_READ(DEIMR); |
036a4a7d ZW |
146 | } |
147 | } | |
148 | ||
0ff9800a | 149 | static void |
2d1013dd | 150 | ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask) |
036a4a7d | 151 | { |
4bc9d430 DV |
152 | assert_spin_locked(&dev_priv->irq_lock); |
153 | ||
730488b2 | 154 | if (WARN_ON(dev_priv->pm.irqs_disabled)) |
c67a470b | 155 | return; |
c67a470b | 156 | |
1ec14ad3 CW |
157 | if ((dev_priv->irq_mask & mask) != mask) { |
158 | dev_priv->irq_mask |= mask; | |
159 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 160 | POSTING_READ(DEIMR); |
036a4a7d ZW |
161 | } |
162 | } | |
163 | ||
43eaea13 PZ |
164 | /** |
165 | * ilk_update_gt_irq - update GTIMR | |
166 | * @dev_priv: driver private | |
167 | * @interrupt_mask: mask of interrupt bits to update | |
168 | * @enabled_irq_mask: mask of interrupt bits to enable | |
169 | */ | |
170 | static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, | |
171 | uint32_t interrupt_mask, | |
172 | uint32_t enabled_irq_mask) | |
173 | { | |
174 | assert_spin_locked(&dev_priv->irq_lock); | |
175 | ||
730488b2 | 176 | if (WARN_ON(dev_priv->pm.irqs_disabled)) |
c67a470b | 177 | return; |
c67a470b | 178 | |
43eaea13 PZ |
179 | dev_priv->gt_irq_mask &= ~interrupt_mask; |
180 | dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); | |
181 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
182 | POSTING_READ(GTIMR); | |
183 | } | |
184 | ||
185 | void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
186 | { | |
187 | ilk_update_gt_irq(dev_priv, mask, mask); | |
188 | } | |
189 | ||
190 | void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
191 | { | |
192 | ilk_update_gt_irq(dev_priv, mask, 0); | |
193 | } | |
194 | ||
edbfdb45 PZ |
195 | /** |
196 | * snb_update_pm_irq - update GEN6_PMIMR | |
197 | * @dev_priv: driver private | |
198 | * @interrupt_mask: mask of interrupt bits to update | |
199 | * @enabled_irq_mask: mask of interrupt bits to enable | |
200 | */ | |
201 | static void snb_update_pm_irq(struct drm_i915_private *dev_priv, | |
202 | uint32_t interrupt_mask, | |
203 | uint32_t enabled_irq_mask) | |
204 | { | |
605cd25b | 205 | uint32_t new_val; |
edbfdb45 PZ |
206 | |
207 | assert_spin_locked(&dev_priv->irq_lock); | |
208 | ||
730488b2 | 209 | if (WARN_ON(dev_priv->pm.irqs_disabled)) |
c67a470b | 210 | return; |
c67a470b | 211 | |
605cd25b | 212 | new_val = dev_priv->pm_irq_mask; |
f52ecbcf PZ |
213 | new_val &= ~interrupt_mask; |
214 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
215 | ||
605cd25b PZ |
216 | if (new_val != dev_priv->pm_irq_mask) { |
217 | dev_priv->pm_irq_mask = new_val; | |
218 | I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask); | |
f52ecbcf PZ |
219 | POSTING_READ(GEN6_PMIMR); |
220 | } | |
edbfdb45 PZ |
221 | } |
222 | ||
223 | void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
224 | { | |
225 | snb_update_pm_irq(dev_priv, mask, mask); | |
226 | } | |
227 | ||
228 | void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
229 | { | |
230 | snb_update_pm_irq(dev_priv, mask, 0); | |
231 | } | |
232 | ||
8664281b PZ |
233 | static bool ivb_can_enable_err_int(struct drm_device *dev) |
234 | { | |
235 | struct drm_i915_private *dev_priv = dev->dev_private; | |
236 | struct intel_crtc *crtc; | |
237 | enum pipe pipe; | |
238 | ||
4bc9d430 DV |
239 | assert_spin_locked(&dev_priv->irq_lock); |
240 | ||
8664281b PZ |
241 | for_each_pipe(pipe) { |
242 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
243 | ||
244 | if (crtc->cpu_fifo_underrun_disabled) | |
245 | return false; | |
246 | } | |
247 | ||
248 | return true; | |
249 | } | |
250 | ||
251 | static bool cpt_can_enable_serr_int(struct drm_device *dev) | |
252 | { | |
253 | struct drm_i915_private *dev_priv = dev->dev_private; | |
254 | enum pipe pipe; | |
255 | struct intel_crtc *crtc; | |
256 | ||
fee884ed DV |
257 | assert_spin_locked(&dev_priv->irq_lock); |
258 | ||
8664281b PZ |
259 | for_each_pipe(pipe) { |
260 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
261 | ||
262 | if (crtc->pch_fifo_underrun_disabled) | |
263 | return false; | |
264 | } | |
265 | ||
266 | return true; | |
267 | } | |
268 | ||
2d9d2b0b VS |
269 | static void i9xx_clear_fifo_underrun(struct drm_device *dev, enum pipe pipe) |
270 | { | |
271 | struct drm_i915_private *dev_priv = dev->dev_private; | |
272 | u32 reg = PIPESTAT(pipe); | |
273 | u32 pipestat = I915_READ(reg) & 0x7fff0000; | |
274 | ||
275 | assert_spin_locked(&dev_priv->irq_lock); | |
276 | ||
277 | I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS); | |
278 | POSTING_READ(reg); | |
279 | } | |
280 | ||
8664281b PZ |
281 | static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev, |
282 | enum pipe pipe, bool enable) | |
283 | { | |
284 | struct drm_i915_private *dev_priv = dev->dev_private; | |
285 | uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN : | |
286 | DE_PIPEB_FIFO_UNDERRUN; | |
287 | ||
288 | if (enable) | |
289 | ironlake_enable_display_irq(dev_priv, bit); | |
290 | else | |
291 | ironlake_disable_display_irq(dev_priv, bit); | |
292 | } | |
293 | ||
294 | static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev, | |
7336df65 | 295 | enum pipe pipe, bool enable) |
8664281b PZ |
296 | { |
297 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8664281b | 298 | if (enable) { |
7336df65 DV |
299 | I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); |
300 | ||
8664281b PZ |
301 | if (!ivb_can_enable_err_int(dev)) |
302 | return; | |
303 | ||
8664281b PZ |
304 | ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB); |
305 | } else { | |
7336df65 DV |
306 | bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB); |
307 | ||
308 | /* Change the state _after_ we've read out the current one. */ | |
8664281b | 309 | ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB); |
7336df65 DV |
310 | |
311 | if (!was_enabled && | |
312 | (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) { | |
313 | DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n", | |
314 | pipe_name(pipe)); | |
315 | } | |
8664281b PZ |
316 | } |
317 | } | |
318 | ||
38d83c96 DV |
319 | static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev, |
320 | enum pipe pipe, bool enable) | |
321 | { | |
322 | struct drm_i915_private *dev_priv = dev->dev_private; | |
323 | ||
324 | assert_spin_locked(&dev_priv->irq_lock); | |
325 | ||
326 | if (enable) | |
327 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN; | |
328 | else | |
329 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN; | |
330 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
331 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
332 | } | |
333 | ||
fee884ed DV |
334 | /** |
335 | * ibx_display_interrupt_update - update SDEIMR | |
336 | * @dev_priv: driver private | |
337 | * @interrupt_mask: mask of interrupt bits to update | |
338 | * @enabled_irq_mask: mask of interrupt bits to enable | |
339 | */ | |
340 | static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, | |
341 | uint32_t interrupt_mask, | |
342 | uint32_t enabled_irq_mask) | |
343 | { | |
344 | uint32_t sdeimr = I915_READ(SDEIMR); | |
345 | sdeimr &= ~interrupt_mask; | |
346 | sdeimr |= (~enabled_irq_mask & interrupt_mask); | |
347 | ||
348 | assert_spin_locked(&dev_priv->irq_lock); | |
349 | ||
730488b2 | 350 | if (WARN_ON(dev_priv->pm.irqs_disabled)) |
c67a470b | 351 | return; |
c67a470b | 352 | |
fee884ed DV |
353 | I915_WRITE(SDEIMR, sdeimr); |
354 | POSTING_READ(SDEIMR); | |
355 | } | |
356 | #define ibx_enable_display_interrupt(dev_priv, bits) \ | |
357 | ibx_display_interrupt_update((dev_priv), (bits), (bits)) | |
358 | #define ibx_disable_display_interrupt(dev_priv, bits) \ | |
359 | ibx_display_interrupt_update((dev_priv), (bits), 0) | |
360 | ||
de28075d DV |
361 | static void ibx_set_fifo_underrun_reporting(struct drm_device *dev, |
362 | enum transcoder pch_transcoder, | |
8664281b PZ |
363 | bool enable) |
364 | { | |
8664281b | 365 | struct drm_i915_private *dev_priv = dev->dev_private; |
de28075d DV |
366 | uint32_t bit = (pch_transcoder == TRANSCODER_A) ? |
367 | SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER; | |
8664281b PZ |
368 | |
369 | if (enable) | |
fee884ed | 370 | ibx_enable_display_interrupt(dev_priv, bit); |
8664281b | 371 | else |
fee884ed | 372 | ibx_disable_display_interrupt(dev_priv, bit); |
8664281b PZ |
373 | } |
374 | ||
375 | static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, | |
376 | enum transcoder pch_transcoder, | |
377 | bool enable) | |
378 | { | |
379 | struct drm_i915_private *dev_priv = dev->dev_private; | |
380 | ||
381 | if (enable) { | |
1dd246fb DV |
382 | I915_WRITE(SERR_INT, |
383 | SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); | |
384 | ||
8664281b PZ |
385 | if (!cpt_can_enable_serr_int(dev)) |
386 | return; | |
387 | ||
fee884ed | 388 | ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
8664281b | 389 | } else { |
1dd246fb DV |
390 | uint32_t tmp = I915_READ(SERR_INT); |
391 | bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT); | |
392 | ||
393 | /* Change the state _after_ we've read out the current one. */ | |
fee884ed | 394 | ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
1dd246fb DV |
395 | |
396 | if (!was_enabled && | |
397 | (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) { | |
398 | DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n", | |
399 | transcoder_name(pch_transcoder)); | |
400 | } | |
8664281b | 401 | } |
8664281b PZ |
402 | } |
403 | ||
404 | /** | |
405 | * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages | |
406 | * @dev: drm device | |
407 | * @pipe: pipe | |
408 | * @enable: true if we want to report FIFO underrun errors, false otherwise | |
409 | * | |
410 | * This function makes us disable or enable CPU fifo underruns for a specific | |
411 | * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun | |
412 | * reporting for one pipe may also disable all the other CPU error interruts for | |
413 | * the other pipes, due to the fact that there's just one interrupt mask/enable | |
414 | * bit for all the pipes. | |
415 | * | |
416 | * Returns the previous state of underrun reporting. | |
417 | */ | |
f88d42f1 ID |
418 | bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, |
419 | enum pipe pipe, bool enable) | |
8664281b PZ |
420 | { |
421 | struct drm_i915_private *dev_priv = dev->dev_private; | |
422 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
423 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8664281b PZ |
424 | bool ret; |
425 | ||
77961eb9 ID |
426 | assert_spin_locked(&dev_priv->irq_lock); |
427 | ||
8664281b PZ |
428 | ret = !intel_crtc->cpu_fifo_underrun_disabled; |
429 | ||
430 | if (enable == ret) | |
431 | goto done; | |
432 | ||
433 | intel_crtc->cpu_fifo_underrun_disabled = !enable; | |
434 | ||
2d9d2b0b VS |
435 | if (enable && (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))) |
436 | i9xx_clear_fifo_underrun(dev, pipe); | |
437 | else if (IS_GEN5(dev) || IS_GEN6(dev)) | |
8664281b PZ |
438 | ironlake_set_fifo_underrun_reporting(dev, pipe, enable); |
439 | else if (IS_GEN7(dev)) | |
7336df65 | 440 | ivybridge_set_fifo_underrun_reporting(dev, pipe, enable); |
38d83c96 DV |
441 | else if (IS_GEN8(dev)) |
442 | broadwell_set_fifo_underrun_reporting(dev, pipe, enable); | |
8664281b PZ |
443 | |
444 | done: | |
f88d42f1 ID |
445 | return ret; |
446 | } | |
447 | ||
448 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, | |
449 | enum pipe pipe, bool enable) | |
450 | { | |
451 | struct drm_i915_private *dev_priv = dev->dev_private; | |
452 | unsigned long flags; | |
453 | bool ret; | |
454 | ||
455 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
456 | ret = __intel_set_cpu_fifo_underrun_reporting(dev, pipe, enable); | |
8664281b | 457 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
f88d42f1 | 458 | |
8664281b PZ |
459 | return ret; |
460 | } | |
461 | ||
91d181dd ID |
462 | static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev, |
463 | enum pipe pipe) | |
464 | { | |
465 | struct drm_i915_private *dev_priv = dev->dev_private; | |
466 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
467 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
468 | ||
469 | return !intel_crtc->cpu_fifo_underrun_disabled; | |
470 | } | |
471 | ||
8664281b PZ |
472 | /** |
473 | * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages | |
474 | * @dev: drm device | |
475 | * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) | |
476 | * @enable: true if we want to report FIFO underrun errors, false otherwise | |
477 | * | |
478 | * This function makes us disable or enable PCH fifo underruns for a specific | |
479 | * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO | |
480 | * underrun reporting for one transcoder may also disable all the other PCH | |
481 | * error interruts for the other transcoders, due to the fact that there's just | |
482 | * one interrupt mask/enable bit for all the transcoders. | |
483 | * | |
484 | * Returns the previous state of underrun reporting. | |
485 | */ | |
486 | bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, | |
487 | enum transcoder pch_transcoder, | |
488 | bool enable) | |
489 | { | |
490 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de28075d DV |
491 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder]; |
492 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8664281b PZ |
493 | unsigned long flags; |
494 | bool ret; | |
495 | ||
de28075d DV |
496 | /* |
497 | * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT | |
498 | * has only one pch transcoder A that all pipes can use. To avoid racy | |
499 | * pch transcoder -> pipe lookups from interrupt code simply store the | |
500 | * underrun statistics in crtc A. Since we never expose this anywhere | |
501 | * nor use it outside of the fifo underrun code here using the "wrong" | |
502 | * crtc on LPT won't cause issues. | |
503 | */ | |
8664281b PZ |
504 | |
505 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
506 | ||
507 | ret = !intel_crtc->pch_fifo_underrun_disabled; | |
508 | ||
509 | if (enable == ret) | |
510 | goto done; | |
511 | ||
512 | intel_crtc->pch_fifo_underrun_disabled = !enable; | |
513 | ||
514 | if (HAS_PCH_IBX(dev)) | |
de28075d | 515 | ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable); |
8664281b PZ |
516 | else |
517 | cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable); | |
518 | ||
519 | done: | |
520 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
521 | return ret; | |
522 | } | |
523 | ||
524 | ||
b5ea642a | 525 | static void |
755e9019 ID |
526 | __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
527 | u32 enable_mask, u32 status_mask) | |
7c463586 | 528 | { |
46c06a30 | 529 | u32 reg = PIPESTAT(pipe); |
755e9019 | 530 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 531 | |
b79480ba DV |
532 | assert_spin_locked(&dev_priv->irq_lock); |
533 | ||
04feced9 VS |
534 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
535 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
536 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
537 | pipe_name(pipe), enable_mask, status_mask)) | |
755e9019 ID |
538 | return; |
539 | ||
540 | if ((pipestat & enable_mask) == enable_mask) | |
46c06a30 VS |
541 | return; |
542 | ||
91d181dd ID |
543 | dev_priv->pipestat_irq_mask[pipe] |= status_mask; |
544 | ||
46c06a30 | 545 | /* Enable the interrupt, clear any pending status */ |
755e9019 | 546 | pipestat |= enable_mask | status_mask; |
46c06a30 VS |
547 | I915_WRITE(reg, pipestat); |
548 | POSTING_READ(reg); | |
7c463586 KP |
549 | } |
550 | ||
b5ea642a | 551 | static void |
755e9019 ID |
552 | __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
553 | u32 enable_mask, u32 status_mask) | |
7c463586 | 554 | { |
46c06a30 | 555 | u32 reg = PIPESTAT(pipe); |
755e9019 | 556 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 557 | |
b79480ba DV |
558 | assert_spin_locked(&dev_priv->irq_lock); |
559 | ||
04feced9 VS |
560 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
561 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
562 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
563 | pipe_name(pipe), enable_mask, status_mask)) | |
46c06a30 VS |
564 | return; |
565 | ||
755e9019 ID |
566 | if ((pipestat & enable_mask) == 0) |
567 | return; | |
568 | ||
91d181dd ID |
569 | dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; |
570 | ||
755e9019 | 571 | pipestat &= ~enable_mask; |
46c06a30 VS |
572 | I915_WRITE(reg, pipestat); |
573 | POSTING_READ(reg); | |
7c463586 KP |
574 | } |
575 | ||
10c59c51 ID |
576 | static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask) |
577 | { | |
578 | u32 enable_mask = status_mask << 16; | |
579 | ||
580 | /* | |
581 | * On pipe A we don't support the PSR interrupt yet, on pipe B the | |
582 | * same bit MBZ. | |
583 | */ | |
584 | if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV)) | |
585 | return 0; | |
586 | ||
587 | enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | | |
588 | SPRITE0_FLIP_DONE_INT_EN_VLV | | |
589 | SPRITE1_FLIP_DONE_INT_EN_VLV); | |
590 | if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV) | |
591 | enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV; | |
592 | if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV) | |
593 | enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; | |
594 | ||
595 | return enable_mask; | |
596 | } | |
597 | ||
755e9019 ID |
598 | void |
599 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
600 | u32 status_mask) | |
601 | { | |
602 | u32 enable_mask; | |
603 | ||
10c59c51 ID |
604 | if (IS_VALLEYVIEW(dev_priv->dev)) |
605 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, | |
606 | status_mask); | |
607 | else | |
608 | enable_mask = status_mask << 16; | |
755e9019 ID |
609 | __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
610 | } | |
611 | ||
612 | void | |
613 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
614 | u32 status_mask) | |
615 | { | |
616 | u32 enable_mask; | |
617 | ||
10c59c51 ID |
618 | if (IS_VALLEYVIEW(dev_priv->dev)) |
619 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, | |
620 | status_mask); | |
621 | else | |
622 | enable_mask = status_mask << 16; | |
755e9019 ID |
623 | __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
624 | } | |
625 | ||
01c66889 | 626 | /** |
f49e38dd | 627 | * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion |
01c66889 | 628 | */ |
f49e38dd | 629 | static void i915_enable_asle_pipestat(struct drm_device *dev) |
01c66889 | 630 | { |
2d1013dd | 631 | struct drm_i915_private *dev_priv = dev->dev_private; |
1ec14ad3 CW |
632 | unsigned long irqflags; |
633 | ||
f49e38dd JN |
634 | if (!dev_priv->opregion.asle || !IS_MOBILE(dev)) |
635 | return; | |
636 | ||
1ec14ad3 | 637 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
01c66889 | 638 | |
755e9019 | 639 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); |
f898780b | 640 | if (INTEL_INFO(dev)->gen >= 4) |
3b6c42e8 | 641 | i915_enable_pipestat(dev_priv, PIPE_A, |
755e9019 | 642 | PIPE_LEGACY_BLC_EVENT_STATUS); |
1ec14ad3 CW |
643 | |
644 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
01c66889 ZY |
645 | } |
646 | ||
0a3e67a4 JB |
647 | /** |
648 | * i915_pipe_enabled - check if a pipe is enabled | |
649 | * @dev: DRM device | |
650 | * @pipe: pipe to check | |
651 | * | |
652 | * Reading certain registers when the pipe is disabled can hang the chip. | |
653 | * Use this routine to make sure the PLL is running and the pipe is active | |
654 | * before reading such registers if unsure. | |
655 | */ | |
656 | static int | |
657 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
658 | { | |
2d1013dd | 659 | struct drm_i915_private *dev_priv = dev->dev_private; |
702e7a56 | 660 | |
a01025af DV |
661 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
662 | /* Locking is horribly broken here, but whatever. */ | |
663 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
664 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
71f8ba6b | 665 | |
a01025af DV |
666 | return intel_crtc->active; |
667 | } else { | |
668 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; | |
669 | } | |
0a3e67a4 JB |
670 | } |
671 | ||
4cdb83ec VS |
672 | static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe) |
673 | { | |
674 | /* Gen2 doesn't have a hardware frame counter */ | |
675 | return 0; | |
676 | } | |
677 | ||
42f52ef8 KP |
678 | /* Called from drm generic code, passed a 'crtc', which |
679 | * we use as a pipe index | |
680 | */ | |
f71d4af4 | 681 | static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
0a3e67a4 | 682 | { |
2d1013dd | 683 | struct drm_i915_private *dev_priv = dev->dev_private; |
0a3e67a4 JB |
684 | unsigned long high_frame; |
685 | unsigned long low_frame; | |
391f75e2 | 686 | u32 high1, high2, low, pixel, vbl_start; |
0a3e67a4 JB |
687 | |
688 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 689 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 690 | "pipe %c\n", pipe_name(pipe)); |
0a3e67a4 JB |
691 | return 0; |
692 | } | |
693 | ||
391f75e2 VS |
694 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
695 | struct intel_crtc *intel_crtc = | |
696 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
697 | const struct drm_display_mode *mode = | |
698 | &intel_crtc->config.adjusted_mode; | |
699 | ||
700 | vbl_start = mode->crtc_vblank_start * mode->crtc_htotal; | |
701 | } else { | |
a2d213dd | 702 | enum transcoder cpu_transcoder = (enum transcoder) pipe; |
391f75e2 VS |
703 | u32 htotal; |
704 | ||
705 | htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1; | |
706 | vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1; | |
707 | ||
708 | vbl_start *= htotal; | |
709 | } | |
710 | ||
9db4a9c7 JB |
711 | high_frame = PIPEFRAME(pipe); |
712 | low_frame = PIPEFRAMEPIXEL(pipe); | |
5eddb70b | 713 | |
0a3e67a4 JB |
714 | /* |
715 | * High & low register fields aren't synchronized, so make sure | |
716 | * we get a low value that's stable across two reads of the high | |
717 | * register. | |
718 | */ | |
719 | do { | |
5eddb70b | 720 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
391f75e2 | 721 | low = I915_READ(low_frame); |
5eddb70b | 722 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
0a3e67a4 JB |
723 | } while (high1 != high2); |
724 | ||
5eddb70b | 725 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
391f75e2 | 726 | pixel = low & PIPE_PIXEL_MASK; |
5eddb70b | 727 | low >>= PIPE_FRAME_LOW_SHIFT; |
391f75e2 VS |
728 | |
729 | /* | |
730 | * The frame counter increments at beginning of active. | |
731 | * Cook up a vblank counter by also checking the pixel | |
732 | * counter against vblank start. | |
733 | */ | |
edc08d0a | 734 | return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; |
0a3e67a4 JB |
735 | } |
736 | ||
f71d4af4 | 737 | static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
9880b7a5 | 738 | { |
2d1013dd | 739 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 740 | int reg = PIPE_FRMCOUNT_GM45(pipe); |
9880b7a5 JB |
741 | |
742 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 743 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 744 | "pipe %c\n", pipe_name(pipe)); |
9880b7a5 JB |
745 | return 0; |
746 | } | |
747 | ||
748 | return I915_READ(reg); | |
749 | } | |
750 | ||
ad3543ed MK |
751 | /* raw reads, only for fast reads of display block, no need for forcewake etc. */ |
752 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) | |
ad3543ed | 753 | |
f71d4af4 | 754 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
abca9e45 VS |
755 | unsigned int flags, int *vpos, int *hpos, |
756 | ktime_t *stime, ktime_t *etime) | |
0af7e4df | 757 | { |
c2baf4b7 VS |
758 | struct drm_i915_private *dev_priv = dev->dev_private; |
759 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
760 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
761 | const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; | |
3aa18df8 | 762 | int position; |
78e8fc6b | 763 | int vbl_start, vbl_end, hsync_start, htotal, vtotal; |
0af7e4df MK |
764 | bool in_vbl = true; |
765 | int ret = 0; | |
ad3543ed | 766 | unsigned long irqflags; |
0af7e4df | 767 | |
c2baf4b7 | 768 | if (!intel_crtc->active) { |
0af7e4df | 769 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
9db4a9c7 | 770 | "pipe %c\n", pipe_name(pipe)); |
0af7e4df MK |
771 | return 0; |
772 | } | |
773 | ||
c2baf4b7 | 774 | htotal = mode->crtc_htotal; |
78e8fc6b | 775 | hsync_start = mode->crtc_hsync_start; |
c2baf4b7 VS |
776 | vtotal = mode->crtc_vtotal; |
777 | vbl_start = mode->crtc_vblank_start; | |
778 | vbl_end = mode->crtc_vblank_end; | |
0af7e4df | 779 | |
d31faf65 VS |
780 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
781 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
782 | vbl_end /= 2; | |
783 | vtotal /= 2; | |
784 | } | |
785 | ||
c2baf4b7 VS |
786 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; |
787 | ||
ad3543ed MK |
788 | /* |
789 | * Lock uncore.lock, as we will do multiple timing critical raw | |
790 | * register reads, potentially with preemption disabled, so the | |
791 | * following code must not block on uncore.lock. | |
792 | */ | |
793 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
78e8fc6b | 794 | |
ad3543ed MK |
795 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ |
796 | ||
797 | /* Get optional system timestamp before query. */ | |
798 | if (stime) | |
799 | *stime = ktime_get(); | |
800 | ||
7c06b08a | 801 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
0af7e4df MK |
802 | /* No obvious pixelcount register. Only query vertical |
803 | * scanout position from Display scan line register. | |
804 | */ | |
7c06b08a | 805 | if (IS_GEN2(dev)) |
ad3543ed | 806 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; |
7c06b08a | 807 | else |
ad3543ed | 808 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; |
54ddcbd2 | 809 | |
78e8fc6b VS |
810 | /* |
811 | * Scanline counter increments at leading edge of hsync, and | |
812 | * it starts counting from vtotal-1 on the first active line. | |
813 | * That means the scanline counter value is always one less | |
814 | * than what we would expect. Ie. just after start of vblank, | |
815 | * which also occurs at start of hsync (on the last active line), | |
816 | * the scanline counter will read vblank_start-1. | |
817 | */ | |
818 | position = (position + 1) % vtotal; | |
0af7e4df MK |
819 | } else { |
820 | /* Have access to pixelcount since start of frame. | |
821 | * We can split this into vertical and horizontal | |
822 | * scanout position. | |
823 | */ | |
ad3543ed | 824 | position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; |
0af7e4df | 825 | |
3aa18df8 VS |
826 | /* convert to pixel counts */ |
827 | vbl_start *= htotal; | |
828 | vbl_end *= htotal; | |
829 | vtotal *= htotal; | |
78e8fc6b VS |
830 | |
831 | /* | |
832 | * Start of vblank interrupt is triggered at start of hsync, | |
833 | * just prior to the first active line of vblank. However we | |
834 | * consider lines to start at the leading edge of horizontal | |
835 | * active. So, should we get here before we've crossed into | |
836 | * the horizontal active of the first line in vblank, we would | |
837 | * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that, | |
838 | * always add htotal-hsync_start to the current pixel position. | |
839 | */ | |
840 | position = (position + htotal - hsync_start) % vtotal; | |
0af7e4df MK |
841 | } |
842 | ||
ad3543ed MK |
843 | /* Get optional system timestamp after query. */ |
844 | if (etime) | |
845 | *etime = ktime_get(); | |
846 | ||
847 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ | |
848 | ||
849 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
850 | ||
3aa18df8 VS |
851 | in_vbl = position >= vbl_start && position < vbl_end; |
852 | ||
853 | /* | |
854 | * While in vblank, position will be negative | |
855 | * counting up towards 0 at vbl_end. And outside | |
856 | * vblank, position will be positive counting | |
857 | * up since vbl_end. | |
858 | */ | |
859 | if (position >= vbl_start) | |
860 | position -= vbl_end; | |
861 | else | |
862 | position += vtotal - vbl_end; | |
0af7e4df | 863 | |
7c06b08a | 864 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
3aa18df8 VS |
865 | *vpos = position; |
866 | *hpos = 0; | |
867 | } else { | |
868 | *vpos = position / htotal; | |
869 | *hpos = position - (*vpos * htotal); | |
870 | } | |
0af7e4df | 871 | |
0af7e4df MK |
872 | /* In vblank? */ |
873 | if (in_vbl) | |
874 | ret |= DRM_SCANOUTPOS_INVBL; | |
875 | ||
876 | return ret; | |
877 | } | |
878 | ||
f71d4af4 | 879 | static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
0af7e4df MK |
880 | int *max_error, |
881 | struct timeval *vblank_time, | |
882 | unsigned flags) | |
883 | { | |
4041b853 | 884 | struct drm_crtc *crtc; |
0af7e4df | 885 | |
7eb552ae | 886 | if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { |
4041b853 | 887 | DRM_ERROR("Invalid crtc %d\n", pipe); |
0af7e4df MK |
888 | return -EINVAL; |
889 | } | |
890 | ||
891 | /* Get drm_crtc to timestamp: */ | |
4041b853 CW |
892 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
893 | if (crtc == NULL) { | |
894 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
895 | return -EINVAL; | |
896 | } | |
897 | ||
898 | if (!crtc->enabled) { | |
899 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); | |
900 | return -EBUSY; | |
901 | } | |
0af7e4df MK |
902 | |
903 | /* Helper routine in DRM core does all the work: */ | |
4041b853 CW |
904 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
905 | vblank_time, flags, | |
7da903ef VS |
906 | crtc, |
907 | &to_intel_crtc(crtc)->config.adjusted_mode); | |
0af7e4df MK |
908 | } |
909 | ||
67c347ff JN |
910 | static bool intel_hpd_irq_event(struct drm_device *dev, |
911 | struct drm_connector *connector) | |
321a1b30 EE |
912 | { |
913 | enum drm_connector_status old_status; | |
914 | ||
915 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); | |
916 | old_status = connector->status; | |
917 | ||
918 | connector->status = connector->funcs->detect(connector, false); | |
67c347ff JN |
919 | if (old_status == connector->status) |
920 | return false; | |
921 | ||
922 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n", | |
321a1b30 EE |
923 | connector->base.id, |
924 | drm_get_connector_name(connector), | |
67c347ff JN |
925 | drm_get_connector_status_name(old_status), |
926 | drm_get_connector_status_name(connector->status)); | |
927 | ||
928 | return true; | |
321a1b30 EE |
929 | } |
930 | ||
5ca58282 JB |
931 | /* |
932 | * Handle hotplug events outside the interrupt handler proper. | |
933 | */ | |
ac4c16c5 EE |
934 | #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000) |
935 | ||
5ca58282 JB |
936 | static void i915_hotplug_work_func(struct work_struct *work) |
937 | { | |
2d1013dd JN |
938 | struct drm_i915_private *dev_priv = |
939 | container_of(work, struct drm_i915_private, hotplug_work); | |
5ca58282 | 940 | struct drm_device *dev = dev_priv->dev; |
c31c4ba3 | 941 | struct drm_mode_config *mode_config = &dev->mode_config; |
cd569aed EE |
942 | struct intel_connector *intel_connector; |
943 | struct intel_encoder *intel_encoder; | |
944 | struct drm_connector *connector; | |
945 | unsigned long irqflags; | |
946 | bool hpd_disabled = false; | |
321a1b30 | 947 | bool changed = false; |
142e2398 | 948 | u32 hpd_event_bits; |
4ef69c7a | 949 | |
52d7eced DV |
950 | /* HPD irq before everything is fully set up. */ |
951 | if (!dev_priv->enable_hotplug_processing) | |
952 | return; | |
953 | ||
a65e34c7 | 954 | mutex_lock(&mode_config->mutex); |
e67189ab JB |
955 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); |
956 | ||
cd569aed | 957 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
142e2398 EE |
958 | |
959 | hpd_event_bits = dev_priv->hpd_event_bits; | |
960 | dev_priv->hpd_event_bits = 0; | |
cd569aed EE |
961 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
962 | intel_connector = to_intel_connector(connector); | |
963 | intel_encoder = intel_connector->encoder; | |
964 | if (intel_encoder->hpd_pin > HPD_NONE && | |
965 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED && | |
966 | connector->polled == DRM_CONNECTOR_POLL_HPD) { | |
967 | DRM_INFO("HPD interrupt storm detected on connector %s: " | |
968 | "switching from hotplug detection to polling\n", | |
969 | drm_get_connector_name(connector)); | |
970 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED; | |
971 | connector->polled = DRM_CONNECTOR_POLL_CONNECT | |
972 | | DRM_CONNECTOR_POLL_DISCONNECT; | |
973 | hpd_disabled = true; | |
974 | } | |
142e2398 EE |
975 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { |
976 | DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n", | |
977 | drm_get_connector_name(connector), intel_encoder->hpd_pin); | |
978 | } | |
cd569aed EE |
979 | } |
980 | /* if there were no outputs to poll, poll was disabled, | |
981 | * therefore make sure it's enabled when disabling HPD on | |
982 | * some connectors */ | |
ac4c16c5 | 983 | if (hpd_disabled) { |
cd569aed | 984 | drm_kms_helper_poll_enable(dev); |
ac4c16c5 EE |
985 | mod_timer(&dev_priv->hotplug_reenable_timer, |
986 | jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY)); | |
987 | } | |
cd569aed EE |
988 | |
989 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
990 | ||
321a1b30 EE |
991 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
992 | intel_connector = to_intel_connector(connector); | |
993 | intel_encoder = intel_connector->encoder; | |
994 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { | |
995 | if (intel_encoder->hot_plug) | |
996 | intel_encoder->hot_plug(intel_encoder); | |
997 | if (intel_hpd_irq_event(dev, connector)) | |
998 | changed = true; | |
999 | } | |
1000 | } | |
40ee3381 KP |
1001 | mutex_unlock(&mode_config->mutex); |
1002 | ||
321a1b30 EE |
1003 | if (changed) |
1004 | drm_kms_helper_hotplug_event(dev); | |
5ca58282 JB |
1005 | } |
1006 | ||
3ca1cced VS |
1007 | static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv) |
1008 | { | |
1009 | del_timer_sync(&dev_priv->hotplug_reenable_timer); | |
1010 | } | |
1011 | ||
d0ecd7e2 | 1012 | static void ironlake_rps_change_irq_handler(struct drm_device *dev) |
f97108d1 | 1013 | { |
2d1013dd | 1014 | struct drm_i915_private *dev_priv = dev->dev_private; |
b5b72e89 | 1015 | u32 busy_up, busy_down, max_avg, min_avg; |
9270388e | 1016 | u8 new_delay; |
9270388e | 1017 | |
d0ecd7e2 | 1018 | spin_lock(&mchdev_lock); |
f97108d1 | 1019 | |
73edd18f DV |
1020 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
1021 | ||
20e4d407 | 1022 | new_delay = dev_priv->ips.cur_delay; |
9270388e | 1023 | |
7648fa99 | 1024 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
1025 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
1026 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
1027 | max_avg = I915_READ(RCBMAXAVG); |
1028 | min_avg = I915_READ(RCBMINAVG); | |
1029 | ||
1030 | /* Handle RCS change request from hw */ | |
b5b72e89 | 1031 | if (busy_up > max_avg) { |
20e4d407 DV |
1032 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
1033 | new_delay = dev_priv->ips.cur_delay - 1; | |
1034 | if (new_delay < dev_priv->ips.max_delay) | |
1035 | new_delay = dev_priv->ips.max_delay; | |
b5b72e89 | 1036 | } else if (busy_down < min_avg) { |
20e4d407 DV |
1037 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
1038 | new_delay = dev_priv->ips.cur_delay + 1; | |
1039 | if (new_delay > dev_priv->ips.min_delay) | |
1040 | new_delay = dev_priv->ips.min_delay; | |
f97108d1 JB |
1041 | } |
1042 | ||
7648fa99 | 1043 | if (ironlake_set_drps(dev, new_delay)) |
20e4d407 | 1044 | dev_priv->ips.cur_delay = new_delay; |
f97108d1 | 1045 | |
d0ecd7e2 | 1046 | spin_unlock(&mchdev_lock); |
9270388e | 1047 | |
f97108d1 JB |
1048 | return; |
1049 | } | |
1050 | ||
549f7365 CW |
1051 | static void notify_ring(struct drm_device *dev, |
1052 | struct intel_ring_buffer *ring) | |
1053 | { | |
475553de CW |
1054 | if (ring->obj == NULL) |
1055 | return; | |
1056 | ||
814e9b57 | 1057 | trace_i915_gem_request_complete(ring); |
9862e600 | 1058 | |
549f7365 | 1059 | wake_up_all(&ring->irq_queue); |
10cd45b6 | 1060 | i915_queue_hangcheck(dev); |
549f7365 CW |
1061 | } |
1062 | ||
4912d041 | 1063 | static void gen6_pm_rps_work(struct work_struct *work) |
3b8d8d91 | 1064 | { |
2d1013dd JN |
1065 | struct drm_i915_private *dev_priv = |
1066 | container_of(work, struct drm_i915_private, rps.work); | |
edbfdb45 | 1067 | u32 pm_iir; |
dd75fdc8 | 1068 | int new_delay, adj; |
4912d041 | 1069 | |
59cdb63d | 1070 | spin_lock_irq(&dev_priv->irq_lock); |
c6a828d3 DV |
1071 | pm_iir = dev_priv->rps.pm_iir; |
1072 | dev_priv->rps.pm_iir = 0; | |
4848405c | 1073 | /* Make sure not to corrupt PMIMR state used by ringbuffer code */ |
a6706b45 | 1074 | snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
59cdb63d | 1075 | spin_unlock_irq(&dev_priv->irq_lock); |
3b8d8d91 | 1076 | |
60611c13 | 1077 | /* Make sure we didn't queue anything we're not going to process. */ |
a6706b45 | 1078 | WARN_ON(pm_iir & ~dev_priv->pm_rps_events); |
60611c13 | 1079 | |
a6706b45 | 1080 | if ((pm_iir & dev_priv->pm_rps_events) == 0) |
3b8d8d91 JB |
1081 | return; |
1082 | ||
4fc688ce | 1083 | mutex_lock(&dev_priv->rps.hw_lock); |
7b9e0ae6 | 1084 | |
dd75fdc8 | 1085 | adj = dev_priv->rps.last_adj; |
7425034a | 1086 | if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { |
dd75fdc8 CW |
1087 | if (adj > 0) |
1088 | adj *= 2; | |
1089 | else | |
1090 | adj = 1; | |
b39fb297 | 1091 | new_delay = dev_priv->rps.cur_freq + adj; |
7425034a VS |
1092 | |
1093 | /* | |
1094 | * For better performance, jump directly | |
1095 | * to RPe if we're below it. | |
1096 | */ | |
b39fb297 BW |
1097 | if (new_delay < dev_priv->rps.efficient_freq) |
1098 | new_delay = dev_priv->rps.efficient_freq; | |
dd75fdc8 | 1099 | } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { |
b39fb297 BW |
1100 | if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq) |
1101 | new_delay = dev_priv->rps.efficient_freq; | |
dd75fdc8 | 1102 | else |
b39fb297 | 1103 | new_delay = dev_priv->rps.min_freq_softlimit; |
dd75fdc8 CW |
1104 | adj = 0; |
1105 | } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { | |
1106 | if (adj < 0) | |
1107 | adj *= 2; | |
1108 | else | |
1109 | adj = -1; | |
b39fb297 | 1110 | new_delay = dev_priv->rps.cur_freq + adj; |
dd75fdc8 | 1111 | } else { /* unknown event */ |
b39fb297 | 1112 | new_delay = dev_priv->rps.cur_freq; |
dd75fdc8 | 1113 | } |
3b8d8d91 | 1114 | |
79249636 BW |
1115 | /* sysfs frequency interfaces may have snuck in while servicing the |
1116 | * interrupt | |
1117 | */ | |
1272e7b8 | 1118 | new_delay = clamp_t(int, new_delay, |
b39fb297 BW |
1119 | dev_priv->rps.min_freq_softlimit, |
1120 | dev_priv->rps.max_freq_softlimit); | |
27544369 | 1121 | |
b39fb297 | 1122 | dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq; |
dd75fdc8 CW |
1123 | |
1124 | if (IS_VALLEYVIEW(dev_priv->dev)) | |
1125 | valleyview_set_rps(dev_priv->dev, new_delay); | |
1126 | else | |
1127 | gen6_set_rps(dev_priv->dev, new_delay); | |
3b8d8d91 | 1128 | |
4fc688ce | 1129 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 JB |
1130 | } |
1131 | ||
e3689190 BW |
1132 | |
1133 | /** | |
1134 | * ivybridge_parity_work - Workqueue called when a parity error interrupt | |
1135 | * occurred. | |
1136 | * @work: workqueue struct | |
1137 | * | |
1138 | * Doesn't actually do anything except notify userspace. As a consequence of | |
1139 | * this event, userspace should try to remap the bad rows since statistically | |
1140 | * it is likely the same row is more likely to go bad again. | |
1141 | */ | |
1142 | static void ivybridge_parity_work(struct work_struct *work) | |
1143 | { | |
2d1013dd JN |
1144 | struct drm_i915_private *dev_priv = |
1145 | container_of(work, struct drm_i915_private, l3_parity.error_work); | |
e3689190 | 1146 | u32 error_status, row, bank, subbank; |
35a85ac6 | 1147 | char *parity_event[6]; |
e3689190 BW |
1148 | uint32_t misccpctl; |
1149 | unsigned long flags; | |
35a85ac6 | 1150 | uint8_t slice = 0; |
e3689190 BW |
1151 | |
1152 | /* We must turn off DOP level clock gating to access the L3 registers. | |
1153 | * In order to prevent a get/put style interface, acquire struct mutex | |
1154 | * any time we access those registers. | |
1155 | */ | |
1156 | mutex_lock(&dev_priv->dev->struct_mutex); | |
1157 | ||
35a85ac6 BW |
1158 | /* If we've screwed up tracking, just let the interrupt fire again */ |
1159 | if (WARN_ON(!dev_priv->l3_parity.which_slice)) | |
1160 | goto out; | |
1161 | ||
e3689190 BW |
1162 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
1163 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
1164 | POSTING_READ(GEN7_MISCCPCTL); | |
1165 | ||
35a85ac6 BW |
1166 | while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { |
1167 | u32 reg; | |
e3689190 | 1168 | |
35a85ac6 BW |
1169 | slice--; |
1170 | if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev))) | |
1171 | break; | |
e3689190 | 1172 | |
35a85ac6 | 1173 | dev_priv->l3_parity.which_slice &= ~(1<<slice); |
e3689190 | 1174 | |
35a85ac6 | 1175 | reg = GEN7_L3CDERRST1 + (slice * 0x200); |
e3689190 | 1176 | |
35a85ac6 BW |
1177 | error_status = I915_READ(reg); |
1178 | row = GEN7_PARITY_ERROR_ROW(error_status); | |
1179 | bank = GEN7_PARITY_ERROR_BANK(error_status); | |
1180 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); | |
1181 | ||
1182 | I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); | |
1183 | POSTING_READ(reg); | |
1184 | ||
1185 | parity_event[0] = I915_L3_PARITY_UEVENT "=1"; | |
1186 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); | |
1187 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); | |
1188 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); | |
1189 | parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); | |
1190 | parity_event[5] = NULL; | |
1191 | ||
5bdebb18 | 1192 | kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj, |
35a85ac6 | 1193 | KOBJ_CHANGE, parity_event); |
e3689190 | 1194 | |
35a85ac6 BW |
1195 | DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", |
1196 | slice, row, bank, subbank); | |
e3689190 | 1197 | |
35a85ac6 BW |
1198 | kfree(parity_event[4]); |
1199 | kfree(parity_event[3]); | |
1200 | kfree(parity_event[2]); | |
1201 | kfree(parity_event[1]); | |
1202 | } | |
e3689190 | 1203 | |
35a85ac6 | 1204 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
e3689190 | 1205 | |
35a85ac6 BW |
1206 | out: |
1207 | WARN_ON(dev_priv->l3_parity.which_slice); | |
1208 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1209 | ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev)); | |
1210 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1211 | ||
1212 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
e3689190 BW |
1213 | } |
1214 | ||
35a85ac6 | 1215 | static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir) |
e3689190 | 1216 | { |
2d1013dd | 1217 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3689190 | 1218 | |
040d2baa | 1219 | if (!HAS_L3_DPF(dev)) |
e3689190 BW |
1220 | return; |
1221 | ||
d0ecd7e2 | 1222 | spin_lock(&dev_priv->irq_lock); |
35a85ac6 | 1223 | ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev)); |
d0ecd7e2 | 1224 | spin_unlock(&dev_priv->irq_lock); |
e3689190 | 1225 | |
35a85ac6 BW |
1226 | iir &= GT_PARITY_ERROR(dev); |
1227 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) | |
1228 | dev_priv->l3_parity.which_slice |= 1 << 1; | |
1229 | ||
1230 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) | |
1231 | dev_priv->l3_parity.which_slice |= 1 << 0; | |
1232 | ||
a4da4fa4 | 1233 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
e3689190 BW |
1234 | } |
1235 | ||
f1af8fc1 PZ |
1236 | static void ilk_gt_irq_handler(struct drm_device *dev, |
1237 | struct drm_i915_private *dev_priv, | |
1238 | u32 gt_iir) | |
1239 | { | |
1240 | if (gt_iir & | |
1241 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
1242 | notify_ring(dev, &dev_priv->ring[RCS]); | |
1243 | if (gt_iir & ILK_BSD_USER_INTERRUPT) | |
1244 | notify_ring(dev, &dev_priv->ring[VCS]); | |
1245 | } | |
1246 | ||
e7b4c6b1 DV |
1247 | static void snb_gt_irq_handler(struct drm_device *dev, |
1248 | struct drm_i915_private *dev_priv, | |
1249 | u32 gt_iir) | |
1250 | { | |
1251 | ||
cc609d5d BW |
1252 | if (gt_iir & |
1253 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
e7b4c6b1 | 1254 | notify_ring(dev, &dev_priv->ring[RCS]); |
cc609d5d | 1255 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
e7b4c6b1 | 1256 | notify_ring(dev, &dev_priv->ring[VCS]); |
cc609d5d | 1257 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
e7b4c6b1 DV |
1258 | notify_ring(dev, &dev_priv->ring[BCS]); |
1259 | ||
cc609d5d BW |
1260 | if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | |
1261 | GT_BSD_CS_ERROR_INTERRUPT | | |
1262 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) { | |
58174462 MK |
1263 | i915_handle_error(dev, false, "GT error interrupt 0x%08x", |
1264 | gt_iir); | |
e7b4c6b1 | 1265 | } |
e3689190 | 1266 | |
35a85ac6 BW |
1267 | if (gt_iir & GT_PARITY_ERROR(dev)) |
1268 | ivybridge_parity_error_irq_handler(dev, gt_iir); | |
e7b4c6b1 DV |
1269 | } |
1270 | ||
abd58f01 BW |
1271 | static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev, |
1272 | struct drm_i915_private *dev_priv, | |
1273 | u32 master_ctl) | |
1274 | { | |
1275 | u32 rcs, bcs, vcs; | |
1276 | uint32_t tmp = 0; | |
1277 | irqreturn_t ret = IRQ_NONE; | |
1278 | ||
1279 | if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { | |
1280 | tmp = I915_READ(GEN8_GT_IIR(0)); | |
1281 | if (tmp) { | |
1282 | ret = IRQ_HANDLED; | |
1283 | rcs = tmp >> GEN8_RCS_IRQ_SHIFT; | |
1284 | bcs = tmp >> GEN8_BCS_IRQ_SHIFT; | |
1285 | if (rcs & GT_RENDER_USER_INTERRUPT) | |
1286 | notify_ring(dev, &dev_priv->ring[RCS]); | |
1287 | if (bcs & GT_RENDER_USER_INTERRUPT) | |
1288 | notify_ring(dev, &dev_priv->ring[BCS]); | |
1289 | I915_WRITE(GEN8_GT_IIR(0), tmp); | |
1290 | } else | |
1291 | DRM_ERROR("The master control interrupt lied (GT0)!\n"); | |
1292 | } | |
1293 | ||
85f9b5f9 | 1294 | if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) { |
abd58f01 BW |
1295 | tmp = I915_READ(GEN8_GT_IIR(1)); |
1296 | if (tmp) { | |
1297 | ret = IRQ_HANDLED; | |
1298 | vcs = tmp >> GEN8_VCS1_IRQ_SHIFT; | |
1299 | if (vcs & GT_RENDER_USER_INTERRUPT) | |
1300 | notify_ring(dev, &dev_priv->ring[VCS]); | |
85f9b5f9 ZY |
1301 | vcs = tmp >> GEN8_VCS2_IRQ_SHIFT; |
1302 | if (vcs & GT_RENDER_USER_INTERRUPT) | |
1303 | notify_ring(dev, &dev_priv->ring[VCS2]); | |
abd58f01 BW |
1304 | I915_WRITE(GEN8_GT_IIR(1), tmp); |
1305 | } else | |
1306 | DRM_ERROR("The master control interrupt lied (GT1)!\n"); | |
1307 | } | |
1308 | ||
1309 | if (master_ctl & GEN8_GT_VECS_IRQ) { | |
1310 | tmp = I915_READ(GEN8_GT_IIR(3)); | |
1311 | if (tmp) { | |
1312 | ret = IRQ_HANDLED; | |
1313 | vcs = tmp >> GEN8_VECS_IRQ_SHIFT; | |
1314 | if (vcs & GT_RENDER_USER_INTERRUPT) | |
1315 | notify_ring(dev, &dev_priv->ring[VECS]); | |
1316 | I915_WRITE(GEN8_GT_IIR(3), tmp); | |
1317 | } else | |
1318 | DRM_ERROR("The master control interrupt lied (GT3)!\n"); | |
1319 | } | |
1320 | ||
1321 | return ret; | |
1322 | } | |
1323 | ||
b543fb04 EE |
1324 | #define HPD_STORM_DETECT_PERIOD 1000 |
1325 | #define HPD_STORM_THRESHOLD 5 | |
1326 | ||
10a504de | 1327 | static inline void intel_hpd_irq_handler(struct drm_device *dev, |
22062dba DV |
1328 | u32 hotplug_trigger, |
1329 | const u32 *hpd) | |
b543fb04 | 1330 | { |
2d1013dd | 1331 | struct drm_i915_private *dev_priv = dev->dev_private; |
b543fb04 | 1332 | int i; |
10a504de | 1333 | bool storm_detected = false; |
b543fb04 | 1334 | |
91d131d2 DV |
1335 | if (!hotplug_trigger) |
1336 | return; | |
1337 | ||
cc9bd499 ID |
1338 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
1339 | hotplug_trigger); | |
1340 | ||
b5ea2d56 | 1341 | spin_lock(&dev_priv->irq_lock); |
b543fb04 | 1342 | for (i = 1; i < HPD_NUM_PINS; i++) { |
821450c6 | 1343 | |
3ff04a16 DV |
1344 | if (hpd[i] & hotplug_trigger && |
1345 | dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) { | |
1346 | /* | |
1347 | * On GMCH platforms the interrupt mask bits only | |
1348 | * prevent irq generation, not the setting of the | |
1349 | * hotplug bits itself. So only WARN about unexpected | |
1350 | * interrupts on saner platforms. | |
1351 | */ | |
1352 | WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev), | |
1353 | "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n", | |
1354 | hotplug_trigger, i, hpd[i]); | |
1355 | ||
1356 | continue; | |
1357 | } | |
b8f102e8 | 1358 | |
b543fb04 EE |
1359 | if (!(hpd[i] & hotplug_trigger) || |
1360 | dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED) | |
1361 | continue; | |
1362 | ||
bc5ead8c | 1363 | dev_priv->hpd_event_bits |= (1 << i); |
b543fb04 EE |
1364 | if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies, |
1365 | dev_priv->hpd_stats[i].hpd_last_jiffies | |
1366 | + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) { | |
1367 | dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies; | |
1368 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
b8f102e8 | 1369 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i); |
b543fb04 EE |
1370 | } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) { |
1371 | dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED; | |
142e2398 | 1372 | dev_priv->hpd_event_bits &= ~(1 << i); |
b543fb04 | 1373 | DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i); |
10a504de | 1374 | storm_detected = true; |
b543fb04 EE |
1375 | } else { |
1376 | dev_priv->hpd_stats[i].hpd_cnt++; | |
b8f102e8 EE |
1377 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i, |
1378 | dev_priv->hpd_stats[i].hpd_cnt); | |
b543fb04 EE |
1379 | } |
1380 | } | |
1381 | ||
10a504de DV |
1382 | if (storm_detected) |
1383 | dev_priv->display.hpd_irq_setup(dev); | |
b5ea2d56 | 1384 | spin_unlock(&dev_priv->irq_lock); |
5876fa0d | 1385 | |
645416f5 DV |
1386 | /* |
1387 | * Our hotplug handler can grab modeset locks (by calling down into the | |
1388 | * fb helpers). Hence it must not be run on our own dev-priv->wq work | |
1389 | * queue for otherwise the flush_work in the pageflip code will | |
1390 | * deadlock. | |
1391 | */ | |
1392 | schedule_work(&dev_priv->hotplug_work); | |
b543fb04 EE |
1393 | } |
1394 | ||
515ac2bb DV |
1395 | static void gmbus_irq_handler(struct drm_device *dev) |
1396 | { | |
2d1013dd | 1397 | struct drm_i915_private *dev_priv = dev->dev_private; |
28c70f16 | 1398 | |
28c70f16 | 1399 | wake_up_all(&dev_priv->gmbus_wait_queue); |
515ac2bb DV |
1400 | } |
1401 | ||
ce99c256 DV |
1402 | static void dp_aux_irq_handler(struct drm_device *dev) |
1403 | { | |
2d1013dd | 1404 | struct drm_i915_private *dev_priv = dev->dev_private; |
9ee32fea | 1405 | |
9ee32fea | 1406 | wake_up_all(&dev_priv->gmbus_wait_queue); |
ce99c256 DV |
1407 | } |
1408 | ||
8bf1e9f1 | 1409 | #if defined(CONFIG_DEBUG_FS) |
277de95e DV |
1410 | static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, |
1411 | uint32_t crc0, uint32_t crc1, | |
1412 | uint32_t crc2, uint32_t crc3, | |
1413 | uint32_t crc4) | |
8bf1e9f1 SH |
1414 | { |
1415 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1416 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; | |
1417 | struct intel_pipe_crc_entry *entry; | |
ac2300d4 | 1418 | int head, tail; |
b2c88f5b | 1419 | |
d538bbdf DL |
1420 | spin_lock(&pipe_crc->lock); |
1421 | ||
0c912c79 | 1422 | if (!pipe_crc->entries) { |
d538bbdf | 1423 | spin_unlock(&pipe_crc->lock); |
0c912c79 DL |
1424 | DRM_ERROR("spurious interrupt\n"); |
1425 | return; | |
1426 | } | |
1427 | ||
d538bbdf DL |
1428 | head = pipe_crc->head; |
1429 | tail = pipe_crc->tail; | |
b2c88f5b DL |
1430 | |
1431 | if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { | |
d538bbdf | 1432 | spin_unlock(&pipe_crc->lock); |
b2c88f5b DL |
1433 | DRM_ERROR("CRC buffer overflowing\n"); |
1434 | return; | |
1435 | } | |
1436 | ||
1437 | entry = &pipe_crc->entries[head]; | |
8bf1e9f1 | 1438 | |
8bc5e955 | 1439 | entry->frame = dev->driver->get_vblank_counter(dev, pipe); |
eba94eb9 DV |
1440 | entry->crc[0] = crc0; |
1441 | entry->crc[1] = crc1; | |
1442 | entry->crc[2] = crc2; | |
1443 | entry->crc[3] = crc3; | |
1444 | entry->crc[4] = crc4; | |
b2c88f5b DL |
1445 | |
1446 | head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
d538bbdf DL |
1447 | pipe_crc->head = head; |
1448 | ||
1449 | spin_unlock(&pipe_crc->lock); | |
07144428 DL |
1450 | |
1451 | wake_up_interruptible(&pipe_crc->wq); | |
8bf1e9f1 | 1452 | } |
277de95e DV |
1453 | #else |
1454 | static inline void | |
1455 | display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, | |
1456 | uint32_t crc0, uint32_t crc1, | |
1457 | uint32_t crc2, uint32_t crc3, | |
1458 | uint32_t crc4) {} | |
1459 | #endif | |
1460 | ||
eba94eb9 | 1461 | |
277de95e | 1462 | static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5a69b89f DV |
1463 | { |
1464 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1465 | ||
277de95e DV |
1466 | display_pipe_crc_irq_handler(dev, pipe, |
1467 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1468 | 0, 0, 0, 0); | |
5a69b89f DV |
1469 | } |
1470 | ||
277de95e | 1471 | static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
eba94eb9 DV |
1472 | { |
1473 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1474 | ||
277de95e DV |
1475 | display_pipe_crc_irq_handler(dev, pipe, |
1476 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1477 | I915_READ(PIPE_CRC_RES_2_IVB(pipe)), | |
1478 | I915_READ(PIPE_CRC_RES_3_IVB(pipe)), | |
1479 | I915_READ(PIPE_CRC_RES_4_IVB(pipe)), | |
1480 | I915_READ(PIPE_CRC_RES_5_IVB(pipe))); | |
eba94eb9 | 1481 | } |
5b3a856b | 1482 | |
277de95e | 1483 | static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5b3a856b DV |
1484 | { |
1485 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0b5c5ed0 DV |
1486 | uint32_t res1, res2; |
1487 | ||
1488 | if (INTEL_INFO(dev)->gen >= 3) | |
1489 | res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); | |
1490 | else | |
1491 | res1 = 0; | |
1492 | ||
1493 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
1494 | res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); | |
1495 | else | |
1496 | res2 = 0; | |
5b3a856b | 1497 | |
277de95e DV |
1498 | display_pipe_crc_irq_handler(dev, pipe, |
1499 | I915_READ(PIPE_CRC_RES_RED(pipe)), | |
1500 | I915_READ(PIPE_CRC_RES_GREEN(pipe)), | |
1501 | I915_READ(PIPE_CRC_RES_BLUE(pipe)), | |
1502 | res1, res2); | |
5b3a856b | 1503 | } |
8bf1e9f1 | 1504 | |
1403c0d4 PZ |
1505 | /* The RPS events need forcewake, so we add them to a work queue and mask their |
1506 | * IMR bits until the work is done. Other interrupts can be processed without | |
1507 | * the work queue. */ | |
1508 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) | |
baf02a1f | 1509 | { |
a6706b45 | 1510 | if (pm_iir & dev_priv->pm_rps_events) { |
59cdb63d | 1511 | spin_lock(&dev_priv->irq_lock); |
a6706b45 D |
1512 | dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; |
1513 | snb_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); | |
59cdb63d | 1514 | spin_unlock(&dev_priv->irq_lock); |
2adbee62 DV |
1515 | |
1516 | queue_work(dev_priv->wq, &dev_priv->rps.work); | |
baf02a1f | 1517 | } |
baf02a1f | 1518 | |
1403c0d4 PZ |
1519 | if (HAS_VEBOX(dev_priv->dev)) { |
1520 | if (pm_iir & PM_VEBOX_USER_INTERRUPT) | |
1521 | notify_ring(dev_priv->dev, &dev_priv->ring[VECS]); | |
12638c57 | 1522 | |
1403c0d4 | 1523 | if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) { |
58174462 MK |
1524 | i915_handle_error(dev_priv->dev, false, |
1525 | "VEBOX CS error interrupt 0x%08x", | |
1526 | pm_iir); | |
1403c0d4 | 1527 | } |
12638c57 | 1528 | } |
baf02a1f BW |
1529 | } |
1530 | ||
c1874ed7 ID |
1531 | static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir) |
1532 | { | |
1533 | struct drm_i915_private *dev_priv = dev->dev_private; | |
91d181dd | 1534 | u32 pipe_stats[I915_MAX_PIPES] = { }; |
c1874ed7 ID |
1535 | int pipe; |
1536 | ||
58ead0d7 | 1537 | spin_lock(&dev_priv->irq_lock); |
c1874ed7 | 1538 | for_each_pipe(pipe) { |
91d181dd | 1539 | int reg; |
bbb5eebf | 1540 | u32 mask, iir_bit = 0; |
91d181dd | 1541 | |
bbb5eebf DV |
1542 | /* |
1543 | * PIPESTAT bits get signalled even when the interrupt is | |
1544 | * disabled with the mask bits, and some of the status bits do | |
1545 | * not generate interrupts at all (like the underrun bit). Hence | |
1546 | * we need to be careful that we only handle what we want to | |
1547 | * handle. | |
1548 | */ | |
1549 | mask = 0; | |
1550 | if (__cpu_fifo_underrun_reporting_enabled(dev, pipe)) | |
1551 | mask |= PIPE_FIFO_UNDERRUN_STATUS; | |
1552 | ||
1553 | switch (pipe) { | |
1554 | case PIPE_A: | |
1555 | iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; | |
1556 | break; | |
1557 | case PIPE_B: | |
1558 | iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
1559 | break; | |
1560 | } | |
1561 | if (iir & iir_bit) | |
1562 | mask |= dev_priv->pipestat_irq_mask[pipe]; | |
1563 | ||
1564 | if (!mask) | |
91d181dd ID |
1565 | continue; |
1566 | ||
1567 | reg = PIPESTAT(pipe); | |
bbb5eebf DV |
1568 | mask |= PIPESTAT_INT_ENABLE_MASK; |
1569 | pipe_stats[pipe] = I915_READ(reg) & mask; | |
c1874ed7 ID |
1570 | |
1571 | /* | |
1572 | * Clear the PIPE*STAT regs before the IIR | |
1573 | */ | |
91d181dd ID |
1574 | if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS | |
1575 | PIPESTAT_INT_STATUS_MASK)) | |
c1874ed7 ID |
1576 | I915_WRITE(reg, pipe_stats[pipe]); |
1577 | } | |
58ead0d7 | 1578 | spin_unlock(&dev_priv->irq_lock); |
c1874ed7 ID |
1579 | |
1580 | for_each_pipe(pipe) { | |
1581 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) | |
1582 | drm_handle_vblank(dev, pipe); | |
1583 | ||
579a9b0e | 1584 | if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) { |
c1874ed7 ID |
1585 | intel_prepare_page_flip(dev, pipe); |
1586 | intel_finish_page_flip(dev, pipe); | |
1587 | } | |
1588 | ||
1589 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
1590 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
1591 | ||
1592 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && | |
1593 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
1594 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); | |
1595 | } | |
1596 | ||
1597 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) | |
1598 | gmbus_irq_handler(dev); | |
1599 | } | |
1600 | ||
16c6c56b VS |
1601 | static void i9xx_hpd_irq_handler(struct drm_device *dev) |
1602 | { | |
1603 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1604 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
1605 | ||
1606 | if (IS_G4X(dev)) { | |
1607 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; | |
1608 | ||
1609 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_g4x); | |
1610 | } else { | |
1611 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; | |
1612 | ||
1613 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); | |
1614 | } | |
1615 | ||
1616 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && | |
1617 | hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) | |
1618 | dp_aux_irq_handler(dev); | |
1619 | ||
1620 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
1621 | /* | |
1622 | * Make sure hotplug status is cleared before we clear IIR, or else we | |
1623 | * may miss hotplug events. | |
1624 | */ | |
1625 | POSTING_READ(PORT_HOTPLUG_STAT); | |
1626 | } | |
1627 | ||
ff1f525e | 1628 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
7e231dbe JB |
1629 | { |
1630 | struct drm_device *dev = (struct drm_device *) arg; | |
2d1013dd | 1631 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
1632 | u32 iir, gt_iir, pm_iir; |
1633 | irqreturn_t ret = IRQ_NONE; | |
7e231dbe | 1634 | |
7e231dbe JB |
1635 | while (true) { |
1636 | iir = I915_READ(VLV_IIR); | |
1637 | gt_iir = I915_READ(GTIIR); | |
1638 | pm_iir = I915_READ(GEN6_PMIIR); | |
1639 | ||
1640 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) | |
1641 | goto out; | |
1642 | ||
1643 | ret = IRQ_HANDLED; | |
1644 | ||
e7b4c6b1 | 1645 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
7e231dbe | 1646 | |
c1874ed7 | 1647 | valleyview_pipestat_irq_handler(dev, iir); |
31acc7f5 | 1648 | |
7e231dbe | 1649 | /* Consume port. Then clear IIR or we'll miss events */ |
16c6c56b VS |
1650 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
1651 | i9xx_hpd_irq_handler(dev); | |
7e231dbe | 1652 | |
60611c13 | 1653 | if (pm_iir) |
d0ecd7e2 | 1654 | gen6_rps_irq_handler(dev_priv, pm_iir); |
7e231dbe JB |
1655 | |
1656 | I915_WRITE(GTIIR, gt_iir); | |
1657 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
1658 | I915_WRITE(VLV_IIR, iir); | |
1659 | } | |
1660 | ||
1661 | out: | |
1662 | return ret; | |
1663 | } | |
1664 | ||
23e81d69 | 1665 | static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) |
776ad806 | 1666 | { |
2d1013dd | 1667 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 1668 | int pipe; |
b543fb04 | 1669 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; |
776ad806 | 1670 | |
91d131d2 DV |
1671 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx); |
1672 | ||
cfc33bf7 VS |
1673 | if (pch_iir & SDE_AUDIO_POWER_MASK) { |
1674 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> | |
1675 | SDE_AUDIO_POWER_SHIFT); | |
776ad806 | 1676 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
cfc33bf7 VS |
1677 | port_name(port)); |
1678 | } | |
776ad806 | 1679 | |
ce99c256 DV |
1680 | if (pch_iir & SDE_AUX_MASK) |
1681 | dp_aux_irq_handler(dev); | |
1682 | ||
776ad806 | 1683 | if (pch_iir & SDE_GMBUS) |
515ac2bb | 1684 | gmbus_irq_handler(dev); |
776ad806 JB |
1685 | |
1686 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
1687 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
1688 | ||
1689 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
1690 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
1691 | ||
1692 | if (pch_iir & SDE_POISON) | |
1693 | DRM_ERROR("PCH poison interrupt\n"); | |
1694 | ||
9db4a9c7 JB |
1695 | if (pch_iir & SDE_FDI_MASK) |
1696 | for_each_pipe(pipe) | |
1697 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", | |
1698 | pipe_name(pipe), | |
1699 | I915_READ(FDI_RX_IIR(pipe))); | |
776ad806 JB |
1700 | |
1701 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
1702 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
1703 | ||
1704 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
1705 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
1706 | ||
776ad806 | 1707 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
8664281b PZ |
1708 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, |
1709 | false)) | |
fc2c807b | 1710 | DRM_ERROR("PCH transcoder A FIFO underrun\n"); |
8664281b PZ |
1711 | |
1712 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
1713 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, | |
1714 | false)) | |
fc2c807b | 1715 | DRM_ERROR("PCH transcoder B FIFO underrun\n"); |
8664281b PZ |
1716 | } |
1717 | ||
1718 | static void ivb_err_int_handler(struct drm_device *dev) | |
1719 | { | |
1720 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1721 | u32 err_int = I915_READ(GEN7_ERR_INT); | |
5a69b89f | 1722 | enum pipe pipe; |
8664281b | 1723 | |
de032bf4 PZ |
1724 | if (err_int & ERR_INT_POISON) |
1725 | DRM_ERROR("Poison interrupt\n"); | |
1726 | ||
5a69b89f DV |
1727 | for_each_pipe(pipe) { |
1728 | if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) { | |
1729 | if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, | |
1730 | false)) | |
fc2c807b VS |
1731 | DRM_ERROR("Pipe %c FIFO underrun\n", |
1732 | pipe_name(pipe)); | |
5a69b89f | 1733 | } |
8bf1e9f1 | 1734 | |
5a69b89f DV |
1735 | if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { |
1736 | if (IS_IVYBRIDGE(dev)) | |
277de95e | 1737 | ivb_pipe_crc_irq_handler(dev, pipe); |
5a69b89f | 1738 | else |
277de95e | 1739 | hsw_pipe_crc_irq_handler(dev, pipe); |
5a69b89f DV |
1740 | } |
1741 | } | |
8bf1e9f1 | 1742 | |
8664281b PZ |
1743 | I915_WRITE(GEN7_ERR_INT, err_int); |
1744 | } | |
1745 | ||
1746 | static void cpt_serr_int_handler(struct drm_device *dev) | |
1747 | { | |
1748 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1749 | u32 serr_int = I915_READ(SERR_INT); | |
1750 | ||
de032bf4 PZ |
1751 | if (serr_int & SERR_INT_POISON) |
1752 | DRM_ERROR("PCH poison interrupt\n"); | |
1753 | ||
8664281b PZ |
1754 | if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) |
1755 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, | |
1756 | false)) | |
fc2c807b | 1757 | DRM_ERROR("PCH transcoder A FIFO underrun\n"); |
8664281b PZ |
1758 | |
1759 | if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) | |
1760 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, | |
1761 | false)) | |
fc2c807b | 1762 | DRM_ERROR("PCH transcoder B FIFO underrun\n"); |
8664281b PZ |
1763 | |
1764 | if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) | |
1765 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C, | |
1766 | false)) | |
fc2c807b | 1767 | DRM_ERROR("PCH transcoder C FIFO underrun\n"); |
8664281b PZ |
1768 | |
1769 | I915_WRITE(SERR_INT, serr_int); | |
776ad806 JB |
1770 | } |
1771 | ||
23e81d69 AJ |
1772 | static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) |
1773 | { | |
2d1013dd | 1774 | struct drm_i915_private *dev_priv = dev->dev_private; |
23e81d69 | 1775 | int pipe; |
b543fb04 | 1776 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; |
23e81d69 | 1777 | |
91d131d2 DV |
1778 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt); |
1779 | ||
cfc33bf7 VS |
1780 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { |
1781 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> | |
1782 | SDE_AUDIO_POWER_SHIFT_CPT); | |
1783 | DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", | |
1784 | port_name(port)); | |
1785 | } | |
23e81d69 AJ |
1786 | |
1787 | if (pch_iir & SDE_AUX_MASK_CPT) | |
ce99c256 | 1788 | dp_aux_irq_handler(dev); |
23e81d69 AJ |
1789 | |
1790 | if (pch_iir & SDE_GMBUS_CPT) | |
515ac2bb | 1791 | gmbus_irq_handler(dev); |
23e81d69 AJ |
1792 | |
1793 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) | |
1794 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); | |
1795 | ||
1796 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) | |
1797 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); | |
1798 | ||
1799 | if (pch_iir & SDE_FDI_MASK_CPT) | |
1800 | for_each_pipe(pipe) | |
1801 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", | |
1802 | pipe_name(pipe), | |
1803 | I915_READ(FDI_RX_IIR(pipe))); | |
8664281b PZ |
1804 | |
1805 | if (pch_iir & SDE_ERROR_CPT) | |
1806 | cpt_serr_int_handler(dev); | |
23e81d69 AJ |
1807 | } |
1808 | ||
c008bc6e PZ |
1809 | static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) |
1810 | { | |
1811 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40da17c2 | 1812 | enum pipe pipe; |
c008bc6e PZ |
1813 | |
1814 | if (de_iir & DE_AUX_CHANNEL_A) | |
1815 | dp_aux_irq_handler(dev); | |
1816 | ||
1817 | if (de_iir & DE_GSE) | |
1818 | intel_opregion_asle_intr(dev); | |
1819 | ||
c008bc6e PZ |
1820 | if (de_iir & DE_POISON) |
1821 | DRM_ERROR("Poison interrupt\n"); | |
1822 | ||
40da17c2 DV |
1823 | for_each_pipe(pipe) { |
1824 | if (de_iir & DE_PIPE_VBLANK(pipe)) | |
1825 | drm_handle_vblank(dev, pipe); | |
5b3a856b | 1826 | |
40da17c2 DV |
1827 | if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) |
1828 | if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
fc2c807b VS |
1829 | DRM_ERROR("Pipe %c FIFO underrun\n", |
1830 | pipe_name(pipe)); | |
5b3a856b | 1831 | |
40da17c2 DV |
1832 | if (de_iir & DE_PIPE_CRC_DONE(pipe)) |
1833 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
c008bc6e | 1834 | |
40da17c2 DV |
1835 | /* plane/pipes map 1:1 on ilk+ */ |
1836 | if (de_iir & DE_PLANE_FLIP_DONE(pipe)) { | |
1837 | intel_prepare_page_flip(dev, pipe); | |
1838 | intel_finish_page_flip_plane(dev, pipe); | |
1839 | } | |
c008bc6e PZ |
1840 | } |
1841 | ||
1842 | /* check event from PCH */ | |
1843 | if (de_iir & DE_PCH_EVENT) { | |
1844 | u32 pch_iir = I915_READ(SDEIIR); | |
1845 | ||
1846 | if (HAS_PCH_CPT(dev)) | |
1847 | cpt_irq_handler(dev, pch_iir); | |
1848 | else | |
1849 | ibx_irq_handler(dev, pch_iir); | |
1850 | ||
1851 | /* should clear PCH hotplug event before clear CPU irq */ | |
1852 | I915_WRITE(SDEIIR, pch_iir); | |
1853 | } | |
1854 | ||
1855 | if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) | |
1856 | ironlake_rps_change_irq_handler(dev); | |
1857 | } | |
1858 | ||
9719fb98 PZ |
1859 | static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir) |
1860 | { | |
1861 | struct drm_i915_private *dev_priv = dev->dev_private; | |
07d27e20 | 1862 | enum pipe pipe; |
9719fb98 PZ |
1863 | |
1864 | if (de_iir & DE_ERR_INT_IVB) | |
1865 | ivb_err_int_handler(dev); | |
1866 | ||
1867 | if (de_iir & DE_AUX_CHANNEL_A_IVB) | |
1868 | dp_aux_irq_handler(dev); | |
1869 | ||
1870 | if (de_iir & DE_GSE_IVB) | |
1871 | intel_opregion_asle_intr(dev); | |
1872 | ||
07d27e20 DL |
1873 | for_each_pipe(pipe) { |
1874 | if (de_iir & (DE_PIPE_VBLANK_IVB(pipe))) | |
1875 | drm_handle_vblank(dev, pipe); | |
40da17c2 DV |
1876 | |
1877 | /* plane/pipes map 1:1 on ilk+ */ | |
07d27e20 DL |
1878 | if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) { |
1879 | intel_prepare_page_flip(dev, pipe); | |
1880 | intel_finish_page_flip_plane(dev, pipe); | |
9719fb98 PZ |
1881 | } |
1882 | } | |
1883 | ||
1884 | /* check event from PCH */ | |
1885 | if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) { | |
1886 | u32 pch_iir = I915_READ(SDEIIR); | |
1887 | ||
1888 | cpt_irq_handler(dev, pch_iir); | |
1889 | ||
1890 | /* clear PCH hotplug event before clear CPU irq */ | |
1891 | I915_WRITE(SDEIIR, pch_iir); | |
1892 | } | |
1893 | } | |
1894 | ||
f1af8fc1 | 1895 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
b1f14ad0 JB |
1896 | { |
1897 | struct drm_device *dev = (struct drm_device *) arg; | |
2d1013dd | 1898 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1af8fc1 | 1899 | u32 de_iir, gt_iir, de_ier, sde_ier = 0; |
0e43406b | 1900 | irqreturn_t ret = IRQ_NONE; |
b1f14ad0 | 1901 | |
8664281b PZ |
1902 | /* We get interrupts on unclaimed registers, so check for this before we |
1903 | * do any I915_{READ,WRITE}. */ | |
907b28c5 | 1904 | intel_uncore_check_errors(dev); |
8664281b | 1905 | |
b1f14ad0 JB |
1906 | /* disable master interrupt before clearing iir */ |
1907 | de_ier = I915_READ(DEIER); | |
1908 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
23a78516 | 1909 | POSTING_READ(DEIER); |
b1f14ad0 | 1910 | |
44498aea PZ |
1911 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
1912 | * interrupts will will be stored on its back queue, and then we'll be | |
1913 | * able to process them after we restore SDEIER (as soon as we restore | |
1914 | * it, we'll get an interrupt if SDEIIR still has something to process | |
1915 | * due to its back queue). */ | |
ab5c608b BW |
1916 | if (!HAS_PCH_NOP(dev)) { |
1917 | sde_ier = I915_READ(SDEIER); | |
1918 | I915_WRITE(SDEIER, 0); | |
1919 | POSTING_READ(SDEIER); | |
1920 | } | |
44498aea | 1921 | |
b1f14ad0 | 1922 | gt_iir = I915_READ(GTIIR); |
0e43406b | 1923 | if (gt_iir) { |
d8fc8a47 | 1924 | if (INTEL_INFO(dev)->gen >= 6) |
f1af8fc1 | 1925 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
d8fc8a47 PZ |
1926 | else |
1927 | ilk_gt_irq_handler(dev, dev_priv, gt_iir); | |
0e43406b CW |
1928 | I915_WRITE(GTIIR, gt_iir); |
1929 | ret = IRQ_HANDLED; | |
b1f14ad0 JB |
1930 | } |
1931 | ||
0e43406b CW |
1932 | de_iir = I915_READ(DEIIR); |
1933 | if (de_iir) { | |
f1af8fc1 PZ |
1934 | if (INTEL_INFO(dev)->gen >= 7) |
1935 | ivb_display_irq_handler(dev, de_iir); | |
1936 | else | |
1937 | ilk_display_irq_handler(dev, de_iir); | |
0e43406b CW |
1938 | I915_WRITE(DEIIR, de_iir); |
1939 | ret = IRQ_HANDLED; | |
b1f14ad0 JB |
1940 | } |
1941 | ||
f1af8fc1 PZ |
1942 | if (INTEL_INFO(dev)->gen >= 6) { |
1943 | u32 pm_iir = I915_READ(GEN6_PMIIR); | |
1944 | if (pm_iir) { | |
1403c0d4 | 1945 | gen6_rps_irq_handler(dev_priv, pm_iir); |
f1af8fc1 PZ |
1946 | I915_WRITE(GEN6_PMIIR, pm_iir); |
1947 | ret = IRQ_HANDLED; | |
1948 | } | |
0e43406b | 1949 | } |
b1f14ad0 | 1950 | |
b1f14ad0 JB |
1951 | I915_WRITE(DEIER, de_ier); |
1952 | POSTING_READ(DEIER); | |
ab5c608b BW |
1953 | if (!HAS_PCH_NOP(dev)) { |
1954 | I915_WRITE(SDEIER, sde_ier); | |
1955 | POSTING_READ(SDEIER); | |
1956 | } | |
b1f14ad0 JB |
1957 | |
1958 | return ret; | |
1959 | } | |
1960 | ||
abd58f01 BW |
1961 | static irqreturn_t gen8_irq_handler(int irq, void *arg) |
1962 | { | |
1963 | struct drm_device *dev = arg; | |
1964 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1965 | u32 master_ctl; | |
1966 | irqreturn_t ret = IRQ_NONE; | |
1967 | uint32_t tmp = 0; | |
c42664cc | 1968 | enum pipe pipe; |
abd58f01 | 1969 | |
abd58f01 BW |
1970 | master_ctl = I915_READ(GEN8_MASTER_IRQ); |
1971 | master_ctl &= ~GEN8_MASTER_IRQ_CONTROL; | |
1972 | if (!master_ctl) | |
1973 | return IRQ_NONE; | |
1974 | ||
1975 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
1976 | POSTING_READ(GEN8_MASTER_IRQ); | |
1977 | ||
1978 | ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl); | |
1979 | ||
1980 | if (master_ctl & GEN8_DE_MISC_IRQ) { | |
1981 | tmp = I915_READ(GEN8_DE_MISC_IIR); | |
1982 | if (tmp & GEN8_DE_MISC_GSE) | |
1983 | intel_opregion_asle_intr(dev); | |
1984 | else if (tmp) | |
1985 | DRM_ERROR("Unexpected DE Misc interrupt\n"); | |
1986 | else | |
1987 | DRM_ERROR("The master control interrupt lied (DE MISC)!\n"); | |
1988 | ||
1989 | if (tmp) { | |
1990 | I915_WRITE(GEN8_DE_MISC_IIR, tmp); | |
1991 | ret = IRQ_HANDLED; | |
1992 | } | |
1993 | } | |
1994 | ||
6d766f02 DV |
1995 | if (master_ctl & GEN8_DE_PORT_IRQ) { |
1996 | tmp = I915_READ(GEN8_DE_PORT_IIR); | |
1997 | if (tmp & GEN8_AUX_CHANNEL_A) | |
1998 | dp_aux_irq_handler(dev); | |
1999 | else if (tmp) | |
2000 | DRM_ERROR("Unexpected DE Port interrupt\n"); | |
2001 | else | |
2002 | DRM_ERROR("The master control interrupt lied (DE PORT)!\n"); | |
2003 | ||
2004 | if (tmp) { | |
2005 | I915_WRITE(GEN8_DE_PORT_IIR, tmp); | |
2006 | ret = IRQ_HANDLED; | |
2007 | } | |
2008 | } | |
2009 | ||
c42664cc DV |
2010 | for_each_pipe(pipe) { |
2011 | uint32_t pipe_iir; | |
abd58f01 | 2012 | |
c42664cc DV |
2013 | if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) |
2014 | continue; | |
abd58f01 | 2015 | |
c42664cc DV |
2016 | pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); |
2017 | if (pipe_iir & GEN8_PIPE_VBLANK) | |
2018 | drm_handle_vblank(dev, pipe); | |
abd58f01 | 2019 | |
d0e1f1cb | 2020 | if (pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE) { |
c42664cc DV |
2021 | intel_prepare_page_flip(dev, pipe); |
2022 | intel_finish_page_flip_plane(dev, pipe); | |
abd58f01 | 2023 | } |
c42664cc | 2024 | |
0fbe7870 DV |
2025 | if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE) |
2026 | hsw_pipe_crc_irq_handler(dev, pipe); | |
2027 | ||
38d83c96 DV |
2028 | if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) { |
2029 | if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, | |
2030 | false)) | |
fc2c807b VS |
2031 | DRM_ERROR("Pipe %c FIFO underrun\n", |
2032 | pipe_name(pipe)); | |
38d83c96 DV |
2033 | } |
2034 | ||
30100f2b DV |
2035 | if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) { |
2036 | DRM_ERROR("Fault errors on pipe %c\n: 0x%08x", | |
2037 | pipe_name(pipe), | |
2038 | pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS); | |
2039 | } | |
c42664cc DV |
2040 | |
2041 | if (pipe_iir) { | |
2042 | ret = IRQ_HANDLED; | |
2043 | I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir); | |
2044 | } else | |
abd58f01 BW |
2045 | DRM_ERROR("The master control interrupt lied (DE PIPE)!\n"); |
2046 | } | |
2047 | ||
92d03a80 DV |
2048 | if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) { |
2049 | /* | |
2050 | * FIXME(BDW): Assume for now that the new interrupt handling | |
2051 | * scheme also closed the SDE interrupt handling race we've seen | |
2052 | * on older pch-split platforms. But this needs testing. | |
2053 | */ | |
2054 | u32 pch_iir = I915_READ(SDEIIR); | |
2055 | ||
2056 | cpt_irq_handler(dev, pch_iir); | |
2057 | ||
2058 | if (pch_iir) { | |
2059 | I915_WRITE(SDEIIR, pch_iir); | |
2060 | ret = IRQ_HANDLED; | |
2061 | } | |
2062 | } | |
2063 | ||
abd58f01 BW |
2064 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
2065 | POSTING_READ(GEN8_MASTER_IRQ); | |
2066 | ||
2067 | return ret; | |
2068 | } | |
2069 | ||
17e1df07 DV |
2070 | static void i915_error_wake_up(struct drm_i915_private *dev_priv, |
2071 | bool reset_completed) | |
2072 | { | |
2073 | struct intel_ring_buffer *ring; | |
2074 | int i; | |
2075 | ||
2076 | /* | |
2077 | * Notify all waiters for GPU completion events that reset state has | |
2078 | * been changed, and that they need to restart their wait after | |
2079 | * checking for potential errors (and bail out to drop locks if there is | |
2080 | * a gpu reset pending so that i915_error_work_func can acquire them). | |
2081 | */ | |
2082 | ||
2083 | /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */ | |
2084 | for_each_ring(ring, dev_priv, i) | |
2085 | wake_up_all(&ring->irq_queue); | |
2086 | ||
2087 | /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */ | |
2088 | wake_up_all(&dev_priv->pending_flip_queue); | |
2089 | ||
2090 | /* | |
2091 | * Signal tasks blocked in i915_gem_wait_for_error that the pending | |
2092 | * reset state is cleared. | |
2093 | */ | |
2094 | if (reset_completed) | |
2095 | wake_up_all(&dev_priv->gpu_error.reset_queue); | |
2096 | } | |
2097 | ||
8a905236 JB |
2098 | /** |
2099 | * i915_error_work_func - do process context error handling work | |
2100 | * @work: work struct | |
2101 | * | |
2102 | * Fire an error uevent so userspace can see that a hang or error | |
2103 | * was detected. | |
2104 | */ | |
2105 | static void i915_error_work_func(struct work_struct *work) | |
2106 | { | |
1f83fee0 DV |
2107 | struct i915_gpu_error *error = container_of(work, struct i915_gpu_error, |
2108 | work); | |
2d1013dd JN |
2109 | struct drm_i915_private *dev_priv = |
2110 | container_of(error, struct drm_i915_private, gpu_error); | |
8a905236 | 2111 | struct drm_device *dev = dev_priv->dev; |
cce723ed BW |
2112 | char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; |
2113 | char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; | |
2114 | char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; | |
17e1df07 | 2115 | int ret; |
8a905236 | 2116 | |
5bdebb18 | 2117 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event); |
f316a42c | 2118 | |
7db0ba24 DV |
2119 | /* |
2120 | * Note that there's only one work item which does gpu resets, so we | |
2121 | * need not worry about concurrent gpu resets potentially incrementing | |
2122 | * error->reset_counter twice. We only need to take care of another | |
2123 | * racing irq/hangcheck declaring the gpu dead for a second time. A | |
2124 | * quick check for that is good enough: schedule_work ensures the | |
2125 | * correct ordering between hang detection and this work item, and since | |
2126 | * the reset in-progress bit is only ever set by code outside of this | |
2127 | * work we don't need to worry about any other races. | |
2128 | */ | |
2129 | if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) { | |
f803aa55 | 2130 | DRM_DEBUG_DRIVER("resetting chip\n"); |
5bdebb18 | 2131 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, |
7db0ba24 | 2132 | reset_event); |
1f83fee0 | 2133 | |
f454c694 ID |
2134 | /* |
2135 | * In most cases it's guaranteed that we get here with an RPM | |
2136 | * reference held, for example because there is a pending GPU | |
2137 | * request that won't finish until the reset is done. This | |
2138 | * isn't the case at least when we get here by doing a | |
2139 | * simulated reset via debugs, so get an RPM reference. | |
2140 | */ | |
2141 | intel_runtime_pm_get(dev_priv); | |
17e1df07 DV |
2142 | /* |
2143 | * All state reset _must_ be completed before we update the | |
2144 | * reset counter, for otherwise waiters might miss the reset | |
2145 | * pending state and not properly drop locks, resulting in | |
2146 | * deadlocks with the reset work. | |
2147 | */ | |
f69061be DV |
2148 | ret = i915_reset(dev); |
2149 | ||
17e1df07 DV |
2150 | intel_display_handle_reset(dev); |
2151 | ||
f454c694 ID |
2152 | intel_runtime_pm_put(dev_priv); |
2153 | ||
f69061be DV |
2154 | if (ret == 0) { |
2155 | /* | |
2156 | * After all the gem state is reset, increment the reset | |
2157 | * counter and wake up everyone waiting for the reset to | |
2158 | * complete. | |
2159 | * | |
2160 | * Since unlock operations are a one-sided barrier only, | |
2161 | * we need to insert a barrier here to order any seqno | |
2162 | * updates before | |
2163 | * the counter increment. | |
2164 | */ | |
2165 | smp_mb__before_atomic_inc(); | |
2166 | atomic_inc(&dev_priv->gpu_error.reset_counter); | |
2167 | ||
5bdebb18 | 2168 | kobject_uevent_env(&dev->primary->kdev->kobj, |
f69061be | 2169 | KOBJ_CHANGE, reset_done_event); |
1f83fee0 | 2170 | } else { |
2ac0f450 | 2171 | atomic_set_mask(I915_WEDGED, &error->reset_counter); |
f316a42c | 2172 | } |
1f83fee0 | 2173 | |
17e1df07 DV |
2174 | /* |
2175 | * Note: The wake_up also serves as a memory barrier so that | |
2176 | * waiters see the update value of the reset counter atomic_t. | |
2177 | */ | |
2178 | i915_error_wake_up(dev_priv, true); | |
f316a42c | 2179 | } |
8a905236 JB |
2180 | } |
2181 | ||
35aed2e6 | 2182 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
2183 | { |
2184 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bd9854f9 | 2185 | uint32_t instdone[I915_NUM_INSTDONE_REG]; |
8a905236 | 2186 | u32 eir = I915_READ(EIR); |
050ee91f | 2187 | int pipe, i; |
8a905236 | 2188 | |
35aed2e6 CW |
2189 | if (!eir) |
2190 | return; | |
8a905236 | 2191 | |
a70491cc | 2192 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
8a905236 | 2193 | |
bd9854f9 BW |
2194 | i915_get_extra_instdone(dev, instdone); |
2195 | ||
8a905236 JB |
2196 | if (IS_G4X(dev)) { |
2197 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
2198 | u32 ipeir = I915_READ(IPEIR_I965); | |
2199 | ||
a70491cc JP |
2200 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2201 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
050ee91f BW |
2202 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2203 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a70491cc | 2204 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2205 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2206 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2207 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2208 | } |
2209 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
2210 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2211 | pr_err("page table error\n"); |
2212 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2213 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2214 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2215 | } |
2216 | } | |
2217 | ||
a6c45cf0 | 2218 | if (!IS_GEN2(dev)) { |
8a905236 JB |
2219 | if (eir & I915_ERROR_PAGE_TABLE) { |
2220 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2221 | pr_err("page table error\n"); |
2222 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2223 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2224 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2225 | } |
2226 | } | |
2227 | ||
2228 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
a70491cc | 2229 | pr_err("memory refresh error:\n"); |
9db4a9c7 | 2230 | for_each_pipe(pipe) |
a70491cc | 2231 | pr_err("pipe %c stat: 0x%08x\n", |
9db4a9c7 | 2232 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
8a905236 JB |
2233 | /* pipestat has already been acked */ |
2234 | } | |
2235 | if (eir & I915_ERROR_INSTRUCTION) { | |
a70491cc JP |
2236 | pr_err("instruction error\n"); |
2237 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); | |
050ee91f BW |
2238 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2239 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a6c45cf0 | 2240 | if (INTEL_INFO(dev)->gen < 4) { |
8a905236 JB |
2241 | u32 ipeir = I915_READ(IPEIR); |
2242 | ||
a70491cc JP |
2243 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
2244 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); | |
a70491cc | 2245 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); |
8a905236 | 2246 | I915_WRITE(IPEIR, ipeir); |
3143a2bf | 2247 | POSTING_READ(IPEIR); |
8a905236 JB |
2248 | } else { |
2249 | u32 ipeir = I915_READ(IPEIR_I965); | |
2250 | ||
a70491cc JP |
2251 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2252 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
a70491cc | 2253 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2254 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2255 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2256 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2257 | } |
2258 | } | |
2259 | ||
2260 | I915_WRITE(EIR, eir); | |
3143a2bf | 2261 | POSTING_READ(EIR); |
8a905236 JB |
2262 | eir = I915_READ(EIR); |
2263 | if (eir) { | |
2264 | /* | |
2265 | * some errors might have become stuck, | |
2266 | * mask them. | |
2267 | */ | |
2268 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
2269 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
2270 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2271 | } | |
35aed2e6 CW |
2272 | } |
2273 | ||
2274 | /** | |
2275 | * i915_handle_error - handle an error interrupt | |
2276 | * @dev: drm device | |
2277 | * | |
2278 | * Do some basic checking of regsiter state at error interrupt time and | |
2279 | * dump it to the syslog. Also call i915_capture_error_state() to make | |
2280 | * sure we get a record and make it available in debugfs. Fire a uevent | |
2281 | * so userspace knows something bad happened (should trigger collection | |
2282 | * of a ring dump etc.). | |
2283 | */ | |
58174462 MK |
2284 | void i915_handle_error(struct drm_device *dev, bool wedged, |
2285 | const char *fmt, ...) | |
35aed2e6 CW |
2286 | { |
2287 | struct drm_i915_private *dev_priv = dev->dev_private; | |
58174462 MK |
2288 | va_list args; |
2289 | char error_msg[80]; | |
35aed2e6 | 2290 | |
58174462 MK |
2291 | va_start(args, fmt); |
2292 | vscnprintf(error_msg, sizeof(error_msg), fmt, args); | |
2293 | va_end(args); | |
2294 | ||
2295 | i915_capture_error_state(dev, wedged, error_msg); | |
35aed2e6 | 2296 | i915_report_and_clear_eir(dev); |
8a905236 | 2297 | |
ba1234d1 | 2298 | if (wedged) { |
f69061be DV |
2299 | atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG, |
2300 | &dev_priv->gpu_error.reset_counter); | |
ba1234d1 | 2301 | |
11ed50ec | 2302 | /* |
17e1df07 DV |
2303 | * Wakeup waiting processes so that the reset work function |
2304 | * i915_error_work_func doesn't deadlock trying to grab various | |
2305 | * locks. By bumping the reset counter first, the woken | |
2306 | * processes will see a reset in progress and back off, | |
2307 | * releasing their locks and then wait for the reset completion. | |
2308 | * We must do this for _all_ gpu waiters that might hold locks | |
2309 | * that the reset work needs to acquire. | |
2310 | * | |
2311 | * Note: The wake_up serves as the required memory barrier to | |
2312 | * ensure that the waiters see the updated value of the reset | |
2313 | * counter atomic_t. | |
11ed50ec | 2314 | */ |
17e1df07 | 2315 | i915_error_wake_up(dev_priv, false); |
11ed50ec BG |
2316 | } |
2317 | ||
122f46ba DV |
2318 | /* |
2319 | * Our reset work can grab modeset locks (since it needs to reset the | |
2320 | * state of outstanding pagelips). Hence it must not be run on our own | |
2321 | * dev-priv->wq work queue for otherwise the flush_work in the pageflip | |
2322 | * code will deadlock. | |
2323 | */ | |
2324 | schedule_work(&dev_priv->gpu_error.work); | |
8a905236 JB |
2325 | } |
2326 | ||
21ad8330 | 2327 | static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe) |
4e5359cd | 2328 | { |
2d1013dd | 2329 | struct drm_i915_private *dev_priv = dev->dev_private; |
4e5359cd SF |
2330 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
2331 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 2332 | struct drm_i915_gem_object *obj; |
4e5359cd SF |
2333 | struct intel_unpin_work *work; |
2334 | unsigned long flags; | |
2335 | bool stall_detected; | |
2336 | ||
2337 | /* Ignore early vblank irqs */ | |
2338 | if (intel_crtc == NULL) | |
2339 | return; | |
2340 | ||
2341 | spin_lock_irqsave(&dev->event_lock, flags); | |
2342 | work = intel_crtc->unpin_work; | |
2343 | ||
e7d841ca CW |
2344 | if (work == NULL || |
2345 | atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE || | |
2346 | !work->enable_stall_check) { | |
4e5359cd SF |
2347 | /* Either the pending flip IRQ arrived, or we're too early. Don't check */ |
2348 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2349 | return; | |
2350 | } | |
2351 | ||
2352 | /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ | |
05394f39 | 2353 | obj = work->pending_flip_obj; |
a6c45cf0 | 2354 | if (INTEL_INFO(dev)->gen >= 4) { |
9db4a9c7 | 2355 | int dspsurf = DSPSURF(intel_crtc->plane); |
446f2545 | 2356 | stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) == |
f343c5f6 | 2357 | i915_gem_obj_ggtt_offset(obj); |
4e5359cd | 2358 | } else { |
9db4a9c7 | 2359 | int dspaddr = DSPADDR(intel_crtc->plane); |
f343c5f6 | 2360 | stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) + |
f4510a27 MR |
2361 | crtc->y * crtc->primary->fb->pitches[0] + |
2362 | crtc->x * crtc->primary->fb->bits_per_pixel/8); | |
4e5359cd SF |
2363 | } |
2364 | ||
2365 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2366 | ||
2367 | if (stall_detected) { | |
2368 | DRM_DEBUG_DRIVER("Pageflip stall detected\n"); | |
2369 | intel_prepare_page_flip(dev, intel_crtc->plane); | |
2370 | } | |
2371 | } | |
2372 | ||
42f52ef8 KP |
2373 | /* Called from drm generic code, passed 'crtc' which |
2374 | * we use as a pipe index | |
2375 | */ | |
f71d4af4 | 2376 | static int i915_enable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 | 2377 | { |
2d1013dd | 2378 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2379 | unsigned long irqflags; |
71e0ffa5 | 2380 | |
5eddb70b | 2381 | if (!i915_pipe_enabled(dev, pipe)) |
71e0ffa5 | 2382 | return -EINVAL; |
0a3e67a4 | 2383 | |
1ec14ad3 | 2384 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2385 | if (INTEL_INFO(dev)->gen >= 4) |
7c463586 | 2386 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2387 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
e9d21d7f | 2388 | else |
7c463586 | 2389 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2390 | PIPE_VBLANK_INTERRUPT_STATUS); |
8692d00e CW |
2391 | |
2392 | /* maintain vblank delivery even in deep C-states */ | |
3d13ef2e | 2393 | if (INTEL_INFO(dev)->gen == 3) |
6b26c86d | 2394 | I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS)); |
1ec14ad3 | 2395 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
8692d00e | 2396 | |
0a3e67a4 JB |
2397 | return 0; |
2398 | } | |
2399 | ||
f71d4af4 | 2400 | static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
f796cf8f | 2401 | { |
2d1013dd | 2402 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2403 | unsigned long irqflags; |
b518421f | 2404 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2405 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2406 | |
2407 | if (!i915_pipe_enabled(dev, pipe)) | |
2408 | return -EINVAL; | |
2409 | ||
2410 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 2411 | ironlake_enable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2412 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2413 | ||
2414 | return 0; | |
2415 | } | |
2416 | ||
7e231dbe JB |
2417 | static int valleyview_enable_vblank(struct drm_device *dev, int pipe) |
2418 | { | |
2d1013dd | 2419 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2420 | unsigned long irqflags; |
7e231dbe JB |
2421 | |
2422 | if (!i915_pipe_enabled(dev, pipe)) | |
2423 | return -EINVAL; | |
2424 | ||
2425 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 | 2426 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2427 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2428 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2429 | ||
2430 | return 0; | |
2431 | } | |
2432 | ||
abd58f01 BW |
2433 | static int gen8_enable_vblank(struct drm_device *dev, int pipe) |
2434 | { | |
2435 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2436 | unsigned long irqflags; | |
abd58f01 BW |
2437 | |
2438 | if (!i915_pipe_enabled(dev, pipe)) | |
2439 | return -EINVAL; | |
2440 | ||
2441 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
7167d7c6 DV |
2442 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK; |
2443 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2444 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2445 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2446 | return 0; | |
2447 | } | |
2448 | ||
42f52ef8 KP |
2449 | /* Called from drm generic code, passed 'crtc' which |
2450 | * we use as a pipe index | |
2451 | */ | |
f71d4af4 | 2452 | static void i915_disable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 | 2453 | { |
2d1013dd | 2454 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2455 | unsigned long irqflags; |
0a3e67a4 | 2456 | |
1ec14ad3 | 2457 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
3d13ef2e | 2458 | if (INTEL_INFO(dev)->gen == 3) |
6b26c86d | 2459 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS)); |
8692d00e | 2460 | |
f796cf8f | 2461 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 ID |
2462 | PIPE_VBLANK_INTERRUPT_STATUS | |
2463 | PIPE_START_VBLANK_INTERRUPT_STATUS); | |
f796cf8f JB |
2464 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2465 | } | |
2466 | ||
f71d4af4 | 2467 | static void ironlake_disable_vblank(struct drm_device *dev, int pipe) |
f796cf8f | 2468 | { |
2d1013dd | 2469 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2470 | unsigned long irqflags; |
b518421f | 2471 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2472 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2473 | |
2474 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 2475 | ironlake_disable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2476 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2477 | } | |
2478 | ||
7e231dbe JB |
2479 | static void valleyview_disable_vblank(struct drm_device *dev, int pipe) |
2480 | { | |
2d1013dd | 2481 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2482 | unsigned long irqflags; |
7e231dbe JB |
2483 | |
2484 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 | 2485 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 | 2486 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2487 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2488 | } | |
2489 | ||
abd58f01 BW |
2490 | static void gen8_disable_vblank(struct drm_device *dev, int pipe) |
2491 | { | |
2492 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2493 | unsigned long irqflags; | |
abd58f01 BW |
2494 | |
2495 | if (!i915_pipe_enabled(dev, pipe)) | |
2496 | return; | |
2497 | ||
2498 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
7167d7c6 DV |
2499 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK; |
2500 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2501 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2502 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2503 | } | |
2504 | ||
893eead0 CW |
2505 | static u32 |
2506 | ring_last_seqno(struct intel_ring_buffer *ring) | |
852835f3 | 2507 | { |
893eead0 CW |
2508 | return list_entry(ring->request_list.prev, |
2509 | struct drm_i915_gem_request, list)->seqno; | |
2510 | } | |
2511 | ||
9107e9d2 CW |
2512 | static bool |
2513 | ring_idle(struct intel_ring_buffer *ring, u32 seqno) | |
2514 | { | |
2515 | return (list_empty(&ring->request_list) || | |
2516 | i915_seqno_passed(seqno, ring_last_seqno(ring))); | |
f65d9421 BG |
2517 | } |
2518 | ||
a028c4b0 DV |
2519 | static bool |
2520 | ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr) | |
2521 | { | |
2522 | if (INTEL_INFO(dev)->gen >= 8) { | |
2523 | /* | |
2524 | * FIXME: gen8 semaphore support - currently we don't emit | |
2525 | * semaphores on bdw anyway, but this needs to be addressed when | |
2526 | * we merge that code. | |
2527 | */ | |
2528 | return false; | |
2529 | } else { | |
2530 | ipehr &= ~MI_SEMAPHORE_SYNC_MASK; | |
2531 | return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | | |
2532 | MI_SEMAPHORE_REGISTER); | |
2533 | } | |
2534 | } | |
2535 | ||
921d42ea DV |
2536 | static struct intel_ring_buffer * |
2537 | semaphore_wait_to_signaller_ring(struct intel_ring_buffer *ring, u32 ipehr) | |
2538 | { | |
2539 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
2540 | struct intel_ring_buffer *signaller; | |
2541 | int i; | |
2542 | ||
2543 | if (INTEL_INFO(dev_priv->dev)->gen >= 8) { | |
2544 | /* | |
2545 | * FIXME: gen8 semaphore support - currently we don't emit | |
2546 | * semaphores on bdw anyway, but this needs to be addressed when | |
2547 | * we merge that code. | |
2548 | */ | |
2549 | return NULL; | |
2550 | } else { | |
2551 | u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK; | |
2552 | ||
2553 | for_each_ring(signaller, dev_priv, i) { | |
2554 | if(ring == signaller) | |
2555 | continue; | |
2556 | ||
2557 | if (sync_bits == | |
2558 | signaller->semaphore_register[ring->id]) | |
2559 | return signaller; | |
2560 | } | |
2561 | } | |
2562 | ||
2563 | DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x\n", | |
2564 | ring->id, ipehr); | |
2565 | ||
2566 | return NULL; | |
2567 | } | |
2568 | ||
6274f212 CW |
2569 | static struct intel_ring_buffer * |
2570 | semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno) | |
a24a11e6 CW |
2571 | { |
2572 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
88fe429d DV |
2573 | u32 cmd, ipehr, head; |
2574 | int i; | |
a24a11e6 CW |
2575 | |
2576 | ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); | |
a028c4b0 | 2577 | if (!ipehr_is_semaphore_wait(ring->dev, ipehr)) |
6274f212 | 2578 | return NULL; |
a24a11e6 | 2579 | |
88fe429d DV |
2580 | /* |
2581 | * HEAD is likely pointing to the dword after the actual command, | |
2582 | * so scan backwards until we find the MBOX. But limit it to just 3 | |
2583 | * dwords. Note that we don't care about ACTHD here since that might | |
2584 | * point at at batch, and semaphores are always emitted into the | |
2585 | * ringbuffer itself. | |
a24a11e6 | 2586 | */ |
88fe429d DV |
2587 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
2588 | ||
2589 | for (i = 4; i; --i) { | |
2590 | /* | |
2591 | * Be paranoid and presume the hw has gone off into the wild - | |
2592 | * our ring is smaller than what the hardware (and hence | |
2593 | * HEAD_ADDR) allows. Also handles wrap-around. | |
2594 | */ | |
2595 | head &= ring->size - 1; | |
2596 | ||
2597 | /* This here seems to blow up */ | |
2598 | cmd = ioread32(ring->virtual_start + head); | |
a24a11e6 CW |
2599 | if (cmd == ipehr) |
2600 | break; | |
2601 | ||
88fe429d DV |
2602 | head -= 4; |
2603 | } | |
a24a11e6 | 2604 | |
88fe429d DV |
2605 | if (!i) |
2606 | return NULL; | |
a24a11e6 | 2607 | |
88fe429d | 2608 | *seqno = ioread32(ring->virtual_start + head + 4) + 1; |
921d42ea | 2609 | return semaphore_wait_to_signaller_ring(ring, ipehr); |
a24a11e6 CW |
2610 | } |
2611 | ||
6274f212 CW |
2612 | static int semaphore_passed(struct intel_ring_buffer *ring) |
2613 | { | |
2614 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
2615 | struct intel_ring_buffer *signaller; | |
2616 | u32 seqno, ctl; | |
2617 | ||
2618 | ring->hangcheck.deadlock = true; | |
2619 | ||
2620 | signaller = semaphore_waits_for(ring, &seqno); | |
2621 | if (signaller == NULL || signaller->hangcheck.deadlock) | |
2622 | return -1; | |
2623 | ||
2624 | /* cursory check for an unkickable deadlock */ | |
2625 | ctl = I915_READ_CTL(signaller); | |
2626 | if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0) | |
2627 | return -1; | |
2628 | ||
2629 | return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno); | |
2630 | } | |
2631 | ||
2632 | static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) | |
2633 | { | |
2634 | struct intel_ring_buffer *ring; | |
2635 | int i; | |
2636 | ||
2637 | for_each_ring(ring, dev_priv, i) | |
2638 | ring->hangcheck.deadlock = false; | |
2639 | } | |
2640 | ||
ad8beaea | 2641 | static enum intel_ring_hangcheck_action |
50877445 | 2642 | ring_stuck(struct intel_ring_buffer *ring, u64 acthd) |
1ec14ad3 CW |
2643 | { |
2644 | struct drm_device *dev = ring->dev; | |
2645 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9107e9d2 CW |
2646 | u32 tmp; |
2647 | ||
6274f212 | 2648 | if (ring->hangcheck.acthd != acthd) |
f2f4d82f | 2649 | return HANGCHECK_ACTIVE; |
6274f212 | 2650 | |
9107e9d2 | 2651 | if (IS_GEN2(dev)) |
f2f4d82f | 2652 | return HANGCHECK_HUNG; |
9107e9d2 CW |
2653 | |
2654 | /* Is the chip hanging on a WAIT_FOR_EVENT? | |
2655 | * If so we can simply poke the RB_WAIT bit | |
2656 | * and break the hang. This should work on | |
2657 | * all but the second generation chipsets. | |
2658 | */ | |
2659 | tmp = I915_READ_CTL(ring); | |
1ec14ad3 | 2660 | if (tmp & RING_WAIT) { |
58174462 MK |
2661 | i915_handle_error(dev, false, |
2662 | "Kicking stuck wait on %s", | |
2663 | ring->name); | |
1ec14ad3 | 2664 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2665 | return HANGCHECK_KICK; |
6274f212 CW |
2666 | } |
2667 | ||
2668 | if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { | |
2669 | switch (semaphore_passed(ring)) { | |
2670 | default: | |
f2f4d82f | 2671 | return HANGCHECK_HUNG; |
6274f212 | 2672 | case 1: |
58174462 MK |
2673 | i915_handle_error(dev, false, |
2674 | "Kicking stuck semaphore on %s", | |
2675 | ring->name); | |
6274f212 | 2676 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2677 | return HANGCHECK_KICK; |
6274f212 | 2678 | case 0: |
f2f4d82f | 2679 | return HANGCHECK_WAIT; |
6274f212 | 2680 | } |
9107e9d2 | 2681 | } |
ed5cbb03 | 2682 | |
f2f4d82f | 2683 | return HANGCHECK_HUNG; |
ed5cbb03 MK |
2684 | } |
2685 | ||
f65d9421 BG |
2686 | /** |
2687 | * This is called when the chip hasn't reported back with completed | |
05407ff8 MK |
2688 | * batchbuffers in a long time. We keep track per ring seqno progress and |
2689 | * if there are no progress, hangcheck score for that ring is increased. | |
2690 | * Further, acthd is inspected to see if the ring is stuck. On stuck case | |
2691 | * we kick the ring. If we see no progress on three subsequent calls | |
2692 | * we assume chip is wedged and try to fix it by resetting the chip. | |
f65d9421 | 2693 | */ |
a658b5d2 | 2694 | static void i915_hangcheck_elapsed(unsigned long data) |
f65d9421 BG |
2695 | { |
2696 | struct drm_device *dev = (struct drm_device *)data; | |
2d1013dd | 2697 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 2698 | struct intel_ring_buffer *ring; |
b4519513 | 2699 | int i; |
05407ff8 | 2700 | int busy_count = 0, rings_hung = 0; |
9107e9d2 CW |
2701 | bool stuck[I915_NUM_RINGS] = { 0 }; |
2702 | #define BUSY 1 | |
2703 | #define KICK 5 | |
2704 | #define HUNG 20 | |
893eead0 | 2705 | |
d330a953 | 2706 | if (!i915.enable_hangcheck) |
3e0dc6b0 BW |
2707 | return; |
2708 | ||
b4519513 | 2709 | for_each_ring(ring, dev_priv, i) { |
50877445 CW |
2710 | u64 acthd; |
2711 | u32 seqno; | |
9107e9d2 | 2712 | bool busy = true; |
05407ff8 | 2713 | |
6274f212 CW |
2714 | semaphore_clear_deadlocks(dev_priv); |
2715 | ||
05407ff8 MK |
2716 | seqno = ring->get_seqno(ring, false); |
2717 | acthd = intel_ring_get_active_head(ring); | |
b4519513 | 2718 | |
9107e9d2 CW |
2719 | if (ring->hangcheck.seqno == seqno) { |
2720 | if (ring_idle(ring, seqno)) { | |
da661464 MK |
2721 | ring->hangcheck.action = HANGCHECK_IDLE; |
2722 | ||
9107e9d2 CW |
2723 | if (waitqueue_active(&ring->irq_queue)) { |
2724 | /* Issue a wake-up to catch stuck h/w. */ | |
094f9a54 | 2725 | if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) { |
f4adcd24 DV |
2726 | if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring))) |
2727 | DRM_ERROR("Hangcheck timer elapsed... %s idle\n", | |
2728 | ring->name); | |
2729 | else | |
2730 | DRM_INFO("Fake missed irq on %s\n", | |
2731 | ring->name); | |
094f9a54 CW |
2732 | wake_up_all(&ring->irq_queue); |
2733 | } | |
2734 | /* Safeguard against driver failure */ | |
2735 | ring->hangcheck.score += BUSY; | |
9107e9d2 CW |
2736 | } else |
2737 | busy = false; | |
05407ff8 | 2738 | } else { |
6274f212 CW |
2739 | /* We always increment the hangcheck score |
2740 | * if the ring is busy and still processing | |
2741 | * the same request, so that no single request | |
2742 | * can run indefinitely (such as a chain of | |
2743 | * batches). The only time we do not increment | |
2744 | * the hangcheck score on this ring, if this | |
2745 | * ring is in a legitimate wait for another | |
2746 | * ring. In that case the waiting ring is a | |
2747 | * victim and we want to be sure we catch the | |
2748 | * right culprit. Then every time we do kick | |
2749 | * the ring, add a small increment to the | |
2750 | * score so that we can catch a batch that is | |
2751 | * being repeatedly kicked and so responsible | |
2752 | * for stalling the machine. | |
2753 | */ | |
ad8beaea MK |
2754 | ring->hangcheck.action = ring_stuck(ring, |
2755 | acthd); | |
2756 | ||
2757 | switch (ring->hangcheck.action) { | |
da661464 | 2758 | case HANGCHECK_IDLE: |
f2f4d82f | 2759 | case HANGCHECK_WAIT: |
6274f212 | 2760 | break; |
f2f4d82f | 2761 | case HANGCHECK_ACTIVE: |
ea04cb31 | 2762 | ring->hangcheck.score += BUSY; |
6274f212 | 2763 | break; |
f2f4d82f | 2764 | case HANGCHECK_KICK: |
ea04cb31 | 2765 | ring->hangcheck.score += KICK; |
6274f212 | 2766 | break; |
f2f4d82f | 2767 | case HANGCHECK_HUNG: |
ea04cb31 | 2768 | ring->hangcheck.score += HUNG; |
6274f212 CW |
2769 | stuck[i] = true; |
2770 | break; | |
2771 | } | |
05407ff8 | 2772 | } |
9107e9d2 | 2773 | } else { |
da661464 MK |
2774 | ring->hangcheck.action = HANGCHECK_ACTIVE; |
2775 | ||
9107e9d2 CW |
2776 | /* Gradually reduce the count so that we catch DoS |
2777 | * attempts across multiple batches. | |
2778 | */ | |
2779 | if (ring->hangcheck.score > 0) | |
2780 | ring->hangcheck.score--; | |
d1e61e7f CW |
2781 | } |
2782 | ||
05407ff8 MK |
2783 | ring->hangcheck.seqno = seqno; |
2784 | ring->hangcheck.acthd = acthd; | |
9107e9d2 | 2785 | busy_count += busy; |
893eead0 | 2786 | } |
b9201c14 | 2787 | |
92cab734 | 2788 | for_each_ring(ring, dev_priv, i) { |
b6b0fac0 | 2789 | if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) { |
b8d88d1d DV |
2790 | DRM_INFO("%s on %s\n", |
2791 | stuck[i] ? "stuck" : "no progress", | |
2792 | ring->name); | |
a43adf07 | 2793 | rings_hung++; |
92cab734 MK |
2794 | } |
2795 | } | |
2796 | ||
05407ff8 | 2797 | if (rings_hung) |
58174462 | 2798 | return i915_handle_error(dev, true, "Ring hung"); |
f65d9421 | 2799 | |
05407ff8 MK |
2800 | if (busy_count) |
2801 | /* Reset timer case chip hangs without another request | |
2802 | * being added */ | |
10cd45b6 MK |
2803 | i915_queue_hangcheck(dev); |
2804 | } | |
2805 | ||
2806 | void i915_queue_hangcheck(struct drm_device *dev) | |
2807 | { | |
2808 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d330a953 | 2809 | if (!i915.enable_hangcheck) |
10cd45b6 MK |
2810 | return; |
2811 | ||
2812 | mod_timer(&dev_priv->gpu_error.hangcheck_timer, | |
2813 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); | |
f65d9421 BG |
2814 | } |
2815 | ||
1c69eb42 | 2816 | static void ibx_irq_reset(struct drm_device *dev) |
91738a95 PZ |
2817 | { |
2818 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2819 | ||
2820 | if (HAS_PCH_NOP(dev)) | |
2821 | return; | |
2822 | ||
f86f3fb0 | 2823 | GEN5_IRQ_RESET(SDE); |
105b122e PZ |
2824 | |
2825 | if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) | |
2826 | I915_WRITE(SERR_INT, 0xffffffff); | |
622364b6 | 2827 | } |
105b122e | 2828 | |
622364b6 PZ |
2829 | /* |
2830 | * SDEIER is also touched by the interrupt handler to work around missed PCH | |
2831 | * interrupts. Hence we can't update it after the interrupt handler is enabled - | |
2832 | * instead we unconditionally enable all PCH interrupt sources here, but then | |
2833 | * only unmask them as needed with SDEIMR. | |
2834 | * | |
2835 | * This function needs to be called before interrupts are enabled. | |
2836 | */ | |
2837 | static void ibx_irq_pre_postinstall(struct drm_device *dev) | |
2838 | { | |
2839 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2840 | ||
2841 | if (HAS_PCH_NOP(dev)) | |
2842 | return; | |
2843 | ||
2844 | WARN_ON(I915_READ(SDEIER) != 0); | |
91738a95 PZ |
2845 | I915_WRITE(SDEIER, 0xffffffff); |
2846 | POSTING_READ(SDEIER); | |
2847 | } | |
2848 | ||
7c4d664e | 2849 | static void gen5_gt_irq_reset(struct drm_device *dev) |
d18ea1b5 DV |
2850 | { |
2851 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2852 | ||
f86f3fb0 | 2853 | GEN5_IRQ_RESET(GT); |
a9d356a6 | 2854 | if (INTEL_INFO(dev)->gen >= 6) |
f86f3fb0 | 2855 | GEN5_IRQ_RESET(GEN6_PM); |
d18ea1b5 DV |
2856 | } |
2857 | ||
1da177e4 LT |
2858 | /* drm_dma.h hooks |
2859 | */ | |
be30b29f | 2860 | static void ironlake_irq_reset(struct drm_device *dev) |
036a4a7d | 2861 | { |
2d1013dd | 2862 | struct drm_i915_private *dev_priv = dev->dev_private; |
036a4a7d | 2863 | |
0c841212 | 2864 | I915_WRITE(HWSTAM, 0xffffffff); |
bdfcdb63 | 2865 | |
f86f3fb0 | 2866 | GEN5_IRQ_RESET(DE); |
c6d954c1 PZ |
2867 | if (IS_GEN7(dev)) |
2868 | I915_WRITE(GEN7_ERR_INT, 0xffffffff); | |
036a4a7d | 2869 | |
7c4d664e | 2870 | gen5_gt_irq_reset(dev); |
c650156a | 2871 | |
1c69eb42 | 2872 | ibx_irq_reset(dev); |
7d99163d | 2873 | } |
c650156a | 2874 | |
be30b29f PZ |
2875 | static void ironlake_irq_preinstall(struct drm_device *dev) |
2876 | { | |
be30b29f | 2877 | ironlake_irq_reset(dev); |
7d99163d BW |
2878 | } |
2879 | ||
7e231dbe JB |
2880 | static void valleyview_irq_preinstall(struct drm_device *dev) |
2881 | { | |
2d1013dd | 2882 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
2883 | int pipe; |
2884 | ||
7e231dbe JB |
2885 | /* VLV magic */ |
2886 | I915_WRITE(VLV_IMR, 0); | |
2887 | I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); | |
2888 | I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); | |
2889 | I915_WRITE(RING_IMR(BLT_RING_BASE), 0); | |
2890 | ||
7e231dbe JB |
2891 | /* and GT */ |
2892 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
2893 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
d18ea1b5 | 2894 | |
7c4d664e | 2895 | gen5_gt_irq_reset(dev); |
7e231dbe JB |
2896 | |
2897 | I915_WRITE(DPINVGTT, 0xff); | |
2898 | ||
2899 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
2900 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
2901 | for_each_pipe(pipe) | |
2902 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
2903 | I915_WRITE(VLV_IIR, 0xffffffff); | |
2904 | I915_WRITE(VLV_IMR, 0xffffffff); | |
2905 | I915_WRITE(VLV_IER, 0x0); | |
2906 | POSTING_READ(VLV_IER); | |
2907 | } | |
2908 | ||
823f6b38 | 2909 | static void gen8_irq_reset(struct drm_device *dev) |
abd58f01 BW |
2910 | { |
2911 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2912 | int pipe; | |
2913 | ||
abd58f01 BW |
2914 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
2915 | POSTING_READ(GEN8_MASTER_IRQ); | |
2916 | ||
f86f3fb0 PZ |
2917 | GEN8_IRQ_RESET_NDX(GT, 0); |
2918 | GEN8_IRQ_RESET_NDX(GT, 1); | |
2919 | GEN8_IRQ_RESET_NDX(GT, 2); | |
2920 | GEN8_IRQ_RESET_NDX(GT, 3); | |
abd58f01 | 2921 | |
823f6b38 | 2922 | for_each_pipe(pipe) |
f86f3fb0 | 2923 | GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); |
abd58f01 | 2924 | |
f86f3fb0 PZ |
2925 | GEN5_IRQ_RESET(GEN8_DE_PORT_); |
2926 | GEN5_IRQ_RESET(GEN8_DE_MISC_); | |
2927 | GEN5_IRQ_RESET(GEN8_PCU_); | |
abd58f01 | 2928 | |
1c69eb42 | 2929 | ibx_irq_reset(dev); |
abd58f01 | 2930 | } |
09f2344d | 2931 | |
823f6b38 PZ |
2932 | static void gen8_irq_preinstall(struct drm_device *dev) |
2933 | { | |
2934 | gen8_irq_reset(dev); | |
abd58f01 BW |
2935 | } |
2936 | ||
82a28bcf | 2937 | static void ibx_hpd_irq_setup(struct drm_device *dev) |
7fe0b973 | 2938 | { |
2d1013dd | 2939 | struct drm_i915_private *dev_priv = dev->dev_private; |
82a28bcf DV |
2940 | struct drm_mode_config *mode_config = &dev->mode_config; |
2941 | struct intel_encoder *intel_encoder; | |
fee884ed | 2942 | u32 hotplug_irqs, hotplug, enabled_irqs = 0; |
82a28bcf DV |
2943 | |
2944 | if (HAS_PCH_IBX(dev)) { | |
fee884ed | 2945 | hotplug_irqs = SDE_HOTPLUG_MASK; |
82a28bcf | 2946 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
cd569aed | 2947 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
fee884ed | 2948 | enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin]; |
82a28bcf | 2949 | } else { |
fee884ed | 2950 | hotplug_irqs = SDE_HOTPLUG_MASK_CPT; |
82a28bcf | 2951 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
cd569aed | 2952 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
fee884ed | 2953 | enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin]; |
82a28bcf | 2954 | } |
7fe0b973 | 2955 | |
fee884ed | 2956 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); |
82a28bcf DV |
2957 | |
2958 | /* | |
2959 | * Enable digital hotplug on the PCH, and configure the DP short pulse | |
2960 | * duration to 2ms (which is the minimum in the Display Port spec) | |
2961 | * | |
2962 | * This register is the same on all known PCH chips. | |
2963 | */ | |
7fe0b973 KP |
2964 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
2965 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); | |
2966 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; | |
2967 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; | |
2968 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; | |
2969 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); | |
2970 | } | |
2971 | ||
d46da437 PZ |
2972 | static void ibx_irq_postinstall(struct drm_device *dev) |
2973 | { | |
2d1013dd | 2974 | struct drm_i915_private *dev_priv = dev->dev_private; |
82a28bcf | 2975 | u32 mask; |
e5868a31 | 2976 | |
692a04cf DV |
2977 | if (HAS_PCH_NOP(dev)) |
2978 | return; | |
2979 | ||
105b122e | 2980 | if (HAS_PCH_IBX(dev)) |
5c673b60 | 2981 | mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; |
105b122e | 2982 | else |
5c673b60 | 2983 | mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; |
8664281b | 2984 | |
337ba017 | 2985 | GEN5_ASSERT_IIR_IS_ZERO(SDEIIR); |
d46da437 | 2986 | I915_WRITE(SDEIMR, ~mask); |
d46da437 PZ |
2987 | } |
2988 | ||
0a9a8c91 DV |
2989 | static void gen5_gt_irq_postinstall(struct drm_device *dev) |
2990 | { | |
2991 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2992 | u32 pm_irqs, gt_irqs; | |
2993 | ||
2994 | pm_irqs = gt_irqs = 0; | |
2995 | ||
2996 | dev_priv->gt_irq_mask = ~0; | |
040d2baa | 2997 | if (HAS_L3_DPF(dev)) { |
0a9a8c91 | 2998 | /* L3 parity interrupt is always unmasked. */ |
35a85ac6 BW |
2999 | dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev); |
3000 | gt_irqs |= GT_PARITY_ERROR(dev); | |
0a9a8c91 DV |
3001 | } |
3002 | ||
3003 | gt_irqs |= GT_RENDER_USER_INTERRUPT; | |
3004 | if (IS_GEN5(dev)) { | |
3005 | gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | | |
3006 | ILK_BSD_USER_INTERRUPT; | |
3007 | } else { | |
3008 | gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; | |
3009 | } | |
3010 | ||
35079899 | 3011 | GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); |
0a9a8c91 DV |
3012 | |
3013 | if (INTEL_INFO(dev)->gen >= 6) { | |
a6706b45 | 3014 | pm_irqs |= dev_priv->pm_rps_events; |
0a9a8c91 DV |
3015 | |
3016 | if (HAS_VEBOX(dev)) | |
3017 | pm_irqs |= PM_VEBOX_USER_INTERRUPT; | |
3018 | ||
605cd25b | 3019 | dev_priv->pm_irq_mask = 0xffffffff; |
35079899 | 3020 | GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs); |
0a9a8c91 DV |
3021 | } |
3022 | } | |
3023 | ||
f71d4af4 | 3024 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d | 3025 | { |
4bc9d430 | 3026 | unsigned long irqflags; |
2d1013dd | 3027 | struct drm_i915_private *dev_priv = dev->dev_private; |
8e76f8dc PZ |
3028 | u32 display_mask, extra_mask; |
3029 | ||
3030 | if (INTEL_INFO(dev)->gen >= 7) { | |
3031 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | | |
3032 | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | | |
3033 | DE_PLANEB_FLIP_DONE_IVB | | |
5c673b60 | 3034 | DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB); |
8e76f8dc | 3035 | extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | |
5c673b60 | 3036 | DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB); |
8e76f8dc PZ |
3037 | } else { |
3038 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | | |
3039 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | | |
5b3a856b | 3040 | DE_AUX_CHANNEL_A | |
5b3a856b DV |
3041 | DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE | |
3042 | DE_POISON); | |
5c673b60 DV |
3043 | extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT | |
3044 | DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN; | |
8e76f8dc | 3045 | } |
036a4a7d | 3046 | |
1ec14ad3 | 3047 | dev_priv->irq_mask = ~display_mask; |
036a4a7d | 3048 | |
0c841212 PZ |
3049 | I915_WRITE(HWSTAM, 0xeffe); |
3050 | ||
622364b6 PZ |
3051 | ibx_irq_pre_postinstall(dev); |
3052 | ||
35079899 | 3053 | GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); |
036a4a7d | 3054 | |
0a9a8c91 | 3055 | gen5_gt_irq_postinstall(dev); |
036a4a7d | 3056 | |
d46da437 | 3057 | ibx_irq_postinstall(dev); |
7fe0b973 | 3058 | |
f97108d1 | 3059 | if (IS_IRONLAKE_M(dev)) { |
6005ce42 DV |
3060 | /* Enable PCU event interrupts |
3061 | * | |
3062 | * spinlocking not required here for correctness since interrupt | |
4bc9d430 DV |
3063 | * setup is guaranteed to run in single-threaded context. But we |
3064 | * need it to make the assert_spin_locked happy. */ | |
3065 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
f97108d1 | 3066 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); |
4bc9d430 | 3067 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
f97108d1 JB |
3068 | } |
3069 | ||
036a4a7d ZW |
3070 | return 0; |
3071 | } | |
3072 | ||
f8b79e58 ID |
3073 | static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv) |
3074 | { | |
3075 | u32 pipestat_mask; | |
3076 | u32 iir_mask; | |
3077 | ||
3078 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | | |
3079 | PIPE_FIFO_UNDERRUN_STATUS; | |
3080 | ||
3081 | I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask); | |
3082 | I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask); | |
3083 | POSTING_READ(PIPESTAT(PIPE_A)); | |
3084 | ||
3085 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3086 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3087 | ||
3088 | i915_enable_pipestat(dev_priv, PIPE_A, pipestat_mask | | |
3089 | PIPE_GMBUS_INTERRUPT_STATUS); | |
3090 | i915_enable_pipestat(dev_priv, PIPE_B, pipestat_mask); | |
3091 | ||
3092 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3093 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3094 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
3095 | dev_priv->irq_mask &= ~iir_mask; | |
3096 | ||
3097 | I915_WRITE(VLV_IIR, iir_mask); | |
3098 | I915_WRITE(VLV_IIR, iir_mask); | |
3099 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); | |
3100 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); | |
3101 | POSTING_READ(VLV_IER); | |
3102 | } | |
3103 | ||
3104 | static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv) | |
3105 | { | |
3106 | u32 pipestat_mask; | |
3107 | u32 iir_mask; | |
3108 | ||
3109 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3110 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
6c7fba04 | 3111 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; |
f8b79e58 ID |
3112 | |
3113 | dev_priv->irq_mask |= iir_mask; | |
3114 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); | |
3115 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); | |
3116 | I915_WRITE(VLV_IIR, iir_mask); | |
3117 | I915_WRITE(VLV_IIR, iir_mask); | |
3118 | POSTING_READ(VLV_IIR); | |
3119 | ||
3120 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3121 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3122 | ||
3123 | i915_disable_pipestat(dev_priv, PIPE_A, pipestat_mask | | |
3124 | PIPE_GMBUS_INTERRUPT_STATUS); | |
3125 | i915_disable_pipestat(dev_priv, PIPE_B, pipestat_mask); | |
3126 | ||
3127 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | | |
3128 | PIPE_FIFO_UNDERRUN_STATUS; | |
3129 | I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask); | |
3130 | I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask); | |
3131 | POSTING_READ(PIPESTAT(PIPE_A)); | |
3132 | } | |
3133 | ||
3134 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) | |
3135 | { | |
3136 | assert_spin_locked(&dev_priv->irq_lock); | |
3137 | ||
3138 | if (dev_priv->display_irqs_enabled) | |
3139 | return; | |
3140 | ||
3141 | dev_priv->display_irqs_enabled = true; | |
3142 | ||
3143 | if (dev_priv->dev->irq_enabled) | |
3144 | valleyview_display_irqs_install(dev_priv); | |
3145 | } | |
3146 | ||
3147 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) | |
3148 | { | |
3149 | assert_spin_locked(&dev_priv->irq_lock); | |
3150 | ||
3151 | if (!dev_priv->display_irqs_enabled) | |
3152 | return; | |
3153 | ||
3154 | dev_priv->display_irqs_enabled = false; | |
3155 | ||
3156 | if (dev_priv->dev->irq_enabled) | |
3157 | valleyview_display_irqs_uninstall(dev_priv); | |
3158 | } | |
3159 | ||
7e231dbe JB |
3160 | static int valleyview_irq_postinstall(struct drm_device *dev) |
3161 | { | |
2d1013dd | 3162 | struct drm_i915_private *dev_priv = dev->dev_private; |
b79480ba | 3163 | unsigned long irqflags; |
7e231dbe | 3164 | |
f8b79e58 | 3165 | dev_priv->irq_mask = ~0; |
7e231dbe | 3166 | |
20afbda2 DV |
3167 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3168 | POSTING_READ(PORT_HOTPLUG_EN); | |
3169 | ||
7e231dbe | 3170 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
f8b79e58 | 3171 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); |
7e231dbe | 3172 | I915_WRITE(VLV_IIR, 0xffffffff); |
7e231dbe JB |
3173 | POSTING_READ(VLV_IER); |
3174 | ||
b79480ba DV |
3175 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3176 | * just to make the assert_spin_locked check happy. */ | |
3177 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
f8b79e58 ID |
3178 | if (dev_priv->display_irqs_enabled) |
3179 | valleyview_display_irqs_install(dev_priv); | |
b79480ba | 3180 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
31acc7f5 | 3181 | |
7e231dbe JB |
3182 | I915_WRITE(VLV_IIR, 0xffffffff); |
3183 | I915_WRITE(VLV_IIR, 0xffffffff); | |
3184 | ||
0a9a8c91 | 3185 | gen5_gt_irq_postinstall(dev); |
7e231dbe JB |
3186 | |
3187 | /* ack & enable invalid PTE error interrupts */ | |
3188 | #if 0 /* FIXME: add support to irq handler for checking these bits */ | |
3189 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); | |
3190 | I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); | |
3191 | #endif | |
3192 | ||
3193 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); | |
20afbda2 DV |
3194 | |
3195 | return 0; | |
3196 | } | |
3197 | ||
abd58f01 BW |
3198 | static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) |
3199 | { | |
3200 | int i; | |
3201 | ||
3202 | /* These are interrupts we'll toggle with the ring mask register */ | |
3203 | uint32_t gt_interrupts[] = { | |
3204 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | | |
3205 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT | | |
3206 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT, | |
3207 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | | |
3208 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT, | |
3209 | 0, | |
3210 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
3211 | }; | |
3212 | ||
337ba017 | 3213 | for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) |
35079899 | 3214 | GEN8_IRQ_INIT_NDX(GT, i, ~gt_interrupts[i], gt_interrupts[i]); |
abd58f01 BW |
3215 | } |
3216 | ||
3217 | static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) | |
3218 | { | |
3219 | struct drm_device *dev = dev_priv->dev; | |
d0e1f1cb | 3220 | uint32_t de_pipe_masked = GEN8_PIPE_PRIMARY_FLIP_DONE | |
13b3a0a7 | 3221 | GEN8_PIPE_CDCLK_CRC_DONE | |
13b3a0a7 | 3222 | GEN8_DE_PIPE_IRQ_FAULT_ERRORS; |
5c673b60 DV |
3223 | uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | |
3224 | GEN8_PIPE_FIFO_UNDERRUN; | |
abd58f01 | 3225 | int pipe; |
13b3a0a7 DV |
3226 | dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; |
3227 | dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; | |
3228 | dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; | |
abd58f01 | 3229 | |
337ba017 | 3230 | for_each_pipe(pipe) |
35079899 PZ |
3231 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, dev_priv->de_irq_mask[pipe], |
3232 | de_pipe_enables); | |
abd58f01 | 3233 | |
35079899 | 3234 | GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A); |
abd58f01 BW |
3235 | } |
3236 | ||
3237 | static int gen8_irq_postinstall(struct drm_device *dev) | |
3238 | { | |
3239 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3240 | ||
622364b6 PZ |
3241 | ibx_irq_pre_postinstall(dev); |
3242 | ||
abd58f01 BW |
3243 | gen8_gt_irq_postinstall(dev_priv); |
3244 | gen8_de_irq_postinstall(dev_priv); | |
3245 | ||
3246 | ibx_irq_postinstall(dev); | |
3247 | ||
3248 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); | |
3249 | POSTING_READ(GEN8_MASTER_IRQ); | |
3250 | ||
3251 | return 0; | |
3252 | } | |
3253 | ||
3254 | static void gen8_irq_uninstall(struct drm_device *dev) | |
3255 | { | |
3256 | struct drm_i915_private *dev_priv = dev->dev_private; | |
abd58f01 BW |
3257 | |
3258 | if (!dev_priv) | |
3259 | return; | |
3260 | ||
d4eb6b10 | 3261 | intel_hpd_irq_uninstall(dev_priv); |
abd58f01 | 3262 | |
823f6b38 | 3263 | gen8_irq_reset(dev); |
abd58f01 BW |
3264 | } |
3265 | ||
7e231dbe JB |
3266 | static void valleyview_irq_uninstall(struct drm_device *dev) |
3267 | { | |
2d1013dd | 3268 | struct drm_i915_private *dev_priv = dev->dev_private; |
f8b79e58 | 3269 | unsigned long irqflags; |
7e231dbe JB |
3270 | int pipe; |
3271 | ||
3272 | if (!dev_priv) | |
3273 | return; | |
3274 | ||
843d0e7d ID |
3275 | I915_WRITE(VLV_MASTER_IER, 0); |
3276 | ||
3ca1cced | 3277 | intel_hpd_irq_uninstall(dev_priv); |
ac4c16c5 | 3278 | |
7e231dbe JB |
3279 | for_each_pipe(pipe) |
3280 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
3281 | ||
3282 | I915_WRITE(HWSTAM, 0xffffffff); | |
3283 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3284 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
f8b79e58 ID |
3285 | |
3286 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3287 | if (dev_priv->display_irqs_enabled) | |
3288 | valleyview_display_irqs_uninstall(dev_priv); | |
3289 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3290 | ||
3291 | dev_priv->irq_mask = 0; | |
3292 | ||
7e231dbe JB |
3293 | I915_WRITE(VLV_IIR, 0xffffffff); |
3294 | I915_WRITE(VLV_IMR, 0xffffffff); | |
3295 | I915_WRITE(VLV_IER, 0x0); | |
3296 | POSTING_READ(VLV_IER); | |
3297 | } | |
3298 | ||
f71d4af4 | 3299 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d | 3300 | { |
2d1013dd | 3301 | struct drm_i915_private *dev_priv = dev->dev_private; |
4697995b JB |
3302 | |
3303 | if (!dev_priv) | |
3304 | return; | |
3305 | ||
3ca1cced | 3306 | intel_hpd_irq_uninstall(dev_priv); |
ac4c16c5 | 3307 | |
be30b29f | 3308 | ironlake_irq_reset(dev); |
036a4a7d ZW |
3309 | } |
3310 | ||
a266c7d5 | 3311 | static void i8xx_irq_preinstall(struct drm_device * dev) |
1da177e4 | 3312 | { |
2d1013dd | 3313 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 3314 | int pipe; |
91e3738e | 3315 | |
9db4a9c7 JB |
3316 | for_each_pipe(pipe) |
3317 | I915_WRITE(PIPESTAT(pipe), 0); | |
a266c7d5 CW |
3318 | I915_WRITE16(IMR, 0xffff); |
3319 | I915_WRITE16(IER, 0x0); | |
3320 | POSTING_READ16(IER); | |
c2798b19 CW |
3321 | } |
3322 | ||
3323 | static int i8xx_irq_postinstall(struct drm_device *dev) | |
3324 | { | |
2d1013dd | 3325 | struct drm_i915_private *dev_priv = dev->dev_private; |
379ef82d | 3326 | unsigned long irqflags; |
c2798b19 | 3327 | |
c2798b19 CW |
3328 | I915_WRITE16(EMR, |
3329 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); | |
3330 | ||
3331 | /* Unmask the interrupts that we always want on. */ | |
3332 | dev_priv->irq_mask = | |
3333 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3334 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3335 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3336 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3337 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3338 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
3339 | ||
3340 | I915_WRITE16(IER, | |
3341 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3342 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3343 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
3344 | I915_USER_INTERRUPT); | |
3345 | POSTING_READ16(IER); | |
3346 | ||
379ef82d DV |
3347 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3348 | * just to make the assert_spin_locked check happy. */ | |
3349 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
755e9019 ID |
3350 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3351 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
379ef82d DV |
3352 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
3353 | ||
c2798b19 CW |
3354 | return 0; |
3355 | } | |
3356 | ||
90a72f87 VS |
3357 | /* |
3358 | * Returns true when a page flip has completed. | |
3359 | */ | |
3360 | static bool i8xx_handle_vblank(struct drm_device *dev, | |
1f1c2e24 | 3361 | int plane, int pipe, u32 iir) |
90a72f87 | 3362 | { |
2d1013dd | 3363 | struct drm_i915_private *dev_priv = dev->dev_private; |
1f1c2e24 | 3364 | u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
90a72f87 VS |
3365 | |
3366 | if (!drm_handle_vblank(dev, pipe)) | |
3367 | return false; | |
3368 | ||
3369 | if ((iir & flip_pending) == 0) | |
3370 | return false; | |
3371 | ||
1f1c2e24 | 3372 | intel_prepare_page_flip(dev, plane); |
90a72f87 VS |
3373 | |
3374 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
3375 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3376 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3377 | * the flip is completed (no longer pending). Since this doesn't raise | |
3378 | * an interrupt per se, we watch for the change at vblank. | |
3379 | */ | |
3380 | if (I915_READ16(ISR) & flip_pending) | |
3381 | return false; | |
3382 | ||
3383 | intel_finish_page_flip(dev, pipe); | |
3384 | ||
3385 | return true; | |
3386 | } | |
3387 | ||
ff1f525e | 3388 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
c2798b19 CW |
3389 | { |
3390 | struct drm_device *dev = (struct drm_device *) arg; | |
2d1013dd | 3391 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
3392 | u16 iir, new_iir; |
3393 | u32 pipe_stats[2]; | |
3394 | unsigned long irqflags; | |
c2798b19 CW |
3395 | int pipe; |
3396 | u16 flip_mask = | |
3397 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3398 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
3399 | ||
c2798b19 CW |
3400 | iir = I915_READ16(IIR); |
3401 | if (iir == 0) | |
3402 | return IRQ_NONE; | |
3403 | ||
3404 | while (iir & ~flip_mask) { | |
3405 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3406 | * have been cleared after the pipestat interrupt was received. | |
3407 | * It doesn't set the bit in iir again, but it still produces | |
3408 | * interrupts (for non-MSI). | |
3409 | */ | |
3410 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3411 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
58174462 MK |
3412 | i915_handle_error(dev, false, |
3413 | "Command parser error, iir 0x%08x", | |
3414 | iir); | |
c2798b19 CW |
3415 | |
3416 | for_each_pipe(pipe) { | |
3417 | int reg = PIPESTAT(pipe); | |
3418 | pipe_stats[pipe] = I915_READ(reg); | |
3419 | ||
3420 | /* | |
3421 | * Clear the PIPE*STAT regs before the IIR | |
3422 | */ | |
2d9d2b0b | 3423 | if (pipe_stats[pipe] & 0x8000ffff) |
c2798b19 | 3424 | I915_WRITE(reg, pipe_stats[pipe]); |
c2798b19 CW |
3425 | } |
3426 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3427 | ||
3428 | I915_WRITE16(IIR, iir & ~flip_mask); | |
3429 | new_iir = I915_READ16(IIR); /* Flush posted writes */ | |
3430 | ||
d05c617e | 3431 | i915_update_dri1_breadcrumb(dev); |
c2798b19 CW |
3432 | |
3433 | if (iir & I915_USER_INTERRUPT) | |
3434 | notify_ring(dev, &dev_priv->ring[RCS]); | |
3435 | ||
4356d586 | 3436 | for_each_pipe(pipe) { |
1f1c2e24 | 3437 | int plane = pipe; |
3a77c4c4 | 3438 | if (HAS_FBC(dev)) |
1f1c2e24 VS |
3439 | plane = !plane; |
3440 | ||
4356d586 | 3441 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
1f1c2e24 VS |
3442 | i8xx_handle_vblank(dev, plane, pipe, iir)) |
3443 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
c2798b19 | 3444 | |
4356d586 | 3445 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
277de95e | 3446 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b VS |
3447 | |
3448 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && | |
3449 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
fc2c807b | 3450 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); |
4356d586 | 3451 | } |
c2798b19 CW |
3452 | |
3453 | iir = new_iir; | |
3454 | } | |
3455 | ||
3456 | return IRQ_HANDLED; | |
3457 | } | |
3458 | ||
3459 | static void i8xx_irq_uninstall(struct drm_device * dev) | |
3460 | { | |
2d1013dd | 3461 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
3462 | int pipe; |
3463 | ||
c2798b19 CW |
3464 | for_each_pipe(pipe) { |
3465 | /* Clear enable bits; then clear status bits */ | |
3466 | I915_WRITE(PIPESTAT(pipe), 0); | |
3467 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); | |
3468 | } | |
3469 | I915_WRITE16(IMR, 0xffff); | |
3470 | I915_WRITE16(IER, 0x0); | |
3471 | I915_WRITE16(IIR, I915_READ16(IIR)); | |
3472 | } | |
3473 | ||
a266c7d5 CW |
3474 | static void i915_irq_preinstall(struct drm_device * dev) |
3475 | { | |
2d1013dd | 3476 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3477 | int pipe; |
3478 | ||
a266c7d5 CW |
3479 | if (I915_HAS_HOTPLUG(dev)) { |
3480 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3481 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3482 | } | |
3483 | ||
00d98ebd | 3484 | I915_WRITE16(HWSTAM, 0xeffe); |
a266c7d5 CW |
3485 | for_each_pipe(pipe) |
3486 | I915_WRITE(PIPESTAT(pipe), 0); | |
3487 | I915_WRITE(IMR, 0xffffffff); | |
3488 | I915_WRITE(IER, 0x0); | |
3489 | POSTING_READ(IER); | |
3490 | } | |
3491 | ||
3492 | static int i915_irq_postinstall(struct drm_device *dev) | |
3493 | { | |
2d1013dd | 3494 | struct drm_i915_private *dev_priv = dev->dev_private; |
38bde180 | 3495 | u32 enable_mask; |
379ef82d | 3496 | unsigned long irqflags; |
a266c7d5 | 3497 | |
38bde180 CW |
3498 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
3499 | ||
3500 | /* Unmask the interrupts that we always want on. */ | |
3501 | dev_priv->irq_mask = | |
3502 | ~(I915_ASLE_INTERRUPT | | |
3503 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3504 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3505 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3506 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3507 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3508 | ||
3509 | enable_mask = | |
3510 | I915_ASLE_INTERRUPT | | |
3511 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3512 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3513 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
3514 | I915_USER_INTERRUPT; | |
3515 | ||
a266c7d5 | 3516 | if (I915_HAS_HOTPLUG(dev)) { |
20afbda2 DV |
3517 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3518 | POSTING_READ(PORT_HOTPLUG_EN); | |
3519 | ||
a266c7d5 CW |
3520 | /* Enable in IER... */ |
3521 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
3522 | /* and unmask in IMR */ | |
3523 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; | |
3524 | } | |
3525 | ||
a266c7d5 CW |
3526 | I915_WRITE(IMR, dev_priv->irq_mask); |
3527 | I915_WRITE(IER, enable_mask); | |
3528 | POSTING_READ(IER); | |
3529 | ||
f49e38dd | 3530 | i915_enable_asle_pipestat(dev); |
20afbda2 | 3531 | |
379ef82d DV |
3532 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3533 | * just to make the assert_spin_locked check happy. */ | |
3534 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
755e9019 ID |
3535 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3536 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
379ef82d DV |
3537 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
3538 | ||
20afbda2 DV |
3539 | return 0; |
3540 | } | |
3541 | ||
90a72f87 VS |
3542 | /* |
3543 | * Returns true when a page flip has completed. | |
3544 | */ | |
3545 | static bool i915_handle_vblank(struct drm_device *dev, | |
3546 | int plane, int pipe, u32 iir) | |
3547 | { | |
2d1013dd | 3548 | struct drm_i915_private *dev_priv = dev->dev_private; |
90a72f87 VS |
3549 | u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
3550 | ||
3551 | if (!drm_handle_vblank(dev, pipe)) | |
3552 | return false; | |
3553 | ||
3554 | if ((iir & flip_pending) == 0) | |
3555 | return false; | |
3556 | ||
3557 | intel_prepare_page_flip(dev, plane); | |
3558 | ||
3559 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
3560 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3561 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3562 | * the flip is completed (no longer pending). Since this doesn't raise | |
3563 | * an interrupt per se, we watch for the change at vblank. | |
3564 | */ | |
3565 | if (I915_READ(ISR) & flip_pending) | |
3566 | return false; | |
3567 | ||
3568 | intel_finish_page_flip(dev, pipe); | |
3569 | ||
3570 | return true; | |
3571 | } | |
3572 | ||
ff1f525e | 3573 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
a266c7d5 CW |
3574 | { |
3575 | struct drm_device *dev = (struct drm_device *) arg; | |
2d1013dd | 3576 | struct drm_i915_private *dev_priv = dev->dev_private; |
8291ee90 | 3577 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
a266c7d5 | 3578 | unsigned long irqflags; |
38bde180 CW |
3579 | u32 flip_mask = |
3580 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3581 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
38bde180 | 3582 | int pipe, ret = IRQ_NONE; |
a266c7d5 | 3583 | |
a266c7d5 | 3584 | iir = I915_READ(IIR); |
38bde180 CW |
3585 | do { |
3586 | bool irq_received = (iir & ~flip_mask) != 0; | |
8291ee90 | 3587 | bool blc_event = false; |
a266c7d5 CW |
3588 | |
3589 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3590 | * have been cleared after the pipestat interrupt was received. | |
3591 | * It doesn't set the bit in iir again, but it still produces | |
3592 | * interrupts (for non-MSI). | |
3593 | */ | |
3594 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3595 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
58174462 MK |
3596 | i915_handle_error(dev, false, |
3597 | "Command parser error, iir 0x%08x", | |
3598 | iir); | |
a266c7d5 CW |
3599 | |
3600 | for_each_pipe(pipe) { | |
3601 | int reg = PIPESTAT(pipe); | |
3602 | pipe_stats[pipe] = I915_READ(reg); | |
3603 | ||
38bde180 | 3604 | /* Clear the PIPE*STAT regs before the IIR */ |
a266c7d5 | 3605 | if (pipe_stats[pipe] & 0x8000ffff) { |
a266c7d5 | 3606 | I915_WRITE(reg, pipe_stats[pipe]); |
38bde180 | 3607 | irq_received = true; |
a266c7d5 CW |
3608 | } |
3609 | } | |
3610 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3611 | ||
3612 | if (!irq_received) | |
3613 | break; | |
3614 | ||
a266c7d5 | 3615 | /* Consume port. Then clear IIR or we'll miss events */ |
16c6c56b VS |
3616 | if (I915_HAS_HOTPLUG(dev) && |
3617 | iir & I915_DISPLAY_PORT_INTERRUPT) | |
3618 | i9xx_hpd_irq_handler(dev); | |
a266c7d5 | 3619 | |
38bde180 | 3620 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
3621 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
3622 | ||
a266c7d5 CW |
3623 | if (iir & I915_USER_INTERRUPT) |
3624 | notify_ring(dev, &dev_priv->ring[RCS]); | |
a266c7d5 | 3625 | |
a266c7d5 | 3626 | for_each_pipe(pipe) { |
38bde180 | 3627 | int plane = pipe; |
3a77c4c4 | 3628 | if (HAS_FBC(dev)) |
38bde180 | 3629 | plane = !plane; |
90a72f87 | 3630 | |
8291ee90 | 3631 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
3632 | i915_handle_vblank(dev, plane, pipe, iir)) |
3633 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
a266c7d5 CW |
3634 | |
3635 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
3636 | blc_event = true; | |
4356d586 DV |
3637 | |
3638 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 3639 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b VS |
3640 | |
3641 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && | |
3642 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
fc2c807b | 3643 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); |
a266c7d5 CW |
3644 | } |
3645 | ||
a266c7d5 CW |
3646 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
3647 | intel_opregion_asle_intr(dev); | |
3648 | ||
3649 | /* With MSI, interrupts are only generated when iir | |
3650 | * transitions from zero to nonzero. If another bit got | |
3651 | * set while we were handling the existing iir bits, then | |
3652 | * we would never get another interrupt. | |
3653 | * | |
3654 | * This is fine on non-MSI as well, as if we hit this path | |
3655 | * we avoid exiting the interrupt handler only to generate | |
3656 | * another one. | |
3657 | * | |
3658 | * Note that for MSI this could cause a stray interrupt report | |
3659 | * if an interrupt landed in the time between writing IIR and | |
3660 | * the posting read. This should be rare enough to never | |
3661 | * trigger the 99% of 100,000 interrupts test for disabling | |
3662 | * stray interrupts. | |
3663 | */ | |
38bde180 | 3664 | ret = IRQ_HANDLED; |
a266c7d5 | 3665 | iir = new_iir; |
38bde180 | 3666 | } while (iir & ~flip_mask); |
a266c7d5 | 3667 | |
d05c617e | 3668 | i915_update_dri1_breadcrumb(dev); |
8291ee90 | 3669 | |
a266c7d5 CW |
3670 | return ret; |
3671 | } | |
3672 | ||
3673 | static void i915_irq_uninstall(struct drm_device * dev) | |
3674 | { | |
2d1013dd | 3675 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3676 | int pipe; |
3677 | ||
3ca1cced | 3678 | intel_hpd_irq_uninstall(dev_priv); |
ac4c16c5 | 3679 | |
a266c7d5 CW |
3680 | if (I915_HAS_HOTPLUG(dev)) { |
3681 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3682 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3683 | } | |
3684 | ||
00d98ebd | 3685 | I915_WRITE16(HWSTAM, 0xffff); |
55b39755 CW |
3686 | for_each_pipe(pipe) { |
3687 | /* Clear enable bits; then clear status bits */ | |
a266c7d5 | 3688 | I915_WRITE(PIPESTAT(pipe), 0); |
55b39755 CW |
3689 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
3690 | } | |
a266c7d5 CW |
3691 | I915_WRITE(IMR, 0xffffffff); |
3692 | I915_WRITE(IER, 0x0); | |
3693 | ||
a266c7d5 CW |
3694 | I915_WRITE(IIR, I915_READ(IIR)); |
3695 | } | |
3696 | ||
3697 | static void i965_irq_preinstall(struct drm_device * dev) | |
3698 | { | |
2d1013dd | 3699 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3700 | int pipe; |
3701 | ||
adca4730 CW |
3702 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3703 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
3704 | |
3705 | I915_WRITE(HWSTAM, 0xeffe); | |
3706 | for_each_pipe(pipe) | |
3707 | I915_WRITE(PIPESTAT(pipe), 0); | |
3708 | I915_WRITE(IMR, 0xffffffff); | |
3709 | I915_WRITE(IER, 0x0); | |
3710 | POSTING_READ(IER); | |
3711 | } | |
3712 | ||
3713 | static int i965_irq_postinstall(struct drm_device *dev) | |
3714 | { | |
2d1013dd | 3715 | struct drm_i915_private *dev_priv = dev->dev_private; |
bbba0a97 | 3716 | u32 enable_mask; |
a266c7d5 | 3717 | u32 error_mask; |
b79480ba | 3718 | unsigned long irqflags; |
a266c7d5 | 3719 | |
a266c7d5 | 3720 | /* Unmask the interrupts that we always want on. */ |
bbba0a97 | 3721 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
adca4730 | 3722 | I915_DISPLAY_PORT_INTERRUPT | |
bbba0a97 CW |
3723 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
3724 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3725 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3726 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3727 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3728 | ||
3729 | enable_mask = ~dev_priv->irq_mask; | |
21ad8330 VS |
3730 | enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
3731 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); | |
bbba0a97 CW |
3732 | enable_mask |= I915_USER_INTERRUPT; |
3733 | ||
3734 | if (IS_G4X(dev)) | |
3735 | enable_mask |= I915_BSD_USER_INTERRUPT; | |
a266c7d5 | 3736 | |
b79480ba DV |
3737 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3738 | * just to make the assert_spin_locked check happy. */ | |
3739 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
755e9019 ID |
3740 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
3741 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
3742 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
b79480ba | 3743 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
a266c7d5 | 3744 | |
a266c7d5 CW |
3745 | /* |
3746 | * Enable some error detection, note the instruction error mask | |
3747 | * bit is reserved, so we leave it masked. | |
3748 | */ | |
3749 | if (IS_G4X(dev)) { | |
3750 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
3751 | GM45_ERROR_MEM_PRIV | | |
3752 | GM45_ERROR_CP_PRIV | | |
3753 | I915_ERROR_MEMORY_REFRESH); | |
3754 | } else { | |
3755 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
3756 | I915_ERROR_MEMORY_REFRESH); | |
3757 | } | |
3758 | I915_WRITE(EMR, error_mask); | |
3759 | ||
3760 | I915_WRITE(IMR, dev_priv->irq_mask); | |
3761 | I915_WRITE(IER, enable_mask); | |
3762 | POSTING_READ(IER); | |
3763 | ||
20afbda2 DV |
3764 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3765 | POSTING_READ(PORT_HOTPLUG_EN); | |
3766 | ||
f49e38dd | 3767 | i915_enable_asle_pipestat(dev); |
20afbda2 DV |
3768 | |
3769 | return 0; | |
3770 | } | |
3771 | ||
bac56d5b | 3772 | static void i915_hpd_irq_setup(struct drm_device *dev) |
20afbda2 | 3773 | { |
2d1013dd | 3774 | struct drm_i915_private *dev_priv = dev->dev_private; |
e5868a31 | 3775 | struct drm_mode_config *mode_config = &dev->mode_config; |
cd569aed | 3776 | struct intel_encoder *intel_encoder; |
20afbda2 DV |
3777 | u32 hotplug_en; |
3778 | ||
b5ea2d56 DV |
3779 | assert_spin_locked(&dev_priv->irq_lock); |
3780 | ||
bac56d5b EE |
3781 | if (I915_HAS_HOTPLUG(dev)) { |
3782 | hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
3783 | hotplug_en &= ~HOTPLUG_INT_EN_MASK; | |
3784 | /* Note HDMI and DP share hotplug bits */ | |
e5868a31 | 3785 | /* enable bits are the same for all generations */ |
cd569aed EE |
3786 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
3787 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) | |
3788 | hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin]; | |
bac56d5b EE |
3789 | /* Programming the CRT detection parameters tends |
3790 | to generate a spurious hotplug event about three | |
3791 | seconds later. So just do it once. | |
3792 | */ | |
3793 | if (IS_G4X(dev)) | |
3794 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
85fc95ba | 3795 | hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK; |
bac56d5b | 3796 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
a266c7d5 | 3797 | |
bac56d5b EE |
3798 | /* Ignore TV since it's buggy */ |
3799 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
3800 | } | |
a266c7d5 CW |
3801 | } |
3802 | ||
ff1f525e | 3803 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
a266c7d5 CW |
3804 | { |
3805 | struct drm_device *dev = (struct drm_device *) arg; | |
2d1013dd | 3806 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3807 | u32 iir, new_iir; |
3808 | u32 pipe_stats[I915_MAX_PIPES]; | |
a266c7d5 | 3809 | unsigned long irqflags; |
a266c7d5 | 3810 | int ret = IRQ_NONE, pipe; |
21ad8330 VS |
3811 | u32 flip_mask = |
3812 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3813 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
a266c7d5 | 3814 | |
a266c7d5 CW |
3815 | iir = I915_READ(IIR); |
3816 | ||
a266c7d5 | 3817 | for (;;) { |
501e01d7 | 3818 | bool irq_received = (iir & ~flip_mask) != 0; |
2c8ba29f CW |
3819 | bool blc_event = false; |
3820 | ||
a266c7d5 CW |
3821 | /* Can't rely on pipestat interrupt bit in iir as it might |
3822 | * have been cleared after the pipestat interrupt was received. | |
3823 | * It doesn't set the bit in iir again, but it still produces | |
3824 | * interrupts (for non-MSI). | |
3825 | */ | |
3826 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3827 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
58174462 MK |
3828 | i915_handle_error(dev, false, |
3829 | "Command parser error, iir 0x%08x", | |
3830 | iir); | |
a266c7d5 CW |
3831 | |
3832 | for_each_pipe(pipe) { | |
3833 | int reg = PIPESTAT(pipe); | |
3834 | pipe_stats[pipe] = I915_READ(reg); | |
3835 | ||
3836 | /* | |
3837 | * Clear the PIPE*STAT regs before the IIR | |
3838 | */ | |
3839 | if (pipe_stats[pipe] & 0x8000ffff) { | |
a266c7d5 | 3840 | I915_WRITE(reg, pipe_stats[pipe]); |
501e01d7 | 3841 | irq_received = true; |
a266c7d5 CW |
3842 | } |
3843 | } | |
3844 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3845 | ||
3846 | if (!irq_received) | |
3847 | break; | |
3848 | ||
3849 | ret = IRQ_HANDLED; | |
3850 | ||
3851 | /* Consume port. Then clear IIR or we'll miss events */ | |
16c6c56b VS |
3852 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
3853 | i9xx_hpd_irq_handler(dev); | |
a266c7d5 | 3854 | |
21ad8330 | 3855 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
3856 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
3857 | ||
a266c7d5 CW |
3858 | if (iir & I915_USER_INTERRUPT) |
3859 | notify_ring(dev, &dev_priv->ring[RCS]); | |
3860 | if (iir & I915_BSD_USER_INTERRUPT) | |
3861 | notify_ring(dev, &dev_priv->ring[VCS]); | |
3862 | ||
a266c7d5 | 3863 | for_each_pipe(pipe) { |
2c8ba29f | 3864 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
3865 | i915_handle_vblank(dev, pipe, pipe, iir)) |
3866 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); | |
a266c7d5 CW |
3867 | |
3868 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
3869 | blc_event = true; | |
4356d586 DV |
3870 | |
3871 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 3872 | i9xx_pipe_crc_irq_handler(dev, pipe); |
a266c7d5 | 3873 | |
2d9d2b0b VS |
3874 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && |
3875 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
fc2c807b | 3876 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); |
2d9d2b0b | 3877 | } |
a266c7d5 CW |
3878 | |
3879 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | |
3880 | intel_opregion_asle_intr(dev); | |
3881 | ||
515ac2bb DV |
3882 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
3883 | gmbus_irq_handler(dev); | |
3884 | ||
a266c7d5 CW |
3885 | /* With MSI, interrupts are only generated when iir |
3886 | * transitions from zero to nonzero. If another bit got | |
3887 | * set while we were handling the existing iir bits, then | |
3888 | * we would never get another interrupt. | |
3889 | * | |
3890 | * This is fine on non-MSI as well, as if we hit this path | |
3891 | * we avoid exiting the interrupt handler only to generate | |
3892 | * another one. | |
3893 | * | |
3894 | * Note that for MSI this could cause a stray interrupt report | |
3895 | * if an interrupt landed in the time between writing IIR and | |
3896 | * the posting read. This should be rare enough to never | |
3897 | * trigger the 99% of 100,000 interrupts test for disabling | |
3898 | * stray interrupts. | |
3899 | */ | |
3900 | iir = new_iir; | |
3901 | } | |
3902 | ||
d05c617e | 3903 | i915_update_dri1_breadcrumb(dev); |
2c8ba29f | 3904 | |
a266c7d5 CW |
3905 | return ret; |
3906 | } | |
3907 | ||
3908 | static void i965_irq_uninstall(struct drm_device * dev) | |
3909 | { | |
2d1013dd | 3910 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3911 | int pipe; |
3912 | ||
3913 | if (!dev_priv) | |
3914 | return; | |
3915 | ||
3ca1cced | 3916 | intel_hpd_irq_uninstall(dev_priv); |
ac4c16c5 | 3917 | |
adca4730 CW |
3918 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3919 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
3920 | |
3921 | I915_WRITE(HWSTAM, 0xffffffff); | |
3922 | for_each_pipe(pipe) | |
3923 | I915_WRITE(PIPESTAT(pipe), 0); | |
3924 | I915_WRITE(IMR, 0xffffffff); | |
3925 | I915_WRITE(IER, 0x0); | |
3926 | ||
3927 | for_each_pipe(pipe) | |
3928 | I915_WRITE(PIPESTAT(pipe), | |
3929 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); | |
3930 | I915_WRITE(IIR, I915_READ(IIR)); | |
3931 | } | |
3932 | ||
3ca1cced | 3933 | static void intel_hpd_irq_reenable(unsigned long data) |
ac4c16c5 | 3934 | { |
2d1013dd | 3935 | struct drm_i915_private *dev_priv = (struct drm_i915_private *)data; |
ac4c16c5 EE |
3936 | struct drm_device *dev = dev_priv->dev; |
3937 | struct drm_mode_config *mode_config = &dev->mode_config; | |
3938 | unsigned long irqflags; | |
3939 | int i; | |
3940 | ||
3941 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3942 | for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) { | |
3943 | struct drm_connector *connector; | |
3944 | ||
3945 | if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED) | |
3946 | continue; | |
3947 | ||
3948 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
3949 | ||
3950 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
3951 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
3952 | ||
3953 | if (intel_connector->encoder->hpd_pin == i) { | |
3954 | if (connector->polled != intel_connector->polled) | |
3955 | DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n", | |
3956 | drm_get_connector_name(connector)); | |
3957 | connector->polled = intel_connector->polled; | |
3958 | if (!connector->polled) | |
3959 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
3960 | } | |
3961 | } | |
3962 | } | |
3963 | if (dev_priv->display.hpd_irq_setup) | |
3964 | dev_priv->display.hpd_irq_setup(dev); | |
3965 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3966 | } | |
3967 | ||
f71d4af4 JB |
3968 | void intel_irq_init(struct drm_device *dev) |
3969 | { | |
8b2e326d CW |
3970 | struct drm_i915_private *dev_priv = dev->dev_private; |
3971 | ||
3972 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); | |
99584db3 | 3973 | INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func); |
c6a828d3 | 3974 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
a4da4fa4 | 3975 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
8b2e326d | 3976 | |
a6706b45 D |
3977 | /* Let's track the enabled rps events */ |
3978 | dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; | |
3979 | ||
99584db3 DV |
3980 | setup_timer(&dev_priv->gpu_error.hangcheck_timer, |
3981 | i915_hangcheck_elapsed, | |
61bac78e | 3982 | (unsigned long) dev); |
3ca1cced | 3983 | setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable, |
ac4c16c5 | 3984 | (unsigned long) dev_priv); |
61bac78e | 3985 | |
97a19a24 | 3986 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); |
9ee32fea | 3987 | |
4cdb83ec VS |
3988 | if (IS_GEN2(dev)) { |
3989 | dev->max_vblank_count = 0; | |
3990 | dev->driver->get_vblank_counter = i8xx_get_vblank_counter; | |
3991 | } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { | |
f71d4af4 JB |
3992 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
3993 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; | |
391f75e2 VS |
3994 | } else { |
3995 | dev->driver->get_vblank_counter = i915_get_vblank_counter; | |
3996 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
f71d4af4 JB |
3997 | } |
3998 | ||
c2baf4b7 | 3999 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
c3613de9 | 4000 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; |
c2baf4b7 VS |
4001 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; |
4002 | } | |
f71d4af4 | 4003 | |
7e231dbe JB |
4004 | if (IS_VALLEYVIEW(dev)) { |
4005 | dev->driver->irq_handler = valleyview_irq_handler; | |
4006 | dev->driver->irq_preinstall = valleyview_irq_preinstall; | |
4007 | dev->driver->irq_postinstall = valleyview_irq_postinstall; | |
4008 | dev->driver->irq_uninstall = valleyview_irq_uninstall; | |
4009 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4010 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
fa00abe0 | 4011 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
abd58f01 BW |
4012 | } else if (IS_GEN8(dev)) { |
4013 | dev->driver->irq_handler = gen8_irq_handler; | |
4014 | dev->driver->irq_preinstall = gen8_irq_preinstall; | |
4015 | dev->driver->irq_postinstall = gen8_irq_postinstall; | |
4016 | dev->driver->irq_uninstall = gen8_irq_uninstall; | |
4017 | dev->driver->enable_vblank = gen8_enable_vblank; | |
4018 | dev->driver->disable_vblank = gen8_disable_vblank; | |
4019 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; | |
f71d4af4 JB |
4020 | } else if (HAS_PCH_SPLIT(dev)) { |
4021 | dev->driver->irq_handler = ironlake_irq_handler; | |
4022 | dev->driver->irq_preinstall = ironlake_irq_preinstall; | |
4023 | dev->driver->irq_postinstall = ironlake_irq_postinstall; | |
4024 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
4025 | dev->driver->enable_vblank = ironlake_enable_vblank; | |
4026 | dev->driver->disable_vblank = ironlake_disable_vblank; | |
82a28bcf | 4027 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; |
f71d4af4 | 4028 | } else { |
c2798b19 CW |
4029 | if (INTEL_INFO(dev)->gen == 2) { |
4030 | dev->driver->irq_preinstall = i8xx_irq_preinstall; | |
4031 | dev->driver->irq_postinstall = i8xx_irq_postinstall; | |
4032 | dev->driver->irq_handler = i8xx_irq_handler; | |
4033 | dev->driver->irq_uninstall = i8xx_irq_uninstall; | |
a266c7d5 CW |
4034 | } else if (INTEL_INFO(dev)->gen == 3) { |
4035 | dev->driver->irq_preinstall = i915_irq_preinstall; | |
4036 | dev->driver->irq_postinstall = i915_irq_postinstall; | |
4037 | dev->driver->irq_uninstall = i915_irq_uninstall; | |
4038 | dev->driver->irq_handler = i915_irq_handler; | |
20afbda2 | 4039 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
c2798b19 | 4040 | } else { |
a266c7d5 CW |
4041 | dev->driver->irq_preinstall = i965_irq_preinstall; |
4042 | dev->driver->irq_postinstall = i965_irq_postinstall; | |
4043 | dev->driver->irq_uninstall = i965_irq_uninstall; | |
4044 | dev->driver->irq_handler = i965_irq_handler; | |
bac56d5b | 4045 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
c2798b19 | 4046 | } |
f71d4af4 JB |
4047 | dev->driver->enable_vblank = i915_enable_vblank; |
4048 | dev->driver->disable_vblank = i915_disable_vblank; | |
4049 | } | |
4050 | } | |
20afbda2 DV |
4051 | |
4052 | void intel_hpd_init(struct drm_device *dev) | |
4053 | { | |
4054 | struct drm_i915_private *dev_priv = dev->dev_private; | |
821450c6 EE |
4055 | struct drm_mode_config *mode_config = &dev->mode_config; |
4056 | struct drm_connector *connector; | |
b5ea2d56 | 4057 | unsigned long irqflags; |
821450c6 | 4058 | int i; |
20afbda2 | 4059 | |
821450c6 EE |
4060 | for (i = 1; i < HPD_NUM_PINS; i++) { |
4061 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
4062 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
4063 | } | |
4064 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
4065 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4066 | connector->polled = intel_connector->polled; | |
4067 | if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE) | |
4068 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
4069 | } | |
b5ea2d56 DV |
4070 | |
4071 | /* Interrupt setup is already guaranteed to be single-threaded, this is | |
4072 | * just to make the assert_spin_locked checks happy. */ | |
4073 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
20afbda2 DV |
4074 | if (dev_priv->display.hpd_irq_setup) |
4075 | dev_priv->display.hpd_irq_setup(dev); | |
b5ea2d56 | 4076 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
20afbda2 | 4077 | } |
c67a470b | 4078 | |
5d584b2e | 4079 | /* Disable interrupts so we can allow runtime PM. */ |
730488b2 | 4080 | void intel_runtime_pm_disable_interrupts(struct drm_device *dev) |
c67a470b PZ |
4081 | { |
4082 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c67a470b | 4083 | |
730488b2 | 4084 | dev->driver->irq_uninstall(dev); |
5d584b2e | 4085 | dev_priv->pm.irqs_disabled = true; |
c67a470b PZ |
4086 | } |
4087 | ||
5d584b2e | 4088 | /* Restore interrupts so we can recover from runtime PM. */ |
730488b2 | 4089 | void intel_runtime_pm_restore_interrupts(struct drm_device *dev) |
c67a470b PZ |
4090 | { |
4091 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c67a470b | 4092 | |
5d584b2e | 4093 | dev_priv->pm.irqs_disabled = false; |
730488b2 PZ |
4094 | dev->driver->irq_preinstall(dev); |
4095 | dev->driver->irq_postinstall(dev); | |
c67a470b | 4096 | } |