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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
63eeaf38 | 31 | #include <linux/sysrq.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
b2c88f5b | 33 | #include <linux/circ_buf.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/i915_drm.h> | |
1da177e4 | 36 | #include "i915_drv.h" |
1c5d22f7 | 37 | #include "i915_trace.h" |
79e53945 | 38 | #include "intel_drv.h" |
1da177e4 | 39 | |
e5868a31 EE |
40 | static const u32 hpd_ibx[] = { |
41 | [HPD_CRT] = SDE_CRT_HOTPLUG, | |
42 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, | |
43 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG, | |
44 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG, | |
45 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG | |
46 | }; | |
47 | ||
48 | static const u32 hpd_cpt[] = { | |
49 | [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, | |
73c352a2 | 50 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, |
e5868a31 EE |
51 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
52 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
53 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT | |
54 | }; | |
55 | ||
56 | static const u32 hpd_mask_i915[] = { | |
57 | [HPD_CRT] = CRT_HOTPLUG_INT_EN, | |
58 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, | |
59 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, | |
60 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, | |
61 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, | |
62 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN | |
63 | }; | |
64 | ||
704cfb87 | 65 | static const u32 hpd_status_g4x[] = { |
e5868a31 EE |
66 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
67 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, | |
68 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, | |
69 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
70 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
71 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
72 | }; | |
73 | ||
e5868a31 EE |
74 | static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ |
75 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, | |
76 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, | |
77 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, | |
78 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
79 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
80 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
81 | }; | |
82 | ||
5c502442 | 83 | /* IIR can theoretically queue up two events. Be paranoid. */ |
f86f3fb0 | 84 | #define GEN8_IRQ_RESET_NDX(type, which) do { \ |
5c502442 PZ |
85 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ |
86 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
87 | I915_WRITE(GEN8_##type##_IER(which), 0); \ | |
88 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
89 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
90 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
91 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
92 | } while (0) | |
93 | ||
f86f3fb0 | 94 | #define GEN5_IRQ_RESET(type) do { \ |
a9d356a6 | 95 | I915_WRITE(type##IMR, 0xffffffff); \ |
5c502442 | 96 | POSTING_READ(type##IMR); \ |
a9d356a6 | 97 | I915_WRITE(type##IER, 0); \ |
5c502442 PZ |
98 | I915_WRITE(type##IIR, 0xffffffff); \ |
99 | POSTING_READ(type##IIR); \ | |
100 | I915_WRITE(type##IIR, 0xffffffff); \ | |
101 | POSTING_READ(type##IIR); \ | |
a9d356a6 PZ |
102 | } while (0) |
103 | ||
337ba017 PZ |
104 | /* |
105 | * We should clear IMR at preinstall/uninstall, and just check at postinstall. | |
106 | */ | |
107 | #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \ | |
108 | u32 val = I915_READ(reg); \ | |
109 | if (val) { \ | |
110 | WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \ | |
111 | (reg), val); \ | |
112 | I915_WRITE((reg), 0xffffffff); \ | |
113 | POSTING_READ(reg); \ | |
114 | I915_WRITE((reg), 0xffffffff); \ | |
115 | POSTING_READ(reg); \ | |
116 | } \ | |
117 | } while (0) | |
118 | ||
35079899 | 119 | #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \ |
337ba017 | 120 | GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \ |
35079899 PZ |
121 | I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \ |
122 | I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \ | |
123 | POSTING_READ(GEN8_##type##_IER(which)); \ | |
124 | } while (0) | |
125 | ||
126 | #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \ | |
337ba017 | 127 | GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \ |
35079899 PZ |
128 | I915_WRITE(type##IMR, (imr_val)); \ |
129 | I915_WRITE(type##IER, (ier_val)); \ | |
130 | POSTING_READ(type##IER); \ | |
131 | } while (0) | |
132 | ||
036a4a7d | 133 | /* For display hotplug interrupt */ |
995b6762 | 134 | static void |
2d1013dd | 135 | ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask) |
036a4a7d | 136 | { |
4bc9d430 DV |
137 | assert_spin_locked(&dev_priv->irq_lock); |
138 | ||
730488b2 | 139 | if (WARN_ON(dev_priv->pm.irqs_disabled)) |
c67a470b | 140 | return; |
c67a470b | 141 | |
1ec14ad3 CW |
142 | if ((dev_priv->irq_mask & mask) != 0) { |
143 | dev_priv->irq_mask &= ~mask; | |
144 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 145 | POSTING_READ(DEIMR); |
036a4a7d ZW |
146 | } |
147 | } | |
148 | ||
0ff9800a | 149 | static void |
2d1013dd | 150 | ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask) |
036a4a7d | 151 | { |
4bc9d430 DV |
152 | assert_spin_locked(&dev_priv->irq_lock); |
153 | ||
730488b2 | 154 | if (WARN_ON(dev_priv->pm.irqs_disabled)) |
c67a470b | 155 | return; |
c67a470b | 156 | |
1ec14ad3 CW |
157 | if ((dev_priv->irq_mask & mask) != mask) { |
158 | dev_priv->irq_mask |= mask; | |
159 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 160 | POSTING_READ(DEIMR); |
036a4a7d ZW |
161 | } |
162 | } | |
163 | ||
43eaea13 PZ |
164 | /** |
165 | * ilk_update_gt_irq - update GTIMR | |
166 | * @dev_priv: driver private | |
167 | * @interrupt_mask: mask of interrupt bits to update | |
168 | * @enabled_irq_mask: mask of interrupt bits to enable | |
169 | */ | |
170 | static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, | |
171 | uint32_t interrupt_mask, | |
172 | uint32_t enabled_irq_mask) | |
173 | { | |
174 | assert_spin_locked(&dev_priv->irq_lock); | |
175 | ||
730488b2 | 176 | if (WARN_ON(dev_priv->pm.irqs_disabled)) |
c67a470b | 177 | return; |
c67a470b | 178 | |
43eaea13 PZ |
179 | dev_priv->gt_irq_mask &= ~interrupt_mask; |
180 | dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); | |
181 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
182 | POSTING_READ(GTIMR); | |
183 | } | |
184 | ||
185 | void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
186 | { | |
187 | ilk_update_gt_irq(dev_priv, mask, mask); | |
188 | } | |
189 | ||
190 | void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
191 | { | |
192 | ilk_update_gt_irq(dev_priv, mask, 0); | |
193 | } | |
194 | ||
edbfdb45 PZ |
195 | /** |
196 | * snb_update_pm_irq - update GEN6_PMIMR | |
197 | * @dev_priv: driver private | |
198 | * @interrupt_mask: mask of interrupt bits to update | |
199 | * @enabled_irq_mask: mask of interrupt bits to enable | |
200 | */ | |
201 | static void snb_update_pm_irq(struct drm_i915_private *dev_priv, | |
202 | uint32_t interrupt_mask, | |
203 | uint32_t enabled_irq_mask) | |
204 | { | |
605cd25b | 205 | uint32_t new_val; |
edbfdb45 PZ |
206 | |
207 | assert_spin_locked(&dev_priv->irq_lock); | |
208 | ||
730488b2 | 209 | if (WARN_ON(dev_priv->pm.irqs_disabled)) |
c67a470b | 210 | return; |
c67a470b | 211 | |
605cd25b | 212 | new_val = dev_priv->pm_irq_mask; |
f52ecbcf PZ |
213 | new_val &= ~interrupt_mask; |
214 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
215 | ||
605cd25b PZ |
216 | if (new_val != dev_priv->pm_irq_mask) { |
217 | dev_priv->pm_irq_mask = new_val; | |
218 | I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask); | |
f52ecbcf PZ |
219 | POSTING_READ(GEN6_PMIMR); |
220 | } | |
edbfdb45 PZ |
221 | } |
222 | ||
223 | void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
224 | { | |
225 | snb_update_pm_irq(dev_priv, mask, mask); | |
226 | } | |
227 | ||
228 | void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
229 | { | |
230 | snb_update_pm_irq(dev_priv, mask, 0); | |
231 | } | |
232 | ||
8664281b PZ |
233 | static bool ivb_can_enable_err_int(struct drm_device *dev) |
234 | { | |
235 | struct drm_i915_private *dev_priv = dev->dev_private; | |
236 | struct intel_crtc *crtc; | |
237 | enum pipe pipe; | |
238 | ||
4bc9d430 DV |
239 | assert_spin_locked(&dev_priv->irq_lock); |
240 | ||
8664281b PZ |
241 | for_each_pipe(pipe) { |
242 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
243 | ||
244 | if (crtc->cpu_fifo_underrun_disabled) | |
245 | return false; | |
246 | } | |
247 | ||
248 | return true; | |
249 | } | |
250 | ||
0961021a BW |
251 | /** |
252 | * bdw_update_pm_irq - update GT interrupt 2 | |
253 | * @dev_priv: driver private | |
254 | * @interrupt_mask: mask of interrupt bits to update | |
255 | * @enabled_irq_mask: mask of interrupt bits to enable | |
256 | * | |
257 | * Copied from the snb function, updated with relevant register offsets | |
258 | */ | |
259 | static void bdw_update_pm_irq(struct drm_i915_private *dev_priv, | |
260 | uint32_t interrupt_mask, | |
261 | uint32_t enabled_irq_mask) | |
262 | { | |
263 | uint32_t new_val; | |
264 | ||
265 | assert_spin_locked(&dev_priv->irq_lock); | |
266 | ||
267 | if (WARN_ON(dev_priv->pm.irqs_disabled)) | |
268 | return; | |
269 | ||
270 | new_val = dev_priv->pm_irq_mask; | |
271 | new_val &= ~interrupt_mask; | |
272 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
273 | ||
274 | if (new_val != dev_priv->pm_irq_mask) { | |
275 | dev_priv->pm_irq_mask = new_val; | |
276 | I915_WRITE(GEN8_GT_IMR(2), dev_priv->pm_irq_mask); | |
277 | POSTING_READ(GEN8_GT_IMR(2)); | |
278 | } | |
279 | } | |
280 | ||
281 | void bdw_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
282 | { | |
283 | bdw_update_pm_irq(dev_priv, mask, mask); | |
284 | } | |
285 | ||
286 | void bdw_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
287 | { | |
288 | bdw_update_pm_irq(dev_priv, mask, 0); | |
289 | } | |
290 | ||
8664281b PZ |
291 | static bool cpt_can_enable_serr_int(struct drm_device *dev) |
292 | { | |
293 | struct drm_i915_private *dev_priv = dev->dev_private; | |
294 | enum pipe pipe; | |
295 | struct intel_crtc *crtc; | |
296 | ||
fee884ed DV |
297 | assert_spin_locked(&dev_priv->irq_lock); |
298 | ||
8664281b PZ |
299 | for_each_pipe(pipe) { |
300 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
301 | ||
302 | if (crtc->pch_fifo_underrun_disabled) | |
303 | return false; | |
304 | } | |
305 | ||
306 | return true; | |
307 | } | |
308 | ||
56b80e1f VS |
309 | void i9xx_check_fifo_underruns(struct drm_device *dev) |
310 | { | |
311 | struct drm_i915_private *dev_priv = dev->dev_private; | |
312 | struct intel_crtc *crtc; | |
313 | unsigned long flags; | |
314 | ||
315 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
316 | ||
317 | for_each_intel_crtc(dev, crtc) { | |
318 | u32 reg = PIPESTAT(crtc->pipe); | |
319 | u32 pipestat; | |
320 | ||
321 | if (crtc->cpu_fifo_underrun_disabled) | |
322 | continue; | |
323 | ||
324 | pipestat = I915_READ(reg) & 0xffff0000; | |
325 | if ((pipestat & PIPE_FIFO_UNDERRUN_STATUS) == 0) | |
326 | continue; | |
327 | ||
328 | I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS); | |
329 | POSTING_READ(reg); | |
330 | ||
331 | DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe)); | |
332 | } | |
333 | ||
334 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
335 | } | |
336 | ||
e69abff0 VS |
337 | static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev, |
338 | enum pipe pipe, bool enable) | |
2d9d2b0b VS |
339 | { |
340 | struct drm_i915_private *dev_priv = dev->dev_private; | |
341 | u32 reg = PIPESTAT(pipe); | |
e69abff0 | 342 | u32 pipestat = I915_READ(reg) & 0xffff0000; |
2d9d2b0b VS |
343 | |
344 | assert_spin_locked(&dev_priv->irq_lock); | |
345 | ||
e69abff0 VS |
346 | if (enable) { |
347 | I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS); | |
348 | POSTING_READ(reg); | |
349 | } else { | |
350 | if (pipestat & PIPE_FIFO_UNDERRUN_STATUS) | |
351 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); | |
352 | } | |
2d9d2b0b VS |
353 | } |
354 | ||
8664281b PZ |
355 | static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev, |
356 | enum pipe pipe, bool enable) | |
357 | { | |
358 | struct drm_i915_private *dev_priv = dev->dev_private; | |
359 | uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN : | |
360 | DE_PIPEB_FIFO_UNDERRUN; | |
361 | ||
362 | if (enable) | |
363 | ironlake_enable_display_irq(dev_priv, bit); | |
364 | else | |
365 | ironlake_disable_display_irq(dev_priv, bit); | |
366 | } | |
367 | ||
368 | static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev, | |
7336df65 | 369 | enum pipe pipe, bool enable) |
8664281b PZ |
370 | { |
371 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8664281b | 372 | if (enable) { |
7336df65 DV |
373 | I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); |
374 | ||
8664281b PZ |
375 | if (!ivb_can_enable_err_int(dev)) |
376 | return; | |
377 | ||
8664281b PZ |
378 | ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB); |
379 | } else { | |
380 | ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB); | |
7336df65 | 381 | |
29c6b0c5 | 382 | if (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { |
823c6909 VS |
383 | DRM_ERROR("uncleared fifo underrun on pipe %c\n", |
384 | pipe_name(pipe)); | |
7336df65 | 385 | } |
8664281b PZ |
386 | } |
387 | } | |
388 | ||
38d83c96 DV |
389 | static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev, |
390 | enum pipe pipe, bool enable) | |
391 | { | |
392 | struct drm_i915_private *dev_priv = dev->dev_private; | |
393 | ||
394 | assert_spin_locked(&dev_priv->irq_lock); | |
395 | ||
396 | if (enable) | |
397 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN; | |
398 | else | |
399 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN; | |
400 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
401 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
402 | } | |
403 | ||
fee884ed DV |
404 | /** |
405 | * ibx_display_interrupt_update - update SDEIMR | |
406 | * @dev_priv: driver private | |
407 | * @interrupt_mask: mask of interrupt bits to update | |
408 | * @enabled_irq_mask: mask of interrupt bits to enable | |
409 | */ | |
410 | static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, | |
411 | uint32_t interrupt_mask, | |
412 | uint32_t enabled_irq_mask) | |
413 | { | |
414 | uint32_t sdeimr = I915_READ(SDEIMR); | |
415 | sdeimr &= ~interrupt_mask; | |
416 | sdeimr |= (~enabled_irq_mask & interrupt_mask); | |
417 | ||
418 | assert_spin_locked(&dev_priv->irq_lock); | |
419 | ||
730488b2 | 420 | if (WARN_ON(dev_priv->pm.irqs_disabled)) |
c67a470b | 421 | return; |
c67a470b | 422 | |
fee884ed DV |
423 | I915_WRITE(SDEIMR, sdeimr); |
424 | POSTING_READ(SDEIMR); | |
425 | } | |
426 | #define ibx_enable_display_interrupt(dev_priv, bits) \ | |
427 | ibx_display_interrupt_update((dev_priv), (bits), (bits)) | |
428 | #define ibx_disable_display_interrupt(dev_priv, bits) \ | |
429 | ibx_display_interrupt_update((dev_priv), (bits), 0) | |
430 | ||
de28075d DV |
431 | static void ibx_set_fifo_underrun_reporting(struct drm_device *dev, |
432 | enum transcoder pch_transcoder, | |
8664281b PZ |
433 | bool enable) |
434 | { | |
8664281b | 435 | struct drm_i915_private *dev_priv = dev->dev_private; |
de28075d DV |
436 | uint32_t bit = (pch_transcoder == TRANSCODER_A) ? |
437 | SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER; | |
8664281b PZ |
438 | |
439 | if (enable) | |
fee884ed | 440 | ibx_enable_display_interrupt(dev_priv, bit); |
8664281b | 441 | else |
fee884ed | 442 | ibx_disable_display_interrupt(dev_priv, bit); |
8664281b PZ |
443 | } |
444 | ||
445 | static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, | |
446 | enum transcoder pch_transcoder, | |
447 | bool enable) | |
448 | { | |
449 | struct drm_i915_private *dev_priv = dev->dev_private; | |
450 | ||
451 | if (enable) { | |
1dd246fb DV |
452 | I915_WRITE(SERR_INT, |
453 | SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); | |
454 | ||
8664281b PZ |
455 | if (!cpt_can_enable_serr_int(dev)) |
456 | return; | |
457 | ||
fee884ed | 458 | ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
8664281b | 459 | } else { |
fee884ed | 460 | ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
1dd246fb | 461 | |
29c6b0c5 | 462 | if (I915_READ(SERR_INT) & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) { |
823c6909 VS |
463 | DRM_ERROR("uncleared pch fifo underrun on pch transcoder %c\n", |
464 | transcoder_name(pch_transcoder)); | |
1dd246fb | 465 | } |
8664281b | 466 | } |
8664281b PZ |
467 | } |
468 | ||
469 | /** | |
470 | * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages | |
471 | * @dev: drm device | |
472 | * @pipe: pipe | |
473 | * @enable: true if we want to report FIFO underrun errors, false otherwise | |
474 | * | |
475 | * This function makes us disable or enable CPU fifo underruns for a specific | |
476 | * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun | |
477 | * reporting for one pipe may also disable all the other CPU error interruts for | |
478 | * the other pipes, due to the fact that there's just one interrupt mask/enable | |
479 | * bit for all the pipes. | |
480 | * | |
481 | * Returns the previous state of underrun reporting. | |
482 | */ | |
c5ab3bc0 DV |
483 | static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, |
484 | enum pipe pipe, bool enable) | |
8664281b PZ |
485 | { |
486 | struct drm_i915_private *dev_priv = dev->dev_private; | |
487 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
488 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8664281b PZ |
489 | bool ret; |
490 | ||
77961eb9 ID |
491 | assert_spin_locked(&dev_priv->irq_lock); |
492 | ||
8664281b PZ |
493 | ret = !intel_crtc->cpu_fifo_underrun_disabled; |
494 | ||
495 | if (enable == ret) | |
496 | goto done; | |
497 | ||
498 | intel_crtc->cpu_fifo_underrun_disabled = !enable; | |
499 | ||
e69abff0 VS |
500 | if (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)) |
501 | i9xx_set_fifo_underrun_reporting(dev, pipe, enable); | |
2d9d2b0b | 502 | else if (IS_GEN5(dev) || IS_GEN6(dev)) |
8664281b PZ |
503 | ironlake_set_fifo_underrun_reporting(dev, pipe, enable); |
504 | else if (IS_GEN7(dev)) | |
7336df65 | 505 | ivybridge_set_fifo_underrun_reporting(dev, pipe, enable); |
38d83c96 DV |
506 | else if (IS_GEN8(dev)) |
507 | broadwell_set_fifo_underrun_reporting(dev, pipe, enable); | |
8664281b PZ |
508 | |
509 | done: | |
f88d42f1 ID |
510 | return ret; |
511 | } | |
512 | ||
513 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, | |
514 | enum pipe pipe, bool enable) | |
515 | { | |
516 | struct drm_i915_private *dev_priv = dev->dev_private; | |
517 | unsigned long flags; | |
518 | bool ret; | |
519 | ||
520 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
521 | ret = __intel_set_cpu_fifo_underrun_reporting(dev, pipe, enable); | |
8664281b | 522 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
f88d42f1 | 523 | |
8664281b PZ |
524 | return ret; |
525 | } | |
526 | ||
91d181dd ID |
527 | static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev, |
528 | enum pipe pipe) | |
529 | { | |
530 | struct drm_i915_private *dev_priv = dev->dev_private; | |
531 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
532 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
533 | ||
534 | return !intel_crtc->cpu_fifo_underrun_disabled; | |
535 | } | |
536 | ||
8664281b PZ |
537 | /** |
538 | * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages | |
539 | * @dev: drm device | |
540 | * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) | |
541 | * @enable: true if we want to report FIFO underrun errors, false otherwise | |
542 | * | |
543 | * This function makes us disable or enable PCH fifo underruns for a specific | |
544 | * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO | |
545 | * underrun reporting for one transcoder may also disable all the other PCH | |
546 | * error interruts for the other transcoders, due to the fact that there's just | |
547 | * one interrupt mask/enable bit for all the transcoders. | |
548 | * | |
549 | * Returns the previous state of underrun reporting. | |
550 | */ | |
551 | bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, | |
552 | enum transcoder pch_transcoder, | |
553 | bool enable) | |
554 | { | |
555 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de28075d DV |
556 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder]; |
557 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8664281b PZ |
558 | unsigned long flags; |
559 | bool ret; | |
560 | ||
de28075d DV |
561 | /* |
562 | * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT | |
563 | * has only one pch transcoder A that all pipes can use. To avoid racy | |
564 | * pch transcoder -> pipe lookups from interrupt code simply store the | |
565 | * underrun statistics in crtc A. Since we never expose this anywhere | |
566 | * nor use it outside of the fifo underrun code here using the "wrong" | |
567 | * crtc on LPT won't cause issues. | |
568 | */ | |
8664281b PZ |
569 | |
570 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
571 | ||
572 | ret = !intel_crtc->pch_fifo_underrun_disabled; | |
573 | ||
574 | if (enable == ret) | |
575 | goto done; | |
576 | ||
577 | intel_crtc->pch_fifo_underrun_disabled = !enable; | |
578 | ||
579 | if (HAS_PCH_IBX(dev)) | |
de28075d | 580 | ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable); |
8664281b PZ |
581 | else |
582 | cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable); | |
583 | ||
584 | done: | |
585 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
586 | return ret; | |
587 | } | |
588 | ||
589 | ||
b5ea642a | 590 | static void |
755e9019 ID |
591 | __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
592 | u32 enable_mask, u32 status_mask) | |
7c463586 | 593 | { |
46c06a30 | 594 | u32 reg = PIPESTAT(pipe); |
755e9019 | 595 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 596 | |
b79480ba DV |
597 | assert_spin_locked(&dev_priv->irq_lock); |
598 | ||
04feced9 VS |
599 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
600 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
601 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
602 | pipe_name(pipe), enable_mask, status_mask)) | |
755e9019 ID |
603 | return; |
604 | ||
605 | if ((pipestat & enable_mask) == enable_mask) | |
46c06a30 VS |
606 | return; |
607 | ||
91d181dd ID |
608 | dev_priv->pipestat_irq_mask[pipe] |= status_mask; |
609 | ||
46c06a30 | 610 | /* Enable the interrupt, clear any pending status */ |
755e9019 | 611 | pipestat |= enable_mask | status_mask; |
46c06a30 VS |
612 | I915_WRITE(reg, pipestat); |
613 | POSTING_READ(reg); | |
7c463586 KP |
614 | } |
615 | ||
b5ea642a | 616 | static void |
755e9019 ID |
617 | __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
618 | u32 enable_mask, u32 status_mask) | |
7c463586 | 619 | { |
46c06a30 | 620 | u32 reg = PIPESTAT(pipe); |
755e9019 | 621 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 622 | |
b79480ba DV |
623 | assert_spin_locked(&dev_priv->irq_lock); |
624 | ||
04feced9 VS |
625 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
626 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
627 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
628 | pipe_name(pipe), enable_mask, status_mask)) | |
46c06a30 VS |
629 | return; |
630 | ||
755e9019 ID |
631 | if ((pipestat & enable_mask) == 0) |
632 | return; | |
633 | ||
91d181dd ID |
634 | dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; |
635 | ||
755e9019 | 636 | pipestat &= ~enable_mask; |
46c06a30 VS |
637 | I915_WRITE(reg, pipestat); |
638 | POSTING_READ(reg); | |
7c463586 KP |
639 | } |
640 | ||
10c59c51 ID |
641 | static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask) |
642 | { | |
643 | u32 enable_mask = status_mask << 16; | |
644 | ||
645 | /* | |
724a6905 VS |
646 | * On pipe A we don't support the PSR interrupt yet, |
647 | * on pipe B and C the same bit MBZ. | |
10c59c51 ID |
648 | */ |
649 | if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV)) | |
650 | return 0; | |
724a6905 VS |
651 | /* |
652 | * On pipe B and C we don't support the PSR interrupt yet, on pipe | |
653 | * A the same bit is for perf counters which we don't use either. | |
654 | */ | |
655 | if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV)) | |
656 | return 0; | |
10c59c51 ID |
657 | |
658 | enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | | |
659 | SPRITE0_FLIP_DONE_INT_EN_VLV | | |
660 | SPRITE1_FLIP_DONE_INT_EN_VLV); | |
661 | if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV) | |
662 | enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV; | |
663 | if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV) | |
664 | enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; | |
665 | ||
666 | return enable_mask; | |
667 | } | |
668 | ||
755e9019 ID |
669 | void |
670 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
671 | u32 status_mask) | |
672 | { | |
673 | u32 enable_mask; | |
674 | ||
10c59c51 ID |
675 | if (IS_VALLEYVIEW(dev_priv->dev)) |
676 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, | |
677 | status_mask); | |
678 | else | |
679 | enable_mask = status_mask << 16; | |
755e9019 ID |
680 | __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
681 | } | |
682 | ||
683 | void | |
684 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
685 | u32 status_mask) | |
686 | { | |
687 | u32 enable_mask; | |
688 | ||
10c59c51 ID |
689 | if (IS_VALLEYVIEW(dev_priv->dev)) |
690 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, | |
691 | status_mask); | |
692 | else | |
693 | enable_mask = status_mask << 16; | |
755e9019 ID |
694 | __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
695 | } | |
696 | ||
01c66889 | 697 | /** |
f49e38dd | 698 | * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion |
01c66889 | 699 | */ |
f49e38dd | 700 | static void i915_enable_asle_pipestat(struct drm_device *dev) |
01c66889 | 701 | { |
2d1013dd | 702 | struct drm_i915_private *dev_priv = dev->dev_private; |
1ec14ad3 CW |
703 | unsigned long irqflags; |
704 | ||
f49e38dd JN |
705 | if (!dev_priv->opregion.asle || !IS_MOBILE(dev)) |
706 | return; | |
707 | ||
1ec14ad3 | 708 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
01c66889 | 709 | |
755e9019 | 710 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); |
f898780b | 711 | if (INTEL_INFO(dev)->gen >= 4) |
3b6c42e8 | 712 | i915_enable_pipestat(dev_priv, PIPE_A, |
755e9019 | 713 | PIPE_LEGACY_BLC_EVENT_STATUS); |
1ec14ad3 CW |
714 | |
715 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
01c66889 ZY |
716 | } |
717 | ||
0a3e67a4 JB |
718 | /** |
719 | * i915_pipe_enabled - check if a pipe is enabled | |
720 | * @dev: DRM device | |
721 | * @pipe: pipe to check | |
722 | * | |
723 | * Reading certain registers when the pipe is disabled can hang the chip. | |
724 | * Use this routine to make sure the PLL is running and the pipe is active | |
725 | * before reading such registers if unsure. | |
726 | */ | |
727 | static int | |
728 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
729 | { | |
2d1013dd | 730 | struct drm_i915_private *dev_priv = dev->dev_private; |
702e7a56 | 731 | |
a01025af DV |
732 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
733 | /* Locking is horribly broken here, but whatever. */ | |
734 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
735 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
71f8ba6b | 736 | |
a01025af DV |
737 | return intel_crtc->active; |
738 | } else { | |
739 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; | |
740 | } | |
0a3e67a4 JB |
741 | } |
742 | ||
4cdb83ec VS |
743 | static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe) |
744 | { | |
745 | /* Gen2 doesn't have a hardware frame counter */ | |
746 | return 0; | |
747 | } | |
748 | ||
42f52ef8 KP |
749 | /* Called from drm generic code, passed a 'crtc', which |
750 | * we use as a pipe index | |
751 | */ | |
f71d4af4 | 752 | static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
0a3e67a4 | 753 | { |
2d1013dd | 754 | struct drm_i915_private *dev_priv = dev->dev_private; |
0a3e67a4 JB |
755 | unsigned long high_frame; |
756 | unsigned long low_frame; | |
391f75e2 | 757 | u32 high1, high2, low, pixel, vbl_start; |
0a3e67a4 JB |
758 | |
759 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 760 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 761 | "pipe %c\n", pipe_name(pipe)); |
0a3e67a4 JB |
762 | return 0; |
763 | } | |
764 | ||
391f75e2 VS |
765 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
766 | struct intel_crtc *intel_crtc = | |
767 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
768 | const struct drm_display_mode *mode = | |
769 | &intel_crtc->config.adjusted_mode; | |
770 | ||
771 | vbl_start = mode->crtc_vblank_start * mode->crtc_htotal; | |
772 | } else { | |
a2d213dd | 773 | enum transcoder cpu_transcoder = (enum transcoder) pipe; |
391f75e2 VS |
774 | u32 htotal; |
775 | ||
776 | htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1; | |
777 | vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1; | |
778 | ||
779 | vbl_start *= htotal; | |
780 | } | |
781 | ||
9db4a9c7 JB |
782 | high_frame = PIPEFRAME(pipe); |
783 | low_frame = PIPEFRAMEPIXEL(pipe); | |
5eddb70b | 784 | |
0a3e67a4 JB |
785 | /* |
786 | * High & low register fields aren't synchronized, so make sure | |
787 | * we get a low value that's stable across two reads of the high | |
788 | * register. | |
789 | */ | |
790 | do { | |
5eddb70b | 791 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
391f75e2 | 792 | low = I915_READ(low_frame); |
5eddb70b | 793 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
0a3e67a4 JB |
794 | } while (high1 != high2); |
795 | ||
5eddb70b | 796 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
391f75e2 | 797 | pixel = low & PIPE_PIXEL_MASK; |
5eddb70b | 798 | low >>= PIPE_FRAME_LOW_SHIFT; |
391f75e2 VS |
799 | |
800 | /* | |
801 | * The frame counter increments at beginning of active. | |
802 | * Cook up a vblank counter by also checking the pixel | |
803 | * counter against vblank start. | |
804 | */ | |
edc08d0a | 805 | return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; |
0a3e67a4 JB |
806 | } |
807 | ||
f71d4af4 | 808 | static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
9880b7a5 | 809 | { |
2d1013dd | 810 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 811 | int reg = PIPE_FRMCOUNT_GM45(pipe); |
9880b7a5 JB |
812 | |
813 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 814 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 815 | "pipe %c\n", pipe_name(pipe)); |
9880b7a5 JB |
816 | return 0; |
817 | } | |
818 | ||
819 | return I915_READ(reg); | |
820 | } | |
821 | ||
ad3543ed MK |
822 | /* raw reads, only for fast reads of display block, no need for forcewake etc. */ |
823 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) | |
ad3543ed | 824 | |
a225f079 VS |
825 | static int __intel_get_crtc_scanline(struct intel_crtc *crtc) |
826 | { | |
827 | struct drm_device *dev = crtc->base.dev; | |
828 | struct drm_i915_private *dev_priv = dev->dev_private; | |
829 | const struct drm_display_mode *mode = &crtc->config.adjusted_mode; | |
830 | enum pipe pipe = crtc->pipe; | |
831 | int vtotal = mode->crtc_vtotal; | |
832 | int position; | |
833 | ||
834 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
835 | vtotal /= 2; | |
836 | ||
837 | if (IS_GEN2(dev)) | |
838 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; | |
839 | else | |
840 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; | |
841 | ||
842 | /* | |
843 | * Scanline counter increments at leading edge of hsync, and | |
844 | * it starts counting from vtotal-1 on the first active line. | |
845 | * That means the scanline counter value is always one less | |
846 | * than what we would expect. Ie. just after start of vblank, | |
847 | * which also occurs at start of hsync (on the last active line), | |
848 | * the scanline counter will read vblank_start-1. | |
849 | */ | |
850 | return (position + 1) % vtotal; | |
851 | } | |
852 | ||
f71d4af4 | 853 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
abca9e45 VS |
854 | unsigned int flags, int *vpos, int *hpos, |
855 | ktime_t *stime, ktime_t *etime) | |
0af7e4df | 856 | { |
c2baf4b7 VS |
857 | struct drm_i915_private *dev_priv = dev->dev_private; |
858 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
859 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
860 | const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; | |
3aa18df8 | 861 | int position; |
78e8fc6b | 862 | int vbl_start, vbl_end, hsync_start, htotal, vtotal; |
0af7e4df MK |
863 | bool in_vbl = true; |
864 | int ret = 0; | |
ad3543ed | 865 | unsigned long irqflags; |
0af7e4df | 866 | |
c2baf4b7 | 867 | if (!intel_crtc->active) { |
0af7e4df | 868 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
9db4a9c7 | 869 | "pipe %c\n", pipe_name(pipe)); |
0af7e4df MK |
870 | return 0; |
871 | } | |
872 | ||
c2baf4b7 | 873 | htotal = mode->crtc_htotal; |
78e8fc6b | 874 | hsync_start = mode->crtc_hsync_start; |
c2baf4b7 VS |
875 | vtotal = mode->crtc_vtotal; |
876 | vbl_start = mode->crtc_vblank_start; | |
877 | vbl_end = mode->crtc_vblank_end; | |
0af7e4df | 878 | |
d31faf65 VS |
879 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
880 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
881 | vbl_end /= 2; | |
882 | vtotal /= 2; | |
883 | } | |
884 | ||
c2baf4b7 VS |
885 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; |
886 | ||
ad3543ed MK |
887 | /* |
888 | * Lock uncore.lock, as we will do multiple timing critical raw | |
889 | * register reads, potentially with preemption disabled, so the | |
890 | * following code must not block on uncore.lock. | |
891 | */ | |
892 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
78e8fc6b | 893 | |
ad3543ed MK |
894 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ |
895 | ||
896 | /* Get optional system timestamp before query. */ | |
897 | if (stime) | |
898 | *stime = ktime_get(); | |
899 | ||
7c06b08a | 900 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
0af7e4df MK |
901 | /* No obvious pixelcount register. Only query vertical |
902 | * scanout position from Display scan line register. | |
903 | */ | |
a225f079 | 904 | position = __intel_get_crtc_scanline(intel_crtc); |
0af7e4df MK |
905 | } else { |
906 | /* Have access to pixelcount since start of frame. | |
907 | * We can split this into vertical and horizontal | |
908 | * scanout position. | |
909 | */ | |
ad3543ed | 910 | position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; |
0af7e4df | 911 | |
3aa18df8 VS |
912 | /* convert to pixel counts */ |
913 | vbl_start *= htotal; | |
914 | vbl_end *= htotal; | |
915 | vtotal *= htotal; | |
78e8fc6b | 916 | |
7e78f1cb VS |
917 | /* |
918 | * In interlaced modes, the pixel counter counts all pixels, | |
919 | * so one field will have htotal more pixels. In order to avoid | |
920 | * the reported position from jumping backwards when the pixel | |
921 | * counter is beyond the length of the shorter field, just | |
922 | * clamp the position the length of the shorter field. This | |
923 | * matches how the scanline counter based position works since | |
924 | * the scanline counter doesn't count the two half lines. | |
925 | */ | |
926 | if (position >= vtotal) | |
927 | position = vtotal - 1; | |
928 | ||
78e8fc6b VS |
929 | /* |
930 | * Start of vblank interrupt is triggered at start of hsync, | |
931 | * just prior to the first active line of vblank. However we | |
932 | * consider lines to start at the leading edge of horizontal | |
933 | * active. So, should we get here before we've crossed into | |
934 | * the horizontal active of the first line in vblank, we would | |
935 | * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that, | |
936 | * always add htotal-hsync_start to the current pixel position. | |
937 | */ | |
938 | position = (position + htotal - hsync_start) % vtotal; | |
0af7e4df MK |
939 | } |
940 | ||
ad3543ed MK |
941 | /* Get optional system timestamp after query. */ |
942 | if (etime) | |
943 | *etime = ktime_get(); | |
944 | ||
945 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ | |
946 | ||
947 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
948 | ||
3aa18df8 VS |
949 | in_vbl = position >= vbl_start && position < vbl_end; |
950 | ||
951 | /* | |
952 | * While in vblank, position will be negative | |
953 | * counting up towards 0 at vbl_end. And outside | |
954 | * vblank, position will be positive counting | |
955 | * up since vbl_end. | |
956 | */ | |
957 | if (position >= vbl_start) | |
958 | position -= vbl_end; | |
959 | else | |
960 | position += vtotal - vbl_end; | |
0af7e4df | 961 | |
7c06b08a | 962 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
3aa18df8 VS |
963 | *vpos = position; |
964 | *hpos = 0; | |
965 | } else { | |
966 | *vpos = position / htotal; | |
967 | *hpos = position - (*vpos * htotal); | |
968 | } | |
0af7e4df | 969 | |
0af7e4df MK |
970 | /* In vblank? */ |
971 | if (in_vbl) | |
972 | ret |= DRM_SCANOUTPOS_INVBL; | |
973 | ||
974 | return ret; | |
975 | } | |
976 | ||
a225f079 VS |
977 | int intel_get_crtc_scanline(struct intel_crtc *crtc) |
978 | { | |
979 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
980 | unsigned long irqflags; | |
981 | int position; | |
982 | ||
983 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
984 | position = __intel_get_crtc_scanline(crtc); | |
985 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
986 | ||
987 | return position; | |
988 | } | |
989 | ||
f71d4af4 | 990 | static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
0af7e4df MK |
991 | int *max_error, |
992 | struct timeval *vblank_time, | |
993 | unsigned flags) | |
994 | { | |
4041b853 | 995 | struct drm_crtc *crtc; |
0af7e4df | 996 | |
7eb552ae | 997 | if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { |
4041b853 | 998 | DRM_ERROR("Invalid crtc %d\n", pipe); |
0af7e4df MK |
999 | return -EINVAL; |
1000 | } | |
1001 | ||
1002 | /* Get drm_crtc to timestamp: */ | |
4041b853 CW |
1003 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
1004 | if (crtc == NULL) { | |
1005 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
1006 | return -EINVAL; | |
1007 | } | |
1008 | ||
1009 | if (!crtc->enabled) { | |
1010 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); | |
1011 | return -EBUSY; | |
1012 | } | |
0af7e4df MK |
1013 | |
1014 | /* Helper routine in DRM core does all the work: */ | |
4041b853 CW |
1015 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
1016 | vblank_time, flags, | |
7da903ef VS |
1017 | crtc, |
1018 | &to_intel_crtc(crtc)->config.adjusted_mode); | |
0af7e4df MK |
1019 | } |
1020 | ||
67c347ff JN |
1021 | static bool intel_hpd_irq_event(struct drm_device *dev, |
1022 | struct drm_connector *connector) | |
321a1b30 EE |
1023 | { |
1024 | enum drm_connector_status old_status; | |
1025 | ||
1026 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); | |
1027 | old_status = connector->status; | |
1028 | ||
1029 | connector->status = connector->funcs->detect(connector, false); | |
67c347ff JN |
1030 | if (old_status == connector->status) |
1031 | return false; | |
1032 | ||
1033 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n", | |
321a1b30 EE |
1034 | connector->base.id, |
1035 | drm_get_connector_name(connector), | |
67c347ff JN |
1036 | drm_get_connector_status_name(old_status), |
1037 | drm_get_connector_status_name(connector->status)); | |
1038 | ||
1039 | return true; | |
321a1b30 EE |
1040 | } |
1041 | ||
5ca58282 JB |
1042 | /* |
1043 | * Handle hotplug events outside the interrupt handler proper. | |
1044 | */ | |
ac4c16c5 EE |
1045 | #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000) |
1046 | ||
5ca58282 JB |
1047 | static void i915_hotplug_work_func(struct work_struct *work) |
1048 | { | |
2d1013dd JN |
1049 | struct drm_i915_private *dev_priv = |
1050 | container_of(work, struct drm_i915_private, hotplug_work); | |
5ca58282 | 1051 | struct drm_device *dev = dev_priv->dev; |
c31c4ba3 | 1052 | struct drm_mode_config *mode_config = &dev->mode_config; |
cd569aed EE |
1053 | struct intel_connector *intel_connector; |
1054 | struct intel_encoder *intel_encoder; | |
1055 | struct drm_connector *connector; | |
1056 | unsigned long irqflags; | |
1057 | bool hpd_disabled = false; | |
321a1b30 | 1058 | bool changed = false; |
142e2398 | 1059 | u32 hpd_event_bits; |
4ef69c7a | 1060 | |
52d7eced DV |
1061 | /* HPD irq before everything is fully set up. */ |
1062 | if (!dev_priv->enable_hotplug_processing) | |
1063 | return; | |
1064 | ||
a65e34c7 | 1065 | mutex_lock(&mode_config->mutex); |
e67189ab JB |
1066 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); |
1067 | ||
cd569aed | 1068 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
142e2398 EE |
1069 | |
1070 | hpd_event_bits = dev_priv->hpd_event_bits; | |
1071 | dev_priv->hpd_event_bits = 0; | |
cd569aed EE |
1072 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
1073 | intel_connector = to_intel_connector(connector); | |
1074 | intel_encoder = intel_connector->encoder; | |
1075 | if (intel_encoder->hpd_pin > HPD_NONE && | |
1076 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED && | |
1077 | connector->polled == DRM_CONNECTOR_POLL_HPD) { | |
1078 | DRM_INFO("HPD interrupt storm detected on connector %s: " | |
1079 | "switching from hotplug detection to polling\n", | |
1080 | drm_get_connector_name(connector)); | |
1081 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED; | |
1082 | connector->polled = DRM_CONNECTOR_POLL_CONNECT | |
1083 | | DRM_CONNECTOR_POLL_DISCONNECT; | |
1084 | hpd_disabled = true; | |
1085 | } | |
142e2398 EE |
1086 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { |
1087 | DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n", | |
1088 | drm_get_connector_name(connector), intel_encoder->hpd_pin); | |
1089 | } | |
cd569aed EE |
1090 | } |
1091 | /* if there were no outputs to poll, poll was disabled, | |
1092 | * therefore make sure it's enabled when disabling HPD on | |
1093 | * some connectors */ | |
ac4c16c5 | 1094 | if (hpd_disabled) { |
cd569aed | 1095 | drm_kms_helper_poll_enable(dev); |
ac4c16c5 EE |
1096 | mod_timer(&dev_priv->hotplug_reenable_timer, |
1097 | jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY)); | |
1098 | } | |
cd569aed EE |
1099 | |
1100 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
1101 | ||
321a1b30 EE |
1102 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
1103 | intel_connector = to_intel_connector(connector); | |
1104 | intel_encoder = intel_connector->encoder; | |
1105 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { | |
1106 | if (intel_encoder->hot_plug) | |
1107 | intel_encoder->hot_plug(intel_encoder); | |
1108 | if (intel_hpd_irq_event(dev, connector)) | |
1109 | changed = true; | |
1110 | } | |
1111 | } | |
40ee3381 KP |
1112 | mutex_unlock(&mode_config->mutex); |
1113 | ||
321a1b30 EE |
1114 | if (changed) |
1115 | drm_kms_helper_hotplug_event(dev); | |
5ca58282 JB |
1116 | } |
1117 | ||
3ca1cced VS |
1118 | static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv) |
1119 | { | |
1120 | del_timer_sync(&dev_priv->hotplug_reenable_timer); | |
1121 | } | |
1122 | ||
d0ecd7e2 | 1123 | static void ironlake_rps_change_irq_handler(struct drm_device *dev) |
f97108d1 | 1124 | { |
2d1013dd | 1125 | struct drm_i915_private *dev_priv = dev->dev_private; |
b5b72e89 | 1126 | u32 busy_up, busy_down, max_avg, min_avg; |
9270388e | 1127 | u8 new_delay; |
9270388e | 1128 | |
d0ecd7e2 | 1129 | spin_lock(&mchdev_lock); |
f97108d1 | 1130 | |
73edd18f DV |
1131 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
1132 | ||
20e4d407 | 1133 | new_delay = dev_priv->ips.cur_delay; |
9270388e | 1134 | |
7648fa99 | 1135 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
1136 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
1137 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
1138 | max_avg = I915_READ(RCBMAXAVG); |
1139 | min_avg = I915_READ(RCBMINAVG); | |
1140 | ||
1141 | /* Handle RCS change request from hw */ | |
b5b72e89 | 1142 | if (busy_up > max_avg) { |
20e4d407 DV |
1143 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
1144 | new_delay = dev_priv->ips.cur_delay - 1; | |
1145 | if (new_delay < dev_priv->ips.max_delay) | |
1146 | new_delay = dev_priv->ips.max_delay; | |
b5b72e89 | 1147 | } else if (busy_down < min_avg) { |
20e4d407 DV |
1148 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
1149 | new_delay = dev_priv->ips.cur_delay + 1; | |
1150 | if (new_delay > dev_priv->ips.min_delay) | |
1151 | new_delay = dev_priv->ips.min_delay; | |
f97108d1 JB |
1152 | } |
1153 | ||
7648fa99 | 1154 | if (ironlake_set_drps(dev, new_delay)) |
20e4d407 | 1155 | dev_priv->ips.cur_delay = new_delay; |
f97108d1 | 1156 | |
d0ecd7e2 | 1157 | spin_unlock(&mchdev_lock); |
9270388e | 1158 | |
f97108d1 JB |
1159 | return; |
1160 | } | |
1161 | ||
549f7365 CW |
1162 | static void notify_ring(struct drm_device *dev, |
1163 | struct intel_ring_buffer *ring) | |
1164 | { | |
475553de CW |
1165 | if (ring->obj == NULL) |
1166 | return; | |
1167 | ||
814e9b57 | 1168 | trace_i915_gem_request_complete(ring); |
9862e600 | 1169 | |
549f7365 | 1170 | wake_up_all(&ring->irq_queue); |
10cd45b6 | 1171 | i915_queue_hangcheck(dev); |
549f7365 CW |
1172 | } |
1173 | ||
4912d041 | 1174 | static void gen6_pm_rps_work(struct work_struct *work) |
3b8d8d91 | 1175 | { |
2d1013dd JN |
1176 | struct drm_i915_private *dev_priv = |
1177 | container_of(work, struct drm_i915_private, rps.work); | |
edbfdb45 | 1178 | u32 pm_iir; |
dd75fdc8 | 1179 | int new_delay, adj; |
4912d041 | 1180 | |
59cdb63d | 1181 | spin_lock_irq(&dev_priv->irq_lock); |
c6a828d3 DV |
1182 | pm_iir = dev_priv->rps.pm_iir; |
1183 | dev_priv->rps.pm_iir = 0; | |
0961021a BW |
1184 | if (IS_BROADWELL(dev_priv->dev)) |
1185 | bdw_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); | |
1186 | else { | |
1187 | /* Make sure not to corrupt PMIMR state used by ringbuffer */ | |
1188 | snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); | |
1189 | } | |
59cdb63d | 1190 | spin_unlock_irq(&dev_priv->irq_lock); |
3b8d8d91 | 1191 | |
60611c13 | 1192 | /* Make sure we didn't queue anything we're not going to process. */ |
a6706b45 | 1193 | WARN_ON(pm_iir & ~dev_priv->pm_rps_events); |
60611c13 | 1194 | |
a6706b45 | 1195 | if ((pm_iir & dev_priv->pm_rps_events) == 0) |
3b8d8d91 JB |
1196 | return; |
1197 | ||
4fc688ce | 1198 | mutex_lock(&dev_priv->rps.hw_lock); |
7b9e0ae6 | 1199 | |
dd75fdc8 | 1200 | adj = dev_priv->rps.last_adj; |
7425034a | 1201 | if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { |
dd75fdc8 CW |
1202 | if (adj > 0) |
1203 | adj *= 2; | |
1204 | else | |
1205 | adj = 1; | |
b39fb297 | 1206 | new_delay = dev_priv->rps.cur_freq + adj; |
7425034a VS |
1207 | |
1208 | /* | |
1209 | * For better performance, jump directly | |
1210 | * to RPe if we're below it. | |
1211 | */ | |
b39fb297 BW |
1212 | if (new_delay < dev_priv->rps.efficient_freq) |
1213 | new_delay = dev_priv->rps.efficient_freq; | |
dd75fdc8 | 1214 | } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { |
b39fb297 BW |
1215 | if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq) |
1216 | new_delay = dev_priv->rps.efficient_freq; | |
dd75fdc8 | 1217 | else |
b39fb297 | 1218 | new_delay = dev_priv->rps.min_freq_softlimit; |
dd75fdc8 CW |
1219 | adj = 0; |
1220 | } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { | |
1221 | if (adj < 0) | |
1222 | adj *= 2; | |
1223 | else | |
1224 | adj = -1; | |
b39fb297 | 1225 | new_delay = dev_priv->rps.cur_freq + adj; |
dd75fdc8 | 1226 | } else { /* unknown event */ |
b39fb297 | 1227 | new_delay = dev_priv->rps.cur_freq; |
dd75fdc8 | 1228 | } |
3b8d8d91 | 1229 | |
79249636 BW |
1230 | /* sysfs frequency interfaces may have snuck in while servicing the |
1231 | * interrupt | |
1232 | */ | |
1272e7b8 | 1233 | new_delay = clamp_t(int, new_delay, |
b39fb297 BW |
1234 | dev_priv->rps.min_freq_softlimit, |
1235 | dev_priv->rps.max_freq_softlimit); | |
27544369 | 1236 | |
b39fb297 | 1237 | dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq; |
dd75fdc8 CW |
1238 | |
1239 | if (IS_VALLEYVIEW(dev_priv->dev)) | |
1240 | valleyview_set_rps(dev_priv->dev, new_delay); | |
1241 | else | |
1242 | gen6_set_rps(dev_priv->dev, new_delay); | |
3b8d8d91 | 1243 | |
4fc688ce | 1244 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 JB |
1245 | } |
1246 | ||
e3689190 BW |
1247 | |
1248 | /** | |
1249 | * ivybridge_parity_work - Workqueue called when a parity error interrupt | |
1250 | * occurred. | |
1251 | * @work: workqueue struct | |
1252 | * | |
1253 | * Doesn't actually do anything except notify userspace. As a consequence of | |
1254 | * this event, userspace should try to remap the bad rows since statistically | |
1255 | * it is likely the same row is more likely to go bad again. | |
1256 | */ | |
1257 | static void ivybridge_parity_work(struct work_struct *work) | |
1258 | { | |
2d1013dd JN |
1259 | struct drm_i915_private *dev_priv = |
1260 | container_of(work, struct drm_i915_private, l3_parity.error_work); | |
e3689190 | 1261 | u32 error_status, row, bank, subbank; |
35a85ac6 | 1262 | char *parity_event[6]; |
e3689190 BW |
1263 | uint32_t misccpctl; |
1264 | unsigned long flags; | |
35a85ac6 | 1265 | uint8_t slice = 0; |
e3689190 BW |
1266 | |
1267 | /* We must turn off DOP level clock gating to access the L3 registers. | |
1268 | * In order to prevent a get/put style interface, acquire struct mutex | |
1269 | * any time we access those registers. | |
1270 | */ | |
1271 | mutex_lock(&dev_priv->dev->struct_mutex); | |
1272 | ||
35a85ac6 BW |
1273 | /* If we've screwed up tracking, just let the interrupt fire again */ |
1274 | if (WARN_ON(!dev_priv->l3_parity.which_slice)) | |
1275 | goto out; | |
1276 | ||
e3689190 BW |
1277 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
1278 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
1279 | POSTING_READ(GEN7_MISCCPCTL); | |
1280 | ||
35a85ac6 BW |
1281 | while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { |
1282 | u32 reg; | |
e3689190 | 1283 | |
35a85ac6 BW |
1284 | slice--; |
1285 | if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev))) | |
1286 | break; | |
e3689190 | 1287 | |
35a85ac6 | 1288 | dev_priv->l3_parity.which_slice &= ~(1<<slice); |
e3689190 | 1289 | |
35a85ac6 | 1290 | reg = GEN7_L3CDERRST1 + (slice * 0x200); |
e3689190 | 1291 | |
35a85ac6 BW |
1292 | error_status = I915_READ(reg); |
1293 | row = GEN7_PARITY_ERROR_ROW(error_status); | |
1294 | bank = GEN7_PARITY_ERROR_BANK(error_status); | |
1295 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); | |
1296 | ||
1297 | I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); | |
1298 | POSTING_READ(reg); | |
1299 | ||
1300 | parity_event[0] = I915_L3_PARITY_UEVENT "=1"; | |
1301 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); | |
1302 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); | |
1303 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); | |
1304 | parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); | |
1305 | parity_event[5] = NULL; | |
1306 | ||
5bdebb18 | 1307 | kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj, |
35a85ac6 | 1308 | KOBJ_CHANGE, parity_event); |
e3689190 | 1309 | |
35a85ac6 BW |
1310 | DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", |
1311 | slice, row, bank, subbank); | |
e3689190 | 1312 | |
35a85ac6 BW |
1313 | kfree(parity_event[4]); |
1314 | kfree(parity_event[3]); | |
1315 | kfree(parity_event[2]); | |
1316 | kfree(parity_event[1]); | |
1317 | } | |
e3689190 | 1318 | |
35a85ac6 | 1319 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
e3689190 | 1320 | |
35a85ac6 BW |
1321 | out: |
1322 | WARN_ON(dev_priv->l3_parity.which_slice); | |
1323 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1324 | ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev)); | |
1325 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1326 | ||
1327 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
e3689190 BW |
1328 | } |
1329 | ||
35a85ac6 | 1330 | static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir) |
e3689190 | 1331 | { |
2d1013dd | 1332 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3689190 | 1333 | |
040d2baa | 1334 | if (!HAS_L3_DPF(dev)) |
e3689190 BW |
1335 | return; |
1336 | ||
d0ecd7e2 | 1337 | spin_lock(&dev_priv->irq_lock); |
35a85ac6 | 1338 | ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev)); |
d0ecd7e2 | 1339 | spin_unlock(&dev_priv->irq_lock); |
e3689190 | 1340 | |
35a85ac6 BW |
1341 | iir &= GT_PARITY_ERROR(dev); |
1342 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) | |
1343 | dev_priv->l3_parity.which_slice |= 1 << 1; | |
1344 | ||
1345 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) | |
1346 | dev_priv->l3_parity.which_slice |= 1 << 0; | |
1347 | ||
a4da4fa4 | 1348 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
e3689190 BW |
1349 | } |
1350 | ||
f1af8fc1 PZ |
1351 | static void ilk_gt_irq_handler(struct drm_device *dev, |
1352 | struct drm_i915_private *dev_priv, | |
1353 | u32 gt_iir) | |
1354 | { | |
1355 | if (gt_iir & | |
1356 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
1357 | notify_ring(dev, &dev_priv->ring[RCS]); | |
1358 | if (gt_iir & ILK_BSD_USER_INTERRUPT) | |
1359 | notify_ring(dev, &dev_priv->ring[VCS]); | |
1360 | } | |
1361 | ||
e7b4c6b1 DV |
1362 | static void snb_gt_irq_handler(struct drm_device *dev, |
1363 | struct drm_i915_private *dev_priv, | |
1364 | u32 gt_iir) | |
1365 | { | |
1366 | ||
cc609d5d BW |
1367 | if (gt_iir & |
1368 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
e7b4c6b1 | 1369 | notify_ring(dev, &dev_priv->ring[RCS]); |
cc609d5d | 1370 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
e7b4c6b1 | 1371 | notify_ring(dev, &dev_priv->ring[VCS]); |
cc609d5d | 1372 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
e7b4c6b1 DV |
1373 | notify_ring(dev, &dev_priv->ring[BCS]); |
1374 | ||
cc609d5d BW |
1375 | if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | |
1376 | GT_BSD_CS_ERROR_INTERRUPT | | |
1377 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) { | |
58174462 MK |
1378 | i915_handle_error(dev, false, "GT error interrupt 0x%08x", |
1379 | gt_iir); | |
e7b4c6b1 | 1380 | } |
e3689190 | 1381 | |
35a85ac6 BW |
1382 | if (gt_iir & GT_PARITY_ERROR(dev)) |
1383 | ivybridge_parity_error_irq_handler(dev, gt_iir); | |
e7b4c6b1 DV |
1384 | } |
1385 | ||
0961021a BW |
1386 | static void gen8_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) |
1387 | { | |
1388 | if ((pm_iir & dev_priv->pm_rps_events) == 0) | |
1389 | return; | |
1390 | ||
1391 | spin_lock(&dev_priv->irq_lock); | |
1392 | dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; | |
1393 | bdw_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); | |
1394 | spin_unlock(&dev_priv->irq_lock); | |
1395 | ||
1396 | queue_work(dev_priv->wq, &dev_priv->rps.work); | |
1397 | } | |
1398 | ||
abd58f01 BW |
1399 | static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev, |
1400 | struct drm_i915_private *dev_priv, | |
1401 | u32 master_ctl) | |
1402 | { | |
1403 | u32 rcs, bcs, vcs; | |
1404 | uint32_t tmp = 0; | |
1405 | irqreturn_t ret = IRQ_NONE; | |
1406 | ||
1407 | if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { | |
1408 | tmp = I915_READ(GEN8_GT_IIR(0)); | |
1409 | if (tmp) { | |
1410 | ret = IRQ_HANDLED; | |
1411 | rcs = tmp >> GEN8_RCS_IRQ_SHIFT; | |
1412 | bcs = tmp >> GEN8_BCS_IRQ_SHIFT; | |
1413 | if (rcs & GT_RENDER_USER_INTERRUPT) | |
1414 | notify_ring(dev, &dev_priv->ring[RCS]); | |
1415 | if (bcs & GT_RENDER_USER_INTERRUPT) | |
1416 | notify_ring(dev, &dev_priv->ring[BCS]); | |
1417 | I915_WRITE(GEN8_GT_IIR(0), tmp); | |
1418 | } else | |
1419 | DRM_ERROR("The master control interrupt lied (GT0)!\n"); | |
1420 | } | |
1421 | ||
85f9b5f9 | 1422 | if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) { |
abd58f01 BW |
1423 | tmp = I915_READ(GEN8_GT_IIR(1)); |
1424 | if (tmp) { | |
1425 | ret = IRQ_HANDLED; | |
1426 | vcs = tmp >> GEN8_VCS1_IRQ_SHIFT; | |
1427 | if (vcs & GT_RENDER_USER_INTERRUPT) | |
1428 | notify_ring(dev, &dev_priv->ring[VCS]); | |
85f9b5f9 ZY |
1429 | vcs = tmp >> GEN8_VCS2_IRQ_SHIFT; |
1430 | if (vcs & GT_RENDER_USER_INTERRUPT) | |
1431 | notify_ring(dev, &dev_priv->ring[VCS2]); | |
abd58f01 BW |
1432 | I915_WRITE(GEN8_GT_IIR(1), tmp); |
1433 | } else | |
1434 | DRM_ERROR("The master control interrupt lied (GT1)!\n"); | |
1435 | } | |
1436 | ||
0961021a BW |
1437 | if (master_ctl & GEN8_GT_PM_IRQ) { |
1438 | tmp = I915_READ(GEN8_GT_IIR(2)); | |
1439 | if (tmp & dev_priv->pm_rps_events) { | |
1440 | ret = IRQ_HANDLED; | |
1441 | gen8_rps_irq_handler(dev_priv, tmp); | |
1442 | I915_WRITE(GEN8_GT_IIR(2), | |
1443 | tmp & dev_priv->pm_rps_events); | |
1444 | } else | |
1445 | DRM_ERROR("The master control interrupt lied (PM)!\n"); | |
1446 | } | |
1447 | ||
abd58f01 BW |
1448 | if (master_ctl & GEN8_GT_VECS_IRQ) { |
1449 | tmp = I915_READ(GEN8_GT_IIR(3)); | |
1450 | if (tmp) { | |
1451 | ret = IRQ_HANDLED; | |
1452 | vcs = tmp >> GEN8_VECS_IRQ_SHIFT; | |
1453 | if (vcs & GT_RENDER_USER_INTERRUPT) | |
1454 | notify_ring(dev, &dev_priv->ring[VECS]); | |
1455 | I915_WRITE(GEN8_GT_IIR(3), tmp); | |
1456 | } else | |
1457 | DRM_ERROR("The master control interrupt lied (GT3)!\n"); | |
1458 | } | |
1459 | ||
1460 | return ret; | |
1461 | } | |
1462 | ||
b543fb04 EE |
1463 | #define HPD_STORM_DETECT_PERIOD 1000 |
1464 | #define HPD_STORM_THRESHOLD 5 | |
1465 | ||
10a504de | 1466 | static inline void intel_hpd_irq_handler(struct drm_device *dev, |
22062dba DV |
1467 | u32 hotplug_trigger, |
1468 | const u32 *hpd) | |
b543fb04 | 1469 | { |
2d1013dd | 1470 | struct drm_i915_private *dev_priv = dev->dev_private; |
b543fb04 | 1471 | int i; |
10a504de | 1472 | bool storm_detected = false; |
b543fb04 | 1473 | |
91d131d2 DV |
1474 | if (!hotplug_trigger) |
1475 | return; | |
1476 | ||
cc9bd499 ID |
1477 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
1478 | hotplug_trigger); | |
1479 | ||
b5ea2d56 | 1480 | spin_lock(&dev_priv->irq_lock); |
b543fb04 | 1481 | for (i = 1; i < HPD_NUM_PINS; i++) { |
821450c6 | 1482 | |
3ff04a16 DV |
1483 | if (hpd[i] & hotplug_trigger && |
1484 | dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) { | |
1485 | /* | |
1486 | * On GMCH platforms the interrupt mask bits only | |
1487 | * prevent irq generation, not the setting of the | |
1488 | * hotplug bits itself. So only WARN about unexpected | |
1489 | * interrupts on saner platforms. | |
1490 | */ | |
1491 | WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev), | |
1492 | "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n", | |
1493 | hotplug_trigger, i, hpd[i]); | |
1494 | ||
1495 | continue; | |
1496 | } | |
b8f102e8 | 1497 | |
b543fb04 EE |
1498 | if (!(hpd[i] & hotplug_trigger) || |
1499 | dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED) | |
1500 | continue; | |
1501 | ||
bc5ead8c | 1502 | dev_priv->hpd_event_bits |= (1 << i); |
b543fb04 EE |
1503 | if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies, |
1504 | dev_priv->hpd_stats[i].hpd_last_jiffies | |
1505 | + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) { | |
1506 | dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies; | |
1507 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
b8f102e8 | 1508 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i); |
b543fb04 EE |
1509 | } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) { |
1510 | dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED; | |
142e2398 | 1511 | dev_priv->hpd_event_bits &= ~(1 << i); |
b543fb04 | 1512 | DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i); |
10a504de | 1513 | storm_detected = true; |
b543fb04 EE |
1514 | } else { |
1515 | dev_priv->hpd_stats[i].hpd_cnt++; | |
b8f102e8 EE |
1516 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i, |
1517 | dev_priv->hpd_stats[i].hpd_cnt); | |
b543fb04 EE |
1518 | } |
1519 | } | |
1520 | ||
10a504de DV |
1521 | if (storm_detected) |
1522 | dev_priv->display.hpd_irq_setup(dev); | |
b5ea2d56 | 1523 | spin_unlock(&dev_priv->irq_lock); |
5876fa0d | 1524 | |
645416f5 DV |
1525 | /* |
1526 | * Our hotplug handler can grab modeset locks (by calling down into the | |
1527 | * fb helpers). Hence it must not be run on our own dev-priv->wq work | |
1528 | * queue for otherwise the flush_work in the pageflip code will | |
1529 | * deadlock. | |
1530 | */ | |
1531 | schedule_work(&dev_priv->hotplug_work); | |
b543fb04 EE |
1532 | } |
1533 | ||
515ac2bb DV |
1534 | static void gmbus_irq_handler(struct drm_device *dev) |
1535 | { | |
2d1013dd | 1536 | struct drm_i915_private *dev_priv = dev->dev_private; |
28c70f16 | 1537 | |
28c70f16 | 1538 | wake_up_all(&dev_priv->gmbus_wait_queue); |
515ac2bb DV |
1539 | } |
1540 | ||
ce99c256 DV |
1541 | static void dp_aux_irq_handler(struct drm_device *dev) |
1542 | { | |
2d1013dd | 1543 | struct drm_i915_private *dev_priv = dev->dev_private; |
9ee32fea | 1544 | |
9ee32fea | 1545 | wake_up_all(&dev_priv->gmbus_wait_queue); |
ce99c256 DV |
1546 | } |
1547 | ||
8bf1e9f1 | 1548 | #if defined(CONFIG_DEBUG_FS) |
277de95e DV |
1549 | static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, |
1550 | uint32_t crc0, uint32_t crc1, | |
1551 | uint32_t crc2, uint32_t crc3, | |
1552 | uint32_t crc4) | |
8bf1e9f1 SH |
1553 | { |
1554 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1555 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; | |
1556 | struct intel_pipe_crc_entry *entry; | |
ac2300d4 | 1557 | int head, tail; |
b2c88f5b | 1558 | |
d538bbdf DL |
1559 | spin_lock(&pipe_crc->lock); |
1560 | ||
0c912c79 | 1561 | if (!pipe_crc->entries) { |
d538bbdf | 1562 | spin_unlock(&pipe_crc->lock); |
0c912c79 DL |
1563 | DRM_ERROR("spurious interrupt\n"); |
1564 | return; | |
1565 | } | |
1566 | ||
d538bbdf DL |
1567 | head = pipe_crc->head; |
1568 | tail = pipe_crc->tail; | |
b2c88f5b DL |
1569 | |
1570 | if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { | |
d538bbdf | 1571 | spin_unlock(&pipe_crc->lock); |
b2c88f5b DL |
1572 | DRM_ERROR("CRC buffer overflowing\n"); |
1573 | return; | |
1574 | } | |
1575 | ||
1576 | entry = &pipe_crc->entries[head]; | |
8bf1e9f1 | 1577 | |
8bc5e955 | 1578 | entry->frame = dev->driver->get_vblank_counter(dev, pipe); |
eba94eb9 DV |
1579 | entry->crc[0] = crc0; |
1580 | entry->crc[1] = crc1; | |
1581 | entry->crc[2] = crc2; | |
1582 | entry->crc[3] = crc3; | |
1583 | entry->crc[4] = crc4; | |
b2c88f5b DL |
1584 | |
1585 | head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
d538bbdf DL |
1586 | pipe_crc->head = head; |
1587 | ||
1588 | spin_unlock(&pipe_crc->lock); | |
07144428 DL |
1589 | |
1590 | wake_up_interruptible(&pipe_crc->wq); | |
8bf1e9f1 | 1591 | } |
277de95e DV |
1592 | #else |
1593 | static inline void | |
1594 | display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, | |
1595 | uint32_t crc0, uint32_t crc1, | |
1596 | uint32_t crc2, uint32_t crc3, | |
1597 | uint32_t crc4) {} | |
1598 | #endif | |
1599 | ||
eba94eb9 | 1600 | |
277de95e | 1601 | static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5a69b89f DV |
1602 | { |
1603 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1604 | ||
277de95e DV |
1605 | display_pipe_crc_irq_handler(dev, pipe, |
1606 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1607 | 0, 0, 0, 0); | |
5a69b89f DV |
1608 | } |
1609 | ||
277de95e | 1610 | static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
eba94eb9 DV |
1611 | { |
1612 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1613 | ||
277de95e DV |
1614 | display_pipe_crc_irq_handler(dev, pipe, |
1615 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1616 | I915_READ(PIPE_CRC_RES_2_IVB(pipe)), | |
1617 | I915_READ(PIPE_CRC_RES_3_IVB(pipe)), | |
1618 | I915_READ(PIPE_CRC_RES_4_IVB(pipe)), | |
1619 | I915_READ(PIPE_CRC_RES_5_IVB(pipe))); | |
eba94eb9 | 1620 | } |
5b3a856b | 1621 | |
277de95e | 1622 | static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5b3a856b DV |
1623 | { |
1624 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0b5c5ed0 DV |
1625 | uint32_t res1, res2; |
1626 | ||
1627 | if (INTEL_INFO(dev)->gen >= 3) | |
1628 | res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); | |
1629 | else | |
1630 | res1 = 0; | |
1631 | ||
1632 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
1633 | res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); | |
1634 | else | |
1635 | res2 = 0; | |
5b3a856b | 1636 | |
277de95e DV |
1637 | display_pipe_crc_irq_handler(dev, pipe, |
1638 | I915_READ(PIPE_CRC_RES_RED(pipe)), | |
1639 | I915_READ(PIPE_CRC_RES_GREEN(pipe)), | |
1640 | I915_READ(PIPE_CRC_RES_BLUE(pipe)), | |
1641 | res1, res2); | |
5b3a856b | 1642 | } |
8bf1e9f1 | 1643 | |
1403c0d4 PZ |
1644 | /* The RPS events need forcewake, so we add them to a work queue and mask their |
1645 | * IMR bits until the work is done. Other interrupts can be processed without | |
1646 | * the work queue. */ | |
1647 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) | |
baf02a1f | 1648 | { |
a6706b45 | 1649 | if (pm_iir & dev_priv->pm_rps_events) { |
59cdb63d | 1650 | spin_lock(&dev_priv->irq_lock); |
a6706b45 D |
1651 | dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; |
1652 | snb_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); | |
59cdb63d | 1653 | spin_unlock(&dev_priv->irq_lock); |
2adbee62 DV |
1654 | |
1655 | queue_work(dev_priv->wq, &dev_priv->rps.work); | |
baf02a1f | 1656 | } |
baf02a1f | 1657 | |
1403c0d4 PZ |
1658 | if (HAS_VEBOX(dev_priv->dev)) { |
1659 | if (pm_iir & PM_VEBOX_USER_INTERRUPT) | |
1660 | notify_ring(dev_priv->dev, &dev_priv->ring[VECS]); | |
12638c57 | 1661 | |
1403c0d4 | 1662 | if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) { |
58174462 MK |
1663 | i915_handle_error(dev_priv->dev, false, |
1664 | "VEBOX CS error interrupt 0x%08x", | |
1665 | pm_iir); | |
1403c0d4 | 1666 | } |
12638c57 | 1667 | } |
baf02a1f BW |
1668 | } |
1669 | ||
8d7849db VS |
1670 | static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe) |
1671 | { | |
1672 | struct intel_crtc *crtc; | |
1673 | ||
1674 | if (!drm_handle_vblank(dev, pipe)) | |
1675 | return false; | |
1676 | ||
1677 | crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
1678 | wake_up(&crtc->vbl_wait); | |
1679 | ||
1680 | return true; | |
1681 | } | |
1682 | ||
c1874ed7 ID |
1683 | static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir) |
1684 | { | |
1685 | struct drm_i915_private *dev_priv = dev->dev_private; | |
91d181dd | 1686 | u32 pipe_stats[I915_MAX_PIPES] = { }; |
c1874ed7 ID |
1687 | int pipe; |
1688 | ||
58ead0d7 | 1689 | spin_lock(&dev_priv->irq_lock); |
c1874ed7 | 1690 | for_each_pipe(pipe) { |
91d181dd | 1691 | int reg; |
bbb5eebf | 1692 | u32 mask, iir_bit = 0; |
91d181dd | 1693 | |
bbb5eebf DV |
1694 | /* |
1695 | * PIPESTAT bits get signalled even when the interrupt is | |
1696 | * disabled with the mask bits, and some of the status bits do | |
1697 | * not generate interrupts at all (like the underrun bit). Hence | |
1698 | * we need to be careful that we only handle what we want to | |
1699 | * handle. | |
1700 | */ | |
1701 | mask = 0; | |
1702 | if (__cpu_fifo_underrun_reporting_enabled(dev, pipe)) | |
1703 | mask |= PIPE_FIFO_UNDERRUN_STATUS; | |
1704 | ||
1705 | switch (pipe) { | |
1706 | case PIPE_A: | |
1707 | iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; | |
1708 | break; | |
1709 | case PIPE_B: | |
1710 | iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
1711 | break; | |
3278f67f VS |
1712 | case PIPE_C: |
1713 | iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
1714 | break; | |
bbb5eebf DV |
1715 | } |
1716 | if (iir & iir_bit) | |
1717 | mask |= dev_priv->pipestat_irq_mask[pipe]; | |
1718 | ||
1719 | if (!mask) | |
91d181dd ID |
1720 | continue; |
1721 | ||
1722 | reg = PIPESTAT(pipe); | |
bbb5eebf DV |
1723 | mask |= PIPESTAT_INT_ENABLE_MASK; |
1724 | pipe_stats[pipe] = I915_READ(reg) & mask; | |
c1874ed7 ID |
1725 | |
1726 | /* | |
1727 | * Clear the PIPE*STAT regs before the IIR | |
1728 | */ | |
91d181dd ID |
1729 | if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS | |
1730 | PIPESTAT_INT_STATUS_MASK)) | |
c1874ed7 ID |
1731 | I915_WRITE(reg, pipe_stats[pipe]); |
1732 | } | |
58ead0d7 | 1733 | spin_unlock(&dev_priv->irq_lock); |
c1874ed7 ID |
1734 | |
1735 | for_each_pipe(pipe) { | |
1736 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) | |
8d7849db | 1737 | intel_pipe_handle_vblank(dev, pipe); |
c1874ed7 | 1738 | |
579a9b0e | 1739 | if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) { |
c1874ed7 ID |
1740 | intel_prepare_page_flip(dev, pipe); |
1741 | intel_finish_page_flip(dev, pipe); | |
1742 | } | |
1743 | ||
1744 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
1745 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
1746 | ||
1747 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && | |
1748 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
1749 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); | |
1750 | } | |
1751 | ||
1752 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) | |
1753 | gmbus_irq_handler(dev); | |
1754 | } | |
1755 | ||
16c6c56b VS |
1756 | static void i9xx_hpd_irq_handler(struct drm_device *dev) |
1757 | { | |
1758 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1759 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
1760 | ||
1761 | if (IS_G4X(dev)) { | |
1762 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; | |
1763 | ||
1764 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_g4x); | |
1765 | } else { | |
1766 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; | |
1767 | ||
1768 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); | |
1769 | } | |
1770 | ||
1771 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && | |
1772 | hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) | |
1773 | dp_aux_irq_handler(dev); | |
1774 | ||
1775 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
1776 | /* | |
1777 | * Make sure hotplug status is cleared before we clear IIR, or else we | |
1778 | * may miss hotplug events. | |
1779 | */ | |
1780 | POSTING_READ(PORT_HOTPLUG_STAT); | |
1781 | } | |
1782 | ||
ff1f525e | 1783 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
7e231dbe | 1784 | { |
45a83f84 | 1785 | struct drm_device *dev = arg; |
2d1013dd | 1786 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
1787 | u32 iir, gt_iir, pm_iir; |
1788 | irqreturn_t ret = IRQ_NONE; | |
7e231dbe | 1789 | |
7e231dbe JB |
1790 | while (true) { |
1791 | iir = I915_READ(VLV_IIR); | |
1792 | gt_iir = I915_READ(GTIIR); | |
1793 | pm_iir = I915_READ(GEN6_PMIIR); | |
1794 | ||
1795 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) | |
1796 | goto out; | |
1797 | ||
1798 | ret = IRQ_HANDLED; | |
1799 | ||
e7b4c6b1 | 1800 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
7e231dbe | 1801 | |
c1874ed7 | 1802 | valleyview_pipestat_irq_handler(dev, iir); |
31acc7f5 | 1803 | |
7e231dbe | 1804 | /* Consume port. Then clear IIR or we'll miss events */ |
16c6c56b VS |
1805 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
1806 | i9xx_hpd_irq_handler(dev); | |
7e231dbe | 1807 | |
60611c13 | 1808 | if (pm_iir) |
d0ecd7e2 | 1809 | gen6_rps_irq_handler(dev_priv, pm_iir); |
7e231dbe JB |
1810 | |
1811 | I915_WRITE(GTIIR, gt_iir); | |
1812 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
1813 | I915_WRITE(VLV_IIR, iir); | |
1814 | } | |
1815 | ||
1816 | out: | |
1817 | return ret; | |
1818 | } | |
1819 | ||
43f328d7 VS |
1820 | static irqreturn_t cherryview_irq_handler(int irq, void *arg) |
1821 | { | |
45a83f84 | 1822 | struct drm_device *dev = arg; |
43f328d7 VS |
1823 | struct drm_i915_private *dev_priv = dev->dev_private; |
1824 | u32 master_ctl, iir; | |
1825 | irqreturn_t ret = IRQ_NONE; | |
43f328d7 | 1826 | |
8e5fd599 VS |
1827 | for (;;) { |
1828 | master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; | |
1829 | iir = I915_READ(VLV_IIR); | |
43f328d7 | 1830 | |
8e5fd599 VS |
1831 | if (master_ctl == 0 && iir == 0) |
1832 | break; | |
43f328d7 | 1833 | |
8e5fd599 | 1834 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
43f328d7 | 1835 | |
8e5fd599 | 1836 | gen8_gt_irq_handler(dev, dev_priv, master_ctl); |
43f328d7 | 1837 | |
8e5fd599 | 1838 | valleyview_pipestat_irq_handler(dev, iir); |
43f328d7 | 1839 | |
8e5fd599 | 1840 | /* Consume port. Then clear IIR or we'll miss events */ |
3278f67f | 1841 | i9xx_hpd_irq_handler(dev); |
43f328d7 | 1842 | |
8e5fd599 | 1843 | I915_WRITE(VLV_IIR, iir); |
43f328d7 | 1844 | |
8e5fd599 VS |
1845 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); |
1846 | POSTING_READ(GEN8_MASTER_IRQ); | |
43f328d7 | 1847 | |
8e5fd599 VS |
1848 | ret = IRQ_HANDLED; |
1849 | } | |
3278f67f | 1850 | |
43f328d7 VS |
1851 | return ret; |
1852 | } | |
1853 | ||
23e81d69 | 1854 | static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) |
776ad806 | 1855 | { |
2d1013dd | 1856 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 1857 | int pipe; |
b543fb04 | 1858 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; |
776ad806 | 1859 | |
91d131d2 DV |
1860 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx); |
1861 | ||
cfc33bf7 VS |
1862 | if (pch_iir & SDE_AUDIO_POWER_MASK) { |
1863 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> | |
1864 | SDE_AUDIO_POWER_SHIFT); | |
776ad806 | 1865 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
cfc33bf7 VS |
1866 | port_name(port)); |
1867 | } | |
776ad806 | 1868 | |
ce99c256 DV |
1869 | if (pch_iir & SDE_AUX_MASK) |
1870 | dp_aux_irq_handler(dev); | |
1871 | ||
776ad806 | 1872 | if (pch_iir & SDE_GMBUS) |
515ac2bb | 1873 | gmbus_irq_handler(dev); |
776ad806 JB |
1874 | |
1875 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
1876 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
1877 | ||
1878 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
1879 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
1880 | ||
1881 | if (pch_iir & SDE_POISON) | |
1882 | DRM_ERROR("PCH poison interrupt\n"); | |
1883 | ||
9db4a9c7 JB |
1884 | if (pch_iir & SDE_FDI_MASK) |
1885 | for_each_pipe(pipe) | |
1886 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", | |
1887 | pipe_name(pipe), | |
1888 | I915_READ(FDI_RX_IIR(pipe))); | |
776ad806 JB |
1889 | |
1890 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
1891 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
1892 | ||
1893 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
1894 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
1895 | ||
776ad806 | 1896 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
8664281b PZ |
1897 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, |
1898 | false)) | |
fc2c807b | 1899 | DRM_ERROR("PCH transcoder A FIFO underrun\n"); |
8664281b PZ |
1900 | |
1901 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
1902 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, | |
1903 | false)) | |
fc2c807b | 1904 | DRM_ERROR("PCH transcoder B FIFO underrun\n"); |
8664281b PZ |
1905 | } |
1906 | ||
1907 | static void ivb_err_int_handler(struct drm_device *dev) | |
1908 | { | |
1909 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1910 | u32 err_int = I915_READ(GEN7_ERR_INT); | |
5a69b89f | 1911 | enum pipe pipe; |
8664281b | 1912 | |
de032bf4 PZ |
1913 | if (err_int & ERR_INT_POISON) |
1914 | DRM_ERROR("Poison interrupt\n"); | |
1915 | ||
5a69b89f DV |
1916 | for_each_pipe(pipe) { |
1917 | if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) { | |
1918 | if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, | |
1919 | false)) | |
fc2c807b VS |
1920 | DRM_ERROR("Pipe %c FIFO underrun\n", |
1921 | pipe_name(pipe)); | |
5a69b89f | 1922 | } |
8bf1e9f1 | 1923 | |
5a69b89f DV |
1924 | if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { |
1925 | if (IS_IVYBRIDGE(dev)) | |
277de95e | 1926 | ivb_pipe_crc_irq_handler(dev, pipe); |
5a69b89f | 1927 | else |
277de95e | 1928 | hsw_pipe_crc_irq_handler(dev, pipe); |
5a69b89f DV |
1929 | } |
1930 | } | |
8bf1e9f1 | 1931 | |
8664281b PZ |
1932 | I915_WRITE(GEN7_ERR_INT, err_int); |
1933 | } | |
1934 | ||
1935 | static void cpt_serr_int_handler(struct drm_device *dev) | |
1936 | { | |
1937 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1938 | u32 serr_int = I915_READ(SERR_INT); | |
1939 | ||
de032bf4 PZ |
1940 | if (serr_int & SERR_INT_POISON) |
1941 | DRM_ERROR("PCH poison interrupt\n"); | |
1942 | ||
8664281b PZ |
1943 | if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) |
1944 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, | |
1945 | false)) | |
fc2c807b | 1946 | DRM_ERROR("PCH transcoder A FIFO underrun\n"); |
8664281b PZ |
1947 | |
1948 | if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) | |
1949 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, | |
1950 | false)) | |
fc2c807b | 1951 | DRM_ERROR("PCH transcoder B FIFO underrun\n"); |
8664281b PZ |
1952 | |
1953 | if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) | |
1954 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C, | |
1955 | false)) | |
fc2c807b | 1956 | DRM_ERROR("PCH transcoder C FIFO underrun\n"); |
8664281b PZ |
1957 | |
1958 | I915_WRITE(SERR_INT, serr_int); | |
776ad806 JB |
1959 | } |
1960 | ||
23e81d69 AJ |
1961 | static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) |
1962 | { | |
2d1013dd | 1963 | struct drm_i915_private *dev_priv = dev->dev_private; |
23e81d69 | 1964 | int pipe; |
b543fb04 | 1965 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; |
23e81d69 | 1966 | |
91d131d2 DV |
1967 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt); |
1968 | ||
cfc33bf7 VS |
1969 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { |
1970 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> | |
1971 | SDE_AUDIO_POWER_SHIFT_CPT); | |
1972 | DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", | |
1973 | port_name(port)); | |
1974 | } | |
23e81d69 AJ |
1975 | |
1976 | if (pch_iir & SDE_AUX_MASK_CPT) | |
ce99c256 | 1977 | dp_aux_irq_handler(dev); |
23e81d69 AJ |
1978 | |
1979 | if (pch_iir & SDE_GMBUS_CPT) | |
515ac2bb | 1980 | gmbus_irq_handler(dev); |
23e81d69 AJ |
1981 | |
1982 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) | |
1983 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); | |
1984 | ||
1985 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) | |
1986 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); | |
1987 | ||
1988 | if (pch_iir & SDE_FDI_MASK_CPT) | |
1989 | for_each_pipe(pipe) | |
1990 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", | |
1991 | pipe_name(pipe), | |
1992 | I915_READ(FDI_RX_IIR(pipe))); | |
8664281b PZ |
1993 | |
1994 | if (pch_iir & SDE_ERROR_CPT) | |
1995 | cpt_serr_int_handler(dev); | |
23e81d69 AJ |
1996 | } |
1997 | ||
c008bc6e PZ |
1998 | static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) |
1999 | { | |
2000 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40da17c2 | 2001 | enum pipe pipe; |
c008bc6e PZ |
2002 | |
2003 | if (de_iir & DE_AUX_CHANNEL_A) | |
2004 | dp_aux_irq_handler(dev); | |
2005 | ||
2006 | if (de_iir & DE_GSE) | |
2007 | intel_opregion_asle_intr(dev); | |
2008 | ||
c008bc6e PZ |
2009 | if (de_iir & DE_POISON) |
2010 | DRM_ERROR("Poison interrupt\n"); | |
2011 | ||
40da17c2 DV |
2012 | for_each_pipe(pipe) { |
2013 | if (de_iir & DE_PIPE_VBLANK(pipe)) | |
8d7849db | 2014 | intel_pipe_handle_vblank(dev, pipe); |
5b3a856b | 2015 | |
40da17c2 DV |
2016 | if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) |
2017 | if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
fc2c807b VS |
2018 | DRM_ERROR("Pipe %c FIFO underrun\n", |
2019 | pipe_name(pipe)); | |
5b3a856b | 2020 | |
40da17c2 DV |
2021 | if (de_iir & DE_PIPE_CRC_DONE(pipe)) |
2022 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
c008bc6e | 2023 | |
40da17c2 DV |
2024 | /* plane/pipes map 1:1 on ilk+ */ |
2025 | if (de_iir & DE_PLANE_FLIP_DONE(pipe)) { | |
2026 | intel_prepare_page_flip(dev, pipe); | |
2027 | intel_finish_page_flip_plane(dev, pipe); | |
2028 | } | |
c008bc6e PZ |
2029 | } |
2030 | ||
2031 | /* check event from PCH */ | |
2032 | if (de_iir & DE_PCH_EVENT) { | |
2033 | u32 pch_iir = I915_READ(SDEIIR); | |
2034 | ||
2035 | if (HAS_PCH_CPT(dev)) | |
2036 | cpt_irq_handler(dev, pch_iir); | |
2037 | else | |
2038 | ibx_irq_handler(dev, pch_iir); | |
2039 | ||
2040 | /* should clear PCH hotplug event before clear CPU irq */ | |
2041 | I915_WRITE(SDEIIR, pch_iir); | |
2042 | } | |
2043 | ||
2044 | if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) | |
2045 | ironlake_rps_change_irq_handler(dev); | |
2046 | } | |
2047 | ||
9719fb98 PZ |
2048 | static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir) |
2049 | { | |
2050 | struct drm_i915_private *dev_priv = dev->dev_private; | |
07d27e20 | 2051 | enum pipe pipe; |
9719fb98 PZ |
2052 | |
2053 | if (de_iir & DE_ERR_INT_IVB) | |
2054 | ivb_err_int_handler(dev); | |
2055 | ||
2056 | if (de_iir & DE_AUX_CHANNEL_A_IVB) | |
2057 | dp_aux_irq_handler(dev); | |
2058 | ||
2059 | if (de_iir & DE_GSE_IVB) | |
2060 | intel_opregion_asle_intr(dev); | |
2061 | ||
07d27e20 DL |
2062 | for_each_pipe(pipe) { |
2063 | if (de_iir & (DE_PIPE_VBLANK_IVB(pipe))) | |
8d7849db | 2064 | intel_pipe_handle_vblank(dev, pipe); |
40da17c2 DV |
2065 | |
2066 | /* plane/pipes map 1:1 on ilk+ */ | |
07d27e20 DL |
2067 | if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) { |
2068 | intel_prepare_page_flip(dev, pipe); | |
2069 | intel_finish_page_flip_plane(dev, pipe); | |
9719fb98 PZ |
2070 | } |
2071 | } | |
2072 | ||
2073 | /* check event from PCH */ | |
2074 | if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) { | |
2075 | u32 pch_iir = I915_READ(SDEIIR); | |
2076 | ||
2077 | cpt_irq_handler(dev, pch_iir); | |
2078 | ||
2079 | /* clear PCH hotplug event before clear CPU irq */ | |
2080 | I915_WRITE(SDEIIR, pch_iir); | |
2081 | } | |
2082 | } | |
2083 | ||
f1af8fc1 | 2084 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
b1f14ad0 | 2085 | { |
45a83f84 | 2086 | struct drm_device *dev = arg; |
2d1013dd | 2087 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1af8fc1 | 2088 | u32 de_iir, gt_iir, de_ier, sde_ier = 0; |
0e43406b | 2089 | irqreturn_t ret = IRQ_NONE; |
b1f14ad0 | 2090 | |
8664281b PZ |
2091 | /* We get interrupts on unclaimed registers, so check for this before we |
2092 | * do any I915_{READ,WRITE}. */ | |
907b28c5 | 2093 | intel_uncore_check_errors(dev); |
8664281b | 2094 | |
b1f14ad0 JB |
2095 | /* disable master interrupt before clearing iir */ |
2096 | de_ier = I915_READ(DEIER); | |
2097 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
23a78516 | 2098 | POSTING_READ(DEIER); |
b1f14ad0 | 2099 | |
44498aea PZ |
2100 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
2101 | * interrupts will will be stored on its back queue, and then we'll be | |
2102 | * able to process them after we restore SDEIER (as soon as we restore | |
2103 | * it, we'll get an interrupt if SDEIIR still has something to process | |
2104 | * due to its back queue). */ | |
ab5c608b BW |
2105 | if (!HAS_PCH_NOP(dev)) { |
2106 | sde_ier = I915_READ(SDEIER); | |
2107 | I915_WRITE(SDEIER, 0); | |
2108 | POSTING_READ(SDEIER); | |
2109 | } | |
44498aea | 2110 | |
b1f14ad0 | 2111 | gt_iir = I915_READ(GTIIR); |
0e43406b | 2112 | if (gt_iir) { |
d8fc8a47 | 2113 | if (INTEL_INFO(dev)->gen >= 6) |
f1af8fc1 | 2114 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
d8fc8a47 PZ |
2115 | else |
2116 | ilk_gt_irq_handler(dev, dev_priv, gt_iir); | |
0e43406b CW |
2117 | I915_WRITE(GTIIR, gt_iir); |
2118 | ret = IRQ_HANDLED; | |
b1f14ad0 JB |
2119 | } |
2120 | ||
0e43406b CW |
2121 | de_iir = I915_READ(DEIIR); |
2122 | if (de_iir) { | |
f1af8fc1 PZ |
2123 | if (INTEL_INFO(dev)->gen >= 7) |
2124 | ivb_display_irq_handler(dev, de_iir); | |
2125 | else | |
2126 | ilk_display_irq_handler(dev, de_iir); | |
0e43406b CW |
2127 | I915_WRITE(DEIIR, de_iir); |
2128 | ret = IRQ_HANDLED; | |
b1f14ad0 JB |
2129 | } |
2130 | ||
f1af8fc1 PZ |
2131 | if (INTEL_INFO(dev)->gen >= 6) { |
2132 | u32 pm_iir = I915_READ(GEN6_PMIIR); | |
2133 | if (pm_iir) { | |
1403c0d4 | 2134 | gen6_rps_irq_handler(dev_priv, pm_iir); |
f1af8fc1 PZ |
2135 | I915_WRITE(GEN6_PMIIR, pm_iir); |
2136 | ret = IRQ_HANDLED; | |
2137 | } | |
0e43406b | 2138 | } |
b1f14ad0 | 2139 | |
b1f14ad0 JB |
2140 | I915_WRITE(DEIER, de_ier); |
2141 | POSTING_READ(DEIER); | |
ab5c608b BW |
2142 | if (!HAS_PCH_NOP(dev)) { |
2143 | I915_WRITE(SDEIER, sde_ier); | |
2144 | POSTING_READ(SDEIER); | |
2145 | } | |
b1f14ad0 JB |
2146 | |
2147 | return ret; | |
2148 | } | |
2149 | ||
abd58f01 BW |
2150 | static irqreturn_t gen8_irq_handler(int irq, void *arg) |
2151 | { | |
2152 | struct drm_device *dev = arg; | |
2153 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2154 | u32 master_ctl; | |
2155 | irqreturn_t ret = IRQ_NONE; | |
2156 | uint32_t tmp = 0; | |
c42664cc | 2157 | enum pipe pipe; |
abd58f01 | 2158 | |
abd58f01 BW |
2159 | master_ctl = I915_READ(GEN8_MASTER_IRQ); |
2160 | master_ctl &= ~GEN8_MASTER_IRQ_CONTROL; | |
2161 | if (!master_ctl) | |
2162 | return IRQ_NONE; | |
2163 | ||
2164 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
2165 | POSTING_READ(GEN8_MASTER_IRQ); | |
2166 | ||
2167 | ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl); | |
2168 | ||
2169 | if (master_ctl & GEN8_DE_MISC_IRQ) { | |
2170 | tmp = I915_READ(GEN8_DE_MISC_IIR); | |
2171 | if (tmp & GEN8_DE_MISC_GSE) | |
2172 | intel_opregion_asle_intr(dev); | |
2173 | else if (tmp) | |
2174 | DRM_ERROR("Unexpected DE Misc interrupt\n"); | |
2175 | else | |
2176 | DRM_ERROR("The master control interrupt lied (DE MISC)!\n"); | |
2177 | ||
2178 | if (tmp) { | |
2179 | I915_WRITE(GEN8_DE_MISC_IIR, tmp); | |
2180 | ret = IRQ_HANDLED; | |
2181 | } | |
2182 | } | |
2183 | ||
6d766f02 DV |
2184 | if (master_ctl & GEN8_DE_PORT_IRQ) { |
2185 | tmp = I915_READ(GEN8_DE_PORT_IIR); | |
2186 | if (tmp & GEN8_AUX_CHANNEL_A) | |
2187 | dp_aux_irq_handler(dev); | |
2188 | else if (tmp) | |
2189 | DRM_ERROR("Unexpected DE Port interrupt\n"); | |
2190 | else | |
2191 | DRM_ERROR("The master control interrupt lied (DE PORT)!\n"); | |
2192 | ||
2193 | if (tmp) { | |
2194 | I915_WRITE(GEN8_DE_PORT_IIR, tmp); | |
2195 | ret = IRQ_HANDLED; | |
2196 | } | |
2197 | } | |
2198 | ||
c42664cc DV |
2199 | for_each_pipe(pipe) { |
2200 | uint32_t pipe_iir; | |
abd58f01 | 2201 | |
c42664cc DV |
2202 | if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) |
2203 | continue; | |
abd58f01 | 2204 | |
c42664cc DV |
2205 | pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); |
2206 | if (pipe_iir & GEN8_PIPE_VBLANK) | |
8d7849db | 2207 | intel_pipe_handle_vblank(dev, pipe); |
abd58f01 | 2208 | |
d0e1f1cb | 2209 | if (pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE) { |
c42664cc DV |
2210 | intel_prepare_page_flip(dev, pipe); |
2211 | intel_finish_page_flip_plane(dev, pipe); | |
abd58f01 | 2212 | } |
c42664cc | 2213 | |
0fbe7870 DV |
2214 | if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE) |
2215 | hsw_pipe_crc_irq_handler(dev, pipe); | |
2216 | ||
38d83c96 DV |
2217 | if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) { |
2218 | if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, | |
2219 | false)) | |
fc2c807b VS |
2220 | DRM_ERROR("Pipe %c FIFO underrun\n", |
2221 | pipe_name(pipe)); | |
38d83c96 DV |
2222 | } |
2223 | ||
30100f2b DV |
2224 | if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) { |
2225 | DRM_ERROR("Fault errors on pipe %c\n: 0x%08x", | |
2226 | pipe_name(pipe), | |
2227 | pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS); | |
2228 | } | |
c42664cc DV |
2229 | |
2230 | if (pipe_iir) { | |
2231 | ret = IRQ_HANDLED; | |
2232 | I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir); | |
2233 | } else | |
abd58f01 BW |
2234 | DRM_ERROR("The master control interrupt lied (DE PIPE)!\n"); |
2235 | } | |
2236 | ||
92d03a80 DV |
2237 | if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) { |
2238 | /* | |
2239 | * FIXME(BDW): Assume for now that the new interrupt handling | |
2240 | * scheme also closed the SDE interrupt handling race we've seen | |
2241 | * on older pch-split platforms. But this needs testing. | |
2242 | */ | |
2243 | u32 pch_iir = I915_READ(SDEIIR); | |
2244 | ||
2245 | cpt_irq_handler(dev, pch_iir); | |
2246 | ||
2247 | if (pch_iir) { | |
2248 | I915_WRITE(SDEIIR, pch_iir); | |
2249 | ret = IRQ_HANDLED; | |
2250 | } | |
2251 | } | |
2252 | ||
abd58f01 BW |
2253 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
2254 | POSTING_READ(GEN8_MASTER_IRQ); | |
2255 | ||
2256 | return ret; | |
2257 | } | |
2258 | ||
17e1df07 DV |
2259 | static void i915_error_wake_up(struct drm_i915_private *dev_priv, |
2260 | bool reset_completed) | |
2261 | { | |
2262 | struct intel_ring_buffer *ring; | |
2263 | int i; | |
2264 | ||
2265 | /* | |
2266 | * Notify all waiters for GPU completion events that reset state has | |
2267 | * been changed, and that they need to restart their wait after | |
2268 | * checking for potential errors (and bail out to drop locks if there is | |
2269 | * a gpu reset pending so that i915_error_work_func can acquire them). | |
2270 | */ | |
2271 | ||
2272 | /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */ | |
2273 | for_each_ring(ring, dev_priv, i) | |
2274 | wake_up_all(&ring->irq_queue); | |
2275 | ||
2276 | /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */ | |
2277 | wake_up_all(&dev_priv->pending_flip_queue); | |
2278 | ||
2279 | /* | |
2280 | * Signal tasks blocked in i915_gem_wait_for_error that the pending | |
2281 | * reset state is cleared. | |
2282 | */ | |
2283 | if (reset_completed) | |
2284 | wake_up_all(&dev_priv->gpu_error.reset_queue); | |
2285 | } | |
2286 | ||
8a905236 JB |
2287 | /** |
2288 | * i915_error_work_func - do process context error handling work | |
2289 | * @work: work struct | |
2290 | * | |
2291 | * Fire an error uevent so userspace can see that a hang or error | |
2292 | * was detected. | |
2293 | */ | |
2294 | static void i915_error_work_func(struct work_struct *work) | |
2295 | { | |
1f83fee0 DV |
2296 | struct i915_gpu_error *error = container_of(work, struct i915_gpu_error, |
2297 | work); | |
2d1013dd JN |
2298 | struct drm_i915_private *dev_priv = |
2299 | container_of(error, struct drm_i915_private, gpu_error); | |
8a905236 | 2300 | struct drm_device *dev = dev_priv->dev; |
cce723ed BW |
2301 | char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; |
2302 | char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; | |
2303 | char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; | |
17e1df07 | 2304 | int ret; |
8a905236 | 2305 | |
5bdebb18 | 2306 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event); |
f316a42c | 2307 | |
7db0ba24 DV |
2308 | /* |
2309 | * Note that there's only one work item which does gpu resets, so we | |
2310 | * need not worry about concurrent gpu resets potentially incrementing | |
2311 | * error->reset_counter twice. We only need to take care of another | |
2312 | * racing irq/hangcheck declaring the gpu dead for a second time. A | |
2313 | * quick check for that is good enough: schedule_work ensures the | |
2314 | * correct ordering between hang detection and this work item, and since | |
2315 | * the reset in-progress bit is only ever set by code outside of this | |
2316 | * work we don't need to worry about any other races. | |
2317 | */ | |
2318 | if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) { | |
f803aa55 | 2319 | DRM_DEBUG_DRIVER("resetting chip\n"); |
5bdebb18 | 2320 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, |
7db0ba24 | 2321 | reset_event); |
1f83fee0 | 2322 | |
f454c694 ID |
2323 | /* |
2324 | * In most cases it's guaranteed that we get here with an RPM | |
2325 | * reference held, for example because there is a pending GPU | |
2326 | * request that won't finish until the reset is done. This | |
2327 | * isn't the case at least when we get here by doing a | |
2328 | * simulated reset via debugs, so get an RPM reference. | |
2329 | */ | |
2330 | intel_runtime_pm_get(dev_priv); | |
17e1df07 DV |
2331 | /* |
2332 | * All state reset _must_ be completed before we update the | |
2333 | * reset counter, for otherwise waiters might miss the reset | |
2334 | * pending state and not properly drop locks, resulting in | |
2335 | * deadlocks with the reset work. | |
2336 | */ | |
f69061be DV |
2337 | ret = i915_reset(dev); |
2338 | ||
17e1df07 DV |
2339 | intel_display_handle_reset(dev); |
2340 | ||
f454c694 ID |
2341 | intel_runtime_pm_put(dev_priv); |
2342 | ||
f69061be DV |
2343 | if (ret == 0) { |
2344 | /* | |
2345 | * After all the gem state is reset, increment the reset | |
2346 | * counter and wake up everyone waiting for the reset to | |
2347 | * complete. | |
2348 | * | |
2349 | * Since unlock operations are a one-sided barrier only, | |
2350 | * we need to insert a barrier here to order any seqno | |
2351 | * updates before | |
2352 | * the counter increment. | |
2353 | */ | |
2354 | smp_mb__before_atomic_inc(); | |
2355 | atomic_inc(&dev_priv->gpu_error.reset_counter); | |
2356 | ||
5bdebb18 | 2357 | kobject_uevent_env(&dev->primary->kdev->kobj, |
f69061be | 2358 | KOBJ_CHANGE, reset_done_event); |
1f83fee0 | 2359 | } else { |
2ac0f450 | 2360 | atomic_set_mask(I915_WEDGED, &error->reset_counter); |
f316a42c | 2361 | } |
1f83fee0 | 2362 | |
17e1df07 DV |
2363 | /* |
2364 | * Note: The wake_up also serves as a memory barrier so that | |
2365 | * waiters see the update value of the reset counter atomic_t. | |
2366 | */ | |
2367 | i915_error_wake_up(dev_priv, true); | |
f316a42c | 2368 | } |
8a905236 JB |
2369 | } |
2370 | ||
35aed2e6 | 2371 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
2372 | { |
2373 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bd9854f9 | 2374 | uint32_t instdone[I915_NUM_INSTDONE_REG]; |
8a905236 | 2375 | u32 eir = I915_READ(EIR); |
050ee91f | 2376 | int pipe, i; |
8a905236 | 2377 | |
35aed2e6 CW |
2378 | if (!eir) |
2379 | return; | |
8a905236 | 2380 | |
a70491cc | 2381 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
8a905236 | 2382 | |
bd9854f9 BW |
2383 | i915_get_extra_instdone(dev, instdone); |
2384 | ||
8a905236 JB |
2385 | if (IS_G4X(dev)) { |
2386 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
2387 | u32 ipeir = I915_READ(IPEIR_I965); | |
2388 | ||
a70491cc JP |
2389 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2390 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
050ee91f BW |
2391 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2392 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a70491cc | 2393 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2394 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2395 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2396 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2397 | } |
2398 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
2399 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2400 | pr_err("page table error\n"); |
2401 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2402 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2403 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2404 | } |
2405 | } | |
2406 | ||
a6c45cf0 | 2407 | if (!IS_GEN2(dev)) { |
8a905236 JB |
2408 | if (eir & I915_ERROR_PAGE_TABLE) { |
2409 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2410 | pr_err("page table error\n"); |
2411 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2412 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2413 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2414 | } |
2415 | } | |
2416 | ||
2417 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
a70491cc | 2418 | pr_err("memory refresh error:\n"); |
9db4a9c7 | 2419 | for_each_pipe(pipe) |
a70491cc | 2420 | pr_err("pipe %c stat: 0x%08x\n", |
9db4a9c7 | 2421 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
8a905236 JB |
2422 | /* pipestat has already been acked */ |
2423 | } | |
2424 | if (eir & I915_ERROR_INSTRUCTION) { | |
a70491cc JP |
2425 | pr_err("instruction error\n"); |
2426 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); | |
050ee91f BW |
2427 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2428 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a6c45cf0 | 2429 | if (INTEL_INFO(dev)->gen < 4) { |
8a905236 JB |
2430 | u32 ipeir = I915_READ(IPEIR); |
2431 | ||
a70491cc JP |
2432 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
2433 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); | |
a70491cc | 2434 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); |
8a905236 | 2435 | I915_WRITE(IPEIR, ipeir); |
3143a2bf | 2436 | POSTING_READ(IPEIR); |
8a905236 JB |
2437 | } else { |
2438 | u32 ipeir = I915_READ(IPEIR_I965); | |
2439 | ||
a70491cc JP |
2440 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2441 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
a70491cc | 2442 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2443 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2444 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2445 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2446 | } |
2447 | } | |
2448 | ||
2449 | I915_WRITE(EIR, eir); | |
3143a2bf | 2450 | POSTING_READ(EIR); |
8a905236 JB |
2451 | eir = I915_READ(EIR); |
2452 | if (eir) { | |
2453 | /* | |
2454 | * some errors might have become stuck, | |
2455 | * mask them. | |
2456 | */ | |
2457 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
2458 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
2459 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2460 | } | |
35aed2e6 CW |
2461 | } |
2462 | ||
2463 | /** | |
2464 | * i915_handle_error - handle an error interrupt | |
2465 | * @dev: drm device | |
2466 | * | |
2467 | * Do some basic checking of regsiter state at error interrupt time and | |
2468 | * dump it to the syslog. Also call i915_capture_error_state() to make | |
2469 | * sure we get a record and make it available in debugfs. Fire a uevent | |
2470 | * so userspace knows something bad happened (should trigger collection | |
2471 | * of a ring dump etc.). | |
2472 | */ | |
58174462 MK |
2473 | void i915_handle_error(struct drm_device *dev, bool wedged, |
2474 | const char *fmt, ...) | |
35aed2e6 CW |
2475 | { |
2476 | struct drm_i915_private *dev_priv = dev->dev_private; | |
58174462 MK |
2477 | va_list args; |
2478 | char error_msg[80]; | |
35aed2e6 | 2479 | |
58174462 MK |
2480 | va_start(args, fmt); |
2481 | vscnprintf(error_msg, sizeof(error_msg), fmt, args); | |
2482 | va_end(args); | |
2483 | ||
2484 | i915_capture_error_state(dev, wedged, error_msg); | |
35aed2e6 | 2485 | i915_report_and_clear_eir(dev); |
8a905236 | 2486 | |
ba1234d1 | 2487 | if (wedged) { |
f69061be DV |
2488 | atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG, |
2489 | &dev_priv->gpu_error.reset_counter); | |
ba1234d1 | 2490 | |
11ed50ec | 2491 | /* |
17e1df07 DV |
2492 | * Wakeup waiting processes so that the reset work function |
2493 | * i915_error_work_func doesn't deadlock trying to grab various | |
2494 | * locks. By bumping the reset counter first, the woken | |
2495 | * processes will see a reset in progress and back off, | |
2496 | * releasing their locks and then wait for the reset completion. | |
2497 | * We must do this for _all_ gpu waiters that might hold locks | |
2498 | * that the reset work needs to acquire. | |
2499 | * | |
2500 | * Note: The wake_up serves as the required memory barrier to | |
2501 | * ensure that the waiters see the updated value of the reset | |
2502 | * counter atomic_t. | |
11ed50ec | 2503 | */ |
17e1df07 | 2504 | i915_error_wake_up(dev_priv, false); |
11ed50ec BG |
2505 | } |
2506 | ||
122f46ba DV |
2507 | /* |
2508 | * Our reset work can grab modeset locks (since it needs to reset the | |
2509 | * state of outstanding pagelips). Hence it must not be run on our own | |
2510 | * dev-priv->wq work queue for otherwise the flush_work in the pageflip | |
2511 | * code will deadlock. | |
2512 | */ | |
2513 | schedule_work(&dev_priv->gpu_error.work); | |
8a905236 JB |
2514 | } |
2515 | ||
21ad8330 | 2516 | static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe) |
4e5359cd | 2517 | { |
2d1013dd | 2518 | struct drm_i915_private *dev_priv = dev->dev_private; |
4e5359cd SF |
2519 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
2520 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 2521 | struct drm_i915_gem_object *obj; |
4e5359cd SF |
2522 | struct intel_unpin_work *work; |
2523 | unsigned long flags; | |
2524 | bool stall_detected; | |
2525 | ||
2526 | /* Ignore early vblank irqs */ | |
2527 | if (intel_crtc == NULL) | |
2528 | return; | |
2529 | ||
2530 | spin_lock_irqsave(&dev->event_lock, flags); | |
2531 | work = intel_crtc->unpin_work; | |
2532 | ||
e7d841ca CW |
2533 | if (work == NULL || |
2534 | atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE || | |
2535 | !work->enable_stall_check) { | |
4e5359cd SF |
2536 | /* Either the pending flip IRQ arrived, or we're too early. Don't check */ |
2537 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2538 | return; | |
2539 | } | |
2540 | ||
2541 | /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ | |
05394f39 | 2542 | obj = work->pending_flip_obj; |
a6c45cf0 | 2543 | if (INTEL_INFO(dev)->gen >= 4) { |
9db4a9c7 | 2544 | int dspsurf = DSPSURF(intel_crtc->plane); |
446f2545 | 2545 | stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) == |
f343c5f6 | 2546 | i915_gem_obj_ggtt_offset(obj); |
4e5359cd | 2547 | } else { |
9db4a9c7 | 2548 | int dspaddr = DSPADDR(intel_crtc->plane); |
f343c5f6 | 2549 | stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) + |
f4510a27 MR |
2550 | crtc->y * crtc->primary->fb->pitches[0] + |
2551 | crtc->x * crtc->primary->fb->bits_per_pixel/8); | |
4e5359cd SF |
2552 | } |
2553 | ||
2554 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2555 | ||
2556 | if (stall_detected) { | |
2557 | DRM_DEBUG_DRIVER("Pageflip stall detected\n"); | |
2558 | intel_prepare_page_flip(dev, intel_crtc->plane); | |
2559 | } | |
2560 | } | |
2561 | ||
42f52ef8 KP |
2562 | /* Called from drm generic code, passed 'crtc' which |
2563 | * we use as a pipe index | |
2564 | */ | |
f71d4af4 | 2565 | static int i915_enable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 | 2566 | { |
2d1013dd | 2567 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2568 | unsigned long irqflags; |
71e0ffa5 | 2569 | |
5eddb70b | 2570 | if (!i915_pipe_enabled(dev, pipe)) |
71e0ffa5 | 2571 | return -EINVAL; |
0a3e67a4 | 2572 | |
1ec14ad3 | 2573 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2574 | if (INTEL_INFO(dev)->gen >= 4) |
7c463586 | 2575 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2576 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
e9d21d7f | 2577 | else |
7c463586 | 2578 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2579 | PIPE_VBLANK_INTERRUPT_STATUS); |
8692d00e CW |
2580 | |
2581 | /* maintain vblank delivery even in deep C-states */ | |
3d13ef2e | 2582 | if (INTEL_INFO(dev)->gen == 3) |
6b26c86d | 2583 | I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS)); |
1ec14ad3 | 2584 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
8692d00e | 2585 | |
0a3e67a4 JB |
2586 | return 0; |
2587 | } | |
2588 | ||
f71d4af4 | 2589 | static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
f796cf8f | 2590 | { |
2d1013dd | 2591 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2592 | unsigned long irqflags; |
b518421f | 2593 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2594 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2595 | |
2596 | if (!i915_pipe_enabled(dev, pipe)) | |
2597 | return -EINVAL; | |
2598 | ||
2599 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 2600 | ironlake_enable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2601 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2602 | ||
2603 | return 0; | |
2604 | } | |
2605 | ||
7e231dbe JB |
2606 | static int valleyview_enable_vblank(struct drm_device *dev, int pipe) |
2607 | { | |
2d1013dd | 2608 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2609 | unsigned long irqflags; |
7e231dbe JB |
2610 | |
2611 | if (!i915_pipe_enabled(dev, pipe)) | |
2612 | return -EINVAL; | |
2613 | ||
2614 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 | 2615 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2616 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2617 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2618 | ||
2619 | return 0; | |
2620 | } | |
2621 | ||
abd58f01 BW |
2622 | static int gen8_enable_vblank(struct drm_device *dev, int pipe) |
2623 | { | |
2624 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2625 | unsigned long irqflags; | |
abd58f01 BW |
2626 | |
2627 | if (!i915_pipe_enabled(dev, pipe)) | |
2628 | return -EINVAL; | |
2629 | ||
2630 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
7167d7c6 DV |
2631 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK; |
2632 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2633 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2634 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2635 | return 0; | |
2636 | } | |
2637 | ||
42f52ef8 KP |
2638 | /* Called from drm generic code, passed 'crtc' which |
2639 | * we use as a pipe index | |
2640 | */ | |
f71d4af4 | 2641 | static void i915_disable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 | 2642 | { |
2d1013dd | 2643 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2644 | unsigned long irqflags; |
0a3e67a4 | 2645 | |
1ec14ad3 | 2646 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
3d13ef2e | 2647 | if (INTEL_INFO(dev)->gen == 3) |
6b26c86d | 2648 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS)); |
8692d00e | 2649 | |
f796cf8f | 2650 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 ID |
2651 | PIPE_VBLANK_INTERRUPT_STATUS | |
2652 | PIPE_START_VBLANK_INTERRUPT_STATUS); | |
f796cf8f JB |
2653 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2654 | } | |
2655 | ||
f71d4af4 | 2656 | static void ironlake_disable_vblank(struct drm_device *dev, int pipe) |
f796cf8f | 2657 | { |
2d1013dd | 2658 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2659 | unsigned long irqflags; |
b518421f | 2660 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2661 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2662 | |
2663 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 2664 | ironlake_disable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2665 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2666 | } | |
2667 | ||
7e231dbe JB |
2668 | static void valleyview_disable_vblank(struct drm_device *dev, int pipe) |
2669 | { | |
2d1013dd | 2670 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2671 | unsigned long irqflags; |
7e231dbe JB |
2672 | |
2673 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 | 2674 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 | 2675 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2676 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2677 | } | |
2678 | ||
abd58f01 BW |
2679 | static void gen8_disable_vblank(struct drm_device *dev, int pipe) |
2680 | { | |
2681 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2682 | unsigned long irqflags; | |
abd58f01 BW |
2683 | |
2684 | if (!i915_pipe_enabled(dev, pipe)) | |
2685 | return; | |
2686 | ||
2687 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
7167d7c6 DV |
2688 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK; |
2689 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2690 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2691 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2692 | } | |
2693 | ||
893eead0 CW |
2694 | static u32 |
2695 | ring_last_seqno(struct intel_ring_buffer *ring) | |
852835f3 | 2696 | { |
893eead0 CW |
2697 | return list_entry(ring->request_list.prev, |
2698 | struct drm_i915_gem_request, list)->seqno; | |
2699 | } | |
2700 | ||
9107e9d2 CW |
2701 | static bool |
2702 | ring_idle(struct intel_ring_buffer *ring, u32 seqno) | |
2703 | { | |
2704 | return (list_empty(&ring->request_list) || | |
2705 | i915_seqno_passed(seqno, ring_last_seqno(ring))); | |
f65d9421 BG |
2706 | } |
2707 | ||
a028c4b0 DV |
2708 | static bool |
2709 | ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr) | |
2710 | { | |
2711 | if (INTEL_INFO(dev)->gen >= 8) { | |
2712 | /* | |
2713 | * FIXME: gen8 semaphore support - currently we don't emit | |
2714 | * semaphores on bdw anyway, but this needs to be addressed when | |
2715 | * we merge that code. | |
2716 | */ | |
2717 | return false; | |
2718 | } else { | |
2719 | ipehr &= ~MI_SEMAPHORE_SYNC_MASK; | |
2720 | return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | | |
2721 | MI_SEMAPHORE_REGISTER); | |
2722 | } | |
2723 | } | |
2724 | ||
921d42ea DV |
2725 | static struct intel_ring_buffer * |
2726 | semaphore_wait_to_signaller_ring(struct intel_ring_buffer *ring, u32 ipehr) | |
2727 | { | |
2728 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
2729 | struct intel_ring_buffer *signaller; | |
2730 | int i; | |
2731 | ||
2732 | if (INTEL_INFO(dev_priv->dev)->gen >= 8) { | |
2733 | /* | |
2734 | * FIXME: gen8 semaphore support - currently we don't emit | |
2735 | * semaphores on bdw anyway, but this needs to be addressed when | |
2736 | * we merge that code. | |
2737 | */ | |
2738 | return NULL; | |
2739 | } else { | |
2740 | u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK; | |
2741 | ||
2742 | for_each_ring(signaller, dev_priv, i) { | |
2743 | if(ring == signaller) | |
2744 | continue; | |
2745 | ||
ebc348b2 | 2746 | if (sync_bits == signaller->semaphore.mbox.wait[ring->id]) |
921d42ea DV |
2747 | return signaller; |
2748 | } | |
2749 | } | |
2750 | ||
2751 | DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x\n", | |
2752 | ring->id, ipehr); | |
2753 | ||
2754 | return NULL; | |
2755 | } | |
2756 | ||
6274f212 CW |
2757 | static struct intel_ring_buffer * |
2758 | semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno) | |
a24a11e6 CW |
2759 | { |
2760 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
88fe429d DV |
2761 | u32 cmd, ipehr, head; |
2762 | int i; | |
a24a11e6 CW |
2763 | |
2764 | ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); | |
a028c4b0 | 2765 | if (!ipehr_is_semaphore_wait(ring->dev, ipehr)) |
6274f212 | 2766 | return NULL; |
a24a11e6 | 2767 | |
88fe429d DV |
2768 | /* |
2769 | * HEAD is likely pointing to the dword after the actual command, | |
2770 | * so scan backwards until we find the MBOX. But limit it to just 3 | |
2771 | * dwords. Note that we don't care about ACTHD here since that might | |
2772 | * point at at batch, and semaphores are always emitted into the | |
2773 | * ringbuffer itself. | |
a24a11e6 | 2774 | */ |
88fe429d DV |
2775 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
2776 | ||
2777 | for (i = 4; i; --i) { | |
2778 | /* | |
2779 | * Be paranoid and presume the hw has gone off into the wild - | |
2780 | * our ring is smaller than what the hardware (and hence | |
2781 | * HEAD_ADDR) allows. Also handles wrap-around. | |
2782 | */ | |
2783 | head &= ring->size - 1; | |
2784 | ||
2785 | /* This here seems to blow up */ | |
2786 | cmd = ioread32(ring->virtual_start + head); | |
a24a11e6 CW |
2787 | if (cmd == ipehr) |
2788 | break; | |
2789 | ||
88fe429d DV |
2790 | head -= 4; |
2791 | } | |
a24a11e6 | 2792 | |
88fe429d DV |
2793 | if (!i) |
2794 | return NULL; | |
a24a11e6 | 2795 | |
88fe429d | 2796 | *seqno = ioread32(ring->virtual_start + head + 4) + 1; |
921d42ea | 2797 | return semaphore_wait_to_signaller_ring(ring, ipehr); |
a24a11e6 CW |
2798 | } |
2799 | ||
6274f212 CW |
2800 | static int semaphore_passed(struct intel_ring_buffer *ring) |
2801 | { | |
2802 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
2803 | struct intel_ring_buffer *signaller; | |
2804 | u32 seqno, ctl; | |
2805 | ||
2806 | ring->hangcheck.deadlock = true; | |
2807 | ||
2808 | signaller = semaphore_waits_for(ring, &seqno); | |
2809 | if (signaller == NULL || signaller->hangcheck.deadlock) | |
2810 | return -1; | |
2811 | ||
2812 | /* cursory check for an unkickable deadlock */ | |
2813 | ctl = I915_READ_CTL(signaller); | |
2814 | if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0) | |
2815 | return -1; | |
2816 | ||
2817 | return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno); | |
2818 | } | |
2819 | ||
2820 | static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) | |
2821 | { | |
2822 | struct intel_ring_buffer *ring; | |
2823 | int i; | |
2824 | ||
2825 | for_each_ring(ring, dev_priv, i) | |
2826 | ring->hangcheck.deadlock = false; | |
2827 | } | |
2828 | ||
ad8beaea | 2829 | static enum intel_ring_hangcheck_action |
50877445 | 2830 | ring_stuck(struct intel_ring_buffer *ring, u64 acthd) |
1ec14ad3 CW |
2831 | { |
2832 | struct drm_device *dev = ring->dev; | |
2833 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9107e9d2 CW |
2834 | u32 tmp; |
2835 | ||
6274f212 | 2836 | if (ring->hangcheck.acthd != acthd) |
f2f4d82f | 2837 | return HANGCHECK_ACTIVE; |
6274f212 | 2838 | |
9107e9d2 | 2839 | if (IS_GEN2(dev)) |
f2f4d82f | 2840 | return HANGCHECK_HUNG; |
9107e9d2 CW |
2841 | |
2842 | /* Is the chip hanging on a WAIT_FOR_EVENT? | |
2843 | * If so we can simply poke the RB_WAIT bit | |
2844 | * and break the hang. This should work on | |
2845 | * all but the second generation chipsets. | |
2846 | */ | |
2847 | tmp = I915_READ_CTL(ring); | |
1ec14ad3 | 2848 | if (tmp & RING_WAIT) { |
58174462 MK |
2849 | i915_handle_error(dev, false, |
2850 | "Kicking stuck wait on %s", | |
2851 | ring->name); | |
1ec14ad3 | 2852 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2853 | return HANGCHECK_KICK; |
6274f212 CW |
2854 | } |
2855 | ||
2856 | if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { | |
2857 | switch (semaphore_passed(ring)) { | |
2858 | default: | |
f2f4d82f | 2859 | return HANGCHECK_HUNG; |
6274f212 | 2860 | case 1: |
58174462 MK |
2861 | i915_handle_error(dev, false, |
2862 | "Kicking stuck semaphore on %s", | |
2863 | ring->name); | |
6274f212 | 2864 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2865 | return HANGCHECK_KICK; |
6274f212 | 2866 | case 0: |
f2f4d82f | 2867 | return HANGCHECK_WAIT; |
6274f212 | 2868 | } |
9107e9d2 | 2869 | } |
ed5cbb03 | 2870 | |
f2f4d82f | 2871 | return HANGCHECK_HUNG; |
ed5cbb03 MK |
2872 | } |
2873 | ||
f65d9421 BG |
2874 | /** |
2875 | * This is called when the chip hasn't reported back with completed | |
05407ff8 MK |
2876 | * batchbuffers in a long time. We keep track per ring seqno progress and |
2877 | * if there are no progress, hangcheck score for that ring is increased. | |
2878 | * Further, acthd is inspected to see if the ring is stuck. On stuck case | |
2879 | * we kick the ring. If we see no progress on three subsequent calls | |
2880 | * we assume chip is wedged and try to fix it by resetting the chip. | |
f65d9421 | 2881 | */ |
a658b5d2 | 2882 | static void i915_hangcheck_elapsed(unsigned long data) |
f65d9421 BG |
2883 | { |
2884 | struct drm_device *dev = (struct drm_device *)data; | |
2d1013dd | 2885 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 2886 | struct intel_ring_buffer *ring; |
b4519513 | 2887 | int i; |
05407ff8 | 2888 | int busy_count = 0, rings_hung = 0; |
9107e9d2 CW |
2889 | bool stuck[I915_NUM_RINGS] = { 0 }; |
2890 | #define BUSY 1 | |
2891 | #define KICK 5 | |
2892 | #define HUNG 20 | |
893eead0 | 2893 | |
d330a953 | 2894 | if (!i915.enable_hangcheck) |
3e0dc6b0 BW |
2895 | return; |
2896 | ||
b4519513 | 2897 | for_each_ring(ring, dev_priv, i) { |
50877445 CW |
2898 | u64 acthd; |
2899 | u32 seqno; | |
9107e9d2 | 2900 | bool busy = true; |
05407ff8 | 2901 | |
6274f212 CW |
2902 | semaphore_clear_deadlocks(dev_priv); |
2903 | ||
05407ff8 MK |
2904 | seqno = ring->get_seqno(ring, false); |
2905 | acthd = intel_ring_get_active_head(ring); | |
b4519513 | 2906 | |
9107e9d2 CW |
2907 | if (ring->hangcheck.seqno == seqno) { |
2908 | if (ring_idle(ring, seqno)) { | |
da661464 MK |
2909 | ring->hangcheck.action = HANGCHECK_IDLE; |
2910 | ||
9107e9d2 CW |
2911 | if (waitqueue_active(&ring->irq_queue)) { |
2912 | /* Issue a wake-up to catch stuck h/w. */ | |
094f9a54 | 2913 | if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) { |
f4adcd24 DV |
2914 | if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring))) |
2915 | DRM_ERROR("Hangcheck timer elapsed... %s idle\n", | |
2916 | ring->name); | |
2917 | else | |
2918 | DRM_INFO("Fake missed irq on %s\n", | |
2919 | ring->name); | |
094f9a54 CW |
2920 | wake_up_all(&ring->irq_queue); |
2921 | } | |
2922 | /* Safeguard against driver failure */ | |
2923 | ring->hangcheck.score += BUSY; | |
9107e9d2 CW |
2924 | } else |
2925 | busy = false; | |
05407ff8 | 2926 | } else { |
6274f212 CW |
2927 | /* We always increment the hangcheck score |
2928 | * if the ring is busy and still processing | |
2929 | * the same request, so that no single request | |
2930 | * can run indefinitely (such as a chain of | |
2931 | * batches). The only time we do not increment | |
2932 | * the hangcheck score on this ring, if this | |
2933 | * ring is in a legitimate wait for another | |
2934 | * ring. In that case the waiting ring is a | |
2935 | * victim and we want to be sure we catch the | |
2936 | * right culprit. Then every time we do kick | |
2937 | * the ring, add a small increment to the | |
2938 | * score so that we can catch a batch that is | |
2939 | * being repeatedly kicked and so responsible | |
2940 | * for stalling the machine. | |
2941 | */ | |
ad8beaea MK |
2942 | ring->hangcheck.action = ring_stuck(ring, |
2943 | acthd); | |
2944 | ||
2945 | switch (ring->hangcheck.action) { | |
da661464 | 2946 | case HANGCHECK_IDLE: |
f2f4d82f | 2947 | case HANGCHECK_WAIT: |
6274f212 | 2948 | break; |
f2f4d82f | 2949 | case HANGCHECK_ACTIVE: |
ea04cb31 | 2950 | ring->hangcheck.score += BUSY; |
6274f212 | 2951 | break; |
f2f4d82f | 2952 | case HANGCHECK_KICK: |
ea04cb31 | 2953 | ring->hangcheck.score += KICK; |
6274f212 | 2954 | break; |
f2f4d82f | 2955 | case HANGCHECK_HUNG: |
ea04cb31 | 2956 | ring->hangcheck.score += HUNG; |
6274f212 CW |
2957 | stuck[i] = true; |
2958 | break; | |
2959 | } | |
05407ff8 | 2960 | } |
9107e9d2 | 2961 | } else { |
da661464 MK |
2962 | ring->hangcheck.action = HANGCHECK_ACTIVE; |
2963 | ||
9107e9d2 CW |
2964 | /* Gradually reduce the count so that we catch DoS |
2965 | * attempts across multiple batches. | |
2966 | */ | |
2967 | if (ring->hangcheck.score > 0) | |
2968 | ring->hangcheck.score--; | |
d1e61e7f CW |
2969 | } |
2970 | ||
05407ff8 MK |
2971 | ring->hangcheck.seqno = seqno; |
2972 | ring->hangcheck.acthd = acthd; | |
9107e9d2 | 2973 | busy_count += busy; |
893eead0 | 2974 | } |
b9201c14 | 2975 | |
92cab734 | 2976 | for_each_ring(ring, dev_priv, i) { |
b6b0fac0 | 2977 | if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) { |
b8d88d1d DV |
2978 | DRM_INFO("%s on %s\n", |
2979 | stuck[i] ? "stuck" : "no progress", | |
2980 | ring->name); | |
a43adf07 | 2981 | rings_hung++; |
92cab734 MK |
2982 | } |
2983 | } | |
2984 | ||
05407ff8 | 2985 | if (rings_hung) |
58174462 | 2986 | return i915_handle_error(dev, true, "Ring hung"); |
f65d9421 | 2987 | |
05407ff8 MK |
2988 | if (busy_count) |
2989 | /* Reset timer case chip hangs without another request | |
2990 | * being added */ | |
10cd45b6 MK |
2991 | i915_queue_hangcheck(dev); |
2992 | } | |
2993 | ||
2994 | void i915_queue_hangcheck(struct drm_device *dev) | |
2995 | { | |
2996 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d330a953 | 2997 | if (!i915.enable_hangcheck) |
10cd45b6 MK |
2998 | return; |
2999 | ||
3000 | mod_timer(&dev_priv->gpu_error.hangcheck_timer, | |
3001 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); | |
f65d9421 BG |
3002 | } |
3003 | ||
1c69eb42 | 3004 | static void ibx_irq_reset(struct drm_device *dev) |
91738a95 PZ |
3005 | { |
3006 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3007 | ||
3008 | if (HAS_PCH_NOP(dev)) | |
3009 | return; | |
3010 | ||
f86f3fb0 | 3011 | GEN5_IRQ_RESET(SDE); |
105b122e PZ |
3012 | |
3013 | if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) | |
3014 | I915_WRITE(SERR_INT, 0xffffffff); | |
622364b6 | 3015 | } |
105b122e | 3016 | |
622364b6 PZ |
3017 | /* |
3018 | * SDEIER is also touched by the interrupt handler to work around missed PCH | |
3019 | * interrupts. Hence we can't update it after the interrupt handler is enabled - | |
3020 | * instead we unconditionally enable all PCH interrupt sources here, but then | |
3021 | * only unmask them as needed with SDEIMR. | |
3022 | * | |
3023 | * This function needs to be called before interrupts are enabled. | |
3024 | */ | |
3025 | static void ibx_irq_pre_postinstall(struct drm_device *dev) | |
3026 | { | |
3027 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3028 | ||
3029 | if (HAS_PCH_NOP(dev)) | |
3030 | return; | |
3031 | ||
3032 | WARN_ON(I915_READ(SDEIER) != 0); | |
91738a95 PZ |
3033 | I915_WRITE(SDEIER, 0xffffffff); |
3034 | POSTING_READ(SDEIER); | |
3035 | } | |
3036 | ||
7c4d664e | 3037 | static void gen5_gt_irq_reset(struct drm_device *dev) |
d18ea1b5 DV |
3038 | { |
3039 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3040 | ||
f86f3fb0 | 3041 | GEN5_IRQ_RESET(GT); |
a9d356a6 | 3042 | if (INTEL_INFO(dev)->gen >= 6) |
f86f3fb0 | 3043 | GEN5_IRQ_RESET(GEN6_PM); |
d18ea1b5 DV |
3044 | } |
3045 | ||
1da177e4 LT |
3046 | /* drm_dma.h hooks |
3047 | */ | |
be30b29f | 3048 | static void ironlake_irq_reset(struct drm_device *dev) |
036a4a7d | 3049 | { |
2d1013dd | 3050 | struct drm_i915_private *dev_priv = dev->dev_private; |
036a4a7d | 3051 | |
0c841212 | 3052 | I915_WRITE(HWSTAM, 0xffffffff); |
bdfcdb63 | 3053 | |
f86f3fb0 | 3054 | GEN5_IRQ_RESET(DE); |
c6d954c1 PZ |
3055 | if (IS_GEN7(dev)) |
3056 | I915_WRITE(GEN7_ERR_INT, 0xffffffff); | |
036a4a7d | 3057 | |
7c4d664e | 3058 | gen5_gt_irq_reset(dev); |
c650156a | 3059 | |
1c69eb42 | 3060 | ibx_irq_reset(dev); |
7d99163d | 3061 | } |
c650156a | 3062 | |
be30b29f PZ |
3063 | static void ironlake_irq_preinstall(struct drm_device *dev) |
3064 | { | |
be30b29f | 3065 | ironlake_irq_reset(dev); |
7d99163d BW |
3066 | } |
3067 | ||
7e231dbe JB |
3068 | static void valleyview_irq_preinstall(struct drm_device *dev) |
3069 | { | |
2d1013dd | 3070 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
3071 | int pipe; |
3072 | ||
7e231dbe JB |
3073 | /* VLV magic */ |
3074 | I915_WRITE(VLV_IMR, 0); | |
3075 | I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); | |
3076 | I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); | |
3077 | I915_WRITE(RING_IMR(BLT_RING_BASE), 0); | |
3078 | ||
7e231dbe JB |
3079 | /* and GT */ |
3080 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
3081 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
d18ea1b5 | 3082 | |
7c4d664e | 3083 | gen5_gt_irq_reset(dev); |
7e231dbe JB |
3084 | |
3085 | I915_WRITE(DPINVGTT, 0xff); | |
3086 | ||
3087 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3088 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3089 | for_each_pipe(pipe) | |
3090 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
3091 | I915_WRITE(VLV_IIR, 0xffffffff); | |
3092 | I915_WRITE(VLV_IMR, 0xffffffff); | |
3093 | I915_WRITE(VLV_IER, 0x0); | |
3094 | POSTING_READ(VLV_IER); | |
3095 | } | |
3096 | ||
823f6b38 | 3097 | static void gen8_irq_reset(struct drm_device *dev) |
abd58f01 BW |
3098 | { |
3099 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3100 | int pipe; | |
3101 | ||
abd58f01 BW |
3102 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
3103 | POSTING_READ(GEN8_MASTER_IRQ); | |
3104 | ||
f86f3fb0 PZ |
3105 | GEN8_IRQ_RESET_NDX(GT, 0); |
3106 | GEN8_IRQ_RESET_NDX(GT, 1); | |
3107 | GEN8_IRQ_RESET_NDX(GT, 2); | |
3108 | GEN8_IRQ_RESET_NDX(GT, 3); | |
abd58f01 | 3109 | |
823f6b38 | 3110 | for_each_pipe(pipe) |
f86f3fb0 | 3111 | GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); |
abd58f01 | 3112 | |
f86f3fb0 PZ |
3113 | GEN5_IRQ_RESET(GEN8_DE_PORT_); |
3114 | GEN5_IRQ_RESET(GEN8_DE_MISC_); | |
3115 | GEN5_IRQ_RESET(GEN8_PCU_); | |
abd58f01 | 3116 | |
1c69eb42 | 3117 | ibx_irq_reset(dev); |
abd58f01 | 3118 | } |
09f2344d | 3119 | |
823f6b38 PZ |
3120 | static void gen8_irq_preinstall(struct drm_device *dev) |
3121 | { | |
3122 | gen8_irq_reset(dev); | |
abd58f01 BW |
3123 | } |
3124 | ||
43f328d7 VS |
3125 | static void cherryview_irq_preinstall(struct drm_device *dev) |
3126 | { | |
3127 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3128 | int pipe; | |
3129 | ||
3130 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3131 | POSTING_READ(GEN8_MASTER_IRQ); | |
3132 | ||
3133 | GEN8_IRQ_RESET_NDX(GT, 0); | |
3134 | GEN8_IRQ_RESET_NDX(GT, 1); | |
3135 | GEN8_IRQ_RESET_NDX(GT, 2); | |
3136 | GEN8_IRQ_RESET_NDX(GT, 3); | |
3137 | ||
3138 | GEN5_IRQ_RESET(GEN8_PCU_); | |
3139 | ||
3140 | POSTING_READ(GEN8_PCU_IIR); | |
3141 | ||
3142 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV); | |
3143 | ||
3144 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3145 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3146 | ||
3147 | for_each_pipe(pipe) | |
3148 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
3149 | ||
3150 | I915_WRITE(VLV_IMR, 0xffffffff); | |
3151 | I915_WRITE(VLV_IER, 0x0); | |
3152 | I915_WRITE(VLV_IIR, 0xffffffff); | |
3153 | POSTING_READ(VLV_IIR); | |
3154 | } | |
3155 | ||
82a28bcf | 3156 | static void ibx_hpd_irq_setup(struct drm_device *dev) |
7fe0b973 | 3157 | { |
2d1013dd | 3158 | struct drm_i915_private *dev_priv = dev->dev_private; |
82a28bcf DV |
3159 | struct drm_mode_config *mode_config = &dev->mode_config; |
3160 | struct intel_encoder *intel_encoder; | |
fee884ed | 3161 | u32 hotplug_irqs, hotplug, enabled_irqs = 0; |
82a28bcf DV |
3162 | |
3163 | if (HAS_PCH_IBX(dev)) { | |
fee884ed | 3164 | hotplug_irqs = SDE_HOTPLUG_MASK; |
82a28bcf | 3165 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
cd569aed | 3166 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
fee884ed | 3167 | enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin]; |
82a28bcf | 3168 | } else { |
fee884ed | 3169 | hotplug_irqs = SDE_HOTPLUG_MASK_CPT; |
82a28bcf | 3170 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
cd569aed | 3171 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
fee884ed | 3172 | enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin]; |
82a28bcf | 3173 | } |
7fe0b973 | 3174 | |
fee884ed | 3175 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); |
82a28bcf DV |
3176 | |
3177 | /* | |
3178 | * Enable digital hotplug on the PCH, and configure the DP short pulse | |
3179 | * duration to 2ms (which is the minimum in the Display Port spec) | |
3180 | * | |
3181 | * This register is the same on all known PCH chips. | |
3182 | */ | |
7fe0b973 KP |
3183 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
3184 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); | |
3185 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; | |
3186 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; | |
3187 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; | |
3188 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); | |
3189 | } | |
3190 | ||
d46da437 PZ |
3191 | static void ibx_irq_postinstall(struct drm_device *dev) |
3192 | { | |
2d1013dd | 3193 | struct drm_i915_private *dev_priv = dev->dev_private; |
82a28bcf | 3194 | u32 mask; |
e5868a31 | 3195 | |
692a04cf DV |
3196 | if (HAS_PCH_NOP(dev)) |
3197 | return; | |
3198 | ||
105b122e | 3199 | if (HAS_PCH_IBX(dev)) |
5c673b60 | 3200 | mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; |
105b122e | 3201 | else |
5c673b60 | 3202 | mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; |
8664281b | 3203 | |
337ba017 | 3204 | GEN5_ASSERT_IIR_IS_ZERO(SDEIIR); |
d46da437 | 3205 | I915_WRITE(SDEIMR, ~mask); |
d46da437 PZ |
3206 | } |
3207 | ||
0a9a8c91 DV |
3208 | static void gen5_gt_irq_postinstall(struct drm_device *dev) |
3209 | { | |
3210 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3211 | u32 pm_irqs, gt_irqs; | |
3212 | ||
3213 | pm_irqs = gt_irqs = 0; | |
3214 | ||
3215 | dev_priv->gt_irq_mask = ~0; | |
040d2baa | 3216 | if (HAS_L3_DPF(dev)) { |
0a9a8c91 | 3217 | /* L3 parity interrupt is always unmasked. */ |
35a85ac6 BW |
3218 | dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev); |
3219 | gt_irqs |= GT_PARITY_ERROR(dev); | |
0a9a8c91 DV |
3220 | } |
3221 | ||
3222 | gt_irqs |= GT_RENDER_USER_INTERRUPT; | |
3223 | if (IS_GEN5(dev)) { | |
3224 | gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | | |
3225 | ILK_BSD_USER_INTERRUPT; | |
3226 | } else { | |
3227 | gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; | |
3228 | } | |
3229 | ||
35079899 | 3230 | GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); |
0a9a8c91 DV |
3231 | |
3232 | if (INTEL_INFO(dev)->gen >= 6) { | |
a6706b45 | 3233 | pm_irqs |= dev_priv->pm_rps_events; |
0a9a8c91 DV |
3234 | |
3235 | if (HAS_VEBOX(dev)) | |
3236 | pm_irqs |= PM_VEBOX_USER_INTERRUPT; | |
3237 | ||
605cd25b | 3238 | dev_priv->pm_irq_mask = 0xffffffff; |
35079899 | 3239 | GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs); |
0a9a8c91 DV |
3240 | } |
3241 | } | |
3242 | ||
f71d4af4 | 3243 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d | 3244 | { |
4bc9d430 | 3245 | unsigned long irqflags; |
2d1013dd | 3246 | struct drm_i915_private *dev_priv = dev->dev_private; |
8e76f8dc PZ |
3247 | u32 display_mask, extra_mask; |
3248 | ||
3249 | if (INTEL_INFO(dev)->gen >= 7) { | |
3250 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | | |
3251 | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | | |
3252 | DE_PLANEB_FLIP_DONE_IVB | | |
5c673b60 | 3253 | DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB); |
8e76f8dc | 3254 | extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | |
5c673b60 | 3255 | DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB); |
8e76f8dc PZ |
3256 | } else { |
3257 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | | |
3258 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | | |
5b3a856b | 3259 | DE_AUX_CHANNEL_A | |
5b3a856b DV |
3260 | DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE | |
3261 | DE_POISON); | |
5c673b60 DV |
3262 | extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT | |
3263 | DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN; | |
8e76f8dc | 3264 | } |
036a4a7d | 3265 | |
1ec14ad3 | 3266 | dev_priv->irq_mask = ~display_mask; |
036a4a7d | 3267 | |
0c841212 PZ |
3268 | I915_WRITE(HWSTAM, 0xeffe); |
3269 | ||
622364b6 PZ |
3270 | ibx_irq_pre_postinstall(dev); |
3271 | ||
35079899 | 3272 | GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); |
036a4a7d | 3273 | |
0a9a8c91 | 3274 | gen5_gt_irq_postinstall(dev); |
036a4a7d | 3275 | |
d46da437 | 3276 | ibx_irq_postinstall(dev); |
7fe0b973 | 3277 | |
f97108d1 | 3278 | if (IS_IRONLAKE_M(dev)) { |
6005ce42 DV |
3279 | /* Enable PCU event interrupts |
3280 | * | |
3281 | * spinlocking not required here for correctness since interrupt | |
4bc9d430 DV |
3282 | * setup is guaranteed to run in single-threaded context. But we |
3283 | * need it to make the assert_spin_locked happy. */ | |
3284 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
f97108d1 | 3285 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); |
4bc9d430 | 3286 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
f97108d1 JB |
3287 | } |
3288 | ||
036a4a7d ZW |
3289 | return 0; |
3290 | } | |
3291 | ||
f8b79e58 ID |
3292 | static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv) |
3293 | { | |
3294 | u32 pipestat_mask; | |
3295 | u32 iir_mask; | |
3296 | ||
3297 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | | |
3298 | PIPE_FIFO_UNDERRUN_STATUS; | |
3299 | ||
3300 | I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask); | |
3301 | I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask); | |
3302 | POSTING_READ(PIPESTAT(PIPE_A)); | |
3303 | ||
3304 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3305 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3306 | ||
3307 | i915_enable_pipestat(dev_priv, PIPE_A, pipestat_mask | | |
3308 | PIPE_GMBUS_INTERRUPT_STATUS); | |
3309 | i915_enable_pipestat(dev_priv, PIPE_B, pipestat_mask); | |
3310 | ||
3311 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3312 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3313 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
3314 | dev_priv->irq_mask &= ~iir_mask; | |
3315 | ||
3316 | I915_WRITE(VLV_IIR, iir_mask); | |
3317 | I915_WRITE(VLV_IIR, iir_mask); | |
3318 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); | |
3319 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); | |
3320 | POSTING_READ(VLV_IER); | |
3321 | } | |
3322 | ||
3323 | static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv) | |
3324 | { | |
3325 | u32 pipestat_mask; | |
3326 | u32 iir_mask; | |
3327 | ||
3328 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3329 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
6c7fba04 | 3330 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; |
f8b79e58 ID |
3331 | |
3332 | dev_priv->irq_mask |= iir_mask; | |
3333 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); | |
3334 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); | |
3335 | I915_WRITE(VLV_IIR, iir_mask); | |
3336 | I915_WRITE(VLV_IIR, iir_mask); | |
3337 | POSTING_READ(VLV_IIR); | |
3338 | ||
3339 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3340 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3341 | ||
3342 | i915_disable_pipestat(dev_priv, PIPE_A, pipestat_mask | | |
3343 | PIPE_GMBUS_INTERRUPT_STATUS); | |
3344 | i915_disable_pipestat(dev_priv, PIPE_B, pipestat_mask); | |
3345 | ||
3346 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | | |
3347 | PIPE_FIFO_UNDERRUN_STATUS; | |
3348 | I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask); | |
3349 | I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask); | |
3350 | POSTING_READ(PIPESTAT(PIPE_A)); | |
3351 | } | |
3352 | ||
3353 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) | |
3354 | { | |
3355 | assert_spin_locked(&dev_priv->irq_lock); | |
3356 | ||
3357 | if (dev_priv->display_irqs_enabled) | |
3358 | return; | |
3359 | ||
3360 | dev_priv->display_irqs_enabled = true; | |
3361 | ||
3362 | if (dev_priv->dev->irq_enabled) | |
3363 | valleyview_display_irqs_install(dev_priv); | |
3364 | } | |
3365 | ||
3366 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) | |
3367 | { | |
3368 | assert_spin_locked(&dev_priv->irq_lock); | |
3369 | ||
3370 | if (!dev_priv->display_irqs_enabled) | |
3371 | return; | |
3372 | ||
3373 | dev_priv->display_irqs_enabled = false; | |
3374 | ||
3375 | if (dev_priv->dev->irq_enabled) | |
3376 | valleyview_display_irqs_uninstall(dev_priv); | |
3377 | } | |
3378 | ||
7e231dbe JB |
3379 | static int valleyview_irq_postinstall(struct drm_device *dev) |
3380 | { | |
2d1013dd | 3381 | struct drm_i915_private *dev_priv = dev->dev_private; |
b79480ba | 3382 | unsigned long irqflags; |
7e231dbe | 3383 | |
f8b79e58 | 3384 | dev_priv->irq_mask = ~0; |
7e231dbe | 3385 | |
20afbda2 DV |
3386 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3387 | POSTING_READ(PORT_HOTPLUG_EN); | |
3388 | ||
7e231dbe | 3389 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
f8b79e58 | 3390 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); |
7e231dbe | 3391 | I915_WRITE(VLV_IIR, 0xffffffff); |
7e231dbe JB |
3392 | POSTING_READ(VLV_IER); |
3393 | ||
b79480ba DV |
3394 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3395 | * just to make the assert_spin_locked check happy. */ | |
3396 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
f8b79e58 ID |
3397 | if (dev_priv->display_irqs_enabled) |
3398 | valleyview_display_irqs_install(dev_priv); | |
b79480ba | 3399 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
31acc7f5 | 3400 | |
7e231dbe JB |
3401 | I915_WRITE(VLV_IIR, 0xffffffff); |
3402 | I915_WRITE(VLV_IIR, 0xffffffff); | |
3403 | ||
0a9a8c91 | 3404 | gen5_gt_irq_postinstall(dev); |
7e231dbe JB |
3405 | |
3406 | /* ack & enable invalid PTE error interrupts */ | |
3407 | #if 0 /* FIXME: add support to irq handler for checking these bits */ | |
3408 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); | |
3409 | I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); | |
3410 | #endif | |
3411 | ||
3412 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); | |
20afbda2 DV |
3413 | |
3414 | return 0; | |
3415 | } | |
3416 | ||
abd58f01 BW |
3417 | static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) |
3418 | { | |
3419 | int i; | |
3420 | ||
3421 | /* These are interrupts we'll toggle with the ring mask register */ | |
3422 | uint32_t gt_interrupts[] = { | |
3423 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | | |
3424 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT | | |
3425 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT, | |
3426 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | | |
3427 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT, | |
3428 | 0, | |
3429 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
3430 | }; | |
3431 | ||
337ba017 | 3432 | for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) |
35079899 | 3433 | GEN8_IRQ_INIT_NDX(GT, i, ~gt_interrupts[i], gt_interrupts[i]); |
0961021a BW |
3434 | |
3435 | dev_priv->pm_irq_mask = 0xffffffff; | |
abd58f01 BW |
3436 | } |
3437 | ||
3438 | static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) | |
3439 | { | |
3440 | struct drm_device *dev = dev_priv->dev; | |
d0e1f1cb | 3441 | uint32_t de_pipe_masked = GEN8_PIPE_PRIMARY_FLIP_DONE | |
13b3a0a7 | 3442 | GEN8_PIPE_CDCLK_CRC_DONE | |
13b3a0a7 | 3443 | GEN8_DE_PIPE_IRQ_FAULT_ERRORS; |
5c673b60 DV |
3444 | uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | |
3445 | GEN8_PIPE_FIFO_UNDERRUN; | |
abd58f01 | 3446 | int pipe; |
13b3a0a7 DV |
3447 | dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; |
3448 | dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; | |
3449 | dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; | |
abd58f01 | 3450 | |
337ba017 | 3451 | for_each_pipe(pipe) |
35079899 PZ |
3452 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, dev_priv->de_irq_mask[pipe], |
3453 | de_pipe_enables); | |
abd58f01 | 3454 | |
35079899 | 3455 | GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A); |
abd58f01 BW |
3456 | } |
3457 | ||
3458 | static int gen8_irq_postinstall(struct drm_device *dev) | |
3459 | { | |
3460 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3461 | ||
622364b6 PZ |
3462 | ibx_irq_pre_postinstall(dev); |
3463 | ||
abd58f01 BW |
3464 | gen8_gt_irq_postinstall(dev_priv); |
3465 | gen8_de_irq_postinstall(dev_priv); | |
3466 | ||
3467 | ibx_irq_postinstall(dev); | |
3468 | ||
3469 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); | |
3470 | POSTING_READ(GEN8_MASTER_IRQ); | |
3471 | ||
3472 | return 0; | |
3473 | } | |
3474 | ||
43f328d7 VS |
3475 | static int cherryview_irq_postinstall(struct drm_device *dev) |
3476 | { | |
3477 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3478 | u32 enable_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3479 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
43f328d7 | 3480 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
3278f67f VS |
3481 | I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; |
3482 | u32 pipestat_enable = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3483 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
43f328d7 VS |
3484 | unsigned long irqflags; |
3485 | int pipe; | |
3486 | ||
3487 | /* | |
3488 | * Leave vblank interrupts masked initially. enable/disable will | |
3489 | * toggle them based on usage. | |
3490 | */ | |
3278f67f | 3491 | dev_priv->irq_mask = ~enable_mask; |
43f328d7 VS |
3492 | |
3493 | for_each_pipe(pipe) | |
3494 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
3495 | ||
3496 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3278f67f | 3497 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
43f328d7 VS |
3498 | for_each_pipe(pipe) |
3499 | i915_enable_pipestat(dev_priv, pipe, pipestat_enable); | |
3500 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3501 | ||
3502 | I915_WRITE(VLV_IIR, 0xffffffff); | |
3503 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); | |
3504 | I915_WRITE(VLV_IER, enable_mask); | |
3505 | ||
3506 | gen8_gt_irq_postinstall(dev_priv); | |
3507 | ||
3508 | I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE); | |
3509 | POSTING_READ(GEN8_MASTER_IRQ); | |
3510 | ||
3511 | return 0; | |
3512 | } | |
3513 | ||
abd58f01 BW |
3514 | static void gen8_irq_uninstall(struct drm_device *dev) |
3515 | { | |
3516 | struct drm_i915_private *dev_priv = dev->dev_private; | |
abd58f01 BW |
3517 | |
3518 | if (!dev_priv) | |
3519 | return; | |
3520 | ||
d4eb6b10 | 3521 | intel_hpd_irq_uninstall(dev_priv); |
abd58f01 | 3522 | |
823f6b38 | 3523 | gen8_irq_reset(dev); |
abd58f01 BW |
3524 | } |
3525 | ||
7e231dbe JB |
3526 | static void valleyview_irq_uninstall(struct drm_device *dev) |
3527 | { | |
2d1013dd | 3528 | struct drm_i915_private *dev_priv = dev->dev_private; |
f8b79e58 | 3529 | unsigned long irqflags; |
7e231dbe JB |
3530 | int pipe; |
3531 | ||
3532 | if (!dev_priv) | |
3533 | return; | |
3534 | ||
843d0e7d ID |
3535 | I915_WRITE(VLV_MASTER_IER, 0); |
3536 | ||
3ca1cced | 3537 | intel_hpd_irq_uninstall(dev_priv); |
ac4c16c5 | 3538 | |
7e231dbe JB |
3539 | for_each_pipe(pipe) |
3540 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
3541 | ||
3542 | I915_WRITE(HWSTAM, 0xffffffff); | |
3543 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3544 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
f8b79e58 ID |
3545 | |
3546 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3547 | if (dev_priv->display_irqs_enabled) | |
3548 | valleyview_display_irqs_uninstall(dev_priv); | |
3549 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3550 | ||
3551 | dev_priv->irq_mask = 0; | |
3552 | ||
7e231dbe JB |
3553 | I915_WRITE(VLV_IIR, 0xffffffff); |
3554 | I915_WRITE(VLV_IMR, 0xffffffff); | |
3555 | I915_WRITE(VLV_IER, 0x0); | |
3556 | POSTING_READ(VLV_IER); | |
3557 | } | |
3558 | ||
43f328d7 VS |
3559 | static void cherryview_irq_uninstall(struct drm_device *dev) |
3560 | { | |
3561 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3562 | int pipe; | |
3563 | ||
3564 | if (!dev_priv) | |
3565 | return; | |
3566 | ||
3567 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3568 | POSTING_READ(GEN8_MASTER_IRQ); | |
3569 | ||
3570 | #define GEN8_IRQ_FINI_NDX(type, which) \ | |
3571 | do { \ | |
3572 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ | |
3573 | I915_WRITE(GEN8_##type##_IER(which), 0); \ | |
3574 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
3575 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
3576 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
3577 | } while (0) | |
3578 | ||
3579 | #define GEN8_IRQ_FINI(type) \ | |
3580 | do { \ | |
3581 | I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \ | |
3582 | I915_WRITE(GEN8_##type##_IER, 0); \ | |
3583 | I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ | |
3584 | POSTING_READ(GEN8_##type##_IIR); \ | |
3585 | I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ | |
3586 | } while (0) | |
3587 | ||
3588 | GEN8_IRQ_FINI_NDX(GT, 0); | |
3589 | GEN8_IRQ_FINI_NDX(GT, 1); | |
3590 | GEN8_IRQ_FINI_NDX(GT, 2); | |
3591 | GEN8_IRQ_FINI_NDX(GT, 3); | |
3592 | ||
3593 | GEN8_IRQ_FINI(PCU); | |
3594 | ||
3595 | #undef GEN8_IRQ_FINI | |
3596 | #undef GEN8_IRQ_FINI_NDX | |
3597 | ||
3598 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3599 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3600 | ||
3601 | for_each_pipe(pipe) | |
3602 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
3603 | ||
3604 | I915_WRITE(VLV_IMR, 0xffffffff); | |
3605 | I915_WRITE(VLV_IER, 0x0); | |
3606 | I915_WRITE(VLV_IIR, 0xffffffff); | |
3607 | POSTING_READ(VLV_IIR); | |
3608 | } | |
3609 | ||
f71d4af4 | 3610 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d | 3611 | { |
2d1013dd | 3612 | struct drm_i915_private *dev_priv = dev->dev_private; |
4697995b JB |
3613 | |
3614 | if (!dev_priv) | |
3615 | return; | |
3616 | ||
3ca1cced | 3617 | intel_hpd_irq_uninstall(dev_priv); |
ac4c16c5 | 3618 | |
be30b29f | 3619 | ironlake_irq_reset(dev); |
036a4a7d ZW |
3620 | } |
3621 | ||
a266c7d5 | 3622 | static void i8xx_irq_preinstall(struct drm_device * dev) |
1da177e4 | 3623 | { |
2d1013dd | 3624 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 3625 | int pipe; |
91e3738e | 3626 | |
9db4a9c7 JB |
3627 | for_each_pipe(pipe) |
3628 | I915_WRITE(PIPESTAT(pipe), 0); | |
a266c7d5 CW |
3629 | I915_WRITE16(IMR, 0xffff); |
3630 | I915_WRITE16(IER, 0x0); | |
3631 | POSTING_READ16(IER); | |
c2798b19 CW |
3632 | } |
3633 | ||
3634 | static int i8xx_irq_postinstall(struct drm_device *dev) | |
3635 | { | |
2d1013dd | 3636 | struct drm_i915_private *dev_priv = dev->dev_private; |
379ef82d | 3637 | unsigned long irqflags; |
c2798b19 | 3638 | |
c2798b19 CW |
3639 | I915_WRITE16(EMR, |
3640 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); | |
3641 | ||
3642 | /* Unmask the interrupts that we always want on. */ | |
3643 | dev_priv->irq_mask = | |
3644 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3645 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3646 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3647 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3648 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3649 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
3650 | ||
3651 | I915_WRITE16(IER, | |
3652 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3653 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3654 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
3655 | I915_USER_INTERRUPT); | |
3656 | POSTING_READ16(IER); | |
3657 | ||
379ef82d DV |
3658 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3659 | * just to make the assert_spin_locked check happy. */ | |
3660 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
755e9019 ID |
3661 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3662 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
379ef82d DV |
3663 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
3664 | ||
c2798b19 CW |
3665 | return 0; |
3666 | } | |
3667 | ||
90a72f87 VS |
3668 | /* |
3669 | * Returns true when a page flip has completed. | |
3670 | */ | |
3671 | static bool i8xx_handle_vblank(struct drm_device *dev, | |
1f1c2e24 | 3672 | int plane, int pipe, u32 iir) |
90a72f87 | 3673 | { |
2d1013dd | 3674 | struct drm_i915_private *dev_priv = dev->dev_private; |
1f1c2e24 | 3675 | u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
90a72f87 | 3676 | |
8d7849db | 3677 | if (!intel_pipe_handle_vblank(dev, pipe)) |
90a72f87 VS |
3678 | return false; |
3679 | ||
3680 | if ((iir & flip_pending) == 0) | |
3681 | return false; | |
3682 | ||
1f1c2e24 | 3683 | intel_prepare_page_flip(dev, plane); |
90a72f87 VS |
3684 | |
3685 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
3686 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3687 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3688 | * the flip is completed (no longer pending). Since this doesn't raise | |
3689 | * an interrupt per se, we watch for the change at vblank. | |
3690 | */ | |
3691 | if (I915_READ16(ISR) & flip_pending) | |
3692 | return false; | |
3693 | ||
3694 | intel_finish_page_flip(dev, pipe); | |
3695 | ||
3696 | return true; | |
3697 | } | |
3698 | ||
ff1f525e | 3699 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
c2798b19 | 3700 | { |
45a83f84 | 3701 | struct drm_device *dev = arg; |
2d1013dd | 3702 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
3703 | u16 iir, new_iir; |
3704 | u32 pipe_stats[2]; | |
3705 | unsigned long irqflags; | |
c2798b19 CW |
3706 | int pipe; |
3707 | u16 flip_mask = | |
3708 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3709 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
3710 | ||
c2798b19 CW |
3711 | iir = I915_READ16(IIR); |
3712 | if (iir == 0) | |
3713 | return IRQ_NONE; | |
3714 | ||
3715 | while (iir & ~flip_mask) { | |
3716 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3717 | * have been cleared after the pipestat interrupt was received. | |
3718 | * It doesn't set the bit in iir again, but it still produces | |
3719 | * interrupts (for non-MSI). | |
3720 | */ | |
3721 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3722 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
58174462 MK |
3723 | i915_handle_error(dev, false, |
3724 | "Command parser error, iir 0x%08x", | |
3725 | iir); | |
c2798b19 CW |
3726 | |
3727 | for_each_pipe(pipe) { | |
3728 | int reg = PIPESTAT(pipe); | |
3729 | pipe_stats[pipe] = I915_READ(reg); | |
3730 | ||
3731 | /* | |
3732 | * Clear the PIPE*STAT regs before the IIR | |
3733 | */ | |
2d9d2b0b | 3734 | if (pipe_stats[pipe] & 0x8000ffff) |
c2798b19 | 3735 | I915_WRITE(reg, pipe_stats[pipe]); |
c2798b19 CW |
3736 | } |
3737 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3738 | ||
3739 | I915_WRITE16(IIR, iir & ~flip_mask); | |
3740 | new_iir = I915_READ16(IIR); /* Flush posted writes */ | |
3741 | ||
d05c617e | 3742 | i915_update_dri1_breadcrumb(dev); |
c2798b19 CW |
3743 | |
3744 | if (iir & I915_USER_INTERRUPT) | |
3745 | notify_ring(dev, &dev_priv->ring[RCS]); | |
3746 | ||
4356d586 | 3747 | for_each_pipe(pipe) { |
1f1c2e24 | 3748 | int plane = pipe; |
3a77c4c4 | 3749 | if (HAS_FBC(dev)) |
1f1c2e24 VS |
3750 | plane = !plane; |
3751 | ||
4356d586 | 3752 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
1f1c2e24 VS |
3753 | i8xx_handle_vblank(dev, plane, pipe, iir)) |
3754 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
c2798b19 | 3755 | |
4356d586 | 3756 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
277de95e | 3757 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b VS |
3758 | |
3759 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && | |
3760 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
fc2c807b | 3761 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); |
4356d586 | 3762 | } |
c2798b19 CW |
3763 | |
3764 | iir = new_iir; | |
3765 | } | |
3766 | ||
3767 | return IRQ_HANDLED; | |
3768 | } | |
3769 | ||
3770 | static void i8xx_irq_uninstall(struct drm_device * dev) | |
3771 | { | |
2d1013dd | 3772 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
3773 | int pipe; |
3774 | ||
c2798b19 CW |
3775 | for_each_pipe(pipe) { |
3776 | /* Clear enable bits; then clear status bits */ | |
3777 | I915_WRITE(PIPESTAT(pipe), 0); | |
3778 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); | |
3779 | } | |
3780 | I915_WRITE16(IMR, 0xffff); | |
3781 | I915_WRITE16(IER, 0x0); | |
3782 | I915_WRITE16(IIR, I915_READ16(IIR)); | |
3783 | } | |
3784 | ||
a266c7d5 CW |
3785 | static void i915_irq_preinstall(struct drm_device * dev) |
3786 | { | |
2d1013dd | 3787 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3788 | int pipe; |
3789 | ||
a266c7d5 CW |
3790 | if (I915_HAS_HOTPLUG(dev)) { |
3791 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3792 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3793 | } | |
3794 | ||
00d98ebd | 3795 | I915_WRITE16(HWSTAM, 0xeffe); |
a266c7d5 CW |
3796 | for_each_pipe(pipe) |
3797 | I915_WRITE(PIPESTAT(pipe), 0); | |
3798 | I915_WRITE(IMR, 0xffffffff); | |
3799 | I915_WRITE(IER, 0x0); | |
3800 | POSTING_READ(IER); | |
3801 | } | |
3802 | ||
3803 | static int i915_irq_postinstall(struct drm_device *dev) | |
3804 | { | |
2d1013dd | 3805 | struct drm_i915_private *dev_priv = dev->dev_private; |
38bde180 | 3806 | u32 enable_mask; |
379ef82d | 3807 | unsigned long irqflags; |
a266c7d5 | 3808 | |
38bde180 CW |
3809 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
3810 | ||
3811 | /* Unmask the interrupts that we always want on. */ | |
3812 | dev_priv->irq_mask = | |
3813 | ~(I915_ASLE_INTERRUPT | | |
3814 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3815 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3816 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3817 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3818 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3819 | ||
3820 | enable_mask = | |
3821 | I915_ASLE_INTERRUPT | | |
3822 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3823 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3824 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
3825 | I915_USER_INTERRUPT; | |
3826 | ||
a266c7d5 | 3827 | if (I915_HAS_HOTPLUG(dev)) { |
20afbda2 DV |
3828 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3829 | POSTING_READ(PORT_HOTPLUG_EN); | |
3830 | ||
a266c7d5 CW |
3831 | /* Enable in IER... */ |
3832 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
3833 | /* and unmask in IMR */ | |
3834 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; | |
3835 | } | |
3836 | ||
a266c7d5 CW |
3837 | I915_WRITE(IMR, dev_priv->irq_mask); |
3838 | I915_WRITE(IER, enable_mask); | |
3839 | POSTING_READ(IER); | |
3840 | ||
f49e38dd | 3841 | i915_enable_asle_pipestat(dev); |
20afbda2 | 3842 | |
379ef82d DV |
3843 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3844 | * just to make the assert_spin_locked check happy. */ | |
3845 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
755e9019 ID |
3846 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3847 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
379ef82d DV |
3848 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
3849 | ||
20afbda2 DV |
3850 | return 0; |
3851 | } | |
3852 | ||
90a72f87 VS |
3853 | /* |
3854 | * Returns true when a page flip has completed. | |
3855 | */ | |
3856 | static bool i915_handle_vblank(struct drm_device *dev, | |
3857 | int plane, int pipe, u32 iir) | |
3858 | { | |
2d1013dd | 3859 | struct drm_i915_private *dev_priv = dev->dev_private; |
90a72f87 VS |
3860 | u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
3861 | ||
8d7849db | 3862 | if (!intel_pipe_handle_vblank(dev, pipe)) |
90a72f87 VS |
3863 | return false; |
3864 | ||
3865 | if ((iir & flip_pending) == 0) | |
3866 | return false; | |
3867 | ||
3868 | intel_prepare_page_flip(dev, plane); | |
3869 | ||
3870 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
3871 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3872 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3873 | * the flip is completed (no longer pending). Since this doesn't raise | |
3874 | * an interrupt per se, we watch for the change at vblank. | |
3875 | */ | |
3876 | if (I915_READ(ISR) & flip_pending) | |
3877 | return false; | |
3878 | ||
3879 | intel_finish_page_flip(dev, pipe); | |
3880 | ||
3881 | return true; | |
3882 | } | |
3883 | ||
ff1f525e | 3884 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
a266c7d5 | 3885 | { |
45a83f84 | 3886 | struct drm_device *dev = arg; |
2d1013dd | 3887 | struct drm_i915_private *dev_priv = dev->dev_private; |
8291ee90 | 3888 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
a266c7d5 | 3889 | unsigned long irqflags; |
38bde180 CW |
3890 | u32 flip_mask = |
3891 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3892 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
38bde180 | 3893 | int pipe, ret = IRQ_NONE; |
a266c7d5 | 3894 | |
a266c7d5 | 3895 | iir = I915_READ(IIR); |
38bde180 CW |
3896 | do { |
3897 | bool irq_received = (iir & ~flip_mask) != 0; | |
8291ee90 | 3898 | bool blc_event = false; |
a266c7d5 CW |
3899 | |
3900 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3901 | * have been cleared after the pipestat interrupt was received. | |
3902 | * It doesn't set the bit in iir again, but it still produces | |
3903 | * interrupts (for non-MSI). | |
3904 | */ | |
3905 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3906 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
58174462 MK |
3907 | i915_handle_error(dev, false, |
3908 | "Command parser error, iir 0x%08x", | |
3909 | iir); | |
a266c7d5 CW |
3910 | |
3911 | for_each_pipe(pipe) { | |
3912 | int reg = PIPESTAT(pipe); | |
3913 | pipe_stats[pipe] = I915_READ(reg); | |
3914 | ||
38bde180 | 3915 | /* Clear the PIPE*STAT regs before the IIR */ |
a266c7d5 | 3916 | if (pipe_stats[pipe] & 0x8000ffff) { |
a266c7d5 | 3917 | I915_WRITE(reg, pipe_stats[pipe]); |
38bde180 | 3918 | irq_received = true; |
a266c7d5 CW |
3919 | } |
3920 | } | |
3921 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3922 | ||
3923 | if (!irq_received) | |
3924 | break; | |
3925 | ||
a266c7d5 | 3926 | /* Consume port. Then clear IIR or we'll miss events */ |
16c6c56b VS |
3927 | if (I915_HAS_HOTPLUG(dev) && |
3928 | iir & I915_DISPLAY_PORT_INTERRUPT) | |
3929 | i9xx_hpd_irq_handler(dev); | |
a266c7d5 | 3930 | |
38bde180 | 3931 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
3932 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
3933 | ||
a266c7d5 CW |
3934 | if (iir & I915_USER_INTERRUPT) |
3935 | notify_ring(dev, &dev_priv->ring[RCS]); | |
a266c7d5 | 3936 | |
a266c7d5 | 3937 | for_each_pipe(pipe) { |
38bde180 | 3938 | int plane = pipe; |
3a77c4c4 | 3939 | if (HAS_FBC(dev)) |
38bde180 | 3940 | plane = !plane; |
90a72f87 | 3941 | |
8291ee90 | 3942 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
3943 | i915_handle_vblank(dev, plane, pipe, iir)) |
3944 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
a266c7d5 CW |
3945 | |
3946 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
3947 | blc_event = true; | |
4356d586 DV |
3948 | |
3949 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 3950 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b VS |
3951 | |
3952 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && | |
3953 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
fc2c807b | 3954 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); |
a266c7d5 CW |
3955 | } |
3956 | ||
a266c7d5 CW |
3957 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
3958 | intel_opregion_asle_intr(dev); | |
3959 | ||
3960 | /* With MSI, interrupts are only generated when iir | |
3961 | * transitions from zero to nonzero. If another bit got | |
3962 | * set while we were handling the existing iir bits, then | |
3963 | * we would never get another interrupt. | |
3964 | * | |
3965 | * This is fine on non-MSI as well, as if we hit this path | |
3966 | * we avoid exiting the interrupt handler only to generate | |
3967 | * another one. | |
3968 | * | |
3969 | * Note that for MSI this could cause a stray interrupt report | |
3970 | * if an interrupt landed in the time between writing IIR and | |
3971 | * the posting read. This should be rare enough to never | |
3972 | * trigger the 99% of 100,000 interrupts test for disabling | |
3973 | * stray interrupts. | |
3974 | */ | |
38bde180 | 3975 | ret = IRQ_HANDLED; |
a266c7d5 | 3976 | iir = new_iir; |
38bde180 | 3977 | } while (iir & ~flip_mask); |
a266c7d5 | 3978 | |
d05c617e | 3979 | i915_update_dri1_breadcrumb(dev); |
8291ee90 | 3980 | |
a266c7d5 CW |
3981 | return ret; |
3982 | } | |
3983 | ||
3984 | static void i915_irq_uninstall(struct drm_device * dev) | |
3985 | { | |
2d1013dd | 3986 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3987 | int pipe; |
3988 | ||
3ca1cced | 3989 | intel_hpd_irq_uninstall(dev_priv); |
ac4c16c5 | 3990 | |
a266c7d5 CW |
3991 | if (I915_HAS_HOTPLUG(dev)) { |
3992 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3993 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3994 | } | |
3995 | ||
00d98ebd | 3996 | I915_WRITE16(HWSTAM, 0xffff); |
55b39755 CW |
3997 | for_each_pipe(pipe) { |
3998 | /* Clear enable bits; then clear status bits */ | |
a266c7d5 | 3999 | I915_WRITE(PIPESTAT(pipe), 0); |
55b39755 CW |
4000 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
4001 | } | |
a266c7d5 CW |
4002 | I915_WRITE(IMR, 0xffffffff); |
4003 | I915_WRITE(IER, 0x0); | |
4004 | ||
a266c7d5 CW |
4005 | I915_WRITE(IIR, I915_READ(IIR)); |
4006 | } | |
4007 | ||
4008 | static void i965_irq_preinstall(struct drm_device * dev) | |
4009 | { | |
2d1013dd | 4010 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4011 | int pipe; |
4012 | ||
adca4730 CW |
4013 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
4014 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
4015 | |
4016 | I915_WRITE(HWSTAM, 0xeffe); | |
4017 | for_each_pipe(pipe) | |
4018 | I915_WRITE(PIPESTAT(pipe), 0); | |
4019 | I915_WRITE(IMR, 0xffffffff); | |
4020 | I915_WRITE(IER, 0x0); | |
4021 | POSTING_READ(IER); | |
4022 | } | |
4023 | ||
4024 | static int i965_irq_postinstall(struct drm_device *dev) | |
4025 | { | |
2d1013dd | 4026 | struct drm_i915_private *dev_priv = dev->dev_private; |
bbba0a97 | 4027 | u32 enable_mask; |
a266c7d5 | 4028 | u32 error_mask; |
b79480ba | 4029 | unsigned long irqflags; |
a266c7d5 | 4030 | |
a266c7d5 | 4031 | /* Unmask the interrupts that we always want on. */ |
bbba0a97 | 4032 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
adca4730 | 4033 | I915_DISPLAY_PORT_INTERRUPT | |
bbba0a97 CW |
4034 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
4035 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
4036 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4037 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
4038 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
4039 | ||
4040 | enable_mask = ~dev_priv->irq_mask; | |
21ad8330 VS |
4041 | enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
4042 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); | |
bbba0a97 CW |
4043 | enable_mask |= I915_USER_INTERRUPT; |
4044 | ||
4045 | if (IS_G4X(dev)) | |
4046 | enable_mask |= I915_BSD_USER_INTERRUPT; | |
a266c7d5 | 4047 | |
b79480ba DV |
4048 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
4049 | * just to make the assert_spin_locked check happy. */ | |
4050 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
755e9019 ID |
4051 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
4052 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
4053 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
b79480ba | 4054 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
a266c7d5 | 4055 | |
a266c7d5 CW |
4056 | /* |
4057 | * Enable some error detection, note the instruction error mask | |
4058 | * bit is reserved, so we leave it masked. | |
4059 | */ | |
4060 | if (IS_G4X(dev)) { | |
4061 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
4062 | GM45_ERROR_MEM_PRIV | | |
4063 | GM45_ERROR_CP_PRIV | | |
4064 | I915_ERROR_MEMORY_REFRESH); | |
4065 | } else { | |
4066 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
4067 | I915_ERROR_MEMORY_REFRESH); | |
4068 | } | |
4069 | I915_WRITE(EMR, error_mask); | |
4070 | ||
4071 | I915_WRITE(IMR, dev_priv->irq_mask); | |
4072 | I915_WRITE(IER, enable_mask); | |
4073 | POSTING_READ(IER); | |
4074 | ||
20afbda2 DV |
4075 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
4076 | POSTING_READ(PORT_HOTPLUG_EN); | |
4077 | ||
f49e38dd | 4078 | i915_enable_asle_pipestat(dev); |
20afbda2 DV |
4079 | |
4080 | return 0; | |
4081 | } | |
4082 | ||
bac56d5b | 4083 | static void i915_hpd_irq_setup(struct drm_device *dev) |
20afbda2 | 4084 | { |
2d1013dd | 4085 | struct drm_i915_private *dev_priv = dev->dev_private; |
e5868a31 | 4086 | struct drm_mode_config *mode_config = &dev->mode_config; |
cd569aed | 4087 | struct intel_encoder *intel_encoder; |
20afbda2 DV |
4088 | u32 hotplug_en; |
4089 | ||
b5ea2d56 DV |
4090 | assert_spin_locked(&dev_priv->irq_lock); |
4091 | ||
bac56d5b EE |
4092 | if (I915_HAS_HOTPLUG(dev)) { |
4093 | hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
4094 | hotplug_en &= ~HOTPLUG_INT_EN_MASK; | |
4095 | /* Note HDMI and DP share hotplug bits */ | |
e5868a31 | 4096 | /* enable bits are the same for all generations */ |
cd569aed EE |
4097 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
4098 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) | |
4099 | hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin]; | |
bac56d5b EE |
4100 | /* Programming the CRT detection parameters tends |
4101 | to generate a spurious hotplug event about three | |
4102 | seconds later. So just do it once. | |
4103 | */ | |
4104 | if (IS_G4X(dev)) | |
4105 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
85fc95ba | 4106 | hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK; |
bac56d5b | 4107 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
a266c7d5 | 4108 | |
bac56d5b EE |
4109 | /* Ignore TV since it's buggy */ |
4110 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
4111 | } | |
a266c7d5 CW |
4112 | } |
4113 | ||
ff1f525e | 4114 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
a266c7d5 | 4115 | { |
45a83f84 | 4116 | struct drm_device *dev = arg; |
2d1013dd | 4117 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4118 | u32 iir, new_iir; |
4119 | u32 pipe_stats[I915_MAX_PIPES]; | |
a266c7d5 | 4120 | unsigned long irqflags; |
a266c7d5 | 4121 | int ret = IRQ_NONE, pipe; |
21ad8330 VS |
4122 | u32 flip_mask = |
4123 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4124 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
a266c7d5 | 4125 | |
a266c7d5 CW |
4126 | iir = I915_READ(IIR); |
4127 | ||
a266c7d5 | 4128 | for (;;) { |
501e01d7 | 4129 | bool irq_received = (iir & ~flip_mask) != 0; |
2c8ba29f CW |
4130 | bool blc_event = false; |
4131 | ||
a266c7d5 CW |
4132 | /* Can't rely on pipestat interrupt bit in iir as it might |
4133 | * have been cleared after the pipestat interrupt was received. | |
4134 | * It doesn't set the bit in iir again, but it still produces | |
4135 | * interrupts (for non-MSI). | |
4136 | */ | |
4137 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
4138 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
58174462 MK |
4139 | i915_handle_error(dev, false, |
4140 | "Command parser error, iir 0x%08x", | |
4141 | iir); | |
a266c7d5 CW |
4142 | |
4143 | for_each_pipe(pipe) { | |
4144 | int reg = PIPESTAT(pipe); | |
4145 | pipe_stats[pipe] = I915_READ(reg); | |
4146 | ||
4147 | /* | |
4148 | * Clear the PIPE*STAT regs before the IIR | |
4149 | */ | |
4150 | if (pipe_stats[pipe] & 0x8000ffff) { | |
a266c7d5 | 4151 | I915_WRITE(reg, pipe_stats[pipe]); |
501e01d7 | 4152 | irq_received = true; |
a266c7d5 CW |
4153 | } |
4154 | } | |
4155 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
4156 | ||
4157 | if (!irq_received) | |
4158 | break; | |
4159 | ||
4160 | ret = IRQ_HANDLED; | |
4161 | ||
4162 | /* Consume port. Then clear IIR or we'll miss events */ | |
16c6c56b VS |
4163 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
4164 | i9xx_hpd_irq_handler(dev); | |
a266c7d5 | 4165 | |
21ad8330 | 4166 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
4167 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
4168 | ||
a266c7d5 CW |
4169 | if (iir & I915_USER_INTERRUPT) |
4170 | notify_ring(dev, &dev_priv->ring[RCS]); | |
4171 | if (iir & I915_BSD_USER_INTERRUPT) | |
4172 | notify_ring(dev, &dev_priv->ring[VCS]); | |
4173 | ||
a266c7d5 | 4174 | for_each_pipe(pipe) { |
2c8ba29f | 4175 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
4176 | i915_handle_vblank(dev, pipe, pipe, iir)) |
4177 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); | |
a266c7d5 CW |
4178 | |
4179 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
4180 | blc_event = true; | |
4356d586 DV |
4181 | |
4182 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 4183 | i9xx_pipe_crc_irq_handler(dev, pipe); |
a266c7d5 | 4184 | |
2d9d2b0b VS |
4185 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && |
4186 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
fc2c807b | 4187 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); |
2d9d2b0b | 4188 | } |
a266c7d5 CW |
4189 | |
4190 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | |
4191 | intel_opregion_asle_intr(dev); | |
4192 | ||
515ac2bb DV |
4193 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
4194 | gmbus_irq_handler(dev); | |
4195 | ||
a266c7d5 CW |
4196 | /* With MSI, interrupts are only generated when iir |
4197 | * transitions from zero to nonzero. If another bit got | |
4198 | * set while we were handling the existing iir bits, then | |
4199 | * we would never get another interrupt. | |
4200 | * | |
4201 | * This is fine on non-MSI as well, as if we hit this path | |
4202 | * we avoid exiting the interrupt handler only to generate | |
4203 | * another one. | |
4204 | * | |
4205 | * Note that for MSI this could cause a stray interrupt report | |
4206 | * if an interrupt landed in the time between writing IIR and | |
4207 | * the posting read. This should be rare enough to never | |
4208 | * trigger the 99% of 100,000 interrupts test for disabling | |
4209 | * stray interrupts. | |
4210 | */ | |
4211 | iir = new_iir; | |
4212 | } | |
4213 | ||
d05c617e | 4214 | i915_update_dri1_breadcrumb(dev); |
2c8ba29f | 4215 | |
a266c7d5 CW |
4216 | return ret; |
4217 | } | |
4218 | ||
4219 | static void i965_irq_uninstall(struct drm_device * dev) | |
4220 | { | |
2d1013dd | 4221 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4222 | int pipe; |
4223 | ||
4224 | if (!dev_priv) | |
4225 | return; | |
4226 | ||
3ca1cced | 4227 | intel_hpd_irq_uninstall(dev_priv); |
ac4c16c5 | 4228 | |
adca4730 CW |
4229 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
4230 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
4231 | |
4232 | I915_WRITE(HWSTAM, 0xffffffff); | |
4233 | for_each_pipe(pipe) | |
4234 | I915_WRITE(PIPESTAT(pipe), 0); | |
4235 | I915_WRITE(IMR, 0xffffffff); | |
4236 | I915_WRITE(IER, 0x0); | |
4237 | ||
4238 | for_each_pipe(pipe) | |
4239 | I915_WRITE(PIPESTAT(pipe), | |
4240 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); | |
4241 | I915_WRITE(IIR, I915_READ(IIR)); | |
4242 | } | |
4243 | ||
3ca1cced | 4244 | static void intel_hpd_irq_reenable(unsigned long data) |
ac4c16c5 | 4245 | { |
2d1013dd | 4246 | struct drm_i915_private *dev_priv = (struct drm_i915_private *)data; |
ac4c16c5 EE |
4247 | struct drm_device *dev = dev_priv->dev; |
4248 | struct drm_mode_config *mode_config = &dev->mode_config; | |
4249 | unsigned long irqflags; | |
4250 | int i; | |
4251 | ||
4252 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
4253 | for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) { | |
4254 | struct drm_connector *connector; | |
4255 | ||
4256 | if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED) | |
4257 | continue; | |
4258 | ||
4259 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
4260 | ||
4261 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
4262 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4263 | ||
4264 | if (intel_connector->encoder->hpd_pin == i) { | |
4265 | if (connector->polled != intel_connector->polled) | |
4266 | DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n", | |
4267 | drm_get_connector_name(connector)); | |
4268 | connector->polled = intel_connector->polled; | |
4269 | if (!connector->polled) | |
4270 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
4271 | } | |
4272 | } | |
4273 | } | |
4274 | if (dev_priv->display.hpd_irq_setup) | |
4275 | dev_priv->display.hpd_irq_setup(dev); | |
4276 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
4277 | } | |
4278 | ||
f71d4af4 JB |
4279 | void intel_irq_init(struct drm_device *dev) |
4280 | { | |
8b2e326d CW |
4281 | struct drm_i915_private *dev_priv = dev->dev_private; |
4282 | ||
4283 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); | |
99584db3 | 4284 | INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func); |
c6a828d3 | 4285 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
a4da4fa4 | 4286 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
8b2e326d | 4287 | |
a6706b45 D |
4288 | /* Let's track the enabled rps events */ |
4289 | dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; | |
4290 | ||
99584db3 DV |
4291 | setup_timer(&dev_priv->gpu_error.hangcheck_timer, |
4292 | i915_hangcheck_elapsed, | |
61bac78e | 4293 | (unsigned long) dev); |
3ca1cced | 4294 | setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable, |
ac4c16c5 | 4295 | (unsigned long) dev_priv); |
61bac78e | 4296 | |
97a19a24 | 4297 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); |
9ee32fea | 4298 | |
4cdb83ec VS |
4299 | if (IS_GEN2(dev)) { |
4300 | dev->max_vblank_count = 0; | |
4301 | dev->driver->get_vblank_counter = i8xx_get_vblank_counter; | |
4302 | } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { | |
f71d4af4 JB |
4303 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
4304 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; | |
391f75e2 VS |
4305 | } else { |
4306 | dev->driver->get_vblank_counter = i915_get_vblank_counter; | |
4307 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
f71d4af4 JB |
4308 | } |
4309 | ||
c2baf4b7 | 4310 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
c3613de9 | 4311 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; |
c2baf4b7 VS |
4312 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; |
4313 | } | |
f71d4af4 | 4314 | |
43f328d7 VS |
4315 | if (IS_CHERRYVIEW(dev)) { |
4316 | dev->driver->irq_handler = cherryview_irq_handler; | |
4317 | dev->driver->irq_preinstall = cherryview_irq_preinstall; | |
4318 | dev->driver->irq_postinstall = cherryview_irq_postinstall; | |
4319 | dev->driver->irq_uninstall = cherryview_irq_uninstall; | |
4320 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4321 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
4322 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; | |
4323 | } else if (IS_VALLEYVIEW(dev)) { | |
7e231dbe JB |
4324 | dev->driver->irq_handler = valleyview_irq_handler; |
4325 | dev->driver->irq_preinstall = valleyview_irq_preinstall; | |
4326 | dev->driver->irq_postinstall = valleyview_irq_postinstall; | |
4327 | dev->driver->irq_uninstall = valleyview_irq_uninstall; | |
4328 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4329 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
fa00abe0 | 4330 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
abd58f01 BW |
4331 | } else if (IS_GEN8(dev)) { |
4332 | dev->driver->irq_handler = gen8_irq_handler; | |
4333 | dev->driver->irq_preinstall = gen8_irq_preinstall; | |
4334 | dev->driver->irq_postinstall = gen8_irq_postinstall; | |
4335 | dev->driver->irq_uninstall = gen8_irq_uninstall; | |
4336 | dev->driver->enable_vblank = gen8_enable_vblank; | |
4337 | dev->driver->disable_vblank = gen8_disable_vblank; | |
4338 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; | |
f71d4af4 JB |
4339 | } else if (HAS_PCH_SPLIT(dev)) { |
4340 | dev->driver->irq_handler = ironlake_irq_handler; | |
4341 | dev->driver->irq_preinstall = ironlake_irq_preinstall; | |
4342 | dev->driver->irq_postinstall = ironlake_irq_postinstall; | |
4343 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
4344 | dev->driver->enable_vblank = ironlake_enable_vblank; | |
4345 | dev->driver->disable_vblank = ironlake_disable_vblank; | |
82a28bcf | 4346 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; |
f71d4af4 | 4347 | } else { |
c2798b19 CW |
4348 | if (INTEL_INFO(dev)->gen == 2) { |
4349 | dev->driver->irq_preinstall = i8xx_irq_preinstall; | |
4350 | dev->driver->irq_postinstall = i8xx_irq_postinstall; | |
4351 | dev->driver->irq_handler = i8xx_irq_handler; | |
4352 | dev->driver->irq_uninstall = i8xx_irq_uninstall; | |
a266c7d5 CW |
4353 | } else if (INTEL_INFO(dev)->gen == 3) { |
4354 | dev->driver->irq_preinstall = i915_irq_preinstall; | |
4355 | dev->driver->irq_postinstall = i915_irq_postinstall; | |
4356 | dev->driver->irq_uninstall = i915_irq_uninstall; | |
4357 | dev->driver->irq_handler = i915_irq_handler; | |
20afbda2 | 4358 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
c2798b19 | 4359 | } else { |
a266c7d5 CW |
4360 | dev->driver->irq_preinstall = i965_irq_preinstall; |
4361 | dev->driver->irq_postinstall = i965_irq_postinstall; | |
4362 | dev->driver->irq_uninstall = i965_irq_uninstall; | |
4363 | dev->driver->irq_handler = i965_irq_handler; | |
bac56d5b | 4364 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
c2798b19 | 4365 | } |
f71d4af4 JB |
4366 | dev->driver->enable_vblank = i915_enable_vblank; |
4367 | dev->driver->disable_vblank = i915_disable_vblank; | |
4368 | } | |
4369 | } | |
20afbda2 DV |
4370 | |
4371 | void intel_hpd_init(struct drm_device *dev) | |
4372 | { | |
4373 | struct drm_i915_private *dev_priv = dev->dev_private; | |
821450c6 EE |
4374 | struct drm_mode_config *mode_config = &dev->mode_config; |
4375 | struct drm_connector *connector; | |
b5ea2d56 | 4376 | unsigned long irqflags; |
821450c6 | 4377 | int i; |
20afbda2 | 4378 | |
821450c6 EE |
4379 | for (i = 1; i < HPD_NUM_PINS; i++) { |
4380 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
4381 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
4382 | } | |
4383 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
4384 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4385 | connector->polled = intel_connector->polled; | |
4386 | if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE) | |
4387 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
4388 | } | |
b5ea2d56 DV |
4389 | |
4390 | /* Interrupt setup is already guaranteed to be single-threaded, this is | |
4391 | * just to make the assert_spin_locked checks happy. */ | |
4392 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
20afbda2 DV |
4393 | if (dev_priv->display.hpd_irq_setup) |
4394 | dev_priv->display.hpd_irq_setup(dev); | |
b5ea2d56 | 4395 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
20afbda2 | 4396 | } |
c67a470b | 4397 | |
5d584b2e | 4398 | /* Disable interrupts so we can allow runtime PM. */ |
730488b2 | 4399 | void intel_runtime_pm_disable_interrupts(struct drm_device *dev) |
c67a470b PZ |
4400 | { |
4401 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c67a470b | 4402 | |
730488b2 | 4403 | dev->driver->irq_uninstall(dev); |
5d584b2e | 4404 | dev_priv->pm.irqs_disabled = true; |
c67a470b PZ |
4405 | } |
4406 | ||
5d584b2e | 4407 | /* Restore interrupts so we can recover from runtime PM. */ |
730488b2 | 4408 | void intel_runtime_pm_restore_interrupts(struct drm_device *dev) |
c67a470b PZ |
4409 | { |
4410 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c67a470b | 4411 | |
5d584b2e | 4412 | dev_priv->pm.irqs_disabled = false; |
730488b2 PZ |
4413 | dev->driver->irq_preinstall(dev); |
4414 | dev->driver->irq_postinstall(dev); | |
c67a470b | 4415 | } |