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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
63eeaf38 | 31 | #include <linux/sysrq.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
b2c88f5b | 33 | #include <linux/circ_buf.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/i915_drm.h> | |
1da177e4 | 36 | #include "i915_drv.h" |
1c5d22f7 | 37 | #include "i915_trace.h" |
79e53945 | 38 | #include "intel_drv.h" |
1da177e4 | 39 | |
e5868a31 EE |
40 | static const u32 hpd_ibx[] = { |
41 | [HPD_CRT] = SDE_CRT_HOTPLUG, | |
42 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, | |
43 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG, | |
44 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG, | |
45 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG | |
46 | }; | |
47 | ||
48 | static const u32 hpd_cpt[] = { | |
49 | [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, | |
73c352a2 | 50 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, |
e5868a31 EE |
51 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
52 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
53 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT | |
54 | }; | |
55 | ||
56 | static const u32 hpd_mask_i915[] = { | |
57 | [HPD_CRT] = CRT_HOTPLUG_INT_EN, | |
58 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, | |
59 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, | |
60 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, | |
61 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, | |
62 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN | |
63 | }; | |
64 | ||
704cfb87 | 65 | static const u32 hpd_status_g4x[] = { |
e5868a31 EE |
66 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
67 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, | |
68 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, | |
69 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
70 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
71 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
72 | }; | |
73 | ||
e5868a31 EE |
74 | static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ |
75 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, | |
76 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, | |
77 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, | |
78 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
79 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
80 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
81 | }; | |
82 | ||
036a4a7d | 83 | /* For display hotplug interrupt */ |
995b6762 | 84 | static void |
f2b115e6 | 85 | ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d | 86 | { |
4bc9d430 DV |
87 | assert_spin_locked(&dev_priv->irq_lock); |
88 | ||
c67a470b PZ |
89 | if (dev_priv->pc8.irqs_disabled) { |
90 | WARN(1, "IRQs disabled\n"); | |
91 | dev_priv->pc8.regsave.deimr &= ~mask; | |
92 | return; | |
93 | } | |
94 | ||
1ec14ad3 CW |
95 | if ((dev_priv->irq_mask & mask) != 0) { |
96 | dev_priv->irq_mask &= ~mask; | |
97 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 98 | POSTING_READ(DEIMR); |
036a4a7d ZW |
99 | } |
100 | } | |
101 | ||
0ff9800a | 102 | static void |
f2b115e6 | 103 | ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d | 104 | { |
4bc9d430 DV |
105 | assert_spin_locked(&dev_priv->irq_lock); |
106 | ||
c67a470b PZ |
107 | if (dev_priv->pc8.irqs_disabled) { |
108 | WARN(1, "IRQs disabled\n"); | |
109 | dev_priv->pc8.regsave.deimr |= mask; | |
110 | return; | |
111 | } | |
112 | ||
1ec14ad3 CW |
113 | if ((dev_priv->irq_mask & mask) != mask) { |
114 | dev_priv->irq_mask |= mask; | |
115 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 116 | POSTING_READ(DEIMR); |
036a4a7d ZW |
117 | } |
118 | } | |
119 | ||
43eaea13 PZ |
120 | /** |
121 | * ilk_update_gt_irq - update GTIMR | |
122 | * @dev_priv: driver private | |
123 | * @interrupt_mask: mask of interrupt bits to update | |
124 | * @enabled_irq_mask: mask of interrupt bits to enable | |
125 | */ | |
126 | static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, | |
127 | uint32_t interrupt_mask, | |
128 | uint32_t enabled_irq_mask) | |
129 | { | |
130 | assert_spin_locked(&dev_priv->irq_lock); | |
131 | ||
c67a470b PZ |
132 | if (dev_priv->pc8.irqs_disabled) { |
133 | WARN(1, "IRQs disabled\n"); | |
134 | dev_priv->pc8.regsave.gtimr &= ~interrupt_mask; | |
135 | dev_priv->pc8.regsave.gtimr |= (~enabled_irq_mask & | |
136 | interrupt_mask); | |
137 | return; | |
138 | } | |
139 | ||
43eaea13 PZ |
140 | dev_priv->gt_irq_mask &= ~interrupt_mask; |
141 | dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); | |
142 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
143 | POSTING_READ(GTIMR); | |
144 | } | |
145 | ||
146 | void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
147 | { | |
148 | ilk_update_gt_irq(dev_priv, mask, mask); | |
149 | } | |
150 | ||
151 | void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
152 | { | |
153 | ilk_update_gt_irq(dev_priv, mask, 0); | |
154 | } | |
155 | ||
edbfdb45 PZ |
156 | /** |
157 | * snb_update_pm_irq - update GEN6_PMIMR | |
158 | * @dev_priv: driver private | |
159 | * @interrupt_mask: mask of interrupt bits to update | |
160 | * @enabled_irq_mask: mask of interrupt bits to enable | |
161 | */ | |
162 | static void snb_update_pm_irq(struct drm_i915_private *dev_priv, | |
163 | uint32_t interrupt_mask, | |
164 | uint32_t enabled_irq_mask) | |
165 | { | |
605cd25b | 166 | uint32_t new_val; |
edbfdb45 PZ |
167 | |
168 | assert_spin_locked(&dev_priv->irq_lock); | |
169 | ||
c67a470b PZ |
170 | if (dev_priv->pc8.irqs_disabled) { |
171 | WARN(1, "IRQs disabled\n"); | |
172 | dev_priv->pc8.regsave.gen6_pmimr &= ~interrupt_mask; | |
173 | dev_priv->pc8.regsave.gen6_pmimr |= (~enabled_irq_mask & | |
174 | interrupt_mask); | |
175 | return; | |
176 | } | |
177 | ||
605cd25b | 178 | new_val = dev_priv->pm_irq_mask; |
f52ecbcf PZ |
179 | new_val &= ~interrupt_mask; |
180 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
181 | ||
605cd25b PZ |
182 | if (new_val != dev_priv->pm_irq_mask) { |
183 | dev_priv->pm_irq_mask = new_val; | |
184 | I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask); | |
f52ecbcf PZ |
185 | POSTING_READ(GEN6_PMIMR); |
186 | } | |
edbfdb45 PZ |
187 | } |
188 | ||
189 | void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
190 | { | |
191 | snb_update_pm_irq(dev_priv, mask, mask); | |
192 | } | |
193 | ||
194 | void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
195 | { | |
196 | snb_update_pm_irq(dev_priv, mask, 0); | |
197 | } | |
198 | ||
8664281b PZ |
199 | static bool ivb_can_enable_err_int(struct drm_device *dev) |
200 | { | |
201 | struct drm_i915_private *dev_priv = dev->dev_private; | |
202 | struct intel_crtc *crtc; | |
203 | enum pipe pipe; | |
204 | ||
4bc9d430 DV |
205 | assert_spin_locked(&dev_priv->irq_lock); |
206 | ||
8664281b PZ |
207 | for_each_pipe(pipe) { |
208 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
209 | ||
210 | if (crtc->cpu_fifo_underrun_disabled) | |
211 | return false; | |
212 | } | |
213 | ||
214 | return true; | |
215 | } | |
216 | ||
217 | static bool cpt_can_enable_serr_int(struct drm_device *dev) | |
218 | { | |
219 | struct drm_i915_private *dev_priv = dev->dev_private; | |
220 | enum pipe pipe; | |
221 | struct intel_crtc *crtc; | |
222 | ||
fee884ed DV |
223 | assert_spin_locked(&dev_priv->irq_lock); |
224 | ||
8664281b PZ |
225 | for_each_pipe(pipe) { |
226 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
227 | ||
228 | if (crtc->pch_fifo_underrun_disabled) | |
229 | return false; | |
230 | } | |
231 | ||
232 | return true; | |
233 | } | |
234 | ||
235 | static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev, | |
236 | enum pipe pipe, bool enable) | |
237 | { | |
238 | struct drm_i915_private *dev_priv = dev->dev_private; | |
239 | uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN : | |
240 | DE_PIPEB_FIFO_UNDERRUN; | |
241 | ||
242 | if (enable) | |
243 | ironlake_enable_display_irq(dev_priv, bit); | |
244 | else | |
245 | ironlake_disable_display_irq(dev_priv, bit); | |
246 | } | |
247 | ||
248 | static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev, | |
7336df65 | 249 | enum pipe pipe, bool enable) |
8664281b PZ |
250 | { |
251 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8664281b | 252 | if (enable) { |
7336df65 DV |
253 | I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); |
254 | ||
8664281b PZ |
255 | if (!ivb_can_enable_err_int(dev)) |
256 | return; | |
257 | ||
8664281b PZ |
258 | ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB); |
259 | } else { | |
7336df65 DV |
260 | bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB); |
261 | ||
262 | /* Change the state _after_ we've read out the current one. */ | |
8664281b | 263 | ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB); |
7336df65 DV |
264 | |
265 | if (!was_enabled && | |
266 | (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) { | |
267 | DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n", | |
268 | pipe_name(pipe)); | |
269 | } | |
8664281b PZ |
270 | } |
271 | } | |
272 | ||
38d83c96 DV |
273 | static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev, |
274 | enum pipe pipe, bool enable) | |
275 | { | |
276 | struct drm_i915_private *dev_priv = dev->dev_private; | |
277 | ||
278 | assert_spin_locked(&dev_priv->irq_lock); | |
279 | ||
280 | if (enable) | |
281 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN; | |
282 | else | |
283 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN; | |
284 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
285 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
286 | } | |
287 | ||
fee884ed DV |
288 | /** |
289 | * ibx_display_interrupt_update - update SDEIMR | |
290 | * @dev_priv: driver private | |
291 | * @interrupt_mask: mask of interrupt bits to update | |
292 | * @enabled_irq_mask: mask of interrupt bits to enable | |
293 | */ | |
294 | static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, | |
295 | uint32_t interrupt_mask, | |
296 | uint32_t enabled_irq_mask) | |
297 | { | |
298 | uint32_t sdeimr = I915_READ(SDEIMR); | |
299 | sdeimr &= ~interrupt_mask; | |
300 | sdeimr |= (~enabled_irq_mask & interrupt_mask); | |
301 | ||
302 | assert_spin_locked(&dev_priv->irq_lock); | |
303 | ||
c67a470b PZ |
304 | if (dev_priv->pc8.irqs_disabled && |
305 | (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) { | |
306 | WARN(1, "IRQs disabled\n"); | |
307 | dev_priv->pc8.regsave.sdeimr &= ~interrupt_mask; | |
308 | dev_priv->pc8.regsave.sdeimr |= (~enabled_irq_mask & | |
309 | interrupt_mask); | |
310 | return; | |
311 | } | |
312 | ||
fee884ed DV |
313 | I915_WRITE(SDEIMR, sdeimr); |
314 | POSTING_READ(SDEIMR); | |
315 | } | |
316 | #define ibx_enable_display_interrupt(dev_priv, bits) \ | |
317 | ibx_display_interrupt_update((dev_priv), (bits), (bits)) | |
318 | #define ibx_disable_display_interrupt(dev_priv, bits) \ | |
319 | ibx_display_interrupt_update((dev_priv), (bits), 0) | |
320 | ||
de28075d DV |
321 | static void ibx_set_fifo_underrun_reporting(struct drm_device *dev, |
322 | enum transcoder pch_transcoder, | |
8664281b PZ |
323 | bool enable) |
324 | { | |
8664281b | 325 | struct drm_i915_private *dev_priv = dev->dev_private; |
de28075d DV |
326 | uint32_t bit = (pch_transcoder == TRANSCODER_A) ? |
327 | SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER; | |
8664281b PZ |
328 | |
329 | if (enable) | |
fee884ed | 330 | ibx_enable_display_interrupt(dev_priv, bit); |
8664281b | 331 | else |
fee884ed | 332 | ibx_disable_display_interrupt(dev_priv, bit); |
8664281b PZ |
333 | } |
334 | ||
335 | static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, | |
336 | enum transcoder pch_transcoder, | |
337 | bool enable) | |
338 | { | |
339 | struct drm_i915_private *dev_priv = dev->dev_private; | |
340 | ||
341 | if (enable) { | |
1dd246fb DV |
342 | I915_WRITE(SERR_INT, |
343 | SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); | |
344 | ||
8664281b PZ |
345 | if (!cpt_can_enable_serr_int(dev)) |
346 | return; | |
347 | ||
fee884ed | 348 | ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
8664281b | 349 | } else { |
1dd246fb DV |
350 | uint32_t tmp = I915_READ(SERR_INT); |
351 | bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT); | |
352 | ||
353 | /* Change the state _after_ we've read out the current one. */ | |
fee884ed | 354 | ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
1dd246fb DV |
355 | |
356 | if (!was_enabled && | |
357 | (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) { | |
358 | DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n", | |
359 | transcoder_name(pch_transcoder)); | |
360 | } | |
8664281b | 361 | } |
8664281b PZ |
362 | } |
363 | ||
364 | /** | |
365 | * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages | |
366 | * @dev: drm device | |
367 | * @pipe: pipe | |
368 | * @enable: true if we want to report FIFO underrun errors, false otherwise | |
369 | * | |
370 | * This function makes us disable or enable CPU fifo underruns for a specific | |
371 | * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun | |
372 | * reporting for one pipe may also disable all the other CPU error interruts for | |
373 | * the other pipes, due to the fact that there's just one interrupt mask/enable | |
374 | * bit for all the pipes. | |
375 | * | |
376 | * Returns the previous state of underrun reporting. | |
377 | */ | |
378 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, | |
379 | enum pipe pipe, bool enable) | |
380 | { | |
381 | struct drm_i915_private *dev_priv = dev->dev_private; | |
382 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
383 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
384 | unsigned long flags; | |
385 | bool ret; | |
386 | ||
387 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
388 | ||
389 | ret = !intel_crtc->cpu_fifo_underrun_disabled; | |
390 | ||
391 | if (enable == ret) | |
392 | goto done; | |
393 | ||
394 | intel_crtc->cpu_fifo_underrun_disabled = !enable; | |
395 | ||
396 | if (IS_GEN5(dev) || IS_GEN6(dev)) | |
397 | ironlake_set_fifo_underrun_reporting(dev, pipe, enable); | |
398 | else if (IS_GEN7(dev)) | |
7336df65 | 399 | ivybridge_set_fifo_underrun_reporting(dev, pipe, enable); |
38d83c96 DV |
400 | else if (IS_GEN8(dev)) |
401 | broadwell_set_fifo_underrun_reporting(dev, pipe, enable); | |
8664281b PZ |
402 | |
403 | done: | |
404 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
405 | return ret; | |
406 | } | |
407 | ||
408 | /** | |
409 | * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages | |
410 | * @dev: drm device | |
411 | * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) | |
412 | * @enable: true if we want to report FIFO underrun errors, false otherwise | |
413 | * | |
414 | * This function makes us disable or enable PCH fifo underruns for a specific | |
415 | * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO | |
416 | * underrun reporting for one transcoder may also disable all the other PCH | |
417 | * error interruts for the other transcoders, due to the fact that there's just | |
418 | * one interrupt mask/enable bit for all the transcoders. | |
419 | * | |
420 | * Returns the previous state of underrun reporting. | |
421 | */ | |
422 | bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, | |
423 | enum transcoder pch_transcoder, | |
424 | bool enable) | |
425 | { | |
426 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de28075d DV |
427 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder]; |
428 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8664281b PZ |
429 | unsigned long flags; |
430 | bool ret; | |
431 | ||
de28075d DV |
432 | /* |
433 | * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT | |
434 | * has only one pch transcoder A that all pipes can use. To avoid racy | |
435 | * pch transcoder -> pipe lookups from interrupt code simply store the | |
436 | * underrun statistics in crtc A. Since we never expose this anywhere | |
437 | * nor use it outside of the fifo underrun code here using the "wrong" | |
438 | * crtc on LPT won't cause issues. | |
439 | */ | |
8664281b PZ |
440 | |
441 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
442 | ||
443 | ret = !intel_crtc->pch_fifo_underrun_disabled; | |
444 | ||
445 | if (enable == ret) | |
446 | goto done; | |
447 | ||
448 | intel_crtc->pch_fifo_underrun_disabled = !enable; | |
449 | ||
450 | if (HAS_PCH_IBX(dev)) | |
de28075d | 451 | ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable); |
8664281b PZ |
452 | else |
453 | cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable); | |
454 | ||
455 | done: | |
456 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
457 | return ret; | |
458 | } | |
459 | ||
460 | ||
7c463586 | 461 | void |
3b6c42e8 | 462 | i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask) |
7c463586 | 463 | { |
46c06a30 VS |
464 | u32 reg = PIPESTAT(pipe); |
465 | u32 pipestat = I915_READ(reg) & 0x7fff0000; | |
7c463586 | 466 | |
b79480ba DV |
467 | assert_spin_locked(&dev_priv->irq_lock); |
468 | ||
46c06a30 VS |
469 | if ((pipestat & mask) == mask) |
470 | return; | |
471 | ||
472 | /* Enable the interrupt, clear any pending status */ | |
473 | pipestat |= mask | (mask >> 16); | |
474 | I915_WRITE(reg, pipestat); | |
475 | POSTING_READ(reg); | |
7c463586 KP |
476 | } |
477 | ||
478 | void | |
3b6c42e8 | 479 | i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask) |
7c463586 | 480 | { |
46c06a30 VS |
481 | u32 reg = PIPESTAT(pipe); |
482 | u32 pipestat = I915_READ(reg) & 0x7fff0000; | |
7c463586 | 483 | |
b79480ba DV |
484 | assert_spin_locked(&dev_priv->irq_lock); |
485 | ||
46c06a30 VS |
486 | if ((pipestat & mask) == 0) |
487 | return; | |
488 | ||
489 | pipestat &= ~mask; | |
490 | I915_WRITE(reg, pipestat); | |
491 | POSTING_READ(reg); | |
7c463586 KP |
492 | } |
493 | ||
01c66889 | 494 | /** |
f49e38dd | 495 | * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion |
01c66889 | 496 | */ |
f49e38dd | 497 | static void i915_enable_asle_pipestat(struct drm_device *dev) |
01c66889 | 498 | { |
1ec14ad3 CW |
499 | drm_i915_private_t *dev_priv = dev->dev_private; |
500 | unsigned long irqflags; | |
501 | ||
f49e38dd JN |
502 | if (!dev_priv->opregion.asle || !IS_MOBILE(dev)) |
503 | return; | |
504 | ||
1ec14ad3 | 505 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
01c66889 | 506 | |
3b6c42e8 | 507 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_ENABLE); |
f898780b | 508 | if (INTEL_INFO(dev)->gen >= 4) |
3b6c42e8 DV |
509 | i915_enable_pipestat(dev_priv, PIPE_A, |
510 | PIPE_LEGACY_BLC_EVENT_ENABLE); | |
1ec14ad3 CW |
511 | |
512 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
01c66889 ZY |
513 | } |
514 | ||
0a3e67a4 JB |
515 | /** |
516 | * i915_pipe_enabled - check if a pipe is enabled | |
517 | * @dev: DRM device | |
518 | * @pipe: pipe to check | |
519 | * | |
520 | * Reading certain registers when the pipe is disabled can hang the chip. | |
521 | * Use this routine to make sure the PLL is running and the pipe is active | |
522 | * before reading such registers if unsure. | |
523 | */ | |
524 | static int | |
525 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
526 | { | |
527 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
702e7a56 | 528 | |
a01025af DV |
529 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
530 | /* Locking is horribly broken here, but whatever. */ | |
531 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
532 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
71f8ba6b | 533 | |
a01025af DV |
534 | return intel_crtc->active; |
535 | } else { | |
536 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; | |
537 | } | |
0a3e67a4 JB |
538 | } |
539 | ||
4cdb83ec VS |
540 | static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe) |
541 | { | |
542 | /* Gen2 doesn't have a hardware frame counter */ | |
543 | return 0; | |
544 | } | |
545 | ||
42f52ef8 KP |
546 | /* Called from drm generic code, passed a 'crtc', which |
547 | * we use as a pipe index | |
548 | */ | |
f71d4af4 | 549 | static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
0a3e67a4 JB |
550 | { |
551 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
552 | unsigned long high_frame; | |
553 | unsigned long low_frame; | |
391f75e2 | 554 | u32 high1, high2, low, pixel, vbl_start; |
0a3e67a4 JB |
555 | |
556 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 557 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 558 | "pipe %c\n", pipe_name(pipe)); |
0a3e67a4 JB |
559 | return 0; |
560 | } | |
561 | ||
391f75e2 VS |
562 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
563 | struct intel_crtc *intel_crtc = | |
564 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
565 | const struct drm_display_mode *mode = | |
566 | &intel_crtc->config.adjusted_mode; | |
567 | ||
568 | vbl_start = mode->crtc_vblank_start * mode->crtc_htotal; | |
569 | } else { | |
570 | enum transcoder cpu_transcoder = | |
571 | intel_pipe_to_cpu_transcoder(dev_priv, pipe); | |
572 | u32 htotal; | |
573 | ||
574 | htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1; | |
575 | vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1; | |
576 | ||
577 | vbl_start *= htotal; | |
578 | } | |
579 | ||
9db4a9c7 JB |
580 | high_frame = PIPEFRAME(pipe); |
581 | low_frame = PIPEFRAMEPIXEL(pipe); | |
5eddb70b | 582 | |
0a3e67a4 JB |
583 | /* |
584 | * High & low register fields aren't synchronized, so make sure | |
585 | * we get a low value that's stable across two reads of the high | |
586 | * register. | |
587 | */ | |
588 | do { | |
5eddb70b | 589 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
391f75e2 | 590 | low = I915_READ(low_frame); |
5eddb70b | 591 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
0a3e67a4 JB |
592 | } while (high1 != high2); |
593 | ||
5eddb70b | 594 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
391f75e2 | 595 | pixel = low & PIPE_PIXEL_MASK; |
5eddb70b | 596 | low >>= PIPE_FRAME_LOW_SHIFT; |
391f75e2 VS |
597 | |
598 | /* | |
599 | * The frame counter increments at beginning of active. | |
600 | * Cook up a vblank counter by also checking the pixel | |
601 | * counter against vblank start. | |
602 | */ | |
edc08d0a | 603 | return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; |
0a3e67a4 JB |
604 | } |
605 | ||
f71d4af4 | 606 | static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
9880b7a5 JB |
607 | { |
608 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 609 | int reg = PIPE_FRMCOUNT_GM45(pipe); |
9880b7a5 JB |
610 | |
611 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 612 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 613 | "pipe %c\n", pipe_name(pipe)); |
9880b7a5 JB |
614 | return 0; |
615 | } | |
616 | ||
617 | return I915_READ(reg); | |
618 | } | |
619 | ||
ad3543ed MK |
620 | /* raw reads, only for fast reads of display block, no need for forcewake etc. */ |
621 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) | |
622 | #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__)) | |
623 | ||
624 | static bool intel_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe) | |
54ddcbd2 VS |
625 | { |
626 | struct drm_i915_private *dev_priv = dev->dev_private; | |
627 | uint32_t status; | |
ad3543ed | 628 | int reg; |
54ddcbd2 VS |
629 | |
630 | if (IS_VALLEYVIEW(dev)) { | |
631 | status = pipe == PIPE_A ? | |
632 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT : | |
633 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; | |
634 | ||
ad3543ed | 635 | reg = VLV_ISR; |
7c06b08a VS |
636 | } else if (IS_GEN2(dev)) { |
637 | status = pipe == PIPE_A ? | |
638 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT : | |
639 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; | |
640 | ||
ad3543ed | 641 | reg = ISR; |
7c06b08a | 642 | } else if (INTEL_INFO(dev)->gen < 5) { |
54ddcbd2 VS |
643 | status = pipe == PIPE_A ? |
644 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT : | |
645 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; | |
646 | ||
ad3543ed | 647 | reg = ISR; |
54ddcbd2 VS |
648 | } else if (INTEL_INFO(dev)->gen < 7) { |
649 | status = pipe == PIPE_A ? | |
650 | DE_PIPEA_VBLANK : | |
651 | DE_PIPEB_VBLANK; | |
652 | ||
ad3543ed | 653 | reg = DEISR; |
54ddcbd2 VS |
654 | } else { |
655 | switch (pipe) { | |
656 | default: | |
657 | case PIPE_A: | |
658 | status = DE_PIPEA_VBLANK_IVB; | |
659 | break; | |
660 | case PIPE_B: | |
661 | status = DE_PIPEB_VBLANK_IVB; | |
662 | break; | |
663 | case PIPE_C: | |
664 | status = DE_PIPEC_VBLANK_IVB; | |
665 | break; | |
666 | } | |
667 | ||
ad3543ed | 668 | reg = DEISR; |
54ddcbd2 | 669 | } |
ad3543ed MK |
670 | |
671 | if (IS_GEN2(dev)) | |
672 | return __raw_i915_read16(dev_priv, reg) & status; | |
673 | else | |
674 | return __raw_i915_read32(dev_priv, reg) & status; | |
54ddcbd2 VS |
675 | } |
676 | ||
f71d4af4 | 677 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
abca9e45 VS |
678 | unsigned int flags, int *vpos, int *hpos, |
679 | ktime_t *stime, ktime_t *etime) | |
0af7e4df | 680 | { |
c2baf4b7 VS |
681 | struct drm_i915_private *dev_priv = dev->dev_private; |
682 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
683 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
684 | const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; | |
3aa18df8 | 685 | int position; |
0af7e4df MK |
686 | int vbl_start, vbl_end, htotal, vtotal; |
687 | bool in_vbl = true; | |
688 | int ret = 0; | |
ad3543ed | 689 | unsigned long irqflags; |
0af7e4df | 690 | |
c2baf4b7 | 691 | if (!intel_crtc->active) { |
0af7e4df | 692 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
9db4a9c7 | 693 | "pipe %c\n", pipe_name(pipe)); |
0af7e4df MK |
694 | return 0; |
695 | } | |
696 | ||
c2baf4b7 VS |
697 | htotal = mode->crtc_htotal; |
698 | vtotal = mode->crtc_vtotal; | |
699 | vbl_start = mode->crtc_vblank_start; | |
700 | vbl_end = mode->crtc_vblank_end; | |
0af7e4df | 701 | |
d31faf65 VS |
702 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
703 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
704 | vbl_end /= 2; | |
705 | vtotal /= 2; | |
706 | } | |
707 | ||
c2baf4b7 VS |
708 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; |
709 | ||
ad3543ed MK |
710 | /* |
711 | * Lock uncore.lock, as we will do multiple timing critical raw | |
712 | * register reads, potentially with preemption disabled, so the | |
713 | * following code must not block on uncore.lock. | |
714 | */ | |
715 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
716 | ||
717 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ | |
718 | ||
719 | /* Get optional system timestamp before query. */ | |
720 | if (stime) | |
721 | *stime = ktime_get(); | |
722 | ||
7c06b08a | 723 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
0af7e4df MK |
724 | /* No obvious pixelcount register. Only query vertical |
725 | * scanout position from Display scan line register. | |
726 | */ | |
7c06b08a | 727 | if (IS_GEN2(dev)) |
ad3543ed | 728 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; |
7c06b08a | 729 | else |
ad3543ed | 730 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; |
54ddcbd2 VS |
731 | |
732 | /* | |
733 | * The scanline counter increments at the leading edge | |
734 | * of hsync, ie. it completely misses the active portion | |
735 | * of the line. Fix up the counter at both edges of vblank | |
736 | * to get a more accurate picture whether we're in vblank | |
737 | * or not. | |
738 | */ | |
ad3543ed | 739 | in_vbl = intel_pipe_in_vblank_locked(dev, pipe); |
54ddcbd2 VS |
740 | if ((in_vbl && position == vbl_start - 1) || |
741 | (!in_vbl && position == vbl_end - 1)) | |
742 | position = (position + 1) % vtotal; | |
0af7e4df MK |
743 | } else { |
744 | /* Have access to pixelcount since start of frame. | |
745 | * We can split this into vertical and horizontal | |
746 | * scanout position. | |
747 | */ | |
ad3543ed | 748 | position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; |
0af7e4df | 749 | |
3aa18df8 VS |
750 | /* convert to pixel counts */ |
751 | vbl_start *= htotal; | |
752 | vbl_end *= htotal; | |
753 | vtotal *= htotal; | |
0af7e4df MK |
754 | } |
755 | ||
ad3543ed MK |
756 | /* Get optional system timestamp after query. */ |
757 | if (etime) | |
758 | *etime = ktime_get(); | |
759 | ||
760 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ | |
761 | ||
762 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
763 | ||
3aa18df8 VS |
764 | in_vbl = position >= vbl_start && position < vbl_end; |
765 | ||
766 | /* | |
767 | * While in vblank, position will be negative | |
768 | * counting up towards 0 at vbl_end. And outside | |
769 | * vblank, position will be positive counting | |
770 | * up since vbl_end. | |
771 | */ | |
772 | if (position >= vbl_start) | |
773 | position -= vbl_end; | |
774 | else | |
775 | position += vtotal - vbl_end; | |
0af7e4df | 776 | |
7c06b08a | 777 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
3aa18df8 VS |
778 | *vpos = position; |
779 | *hpos = 0; | |
780 | } else { | |
781 | *vpos = position / htotal; | |
782 | *hpos = position - (*vpos * htotal); | |
783 | } | |
0af7e4df | 784 | |
0af7e4df MK |
785 | /* In vblank? */ |
786 | if (in_vbl) | |
787 | ret |= DRM_SCANOUTPOS_INVBL; | |
788 | ||
789 | return ret; | |
790 | } | |
791 | ||
f71d4af4 | 792 | static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
0af7e4df MK |
793 | int *max_error, |
794 | struct timeval *vblank_time, | |
795 | unsigned flags) | |
796 | { | |
4041b853 | 797 | struct drm_crtc *crtc; |
0af7e4df | 798 | |
7eb552ae | 799 | if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { |
4041b853 | 800 | DRM_ERROR("Invalid crtc %d\n", pipe); |
0af7e4df MK |
801 | return -EINVAL; |
802 | } | |
803 | ||
804 | /* Get drm_crtc to timestamp: */ | |
4041b853 CW |
805 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
806 | if (crtc == NULL) { | |
807 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
808 | return -EINVAL; | |
809 | } | |
810 | ||
811 | if (!crtc->enabled) { | |
812 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); | |
813 | return -EBUSY; | |
814 | } | |
0af7e4df MK |
815 | |
816 | /* Helper routine in DRM core does all the work: */ | |
4041b853 CW |
817 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
818 | vblank_time, flags, | |
7da903ef VS |
819 | crtc, |
820 | &to_intel_crtc(crtc)->config.adjusted_mode); | |
0af7e4df MK |
821 | } |
822 | ||
67c347ff JN |
823 | static bool intel_hpd_irq_event(struct drm_device *dev, |
824 | struct drm_connector *connector) | |
321a1b30 EE |
825 | { |
826 | enum drm_connector_status old_status; | |
827 | ||
828 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); | |
829 | old_status = connector->status; | |
830 | ||
831 | connector->status = connector->funcs->detect(connector, false); | |
67c347ff JN |
832 | if (old_status == connector->status) |
833 | return false; | |
834 | ||
835 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n", | |
321a1b30 EE |
836 | connector->base.id, |
837 | drm_get_connector_name(connector), | |
67c347ff JN |
838 | drm_get_connector_status_name(old_status), |
839 | drm_get_connector_status_name(connector->status)); | |
840 | ||
841 | return true; | |
321a1b30 EE |
842 | } |
843 | ||
5ca58282 JB |
844 | /* |
845 | * Handle hotplug events outside the interrupt handler proper. | |
846 | */ | |
ac4c16c5 EE |
847 | #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000) |
848 | ||
5ca58282 JB |
849 | static void i915_hotplug_work_func(struct work_struct *work) |
850 | { | |
851 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
852 | hotplug_work); | |
853 | struct drm_device *dev = dev_priv->dev; | |
c31c4ba3 | 854 | struct drm_mode_config *mode_config = &dev->mode_config; |
cd569aed EE |
855 | struct intel_connector *intel_connector; |
856 | struct intel_encoder *intel_encoder; | |
857 | struct drm_connector *connector; | |
858 | unsigned long irqflags; | |
859 | bool hpd_disabled = false; | |
321a1b30 | 860 | bool changed = false; |
142e2398 | 861 | u32 hpd_event_bits; |
4ef69c7a | 862 | |
52d7eced DV |
863 | /* HPD irq before everything is fully set up. */ |
864 | if (!dev_priv->enable_hotplug_processing) | |
865 | return; | |
866 | ||
a65e34c7 | 867 | mutex_lock(&mode_config->mutex); |
e67189ab JB |
868 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); |
869 | ||
cd569aed | 870 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
142e2398 EE |
871 | |
872 | hpd_event_bits = dev_priv->hpd_event_bits; | |
873 | dev_priv->hpd_event_bits = 0; | |
cd569aed EE |
874 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
875 | intel_connector = to_intel_connector(connector); | |
876 | intel_encoder = intel_connector->encoder; | |
877 | if (intel_encoder->hpd_pin > HPD_NONE && | |
878 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED && | |
879 | connector->polled == DRM_CONNECTOR_POLL_HPD) { | |
880 | DRM_INFO("HPD interrupt storm detected on connector %s: " | |
881 | "switching from hotplug detection to polling\n", | |
882 | drm_get_connector_name(connector)); | |
883 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED; | |
884 | connector->polled = DRM_CONNECTOR_POLL_CONNECT | |
885 | | DRM_CONNECTOR_POLL_DISCONNECT; | |
886 | hpd_disabled = true; | |
887 | } | |
142e2398 EE |
888 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { |
889 | DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n", | |
890 | drm_get_connector_name(connector), intel_encoder->hpd_pin); | |
891 | } | |
cd569aed EE |
892 | } |
893 | /* if there were no outputs to poll, poll was disabled, | |
894 | * therefore make sure it's enabled when disabling HPD on | |
895 | * some connectors */ | |
ac4c16c5 | 896 | if (hpd_disabled) { |
cd569aed | 897 | drm_kms_helper_poll_enable(dev); |
ac4c16c5 EE |
898 | mod_timer(&dev_priv->hotplug_reenable_timer, |
899 | jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY)); | |
900 | } | |
cd569aed EE |
901 | |
902 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
903 | ||
321a1b30 EE |
904 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
905 | intel_connector = to_intel_connector(connector); | |
906 | intel_encoder = intel_connector->encoder; | |
907 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { | |
908 | if (intel_encoder->hot_plug) | |
909 | intel_encoder->hot_plug(intel_encoder); | |
910 | if (intel_hpd_irq_event(dev, connector)) | |
911 | changed = true; | |
912 | } | |
913 | } | |
40ee3381 KP |
914 | mutex_unlock(&mode_config->mutex); |
915 | ||
321a1b30 EE |
916 | if (changed) |
917 | drm_kms_helper_hotplug_event(dev); | |
5ca58282 JB |
918 | } |
919 | ||
d0ecd7e2 | 920 | static void ironlake_rps_change_irq_handler(struct drm_device *dev) |
f97108d1 JB |
921 | { |
922 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b5b72e89 | 923 | u32 busy_up, busy_down, max_avg, min_avg; |
9270388e | 924 | u8 new_delay; |
9270388e | 925 | |
d0ecd7e2 | 926 | spin_lock(&mchdev_lock); |
f97108d1 | 927 | |
73edd18f DV |
928 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
929 | ||
20e4d407 | 930 | new_delay = dev_priv->ips.cur_delay; |
9270388e | 931 | |
7648fa99 | 932 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
933 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
934 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
935 | max_avg = I915_READ(RCBMAXAVG); |
936 | min_avg = I915_READ(RCBMINAVG); | |
937 | ||
938 | /* Handle RCS change request from hw */ | |
b5b72e89 | 939 | if (busy_up > max_avg) { |
20e4d407 DV |
940 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
941 | new_delay = dev_priv->ips.cur_delay - 1; | |
942 | if (new_delay < dev_priv->ips.max_delay) | |
943 | new_delay = dev_priv->ips.max_delay; | |
b5b72e89 | 944 | } else if (busy_down < min_avg) { |
20e4d407 DV |
945 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
946 | new_delay = dev_priv->ips.cur_delay + 1; | |
947 | if (new_delay > dev_priv->ips.min_delay) | |
948 | new_delay = dev_priv->ips.min_delay; | |
f97108d1 JB |
949 | } |
950 | ||
7648fa99 | 951 | if (ironlake_set_drps(dev, new_delay)) |
20e4d407 | 952 | dev_priv->ips.cur_delay = new_delay; |
f97108d1 | 953 | |
d0ecd7e2 | 954 | spin_unlock(&mchdev_lock); |
9270388e | 955 | |
f97108d1 JB |
956 | return; |
957 | } | |
958 | ||
549f7365 CW |
959 | static void notify_ring(struct drm_device *dev, |
960 | struct intel_ring_buffer *ring) | |
961 | { | |
475553de CW |
962 | if (ring->obj == NULL) |
963 | return; | |
964 | ||
814e9b57 | 965 | trace_i915_gem_request_complete(ring); |
9862e600 | 966 | |
549f7365 | 967 | wake_up_all(&ring->irq_queue); |
10cd45b6 | 968 | i915_queue_hangcheck(dev); |
549f7365 CW |
969 | } |
970 | ||
4912d041 | 971 | static void gen6_pm_rps_work(struct work_struct *work) |
3b8d8d91 | 972 | { |
4912d041 | 973 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
c6a828d3 | 974 | rps.work); |
edbfdb45 | 975 | u32 pm_iir; |
dd75fdc8 | 976 | int new_delay, adj; |
4912d041 | 977 | |
59cdb63d | 978 | spin_lock_irq(&dev_priv->irq_lock); |
c6a828d3 DV |
979 | pm_iir = dev_priv->rps.pm_iir; |
980 | dev_priv->rps.pm_iir = 0; | |
4848405c | 981 | /* Make sure not to corrupt PMIMR state used by ringbuffer code */ |
edbfdb45 | 982 | snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS); |
59cdb63d | 983 | spin_unlock_irq(&dev_priv->irq_lock); |
3b8d8d91 | 984 | |
60611c13 PZ |
985 | /* Make sure we didn't queue anything we're not going to process. */ |
986 | WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS); | |
987 | ||
4848405c | 988 | if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0) |
3b8d8d91 JB |
989 | return; |
990 | ||
4fc688ce | 991 | mutex_lock(&dev_priv->rps.hw_lock); |
7b9e0ae6 | 992 | |
dd75fdc8 | 993 | adj = dev_priv->rps.last_adj; |
7425034a | 994 | if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { |
dd75fdc8 CW |
995 | if (adj > 0) |
996 | adj *= 2; | |
997 | else | |
998 | adj = 1; | |
999 | new_delay = dev_priv->rps.cur_delay + adj; | |
7425034a VS |
1000 | |
1001 | /* | |
1002 | * For better performance, jump directly | |
1003 | * to RPe if we're below it. | |
1004 | */ | |
dd75fdc8 CW |
1005 | if (new_delay < dev_priv->rps.rpe_delay) |
1006 | new_delay = dev_priv->rps.rpe_delay; | |
1007 | } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { | |
1008 | if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay) | |
7425034a | 1009 | new_delay = dev_priv->rps.rpe_delay; |
dd75fdc8 CW |
1010 | else |
1011 | new_delay = dev_priv->rps.min_delay; | |
1012 | adj = 0; | |
1013 | } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { | |
1014 | if (adj < 0) | |
1015 | adj *= 2; | |
1016 | else | |
1017 | adj = -1; | |
1018 | new_delay = dev_priv->rps.cur_delay + adj; | |
1019 | } else { /* unknown event */ | |
1020 | new_delay = dev_priv->rps.cur_delay; | |
1021 | } | |
3b8d8d91 | 1022 | |
79249636 BW |
1023 | /* sysfs frequency interfaces may have snuck in while servicing the |
1024 | * interrupt | |
1025 | */ | |
1272e7b8 VS |
1026 | new_delay = clamp_t(int, new_delay, |
1027 | dev_priv->rps.min_delay, dev_priv->rps.max_delay); | |
dd75fdc8 CW |
1028 | dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay; |
1029 | ||
1030 | if (IS_VALLEYVIEW(dev_priv->dev)) | |
1031 | valleyview_set_rps(dev_priv->dev, new_delay); | |
1032 | else | |
1033 | gen6_set_rps(dev_priv->dev, new_delay); | |
3b8d8d91 | 1034 | |
4fc688ce | 1035 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 JB |
1036 | } |
1037 | ||
e3689190 BW |
1038 | |
1039 | /** | |
1040 | * ivybridge_parity_work - Workqueue called when a parity error interrupt | |
1041 | * occurred. | |
1042 | * @work: workqueue struct | |
1043 | * | |
1044 | * Doesn't actually do anything except notify userspace. As a consequence of | |
1045 | * this event, userspace should try to remap the bad rows since statistically | |
1046 | * it is likely the same row is more likely to go bad again. | |
1047 | */ | |
1048 | static void ivybridge_parity_work(struct work_struct *work) | |
1049 | { | |
1050 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
a4da4fa4 | 1051 | l3_parity.error_work); |
e3689190 | 1052 | u32 error_status, row, bank, subbank; |
35a85ac6 | 1053 | char *parity_event[6]; |
e3689190 BW |
1054 | uint32_t misccpctl; |
1055 | unsigned long flags; | |
35a85ac6 | 1056 | uint8_t slice = 0; |
e3689190 BW |
1057 | |
1058 | /* We must turn off DOP level clock gating to access the L3 registers. | |
1059 | * In order to prevent a get/put style interface, acquire struct mutex | |
1060 | * any time we access those registers. | |
1061 | */ | |
1062 | mutex_lock(&dev_priv->dev->struct_mutex); | |
1063 | ||
35a85ac6 BW |
1064 | /* If we've screwed up tracking, just let the interrupt fire again */ |
1065 | if (WARN_ON(!dev_priv->l3_parity.which_slice)) | |
1066 | goto out; | |
1067 | ||
e3689190 BW |
1068 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
1069 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
1070 | POSTING_READ(GEN7_MISCCPCTL); | |
1071 | ||
35a85ac6 BW |
1072 | while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { |
1073 | u32 reg; | |
e3689190 | 1074 | |
35a85ac6 BW |
1075 | slice--; |
1076 | if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev))) | |
1077 | break; | |
e3689190 | 1078 | |
35a85ac6 | 1079 | dev_priv->l3_parity.which_slice &= ~(1<<slice); |
e3689190 | 1080 | |
35a85ac6 | 1081 | reg = GEN7_L3CDERRST1 + (slice * 0x200); |
e3689190 | 1082 | |
35a85ac6 BW |
1083 | error_status = I915_READ(reg); |
1084 | row = GEN7_PARITY_ERROR_ROW(error_status); | |
1085 | bank = GEN7_PARITY_ERROR_BANK(error_status); | |
1086 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); | |
1087 | ||
1088 | I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); | |
1089 | POSTING_READ(reg); | |
1090 | ||
1091 | parity_event[0] = I915_L3_PARITY_UEVENT "=1"; | |
1092 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); | |
1093 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); | |
1094 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); | |
1095 | parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); | |
1096 | parity_event[5] = NULL; | |
1097 | ||
5bdebb18 | 1098 | kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj, |
35a85ac6 | 1099 | KOBJ_CHANGE, parity_event); |
e3689190 | 1100 | |
35a85ac6 BW |
1101 | DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", |
1102 | slice, row, bank, subbank); | |
e3689190 | 1103 | |
35a85ac6 BW |
1104 | kfree(parity_event[4]); |
1105 | kfree(parity_event[3]); | |
1106 | kfree(parity_event[2]); | |
1107 | kfree(parity_event[1]); | |
1108 | } | |
e3689190 | 1109 | |
35a85ac6 | 1110 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
e3689190 | 1111 | |
35a85ac6 BW |
1112 | out: |
1113 | WARN_ON(dev_priv->l3_parity.which_slice); | |
1114 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1115 | ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev)); | |
1116 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1117 | ||
1118 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
e3689190 BW |
1119 | } |
1120 | ||
35a85ac6 | 1121 | static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir) |
e3689190 BW |
1122 | { |
1123 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e3689190 | 1124 | |
040d2baa | 1125 | if (!HAS_L3_DPF(dev)) |
e3689190 BW |
1126 | return; |
1127 | ||
d0ecd7e2 | 1128 | spin_lock(&dev_priv->irq_lock); |
35a85ac6 | 1129 | ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev)); |
d0ecd7e2 | 1130 | spin_unlock(&dev_priv->irq_lock); |
e3689190 | 1131 | |
35a85ac6 BW |
1132 | iir &= GT_PARITY_ERROR(dev); |
1133 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) | |
1134 | dev_priv->l3_parity.which_slice |= 1 << 1; | |
1135 | ||
1136 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) | |
1137 | dev_priv->l3_parity.which_slice |= 1 << 0; | |
1138 | ||
a4da4fa4 | 1139 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
e3689190 BW |
1140 | } |
1141 | ||
f1af8fc1 PZ |
1142 | static void ilk_gt_irq_handler(struct drm_device *dev, |
1143 | struct drm_i915_private *dev_priv, | |
1144 | u32 gt_iir) | |
1145 | { | |
1146 | if (gt_iir & | |
1147 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
1148 | notify_ring(dev, &dev_priv->ring[RCS]); | |
1149 | if (gt_iir & ILK_BSD_USER_INTERRUPT) | |
1150 | notify_ring(dev, &dev_priv->ring[VCS]); | |
1151 | } | |
1152 | ||
e7b4c6b1 DV |
1153 | static void snb_gt_irq_handler(struct drm_device *dev, |
1154 | struct drm_i915_private *dev_priv, | |
1155 | u32 gt_iir) | |
1156 | { | |
1157 | ||
cc609d5d BW |
1158 | if (gt_iir & |
1159 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
e7b4c6b1 | 1160 | notify_ring(dev, &dev_priv->ring[RCS]); |
cc609d5d | 1161 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
e7b4c6b1 | 1162 | notify_ring(dev, &dev_priv->ring[VCS]); |
cc609d5d | 1163 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
e7b4c6b1 DV |
1164 | notify_ring(dev, &dev_priv->ring[BCS]); |
1165 | ||
cc609d5d BW |
1166 | if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | |
1167 | GT_BSD_CS_ERROR_INTERRUPT | | |
1168 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) { | |
e7b4c6b1 DV |
1169 | DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir); |
1170 | i915_handle_error(dev, false); | |
1171 | } | |
e3689190 | 1172 | |
35a85ac6 BW |
1173 | if (gt_iir & GT_PARITY_ERROR(dev)) |
1174 | ivybridge_parity_error_irq_handler(dev, gt_iir); | |
e7b4c6b1 DV |
1175 | } |
1176 | ||
abd58f01 BW |
1177 | static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev, |
1178 | struct drm_i915_private *dev_priv, | |
1179 | u32 master_ctl) | |
1180 | { | |
1181 | u32 rcs, bcs, vcs; | |
1182 | uint32_t tmp = 0; | |
1183 | irqreturn_t ret = IRQ_NONE; | |
1184 | ||
1185 | if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { | |
1186 | tmp = I915_READ(GEN8_GT_IIR(0)); | |
1187 | if (tmp) { | |
1188 | ret = IRQ_HANDLED; | |
1189 | rcs = tmp >> GEN8_RCS_IRQ_SHIFT; | |
1190 | bcs = tmp >> GEN8_BCS_IRQ_SHIFT; | |
1191 | if (rcs & GT_RENDER_USER_INTERRUPT) | |
1192 | notify_ring(dev, &dev_priv->ring[RCS]); | |
1193 | if (bcs & GT_RENDER_USER_INTERRUPT) | |
1194 | notify_ring(dev, &dev_priv->ring[BCS]); | |
1195 | I915_WRITE(GEN8_GT_IIR(0), tmp); | |
1196 | } else | |
1197 | DRM_ERROR("The master control interrupt lied (GT0)!\n"); | |
1198 | } | |
1199 | ||
1200 | if (master_ctl & GEN8_GT_VCS1_IRQ) { | |
1201 | tmp = I915_READ(GEN8_GT_IIR(1)); | |
1202 | if (tmp) { | |
1203 | ret = IRQ_HANDLED; | |
1204 | vcs = tmp >> GEN8_VCS1_IRQ_SHIFT; | |
1205 | if (vcs & GT_RENDER_USER_INTERRUPT) | |
1206 | notify_ring(dev, &dev_priv->ring[VCS]); | |
1207 | I915_WRITE(GEN8_GT_IIR(1), tmp); | |
1208 | } else | |
1209 | DRM_ERROR("The master control interrupt lied (GT1)!\n"); | |
1210 | } | |
1211 | ||
1212 | if (master_ctl & GEN8_GT_VECS_IRQ) { | |
1213 | tmp = I915_READ(GEN8_GT_IIR(3)); | |
1214 | if (tmp) { | |
1215 | ret = IRQ_HANDLED; | |
1216 | vcs = tmp >> GEN8_VECS_IRQ_SHIFT; | |
1217 | if (vcs & GT_RENDER_USER_INTERRUPT) | |
1218 | notify_ring(dev, &dev_priv->ring[VECS]); | |
1219 | I915_WRITE(GEN8_GT_IIR(3), tmp); | |
1220 | } else | |
1221 | DRM_ERROR("The master control interrupt lied (GT3)!\n"); | |
1222 | } | |
1223 | ||
1224 | return ret; | |
1225 | } | |
1226 | ||
b543fb04 EE |
1227 | #define HPD_STORM_DETECT_PERIOD 1000 |
1228 | #define HPD_STORM_THRESHOLD 5 | |
1229 | ||
10a504de | 1230 | static inline void intel_hpd_irq_handler(struct drm_device *dev, |
22062dba DV |
1231 | u32 hotplug_trigger, |
1232 | const u32 *hpd) | |
b543fb04 EE |
1233 | { |
1234 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b543fb04 | 1235 | int i; |
10a504de | 1236 | bool storm_detected = false; |
b543fb04 | 1237 | |
91d131d2 DV |
1238 | if (!hotplug_trigger) |
1239 | return; | |
1240 | ||
b5ea2d56 | 1241 | spin_lock(&dev_priv->irq_lock); |
b543fb04 | 1242 | for (i = 1; i < HPD_NUM_PINS; i++) { |
821450c6 | 1243 | |
3432087e | 1244 | WARN_ONCE(hpd[i] & hotplug_trigger && |
8b5565b8 | 1245 | dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED, |
cba1c073 CW |
1246 | "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n", |
1247 | hotplug_trigger, i, hpd[i]); | |
b8f102e8 | 1248 | |
b543fb04 EE |
1249 | if (!(hpd[i] & hotplug_trigger) || |
1250 | dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED) | |
1251 | continue; | |
1252 | ||
bc5ead8c | 1253 | dev_priv->hpd_event_bits |= (1 << i); |
b543fb04 EE |
1254 | if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies, |
1255 | dev_priv->hpd_stats[i].hpd_last_jiffies | |
1256 | + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) { | |
1257 | dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies; | |
1258 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
b8f102e8 | 1259 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i); |
b543fb04 EE |
1260 | } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) { |
1261 | dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED; | |
142e2398 | 1262 | dev_priv->hpd_event_bits &= ~(1 << i); |
b543fb04 | 1263 | DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i); |
10a504de | 1264 | storm_detected = true; |
b543fb04 EE |
1265 | } else { |
1266 | dev_priv->hpd_stats[i].hpd_cnt++; | |
b8f102e8 EE |
1267 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i, |
1268 | dev_priv->hpd_stats[i].hpd_cnt); | |
b543fb04 EE |
1269 | } |
1270 | } | |
1271 | ||
10a504de DV |
1272 | if (storm_detected) |
1273 | dev_priv->display.hpd_irq_setup(dev); | |
b5ea2d56 | 1274 | spin_unlock(&dev_priv->irq_lock); |
5876fa0d | 1275 | |
645416f5 DV |
1276 | /* |
1277 | * Our hotplug handler can grab modeset locks (by calling down into the | |
1278 | * fb helpers). Hence it must not be run on our own dev-priv->wq work | |
1279 | * queue for otherwise the flush_work in the pageflip code will | |
1280 | * deadlock. | |
1281 | */ | |
1282 | schedule_work(&dev_priv->hotplug_work); | |
b543fb04 EE |
1283 | } |
1284 | ||
515ac2bb DV |
1285 | static void gmbus_irq_handler(struct drm_device *dev) |
1286 | { | |
28c70f16 DV |
1287 | struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private; |
1288 | ||
28c70f16 | 1289 | wake_up_all(&dev_priv->gmbus_wait_queue); |
515ac2bb DV |
1290 | } |
1291 | ||
ce99c256 DV |
1292 | static void dp_aux_irq_handler(struct drm_device *dev) |
1293 | { | |
9ee32fea DV |
1294 | struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private; |
1295 | ||
9ee32fea | 1296 | wake_up_all(&dev_priv->gmbus_wait_queue); |
ce99c256 DV |
1297 | } |
1298 | ||
8bf1e9f1 | 1299 | #if defined(CONFIG_DEBUG_FS) |
277de95e DV |
1300 | static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, |
1301 | uint32_t crc0, uint32_t crc1, | |
1302 | uint32_t crc2, uint32_t crc3, | |
1303 | uint32_t crc4) | |
8bf1e9f1 SH |
1304 | { |
1305 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1306 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; | |
1307 | struct intel_pipe_crc_entry *entry; | |
ac2300d4 | 1308 | int head, tail; |
b2c88f5b | 1309 | |
d538bbdf DL |
1310 | spin_lock(&pipe_crc->lock); |
1311 | ||
0c912c79 | 1312 | if (!pipe_crc->entries) { |
d538bbdf | 1313 | spin_unlock(&pipe_crc->lock); |
0c912c79 DL |
1314 | DRM_ERROR("spurious interrupt\n"); |
1315 | return; | |
1316 | } | |
1317 | ||
d538bbdf DL |
1318 | head = pipe_crc->head; |
1319 | tail = pipe_crc->tail; | |
b2c88f5b DL |
1320 | |
1321 | if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { | |
d538bbdf | 1322 | spin_unlock(&pipe_crc->lock); |
b2c88f5b DL |
1323 | DRM_ERROR("CRC buffer overflowing\n"); |
1324 | return; | |
1325 | } | |
1326 | ||
1327 | entry = &pipe_crc->entries[head]; | |
8bf1e9f1 | 1328 | |
8bc5e955 | 1329 | entry->frame = dev->driver->get_vblank_counter(dev, pipe); |
eba94eb9 DV |
1330 | entry->crc[0] = crc0; |
1331 | entry->crc[1] = crc1; | |
1332 | entry->crc[2] = crc2; | |
1333 | entry->crc[3] = crc3; | |
1334 | entry->crc[4] = crc4; | |
b2c88f5b DL |
1335 | |
1336 | head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
d538bbdf DL |
1337 | pipe_crc->head = head; |
1338 | ||
1339 | spin_unlock(&pipe_crc->lock); | |
07144428 DL |
1340 | |
1341 | wake_up_interruptible(&pipe_crc->wq); | |
8bf1e9f1 | 1342 | } |
277de95e DV |
1343 | #else |
1344 | static inline void | |
1345 | display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, | |
1346 | uint32_t crc0, uint32_t crc1, | |
1347 | uint32_t crc2, uint32_t crc3, | |
1348 | uint32_t crc4) {} | |
1349 | #endif | |
1350 | ||
eba94eb9 | 1351 | |
277de95e | 1352 | static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5a69b89f DV |
1353 | { |
1354 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1355 | ||
277de95e DV |
1356 | display_pipe_crc_irq_handler(dev, pipe, |
1357 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1358 | 0, 0, 0, 0); | |
5a69b89f DV |
1359 | } |
1360 | ||
277de95e | 1361 | static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
eba94eb9 DV |
1362 | { |
1363 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1364 | ||
277de95e DV |
1365 | display_pipe_crc_irq_handler(dev, pipe, |
1366 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1367 | I915_READ(PIPE_CRC_RES_2_IVB(pipe)), | |
1368 | I915_READ(PIPE_CRC_RES_3_IVB(pipe)), | |
1369 | I915_READ(PIPE_CRC_RES_4_IVB(pipe)), | |
1370 | I915_READ(PIPE_CRC_RES_5_IVB(pipe))); | |
eba94eb9 | 1371 | } |
5b3a856b | 1372 | |
277de95e | 1373 | static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5b3a856b DV |
1374 | { |
1375 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0b5c5ed0 DV |
1376 | uint32_t res1, res2; |
1377 | ||
1378 | if (INTEL_INFO(dev)->gen >= 3) | |
1379 | res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); | |
1380 | else | |
1381 | res1 = 0; | |
1382 | ||
1383 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
1384 | res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); | |
1385 | else | |
1386 | res2 = 0; | |
5b3a856b | 1387 | |
277de95e DV |
1388 | display_pipe_crc_irq_handler(dev, pipe, |
1389 | I915_READ(PIPE_CRC_RES_RED(pipe)), | |
1390 | I915_READ(PIPE_CRC_RES_GREEN(pipe)), | |
1391 | I915_READ(PIPE_CRC_RES_BLUE(pipe)), | |
1392 | res1, res2); | |
5b3a856b | 1393 | } |
8bf1e9f1 | 1394 | |
1403c0d4 PZ |
1395 | /* The RPS events need forcewake, so we add them to a work queue and mask their |
1396 | * IMR bits until the work is done. Other interrupts can be processed without | |
1397 | * the work queue. */ | |
1398 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) | |
baf02a1f | 1399 | { |
41a05a3a | 1400 | if (pm_iir & GEN6_PM_RPS_EVENTS) { |
59cdb63d | 1401 | spin_lock(&dev_priv->irq_lock); |
41a05a3a | 1402 | dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS; |
4d3b3d5f | 1403 | snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS); |
59cdb63d | 1404 | spin_unlock(&dev_priv->irq_lock); |
2adbee62 DV |
1405 | |
1406 | queue_work(dev_priv->wq, &dev_priv->rps.work); | |
baf02a1f | 1407 | } |
baf02a1f | 1408 | |
1403c0d4 PZ |
1409 | if (HAS_VEBOX(dev_priv->dev)) { |
1410 | if (pm_iir & PM_VEBOX_USER_INTERRUPT) | |
1411 | notify_ring(dev_priv->dev, &dev_priv->ring[VECS]); | |
12638c57 | 1412 | |
1403c0d4 PZ |
1413 | if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) { |
1414 | DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir); | |
1415 | i915_handle_error(dev_priv->dev, false); | |
1416 | } | |
12638c57 | 1417 | } |
baf02a1f BW |
1418 | } |
1419 | ||
ff1f525e | 1420 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
7e231dbe JB |
1421 | { |
1422 | struct drm_device *dev = (struct drm_device *) arg; | |
1423 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1424 | u32 iir, gt_iir, pm_iir; | |
1425 | irqreturn_t ret = IRQ_NONE; | |
1426 | unsigned long irqflags; | |
1427 | int pipe; | |
1428 | u32 pipe_stats[I915_MAX_PIPES]; | |
7e231dbe JB |
1429 | |
1430 | atomic_inc(&dev_priv->irq_received); | |
1431 | ||
7e231dbe JB |
1432 | while (true) { |
1433 | iir = I915_READ(VLV_IIR); | |
1434 | gt_iir = I915_READ(GTIIR); | |
1435 | pm_iir = I915_READ(GEN6_PMIIR); | |
1436 | ||
1437 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) | |
1438 | goto out; | |
1439 | ||
1440 | ret = IRQ_HANDLED; | |
1441 | ||
e7b4c6b1 | 1442 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
7e231dbe JB |
1443 | |
1444 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
1445 | for_each_pipe(pipe) { | |
1446 | int reg = PIPESTAT(pipe); | |
1447 | pipe_stats[pipe] = I915_READ(reg); | |
1448 | ||
1449 | /* | |
1450 | * Clear the PIPE*STAT regs before the IIR | |
1451 | */ | |
1452 | if (pipe_stats[pipe] & 0x8000ffff) { | |
1453 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | |
1454 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | |
1455 | pipe_name(pipe)); | |
1456 | I915_WRITE(reg, pipe_stats[pipe]); | |
1457 | } | |
1458 | } | |
1459 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
1460 | ||
31acc7f5 | 1461 | for_each_pipe(pipe) { |
7b5562d4 | 1462 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) |
31acc7f5 JB |
1463 | drm_handle_vblank(dev, pipe); |
1464 | ||
1465 | if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) { | |
1466 | intel_prepare_page_flip(dev, pipe); | |
1467 | intel_finish_page_flip(dev, pipe); | |
1468 | } | |
4356d586 DV |
1469 | |
1470 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 1471 | i9xx_pipe_crc_irq_handler(dev, pipe); |
31acc7f5 JB |
1472 | } |
1473 | ||
7e231dbe JB |
1474 | /* Consume port. Then clear IIR or we'll miss events */ |
1475 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { | |
1476 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
b543fb04 | 1477 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; |
7e231dbe JB |
1478 | |
1479 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", | |
1480 | hotplug_status); | |
91d131d2 DV |
1481 | |
1482 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); | |
1483 | ||
4aeebd74 DV |
1484 | if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) |
1485 | dp_aux_irq_handler(dev); | |
1486 | ||
7e231dbe JB |
1487 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
1488 | I915_READ(PORT_HOTPLUG_STAT); | |
1489 | } | |
1490 | ||
515ac2bb DV |
1491 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
1492 | gmbus_irq_handler(dev); | |
7e231dbe | 1493 | |
60611c13 | 1494 | if (pm_iir) |
d0ecd7e2 | 1495 | gen6_rps_irq_handler(dev_priv, pm_iir); |
7e231dbe JB |
1496 | |
1497 | I915_WRITE(GTIIR, gt_iir); | |
1498 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
1499 | I915_WRITE(VLV_IIR, iir); | |
1500 | } | |
1501 | ||
1502 | out: | |
1503 | return ret; | |
1504 | } | |
1505 | ||
23e81d69 | 1506 | static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) |
776ad806 JB |
1507 | { |
1508 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 1509 | int pipe; |
b543fb04 | 1510 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; |
776ad806 | 1511 | |
91d131d2 DV |
1512 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx); |
1513 | ||
cfc33bf7 VS |
1514 | if (pch_iir & SDE_AUDIO_POWER_MASK) { |
1515 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> | |
1516 | SDE_AUDIO_POWER_SHIFT); | |
776ad806 | 1517 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
cfc33bf7 VS |
1518 | port_name(port)); |
1519 | } | |
776ad806 | 1520 | |
ce99c256 DV |
1521 | if (pch_iir & SDE_AUX_MASK) |
1522 | dp_aux_irq_handler(dev); | |
1523 | ||
776ad806 | 1524 | if (pch_iir & SDE_GMBUS) |
515ac2bb | 1525 | gmbus_irq_handler(dev); |
776ad806 JB |
1526 | |
1527 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
1528 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
1529 | ||
1530 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
1531 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
1532 | ||
1533 | if (pch_iir & SDE_POISON) | |
1534 | DRM_ERROR("PCH poison interrupt\n"); | |
1535 | ||
9db4a9c7 JB |
1536 | if (pch_iir & SDE_FDI_MASK) |
1537 | for_each_pipe(pipe) | |
1538 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", | |
1539 | pipe_name(pipe), | |
1540 | I915_READ(FDI_RX_IIR(pipe))); | |
776ad806 JB |
1541 | |
1542 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
1543 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
1544 | ||
1545 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
1546 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
1547 | ||
776ad806 | 1548 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
8664281b PZ |
1549 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, |
1550 | false)) | |
1551 | DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n"); | |
1552 | ||
1553 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
1554 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, | |
1555 | false)) | |
1556 | DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n"); | |
1557 | } | |
1558 | ||
1559 | static void ivb_err_int_handler(struct drm_device *dev) | |
1560 | { | |
1561 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1562 | u32 err_int = I915_READ(GEN7_ERR_INT); | |
5a69b89f | 1563 | enum pipe pipe; |
8664281b | 1564 | |
de032bf4 PZ |
1565 | if (err_int & ERR_INT_POISON) |
1566 | DRM_ERROR("Poison interrupt\n"); | |
1567 | ||
5a69b89f DV |
1568 | for_each_pipe(pipe) { |
1569 | if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) { | |
1570 | if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, | |
1571 | false)) | |
1572 | DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n", | |
1573 | pipe_name(pipe)); | |
1574 | } | |
8bf1e9f1 | 1575 | |
5a69b89f DV |
1576 | if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { |
1577 | if (IS_IVYBRIDGE(dev)) | |
277de95e | 1578 | ivb_pipe_crc_irq_handler(dev, pipe); |
5a69b89f | 1579 | else |
277de95e | 1580 | hsw_pipe_crc_irq_handler(dev, pipe); |
5a69b89f DV |
1581 | } |
1582 | } | |
8bf1e9f1 | 1583 | |
8664281b PZ |
1584 | I915_WRITE(GEN7_ERR_INT, err_int); |
1585 | } | |
1586 | ||
1587 | static void cpt_serr_int_handler(struct drm_device *dev) | |
1588 | { | |
1589 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1590 | u32 serr_int = I915_READ(SERR_INT); | |
1591 | ||
de032bf4 PZ |
1592 | if (serr_int & SERR_INT_POISON) |
1593 | DRM_ERROR("PCH poison interrupt\n"); | |
1594 | ||
8664281b PZ |
1595 | if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) |
1596 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, | |
1597 | false)) | |
1598 | DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n"); | |
1599 | ||
1600 | if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) | |
1601 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, | |
1602 | false)) | |
1603 | DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n"); | |
1604 | ||
1605 | if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) | |
1606 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C, | |
1607 | false)) | |
1608 | DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n"); | |
1609 | ||
1610 | I915_WRITE(SERR_INT, serr_int); | |
776ad806 JB |
1611 | } |
1612 | ||
23e81d69 AJ |
1613 | static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) |
1614 | { | |
1615 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1616 | int pipe; | |
b543fb04 | 1617 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; |
23e81d69 | 1618 | |
91d131d2 DV |
1619 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt); |
1620 | ||
cfc33bf7 VS |
1621 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { |
1622 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> | |
1623 | SDE_AUDIO_POWER_SHIFT_CPT); | |
1624 | DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", | |
1625 | port_name(port)); | |
1626 | } | |
23e81d69 AJ |
1627 | |
1628 | if (pch_iir & SDE_AUX_MASK_CPT) | |
ce99c256 | 1629 | dp_aux_irq_handler(dev); |
23e81d69 AJ |
1630 | |
1631 | if (pch_iir & SDE_GMBUS_CPT) | |
515ac2bb | 1632 | gmbus_irq_handler(dev); |
23e81d69 AJ |
1633 | |
1634 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) | |
1635 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); | |
1636 | ||
1637 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) | |
1638 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); | |
1639 | ||
1640 | if (pch_iir & SDE_FDI_MASK_CPT) | |
1641 | for_each_pipe(pipe) | |
1642 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", | |
1643 | pipe_name(pipe), | |
1644 | I915_READ(FDI_RX_IIR(pipe))); | |
8664281b PZ |
1645 | |
1646 | if (pch_iir & SDE_ERROR_CPT) | |
1647 | cpt_serr_int_handler(dev); | |
23e81d69 AJ |
1648 | } |
1649 | ||
c008bc6e PZ |
1650 | static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) |
1651 | { | |
1652 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40da17c2 | 1653 | enum pipe pipe; |
c008bc6e PZ |
1654 | |
1655 | if (de_iir & DE_AUX_CHANNEL_A) | |
1656 | dp_aux_irq_handler(dev); | |
1657 | ||
1658 | if (de_iir & DE_GSE) | |
1659 | intel_opregion_asle_intr(dev); | |
1660 | ||
c008bc6e PZ |
1661 | if (de_iir & DE_POISON) |
1662 | DRM_ERROR("Poison interrupt\n"); | |
1663 | ||
40da17c2 DV |
1664 | for_each_pipe(pipe) { |
1665 | if (de_iir & DE_PIPE_VBLANK(pipe)) | |
1666 | drm_handle_vblank(dev, pipe); | |
5b3a856b | 1667 | |
40da17c2 DV |
1668 | if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) |
1669 | if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
1670 | DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n", | |
1671 | pipe_name(pipe)); | |
5b3a856b | 1672 | |
40da17c2 DV |
1673 | if (de_iir & DE_PIPE_CRC_DONE(pipe)) |
1674 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
c008bc6e | 1675 | |
40da17c2 DV |
1676 | /* plane/pipes map 1:1 on ilk+ */ |
1677 | if (de_iir & DE_PLANE_FLIP_DONE(pipe)) { | |
1678 | intel_prepare_page_flip(dev, pipe); | |
1679 | intel_finish_page_flip_plane(dev, pipe); | |
1680 | } | |
c008bc6e PZ |
1681 | } |
1682 | ||
1683 | /* check event from PCH */ | |
1684 | if (de_iir & DE_PCH_EVENT) { | |
1685 | u32 pch_iir = I915_READ(SDEIIR); | |
1686 | ||
1687 | if (HAS_PCH_CPT(dev)) | |
1688 | cpt_irq_handler(dev, pch_iir); | |
1689 | else | |
1690 | ibx_irq_handler(dev, pch_iir); | |
1691 | ||
1692 | /* should clear PCH hotplug event before clear CPU irq */ | |
1693 | I915_WRITE(SDEIIR, pch_iir); | |
1694 | } | |
1695 | ||
1696 | if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) | |
1697 | ironlake_rps_change_irq_handler(dev); | |
1698 | } | |
1699 | ||
9719fb98 PZ |
1700 | static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir) |
1701 | { | |
1702 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3b6c42e8 | 1703 | enum pipe i; |
9719fb98 PZ |
1704 | |
1705 | if (de_iir & DE_ERR_INT_IVB) | |
1706 | ivb_err_int_handler(dev); | |
1707 | ||
1708 | if (de_iir & DE_AUX_CHANNEL_A_IVB) | |
1709 | dp_aux_irq_handler(dev); | |
1710 | ||
1711 | if (de_iir & DE_GSE_IVB) | |
1712 | intel_opregion_asle_intr(dev); | |
1713 | ||
3b6c42e8 | 1714 | for_each_pipe(i) { |
40da17c2 | 1715 | if (de_iir & (DE_PIPE_VBLANK_IVB(i))) |
9719fb98 | 1716 | drm_handle_vblank(dev, i); |
40da17c2 DV |
1717 | |
1718 | /* plane/pipes map 1:1 on ilk+ */ | |
1719 | if (de_iir & DE_PLANE_FLIP_DONE_IVB(i)) { | |
9719fb98 PZ |
1720 | intel_prepare_page_flip(dev, i); |
1721 | intel_finish_page_flip_plane(dev, i); | |
1722 | } | |
1723 | } | |
1724 | ||
1725 | /* check event from PCH */ | |
1726 | if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) { | |
1727 | u32 pch_iir = I915_READ(SDEIIR); | |
1728 | ||
1729 | cpt_irq_handler(dev, pch_iir); | |
1730 | ||
1731 | /* clear PCH hotplug event before clear CPU irq */ | |
1732 | I915_WRITE(SDEIIR, pch_iir); | |
1733 | } | |
1734 | } | |
1735 | ||
f1af8fc1 | 1736 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
b1f14ad0 JB |
1737 | { |
1738 | struct drm_device *dev = (struct drm_device *) arg; | |
1739 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
f1af8fc1 | 1740 | u32 de_iir, gt_iir, de_ier, sde_ier = 0; |
0e43406b | 1741 | irqreturn_t ret = IRQ_NONE; |
b1f14ad0 JB |
1742 | |
1743 | atomic_inc(&dev_priv->irq_received); | |
1744 | ||
8664281b PZ |
1745 | /* We get interrupts on unclaimed registers, so check for this before we |
1746 | * do any I915_{READ,WRITE}. */ | |
907b28c5 | 1747 | intel_uncore_check_errors(dev); |
8664281b | 1748 | |
b1f14ad0 JB |
1749 | /* disable master interrupt before clearing iir */ |
1750 | de_ier = I915_READ(DEIER); | |
1751 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
23a78516 | 1752 | POSTING_READ(DEIER); |
b1f14ad0 | 1753 | |
44498aea PZ |
1754 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
1755 | * interrupts will will be stored on its back queue, and then we'll be | |
1756 | * able to process them after we restore SDEIER (as soon as we restore | |
1757 | * it, we'll get an interrupt if SDEIIR still has something to process | |
1758 | * due to its back queue). */ | |
ab5c608b BW |
1759 | if (!HAS_PCH_NOP(dev)) { |
1760 | sde_ier = I915_READ(SDEIER); | |
1761 | I915_WRITE(SDEIER, 0); | |
1762 | POSTING_READ(SDEIER); | |
1763 | } | |
44498aea | 1764 | |
b1f14ad0 | 1765 | gt_iir = I915_READ(GTIIR); |
0e43406b | 1766 | if (gt_iir) { |
d8fc8a47 | 1767 | if (INTEL_INFO(dev)->gen >= 6) |
f1af8fc1 | 1768 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
d8fc8a47 PZ |
1769 | else |
1770 | ilk_gt_irq_handler(dev, dev_priv, gt_iir); | |
0e43406b CW |
1771 | I915_WRITE(GTIIR, gt_iir); |
1772 | ret = IRQ_HANDLED; | |
b1f14ad0 JB |
1773 | } |
1774 | ||
0e43406b CW |
1775 | de_iir = I915_READ(DEIIR); |
1776 | if (de_iir) { | |
f1af8fc1 PZ |
1777 | if (INTEL_INFO(dev)->gen >= 7) |
1778 | ivb_display_irq_handler(dev, de_iir); | |
1779 | else | |
1780 | ilk_display_irq_handler(dev, de_iir); | |
0e43406b CW |
1781 | I915_WRITE(DEIIR, de_iir); |
1782 | ret = IRQ_HANDLED; | |
b1f14ad0 JB |
1783 | } |
1784 | ||
f1af8fc1 PZ |
1785 | if (INTEL_INFO(dev)->gen >= 6) { |
1786 | u32 pm_iir = I915_READ(GEN6_PMIIR); | |
1787 | if (pm_iir) { | |
1403c0d4 | 1788 | gen6_rps_irq_handler(dev_priv, pm_iir); |
f1af8fc1 PZ |
1789 | I915_WRITE(GEN6_PMIIR, pm_iir); |
1790 | ret = IRQ_HANDLED; | |
1791 | } | |
0e43406b | 1792 | } |
b1f14ad0 | 1793 | |
b1f14ad0 JB |
1794 | I915_WRITE(DEIER, de_ier); |
1795 | POSTING_READ(DEIER); | |
ab5c608b BW |
1796 | if (!HAS_PCH_NOP(dev)) { |
1797 | I915_WRITE(SDEIER, sde_ier); | |
1798 | POSTING_READ(SDEIER); | |
1799 | } | |
b1f14ad0 JB |
1800 | |
1801 | return ret; | |
1802 | } | |
1803 | ||
abd58f01 BW |
1804 | static irqreturn_t gen8_irq_handler(int irq, void *arg) |
1805 | { | |
1806 | struct drm_device *dev = arg; | |
1807 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1808 | u32 master_ctl; | |
1809 | irqreturn_t ret = IRQ_NONE; | |
1810 | uint32_t tmp = 0; | |
c42664cc | 1811 | enum pipe pipe; |
abd58f01 BW |
1812 | |
1813 | atomic_inc(&dev_priv->irq_received); | |
1814 | ||
1815 | master_ctl = I915_READ(GEN8_MASTER_IRQ); | |
1816 | master_ctl &= ~GEN8_MASTER_IRQ_CONTROL; | |
1817 | if (!master_ctl) | |
1818 | return IRQ_NONE; | |
1819 | ||
1820 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
1821 | POSTING_READ(GEN8_MASTER_IRQ); | |
1822 | ||
1823 | ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl); | |
1824 | ||
1825 | if (master_ctl & GEN8_DE_MISC_IRQ) { | |
1826 | tmp = I915_READ(GEN8_DE_MISC_IIR); | |
1827 | if (tmp & GEN8_DE_MISC_GSE) | |
1828 | intel_opregion_asle_intr(dev); | |
1829 | else if (tmp) | |
1830 | DRM_ERROR("Unexpected DE Misc interrupt\n"); | |
1831 | else | |
1832 | DRM_ERROR("The master control interrupt lied (DE MISC)!\n"); | |
1833 | ||
1834 | if (tmp) { | |
1835 | I915_WRITE(GEN8_DE_MISC_IIR, tmp); | |
1836 | ret = IRQ_HANDLED; | |
1837 | } | |
1838 | } | |
1839 | ||
6d766f02 DV |
1840 | if (master_ctl & GEN8_DE_PORT_IRQ) { |
1841 | tmp = I915_READ(GEN8_DE_PORT_IIR); | |
1842 | if (tmp & GEN8_AUX_CHANNEL_A) | |
1843 | dp_aux_irq_handler(dev); | |
1844 | else if (tmp) | |
1845 | DRM_ERROR("Unexpected DE Port interrupt\n"); | |
1846 | else | |
1847 | DRM_ERROR("The master control interrupt lied (DE PORT)!\n"); | |
1848 | ||
1849 | if (tmp) { | |
1850 | I915_WRITE(GEN8_DE_PORT_IIR, tmp); | |
1851 | ret = IRQ_HANDLED; | |
1852 | } | |
1853 | } | |
1854 | ||
c42664cc DV |
1855 | for_each_pipe(pipe) { |
1856 | uint32_t pipe_iir; | |
abd58f01 | 1857 | |
c42664cc DV |
1858 | if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) |
1859 | continue; | |
abd58f01 | 1860 | |
c42664cc DV |
1861 | pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); |
1862 | if (pipe_iir & GEN8_PIPE_VBLANK) | |
1863 | drm_handle_vblank(dev, pipe); | |
abd58f01 | 1864 | |
c42664cc DV |
1865 | if (pipe_iir & GEN8_PIPE_FLIP_DONE) { |
1866 | intel_prepare_page_flip(dev, pipe); | |
1867 | intel_finish_page_flip_plane(dev, pipe); | |
abd58f01 | 1868 | } |
c42664cc | 1869 | |
0fbe7870 DV |
1870 | if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE) |
1871 | hsw_pipe_crc_irq_handler(dev, pipe); | |
1872 | ||
38d83c96 DV |
1873 | if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) { |
1874 | if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, | |
1875 | false)) | |
1876 | DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n", | |
1877 | pipe_name(pipe)); | |
1878 | } | |
1879 | ||
30100f2b DV |
1880 | if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) { |
1881 | DRM_ERROR("Fault errors on pipe %c\n: 0x%08x", | |
1882 | pipe_name(pipe), | |
1883 | pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS); | |
1884 | } | |
c42664cc DV |
1885 | |
1886 | if (pipe_iir) { | |
1887 | ret = IRQ_HANDLED; | |
1888 | I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir); | |
1889 | } else | |
abd58f01 BW |
1890 | DRM_ERROR("The master control interrupt lied (DE PIPE)!\n"); |
1891 | } | |
1892 | ||
92d03a80 DV |
1893 | if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) { |
1894 | /* | |
1895 | * FIXME(BDW): Assume for now that the new interrupt handling | |
1896 | * scheme also closed the SDE interrupt handling race we've seen | |
1897 | * on older pch-split platforms. But this needs testing. | |
1898 | */ | |
1899 | u32 pch_iir = I915_READ(SDEIIR); | |
1900 | ||
1901 | cpt_irq_handler(dev, pch_iir); | |
1902 | ||
1903 | if (pch_iir) { | |
1904 | I915_WRITE(SDEIIR, pch_iir); | |
1905 | ret = IRQ_HANDLED; | |
1906 | } | |
1907 | } | |
1908 | ||
abd58f01 BW |
1909 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
1910 | POSTING_READ(GEN8_MASTER_IRQ); | |
1911 | ||
1912 | return ret; | |
1913 | } | |
1914 | ||
17e1df07 DV |
1915 | static void i915_error_wake_up(struct drm_i915_private *dev_priv, |
1916 | bool reset_completed) | |
1917 | { | |
1918 | struct intel_ring_buffer *ring; | |
1919 | int i; | |
1920 | ||
1921 | /* | |
1922 | * Notify all waiters for GPU completion events that reset state has | |
1923 | * been changed, and that they need to restart their wait after | |
1924 | * checking for potential errors (and bail out to drop locks if there is | |
1925 | * a gpu reset pending so that i915_error_work_func can acquire them). | |
1926 | */ | |
1927 | ||
1928 | /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */ | |
1929 | for_each_ring(ring, dev_priv, i) | |
1930 | wake_up_all(&ring->irq_queue); | |
1931 | ||
1932 | /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */ | |
1933 | wake_up_all(&dev_priv->pending_flip_queue); | |
1934 | ||
1935 | /* | |
1936 | * Signal tasks blocked in i915_gem_wait_for_error that the pending | |
1937 | * reset state is cleared. | |
1938 | */ | |
1939 | if (reset_completed) | |
1940 | wake_up_all(&dev_priv->gpu_error.reset_queue); | |
1941 | } | |
1942 | ||
8a905236 JB |
1943 | /** |
1944 | * i915_error_work_func - do process context error handling work | |
1945 | * @work: work struct | |
1946 | * | |
1947 | * Fire an error uevent so userspace can see that a hang or error | |
1948 | * was detected. | |
1949 | */ | |
1950 | static void i915_error_work_func(struct work_struct *work) | |
1951 | { | |
1f83fee0 DV |
1952 | struct i915_gpu_error *error = container_of(work, struct i915_gpu_error, |
1953 | work); | |
1954 | drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t, | |
1955 | gpu_error); | |
8a905236 | 1956 | struct drm_device *dev = dev_priv->dev; |
cce723ed BW |
1957 | char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; |
1958 | char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; | |
1959 | char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; | |
17e1df07 | 1960 | int ret; |
8a905236 | 1961 | |
5bdebb18 | 1962 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event); |
f316a42c | 1963 | |
7db0ba24 DV |
1964 | /* |
1965 | * Note that there's only one work item which does gpu resets, so we | |
1966 | * need not worry about concurrent gpu resets potentially incrementing | |
1967 | * error->reset_counter twice. We only need to take care of another | |
1968 | * racing irq/hangcheck declaring the gpu dead for a second time. A | |
1969 | * quick check for that is good enough: schedule_work ensures the | |
1970 | * correct ordering between hang detection and this work item, and since | |
1971 | * the reset in-progress bit is only ever set by code outside of this | |
1972 | * work we don't need to worry about any other races. | |
1973 | */ | |
1974 | if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) { | |
f803aa55 | 1975 | DRM_DEBUG_DRIVER("resetting chip\n"); |
5bdebb18 | 1976 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, |
7db0ba24 | 1977 | reset_event); |
1f83fee0 | 1978 | |
17e1df07 DV |
1979 | /* |
1980 | * All state reset _must_ be completed before we update the | |
1981 | * reset counter, for otherwise waiters might miss the reset | |
1982 | * pending state and not properly drop locks, resulting in | |
1983 | * deadlocks with the reset work. | |
1984 | */ | |
f69061be DV |
1985 | ret = i915_reset(dev); |
1986 | ||
17e1df07 DV |
1987 | intel_display_handle_reset(dev); |
1988 | ||
f69061be DV |
1989 | if (ret == 0) { |
1990 | /* | |
1991 | * After all the gem state is reset, increment the reset | |
1992 | * counter and wake up everyone waiting for the reset to | |
1993 | * complete. | |
1994 | * | |
1995 | * Since unlock operations are a one-sided barrier only, | |
1996 | * we need to insert a barrier here to order any seqno | |
1997 | * updates before | |
1998 | * the counter increment. | |
1999 | */ | |
2000 | smp_mb__before_atomic_inc(); | |
2001 | atomic_inc(&dev_priv->gpu_error.reset_counter); | |
2002 | ||
5bdebb18 | 2003 | kobject_uevent_env(&dev->primary->kdev->kobj, |
f69061be | 2004 | KOBJ_CHANGE, reset_done_event); |
1f83fee0 | 2005 | } else { |
2ac0f450 | 2006 | atomic_set_mask(I915_WEDGED, &error->reset_counter); |
f316a42c | 2007 | } |
1f83fee0 | 2008 | |
17e1df07 DV |
2009 | /* |
2010 | * Note: The wake_up also serves as a memory barrier so that | |
2011 | * waiters see the update value of the reset counter atomic_t. | |
2012 | */ | |
2013 | i915_error_wake_up(dev_priv, true); | |
f316a42c | 2014 | } |
8a905236 JB |
2015 | } |
2016 | ||
35aed2e6 | 2017 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
2018 | { |
2019 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bd9854f9 | 2020 | uint32_t instdone[I915_NUM_INSTDONE_REG]; |
8a905236 | 2021 | u32 eir = I915_READ(EIR); |
050ee91f | 2022 | int pipe, i; |
8a905236 | 2023 | |
35aed2e6 CW |
2024 | if (!eir) |
2025 | return; | |
8a905236 | 2026 | |
a70491cc | 2027 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
8a905236 | 2028 | |
bd9854f9 BW |
2029 | i915_get_extra_instdone(dev, instdone); |
2030 | ||
8a905236 JB |
2031 | if (IS_G4X(dev)) { |
2032 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
2033 | u32 ipeir = I915_READ(IPEIR_I965); | |
2034 | ||
a70491cc JP |
2035 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2036 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
050ee91f BW |
2037 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2038 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a70491cc | 2039 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2040 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2041 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2042 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2043 | } |
2044 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
2045 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2046 | pr_err("page table error\n"); |
2047 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2048 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2049 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2050 | } |
2051 | } | |
2052 | ||
a6c45cf0 | 2053 | if (!IS_GEN2(dev)) { |
8a905236 JB |
2054 | if (eir & I915_ERROR_PAGE_TABLE) { |
2055 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2056 | pr_err("page table error\n"); |
2057 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2058 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2059 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2060 | } |
2061 | } | |
2062 | ||
2063 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
a70491cc | 2064 | pr_err("memory refresh error:\n"); |
9db4a9c7 | 2065 | for_each_pipe(pipe) |
a70491cc | 2066 | pr_err("pipe %c stat: 0x%08x\n", |
9db4a9c7 | 2067 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
8a905236 JB |
2068 | /* pipestat has already been acked */ |
2069 | } | |
2070 | if (eir & I915_ERROR_INSTRUCTION) { | |
a70491cc JP |
2071 | pr_err("instruction error\n"); |
2072 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); | |
050ee91f BW |
2073 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2074 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a6c45cf0 | 2075 | if (INTEL_INFO(dev)->gen < 4) { |
8a905236 JB |
2076 | u32 ipeir = I915_READ(IPEIR); |
2077 | ||
a70491cc JP |
2078 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
2079 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); | |
a70491cc | 2080 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); |
8a905236 | 2081 | I915_WRITE(IPEIR, ipeir); |
3143a2bf | 2082 | POSTING_READ(IPEIR); |
8a905236 JB |
2083 | } else { |
2084 | u32 ipeir = I915_READ(IPEIR_I965); | |
2085 | ||
a70491cc JP |
2086 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2087 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
a70491cc | 2088 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2089 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2090 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2091 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2092 | } |
2093 | } | |
2094 | ||
2095 | I915_WRITE(EIR, eir); | |
3143a2bf | 2096 | POSTING_READ(EIR); |
8a905236 JB |
2097 | eir = I915_READ(EIR); |
2098 | if (eir) { | |
2099 | /* | |
2100 | * some errors might have become stuck, | |
2101 | * mask them. | |
2102 | */ | |
2103 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
2104 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
2105 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2106 | } | |
35aed2e6 CW |
2107 | } |
2108 | ||
2109 | /** | |
2110 | * i915_handle_error - handle an error interrupt | |
2111 | * @dev: drm device | |
2112 | * | |
2113 | * Do some basic checking of regsiter state at error interrupt time and | |
2114 | * dump it to the syslog. Also call i915_capture_error_state() to make | |
2115 | * sure we get a record and make it available in debugfs. Fire a uevent | |
2116 | * so userspace knows something bad happened (should trigger collection | |
2117 | * of a ring dump etc.). | |
2118 | */ | |
527f9e90 | 2119 | void i915_handle_error(struct drm_device *dev, bool wedged) |
35aed2e6 CW |
2120 | { |
2121 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2122 | ||
2123 | i915_capture_error_state(dev); | |
2124 | i915_report_and_clear_eir(dev); | |
8a905236 | 2125 | |
ba1234d1 | 2126 | if (wedged) { |
f69061be DV |
2127 | atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG, |
2128 | &dev_priv->gpu_error.reset_counter); | |
ba1234d1 | 2129 | |
11ed50ec | 2130 | /* |
17e1df07 DV |
2131 | * Wakeup waiting processes so that the reset work function |
2132 | * i915_error_work_func doesn't deadlock trying to grab various | |
2133 | * locks. By bumping the reset counter first, the woken | |
2134 | * processes will see a reset in progress and back off, | |
2135 | * releasing their locks and then wait for the reset completion. | |
2136 | * We must do this for _all_ gpu waiters that might hold locks | |
2137 | * that the reset work needs to acquire. | |
2138 | * | |
2139 | * Note: The wake_up serves as the required memory barrier to | |
2140 | * ensure that the waiters see the updated value of the reset | |
2141 | * counter atomic_t. | |
11ed50ec | 2142 | */ |
17e1df07 | 2143 | i915_error_wake_up(dev_priv, false); |
11ed50ec BG |
2144 | } |
2145 | ||
122f46ba DV |
2146 | /* |
2147 | * Our reset work can grab modeset locks (since it needs to reset the | |
2148 | * state of outstanding pagelips). Hence it must not be run on our own | |
2149 | * dev-priv->wq work queue for otherwise the flush_work in the pageflip | |
2150 | * code will deadlock. | |
2151 | */ | |
2152 | schedule_work(&dev_priv->gpu_error.work); | |
8a905236 JB |
2153 | } |
2154 | ||
21ad8330 | 2155 | static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe) |
4e5359cd SF |
2156 | { |
2157 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2158 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
2159 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 2160 | struct drm_i915_gem_object *obj; |
4e5359cd SF |
2161 | struct intel_unpin_work *work; |
2162 | unsigned long flags; | |
2163 | bool stall_detected; | |
2164 | ||
2165 | /* Ignore early vblank irqs */ | |
2166 | if (intel_crtc == NULL) | |
2167 | return; | |
2168 | ||
2169 | spin_lock_irqsave(&dev->event_lock, flags); | |
2170 | work = intel_crtc->unpin_work; | |
2171 | ||
e7d841ca CW |
2172 | if (work == NULL || |
2173 | atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE || | |
2174 | !work->enable_stall_check) { | |
4e5359cd SF |
2175 | /* Either the pending flip IRQ arrived, or we're too early. Don't check */ |
2176 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2177 | return; | |
2178 | } | |
2179 | ||
2180 | /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ | |
05394f39 | 2181 | obj = work->pending_flip_obj; |
a6c45cf0 | 2182 | if (INTEL_INFO(dev)->gen >= 4) { |
9db4a9c7 | 2183 | int dspsurf = DSPSURF(intel_crtc->plane); |
446f2545 | 2184 | stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) == |
f343c5f6 | 2185 | i915_gem_obj_ggtt_offset(obj); |
4e5359cd | 2186 | } else { |
9db4a9c7 | 2187 | int dspaddr = DSPADDR(intel_crtc->plane); |
f343c5f6 | 2188 | stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) + |
01f2c773 | 2189 | crtc->y * crtc->fb->pitches[0] + |
4e5359cd SF |
2190 | crtc->x * crtc->fb->bits_per_pixel/8); |
2191 | } | |
2192 | ||
2193 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2194 | ||
2195 | if (stall_detected) { | |
2196 | DRM_DEBUG_DRIVER("Pageflip stall detected\n"); | |
2197 | intel_prepare_page_flip(dev, intel_crtc->plane); | |
2198 | } | |
2199 | } | |
2200 | ||
42f52ef8 KP |
2201 | /* Called from drm generic code, passed 'crtc' which |
2202 | * we use as a pipe index | |
2203 | */ | |
f71d4af4 | 2204 | static int i915_enable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 JB |
2205 | { |
2206 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 2207 | unsigned long irqflags; |
71e0ffa5 | 2208 | |
5eddb70b | 2209 | if (!i915_pipe_enabled(dev, pipe)) |
71e0ffa5 | 2210 | return -EINVAL; |
0a3e67a4 | 2211 | |
1ec14ad3 | 2212 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2213 | if (INTEL_INFO(dev)->gen >= 4) |
7c463586 KP |
2214 | i915_enable_pipestat(dev_priv, pipe, |
2215 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 2216 | else |
7c463586 KP |
2217 | i915_enable_pipestat(dev_priv, pipe, |
2218 | PIPE_VBLANK_INTERRUPT_ENABLE); | |
8692d00e CW |
2219 | |
2220 | /* maintain vblank delivery even in deep C-states */ | |
2221 | if (dev_priv->info->gen == 3) | |
6b26c86d | 2222 | I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS)); |
1ec14ad3 | 2223 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
8692d00e | 2224 | |
0a3e67a4 JB |
2225 | return 0; |
2226 | } | |
2227 | ||
f71d4af4 | 2228 | static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
f796cf8f JB |
2229 | { |
2230 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2231 | unsigned long irqflags; | |
b518421f | 2232 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2233 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2234 | |
2235 | if (!i915_pipe_enabled(dev, pipe)) | |
2236 | return -EINVAL; | |
2237 | ||
2238 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 2239 | ironlake_enable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2240 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2241 | ||
2242 | return 0; | |
2243 | } | |
2244 | ||
7e231dbe JB |
2245 | static int valleyview_enable_vblank(struct drm_device *dev, int pipe) |
2246 | { | |
2247 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2248 | unsigned long irqflags; | |
31acc7f5 | 2249 | u32 imr; |
7e231dbe JB |
2250 | |
2251 | if (!i915_pipe_enabled(dev, pipe)) | |
2252 | return -EINVAL; | |
2253 | ||
2254 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
7e231dbe | 2255 | imr = I915_READ(VLV_IMR); |
3b6c42e8 | 2256 | if (pipe == PIPE_A) |
7e231dbe | 2257 | imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; |
31acc7f5 | 2258 | else |
7e231dbe | 2259 | imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
7e231dbe | 2260 | I915_WRITE(VLV_IMR, imr); |
31acc7f5 JB |
2261 | i915_enable_pipestat(dev_priv, pipe, |
2262 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
7e231dbe JB |
2263 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2264 | ||
2265 | return 0; | |
2266 | } | |
2267 | ||
abd58f01 BW |
2268 | static int gen8_enable_vblank(struct drm_device *dev, int pipe) |
2269 | { | |
2270 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2271 | unsigned long irqflags; | |
abd58f01 BW |
2272 | |
2273 | if (!i915_pipe_enabled(dev, pipe)) | |
2274 | return -EINVAL; | |
2275 | ||
2276 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
7167d7c6 DV |
2277 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK; |
2278 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2279 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2280 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2281 | return 0; | |
2282 | } | |
2283 | ||
42f52ef8 KP |
2284 | /* Called from drm generic code, passed 'crtc' which |
2285 | * we use as a pipe index | |
2286 | */ | |
f71d4af4 | 2287 | static void i915_disable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 JB |
2288 | { |
2289 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 2290 | unsigned long irqflags; |
0a3e67a4 | 2291 | |
1ec14ad3 | 2292 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
8692d00e | 2293 | if (dev_priv->info->gen == 3) |
6b26c86d | 2294 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS)); |
8692d00e | 2295 | |
f796cf8f JB |
2296 | i915_disable_pipestat(dev_priv, pipe, |
2297 | PIPE_VBLANK_INTERRUPT_ENABLE | | |
2298 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
2299 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
2300 | } | |
2301 | ||
f71d4af4 | 2302 | static void ironlake_disable_vblank(struct drm_device *dev, int pipe) |
f796cf8f JB |
2303 | { |
2304 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2305 | unsigned long irqflags; | |
b518421f | 2306 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2307 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2308 | |
2309 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 2310 | ironlake_disable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2311 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2312 | } | |
2313 | ||
7e231dbe JB |
2314 | static void valleyview_disable_vblank(struct drm_device *dev, int pipe) |
2315 | { | |
2316 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2317 | unsigned long irqflags; | |
31acc7f5 | 2318 | u32 imr; |
7e231dbe JB |
2319 | |
2320 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 JB |
2321 | i915_disable_pipestat(dev_priv, pipe, |
2322 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
7e231dbe | 2323 | imr = I915_READ(VLV_IMR); |
3b6c42e8 | 2324 | if (pipe == PIPE_A) |
7e231dbe | 2325 | imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; |
31acc7f5 | 2326 | else |
7e231dbe | 2327 | imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
7e231dbe | 2328 | I915_WRITE(VLV_IMR, imr); |
7e231dbe JB |
2329 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2330 | } | |
2331 | ||
abd58f01 BW |
2332 | static void gen8_disable_vblank(struct drm_device *dev, int pipe) |
2333 | { | |
2334 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2335 | unsigned long irqflags; | |
abd58f01 BW |
2336 | |
2337 | if (!i915_pipe_enabled(dev, pipe)) | |
2338 | return; | |
2339 | ||
2340 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
7167d7c6 DV |
2341 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK; |
2342 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2343 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2344 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2345 | } | |
2346 | ||
893eead0 CW |
2347 | static u32 |
2348 | ring_last_seqno(struct intel_ring_buffer *ring) | |
852835f3 | 2349 | { |
893eead0 CW |
2350 | return list_entry(ring->request_list.prev, |
2351 | struct drm_i915_gem_request, list)->seqno; | |
2352 | } | |
2353 | ||
9107e9d2 CW |
2354 | static bool |
2355 | ring_idle(struct intel_ring_buffer *ring, u32 seqno) | |
2356 | { | |
2357 | return (list_empty(&ring->request_list) || | |
2358 | i915_seqno_passed(seqno, ring_last_seqno(ring))); | |
f65d9421 BG |
2359 | } |
2360 | ||
6274f212 CW |
2361 | static struct intel_ring_buffer * |
2362 | semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno) | |
a24a11e6 CW |
2363 | { |
2364 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
6274f212 | 2365 | u32 cmd, ipehr, acthd, acthd_min; |
a24a11e6 CW |
2366 | |
2367 | ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); | |
2368 | if ((ipehr & ~(0x3 << 16)) != | |
2369 | (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER)) | |
6274f212 | 2370 | return NULL; |
a24a11e6 CW |
2371 | |
2372 | /* ACTHD is likely pointing to the dword after the actual command, | |
2373 | * so scan backwards until we find the MBOX. | |
2374 | */ | |
6274f212 | 2375 | acthd = intel_ring_get_active_head(ring) & HEAD_ADDR; |
a24a11e6 CW |
2376 | acthd_min = max((int)acthd - 3 * 4, 0); |
2377 | do { | |
2378 | cmd = ioread32(ring->virtual_start + acthd); | |
2379 | if (cmd == ipehr) | |
2380 | break; | |
2381 | ||
2382 | acthd -= 4; | |
2383 | if (acthd < acthd_min) | |
6274f212 | 2384 | return NULL; |
a24a11e6 CW |
2385 | } while (1); |
2386 | ||
6274f212 CW |
2387 | *seqno = ioread32(ring->virtual_start+acthd+4)+1; |
2388 | return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3]; | |
a24a11e6 CW |
2389 | } |
2390 | ||
6274f212 CW |
2391 | static int semaphore_passed(struct intel_ring_buffer *ring) |
2392 | { | |
2393 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
2394 | struct intel_ring_buffer *signaller; | |
2395 | u32 seqno, ctl; | |
2396 | ||
2397 | ring->hangcheck.deadlock = true; | |
2398 | ||
2399 | signaller = semaphore_waits_for(ring, &seqno); | |
2400 | if (signaller == NULL || signaller->hangcheck.deadlock) | |
2401 | return -1; | |
2402 | ||
2403 | /* cursory check for an unkickable deadlock */ | |
2404 | ctl = I915_READ_CTL(signaller); | |
2405 | if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0) | |
2406 | return -1; | |
2407 | ||
2408 | return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno); | |
2409 | } | |
2410 | ||
2411 | static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) | |
2412 | { | |
2413 | struct intel_ring_buffer *ring; | |
2414 | int i; | |
2415 | ||
2416 | for_each_ring(ring, dev_priv, i) | |
2417 | ring->hangcheck.deadlock = false; | |
2418 | } | |
2419 | ||
ad8beaea MK |
2420 | static enum intel_ring_hangcheck_action |
2421 | ring_stuck(struct intel_ring_buffer *ring, u32 acthd) | |
1ec14ad3 CW |
2422 | { |
2423 | struct drm_device *dev = ring->dev; | |
2424 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9107e9d2 CW |
2425 | u32 tmp; |
2426 | ||
6274f212 | 2427 | if (ring->hangcheck.acthd != acthd) |
f2f4d82f | 2428 | return HANGCHECK_ACTIVE; |
6274f212 | 2429 | |
9107e9d2 | 2430 | if (IS_GEN2(dev)) |
f2f4d82f | 2431 | return HANGCHECK_HUNG; |
9107e9d2 CW |
2432 | |
2433 | /* Is the chip hanging on a WAIT_FOR_EVENT? | |
2434 | * If so we can simply poke the RB_WAIT bit | |
2435 | * and break the hang. This should work on | |
2436 | * all but the second generation chipsets. | |
2437 | */ | |
2438 | tmp = I915_READ_CTL(ring); | |
1ec14ad3 CW |
2439 | if (tmp & RING_WAIT) { |
2440 | DRM_ERROR("Kicking stuck wait on %s\n", | |
2441 | ring->name); | |
09e14bf3 | 2442 | i915_handle_error(dev, false); |
1ec14ad3 | 2443 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2444 | return HANGCHECK_KICK; |
6274f212 CW |
2445 | } |
2446 | ||
2447 | if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { | |
2448 | switch (semaphore_passed(ring)) { | |
2449 | default: | |
f2f4d82f | 2450 | return HANGCHECK_HUNG; |
6274f212 CW |
2451 | case 1: |
2452 | DRM_ERROR("Kicking stuck semaphore on %s\n", | |
2453 | ring->name); | |
09e14bf3 | 2454 | i915_handle_error(dev, false); |
6274f212 | 2455 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2456 | return HANGCHECK_KICK; |
6274f212 | 2457 | case 0: |
f2f4d82f | 2458 | return HANGCHECK_WAIT; |
6274f212 | 2459 | } |
9107e9d2 | 2460 | } |
ed5cbb03 | 2461 | |
f2f4d82f | 2462 | return HANGCHECK_HUNG; |
ed5cbb03 MK |
2463 | } |
2464 | ||
f65d9421 BG |
2465 | /** |
2466 | * This is called when the chip hasn't reported back with completed | |
05407ff8 MK |
2467 | * batchbuffers in a long time. We keep track per ring seqno progress and |
2468 | * if there are no progress, hangcheck score for that ring is increased. | |
2469 | * Further, acthd is inspected to see if the ring is stuck. On stuck case | |
2470 | * we kick the ring. If we see no progress on three subsequent calls | |
2471 | * we assume chip is wedged and try to fix it by resetting the chip. | |
f65d9421 | 2472 | */ |
a658b5d2 | 2473 | static void i915_hangcheck_elapsed(unsigned long data) |
f65d9421 BG |
2474 | { |
2475 | struct drm_device *dev = (struct drm_device *)data; | |
2476 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2477 | struct intel_ring_buffer *ring; |
b4519513 | 2478 | int i; |
05407ff8 | 2479 | int busy_count = 0, rings_hung = 0; |
9107e9d2 CW |
2480 | bool stuck[I915_NUM_RINGS] = { 0 }; |
2481 | #define BUSY 1 | |
2482 | #define KICK 5 | |
2483 | #define HUNG 20 | |
2484 | #define FIRE 30 | |
893eead0 | 2485 | |
3e0dc6b0 BW |
2486 | if (!i915_enable_hangcheck) |
2487 | return; | |
2488 | ||
b4519513 | 2489 | for_each_ring(ring, dev_priv, i) { |
05407ff8 | 2490 | u32 seqno, acthd; |
9107e9d2 | 2491 | bool busy = true; |
05407ff8 | 2492 | |
6274f212 CW |
2493 | semaphore_clear_deadlocks(dev_priv); |
2494 | ||
05407ff8 MK |
2495 | seqno = ring->get_seqno(ring, false); |
2496 | acthd = intel_ring_get_active_head(ring); | |
b4519513 | 2497 | |
9107e9d2 CW |
2498 | if (ring->hangcheck.seqno == seqno) { |
2499 | if (ring_idle(ring, seqno)) { | |
da661464 MK |
2500 | ring->hangcheck.action = HANGCHECK_IDLE; |
2501 | ||
9107e9d2 CW |
2502 | if (waitqueue_active(&ring->irq_queue)) { |
2503 | /* Issue a wake-up to catch stuck h/w. */ | |
094f9a54 | 2504 | if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) { |
f4adcd24 DV |
2505 | if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring))) |
2506 | DRM_ERROR("Hangcheck timer elapsed... %s idle\n", | |
2507 | ring->name); | |
2508 | else | |
2509 | DRM_INFO("Fake missed irq on %s\n", | |
2510 | ring->name); | |
094f9a54 CW |
2511 | wake_up_all(&ring->irq_queue); |
2512 | } | |
2513 | /* Safeguard against driver failure */ | |
2514 | ring->hangcheck.score += BUSY; | |
9107e9d2 CW |
2515 | } else |
2516 | busy = false; | |
05407ff8 | 2517 | } else { |
6274f212 CW |
2518 | /* We always increment the hangcheck score |
2519 | * if the ring is busy and still processing | |
2520 | * the same request, so that no single request | |
2521 | * can run indefinitely (such as a chain of | |
2522 | * batches). The only time we do not increment | |
2523 | * the hangcheck score on this ring, if this | |
2524 | * ring is in a legitimate wait for another | |
2525 | * ring. In that case the waiting ring is a | |
2526 | * victim and we want to be sure we catch the | |
2527 | * right culprit. Then every time we do kick | |
2528 | * the ring, add a small increment to the | |
2529 | * score so that we can catch a batch that is | |
2530 | * being repeatedly kicked and so responsible | |
2531 | * for stalling the machine. | |
2532 | */ | |
ad8beaea MK |
2533 | ring->hangcheck.action = ring_stuck(ring, |
2534 | acthd); | |
2535 | ||
2536 | switch (ring->hangcheck.action) { | |
da661464 | 2537 | case HANGCHECK_IDLE: |
f2f4d82f | 2538 | case HANGCHECK_WAIT: |
6274f212 | 2539 | break; |
f2f4d82f | 2540 | case HANGCHECK_ACTIVE: |
ea04cb31 | 2541 | ring->hangcheck.score += BUSY; |
6274f212 | 2542 | break; |
f2f4d82f | 2543 | case HANGCHECK_KICK: |
ea04cb31 | 2544 | ring->hangcheck.score += KICK; |
6274f212 | 2545 | break; |
f2f4d82f | 2546 | case HANGCHECK_HUNG: |
ea04cb31 | 2547 | ring->hangcheck.score += HUNG; |
6274f212 CW |
2548 | stuck[i] = true; |
2549 | break; | |
2550 | } | |
05407ff8 | 2551 | } |
9107e9d2 | 2552 | } else { |
da661464 MK |
2553 | ring->hangcheck.action = HANGCHECK_ACTIVE; |
2554 | ||
9107e9d2 CW |
2555 | /* Gradually reduce the count so that we catch DoS |
2556 | * attempts across multiple batches. | |
2557 | */ | |
2558 | if (ring->hangcheck.score > 0) | |
2559 | ring->hangcheck.score--; | |
d1e61e7f CW |
2560 | } |
2561 | ||
05407ff8 MK |
2562 | ring->hangcheck.seqno = seqno; |
2563 | ring->hangcheck.acthd = acthd; | |
9107e9d2 | 2564 | busy_count += busy; |
893eead0 | 2565 | } |
b9201c14 | 2566 | |
92cab734 | 2567 | for_each_ring(ring, dev_priv, i) { |
9107e9d2 | 2568 | if (ring->hangcheck.score > FIRE) { |
b8d88d1d DV |
2569 | DRM_INFO("%s on %s\n", |
2570 | stuck[i] ? "stuck" : "no progress", | |
2571 | ring->name); | |
a43adf07 | 2572 | rings_hung++; |
92cab734 MK |
2573 | } |
2574 | } | |
2575 | ||
05407ff8 MK |
2576 | if (rings_hung) |
2577 | return i915_handle_error(dev, true); | |
f65d9421 | 2578 | |
05407ff8 MK |
2579 | if (busy_count) |
2580 | /* Reset timer case chip hangs without another request | |
2581 | * being added */ | |
10cd45b6 MK |
2582 | i915_queue_hangcheck(dev); |
2583 | } | |
2584 | ||
2585 | void i915_queue_hangcheck(struct drm_device *dev) | |
2586 | { | |
2587 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2588 | if (!i915_enable_hangcheck) | |
2589 | return; | |
2590 | ||
2591 | mod_timer(&dev_priv->gpu_error.hangcheck_timer, | |
2592 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); | |
f65d9421 BG |
2593 | } |
2594 | ||
91738a95 PZ |
2595 | static void ibx_irq_preinstall(struct drm_device *dev) |
2596 | { | |
2597 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2598 | ||
2599 | if (HAS_PCH_NOP(dev)) | |
2600 | return; | |
2601 | ||
2602 | /* south display irq */ | |
2603 | I915_WRITE(SDEIMR, 0xffffffff); | |
2604 | /* | |
2605 | * SDEIER is also touched by the interrupt handler to work around missed | |
2606 | * PCH interrupts. Hence we can't update it after the interrupt handler | |
2607 | * is enabled - instead we unconditionally enable all PCH interrupt | |
2608 | * sources here, but then only unmask them as needed with SDEIMR. | |
2609 | */ | |
2610 | I915_WRITE(SDEIER, 0xffffffff); | |
2611 | POSTING_READ(SDEIER); | |
2612 | } | |
2613 | ||
d18ea1b5 DV |
2614 | static void gen5_gt_irq_preinstall(struct drm_device *dev) |
2615 | { | |
2616 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2617 | ||
2618 | /* and GT */ | |
2619 | I915_WRITE(GTIMR, 0xffffffff); | |
2620 | I915_WRITE(GTIER, 0x0); | |
2621 | POSTING_READ(GTIER); | |
2622 | ||
2623 | if (INTEL_INFO(dev)->gen >= 6) { | |
2624 | /* and PM */ | |
2625 | I915_WRITE(GEN6_PMIMR, 0xffffffff); | |
2626 | I915_WRITE(GEN6_PMIER, 0x0); | |
2627 | POSTING_READ(GEN6_PMIER); | |
2628 | } | |
2629 | } | |
2630 | ||
1da177e4 LT |
2631 | /* drm_dma.h hooks |
2632 | */ | |
f71d4af4 | 2633 | static void ironlake_irq_preinstall(struct drm_device *dev) |
036a4a7d ZW |
2634 | { |
2635 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2636 | ||
4697995b JB |
2637 | atomic_set(&dev_priv->irq_received, 0); |
2638 | ||
036a4a7d | 2639 | I915_WRITE(HWSTAM, 0xeffe); |
bdfcdb63 | 2640 | |
036a4a7d ZW |
2641 | I915_WRITE(DEIMR, 0xffffffff); |
2642 | I915_WRITE(DEIER, 0x0); | |
3143a2bf | 2643 | POSTING_READ(DEIER); |
036a4a7d | 2644 | |
d18ea1b5 | 2645 | gen5_gt_irq_preinstall(dev); |
c650156a | 2646 | |
91738a95 | 2647 | ibx_irq_preinstall(dev); |
7d99163d BW |
2648 | } |
2649 | ||
7e231dbe JB |
2650 | static void valleyview_irq_preinstall(struct drm_device *dev) |
2651 | { | |
2652 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2653 | int pipe; | |
2654 | ||
2655 | atomic_set(&dev_priv->irq_received, 0); | |
2656 | ||
7e231dbe JB |
2657 | /* VLV magic */ |
2658 | I915_WRITE(VLV_IMR, 0); | |
2659 | I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); | |
2660 | I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); | |
2661 | I915_WRITE(RING_IMR(BLT_RING_BASE), 0); | |
2662 | ||
7e231dbe JB |
2663 | /* and GT */ |
2664 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
2665 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
d18ea1b5 DV |
2666 | |
2667 | gen5_gt_irq_preinstall(dev); | |
7e231dbe JB |
2668 | |
2669 | I915_WRITE(DPINVGTT, 0xff); | |
2670 | ||
2671 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
2672 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
2673 | for_each_pipe(pipe) | |
2674 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
2675 | I915_WRITE(VLV_IIR, 0xffffffff); | |
2676 | I915_WRITE(VLV_IMR, 0xffffffff); | |
2677 | I915_WRITE(VLV_IER, 0x0); | |
2678 | POSTING_READ(VLV_IER); | |
2679 | } | |
2680 | ||
abd58f01 BW |
2681 | static void gen8_irq_preinstall(struct drm_device *dev) |
2682 | { | |
2683 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2684 | int pipe; | |
2685 | ||
2686 | atomic_set(&dev_priv->irq_received, 0); | |
2687 | ||
2688 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
2689 | POSTING_READ(GEN8_MASTER_IRQ); | |
2690 | ||
2691 | /* IIR can theoretically queue up two events. Be paranoid */ | |
2692 | #define GEN8_IRQ_INIT_NDX(type, which) do { \ | |
2693 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ | |
2694 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
2695 | I915_WRITE(GEN8_##type##_IER(which), 0); \ | |
2696 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
2697 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
2698 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
2699 | } while (0) | |
2700 | ||
2701 | #define GEN8_IRQ_INIT(type) do { \ | |
2702 | I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \ | |
2703 | POSTING_READ(GEN8_##type##_IMR); \ | |
2704 | I915_WRITE(GEN8_##type##_IER, 0); \ | |
2705 | I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ | |
2706 | POSTING_READ(GEN8_##type##_IIR); \ | |
2707 | I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ | |
2708 | } while (0) | |
2709 | ||
2710 | GEN8_IRQ_INIT_NDX(GT, 0); | |
2711 | GEN8_IRQ_INIT_NDX(GT, 1); | |
2712 | GEN8_IRQ_INIT_NDX(GT, 2); | |
2713 | GEN8_IRQ_INIT_NDX(GT, 3); | |
2714 | ||
2715 | for_each_pipe(pipe) { | |
2716 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe); | |
2717 | } | |
2718 | ||
2719 | GEN8_IRQ_INIT(DE_PORT); | |
2720 | GEN8_IRQ_INIT(DE_MISC); | |
2721 | GEN8_IRQ_INIT(PCU); | |
2722 | #undef GEN8_IRQ_INIT | |
2723 | #undef GEN8_IRQ_INIT_NDX | |
2724 | ||
2725 | POSTING_READ(GEN8_PCU_IIR); | |
09f2344d JB |
2726 | |
2727 | ibx_irq_preinstall(dev); | |
abd58f01 BW |
2728 | } |
2729 | ||
82a28bcf | 2730 | static void ibx_hpd_irq_setup(struct drm_device *dev) |
7fe0b973 KP |
2731 | { |
2732 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
82a28bcf DV |
2733 | struct drm_mode_config *mode_config = &dev->mode_config; |
2734 | struct intel_encoder *intel_encoder; | |
fee884ed | 2735 | u32 hotplug_irqs, hotplug, enabled_irqs = 0; |
82a28bcf DV |
2736 | |
2737 | if (HAS_PCH_IBX(dev)) { | |
fee884ed | 2738 | hotplug_irqs = SDE_HOTPLUG_MASK; |
82a28bcf | 2739 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
cd569aed | 2740 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
fee884ed | 2741 | enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin]; |
82a28bcf | 2742 | } else { |
fee884ed | 2743 | hotplug_irqs = SDE_HOTPLUG_MASK_CPT; |
82a28bcf | 2744 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
cd569aed | 2745 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
fee884ed | 2746 | enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin]; |
82a28bcf | 2747 | } |
7fe0b973 | 2748 | |
fee884ed | 2749 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); |
82a28bcf DV |
2750 | |
2751 | /* | |
2752 | * Enable digital hotplug on the PCH, and configure the DP short pulse | |
2753 | * duration to 2ms (which is the minimum in the Display Port spec) | |
2754 | * | |
2755 | * This register is the same on all known PCH chips. | |
2756 | */ | |
7fe0b973 KP |
2757 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
2758 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); | |
2759 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; | |
2760 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; | |
2761 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; | |
2762 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); | |
2763 | } | |
2764 | ||
d46da437 PZ |
2765 | static void ibx_irq_postinstall(struct drm_device *dev) |
2766 | { | |
2767 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
82a28bcf | 2768 | u32 mask; |
e5868a31 | 2769 | |
692a04cf DV |
2770 | if (HAS_PCH_NOP(dev)) |
2771 | return; | |
2772 | ||
8664281b PZ |
2773 | if (HAS_PCH_IBX(dev)) { |
2774 | mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER | | |
de032bf4 | 2775 | SDE_TRANSA_FIFO_UNDER | SDE_POISON; |
8664281b PZ |
2776 | } else { |
2777 | mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT; | |
2778 | ||
2779 | I915_WRITE(SERR_INT, I915_READ(SERR_INT)); | |
2780 | } | |
ab5c608b | 2781 | |
d46da437 PZ |
2782 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); |
2783 | I915_WRITE(SDEIMR, ~mask); | |
d46da437 PZ |
2784 | } |
2785 | ||
0a9a8c91 DV |
2786 | static void gen5_gt_irq_postinstall(struct drm_device *dev) |
2787 | { | |
2788 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2789 | u32 pm_irqs, gt_irqs; | |
2790 | ||
2791 | pm_irqs = gt_irqs = 0; | |
2792 | ||
2793 | dev_priv->gt_irq_mask = ~0; | |
040d2baa | 2794 | if (HAS_L3_DPF(dev)) { |
0a9a8c91 | 2795 | /* L3 parity interrupt is always unmasked. */ |
35a85ac6 BW |
2796 | dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev); |
2797 | gt_irqs |= GT_PARITY_ERROR(dev); | |
0a9a8c91 DV |
2798 | } |
2799 | ||
2800 | gt_irqs |= GT_RENDER_USER_INTERRUPT; | |
2801 | if (IS_GEN5(dev)) { | |
2802 | gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | | |
2803 | ILK_BSD_USER_INTERRUPT; | |
2804 | } else { | |
2805 | gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; | |
2806 | } | |
2807 | ||
2808 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
2809 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
2810 | I915_WRITE(GTIER, gt_irqs); | |
2811 | POSTING_READ(GTIER); | |
2812 | ||
2813 | if (INTEL_INFO(dev)->gen >= 6) { | |
2814 | pm_irqs |= GEN6_PM_RPS_EVENTS; | |
2815 | ||
2816 | if (HAS_VEBOX(dev)) | |
2817 | pm_irqs |= PM_VEBOX_USER_INTERRUPT; | |
2818 | ||
605cd25b | 2819 | dev_priv->pm_irq_mask = 0xffffffff; |
0a9a8c91 | 2820 | I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); |
605cd25b | 2821 | I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask); |
0a9a8c91 DV |
2822 | I915_WRITE(GEN6_PMIER, pm_irqs); |
2823 | POSTING_READ(GEN6_PMIER); | |
2824 | } | |
2825 | } | |
2826 | ||
f71d4af4 | 2827 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d | 2828 | { |
4bc9d430 | 2829 | unsigned long irqflags; |
036a4a7d | 2830 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
8e76f8dc PZ |
2831 | u32 display_mask, extra_mask; |
2832 | ||
2833 | if (INTEL_INFO(dev)->gen >= 7) { | |
2834 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | | |
2835 | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | | |
2836 | DE_PLANEB_FLIP_DONE_IVB | | |
2837 | DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB | | |
2838 | DE_ERR_INT_IVB); | |
2839 | extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | | |
2840 | DE_PIPEA_VBLANK_IVB); | |
2841 | ||
2842 | I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT)); | |
2843 | } else { | |
2844 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | | |
2845 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | | |
5b3a856b DV |
2846 | DE_AUX_CHANNEL_A | |
2847 | DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN | | |
2848 | DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE | | |
2849 | DE_POISON); | |
8e76f8dc PZ |
2850 | extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT; |
2851 | } | |
036a4a7d | 2852 | |
1ec14ad3 | 2853 | dev_priv->irq_mask = ~display_mask; |
036a4a7d ZW |
2854 | |
2855 | /* should always can generate irq */ | |
2856 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1ec14ad3 | 2857 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
8e76f8dc | 2858 | I915_WRITE(DEIER, display_mask | extra_mask); |
3143a2bf | 2859 | POSTING_READ(DEIER); |
036a4a7d | 2860 | |
0a9a8c91 | 2861 | gen5_gt_irq_postinstall(dev); |
036a4a7d | 2862 | |
d46da437 | 2863 | ibx_irq_postinstall(dev); |
7fe0b973 | 2864 | |
f97108d1 | 2865 | if (IS_IRONLAKE_M(dev)) { |
6005ce42 DV |
2866 | /* Enable PCU event interrupts |
2867 | * | |
2868 | * spinlocking not required here for correctness since interrupt | |
4bc9d430 DV |
2869 | * setup is guaranteed to run in single-threaded context. But we |
2870 | * need it to make the assert_spin_locked happy. */ | |
2871 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
f97108d1 | 2872 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); |
4bc9d430 | 2873 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
f97108d1 JB |
2874 | } |
2875 | ||
036a4a7d ZW |
2876 | return 0; |
2877 | } | |
2878 | ||
7e231dbe JB |
2879 | static int valleyview_irq_postinstall(struct drm_device *dev) |
2880 | { | |
2881 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
7e231dbe | 2882 | u32 enable_mask; |
379ef82d DV |
2883 | u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV | |
2884 | PIPE_CRC_DONE_ENABLE; | |
b79480ba | 2885 | unsigned long irqflags; |
7e231dbe JB |
2886 | |
2887 | enable_mask = I915_DISPLAY_PORT_INTERRUPT; | |
31acc7f5 JB |
2888 | enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
2889 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | | |
2890 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
7e231dbe JB |
2891 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
2892 | ||
31acc7f5 JB |
2893 | /* |
2894 | *Leave vblank interrupts masked initially. enable/disable will | |
2895 | * toggle them based on usage. | |
2896 | */ | |
2897 | dev_priv->irq_mask = (~enable_mask) | | |
2898 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | | |
2899 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; | |
7e231dbe | 2900 | |
20afbda2 DV |
2901 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
2902 | POSTING_READ(PORT_HOTPLUG_EN); | |
2903 | ||
7e231dbe JB |
2904 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
2905 | I915_WRITE(VLV_IER, enable_mask); | |
2906 | I915_WRITE(VLV_IIR, 0xffffffff); | |
2907 | I915_WRITE(PIPESTAT(0), 0xffff); | |
2908 | I915_WRITE(PIPESTAT(1), 0xffff); | |
2909 | POSTING_READ(VLV_IER); | |
2910 | ||
b79480ba DV |
2911 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
2912 | * just to make the assert_spin_locked check happy. */ | |
2913 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3b6c42e8 DV |
2914 | i915_enable_pipestat(dev_priv, PIPE_A, pipestat_enable); |
2915 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE); | |
2916 | i915_enable_pipestat(dev_priv, PIPE_B, pipestat_enable); | |
b79480ba | 2917 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
31acc7f5 | 2918 | |
7e231dbe JB |
2919 | I915_WRITE(VLV_IIR, 0xffffffff); |
2920 | I915_WRITE(VLV_IIR, 0xffffffff); | |
2921 | ||
0a9a8c91 | 2922 | gen5_gt_irq_postinstall(dev); |
7e231dbe JB |
2923 | |
2924 | /* ack & enable invalid PTE error interrupts */ | |
2925 | #if 0 /* FIXME: add support to irq handler for checking these bits */ | |
2926 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); | |
2927 | I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); | |
2928 | #endif | |
2929 | ||
2930 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); | |
20afbda2 DV |
2931 | |
2932 | return 0; | |
2933 | } | |
2934 | ||
abd58f01 BW |
2935 | static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) |
2936 | { | |
2937 | int i; | |
2938 | ||
2939 | /* These are interrupts we'll toggle with the ring mask register */ | |
2940 | uint32_t gt_interrupts[] = { | |
2941 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | | |
2942 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT | | |
2943 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT, | |
2944 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | | |
2945 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT, | |
2946 | 0, | |
2947 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
2948 | }; | |
2949 | ||
2950 | for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) { | |
2951 | u32 tmp = I915_READ(GEN8_GT_IIR(i)); | |
2952 | if (tmp) | |
2953 | DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n", | |
2954 | i, tmp); | |
2955 | I915_WRITE(GEN8_GT_IMR(i), ~gt_interrupts[i]); | |
2956 | I915_WRITE(GEN8_GT_IER(i), gt_interrupts[i]); | |
2957 | } | |
2958 | POSTING_READ(GEN8_GT_IER(0)); | |
2959 | } | |
2960 | ||
2961 | static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) | |
2962 | { | |
2963 | struct drm_device *dev = dev_priv->dev; | |
13b3a0a7 DV |
2964 | uint32_t de_pipe_masked = GEN8_PIPE_FLIP_DONE | |
2965 | GEN8_PIPE_CDCLK_CRC_DONE | | |
2966 | GEN8_PIPE_FIFO_UNDERRUN | | |
2967 | GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
2968 | uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK; | |
abd58f01 | 2969 | int pipe; |
13b3a0a7 DV |
2970 | dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; |
2971 | dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; | |
2972 | dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; | |
abd58f01 BW |
2973 | |
2974 | for_each_pipe(pipe) { | |
2975 | u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe)); | |
2976 | if (tmp) | |
2977 | DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n", | |
2978 | pipe, tmp); | |
2979 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2980 | I915_WRITE(GEN8_DE_PIPE_IER(pipe), de_pipe_enables); | |
2981 | } | |
2982 | POSTING_READ(GEN8_DE_PIPE_ISR(0)); | |
2983 | ||
6d766f02 DV |
2984 | I915_WRITE(GEN8_DE_PORT_IMR, ~GEN8_AUX_CHANNEL_A); |
2985 | I915_WRITE(GEN8_DE_PORT_IER, GEN8_AUX_CHANNEL_A); | |
abd58f01 BW |
2986 | POSTING_READ(GEN8_DE_PORT_IER); |
2987 | } | |
2988 | ||
2989 | static int gen8_irq_postinstall(struct drm_device *dev) | |
2990 | { | |
2991 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2992 | ||
2993 | gen8_gt_irq_postinstall(dev_priv); | |
2994 | gen8_de_irq_postinstall(dev_priv); | |
2995 | ||
2996 | ibx_irq_postinstall(dev); | |
2997 | ||
2998 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); | |
2999 | POSTING_READ(GEN8_MASTER_IRQ); | |
3000 | ||
3001 | return 0; | |
3002 | } | |
3003 | ||
3004 | static void gen8_irq_uninstall(struct drm_device *dev) | |
3005 | { | |
3006 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3007 | int pipe; | |
3008 | ||
3009 | if (!dev_priv) | |
3010 | return; | |
3011 | ||
3012 | atomic_set(&dev_priv->irq_received, 0); | |
3013 | ||
3014 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3015 | ||
3016 | #define GEN8_IRQ_FINI_NDX(type, which) do { \ | |
3017 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ | |
3018 | I915_WRITE(GEN8_##type##_IER(which), 0); \ | |
3019 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
3020 | } while (0) | |
3021 | ||
3022 | #define GEN8_IRQ_FINI(type) do { \ | |
3023 | I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \ | |
3024 | I915_WRITE(GEN8_##type##_IER, 0); \ | |
3025 | I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ | |
3026 | } while (0) | |
3027 | ||
3028 | GEN8_IRQ_FINI_NDX(GT, 0); | |
3029 | GEN8_IRQ_FINI_NDX(GT, 1); | |
3030 | GEN8_IRQ_FINI_NDX(GT, 2); | |
3031 | GEN8_IRQ_FINI_NDX(GT, 3); | |
3032 | ||
3033 | for_each_pipe(pipe) { | |
3034 | GEN8_IRQ_FINI_NDX(DE_PIPE, pipe); | |
3035 | } | |
3036 | ||
3037 | GEN8_IRQ_FINI(DE_PORT); | |
3038 | GEN8_IRQ_FINI(DE_MISC); | |
3039 | GEN8_IRQ_FINI(PCU); | |
3040 | #undef GEN8_IRQ_FINI | |
3041 | #undef GEN8_IRQ_FINI_NDX | |
3042 | ||
3043 | POSTING_READ(GEN8_PCU_IIR); | |
3044 | } | |
3045 | ||
7e231dbe JB |
3046 | static void valleyview_irq_uninstall(struct drm_device *dev) |
3047 | { | |
3048 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
3049 | int pipe; | |
3050 | ||
3051 | if (!dev_priv) | |
3052 | return; | |
3053 | ||
ac4c16c5 EE |
3054 | del_timer_sync(&dev_priv->hotplug_reenable_timer); |
3055 | ||
7e231dbe JB |
3056 | for_each_pipe(pipe) |
3057 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
3058 | ||
3059 | I915_WRITE(HWSTAM, 0xffffffff); | |
3060 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3061 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3062 | for_each_pipe(pipe) | |
3063 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
3064 | I915_WRITE(VLV_IIR, 0xffffffff); | |
3065 | I915_WRITE(VLV_IMR, 0xffffffff); | |
3066 | I915_WRITE(VLV_IER, 0x0); | |
3067 | POSTING_READ(VLV_IER); | |
3068 | } | |
3069 | ||
f71d4af4 | 3070 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d ZW |
3071 | { |
3072 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
4697995b JB |
3073 | |
3074 | if (!dev_priv) | |
3075 | return; | |
3076 | ||
ac4c16c5 EE |
3077 | del_timer_sync(&dev_priv->hotplug_reenable_timer); |
3078 | ||
036a4a7d ZW |
3079 | I915_WRITE(HWSTAM, 0xffffffff); |
3080 | ||
3081 | I915_WRITE(DEIMR, 0xffffffff); | |
3082 | I915_WRITE(DEIER, 0x0); | |
3083 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
8664281b PZ |
3084 | if (IS_GEN7(dev)) |
3085 | I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT)); | |
036a4a7d ZW |
3086 | |
3087 | I915_WRITE(GTIMR, 0xffffffff); | |
3088 | I915_WRITE(GTIER, 0x0); | |
3089 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
192aac1f | 3090 | |
ab5c608b BW |
3091 | if (HAS_PCH_NOP(dev)) |
3092 | return; | |
3093 | ||
192aac1f KP |
3094 | I915_WRITE(SDEIMR, 0xffffffff); |
3095 | I915_WRITE(SDEIER, 0x0); | |
3096 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | |
8664281b PZ |
3097 | if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) |
3098 | I915_WRITE(SERR_INT, I915_READ(SERR_INT)); | |
036a4a7d ZW |
3099 | } |
3100 | ||
a266c7d5 | 3101 | static void i8xx_irq_preinstall(struct drm_device * dev) |
1da177e4 LT |
3102 | { |
3103 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 3104 | int pipe; |
91e3738e | 3105 | |
a266c7d5 | 3106 | atomic_set(&dev_priv->irq_received, 0); |
5ca58282 | 3107 | |
9db4a9c7 JB |
3108 | for_each_pipe(pipe) |
3109 | I915_WRITE(PIPESTAT(pipe), 0); | |
a266c7d5 CW |
3110 | I915_WRITE16(IMR, 0xffff); |
3111 | I915_WRITE16(IER, 0x0); | |
3112 | POSTING_READ16(IER); | |
c2798b19 CW |
3113 | } |
3114 | ||
3115 | static int i8xx_irq_postinstall(struct drm_device *dev) | |
3116 | { | |
3117 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
379ef82d | 3118 | unsigned long irqflags; |
c2798b19 | 3119 | |
c2798b19 CW |
3120 | I915_WRITE16(EMR, |
3121 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); | |
3122 | ||
3123 | /* Unmask the interrupts that we always want on. */ | |
3124 | dev_priv->irq_mask = | |
3125 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3126 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3127 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3128 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3129 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3130 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
3131 | ||
3132 | I915_WRITE16(IER, | |
3133 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3134 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3135 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
3136 | I915_USER_INTERRUPT); | |
3137 | POSTING_READ16(IER); | |
3138 | ||
379ef82d DV |
3139 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3140 | * just to make the assert_spin_locked check happy. */ | |
3141 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3b6c42e8 DV |
3142 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE); |
3143 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE); | |
379ef82d DV |
3144 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
3145 | ||
c2798b19 CW |
3146 | return 0; |
3147 | } | |
3148 | ||
90a72f87 VS |
3149 | /* |
3150 | * Returns true when a page flip has completed. | |
3151 | */ | |
3152 | static bool i8xx_handle_vblank(struct drm_device *dev, | |
1f1c2e24 | 3153 | int plane, int pipe, u32 iir) |
90a72f87 VS |
3154 | { |
3155 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1f1c2e24 | 3156 | u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
90a72f87 VS |
3157 | |
3158 | if (!drm_handle_vblank(dev, pipe)) | |
3159 | return false; | |
3160 | ||
3161 | if ((iir & flip_pending) == 0) | |
3162 | return false; | |
3163 | ||
1f1c2e24 | 3164 | intel_prepare_page_flip(dev, plane); |
90a72f87 VS |
3165 | |
3166 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
3167 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3168 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3169 | * the flip is completed (no longer pending). Since this doesn't raise | |
3170 | * an interrupt per se, we watch for the change at vblank. | |
3171 | */ | |
3172 | if (I915_READ16(ISR) & flip_pending) | |
3173 | return false; | |
3174 | ||
3175 | intel_finish_page_flip(dev, pipe); | |
3176 | ||
3177 | return true; | |
3178 | } | |
3179 | ||
ff1f525e | 3180 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
c2798b19 CW |
3181 | { |
3182 | struct drm_device *dev = (struct drm_device *) arg; | |
3183 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
c2798b19 CW |
3184 | u16 iir, new_iir; |
3185 | u32 pipe_stats[2]; | |
3186 | unsigned long irqflags; | |
c2798b19 CW |
3187 | int pipe; |
3188 | u16 flip_mask = | |
3189 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3190 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
3191 | ||
3192 | atomic_inc(&dev_priv->irq_received); | |
3193 | ||
3194 | iir = I915_READ16(IIR); | |
3195 | if (iir == 0) | |
3196 | return IRQ_NONE; | |
3197 | ||
3198 | while (iir & ~flip_mask) { | |
3199 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3200 | * have been cleared after the pipestat interrupt was received. | |
3201 | * It doesn't set the bit in iir again, but it still produces | |
3202 | * interrupts (for non-MSI). | |
3203 | */ | |
3204 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3205 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
3206 | i915_handle_error(dev, false); | |
3207 | ||
3208 | for_each_pipe(pipe) { | |
3209 | int reg = PIPESTAT(pipe); | |
3210 | pipe_stats[pipe] = I915_READ(reg); | |
3211 | ||
3212 | /* | |
3213 | * Clear the PIPE*STAT regs before the IIR | |
3214 | */ | |
3215 | if (pipe_stats[pipe] & 0x8000ffff) { | |
3216 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | |
3217 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | |
3218 | pipe_name(pipe)); | |
3219 | I915_WRITE(reg, pipe_stats[pipe]); | |
c2798b19 CW |
3220 | } |
3221 | } | |
3222 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3223 | ||
3224 | I915_WRITE16(IIR, iir & ~flip_mask); | |
3225 | new_iir = I915_READ16(IIR); /* Flush posted writes */ | |
3226 | ||
d05c617e | 3227 | i915_update_dri1_breadcrumb(dev); |
c2798b19 CW |
3228 | |
3229 | if (iir & I915_USER_INTERRUPT) | |
3230 | notify_ring(dev, &dev_priv->ring[RCS]); | |
3231 | ||
4356d586 | 3232 | for_each_pipe(pipe) { |
1f1c2e24 | 3233 | int plane = pipe; |
3a77c4c4 | 3234 | if (HAS_FBC(dev)) |
1f1c2e24 VS |
3235 | plane = !plane; |
3236 | ||
4356d586 | 3237 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
1f1c2e24 VS |
3238 | i8xx_handle_vblank(dev, plane, pipe, iir)) |
3239 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
c2798b19 | 3240 | |
4356d586 | 3241 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
277de95e | 3242 | i9xx_pipe_crc_irq_handler(dev, pipe); |
4356d586 | 3243 | } |
c2798b19 CW |
3244 | |
3245 | iir = new_iir; | |
3246 | } | |
3247 | ||
3248 | return IRQ_HANDLED; | |
3249 | } | |
3250 | ||
3251 | static void i8xx_irq_uninstall(struct drm_device * dev) | |
3252 | { | |
3253 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
3254 | int pipe; | |
3255 | ||
c2798b19 CW |
3256 | for_each_pipe(pipe) { |
3257 | /* Clear enable bits; then clear status bits */ | |
3258 | I915_WRITE(PIPESTAT(pipe), 0); | |
3259 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); | |
3260 | } | |
3261 | I915_WRITE16(IMR, 0xffff); | |
3262 | I915_WRITE16(IER, 0x0); | |
3263 | I915_WRITE16(IIR, I915_READ16(IIR)); | |
3264 | } | |
3265 | ||
a266c7d5 CW |
3266 | static void i915_irq_preinstall(struct drm_device * dev) |
3267 | { | |
3268 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
3269 | int pipe; | |
3270 | ||
3271 | atomic_set(&dev_priv->irq_received, 0); | |
3272 | ||
3273 | if (I915_HAS_HOTPLUG(dev)) { | |
3274 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3275 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3276 | } | |
3277 | ||
00d98ebd | 3278 | I915_WRITE16(HWSTAM, 0xeffe); |
a266c7d5 CW |
3279 | for_each_pipe(pipe) |
3280 | I915_WRITE(PIPESTAT(pipe), 0); | |
3281 | I915_WRITE(IMR, 0xffffffff); | |
3282 | I915_WRITE(IER, 0x0); | |
3283 | POSTING_READ(IER); | |
3284 | } | |
3285 | ||
3286 | static int i915_irq_postinstall(struct drm_device *dev) | |
3287 | { | |
3288 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
38bde180 | 3289 | u32 enable_mask; |
379ef82d | 3290 | unsigned long irqflags; |
a266c7d5 | 3291 | |
38bde180 CW |
3292 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
3293 | ||
3294 | /* Unmask the interrupts that we always want on. */ | |
3295 | dev_priv->irq_mask = | |
3296 | ~(I915_ASLE_INTERRUPT | | |
3297 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3298 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3299 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3300 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3301 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3302 | ||
3303 | enable_mask = | |
3304 | I915_ASLE_INTERRUPT | | |
3305 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3306 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3307 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
3308 | I915_USER_INTERRUPT; | |
3309 | ||
a266c7d5 | 3310 | if (I915_HAS_HOTPLUG(dev)) { |
20afbda2 DV |
3311 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3312 | POSTING_READ(PORT_HOTPLUG_EN); | |
3313 | ||
a266c7d5 CW |
3314 | /* Enable in IER... */ |
3315 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
3316 | /* and unmask in IMR */ | |
3317 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; | |
3318 | } | |
3319 | ||
a266c7d5 CW |
3320 | I915_WRITE(IMR, dev_priv->irq_mask); |
3321 | I915_WRITE(IER, enable_mask); | |
3322 | POSTING_READ(IER); | |
3323 | ||
f49e38dd | 3324 | i915_enable_asle_pipestat(dev); |
20afbda2 | 3325 | |
379ef82d DV |
3326 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3327 | * just to make the assert_spin_locked check happy. */ | |
3328 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3b6c42e8 DV |
3329 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE); |
3330 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE); | |
379ef82d DV |
3331 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
3332 | ||
20afbda2 DV |
3333 | return 0; |
3334 | } | |
3335 | ||
90a72f87 VS |
3336 | /* |
3337 | * Returns true when a page flip has completed. | |
3338 | */ | |
3339 | static bool i915_handle_vblank(struct drm_device *dev, | |
3340 | int plane, int pipe, u32 iir) | |
3341 | { | |
3342 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3343 | u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); | |
3344 | ||
3345 | if (!drm_handle_vblank(dev, pipe)) | |
3346 | return false; | |
3347 | ||
3348 | if ((iir & flip_pending) == 0) | |
3349 | return false; | |
3350 | ||
3351 | intel_prepare_page_flip(dev, plane); | |
3352 | ||
3353 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
3354 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3355 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3356 | * the flip is completed (no longer pending). Since this doesn't raise | |
3357 | * an interrupt per se, we watch for the change at vblank. | |
3358 | */ | |
3359 | if (I915_READ(ISR) & flip_pending) | |
3360 | return false; | |
3361 | ||
3362 | intel_finish_page_flip(dev, pipe); | |
3363 | ||
3364 | return true; | |
3365 | } | |
3366 | ||
ff1f525e | 3367 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
a266c7d5 CW |
3368 | { |
3369 | struct drm_device *dev = (struct drm_device *) arg; | |
3370 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
8291ee90 | 3371 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
a266c7d5 | 3372 | unsigned long irqflags; |
38bde180 CW |
3373 | u32 flip_mask = |
3374 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3375 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
38bde180 | 3376 | int pipe, ret = IRQ_NONE; |
a266c7d5 CW |
3377 | |
3378 | atomic_inc(&dev_priv->irq_received); | |
3379 | ||
3380 | iir = I915_READ(IIR); | |
38bde180 CW |
3381 | do { |
3382 | bool irq_received = (iir & ~flip_mask) != 0; | |
8291ee90 | 3383 | bool blc_event = false; |
a266c7d5 CW |
3384 | |
3385 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3386 | * have been cleared after the pipestat interrupt was received. | |
3387 | * It doesn't set the bit in iir again, but it still produces | |
3388 | * interrupts (for non-MSI). | |
3389 | */ | |
3390 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3391 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
3392 | i915_handle_error(dev, false); | |
3393 | ||
3394 | for_each_pipe(pipe) { | |
3395 | int reg = PIPESTAT(pipe); | |
3396 | pipe_stats[pipe] = I915_READ(reg); | |
3397 | ||
38bde180 | 3398 | /* Clear the PIPE*STAT regs before the IIR */ |
a266c7d5 CW |
3399 | if (pipe_stats[pipe] & 0x8000ffff) { |
3400 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | |
3401 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | |
3402 | pipe_name(pipe)); | |
3403 | I915_WRITE(reg, pipe_stats[pipe]); | |
38bde180 | 3404 | irq_received = true; |
a266c7d5 CW |
3405 | } |
3406 | } | |
3407 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3408 | ||
3409 | if (!irq_received) | |
3410 | break; | |
3411 | ||
a266c7d5 CW |
3412 | /* Consume port. Then clear IIR or we'll miss events */ |
3413 | if ((I915_HAS_HOTPLUG(dev)) && | |
3414 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { | |
3415 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
b543fb04 | 3416 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; |
a266c7d5 CW |
3417 | |
3418 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", | |
3419 | hotplug_status); | |
91d131d2 DV |
3420 | |
3421 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); | |
3422 | ||
a266c7d5 | 3423 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
38bde180 | 3424 | POSTING_READ(PORT_HOTPLUG_STAT); |
a266c7d5 CW |
3425 | } |
3426 | ||
38bde180 | 3427 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
3428 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
3429 | ||
a266c7d5 CW |
3430 | if (iir & I915_USER_INTERRUPT) |
3431 | notify_ring(dev, &dev_priv->ring[RCS]); | |
a266c7d5 | 3432 | |
a266c7d5 | 3433 | for_each_pipe(pipe) { |
38bde180 | 3434 | int plane = pipe; |
3a77c4c4 | 3435 | if (HAS_FBC(dev)) |
38bde180 | 3436 | plane = !plane; |
90a72f87 | 3437 | |
8291ee90 | 3438 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
3439 | i915_handle_vblank(dev, plane, pipe, iir)) |
3440 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
a266c7d5 CW |
3441 | |
3442 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
3443 | blc_event = true; | |
4356d586 DV |
3444 | |
3445 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 3446 | i9xx_pipe_crc_irq_handler(dev, pipe); |
a266c7d5 CW |
3447 | } |
3448 | ||
a266c7d5 CW |
3449 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
3450 | intel_opregion_asle_intr(dev); | |
3451 | ||
3452 | /* With MSI, interrupts are only generated when iir | |
3453 | * transitions from zero to nonzero. If another bit got | |
3454 | * set while we were handling the existing iir bits, then | |
3455 | * we would never get another interrupt. | |
3456 | * | |
3457 | * This is fine on non-MSI as well, as if we hit this path | |
3458 | * we avoid exiting the interrupt handler only to generate | |
3459 | * another one. | |
3460 | * | |
3461 | * Note that for MSI this could cause a stray interrupt report | |
3462 | * if an interrupt landed in the time between writing IIR and | |
3463 | * the posting read. This should be rare enough to never | |
3464 | * trigger the 99% of 100,000 interrupts test for disabling | |
3465 | * stray interrupts. | |
3466 | */ | |
38bde180 | 3467 | ret = IRQ_HANDLED; |
a266c7d5 | 3468 | iir = new_iir; |
38bde180 | 3469 | } while (iir & ~flip_mask); |
a266c7d5 | 3470 | |
d05c617e | 3471 | i915_update_dri1_breadcrumb(dev); |
8291ee90 | 3472 | |
a266c7d5 CW |
3473 | return ret; |
3474 | } | |
3475 | ||
3476 | static void i915_irq_uninstall(struct drm_device * dev) | |
3477 | { | |
3478 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
3479 | int pipe; | |
3480 | ||
ac4c16c5 EE |
3481 | del_timer_sync(&dev_priv->hotplug_reenable_timer); |
3482 | ||
a266c7d5 CW |
3483 | if (I915_HAS_HOTPLUG(dev)) { |
3484 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3485 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3486 | } | |
3487 | ||
00d98ebd | 3488 | I915_WRITE16(HWSTAM, 0xffff); |
55b39755 CW |
3489 | for_each_pipe(pipe) { |
3490 | /* Clear enable bits; then clear status bits */ | |
a266c7d5 | 3491 | I915_WRITE(PIPESTAT(pipe), 0); |
55b39755 CW |
3492 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
3493 | } | |
a266c7d5 CW |
3494 | I915_WRITE(IMR, 0xffffffff); |
3495 | I915_WRITE(IER, 0x0); | |
3496 | ||
a266c7d5 CW |
3497 | I915_WRITE(IIR, I915_READ(IIR)); |
3498 | } | |
3499 | ||
3500 | static void i965_irq_preinstall(struct drm_device * dev) | |
3501 | { | |
3502 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
3503 | int pipe; | |
3504 | ||
3505 | atomic_set(&dev_priv->irq_received, 0); | |
3506 | ||
adca4730 CW |
3507 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3508 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
3509 | |
3510 | I915_WRITE(HWSTAM, 0xeffe); | |
3511 | for_each_pipe(pipe) | |
3512 | I915_WRITE(PIPESTAT(pipe), 0); | |
3513 | I915_WRITE(IMR, 0xffffffff); | |
3514 | I915_WRITE(IER, 0x0); | |
3515 | POSTING_READ(IER); | |
3516 | } | |
3517 | ||
3518 | static int i965_irq_postinstall(struct drm_device *dev) | |
3519 | { | |
3520 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
bbba0a97 | 3521 | u32 enable_mask; |
a266c7d5 | 3522 | u32 error_mask; |
b79480ba | 3523 | unsigned long irqflags; |
a266c7d5 | 3524 | |
a266c7d5 | 3525 | /* Unmask the interrupts that we always want on. */ |
bbba0a97 | 3526 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
adca4730 | 3527 | I915_DISPLAY_PORT_INTERRUPT | |
bbba0a97 CW |
3528 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
3529 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3530 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3531 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3532 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3533 | ||
3534 | enable_mask = ~dev_priv->irq_mask; | |
21ad8330 VS |
3535 | enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
3536 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); | |
bbba0a97 CW |
3537 | enable_mask |= I915_USER_INTERRUPT; |
3538 | ||
3539 | if (IS_G4X(dev)) | |
3540 | enable_mask |= I915_BSD_USER_INTERRUPT; | |
a266c7d5 | 3541 | |
b79480ba DV |
3542 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3543 | * just to make the assert_spin_locked check happy. */ | |
3544 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3b6c42e8 DV |
3545 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE); |
3546 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE); | |
3547 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE); | |
b79480ba | 3548 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
a266c7d5 | 3549 | |
a266c7d5 CW |
3550 | /* |
3551 | * Enable some error detection, note the instruction error mask | |
3552 | * bit is reserved, so we leave it masked. | |
3553 | */ | |
3554 | if (IS_G4X(dev)) { | |
3555 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
3556 | GM45_ERROR_MEM_PRIV | | |
3557 | GM45_ERROR_CP_PRIV | | |
3558 | I915_ERROR_MEMORY_REFRESH); | |
3559 | } else { | |
3560 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
3561 | I915_ERROR_MEMORY_REFRESH); | |
3562 | } | |
3563 | I915_WRITE(EMR, error_mask); | |
3564 | ||
3565 | I915_WRITE(IMR, dev_priv->irq_mask); | |
3566 | I915_WRITE(IER, enable_mask); | |
3567 | POSTING_READ(IER); | |
3568 | ||
20afbda2 DV |
3569 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3570 | POSTING_READ(PORT_HOTPLUG_EN); | |
3571 | ||
f49e38dd | 3572 | i915_enable_asle_pipestat(dev); |
20afbda2 DV |
3573 | |
3574 | return 0; | |
3575 | } | |
3576 | ||
bac56d5b | 3577 | static void i915_hpd_irq_setup(struct drm_device *dev) |
20afbda2 DV |
3578 | { |
3579 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e5868a31 | 3580 | struct drm_mode_config *mode_config = &dev->mode_config; |
cd569aed | 3581 | struct intel_encoder *intel_encoder; |
20afbda2 DV |
3582 | u32 hotplug_en; |
3583 | ||
b5ea2d56 DV |
3584 | assert_spin_locked(&dev_priv->irq_lock); |
3585 | ||
bac56d5b EE |
3586 | if (I915_HAS_HOTPLUG(dev)) { |
3587 | hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
3588 | hotplug_en &= ~HOTPLUG_INT_EN_MASK; | |
3589 | /* Note HDMI and DP share hotplug bits */ | |
e5868a31 | 3590 | /* enable bits are the same for all generations */ |
cd569aed EE |
3591 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
3592 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) | |
3593 | hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin]; | |
bac56d5b EE |
3594 | /* Programming the CRT detection parameters tends |
3595 | to generate a spurious hotplug event about three | |
3596 | seconds later. So just do it once. | |
3597 | */ | |
3598 | if (IS_G4X(dev)) | |
3599 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
85fc95ba | 3600 | hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK; |
bac56d5b | 3601 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
a266c7d5 | 3602 | |
bac56d5b EE |
3603 | /* Ignore TV since it's buggy */ |
3604 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
3605 | } | |
a266c7d5 CW |
3606 | } |
3607 | ||
ff1f525e | 3608 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
a266c7d5 CW |
3609 | { |
3610 | struct drm_device *dev = (struct drm_device *) arg; | |
3611 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
a266c7d5 CW |
3612 | u32 iir, new_iir; |
3613 | u32 pipe_stats[I915_MAX_PIPES]; | |
a266c7d5 CW |
3614 | unsigned long irqflags; |
3615 | int irq_received; | |
3616 | int ret = IRQ_NONE, pipe; | |
21ad8330 VS |
3617 | u32 flip_mask = |
3618 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3619 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
a266c7d5 CW |
3620 | |
3621 | atomic_inc(&dev_priv->irq_received); | |
3622 | ||
3623 | iir = I915_READ(IIR); | |
3624 | ||
a266c7d5 | 3625 | for (;;) { |
2c8ba29f CW |
3626 | bool blc_event = false; |
3627 | ||
21ad8330 | 3628 | irq_received = (iir & ~flip_mask) != 0; |
a266c7d5 CW |
3629 | |
3630 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3631 | * have been cleared after the pipestat interrupt was received. | |
3632 | * It doesn't set the bit in iir again, but it still produces | |
3633 | * interrupts (for non-MSI). | |
3634 | */ | |
3635 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3636 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
3637 | i915_handle_error(dev, false); | |
3638 | ||
3639 | for_each_pipe(pipe) { | |
3640 | int reg = PIPESTAT(pipe); | |
3641 | pipe_stats[pipe] = I915_READ(reg); | |
3642 | ||
3643 | /* | |
3644 | * Clear the PIPE*STAT regs before the IIR | |
3645 | */ | |
3646 | if (pipe_stats[pipe] & 0x8000ffff) { | |
3647 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | |
3648 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | |
3649 | pipe_name(pipe)); | |
3650 | I915_WRITE(reg, pipe_stats[pipe]); | |
3651 | irq_received = 1; | |
3652 | } | |
3653 | } | |
3654 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3655 | ||
3656 | if (!irq_received) | |
3657 | break; | |
3658 | ||
3659 | ret = IRQ_HANDLED; | |
3660 | ||
3661 | /* Consume port. Then clear IIR or we'll miss events */ | |
adca4730 | 3662 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { |
a266c7d5 | 3663 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
b543fb04 EE |
3664 | u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ? |
3665 | HOTPLUG_INT_STATUS_G4X : | |
4f7fd709 | 3666 | HOTPLUG_INT_STATUS_I915); |
a266c7d5 CW |
3667 | |
3668 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", | |
3669 | hotplug_status); | |
91d131d2 DV |
3670 | |
3671 | intel_hpd_irq_handler(dev, hotplug_trigger, | |
704cfb87 | 3672 | IS_G4X(dev) ? hpd_status_g4x : hpd_status_i915); |
91d131d2 | 3673 | |
4aeebd74 DV |
3674 | if (IS_G4X(dev) && |
3675 | (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)) | |
3676 | dp_aux_irq_handler(dev); | |
3677 | ||
a266c7d5 CW |
3678 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
3679 | I915_READ(PORT_HOTPLUG_STAT); | |
3680 | } | |
3681 | ||
21ad8330 | 3682 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
3683 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
3684 | ||
a266c7d5 CW |
3685 | if (iir & I915_USER_INTERRUPT) |
3686 | notify_ring(dev, &dev_priv->ring[RCS]); | |
3687 | if (iir & I915_BSD_USER_INTERRUPT) | |
3688 | notify_ring(dev, &dev_priv->ring[VCS]); | |
3689 | ||
a266c7d5 | 3690 | for_each_pipe(pipe) { |
2c8ba29f | 3691 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
3692 | i915_handle_vblank(dev, pipe, pipe, iir)) |
3693 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); | |
a266c7d5 CW |
3694 | |
3695 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
3696 | blc_event = true; | |
4356d586 DV |
3697 | |
3698 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 3699 | i9xx_pipe_crc_irq_handler(dev, pipe); |
a266c7d5 CW |
3700 | } |
3701 | ||
3702 | ||
3703 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | |
3704 | intel_opregion_asle_intr(dev); | |
3705 | ||
515ac2bb DV |
3706 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
3707 | gmbus_irq_handler(dev); | |
3708 | ||
a266c7d5 CW |
3709 | /* With MSI, interrupts are only generated when iir |
3710 | * transitions from zero to nonzero. If another bit got | |
3711 | * set while we were handling the existing iir bits, then | |
3712 | * we would never get another interrupt. | |
3713 | * | |
3714 | * This is fine on non-MSI as well, as if we hit this path | |
3715 | * we avoid exiting the interrupt handler only to generate | |
3716 | * another one. | |
3717 | * | |
3718 | * Note that for MSI this could cause a stray interrupt report | |
3719 | * if an interrupt landed in the time between writing IIR and | |
3720 | * the posting read. This should be rare enough to never | |
3721 | * trigger the 99% of 100,000 interrupts test for disabling | |
3722 | * stray interrupts. | |
3723 | */ | |
3724 | iir = new_iir; | |
3725 | } | |
3726 | ||
d05c617e | 3727 | i915_update_dri1_breadcrumb(dev); |
2c8ba29f | 3728 | |
a266c7d5 CW |
3729 | return ret; |
3730 | } | |
3731 | ||
3732 | static void i965_irq_uninstall(struct drm_device * dev) | |
3733 | { | |
3734 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
3735 | int pipe; | |
3736 | ||
3737 | if (!dev_priv) | |
3738 | return; | |
3739 | ||
ac4c16c5 EE |
3740 | del_timer_sync(&dev_priv->hotplug_reenable_timer); |
3741 | ||
adca4730 CW |
3742 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3743 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
3744 | |
3745 | I915_WRITE(HWSTAM, 0xffffffff); | |
3746 | for_each_pipe(pipe) | |
3747 | I915_WRITE(PIPESTAT(pipe), 0); | |
3748 | I915_WRITE(IMR, 0xffffffff); | |
3749 | I915_WRITE(IER, 0x0); | |
3750 | ||
3751 | for_each_pipe(pipe) | |
3752 | I915_WRITE(PIPESTAT(pipe), | |
3753 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); | |
3754 | I915_WRITE(IIR, I915_READ(IIR)); | |
3755 | } | |
3756 | ||
ac4c16c5 EE |
3757 | static void i915_reenable_hotplug_timer_func(unsigned long data) |
3758 | { | |
3759 | drm_i915_private_t *dev_priv = (drm_i915_private_t *)data; | |
3760 | struct drm_device *dev = dev_priv->dev; | |
3761 | struct drm_mode_config *mode_config = &dev->mode_config; | |
3762 | unsigned long irqflags; | |
3763 | int i; | |
3764 | ||
3765 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3766 | for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) { | |
3767 | struct drm_connector *connector; | |
3768 | ||
3769 | if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED) | |
3770 | continue; | |
3771 | ||
3772 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
3773 | ||
3774 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
3775 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
3776 | ||
3777 | if (intel_connector->encoder->hpd_pin == i) { | |
3778 | if (connector->polled != intel_connector->polled) | |
3779 | DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n", | |
3780 | drm_get_connector_name(connector)); | |
3781 | connector->polled = intel_connector->polled; | |
3782 | if (!connector->polled) | |
3783 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
3784 | } | |
3785 | } | |
3786 | } | |
3787 | if (dev_priv->display.hpd_irq_setup) | |
3788 | dev_priv->display.hpd_irq_setup(dev); | |
3789 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3790 | } | |
3791 | ||
f71d4af4 JB |
3792 | void intel_irq_init(struct drm_device *dev) |
3793 | { | |
8b2e326d CW |
3794 | struct drm_i915_private *dev_priv = dev->dev_private; |
3795 | ||
3796 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); | |
99584db3 | 3797 | INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func); |
c6a828d3 | 3798 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
a4da4fa4 | 3799 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
8b2e326d | 3800 | |
99584db3 DV |
3801 | setup_timer(&dev_priv->gpu_error.hangcheck_timer, |
3802 | i915_hangcheck_elapsed, | |
61bac78e | 3803 | (unsigned long) dev); |
ac4c16c5 EE |
3804 | setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func, |
3805 | (unsigned long) dev_priv); | |
61bac78e | 3806 | |
97a19a24 | 3807 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); |
9ee32fea | 3808 | |
4cdb83ec VS |
3809 | if (IS_GEN2(dev)) { |
3810 | dev->max_vblank_count = 0; | |
3811 | dev->driver->get_vblank_counter = i8xx_get_vblank_counter; | |
3812 | } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { | |
f71d4af4 JB |
3813 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
3814 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; | |
391f75e2 VS |
3815 | } else { |
3816 | dev->driver->get_vblank_counter = i915_get_vblank_counter; | |
3817 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
f71d4af4 JB |
3818 | } |
3819 | ||
c2baf4b7 | 3820 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
c3613de9 | 3821 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; |
c2baf4b7 VS |
3822 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; |
3823 | } | |
f71d4af4 | 3824 | |
7e231dbe JB |
3825 | if (IS_VALLEYVIEW(dev)) { |
3826 | dev->driver->irq_handler = valleyview_irq_handler; | |
3827 | dev->driver->irq_preinstall = valleyview_irq_preinstall; | |
3828 | dev->driver->irq_postinstall = valleyview_irq_postinstall; | |
3829 | dev->driver->irq_uninstall = valleyview_irq_uninstall; | |
3830 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
3831 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
fa00abe0 | 3832 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
abd58f01 BW |
3833 | } else if (IS_GEN8(dev)) { |
3834 | dev->driver->irq_handler = gen8_irq_handler; | |
3835 | dev->driver->irq_preinstall = gen8_irq_preinstall; | |
3836 | dev->driver->irq_postinstall = gen8_irq_postinstall; | |
3837 | dev->driver->irq_uninstall = gen8_irq_uninstall; | |
3838 | dev->driver->enable_vblank = gen8_enable_vblank; | |
3839 | dev->driver->disable_vblank = gen8_disable_vblank; | |
3840 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; | |
f71d4af4 JB |
3841 | } else if (HAS_PCH_SPLIT(dev)) { |
3842 | dev->driver->irq_handler = ironlake_irq_handler; | |
3843 | dev->driver->irq_preinstall = ironlake_irq_preinstall; | |
3844 | dev->driver->irq_postinstall = ironlake_irq_postinstall; | |
3845 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
3846 | dev->driver->enable_vblank = ironlake_enable_vblank; | |
3847 | dev->driver->disable_vblank = ironlake_disable_vblank; | |
82a28bcf | 3848 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; |
f71d4af4 | 3849 | } else { |
c2798b19 CW |
3850 | if (INTEL_INFO(dev)->gen == 2) { |
3851 | dev->driver->irq_preinstall = i8xx_irq_preinstall; | |
3852 | dev->driver->irq_postinstall = i8xx_irq_postinstall; | |
3853 | dev->driver->irq_handler = i8xx_irq_handler; | |
3854 | dev->driver->irq_uninstall = i8xx_irq_uninstall; | |
a266c7d5 CW |
3855 | } else if (INTEL_INFO(dev)->gen == 3) { |
3856 | dev->driver->irq_preinstall = i915_irq_preinstall; | |
3857 | dev->driver->irq_postinstall = i915_irq_postinstall; | |
3858 | dev->driver->irq_uninstall = i915_irq_uninstall; | |
3859 | dev->driver->irq_handler = i915_irq_handler; | |
20afbda2 | 3860 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
c2798b19 | 3861 | } else { |
a266c7d5 CW |
3862 | dev->driver->irq_preinstall = i965_irq_preinstall; |
3863 | dev->driver->irq_postinstall = i965_irq_postinstall; | |
3864 | dev->driver->irq_uninstall = i965_irq_uninstall; | |
3865 | dev->driver->irq_handler = i965_irq_handler; | |
bac56d5b | 3866 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
c2798b19 | 3867 | } |
f71d4af4 JB |
3868 | dev->driver->enable_vblank = i915_enable_vblank; |
3869 | dev->driver->disable_vblank = i915_disable_vblank; | |
3870 | } | |
3871 | } | |
20afbda2 DV |
3872 | |
3873 | void intel_hpd_init(struct drm_device *dev) | |
3874 | { | |
3875 | struct drm_i915_private *dev_priv = dev->dev_private; | |
821450c6 EE |
3876 | struct drm_mode_config *mode_config = &dev->mode_config; |
3877 | struct drm_connector *connector; | |
b5ea2d56 | 3878 | unsigned long irqflags; |
821450c6 | 3879 | int i; |
20afbda2 | 3880 | |
821450c6 EE |
3881 | for (i = 1; i < HPD_NUM_PINS; i++) { |
3882 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
3883 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
3884 | } | |
3885 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
3886 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
3887 | connector->polled = intel_connector->polled; | |
3888 | if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE) | |
3889 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
3890 | } | |
b5ea2d56 DV |
3891 | |
3892 | /* Interrupt setup is already guaranteed to be single-threaded, this is | |
3893 | * just to make the assert_spin_locked checks happy. */ | |
3894 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
20afbda2 DV |
3895 | if (dev_priv->display.hpd_irq_setup) |
3896 | dev_priv->display.hpd_irq_setup(dev); | |
b5ea2d56 | 3897 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
20afbda2 | 3898 | } |
c67a470b PZ |
3899 | |
3900 | /* Disable interrupts so we can allow Package C8+. */ | |
3901 | void hsw_pc8_disable_interrupts(struct drm_device *dev) | |
3902 | { | |
3903 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3904 | unsigned long irqflags; | |
3905 | ||
3906 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3907 | ||
3908 | dev_priv->pc8.regsave.deimr = I915_READ(DEIMR); | |
3909 | dev_priv->pc8.regsave.sdeimr = I915_READ(SDEIMR); | |
3910 | dev_priv->pc8.regsave.gtimr = I915_READ(GTIMR); | |
3911 | dev_priv->pc8.regsave.gtier = I915_READ(GTIER); | |
3912 | dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR); | |
3913 | ||
1f2d4531 PZ |
3914 | ironlake_disable_display_irq(dev_priv, 0xffffffff); |
3915 | ibx_disable_display_interrupt(dev_priv, 0xffffffff); | |
c67a470b PZ |
3916 | ilk_disable_gt_irq(dev_priv, 0xffffffff); |
3917 | snb_disable_pm_irq(dev_priv, 0xffffffff); | |
3918 | ||
3919 | dev_priv->pc8.irqs_disabled = true; | |
3920 | ||
3921 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3922 | } | |
3923 | ||
3924 | /* Restore interrupts so we can recover from Package C8+. */ | |
3925 | void hsw_pc8_restore_interrupts(struct drm_device *dev) | |
3926 | { | |
3927 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3928 | unsigned long irqflags; | |
1f2d4531 | 3929 | uint32_t val; |
c67a470b PZ |
3930 | |
3931 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3932 | ||
3933 | val = I915_READ(DEIMR); | |
1f2d4531 | 3934 | WARN(val != 0xffffffff, "DEIMR is 0x%08x\n", val); |
c67a470b | 3935 | |
1f2d4531 PZ |
3936 | val = I915_READ(SDEIMR); |
3937 | WARN(val != 0xffffffff, "SDEIMR is 0x%08x\n", val); | |
c67a470b PZ |
3938 | |
3939 | val = I915_READ(GTIMR); | |
1f2d4531 | 3940 | WARN(val != 0xffffffff, "GTIMR is 0x%08x\n", val); |
c67a470b PZ |
3941 | |
3942 | val = I915_READ(GEN6_PMIMR); | |
1f2d4531 | 3943 | WARN(val != 0xffffffff, "GEN6_PMIMR is 0x%08x\n", val); |
c67a470b PZ |
3944 | |
3945 | dev_priv->pc8.irqs_disabled = false; | |
3946 | ||
3947 | ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr); | |
1f2d4531 | 3948 | ibx_enable_display_interrupt(dev_priv, ~dev_priv->pc8.regsave.sdeimr); |
c67a470b PZ |
3949 | ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr); |
3950 | snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr); | |
3951 | I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier); | |
3952 | ||
3953 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3954 | } |