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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
63eeaf38 | 31 | #include <linux/sysrq.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
b2c88f5b | 33 | #include <linux/circ_buf.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/i915_drm.h> | |
1da177e4 | 36 | #include "i915_drv.h" |
1c5d22f7 | 37 | #include "i915_trace.h" |
79e53945 | 38 | #include "intel_drv.h" |
1da177e4 | 39 | |
e5868a31 EE |
40 | static const u32 hpd_ibx[] = { |
41 | [HPD_CRT] = SDE_CRT_HOTPLUG, | |
42 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, | |
43 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG, | |
44 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG, | |
45 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG | |
46 | }; | |
47 | ||
48 | static const u32 hpd_cpt[] = { | |
49 | [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, | |
73c352a2 | 50 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, |
e5868a31 EE |
51 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
52 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
53 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT | |
54 | }; | |
55 | ||
56 | static const u32 hpd_mask_i915[] = { | |
57 | [HPD_CRT] = CRT_HOTPLUG_INT_EN, | |
58 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, | |
59 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, | |
60 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, | |
61 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, | |
62 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN | |
63 | }; | |
64 | ||
704cfb87 | 65 | static const u32 hpd_status_g4x[] = { |
e5868a31 EE |
66 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
67 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, | |
68 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, | |
69 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
70 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
71 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
72 | }; | |
73 | ||
e5868a31 EE |
74 | static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ |
75 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, | |
76 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, | |
77 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, | |
78 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
79 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
80 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
81 | }; | |
82 | ||
5c502442 | 83 | /* IIR can theoretically queue up two events. Be paranoid. */ |
f86f3fb0 | 84 | #define GEN8_IRQ_RESET_NDX(type, which) do { \ |
5c502442 PZ |
85 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ |
86 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
87 | I915_WRITE(GEN8_##type##_IER(which), 0); \ | |
88 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
89 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
90 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
91 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
92 | } while (0) | |
93 | ||
f86f3fb0 | 94 | #define GEN5_IRQ_RESET(type) do { \ |
a9d356a6 | 95 | I915_WRITE(type##IMR, 0xffffffff); \ |
5c502442 | 96 | POSTING_READ(type##IMR); \ |
a9d356a6 | 97 | I915_WRITE(type##IER, 0); \ |
5c502442 PZ |
98 | I915_WRITE(type##IIR, 0xffffffff); \ |
99 | POSTING_READ(type##IIR); \ | |
100 | I915_WRITE(type##IIR, 0xffffffff); \ | |
101 | POSTING_READ(type##IIR); \ | |
a9d356a6 PZ |
102 | } while (0) |
103 | ||
337ba017 PZ |
104 | /* |
105 | * We should clear IMR at preinstall/uninstall, and just check at postinstall. | |
106 | */ | |
107 | #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \ | |
108 | u32 val = I915_READ(reg); \ | |
109 | if (val) { \ | |
110 | WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \ | |
111 | (reg), val); \ | |
112 | I915_WRITE((reg), 0xffffffff); \ | |
113 | POSTING_READ(reg); \ | |
114 | I915_WRITE((reg), 0xffffffff); \ | |
115 | POSTING_READ(reg); \ | |
116 | } \ | |
117 | } while (0) | |
118 | ||
35079899 | 119 | #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \ |
337ba017 | 120 | GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \ |
35079899 PZ |
121 | I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \ |
122 | I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \ | |
123 | POSTING_READ(GEN8_##type##_IER(which)); \ | |
124 | } while (0) | |
125 | ||
126 | #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \ | |
337ba017 | 127 | GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \ |
35079899 PZ |
128 | I915_WRITE(type##IMR, (imr_val)); \ |
129 | I915_WRITE(type##IER, (ier_val)); \ | |
130 | POSTING_READ(type##IER); \ | |
131 | } while (0) | |
132 | ||
036a4a7d | 133 | /* For display hotplug interrupt */ |
995b6762 | 134 | static void |
2d1013dd | 135 | ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask) |
036a4a7d | 136 | { |
4bc9d430 DV |
137 | assert_spin_locked(&dev_priv->irq_lock); |
138 | ||
730488b2 | 139 | if (WARN_ON(dev_priv->pm.irqs_disabled)) |
c67a470b | 140 | return; |
c67a470b | 141 | |
1ec14ad3 CW |
142 | if ((dev_priv->irq_mask & mask) != 0) { |
143 | dev_priv->irq_mask &= ~mask; | |
144 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 145 | POSTING_READ(DEIMR); |
036a4a7d ZW |
146 | } |
147 | } | |
148 | ||
0ff9800a | 149 | static void |
2d1013dd | 150 | ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask) |
036a4a7d | 151 | { |
4bc9d430 DV |
152 | assert_spin_locked(&dev_priv->irq_lock); |
153 | ||
730488b2 | 154 | if (WARN_ON(dev_priv->pm.irqs_disabled)) |
c67a470b | 155 | return; |
c67a470b | 156 | |
1ec14ad3 CW |
157 | if ((dev_priv->irq_mask & mask) != mask) { |
158 | dev_priv->irq_mask |= mask; | |
159 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 160 | POSTING_READ(DEIMR); |
036a4a7d ZW |
161 | } |
162 | } | |
163 | ||
43eaea13 PZ |
164 | /** |
165 | * ilk_update_gt_irq - update GTIMR | |
166 | * @dev_priv: driver private | |
167 | * @interrupt_mask: mask of interrupt bits to update | |
168 | * @enabled_irq_mask: mask of interrupt bits to enable | |
169 | */ | |
170 | static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, | |
171 | uint32_t interrupt_mask, | |
172 | uint32_t enabled_irq_mask) | |
173 | { | |
174 | assert_spin_locked(&dev_priv->irq_lock); | |
175 | ||
730488b2 | 176 | if (WARN_ON(dev_priv->pm.irqs_disabled)) |
c67a470b | 177 | return; |
c67a470b | 178 | |
43eaea13 PZ |
179 | dev_priv->gt_irq_mask &= ~interrupt_mask; |
180 | dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); | |
181 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
182 | POSTING_READ(GTIMR); | |
183 | } | |
184 | ||
185 | void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
186 | { | |
187 | ilk_update_gt_irq(dev_priv, mask, mask); | |
188 | } | |
189 | ||
190 | void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
191 | { | |
192 | ilk_update_gt_irq(dev_priv, mask, 0); | |
193 | } | |
194 | ||
edbfdb45 PZ |
195 | /** |
196 | * snb_update_pm_irq - update GEN6_PMIMR | |
197 | * @dev_priv: driver private | |
198 | * @interrupt_mask: mask of interrupt bits to update | |
199 | * @enabled_irq_mask: mask of interrupt bits to enable | |
200 | */ | |
201 | static void snb_update_pm_irq(struct drm_i915_private *dev_priv, | |
202 | uint32_t interrupt_mask, | |
203 | uint32_t enabled_irq_mask) | |
204 | { | |
605cd25b | 205 | uint32_t new_val; |
edbfdb45 PZ |
206 | |
207 | assert_spin_locked(&dev_priv->irq_lock); | |
208 | ||
730488b2 | 209 | if (WARN_ON(dev_priv->pm.irqs_disabled)) |
c67a470b | 210 | return; |
c67a470b | 211 | |
605cd25b | 212 | new_val = dev_priv->pm_irq_mask; |
f52ecbcf PZ |
213 | new_val &= ~interrupt_mask; |
214 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
215 | ||
605cd25b PZ |
216 | if (new_val != dev_priv->pm_irq_mask) { |
217 | dev_priv->pm_irq_mask = new_val; | |
218 | I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask); | |
f52ecbcf PZ |
219 | POSTING_READ(GEN6_PMIMR); |
220 | } | |
edbfdb45 PZ |
221 | } |
222 | ||
223 | void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
224 | { | |
225 | snb_update_pm_irq(dev_priv, mask, mask); | |
226 | } | |
227 | ||
228 | void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
229 | { | |
230 | snb_update_pm_irq(dev_priv, mask, 0); | |
231 | } | |
232 | ||
8664281b PZ |
233 | static bool ivb_can_enable_err_int(struct drm_device *dev) |
234 | { | |
235 | struct drm_i915_private *dev_priv = dev->dev_private; | |
236 | struct intel_crtc *crtc; | |
237 | enum pipe pipe; | |
238 | ||
4bc9d430 DV |
239 | assert_spin_locked(&dev_priv->irq_lock); |
240 | ||
8664281b PZ |
241 | for_each_pipe(pipe) { |
242 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
243 | ||
244 | if (crtc->cpu_fifo_underrun_disabled) | |
245 | return false; | |
246 | } | |
247 | ||
248 | return true; | |
249 | } | |
250 | ||
0961021a BW |
251 | /** |
252 | * bdw_update_pm_irq - update GT interrupt 2 | |
253 | * @dev_priv: driver private | |
254 | * @interrupt_mask: mask of interrupt bits to update | |
255 | * @enabled_irq_mask: mask of interrupt bits to enable | |
256 | * | |
257 | * Copied from the snb function, updated with relevant register offsets | |
258 | */ | |
259 | static void bdw_update_pm_irq(struct drm_i915_private *dev_priv, | |
260 | uint32_t interrupt_mask, | |
261 | uint32_t enabled_irq_mask) | |
262 | { | |
263 | uint32_t new_val; | |
264 | ||
265 | assert_spin_locked(&dev_priv->irq_lock); | |
266 | ||
267 | if (WARN_ON(dev_priv->pm.irqs_disabled)) | |
268 | return; | |
269 | ||
270 | new_val = dev_priv->pm_irq_mask; | |
271 | new_val &= ~interrupt_mask; | |
272 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
273 | ||
274 | if (new_val != dev_priv->pm_irq_mask) { | |
275 | dev_priv->pm_irq_mask = new_val; | |
276 | I915_WRITE(GEN8_GT_IMR(2), dev_priv->pm_irq_mask); | |
277 | POSTING_READ(GEN8_GT_IMR(2)); | |
278 | } | |
279 | } | |
280 | ||
281 | void bdw_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
282 | { | |
283 | bdw_update_pm_irq(dev_priv, mask, mask); | |
284 | } | |
285 | ||
286 | void bdw_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
287 | { | |
288 | bdw_update_pm_irq(dev_priv, mask, 0); | |
289 | } | |
290 | ||
8664281b PZ |
291 | static bool cpt_can_enable_serr_int(struct drm_device *dev) |
292 | { | |
293 | struct drm_i915_private *dev_priv = dev->dev_private; | |
294 | enum pipe pipe; | |
295 | struct intel_crtc *crtc; | |
296 | ||
fee884ed DV |
297 | assert_spin_locked(&dev_priv->irq_lock); |
298 | ||
8664281b PZ |
299 | for_each_pipe(pipe) { |
300 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
301 | ||
302 | if (crtc->pch_fifo_underrun_disabled) | |
303 | return false; | |
304 | } | |
305 | ||
306 | return true; | |
307 | } | |
308 | ||
2d9d2b0b VS |
309 | static void i9xx_clear_fifo_underrun(struct drm_device *dev, enum pipe pipe) |
310 | { | |
311 | struct drm_i915_private *dev_priv = dev->dev_private; | |
312 | u32 reg = PIPESTAT(pipe); | |
313 | u32 pipestat = I915_READ(reg) & 0x7fff0000; | |
314 | ||
315 | assert_spin_locked(&dev_priv->irq_lock); | |
316 | ||
317 | I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS); | |
318 | POSTING_READ(reg); | |
319 | } | |
320 | ||
8664281b PZ |
321 | static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev, |
322 | enum pipe pipe, bool enable) | |
323 | { | |
324 | struct drm_i915_private *dev_priv = dev->dev_private; | |
325 | uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN : | |
326 | DE_PIPEB_FIFO_UNDERRUN; | |
327 | ||
328 | if (enable) | |
329 | ironlake_enable_display_irq(dev_priv, bit); | |
330 | else | |
331 | ironlake_disable_display_irq(dev_priv, bit); | |
332 | } | |
333 | ||
334 | static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev, | |
7336df65 | 335 | enum pipe pipe, bool enable) |
8664281b PZ |
336 | { |
337 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8664281b | 338 | if (enable) { |
7336df65 DV |
339 | I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); |
340 | ||
8664281b PZ |
341 | if (!ivb_can_enable_err_int(dev)) |
342 | return; | |
343 | ||
8664281b PZ |
344 | ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB); |
345 | } else { | |
7336df65 DV |
346 | bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB); |
347 | ||
348 | /* Change the state _after_ we've read out the current one. */ | |
8664281b | 349 | ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB); |
7336df65 DV |
350 | |
351 | if (!was_enabled && | |
352 | (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) { | |
823c6909 VS |
353 | DRM_ERROR("uncleared fifo underrun on pipe %c\n", |
354 | pipe_name(pipe)); | |
7336df65 | 355 | } |
8664281b PZ |
356 | } |
357 | } | |
358 | ||
38d83c96 DV |
359 | static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev, |
360 | enum pipe pipe, bool enable) | |
361 | { | |
362 | struct drm_i915_private *dev_priv = dev->dev_private; | |
363 | ||
364 | assert_spin_locked(&dev_priv->irq_lock); | |
365 | ||
366 | if (enable) | |
367 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN; | |
368 | else | |
369 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN; | |
370 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
371 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
372 | } | |
373 | ||
fee884ed DV |
374 | /** |
375 | * ibx_display_interrupt_update - update SDEIMR | |
376 | * @dev_priv: driver private | |
377 | * @interrupt_mask: mask of interrupt bits to update | |
378 | * @enabled_irq_mask: mask of interrupt bits to enable | |
379 | */ | |
380 | static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, | |
381 | uint32_t interrupt_mask, | |
382 | uint32_t enabled_irq_mask) | |
383 | { | |
384 | uint32_t sdeimr = I915_READ(SDEIMR); | |
385 | sdeimr &= ~interrupt_mask; | |
386 | sdeimr |= (~enabled_irq_mask & interrupt_mask); | |
387 | ||
388 | assert_spin_locked(&dev_priv->irq_lock); | |
389 | ||
730488b2 | 390 | if (WARN_ON(dev_priv->pm.irqs_disabled)) |
c67a470b | 391 | return; |
c67a470b | 392 | |
fee884ed DV |
393 | I915_WRITE(SDEIMR, sdeimr); |
394 | POSTING_READ(SDEIMR); | |
395 | } | |
396 | #define ibx_enable_display_interrupt(dev_priv, bits) \ | |
397 | ibx_display_interrupt_update((dev_priv), (bits), (bits)) | |
398 | #define ibx_disable_display_interrupt(dev_priv, bits) \ | |
399 | ibx_display_interrupt_update((dev_priv), (bits), 0) | |
400 | ||
de28075d DV |
401 | static void ibx_set_fifo_underrun_reporting(struct drm_device *dev, |
402 | enum transcoder pch_transcoder, | |
8664281b PZ |
403 | bool enable) |
404 | { | |
8664281b | 405 | struct drm_i915_private *dev_priv = dev->dev_private; |
de28075d DV |
406 | uint32_t bit = (pch_transcoder == TRANSCODER_A) ? |
407 | SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER; | |
8664281b PZ |
408 | |
409 | if (enable) | |
fee884ed | 410 | ibx_enable_display_interrupt(dev_priv, bit); |
8664281b | 411 | else |
fee884ed | 412 | ibx_disable_display_interrupt(dev_priv, bit); |
8664281b PZ |
413 | } |
414 | ||
415 | static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, | |
416 | enum transcoder pch_transcoder, | |
417 | bool enable) | |
418 | { | |
419 | struct drm_i915_private *dev_priv = dev->dev_private; | |
420 | ||
421 | if (enable) { | |
1dd246fb DV |
422 | I915_WRITE(SERR_INT, |
423 | SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); | |
424 | ||
8664281b PZ |
425 | if (!cpt_can_enable_serr_int(dev)) |
426 | return; | |
427 | ||
fee884ed | 428 | ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
8664281b | 429 | } else { |
1dd246fb DV |
430 | uint32_t tmp = I915_READ(SERR_INT); |
431 | bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT); | |
432 | ||
433 | /* Change the state _after_ we've read out the current one. */ | |
fee884ed | 434 | ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
1dd246fb DV |
435 | |
436 | if (!was_enabled && | |
437 | (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) { | |
823c6909 VS |
438 | DRM_ERROR("uncleared pch fifo underrun on pch transcoder %c\n", |
439 | transcoder_name(pch_transcoder)); | |
1dd246fb | 440 | } |
8664281b | 441 | } |
8664281b PZ |
442 | } |
443 | ||
444 | /** | |
445 | * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages | |
446 | * @dev: drm device | |
447 | * @pipe: pipe | |
448 | * @enable: true if we want to report FIFO underrun errors, false otherwise | |
449 | * | |
450 | * This function makes us disable or enable CPU fifo underruns for a specific | |
451 | * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun | |
452 | * reporting for one pipe may also disable all the other CPU error interruts for | |
453 | * the other pipes, due to the fact that there's just one interrupt mask/enable | |
454 | * bit for all the pipes. | |
455 | * | |
456 | * Returns the previous state of underrun reporting. | |
457 | */ | |
f88d42f1 ID |
458 | bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, |
459 | enum pipe pipe, bool enable) | |
8664281b PZ |
460 | { |
461 | struct drm_i915_private *dev_priv = dev->dev_private; | |
462 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
463 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8664281b PZ |
464 | bool ret; |
465 | ||
77961eb9 ID |
466 | assert_spin_locked(&dev_priv->irq_lock); |
467 | ||
8664281b PZ |
468 | ret = !intel_crtc->cpu_fifo_underrun_disabled; |
469 | ||
470 | if (enable == ret) | |
471 | goto done; | |
472 | ||
473 | intel_crtc->cpu_fifo_underrun_disabled = !enable; | |
474 | ||
2d9d2b0b VS |
475 | if (enable && (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))) |
476 | i9xx_clear_fifo_underrun(dev, pipe); | |
477 | else if (IS_GEN5(dev) || IS_GEN6(dev)) | |
8664281b PZ |
478 | ironlake_set_fifo_underrun_reporting(dev, pipe, enable); |
479 | else if (IS_GEN7(dev)) | |
7336df65 | 480 | ivybridge_set_fifo_underrun_reporting(dev, pipe, enable); |
38d83c96 DV |
481 | else if (IS_GEN8(dev)) |
482 | broadwell_set_fifo_underrun_reporting(dev, pipe, enable); | |
8664281b PZ |
483 | |
484 | done: | |
f88d42f1 ID |
485 | return ret; |
486 | } | |
487 | ||
488 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, | |
489 | enum pipe pipe, bool enable) | |
490 | { | |
491 | struct drm_i915_private *dev_priv = dev->dev_private; | |
492 | unsigned long flags; | |
493 | bool ret; | |
494 | ||
495 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
496 | ret = __intel_set_cpu_fifo_underrun_reporting(dev, pipe, enable); | |
8664281b | 497 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
f88d42f1 | 498 | |
8664281b PZ |
499 | return ret; |
500 | } | |
501 | ||
91d181dd ID |
502 | static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev, |
503 | enum pipe pipe) | |
504 | { | |
505 | struct drm_i915_private *dev_priv = dev->dev_private; | |
506 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
507 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
508 | ||
509 | return !intel_crtc->cpu_fifo_underrun_disabled; | |
510 | } | |
511 | ||
8664281b PZ |
512 | /** |
513 | * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages | |
514 | * @dev: drm device | |
515 | * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) | |
516 | * @enable: true if we want to report FIFO underrun errors, false otherwise | |
517 | * | |
518 | * This function makes us disable or enable PCH fifo underruns for a specific | |
519 | * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO | |
520 | * underrun reporting for one transcoder may also disable all the other PCH | |
521 | * error interruts for the other transcoders, due to the fact that there's just | |
522 | * one interrupt mask/enable bit for all the transcoders. | |
523 | * | |
524 | * Returns the previous state of underrun reporting. | |
525 | */ | |
526 | bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, | |
527 | enum transcoder pch_transcoder, | |
528 | bool enable) | |
529 | { | |
530 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de28075d DV |
531 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder]; |
532 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8664281b PZ |
533 | unsigned long flags; |
534 | bool ret; | |
535 | ||
de28075d DV |
536 | /* |
537 | * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT | |
538 | * has only one pch transcoder A that all pipes can use. To avoid racy | |
539 | * pch transcoder -> pipe lookups from interrupt code simply store the | |
540 | * underrun statistics in crtc A. Since we never expose this anywhere | |
541 | * nor use it outside of the fifo underrun code here using the "wrong" | |
542 | * crtc on LPT won't cause issues. | |
543 | */ | |
8664281b PZ |
544 | |
545 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
546 | ||
547 | ret = !intel_crtc->pch_fifo_underrun_disabled; | |
548 | ||
549 | if (enable == ret) | |
550 | goto done; | |
551 | ||
552 | intel_crtc->pch_fifo_underrun_disabled = !enable; | |
553 | ||
554 | if (HAS_PCH_IBX(dev)) | |
de28075d | 555 | ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable); |
8664281b PZ |
556 | else |
557 | cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable); | |
558 | ||
559 | done: | |
560 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
561 | return ret; | |
562 | } | |
563 | ||
564 | ||
b5ea642a | 565 | static void |
755e9019 ID |
566 | __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
567 | u32 enable_mask, u32 status_mask) | |
7c463586 | 568 | { |
46c06a30 | 569 | u32 reg = PIPESTAT(pipe); |
755e9019 | 570 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 571 | |
b79480ba DV |
572 | assert_spin_locked(&dev_priv->irq_lock); |
573 | ||
04feced9 VS |
574 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
575 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
576 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
577 | pipe_name(pipe), enable_mask, status_mask)) | |
755e9019 ID |
578 | return; |
579 | ||
580 | if ((pipestat & enable_mask) == enable_mask) | |
46c06a30 VS |
581 | return; |
582 | ||
91d181dd ID |
583 | dev_priv->pipestat_irq_mask[pipe] |= status_mask; |
584 | ||
46c06a30 | 585 | /* Enable the interrupt, clear any pending status */ |
755e9019 | 586 | pipestat |= enable_mask | status_mask; |
46c06a30 VS |
587 | I915_WRITE(reg, pipestat); |
588 | POSTING_READ(reg); | |
7c463586 KP |
589 | } |
590 | ||
b5ea642a | 591 | static void |
755e9019 ID |
592 | __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
593 | u32 enable_mask, u32 status_mask) | |
7c463586 | 594 | { |
46c06a30 | 595 | u32 reg = PIPESTAT(pipe); |
755e9019 | 596 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 597 | |
b79480ba DV |
598 | assert_spin_locked(&dev_priv->irq_lock); |
599 | ||
04feced9 VS |
600 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
601 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
602 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
603 | pipe_name(pipe), enable_mask, status_mask)) | |
46c06a30 VS |
604 | return; |
605 | ||
755e9019 ID |
606 | if ((pipestat & enable_mask) == 0) |
607 | return; | |
608 | ||
91d181dd ID |
609 | dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; |
610 | ||
755e9019 | 611 | pipestat &= ~enable_mask; |
46c06a30 VS |
612 | I915_WRITE(reg, pipestat); |
613 | POSTING_READ(reg); | |
7c463586 KP |
614 | } |
615 | ||
10c59c51 ID |
616 | static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask) |
617 | { | |
618 | u32 enable_mask = status_mask << 16; | |
619 | ||
620 | /* | |
621 | * On pipe A we don't support the PSR interrupt yet, on pipe B the | |
622 | * same bit MBZ. | |
623 | */ | |
624 | if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV)) | |
625 | return 0; | |
626 | ||
627 | enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | | |
628 | SPRITE0_FLIP_DONE_INT_EN_VLV | | |
629 | SPRITE1_FLIP_DONE_INT_EN_VLV); | |
630 | if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV) | |
631 | enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV; | |
632 | if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV) | |
633 | enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; | |
634 | ||
635 | return enable_mask; | |
636 | } | |
637 | ||
755e9019 ID |
638 | void |
639 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
640 | u32 status_mask) | |
641 | { | |
642 | u32 enable_mask; | |
643 | ||
10c59c51 ID |
644 | if (IS_VALLEYVIEW(dev_priv->dev)) |
645 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, | |
646 | status_mask); | |
647 | else | |
648 | enable_mask = status_mask << 16; | |
755e9019 ID |
649 | __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
650 | } | |
651 | ||
652 | void | |
653 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
654 | u32 status_mask) | |
655 | { | |
656 | u32 enable_mask; | |
657 | ||
10c59c51 ID |
658 | if (IS_VALLEYVIEW(dev_priv->dev)) |
659 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, | |
660 | status_mask); | |
661 | else | |
662 | enable_mask = status_mask << 16; | |
755e9019 ID |
663 | __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
664 | } | |
665 | ||
01c66889 | 666 | /** |
f49e38dd | 667 | * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion |
01c66889 | 668 | */ |
f49e38dd | 669 | static void i915_enable_asle_pipestat(struct drm_device *dev) |
01c66889 | 670 | { |
2d1013dd | 671 | struct drm_i915_private *dev_priv = dev->dev_private; |
1ec14ad3 CW |
672 | unsigned long irqflags; |
673 | ||
f49e38dd JN |
674 | if (!dev_priv->opregion.asle || !IS_MOBILE(dev)) |
675 | return; | |
676 | ||
1ec14ad3 | 677 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
01c66889 | 678 | |
755e9019 | 679 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); |
f898780b | 680 | if (INTEL_INFO(dev)->gen >= 4) |
3b6c42e8 | 681 | i915_enable_pipestat(dev_priv, PIPE_A, |
755e9019 | 682 | PIPE_LEGACY_BLC_EVENT_STATUS); |
1ec14ad3 CW |
683 | |
684 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
01c66889 ZY |
685 | } |
686 | ||
0a3e67a4 JB |
687 | /** |
688 | * i915_pipe_enabled - check if a pipe is enabled | |
689 | * @dev: DRM device | |
690 | * @pipe: pipe to check | |
691 | * | |
692 | * Reading certain registers when the pipe is disabled can hang the chip. | |
693 | * Use this routine to make sure the PLL is running and the pipe is active | |
694 | * before reading such registers if unsure. | |
695 | */ | |
696 | static int | |
697 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
698 | { | |
2d1013dd | 699 | struct drm_i915_private *dev_priv = dev->dev_private; |
702e7a56 | 700 | |
a01025af DV |
701 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
702 | /* Locking is horribly broken here, but whatever. */ | |
703 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
704 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
71f8ba6b | 705 | |
a01025af DV |
706 | return intel_crtc->active; |
707 | } else { | |
708 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; | |
709 | } | |
0a3e67a4 JB |
710 | } |
711 | ||
4cdb83ec VS |
712 | static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe) |
713 | { | |
714 | /* Gen2 doesn't have a hardware frame counter */ | |
715 | return 0; | |
716 | } | |
717 | ||
42f52ef8 KP |
718 | /* Called from drm generic code, passed a 'crtc', which |
719 | * we use as a pipe index | |
720 | */ | |
f71d4af4 | 721 | static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
0a3e67a4 | 722 | { |
2d1013dd | 723 | struct drm_i915_private *dev_priv = dev->dev_private; |
0a3e67a4 JB |
724 | unsigned long high_frame; |
725 | unsigned long low_frame; | |
391f75e2 | 726 | u32 high1, high2, low, pixel, vbl_start; |
0a3e67a4 JB |
727 | |
728 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 729 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 730 | "pipe %c\n", pipe_name(pipe)); |
0a3e67a4 JB |
731 | return 0; |
732 | } | |
733 | ||
391f75e2 VS |
734 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
735 | struct intel_crtc *intel_crtc = | |
736 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
737 | const struct drm_display_mode *mode = | |
738 | &intel_crtc->config.adjusted_mode; | |
739 | ||
740 | vbl_start = mode->crtc_vblank_start * mode->crtc_htotal; | |
741 | } else { | |
a2d213dd | 742 | enum transcoder cpu_transcoder = (enum transcoder) pipe; |
391f75e2 VS |
743 | u32 htotal; |
744 | ||
745 | htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1; | |
746 | vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1; | |
747 | ||
748 | vbl_start *= htotal; | |
749 | } | |
750 | ||
9db4a9c7 JB |
751 | high_frame = PIPEFRAME(pipe); |
752 | low_frame = PIPEFRAMEPIXEL(pipe); | |
5eddb70b | 753 | |
0a3e67a4 JB |
754 | /* |
755 | * High & low register fields aren't synchronized, so make sure | |
756 | * we get a low value that's stable across two reads of the high | |
757 | * register. | |
758 | */ | |
759 | do { | |
5eddb70b | 760 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
391f75e2 | 761 | low = I915_READ(low_frame); |
5eddb70b | 762 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
0a3e67a4 JB |
763 | } while (high1 != high2); |
764 | ||
5eddb70b | 765 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
391f75e2 | 766 | pixel = low & PIPE_PIXEL_MASK; |
5eddb70b | 767 | low >>= PIPE_FRAME_LOW_SHIFT; |
391f75e2 VS |
768 | |
769 | /* | |
770 | * The frame counter increments at beginning of active. | |
771 | * Cook up a vblank counter by also checking the pixel | |
772 | * counter against vblank start. | |
773 | */ | |
edc08d0a | 774 | return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; |
0a3e67a4 JB |
775 | } |
776 | ||
f71d4af4 | 777 | static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
9880b7a5 | 778 | { |
2d1013dd | 779 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 780 | int reg = PIPE_FRMCOUNT_GM45(pipe); |
9880b7a5 JB |
781 | |
782 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 783 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 784 | "pipe %c\n", pipe_name(pipe)); |
9880b7a5 JB |
785 | return 0; |
786 | } | |
787 | ||
788 | return I915_READ(reg); | |
789 | } | |
790 | ||
ad3543ed MK |
791 | /* raw reads, only for fast reads of display block, no need for forcewake etc. */ |
792 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) | |
ad3543ed | 793 | |
a225f079 VS |
794 | static int __intel_get_crtc_scanline(struct intel_crtc *crtc) |
795 | { | |
796 | struct drm_device *dev = crtc->base.dev; | |
797 | struct drm_i915_private *dev_priv = dev->dev_private; | |
798 | const struct drm_display_mode *mode = &crtc->config.adjusted_mode; | |
799 | enum pipe pipe = crtc->pipe; | |
800 | int vtotal = mode->crtc_vtotal; | |
801 | int position; | |
802 | ||
803 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
804 | vtotal /= 2; | |
805 | ||
806 | if (IS_GEN2(dev)) | |
807 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; | |
808 | else | |
809 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; | |
810 | ||
811 | /* | |
812 | * Scanline counter increments at leading edge of hsync, and | |
813 | * it starts counting from vtotal-1 on the first active line. | |
814 | * That means the scanline counter value is always one less | |
815 | * than what we would expect. Ie. just after start of vblank, | |
816 | * which also occurs at start of hsync (on the last active line), | |
817 | * the scanline counter will read vblank_start-1. | |
818 | */ | |
819 | return (position + 1) % vtotal; | |
820 | } | |
821 | ||
f71d4af4 | 822 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
abca9e45 VS |
823 | unsigned int flags, int *vpos, int *hpos, |
824 | ktime_t *stime, ktime_t *etime) | |
0af7e4df | 825 | { |
c2baf4b7 VS |
826 | struct drm_i915_private *dev_priv = dev->dev_private; |
827 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
828 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
829 | const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; | |
3aa18df8 | 830 | int position; |
78e8fc6b | 831 | int vbl_start, vbl_end, hsync_start, htotal, vtotal; |
0af7e4df MK |
832 | bool in_vbl = true; |
833 | int ret = 0; | |
ad3543ed | 834 | unsigned long irqflags; |
0af7e4df | 835 | |
c2baf4b7 | 836 | if (!intel_crtc->active) { |
0af7e4df | 837 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
9db4a9c7 | 838 | "pipe %c\n", pipe_name(pipe)); |
0af7e4df MK |
839 | return 0; |
840 | } | |
841 | ||
c2baf4b7 | 842 | htotal = mode->crtc_htotal; |
78e8fc6b | 843 | hsync_start = mode->crtc_hsync_start; |
c2baf4b7 VS |
844 | vtotal = mode->crtc_vtotal; |
845 | vbl_start = mode->crtc_vblank_start; | |
846 | vbl_end = mode->crtc_vblank_end; | |
0af7e4df | 847 | |
d31faf65 VS |
848 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
849 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
850 | vbl_end /= 2; | |
851 | vtotal /= 2; | |
852 | } | |
853 | ||
c2baf4b7 VS |
854 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; |
855 | ||
ad3543ed MK |
856 | /* |
857 | * Lock uncore.lock, as we will do multiple timing critical raw | |
858 | * register reads, potentially with preemption disabled, so the | |
859 | * following code must not block on uncore.lock. | |
860 | */ | |
861 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
78e8fc6b | 862 | |
ad3543ed MK |
863 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ |
864 | ||
865 | /* Get optional system timestamp before query. */ | |
866 | if (stime) | |
867 | *stime = ktime_get(); | |
868 | ||
7c06b08a | 869 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
0af7e4df MK |
870 | /* No obvious pixelcount register. Only query vertical |
871 | * scanout position from Display scan line register. | |
872 | */ | |
a225f079 | 873 | position = __intel_get_crtc_scanline(intel_crtc); |
0af7e4df MK |
874 | } else { |
875 | /* Have access to pixelcount since start of frame. | |
876 | * We can split this into vertical and horizontal | |
877 | * scanout position. | |
878 | */ | |
ad3543ed | 879 | position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; |
0af7e4df | 880 | |
3aa18df8 VS |
881 | /* convert to pixel counts */ |
882 | vbl_start *= htotal; | |
883 | vbl_end *= htotal; | |
884 | vtotal *= htotal; | |
78e8fc6b VS |
885 | |
886 | /* | |
887 | * Start of vblank interrupt is triggered at start of hsync, | |
888 | * just prior to the first active line of vblank. However we | |
889 | * consider lines to start at the leading edge of horizontal | |
890 | * active. So, should we get here before we've crossed into | |
891 | * the horizontal active of the first line in vblank, we would | |
892 | * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that, | |
893 | * always add htotal-hsync_start to the current pixel position. | |
894 | */ | |
895 | position = (position + htotal - hsync_start) % vtotal; | |
0af7e4df MK |
896 | } |
897 | ||
ad3543ed MK |
898 | /* Get optional system timestamp after query. */ |
899 | if (etime) | |
900 | *etime = ktime_get(); | |
901 | ||
902 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ | |
903 | ||
904 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
905 | ||
3aa18df8 VS |
906 | in_vbl = position >= vbl_start && position < vbl_end; |
907 | ||
908 | /* | |
909 | * While in vblank, position will be negative | |
910 | * counting up towards 0 at vbl_end. And outside | |
911 | * vblank, position will be positive counting | |
912 | * up since vbl_end. | |
913 | */ | |
914 | if (position >= vbl_start) | |
915 | position -= vbl_end; | |
916 | else | |
917 | position += vtotal - vbl_end; | |
0af7e4df | 918 | |
7c06b08a | 919 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
3aa18df8 VS |
920 | *vpos = position; |
921 | *hpos = 0; | |
922 | } else { | |
923 | *vpos = position / htotal; | |
924 | *hpos = position - (*vpos * htotal); | |
925 | } | |
0af7e4df | 926 | |
0af7e4df MK |
927 | /* In vblank? */ |
928 | if (in_vbl) | |
929 | ret |= DRM_SCANOUTPOS_INVBL; | |
930 | ||
931 | return ret; | |
932 | } | |
933 | ||
a225f079 VS |
934 | int intel_get_crtc_scanline(struct intel_crtc *crtc) |
935 | { | |
936 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
937 | unsigned long irqflags; | |
938 | int position; | |
939 | ||
940 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
941 | position = __intel_get_crtc_scanline(crtc); | |
942 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
943 | ||
944 | return position; | |
945 | } | |
946 | ||
f71d4af4 | 947 | static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
0af7e4df MK |
948 | int *max_error, |
949 | struct timeval *vblank_time, | |
950 | unsigned flags) | |
951 | { | |
4041b853 | 952 | struct drm_crtc *crtc; |
0af7e4df | 953 | |
7eb552ae | 954 | if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { |
4041b853 | 955 | DRM_ERROR("Invalid crtc %d\n", pipe); |
0af7e4df MK |
956 | return -EINVAL; |
957 | } | |
958 | ||
959 | /* Get drm_crtc to timestamp: */ | |
4041b853 CW |
960 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
961 | if (crtc == NULL) { | |
962 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
963 | return -EINVAL; | |
964 | } | |
965 | ||
966 | if (!crtc->enabled) { | |
967 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); | |
968 | return -EBUSY; | |
969 | } | |
0af7e4df MK |
970 | |
971 | /* Helper routine in DRM core does all the work: */ | |
4041b853 CW |
972 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
973 | vblank_time, flags, | |
7da903ef VS |
974 | crtc, |
975 | &to_intel_crtc(crtc)->config.adjusted_mode); | |
0af7e4df MK |
976 | } |
977 | ||
67c347ff JN |
978 | static bool intel_hpd_irq_event(struct drm_device *dev, |
979 | struct drm_connector *connector) | |
321a1b30 EE |
980 | { |
981 | enum drm_connector_status old_status; | |
982 | ||
983 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); | |
984 | old_status = connector->status; | |
985 | ||
986 | connector->status = connector->funcs->detect(connector, false); | |
67c347ff JN |
987 | if (old_status == connector->status) |
988 | return false; | |
989 | ||
990 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n", | |
321a1b30 EE |
991 | connector->base.id, |
992 | drm_get_connector_name(connector), | |
67c347ff JN |
993 | drm_get_connector_status_name(old_status), |
994 | drm_get_connector_status_name(connector->status)); | |
995 | ||
996 | return true; | |
321a1b30 EE |
997 | } |
998 | ||
5ca58282 JB |
999 | /* |
1000 | * Handle hotplug events outside the interrupt handler proper. | |
1001 | */ | |
ac4c16c5 EE |
1002 | #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000) |
1003 | ||
5ca58282 JB |
1004 | static void i915_hotplug_work_func(struct work_struct *work) |
1005 | { | |
2d1013dd JN |
1006 | struct drm_i915_private *dev_priv = |
1007 | container_of(work, struct drm_i915_private, hotplug_work); | |
5ca58282 | 1008 | struct drm_device *dev = dev_priv->dev; |
c31c4ba3 | 1009 | struct drm_mode_config *mode_config = &dev->mode_config; |
cd569aed EE |
1010 | struct intel_connector *intel_connector; |
1011 | struct intel_encoder *intel_encoder; | |
1012 | struct drm_connector *connector; | |
1013 | unsigned long irqflags; | |
1014 | bool hpd_disabled = false; | |
321a1b30 | 1015 | bool changed = false; |
142e2398 | 1016 | u32 hpd_event_bits; |
4ef69c7a | 1017 | |
52d7eced DV |
1018 | /* HPD irq before everything is fully set up. */ |
1019 | if (!dev_priv->enable_hotplug_processing) | |
1020 | return; | |
1021 | ||
a65e34c7 | 1022 | mutex_lock(&mode_config->mutex); |
e67189ab JB |
1023 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); |
1024 | ||
cd569aed | 1025 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
142e2398 EE |
1026 | |
1027 | hpd_event_bits = dev_priv->hpd_event_bits; | |
1028 | dev_priv->hpd_event_bits = 0; | |
cd569aed EE |
1029 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
1030 | intel_connector = to_intel_connector(connector); | |
1031 | intel_encoder = intel_connector->encoder; | |
1032 | if (intel_encoder->hpd_pin > HPD_NONE && | |
1033 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED && | |
1034 | connector->polled == DRM_CONNECTOR_POLL_HPD) { | |
1035 | DRM_INFO("HPD interrupt storm detected on connector %s: " | |
1036 | "switching from hotplug detection to polling\n", | |
1037 | drm_get_connector_name(connector)); | |
1038 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED; | |
1039 | connector->polled = DRM_CONNECTOR_POLL_CONNECT | |
1040 | | DRM_CONNECTOR_POLL_DISCONNECT; | |
1041 | hpd_disabled = true; | |
1042 | } | |
142e2398 EE |
1043 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { |
1044 | DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n", | |
1045 | drm_get_connector_name(connector), intel_encoder->hpd_pin); | |
1046 | } | |
cd569aed EE |
1047 | } |
1048 | /* if there were no outputs to poll, poll was disabled, | |
1049 | * therefore make sure it's enabled when disabling HPD on | |
1050 | * some connectors */ | |
ac4c16c5 | 1051 | if (hpd_disabled) { |
cd569aed | 1052 | drm_kms_helper_poll_enable(dev); |
ac4c16c5 EE |
1053 | mod_timer(&dev_priv->hotplug_reenable_timer, |
1054 | jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY)); | |
1055 | } | |
cd569aed EE |
1056 | |
1057 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
1058 | ||
321a1b30 EE |
1059 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
1060 | intel_connector = to_intel_connector(connector); | |
1061 | intel_encoder = intel_connector->encoder; | |
1062 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { | |
1063 | if (intel_encoder->hot_plug) | |
1064 | intel_encoder->hot_plug(intel_encoder); | |
1065 | if (intel_hpd_irq_event(dev, connector)) | |
1066 | changed = true; | |
1067 | } | |
1068 | } | |
40ee3381 KP |
1069 | mutex_unlock(&mode_config->mutex); |
1070 | ||
321a1b30 EE |
1071 | if (changed) |
1072 | drm_kms_helper_hotplug_event(dev); | |
5ca58282 JB |
1073 | } |
1074 | ||
3ca1cced VS |
1075 | static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv) |
1076 | { | |
1077 | del_timer_sync(&dev_priv->hotplug_reenable_timer); | |
1078 | } | |
1079 | ||
d0ecd7e2 | 1080 | static void ironlake_rps_change_irq_handler(struct drm_device *dev) |
f97108d1 | 1081 | { |
2d1013dd | 1082 | struct drm_i915_private *dev_priv = dev->dev_private; |
b5b72e89 | 1083 | u32 busy_up, busy_down, max_avg, min_avg; |
9270388e | 1084 | u8 new_delay; |
9270388e | 1085 | |
d0ecd7e2 | 1086 | spin_lock(&mchdev_lock); |
f97108d1 | 1087 | |
73edd18f DV |
1088 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
1089 | ||
20e4d407 | 1090 | new_delay = dev_priv->ips.cur_delay; |
9270388e | 1091 | |
7648fa99 | 1092 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
1093 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
1094 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
1095 | max_avg = I915_READ(RCBMAXAVG); |
1096 | min_avg = I915_READ(RCBMINAVG); | |
1097 | ||
1098 | /* Handle RCS change request from hw */ | |
b5b72e89 | 1099 | if (busy_up > max_avg) { |
20e4d407 DV |
1100 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
1101 | new_delay = dev_priv->ips.cur_delay - 1; | |
1102 | if (new_delay < dev_priv->ips.max_delay) | |
1103 | new_delay = dev_priv->ips.max_delay; | |
b5b72e89 | 1104 | } else if (busy_down < min_avg) { |
20e4d407 DV |
1105 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
1106 | new_delay = dev_priv->ips.cur_delay + 1; | |
1107 | if (new_delay > dev_priv->ips.min_delay) | |
1108 | new_delay = dev_priv->ips.min_delay; | |
f97108d1 JB |
1109 | } |
1110 | ||
7648fa99 | 1111 | if (ironlake_set_drps(dev, new_delay)) |
20e4d407 | 1112 | dev_priv->ips.cur_delay = new_delay; |
f97108d1 | 1113 | |
d0ecd7e2 | 1114 | spin_unlock(&mchdev_lock); |
9270388e | 1115 | |
f97108d1 JB |
1116 | return; |
1117 | } | |
1118 | ||
549f7365 CW |
1119 | static void notify_ring(struct drm_device *dev, |
1120 | struct intel_ring_buffer *ring) | |
1121 | { | |
475553de CW |
1122 | if (ring->obj == NULL) |
1123 | return; | |
1124 | ||
814e9b57 | 1125 | trace_i915_gem_request_complete(ring); |
9862e600 | 1126 | |
549f7365 | 1127 | wake_up_all(&ring->irq_queue); |
10cd45b6 | 1128 | i915_queue_hangcheck(dev); |
549f7365 CW |
1129 | } |
1130 | ||
4912d041 | 1131 | static void gen6_pm_rps_work(struct work_struct *work) |
3b8d8d91 | 1132 | { |
2d1013dd JN |
1133 | struct drm_i915_private *dev_priv = |
1134 | container_of(work, struct drm_i915_private, rps.work); | |
edbfdb45 | 1135 | u32 pm_iir; |
dd75fdc8 | 1136 | int new_delay, adj; |
4912d041 | 1137 | |
59cdb63d | 1138 | spin_lock_irq(&dev_priv->irq_lock); |
c6a828d3 DV |
1139 | pm_iir = dev_priv->rps.pm_iir; |
1140 | dev_priv->rps.pm_iir = 0; | |
0961021a BW |
1141 | if (IS_BROADWELL(dev_priv->dev)) |
1142 | bdw_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); | |
1143 | else { | |
1144 | /* Make sure not to corrupt PMIMR state used by ringbuffer */ | |
1145 | snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); | |
1146 | } | |
59cdb63d | 1147 | spin_unlock_irq(&dev_priv->irq_lock); |
3b8d8d91 | 1148 | |
60611c13 | 1149 | /* Make sure we didn't queue anything we're not going to process. */ |
a6706b45 | 1150 | WARN_ON(pm_iir & ~dev_priv->pm_rps_events); |
60611c13 | 1151 | |
a6706b45 | 1152 | if ((pm_iir & dev_priv->pm_rps_events) == 0) |
3b8d8d91 JB |
1153 | return; |
1154 | ||
4fc688ce | 1155 | mutex_lock(&dev_priv->rps.hw_lock); |
7b9e0ae6 | 1156 | |
dd75fdc8 | 1157 | adj = dev_priv->rps.last_adj; |
7425034a | 1158 | if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { |
dd75fdc8 CW |
1159 | if (adj > 0) |
1160 | adj *= 2; | |
1161 | else | |
1162 | adj = 1; | |
b39fb297 | 1163 | new_delay = dev_priv->rps.cur_freq + adj; |
7425034a VS |
1164 | |
1165 | /* | |
1166 | * For better performance, jump directly | |
1167 | * to RPe if we're below it. | |
1168 | */ | |
b39fb297 BW |
1169 | if (new_delay < dev_priv->rps.efficient_freq) |
1170 | new_delay = dev_priv->rps.efficient_freq; | |
dd75fdc8 | 1171 | } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { |
b39fb297 BW |
1172 | if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq) |
1173 | new_delay = dev_priv->rps.efficient_freq; | |
dd75fdc8 | 1174 | else |
b39fb297 | 1175 | new_delay = dev_priv->rps.min_freq_softlimit; |
dd75fdc8 CW |
1176 | adj = 0; |
1177 | } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { | |
1178 | if (adj < 0) | |
1179 | adj *= 2; | |
1180 | else | |
1181 | adj = -1; | |
b39fb297 | 1182 | new_delay = dev_priv->rps.cur_freq + adj; |
dd75fdc8 | 1183 | } else { /* unknown event */ |
b39fb297 | 1184 | new_delay = dev_priv->rps.cur_freq; |
dd75fdc8 | 1185 | } |
3b8d8d91 | 1186 | |
79249636 BW |
1187 | /* sysfs frequency interfaces may have snuck in while servicing the |
1188 | * interrupt | |
1189 | */ | |
1272e7b8 | 1190 | new_delay = clamp_t(int, new_delay, |
b39fb297 BW |
1191 | dev_priv->rps.min_freq_softlimit, |
1192 | dev_priv->rps.max_freq_softlimit); | |
27544369 | 1193 | |
b39fb297 | 1194 | dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq; |
dd75fdc8 CW |
1195 | |
1196 | if (IS_VALLEYVIEW(dev_priv->dev)) | |
1197 | valleyview_set_rps(dev_priv->dev, new_delay); | |
1198 | else | |
1199 | gen6_set_rps(dev_priv->dev, new_delay); | |
3b8d8d91 | 1200 | |
4fc688ce | 1201 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 JB |
1202 | } |
1203 | ||
e3689190 BW |
1204 | |
1205 | /** | |
1206 | * ivybridge_parity_work - Workqueue called when a parity error interrupt | |
1207 | * occurred. | |
1208 | * @work: workqueue struct | |
1209 | * | |
1210 | * Doesn't actually do anything except notify userspace. As a consequence of | |
1211 | * this event, userspace should try to remap the bad rows since statistically | |
1212 | * it is likely the same row is more likely to go bad again. | |
1213 | */ | |
1214 | static void ivybridge_parity_work(struct work_struct *work) | |
1215 | { | |
2d1013dd JN |
1216 | struct drm_i915_private *dev_priv = |
1217 | container_of(work, struct drm_i915_private, l3_parity.error_work); | |
e3689190 | 1218 | u32 error_status, row, bank, subbank; |
35a85ac6 | 1219 | char *parity_event[6]; |
e3689190 BW |
1220 | uint32_t misccpctl; |
1221 | unsigned long flags; | |
35a85ac6 | 1222 | uint8_t slice = 0; |
e3689190 BW |
1223 | |
1224 | /* We must turn off DOP level clock gating to access the L3 registers. | |
1225 | * In order to prevent a get/put style interface, acquire struct mutex | |
1226 | * any time we access those registers. | |
1227 | */ | |
1228 | mutex_lock(&dev_priv->dev->struct_mutex); | |
1229 | ||
35a85ac6 BW |
1230 | /* If we've screwed up tracking, just let the interrupt fire again */ |
1231 | if (WARN_ON(!dev_priv->l3_parity.which_slice)) | |
1232 | goto out; | |
1233 | ||
e3689190 BW |
1234 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
1235 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
1236 | POSTING_READ(GEN7_MISCCPCTL); | |
1237 | ||
35a85ac6 BW |
1238 | while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { |
1239 | u32 reg; | |
e3689190 | 1240 | |
35a85ac6 BW |
1241 | slice--; |
1242 | if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev))) | |
1243 | break; | |
e3689190 | 1244 | |
35a85ac6 | 1245 | dev_priv->l3_parity.which_slice &= ~(1<<slice); |
e3689190 | 1246 | |
35a85ac6 | 1247 | reg = GEN7_L3CDERRST1 + (slice * 0x200); |
e3689190 | 1248 | |
35a85ac6 BW |
1249 | error_status = I915_READ(reg); |
1250 | row = GEN7_PARITY_ERROR_ROW(error_status); | |
1251 | bank = GEN7_PARITY_ERROR_BANK(error_status); | |
1252 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); | |
1253 | ||
1254 | I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); | |
1255 | POSTING_READ(reg); | |
1256 | ||
1257 | parity_event[0] = I915_L3_PARITY_UEVENT "=1"; | |
1258 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); | |
1259 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); | |
1260 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); | |
1261 | parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); | |
1262 | parity_event[5] = NULL; | |
1263 | ||
5bdebb18 | 1264 | kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj, |
35a85ac6 | 1265 | KOBJ_CHANGE, parity_event); |
e3689190 | 1266 | |
35a85ac6 BW |
1267 | DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", |
1268 | slice, row, bank, subbank); | |
e3689190 | 1269 | |
35a85ac6 BW |
1270 | kfree(parity_event[4]); |
1271 | kfree(parity_event[3]); | |
1272 | kfree(parity_event[2]); | |
1273 | kfree(parity_event[1]); | |
1274 | } | |
e3689190 | 1275 | |
35a85ac6 | 1276 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
e3689190 | 1277 | |
35a85ac6 BW |
1278 | out: |
1279 | WARN_ON(dev_priv->l3_parity.which_slice); | |
1280 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1281 | ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev)); | |
1282 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1283 | ||
1284 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
e3689190 BW |
1285 | } |
1286 | ||
35a85ac6 | 1287 | static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir) |
e3689190 | 1288 | { |
2d1013dd | 1289 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3689190 | 1290 | |
040d2baa | 1291 | if (!HAS_L3_DPF(dev)) |
e3689190 BW |
1292 | return; |
1293 | ||
d0ecd7e2 | 1294 | spin_lock(&dev_priv->irq_lock); |
35a85ac6 | 1295 | ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev)); |
d0ecd7e2 | 1296 | spin_unlock(&dev_priv->irq_lock); |
e3689190 | 1297 | |
35a85ac6 BW |
1298 | iir &= GT_PARITY_ERROR(dev); |
1299 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) | |
1300 | dev_priv->l3_parity.which_slice |= 1 << 1; | |
1301 | ||
1302 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) | |
1303 | dev_priv->l3_parity.which_slice |= 1 << 0; | |
1304 | ||
a4da4fa4 | 1305 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
e3689190 BW |
1306 | } |
1307 | ||
f1af8fc1 PZ |
1308 | static void ilk_gt_irq_handler(struct drm_device *dev, |
1309 | struct drm_i915_private *dev_priv, | |
1310 | u32 gt_iir) | |
1311 | { | |
1312 | if (gt_iir & | |
1313 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
1314 | notify_ring(dev, &dev_priv->ring[RCS]); | |
1315 | if (gt_iir & ILK_BSD_USER_INTERRUPT) | |
1316 | notify_ring(dev, &dev_priv->ring[VCS]); | |
1317 | } | |
1318 | ||
e7b4c6b1 DV |
1319 | static void snb_gt_irq_handler(struct drm_device *dev, |
1320 | struct drm_i915_private *dev_priv, | |
1321 | u32 gt_iir) | |
1322 | { | |
1323 | ||
cc609d5d BW |
1324 | if (gt_iir & |
1325 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
e7b4c6b1 | 1326 | notify_ring(dev, &dev_priv->ring[RCS]); |
cc609d5d | 1327 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
e7b4c6b1 | 1328 | notify_ring(dev, &dev_priv->ring[VCS]); |
cc609d5d | 1329 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
e7b4c6b1 DV |
1330 | notify_ring(dev, &dev_priv->ring[BCS]); |
1331 | ||
cc609d5d BW |
1332 | if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | |
1333 | GT_BSD_CS_ERROR_INTERRUPT | | |
1334 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) { | |
58174462 MK |
1335 | i915_handle_error(dev, false, "GT error interrupt 0x%08x", |
1336 | gt_iir); | |
e7b4c6b1 | 1337 | } |
e3689190 | 1338 | |
35a85ac6 BW |
1339 | if (gt_iir & GT_PARITY_ERROR(dev)) |
1340 | ivybridge_parity_error_irq_handler(dev, gt_iir); | |
e7b4c6b1 DV |
1341 | } |
1342 | ||
0961021a BW |
1343 | static void gen8_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) |
1344 | { | |
1345 | if ((pm_iir & dev_priv->pm_rps_events) == 0) | |
1346 | return; | |
1347 | ||
1348 | spin_lock(&dev_priv->irq_lock); | |
1349 | dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; | |
1350 | bdw_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); | |
1351 | spin_unlock(&dev_priv->irq_lock); | |
1352 | ||
1353 | queue_work(dev_priv->wq, &dev_priv->rps.work); | |
1354 | } | |
1355 | ||
abd58f01 BW |
1356 | static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev, |
1357 | struct drm_i915_private *dev_priv, | |
1358 | u32 master_ctl) | |
1359 | { | |
1360 | u32 rcs, bcs, vcs; | |
1361 | uint32_t tmp = 0; | |
1362 | irqreturn_t ret = IRQ_NONE; | |
1363 | ||
1364 | if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { | |
1365 | tmp = I915_READ(GEN8_GT_IIR(0)); | |
1366 | if (tmp) { | |
1367 | ret = IRQ_HANDLED; | |
1368 | rcs = tmp >> GEN8_RCS_IRQ_SHIFT; | |
1369 | bcs = tmp >> GEN8_BCS_IRQ_SHIFT; | |
1370 | if (rcs & GT_RENDER_USER_INTERRUPT) | |
1371 | notify_ring(dev, &dev_priv->ring[RCS]); | |
1372 | if (bcs & GT_RENDER_USER_INTERRUPT) | |
1373 | notify_ring(dev, &dev_priv->ring[BCS]); | |
1374 | I915_WRITE(GEN8_GT_IIR(0), tmp); | |
1375 | } else | |
1376 | DRM_ERROR("The master control interrupt lied (GT0)!\n"); | |
1377 | } | |
1378 | ||
85f9b5f9 | 1379 | if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) { |
abd58f01 BW |
1380 | tmp = I915_READ(GEN8_GT_IIR(1)); |
1381 | if (tmp) { | |
1382 | ret = IRQ_HANDLED; | |
1383 | vcs = tmp >> GEN8_VCS1_IRQ_SHIFT; | |
1384 | if (vcs & GT_RENDER_USER_INTERRUPT) | |
1385 | notify_ring(dev, &dev_priv->ring[VCS]); | |
85f9b5f9 ZY |
1386 | vcs = tmp >> GEN8_VCS2_IRQ_SHIFT; |
1387 | if (vcs & GT_RENDER_USER_INTERRUPT) | |
1388 | notify_ring(dev, &dev_priv->ring[VCS2]); | |
abd58f01 BW |
1389 | I915_WRITE(GEN8_GT_IIR(1), tmp); |
1390 | } else | |
1391 | DRM_ERROR("The master control interrupt lied (GT1)!\n"); | |
1392 | } | |
1393 | ||
0961021a BW |
1394 | if (master_ctl & GEN8_GT_PM_IRQ) { |
1395 | tmp = I915_READ(GEN8_GT_IIR(2)); | |
1396 | if (tmp & dev_priv->pm_rps_events) { | |
1397 | ret = IRQ_HANDLED; | |
1398 | gen8_rps_irq_handler(dev_priv, tmp); | |
1399 | I915_WRITE(GEN8_GT_IIR(2), | |
1400 | tmp & dev_priv->pm_rps_events); | |
1401 | } else | |
1402 | DRM_ERROR("The master control interrupt lied (PM)!\n"); | |
1403 | } | |
1404 | ||
abd58f01 BW |
1405 | if (master_ctl & GEN8_GT_VECS_IRQ) { |
1406 | tmp = I915_READ(GEN8_GT_IIR(3)); | |
1407 | if (tmp) { | |
1408 | ret = IRQ_HANDLED; | |
1409 | vcs = tmp >> GEN8_VECS_IRQ_SHIFT; | |
1410 | if (vcs & GT_RENDER_USER_INTERRUPT) | |
1411 | notify_ring(dev, &dev_priv->ring[VECS]); | |
1412 | I915_WRITE(GEN8_GT_IIR(3), tmp); | |
1413 | } else | |
1414 | DRM_ERROR("The master control interrupt lied (GT3)!\n"); | |
1415 | } | |
1416 | ||
1417 | return ret; | |
1418 | } | |
1419 | ||
b543fb04 EE |
1420 | #define HPD_STORM_DETECT_PERIOD 1000 |
1421 | #define HPD_STORM_THRESHOLD 5 | |
1422 | ||
10a504de | 1423 | static inline void intel_hpd_irq_handler(struct drm_device *dev, |
22062dba DV |
1424 | u32 hotplug_trigger, |
1425 | const u32 *hpd) | |
b543fb04 | 1426 | { |
2d1013dd | 1427 | struct drm_i915_private *dev_priv = dev->dev_private; |
b543fb04 | 1428 | int i; |
10a504de | 1429 | bool storm_detected = false; |
b543fb04 | 1430 | |
91d131d2 DV |
1431 | if (!hotplug_trigger) |
1432 | return; | |
1433 | ||
cc9bd499 ID |
1434 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
1435 | hotplug_trigger); | |
1436 | ||
b5ea2d56 | 1437 | spin_lock(&dev_priv->irq_lock); |
b543fb04 | 1438 | for (i = 1; i < HPD_NUM_PINS; i++) { |
821450c6 | 1439 | |
3ff04a16 DV |
1440 | if (hpd[i] & hotplug_trigger && |
1441 | dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) { | |
1442 | /* | |
1443 | * On GMCH platforms the interrupt mask bits only | |
1444 | * prevent irq generation, not the setting of the | |
1445 | * hotplug bits itself. So only WARN about unexpected | |
1446 | * interrupts on saner platforms. | |
1447 | */ | |
1448 | WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev), | |
1449 | "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n", | |
1450 | hotplug_trigger, i, hpd[i]); | |
1451 | ||
1452 | continue; | |
1453 | } | |
b8f102e8 | 1454 | |
b543fb04 EE |
1455 | if (!(hpd[i] & hotplug_trigger) || |
1456 | dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED) | |
1457 | continue; | |
1458 | ||
bc5ead8c | 1459 | dev_priv->hpd_event_bits |= (1 << i); |
b543fb04 EE |
1460 | if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies, |
1461 | dev_priv->hpd_stats[i].hpd_last_jiffies | |
1462 | + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) { | |
1463 | dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies; | |
1464 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
b8f102e8 | 1465 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i); |
b543fb04 EE |
1466 | } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) { |
1467 | dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED; | |
142e2398 | 1468 | dev_priv->hpd_event_bits &= ~(1 << i); |
b543fb04 | 1469 | DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i); |
10a504de | 1470 | storm_detected = true; |
b543fb04 EE |
1471 | } else { |
1472 | dev_priv->hpd_stats[i].hpd_cnt++; | |
b8f102e8 EE |
1473 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i, |
1474 | dev_priv->hpd_stats[i].hpd_cnt); | |
b543fb04 EE |
1475 | } |
1476 | } | |
1477 | ||
10a504de DV |
1478 | if (storm_detected) |
1479 | dev_priv->display.hpd_irq_setup(dev); | |
b5ea2d56 | 1480 | spin_unlock(&dev_priv->irq_lock); |
5876fa0d | 1481 | |
645416f5 DV |
1482 | /* |
1483 | * Our hotplug handler can grab modeset locks (by calling down into the | |
1484 | * fb helpers). Hence it must not be run on our own dev-priv->wq work | |
1485 | * queue for otherwise the flush_work in the pageflip code will | |
1486 | * deadlock. | |
1487 | */ | |
1488 | schedule_work(&dev_priv->hotplug_work); | |
b543fb04 EE |
1489 | } |
1490 | ||
515ac2bb DV |
1491 | static void gmbus_irq_handler(struct drm_device *dev) |
1492 | { | |
2d1013dd | 1493 | struct drm_i915_private *dev_priv = dev->dev_private; |
28c70f16 | 1494 | |
28c70f16 | 1495 | wake_up_all(&dev_priv->gmbus_wait_queue); |
515ac2bb DV |
1496 | } |
1497 | ||
ce99c256 DV |
1498 | static void dp_aux_irq_handler(struct drm_device *dev) |
1499 | { | |
2d1013dd | 1500 | struct drm_i915_private *dev_priv = dev->dev_private; |
9ee32fea | 1501 | |
9ee32fea | 1502 | wake_up_all(&dev_priv->gmbus_wait_queue); |
ce99c256 DV |
1503 | } |
1504 | ||
8bf1e9f1 | 1505 | #if defined(CONFIG_DEBUG_FS) |
277de95e DV |
1506 | static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, |
1507 | uint32_t crc0, uint32_t crc1, | |
1508 | uint32_t crc2, uint32_t crc3, | |
1509 | uint32_t crc4) | |
8bf1e9f1 SH |
1510 | { |
1511 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1512 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; | |
1513 | struct intel_pipe_crc_entry *entry; | |
ac2300d4 | 1514 | int head, tail; |
b2c88f5b | 1515 | |
d538bbdf DL |
1516 | spin_lock(&pipe_crc->lock); |
1517 | ||
0c912c79 | 1518 | if (!pipe_crc->entries) { |
d538bbdf | 1519 | spin_unlock(&pipe_crc->lock); |
0c912c79 DL |
1520 | DRM_ERROR("spurious interrupt\n"); |
1521 | return; | |
1522 | } | |
1523 | ||
d538bbdf DL |
1524 | head = pipe_crc->head; |
1525 | tail = pipe_crc->tail; | |
b2c88f5b DL |
1526 | |
1527 | if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { | |
d538bbdf | 1528 | spin_unlock(&pipe_crc->lock); |
b2c88f5b DL |
1529 | DRM_ERROR("CRC buffer overflowing\n"); |
1530 | return; | |
1531 | } | |
1532 | ||
1533 | entry = &pipe_crc->entries[head]; | |
8bf1e9f1 | 1534 | |
8bc5e955 | 1535 | entry->frame = dev->driver->get_vblank_counter(dev, pipe); |
eba94eb9 DV |
1536 | entry->crc[0] = crc0; |
1537 | entry->crc[1] = crc1; | |
1538 | entry->crc[2] = crc2; | |
1539 | entry->crc[3] = crc3; | |
1540 | entry->crc[4] = crc4; | |
b2c88f5b DL |
1541 | |
1542 | head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
d538bbdf DL |
1543 | pipe_crc->head = head; |
1544 | ||
1545 | spin_unlock(&pipe_crc->lock); | |
07144428 DL |
1546 | |
1547 | wake_up_interruptible(&pipe_crc->wq); | |
8bf1e9f1 | 1548 | } |
277de95e DV |
1549 | #else |
1550 | static inline void | |
1551 | display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, | |
1552 | uint32_t crc0, uint32_t crc1, | |
1553 | uint32_t crc2, uint32_t crc3, | |
1554 | uint32_t crc4) {} | |
1555 | #endif | |
1556 | ||
eba94eb9 | 1557 | |
277de95e | 1558 | static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5a69b89f DV |
1559 | { |
1560 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1561 | ||
277de95e DV |
1562 | display_pipe_crc_irq_handler(dev, pipe, |
1563 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1564 | 0, 0, 0, 0); | |
5a69b89f DV |
1565 | } |
1566 | ||
277de95e | 1567 | static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
eba94eb9 DV |
1568 | { |
1569 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1570 | ||
277de95e DV |
1571 | display_pipe_crc_irq_handler(dev, pipe, |
1572 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1573 | I915_READ(PIPE_CRC_RES_2_IVB(pipe)), | |
1574 | I915_READ(PIPE_CRC_RES_3_IVB(pipe)), | |
1575 | I915_READ(PIPE_CRC_RES_4_IVB(pipe)), | |
1576 | I915_READ(PIPE_CRC_RES_5_IVB(pipe))); | |
eba94eb9 | 1577 | } |
5b3a856b | 1578 | |
277de95e | 1579 | static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5b3a856b DV |
1580 | { |
1581 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0b5c5ed0 DV |
1582 | uint32_t res1, res2; |
1583 | ||
1584 | if (INTEL_INFO(dev)->gen >= 3) | |
1585 | res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); | |
1586 | else | |
1587 | res1 = 0; | |
1588 | ||
1589 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
1590 | res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); | |
1591 | else | |
1592 | res2 = 0; | |
5b3a856b | 1593 | |
277de95e DV |
1594 | display_pipe_crc_irq_handler(dev, pipe, |
1595 | I915_READ(PIPE_CRC_RES_RED(pipe)), | |
1596 | I915_READ(PIPE_CRC_RES_GREEN(pipe)), | |
1597 | I915_READ(PIPE_CRC_RES_BLUE(pipe)), | |
1598 | res1, res2); | |
5b3a856b | 1599 | } |
8bf1e9f1 | 1600 | |
1403c0d4 PZ |
1601 | /* The RPS events need forcewake, so we add them to a work queue and mask their |
1602 | * IMR bits until the work is done. Other interrupts can be processed without | |
1603 | * the work queue. */ | |
1604 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) | |
baf02a1f | 1605 | { |
a6706b45 | 1606 | if (pm_iir & dev_priv->pm_rps_events) { |
59cdb63d | 1607 | spin_lock(&dev_priv->irq_lock); |
a6706b45 D |
1608 | dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; |
1609 | snb_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); | |
59cdb63d | 1610 | spin_unlock(&dev_priv->irq_lock); |
2adbee62 DV |
1611 | |
1612 | queue_work(dev_priv->wq, &dev_priv->rps.work); | |
baf02a1f | 1613 | } |
baf02a1f | 1614 | |
1403c0d4 PZ |
1615 | if (HAS_VEBOX(dev_priv->dev)) { |
1616 | if (pm_iir & PM_VEBOX_USER_INTERRUPT) | |
1617 | notify_ring(dev_priv->dev, &dev_priv->ring[VECS]); | |
12638c57 | 1618 | |
1403c0d4 | 1619 | if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) { |
58174462 MK |
1620 | i915_handle_error(dev_priv->dev, false, |
1621 | "VEBOX CS error interrupt 0x%08x", | |
1622 | pm_iir); | |
1403c0d4 | 1623 | } |
12638c57 | 1624 | } |
baf02a1f BW |
1625 | } |
1626 | ||
8d7849db VS |
1627 | static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe) |
1628 | { | |
1629 | struct intel_crtc *crtc; | |
1630 | ||
1631 | if (!drm_handle_vblank(dev, pipe)) | |
1632 | return false; | |
1633 | ||
1634 | crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
1635 | wake_up(&crtc->vbl_wait); | |
1636 | ||
1637 | return true; | |
1638 | } | |
1639 | ||
c1874ed7 ID |
1640 | static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir) |
1641 | { | |
1642 | struct drm_i915_private *dev_priv = dev->dev_private; | |
91d181dd | 1643 | u32 pipe_stats[I915_MAX_PIPES] = { }; |
c1874ed7 ID |
1644 | int pipe; |
1645 | ||
58ead0d7 | 1646 | spin_lock(&dev_priv->irq_lock); |
c1874ed7 | 1647 | for_each_pipe(pipe) { |
91d181dd | 1648 | int reg; |
bbb5eebf | 1649 | u32 mask, iir_bit = 0; |
91d181dd | 1650 | |
bbb5eebf DV |
1651 | /* |
1652 | * PIPESTAT bits get signalled even when the interrupt is | |
1653 | * disabled with the mask bits, and some of the status bits do | |
1654 | * not generate interrupts at all (like the underrun bit). Hence | |
1655 | * we need to be careful that we only handle what we want to | |
1656 | * handle. | |
1657 | */ | |
1658 | mask = 0; | |
1659 | if (__cpu_fifo_underrun_reporting_enabled(dev, pipe)) | |
1660 | mask |= PIPE_FIFO_UNDERRUN_STATUS; | |
1661 | ||
1662 | switch (pipe) { | |
1663 | case PIPE_A: | |
1664 | iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; | |
1665 | break; | |
1666 | case PIPE_B: | |
1667 | iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
1668 | break; | |
1669 | } | |
1670 | if (iir & iir_bit) | |
1671 | mask |= dev_priv->pipestat_irq_mask[pipe]; | |
1672 | ||
1673 | if (!mask) | |
91d181dd ID |
1674 | continue; |
1675 | ||
1676 | reg = PIPESTAT(pipe); | |
bbb5eebf DV |
1677 | mask |= PIPESTAT_INT_ENABLE_MASK; |
1678 | pipe_stats[pipe] = I915_READ(reg) & mask; | |
c1874ed7 ID |
1679 | |
1680 | /* | |
1681 | * Clear the PIPE*STAT regs before the IIR | |
1682 | */ | |
91d181dd ID |
1683 | if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS | |
1684 | PIPESTAT_INT_STATUS_MASK)) | |
c1874ed7 ID |
1685 | I915_WRITE(reg, pipe_stats[pipe]); |
1686 | } | |
58ead0d7 | 1687 | spin_unlock(&dev_priv->irq_lock); |
c1874ed7 ID |
1688 | |
1689 | for_each_pipe(pipe) { | |
1690 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) | |
8d7849db | 1691 | intel_pipe_handle_vblank(dev, pipe); |
c1874ed7 | 1692 | |
579a9b0e | 1693 | if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) { |
c1874ed7 ID |
1694 | intel_prepare_page_flip(dev, pipe); |
1695 | intel_finish_page_flip(dev, pipe); | |
1696 | } | |
1697 | ||
1698 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
1699 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
1700 | ||
1701 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && | |
1702 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
1703 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); | |
1704 | } | |
1705 | ||
1706 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) | |
1707 | gmbus_irq_handler(dev); | |
1708 | } | |
1709 | ||
16c6c56b VS |
1710 | static void i9xx_hpd_irq_handler(struct drm_device *dev) |
1711 | { | |
1712 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1713 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
1714 | ||
1715 | if (IS_G4X(dev)) { | |
1716 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; | |
1717 | ||
1718 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_g4x); | |
1719 | } else { | |
1720 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; | |
1721 | ||
1722 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); | |
1723 | } | |
1724 | ||
1725 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && | |
1726 | hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) | |
1727 | dp_aux_irq_handler(dev); | |
1728 | ||
1729 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
1730 | /* | |
1731 | * Make sure hotplug status is cleared before we clear IIR, or else we | |
1732 | * may miss hotplug events. | |
1733 | */ | |
1734 | POSTING_READ(PORT_HOTPLUG_STAT); | |
1735 | } | |
1736 | ||
ff1f525e | 1737 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
7e231dbe | 1738 | { |
45a83f84 | 1739 | struct drm_device *dev = arg; |
2d1013dd | 1740 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
1741 | u32 iir, gt_iir, pm_iir; |
1742 | irqreturn_t ret = IRQ_NONE; | |
7e231dbe | 1743 | |
7e231dbe JB |
1744 | while (true) { |
1745 | iir = I915_READ(VLV_IIR); | |
1746 | gt_iir = I915_READ(GTIIR); | |
1747 | pm_iir = I915_READ(GEN6_PMIIR); | |
1748 | ||
1749 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) | |
1750 | goto out; | |
1751 | ||
1752 | ret = IRQ_HANDLED; | |
1753 | ||
e7b4c6b1 | 1754 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
7e231dbe | 1755 | |
c1874ed7 | 1756 | valleyview_pipestat_irq_handler(dev, iir); |
31acc7f5 | 1757 | |
7e231dbe | 1758 | /* Consume port. Then clear IIR or we'll miss events */ |
16c6c56b VS |
1759 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
1760 | i9xx_hpd_irq_handler(dev); | |
7e231dbe | 1761 | |
60611c13 | 1762 | if (pm_iir) |
d0ecd7e2 | 1763 | gen6_rps_irq_handler(dev_priv, pm_iir); |
7e231dbe JB |
1764 | |
1765 | I915_WRITE(GTIIR, gt_iir); | |
1766 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
1767 | I915_WRITE(VLV_IIR, iir); | |
1768 | } | |
1769 | ||
1770 | out: | |
1771 | return ret; | |
1772 | } | |
1773 | ||
43f328d7 VS |
1774 | static irqreturn_t cherryview_irq_handler(int irq, void *arg) |
1775 | { | |
45a83f84 | 1776 | struct drm_device *dev = arg; |
43f328d7 VS |
1777 | struct drm_i915_private *dev_priv = dev->dev_private; |
1778 | u32 master_ctl, iir; | |
1779 | irqreturn_t ret = IRQ_NONE; | |
1780 | unsigned int pipes = 0; | |
1781 | ||
1782 | master_ctl = I915_READ(GEN8_MASTER_IRQ); | |
1783 | ||
1784 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
1785 | ||
1786 | ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl); | |
1787 | ||
1788 | iir = I915_READ(VLV_IIR); | |
1789 | ||
1790 | if (iir & (I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT)) | |
1791 | pipes |= 1 << 0; | |
1792 | if (iir & (I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)) | |
1793 | pipes |= 1 << 1; | |
1794 | if (iir & (I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT | I915_DISPLAY_PIPE_C_EVENT_INTERRUPT)) | |
1795 | pipes |= 1 << 2; | |
1796 | ||
1797 | if (pipes) { | |
1798 | u32 pipe_stats[I915_MAX_PIPES] = {}; | |
1799 | unsigned long irqflags; | |
1800 | int pipe; | |
1801 | ||
1802 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
1803 | for_each_pipe(pipe) { | |
1804 | unsigned int reg; | |
1805 | ||
1806 | if (!(pipes & (1 << pipe))) | |
1807 | continue; | |
1808 | ||
1809 | reg = PIPESTAT(pipe); | |
1810 | pipe_stats[pipe] = I915_READ(reg); | |
1811 | ||
1812 | /* | |
1813 | * Clear the PIPE*STAT regs before the IIR | |
1814 | */ | |
1815 | if (pipe_stats[pipe] & 0x8000ffff) { | |
1816 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | |
1817 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | |
1818 | pipe_name(pipe)); | |
1819 | I915_WRITE(reg, pipe_stats[pipe]); | |
1820 | } | |
1821 | } | |
1822 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
1823 | ||
1824 | for_each_pipe(pipe) { | |
1825 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) | |
1826 | drm_handle_vblank(dev, pipe); | |
1827 | ||
1828 | if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) { | |
1829 | intel_prepare_page_flip(dev, pipe); | |
1830 | intel_finish_page_flip(dev, pipe); | |
1831 | } | |
1832 | } | |
1833 | ||
1834 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) | |
1835 | gmbus_irq_handler(dev); | |
1836 | ||
1837 | ret = IRQ_HANDLED; | |
1838 | } | |
1839 | ||
1840 | /* Consume port. Then clear IIR or we'll miss events */ | |
1841 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { | |
1842 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
1843 | ||
1844 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
1845 | ||
1846 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", | |
1847 | hotplug_status); | |
1848 | if (hotplug_status & HOTPLUG_INT_STATUS_I915) | |
1849 | queue_work(dev_priv->wq, | |
1850 | &dev_priv->hotplug_work); | |
1851 | ||
1852 | ret = IRQ_HANDLED; | |
1853 | } | |
1854 | ||
1855 | I915_WRITE(VLV_IIR, iir); | |
1856 | ||
1857 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); | |
1858 | POSTING_READ(GEN8_MASTER_IRQ); | |
1859 | ||
1860 | return ret; | |
1861 | } | |
1862 | ||
23e81d69 | 1863 | static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) |
776ad806 | 1864 | { |
2d1013dd | 1865 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 1866 | int pipe; |
b543fb04 | 1867 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; |
776ad806 | 1868 | |
91d131d2 DV |
1869 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx); |
1870 | ||
cfc33bf7 VS |
1871 | if (pch_iir & SDE_AUDIO_POWER_MASK) { |
1872 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> | |
1873 | SDE_AUDIO_POWER_SHIFT); | |
776ad806 | 1874 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
cfc33bf7 VS |
1875 | port_name(port)); |
1876 | } | |
776ad806 | 1877 | |
ce99c256 DV |
1878 | if (pch_iir & SDE_AUX_MASK) |
1879 | dp_aux_irq_handler(dev); | |
1880 | ||
776ad806 | 1881 | if (pch_iir & SDE_GMBUS) |
515ac2bb | 1882 | gmbus_irq_handler(dev); |
776ad806 JB |
1883 | |
1884 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
1885 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
1886 | ||
1887 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
1888 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
1889 | ||
1890 | if (pch_iir & SDE_POISON) | |
1891 | DRM_ERROR("PCH poison interrupt\n"); | |
1892 | ||
9db4a9c7 JB |
1893 | if (pch_iir & SDE_FDI_MASK) |
1894 | for_each_pipe(pipe) | |
1895 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", | |
1896 | pipe_name(pipe), | |
1897 | I915_READ(FDI_RX_IIR(pipe))); | |
776ad806 JB |
1898 | |
1899 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
1900 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
1901 | ||
1902 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
1903 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
1904 | ||
776ad806 | 1905 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
8664281b PZ |
1906 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, |
1907 | false)) | |
fc2c807b | 1908 | DRM_ERROR("PCH transcoder A FIFO underrun\n"); |
8664281b PZ |
1909 | |
1910 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
1911 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, | |
1912 | false)) | |
fc2c807b | 1913 | DRM_ERROR("PCH transcoder B FIFO underrun\n"); |
8664281b PZ |
1914 | } |
1915 | ||
1916 | static void ivb_err_int_handler(struct drm_device *dev) | |
1917 | { | |
1918 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1919 | u32 err_int = I915_READ(GEN7_ERR_INT); | |
5a69b89f | 1920 | enum pipe pipe; |
8664281b | 1921 | |
de032bf4 PZ |
1922 | if (err_int & ERR_INT_POISON) |
1923 | DRM_ERROR("Poison interrupt\n"); | |
1924 | ||
5a69b89f DV |
1925 | for_each_pipe(pipe) { |
1926 | if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) { | |
1927 | if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, | |
1928 | false)) | |
fc2c807b VS |
1929 | DRM_ERROR("Pipe %c FIFO underrun\n", |
1930 | pipe_name(pipe)); | |
5a69b89f | 1931 | } |
8bf1e9f1 | 1932 | |
5a69b89f DV |
1933 | if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { |
1934 | if (IS_IVYBRIDGE(dev)) | |
277de95e | 1935 | ivb_pipe_crc_irq_handler(dev, pipe); |
5a69b89f | 1936 | else |
277de95e | 1937 | hsw_pipe_crc_irq_handler(dev, pipe); |
5a69b89f DV |
1938 | } |
1939 | } | |
8bf1e9f1 | 1940 | |
8664281b PZ |
1941 | I915_WRITE(GEN7_ERR_INT, err_int); |
1942 | } | |
1943 | ||
1944 | static void cpt_serr_int_handler(struct drm_device *dev) | |
1945 | { | |
1946 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1947 | u32 serr_int = I915_READ(SERR_INT); | |
1948 | ||
de032bf4 PZ |
1949 | if (serr_int & SERR_INT_POISON) |
1950 | DRM_ERROR("PCH poison interrupt\n"); | |
1951 | ||
8664281b PZ |
1952 | if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) |
1953 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, | |
1954 | false)) | |
fc2c807b | 1955 | DRM_ERROR("PCH transcoder A FIFO underrun\n"); |
8664281b PZ |
1956 | |
1957 | if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) | |
1958 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, | |
1959 | false)) | |
fc2c807b | 1960 | DRM_ERROR("PCH transcoder B FIFO underrun\n"); |
8664281b PZ |
1961 | |
1962 | if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) | |
1963 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C, | |
1964 | false)) | |
fc2c807b | 1965 | DRM_ERROR("PCH transcoder C FIFO underrun\n"); |
8664281b PZ |
1966 | |
1967 | I915_WRITE(SERR_INT, serr_int); | |
776ad806 JB |
1968 | } |
1969 | ||
23e81d69 AJ |
1970 | static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) |
1971 | { | |
2d1013dd | 1972 | struct drm_i915_private *dev_priv = dev->dev_private; |
23e81d69 | 1973 | int pipe; |
b543fb04 | 1974 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; |
23e81d69 | 1975 | |
91d131d2 DV |
1976 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt); |
1977 | ||
cfc33bf7 VS |
1978 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { |
1979 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> | |
1980 | SDE_AUDIO_POWER_SHIFT_CPT); | |
1981 | DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", | |
1982 | port_name(port)); | |
1983 | } | |
23e81d69 AJ |
1984 | |
1985 | if (pch_iir & SDE_AUX_MASK_CPT) | |
ce99c256 | 1986 | dp_aux_irq_handler(dev); |
23e81d69 AJ |
1987 | |
1988 | if (pch_iir & SDE_GMBUS_CPT) | |
515ac2bb | 1989 | gmbus_irq_handler(dev); |
23e81d69 AJ |
1990 | |
1991 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) | |
1992 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); | |
1993 | ||
1994 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) | |
1995 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); | |
1996 | ||
1997 | if (pch_iir & SDE_FDI_MASK_CPT) | |
1998 | for_each_pipe(pipe) | |
1999 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", | |
2000 | pipe_name(pipe), | |
2001 | I915_READ(FDI_RX_IIR(pipe))); | |
8664281b PZ |
2002 | |
2003 | if (pch_iir & SDE_ERROR_CPT) | |
2004 | cpt_serr_int_handler(dev); | |
23e81d69 AJ |
2005 | } |
2006 | ||
c008bc6e PZ |
2007 | static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) |
2008 | { | |
2009 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40da17c2 | 2010 | enum pipe pipe; |
c008bc6e PZ |
2011 | |
2012 | if (de_iir & DE_AUX_CHANNEL_A) | |
2013 | dp_aux_irq_handler(dev); | |
2014 | ||
2015 | if (de_iir & DE_GSE) | |
2016 | intel_opregion_asle_intr(dev); | |
2017 | ||
c008bc6e PZ |
2018 | if (de_iir & DE_POISON) |
2019 | DRM_ERROR("Poison interrupt\n"); | |
2020 | ||
40da17c2 DV |
2021 | for_each_pipe(pipe) { |
2022 | if (de_iir & DE_PIPE_VBLANK(pipe)) | |
8d7849db | 2023 | intel_pipe_handle_vblank(dev, pipe); |
5b3a856b | 2024 | |
40da17c2 DV |
2025 | if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) |
2026 | if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
fc2c807b VS |
2027 | DRM_ERROR("Pipe %c FIFO underrun\n", |
2028 | pipe_name(pipe)); | |
5b3a856b | 2029 | |
40da17c2 DV |
2030 | if (de_iir & DE_PIPE_CRC_DONE(pipe)) |
2031 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
c008bc6e | 2032 | |
40da17c2 DV |
2033 | /* plane/pipes map 1:1 on ilk+ */ |
2034 | if (de_iir & DE_PLANE_FLIP_DONE(pipe)) { | |
2035 | intel_prepare_page_flip(dev, pipe); | |
2036 | intel_finish_page_flip_plane(dev, pipe); | |
2037 | } | |
c008bc6e PZ |
2038 | } |
2039 | ||
2040 | /* check event from PCH */ | |
2041 | if (de_iir & DE_PCH_EVENT) { | |
2042 | u32 pch_iir = I915_READ(SDEIIR); | |
2043 | ||
2044 | if (HAS_PCH_CPT(dev)) | |
2045 | cpt_irq_handler(dev, pch_iir); | |
2046 | else | |
2047 | ibx_irq_handler(dev, pch_iir); | |
2048 | ||
2049 | /* should clear PCH hotplug event before clear CPU irq */ | |
2050 | I915_WRITE(SDEIIR, pch_iir); | |
2051 | } | |
2052 | ||
2053 | if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) | |
2054 | ironlake_rps_change_irq_handler(dev); | |
2055 | } | |
2056 | ||
9719fb98 PZ |
2057 | static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir) |
2058 | { | |
2059 | struct drm_i915_private *dev_priv = dev->dev_private; | |
07d27e20 | 2060 | enum pipe pipe; |
9719fb98 PZ |
2061 | |
2062 | if (de_iir & DE_ERR_INT_IVB) | |
2063 | ivb_err_int_handler(dev); | |
2064 | ||
2065 | if (de_iir & DE_AUX_CHANNEL_A_IVB) | |
2066 | dp_aux_irq_handler(dev); | |
2067 | ||
2068 | if (de_iir & DE_GSE_IVB) | |
2069 | intel_opregion_asle_intr(dev); | |
2070 | ||
07d27e20 DL |
2071 | for_each_pipe(pipe) { |
2072 | if (de_iir & (DE_PIPE_VBLANK_IVB(pipe))) | |
8d7849db | 2073 | intel_pipe_handle_vblank(dev, pipe); |
40da17c2 DV |
2074 | |
2075 | /* plane/pipes map 1:1 on ilk+ */ | |
07d27e20 DL |
2076 | if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) { |
2077 | intel_prepare_page_flip(dev, pipe); | |
2078 | intel_finish_page_flip_plane(dev, pipe); | |
9719fb98 PZ |
2079 | } |
2080 | } | |
2081 | ||
2082 | /* check event from PCH */ | |
2083 | if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) { | |
2084 | u32 pch_iir = I915_READ(SDEIIR); | |
2085 | ||
2086 | cpt_irq_handler(dev, pch_iir); | |
2087 | ||
2088 | /* clear PCH hotplug event before clear CPU irq */ | |
2089 | I915_WRITE(SDEIIR, pch_iir); | |
2090 | } | |
2091 | } | |
2092 | ||
f1af8fc1 | 2093 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
b1f14ad0 | 2094 | { |
45a83f84 | 2095 | struct drm_device *dev = arg; |
2d1013dd | 2096 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1af8fc1 | 2097 | u32 de_iir, gt_iir, de_ier, sde_ier = 0; |
0e43406b | 2098 | irqreturn_t ret = IRQ_NONE; |
b1f14ad0 | 2099 | |
8664281b PZ |
2100 | /* We get interrupts on unclaimed registers, so check for this before we |
2101 | * do any I915_{READ,WRITE}. */ | |
907b28c5 | 2102 | intel_uncore_check_errors(dev); |
8664281b | 2103 | |
b1f14ad0 JB |
2104 | /* disable master interrupt before clearing iir */ |
2105 | de_ier = I915_READ(DEIER); | |
2106 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
23a78516 | 2107 | POSTING_READ(DEIER); |
b1f14ad0 | 2108 | |
44498aea PZ |
2109 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
2110 | * interrupts will will be stored on its back queue, and then we'll be | |
2111 | * able to process them after we restore SDEIER (as soon as we restore | |
2112 | * it, we'll get an interrupt if SDEIIR still has something to process | |
2113 | * due to its back queue). */ | |
ab5c608b BW |
2114 | if (!HAS_PCH_NOP(dev)) { |
2115 | sde_ier = I915_READ(SDEIER); | |
2116 | I915_WRITE(SDEIER, 0); | |
2117 | POSTING_READ(SDEIER); | |
2118 | } | |
44498aea | 2119 | |
b1f14ad0 | 2120 | gt_iir = I915_READ(GTIIR); |
0e43406b | 2121 | if (gt_iir) { |
d8fc8a47 | 2122 | if (INTEL_INFO(dev)->gen >= 6) |
f1af8fc1 | 2123 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
d8fc8a47 PZ |
2124 | else |
2125 | ilk_gt_irq_handler(dev, dev_priv, gt_iir); | |
0e43406b CW |
2126 | I915_WRITE(GTIIR, gt_iir); |
2127 | ret = IRQ_HANDLED; | |
b1f14ad0 JB |
2128 | } |
2129 | ||
0e43406b CW |
2130 | de_iir = I915_READ(DEIIR); |
2131 | if (de_iir) { | |
f1af8fc1 PZ |
2132 | if (INTEL_INFO(dev)->gen >= 7) |
2133 | ivb_display_irq_handler(dev, de_iir); | |
2134 | else | |
2135 | ilk_display_irq_handler(dev, de_iir); | |
0e43406b CW |
2136 | I915_WRITE(DEIIR, de_iir); |
2137 | ret = IRQ_HANDLED; | |
b1f14ad0 JB |
2138 | } |
2139 | ||
f1af8fc1 PZ |
2140 | if (INTEL_INFO(dev)->gen >= 6) { |
2141 | u32 pm_iir = I915_READ(GEN6_PMIIR); | |
2142 | if (pm_iir) { | |
1403c0d4 | 2143 | gen6_rps_irq_handler(dev_priv, pm_iir); |
f1af8fc1 PZ |
2144 | I915_WRITE(GEN6_PMIIR, pm_iir); |
2145 | ret = IRQ_HANDLED; | |
2146 | } | |
0e43406b | 2147 | } |
b1f14ad0 | 2148 | |
b1f14ad0 JB |
2149 | I915_WRITE(DEIER, de_ier); |
2150 | POSTING_READ(DEIER); | |
ab5c608b BW |
2151 | if (!HAS_PCH_NOP(dev)) { |
2152 | I915_WRITE(SDEIER, sde_ier); | |
2153 | POSTING_READ(SDEIER); | |
2154 | } | |
b1f14ad0 JB |
2155 | |
2156 | return ret; | |
2157 | } | |
2158 | ||
abd58f01 BW |
2159 | static irqreturn_t gen8_irq_handler(int irq, void *arg) |
2160 | { | |
2161 | struct drm_device *dev = arg; | |
2162 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2163 | u32 master_ctl; | |
2164 | irqreturn_t ret = IRQ_NONE; | |
2165 | uint32_t tmp = 0; | |
c42664cc | 2166 | enum pipe pipe; |
abd58f01 | 2167 | |
abd58f01 BW |
2168 | master_ctl = I915_READ(GEN8_MASTER_IRQ); |
2169 | master_ctl &= ~GEN8_MASTER_IRQ_CONTROL; | |
2170 | if (!master_ctl) | |
2171 | return IRQ_NONE; | |
2172 | ||
2173 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
2174 | POSTING_READ(GEN8_MASTER_IRQ); | |
2175 | ||
2176 | ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl); | |
2177 | ||
2178 | if (master_ctl & GEN8_DE_MISC_IRQ) { | |
2179 | tmp = I915_READ(GEN8_DE_MISC_IIR); | |
2180 | if (tmp & GEN8_DE_MISC_GSE) | |
2181 | intel_opregion_asle_intr(dev); | |
2182 | else if (tmp) | |
2183 | DRM_ERROR("Unexpected DE Misc interrupt\n"); | |
2184 | else | |
2185 | DRM_ERROR("The master control interrupt lied (DE MISC)!\n"); | |
2186 | ||
2187 | if (tmp) { | |
2188 | I915_WRITE(GEN8_DE_MISC_IIR, tmp); | |
2189 | ret = IRQ_HANDLED; | |
2190 | } | |
2191 | } | |
2192 | ||
6d766f02 DV |
2193 | if (master_ctl & GEN8_DE_PORT_IRQ) { |
2194 | tmp = I915_READ(GEN8_DE_PORT_IIR); | |
2195 | if (tmp & GEN8_AUX_CHANNEL_A) | |
2196 | dp_aux_irq_handler(dev); | |
2197 | else if (tmp) | |
2198 | DRM_ERROR("Unexpected DE Port interrupt\n"); | |
2199 | else | |
2200 | DRM_ERROR("The master control interrupt lied (DE PORT)!\n"); | |
2201 | ||
2202 | if (tmp) { | |
2203 | I915_WRITE(GEN8_DE_PORT_IIR, tmp); | |
2204 | ret = IRQ_HANDLED; | |
2205 | } | |
2206 | } | |
2207 | ||
c42664cc DV |
2208 | for_each_pipe(pipe) { |
2209 | uint32_t pipe_iir; | |
abd58f01 | 2210 | |
c42664cc DV |
2211 | if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) |
2212 | continue; | |
abd58f01 | 2213 | |
c42664cc DV |
2214 | pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); |
2215 | if (pipe_iir & GEN8_PIPE_VBLANK) | |
8d7849db | 2216 | intel_pipe_handle_vblank(dev, pipe); |
abd58f01 | 2217 | |
d0e1f1cb | 2218 | if (pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE) { |
c42664cc DV |
2219 | intel_prepare_page_flip(dev, pipe); |
2220 | intel_finish_page_flip_plane(dev, pipe); | |
abd58f01 | 2221 | } |
c42664cc | 2222 | |
0fbe7870 DV |
2223 | if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE) |
2224 | hsw_pipe_crc_irq_handler(dev, pipe); | |
2225 | ||
38d83c96 DV |
2226 | if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) { |
2227 | if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, | |
2228 | false)) | |
fc2c807b VS |
2229 | DRM_ERROR("Pipe %c FIFO underrun\n", |
2230 | pipe_name(pipe)); | |
38d83c96 DV |
2231 | } |
2232 | ||
30100f2b DV |
2233 | if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) { |
2234 | DRM_ERROR("Fault errors on pipe %c\n: 0x%08x", | |
2235 | pipe_name(pipe), | |
2236 | pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS); | |
2237 | } | |
c42664cc DV |
2238 | |
2239 | if (pipe_iir) { | |
2240 | ret = IRQ_HANDLED; | |
2241 | I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir); | |
2242 | } else | |
abd58f01 BW |
2243 | DRM_ERROR("The master control interrupt lied (DE PIPE)!\n"); |
2244 | } | |
2245 | ||
92d03a80 DV |
2246 | if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) { |
2247 | /* | |
2248 | * FIXME(BDW): Assume for now that the new interrupt handling | |
2249 | * scheme also closed the SDE interrupt handling race we've seen | |
2250 | * on older pch-split platforms. But this needs testing. | |
2251 | */ | |
2252 | u32 pch_iir = I915_READ(SDEIIR); | |
2253 | ||
2254 | cpt_irq_handler(dev, pch_iir); | |
2255 | ||
2256 | if (pch_iir) { | |
2257 | I915_WRITE(SDEIIR, pch_iir); | |
2258 | ret = IRQ_HANDLED; | |
2259 | } | |
2260 | } | |
2261 | ||
abd58f01 BW |
2262 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
2263 | POSTING_READ(GEN8_MASTER_IRQ); | |
2264 | ||
2265 | return ret; | |
2266 | } | |
2267 | ||
17e1df07 DV |
2268 | static void i915_error_wake_up(struct drm_i915_private *dev_priv, |
2269 | bool reset_completed) | |
2270 | { | |
2271 | struct intel_ring_buffer *ring; | |
2272 | int i; | |
2273 | ||
2274 | /* | |
2275 | * Notify all waiters for GPU completion events that reset state has | |
2276 | * been changed, and that they need to restart their wait after | |
2277 | * checking for potential errors (and bail out to drop locks if there is | |
2278 | * a gpu reset pending so that i915_error_work_func can acquire them). | |
2279 | */ | |
2280 | ||
2281 | /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */ | |
2282 | for_each_ring(ring, dev_priv, i) | |
2283 | wake_up_all(&ring->irq_queue); | |
2284 | ||
2285 | /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */ | |
2286 | wake_up_all(&dev_priv->pending_flip_queue); | |
2287 | ||
2288 | /* | |
2289 | * Signal tasks blocked in i915_gem_wait_for_error that the pending | |
2290 | * reset state is cleared. | |
2291 | */ | |
2292 | if (reset_completed) | |
2293 | wake_up_all(&dev_priv->gpu_error.reset_queue); | |
2294 | } | |
2295 | ||
8a905236 JB |
2296 | /** |
2297 | * i915_error_work_func - do process context error handling work | |
2298 | * @work: work struct | |
2299 | * | |
2300 | * Fire an error uevent so userspace can see that a hang or error | |
2301 | * was detected. | |
2302 | */ | |
2303 | static void i915_error_work_func(struct work_struct *work) | |
2304 | { | |
1f83fee0 DV |
2305 | struct i915_gpu_error *error = container_of(work, struct i915_gpu_error, |
2306 | work); | |
2d1013dd JN |
2307 | struct drm_i915_private *dev_priv = |
2308 | container_of(error, struct drm_i915_private, gpu_error); | |
8a905236 | 2309 | struct drm_device *dev = dev_priv->dev; |
cce723ed BW |
2310 | char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; |
2311 | char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; | |
2312 | char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; | |
17e1df07 | 2313 | int ret; |
8a905236 | 2314 | |
5bdebb18 | 2315 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event); |
f316a42c | 2316 | |
7db0ba24 DV |
2317 | /* |
2318 | * Note that there's only one work item which does gpu resets, so we | |
2319 | * need not worry about concurrent gpu resets potentially incrementing | |
2320 | * error->reset_counter twice. We only need to take care of another | |
2321 | * racing irq/hangcheck declaring the gpu dead for a second time. A | |
2322 | * quick check for that is good enough: schedule_work ensures the | |
2323 | * correct ordering between hang detection and this work item, and since | |
2324 | * the reset in-progress bit is only ever set by code outside of this | |
2325 | * work we don't need to worry about any other races. | |
2326 | */ | |
2327 | if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) { | |
f803aa55 | 2328 | DRM_DEBUG_DRIVER("resetting chip\n"); |
5bdebb18 | 2329 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, |
7db0ba24 | 2330 | reset_event); |
1f83fee0 | 2331 | |
f454c694 ID |
2332 | /* |
2333 | * In most cases it's guaranteed that we get here with an RPM | |
2334 | * reference held, for example because there is a pending GPU | |
2335 | * request that won't finish until the reset is done. This | |
2336 | * isn't the case at least when we get here by doing a | |
2337 | * simulated reset via debugs, so get an RPM reference. | |
2338 | */ | |
2339 | intel_runtime_pm_get(dev_priv); | |
17e1df07 DV |
2340 | /* |
2341 | * All state reset _must_ be completed before we update the | |
2342 | * reset counter, for otherwise waiters might miss the reset | |
2343 | * pending state and not properly drop locks, resulting in | |
2344 | * deadlocks with the reset work. | |
2345 | */ | |
f69061be DV |
2346 | ret = i915_reset(dev); |
2347 | ||
17e1df07 DV |
2348 | intel_display_handle_reset(dev); |
2349 | ||
f454c694 ID |
2350 | intel_runtime_pm_put(dev_priv); |
2351 | ||
f69061be DV |
2352 | if (ret == 0) { |
2353 | /* | |
2354 | * After all the gem state is reset, increment the reset | |
2355 | * counter and wake up everyone waiting for the reset to | |
2356 | * complete. | |
2357 | * | |
2358 | * Since unlock operations are a one-sided barrier only, | |
2359 | * we need to insert a barrier here to order any seqno | |
2360 | * updates before | |
2361 | * the counter increment. | |
2362 | */ | |
2363 | smp_mb__before_atomic_inc(); | |
2364 | atomic_inc(&dev_priv->gpu_error.reset_counter); | |
2365 | ||
5bdebb18 | 2366 | kobject_uevent_env(&dev->primary->kdev->kobj, |
f69061be | 2367 | KOBJ_CHANGE, reset_done_event); |
1f83fee0 | 2368 | } else { |
2ac0f450 | 2369 | atomic_set_mask(I915_WEDGED, &error->reset_counter); |
f316a42c | 2370 | } |
1f83fee0 | 2371 | |
17e1df07 DV |
2372 | /* |
2373 | * Note: The wake_up also serves as a memory barrier so that | |
2374 | * waiters see the update value of the reset counter atomic_t. | |
2375 | */ | |
2376 | i915_error_wake_up(dev_priv, true); | |
f316a42c | 2377 | } |
8a905236 JB |
2378 | } |
2379 | ||
35aed2e6 | 2380 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
2381 | { |
2382 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bd9854f9 | 2383 | uint32_t instdone[I915_NUM_INSTDONE_REG]; |
8a905236 | 2384 | u32 eir = I915_READ(EIR); |
050ee91f | 2385 | int pipe, i; |
8a905236 | 2386 | |
35aed2e6 CW |
2387 | if (!eir) |
2388 | return; | |
8a905236 | 2389 | |
a70491cc | 2390 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
8a905236 | 2391 | |
bd9854f9 BW |
2392 | i915_get_extra_instdone(dev, instdone); |
2393 | ||
8a905236 JB |
2394 | if (IS_G4X(dev)) { |
2395 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
2396 | u32 ipeir = I915_READ(IPEIR_I965); | |
2397 | ||
a70491cc JP |
2398 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2399 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
050ee91f BW |
2400 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2401 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a70491cc | 2402 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2403 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2404 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2405 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2406 | } |
2407 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
2408 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2409 | pr_err("page table error\n"); |
2410 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2411 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2412 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2413 | } |
2414 | } | |
2415 | ||
a6c45cf0 | 2416 | if (!IS_GEN2(dev)) { |
8a905236 JB |
2417 | if (eir & I915_ERROR_PAGE_TABLE) { |
2418 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2419 | pr_err("page table error\n"); |
2420 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2421 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2422 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2423 | } |
2424 | } | |
2425 | ||
2426 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
a70491cc | 2427 | pr_err("memory refresh error:\n"); |
9db4a9c7 | 2428 | for_each_pipe(pipe) |
a70491cc | 2429 | pr_err("pipe %c stat: 0x%08x\n", |
9db4a9c7 | 2430 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
8a905236 JB |
2431 | /* pipestat has already been acked */ |
2432 | } | |
2433 | if (eir & I915_ERROR_INSTRUCTION) { | |
a70491cc JP |
2434 | pr_err("instruction error\n"); |
2435 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); | |
050ee91f BW |
2436 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2437 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a6c45cf0 | 2438 | if (INTEL_INFO(dev)->gen < 4) { |
8a905236 JB |
2439 | u32 ipeir = I915_READ(IPEIR); |
2440 | ||
a70491cc JP |
2441 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
2442 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); | |
a70491cc | 2443 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); |
8a905236 | 2444 | I915_WRITE(IPEIR, ipeir); |
3143a2bf | 2445 | POSTING_READ(IPEIR); |
8a905236 JB |
2446 | } else { |
2447 | u32 ipeir = I915_READ(IPEIR_I965); | |
2448 | ||
a70491cc JP |
2449 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2450 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
a70491cc | 2451 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2452 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2453 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2454 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2455 | } |
2456 | } | |
2457 | ||
2458 | I915_WRITE(EIR, eir); | |
3143a2bf | 2459 | POSTING_READ(EIR); |
8a905236 JB |
2460 | eir = I915_READ(EIR); |
2461 | if (eir) { | |
2462 | /* | |
2463 | * some errors might have become stuck, | |
2464 | * mask them. | |
2465 | */ | |
2466 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
2467 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
2468 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2469 | } | |
35aed2e6 CW |
2470 | } |
2471 | ||
2472 | /** | |
2473 | * i915_handle_error - handle an error interrupt | |
2474 | * @dev: drm device | |
2475 | * | |
2476 | * Do some basic checking of regsiter state at error interrupt time and | |
2477 | * dump it to the syslog. Also call i915_capture_error_state() to make | |
2478 | * sure we get a record and make it available in debugfs. Fire a uevent | |
2479 | * so userspace knows something bad happened (should trigger collection | |
2480 | * of a ring dump etc.). | |
2481 | */ | |
58174462 MK |
2482 | void i915_handle_error(struct drm_device *dev, bool wedged, |
2483 | const char *fmt, ...) | |
35aed2e6 CW |
2484 | { |
2485 | struct drm_i915_private *dev_priv = dev->dev_private; | |
58174462 MK |
2486 | va_list args; |
2487 | char error_msg[80]; | |
35aed2e6 | 2488 | |
58174462 MK |
2489 | va_start(args, fmt); |
2490 | vscnprintf(error_msg, sizeof(error_msg), fmt, args); | |
2491 | va_end(args); | |
2492 | ||
2493 | i915_capture_error_state(dev, wedged, error_msg); | |
35aed2e6 | 2494 | i915_report_and_clear_eir(dev); |
8a905236 | 2495 | |
ba1234d1 | 2496 | if (wedged) { |
f69061be DV |
2497 | atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG, |
2498 | &dev_priv->gpu_error.reset_counter); | |
ba1234d1 | 2499 | |
11ed50ec | 2500 | /* |
17e1df07 DV |
2501 | * Wakeup waiting processes so that the reset work function |
2502 | * i915_error_work_func doesn't deadlock trying to grab various | |
2503 | * locks. By bumping the reset counter first, the woken | |
2504 | * processes will see a reset in progress and back off, | |
2505 | * releasing their locks and then wait for the reset completion. | |
2506 | * We must do this for _all_ gpu waiters that might hold locks | |
2507 | * that the reset work needs to acquire. | |
2508 | * | |
2509 | * Note: The wake_up serves as the required memory barrier to | |
2510 | * ensure that the waiters see the updated value of the reset | |
2511 | * counter atomic_t. | |
11ed50ec | 2512 | */ |
17e1df07 | 2513 | i915_error_wake_up(dev_priv, false); |
11ed50ec BG |
2514 | } |
2515 | ||
122f46ba DV |
2516 | /* |
2517 | * Our reset work can grab modeset locks (since it needs to reset the | |
2518 | * state of outstanding pagelips). Hence it must not be run on our own | |
2519 | * dev-priv->wq work queue for otherwise the flush_work in the pageflip | |
2520 | * code will deadlock. | |
2521 | */ | |
2522 | schedule_work(&dev_priv->gpu_error.work); | |
8a905236 JB |
2523 | } |
2524 | ||
21ad8330 | 2525 | static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe) |
4e5359cd | 2526 | { |
2d1013dd | 2527 | struct drm_i915_private *dev_priv = dev->dev_private; |
4e5359cd SF |
2528 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
2529 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 2530 | struct drm_i915_gem_object *obj; |
4e5359cd SF |
2531 | struct intel_unpin_work *work; |
2532 | unsigned long flags; | |
2533 | bool stall_detected; | |
2534 | ||
2535 | /* Ignore early vblank irqs */ | |
2536 | if (intel_crtc == NULL) | |
2537 | return; | |
2538 | ||
2539 | spin_lock_irqsave(&dev->event_lock, flags); | |
2540 | work = intel_crtc->unpin_work; | |
2541 | ||
e7d841ca CW |
2542 | if (work == NULL || |
2543 | atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE || | |
2544 | !work->enable_stall_check) { | |
4e5359cd SF |
2545 | /* Either the pending flip IRQ arrived, or we're too early. Don't check */ |
2546 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2547 | return; | |
2548 | } | |
2549 | ||
2550 | /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ | |
05394f39 | 2551 | obj = work->pending_flip_obj; |
a6c45cf0 | 2552 | if (INTEL_INFO(dev)->gen >= 4) { |
9db4a9c7 | 2553 | int dspsurf = DSPSURF(intel_crtc->plane); |
446f2545 | 2554 | stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) == |
f343c5f6 | 2555 | i915_gem_obj_ggtt_offset(obj); |
4e5359cd | 2556 | } else { |
9db4a9c7 | 2557 | int dspaddr = DSPADDR(intel_crtc->plane); |
f343c5f6 | 2558 | stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) + |
f4510a27 MR |
2559 | crtc->y * crtc->primary->fb->pitches[0] + |
2560 | crtc->x * crtc->primary->fb->bits_per_pixel/8); | |
4e5359cd SF |
2561 | } |
2562 | ||
2563 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2564 | ||
2565 | if (stall_detected) { | |
2566 | DRM_DEBUG_DRIVER("Pageflip stall detected\n"); | |
2567 | intel_prepare_page_flip(dev, intel_crtc->plane); | |
2568 | } | |
2569 | } | |
2570 | ||
42f52ef8 KP |
2571 | /* Called from drm generic code, passed 'crtc' which |
2572 | * we use as a pipe index | |
2573 | */ | |
f71d4af4 | 2574 | static int i915_enable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 | 2575 | { |
2d1013dd | 2576 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2577 | unsigned long irqflags; |
71e0ffa5 | 2578 | |
5eddb70b | 2579 | if (!i915_pipe_enabled(dev, pipe)) |
71e0ffa5 | 2580 | return -EINVAL; |
0a3e67a4 | 2581 | |
1ec14ad3 | 2582 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2583 | if (INTEL_INFO(dev)->gen >= 4) |
7c463586 | 2584 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2585 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
e9d21d7f | 2586 | else |
7c463586 | 2587 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2588 | PIPE_VBLANK_INTERRUPT_STATUS); |
8692d00e CW |
2589 | |
2590 | /* maintain vblank delivery even in deep C-states */ | |
3d13ef2e | 2591 | if (INTEL_INFO(dev)->gen == 3) |
6b26c86d | 2592 | I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS)); |
1ec14ad3 | 2593 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
8692d00e | 2594 | |
0a3e67a4 JB |
2595 | return 0; |
2596 | } | |
2597 | ||
f71d4af4 | 2598 | static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
f796cf8f | 2599 | { |
2d1013dd | 2600 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2601 | unsigned long irqflags; |
b518421f | 2602 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2603 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2604 | |
2605 | if (!i915_pipe_enabled(dev, pipe)) | |
2606 | return -EINVAL; | |
2607 | ||
2608 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 2609 | ironlake_enable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2610 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2611 | ||
2612 | return 0; | |
2613 | } | |
2614 | ||
7e231dbe JB |
2615 | static int valleyview_enable_vblank(struct drm_device *dev, int pipe) |
2616 | { | |
2d1013dd | 2617 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2618 | unsigned long irqflags; |
7e231dbe JB |
2619 | |
2620 | if (!i915_pipe_enabled(dev, pipe)) | |
2621 | return -EINVAL; | |
2622 | ||
2623 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 | 2624 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2625 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2626 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2627 | ||
2628 | return 0; | |
2629 | } | |
2630 | ||
abd58f01 BW |
2631 | static int gen8_enable_vblank(struct drm_device *dev, int pipe) |
2632 | { | |
2633 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2634 | unsigned long irqflags; | |
abd58f01 BW |
2635 | |
2636 | if (!i915_pipe_enabled(dev, pipe)) | |
2637 | return -EINVAL; | |
2638 | ||
2639 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
7167d7c6 DV |
2640 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK; |
2641 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2642 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2643 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2644 | return 0; | |
2645 | } | |
2646 | ||
42f52ef8 KP |
2647 | /* Called from drm generic code, passed 'crtc' which |
2648 | * we use as a pipe index | |
2649 | */ | |
f71d4af4 | 2650 | static void i915_disable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 | 2651 | { |
2d1013dd | 2652 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2653 | unsigned long irqflags; |
0a3e67a4 | 2654 | |
1ec14ad3 | 2655 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
3d13ef2e | 2656 | if (INTEL_INFO(dev)->gen == 3) |
6b26c86d | 2657 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS)); |
8692d00e | 2658 | |
f796cf8f | 2659 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 ID |
2660 | PIPE_VBLANK_INTERRUPT_STATUS | |
2661 | PIPE_START_VBLANK_INTERRUPT_STATUS); | |
f796cf8f JB |
2662 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2663 | } | |
2664 | ||
f71d4af4 | 2665 | static void ironlake_disable_vblank(struct drm_device *dev, int pipe) |
f796cf8f | 2666 | { |
2d1013dd | 2667 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2668 | unsigned long irqflags; |
b518421f | 2669 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2670 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2671 | |
2672 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 2673 | ironlake_disable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2674 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2675 | } | |
2676 | ||
7e231dbe JB |
2677 | static void valleyview_disable_vblank(struct drm_device *dev, int pipe) |
2678 | { | |
2d1013dd | 2679 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2680 | unsigned long irqflags; |
7e231dbe JB |
2681 | |
2682 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 | 2683 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 | 2684 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2685 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2686 | } | |
2687 | ||
abd58f01 BW |
2688 | static void gen8_disable_vblank(struct drm_device *dev, int pipe) |
2689 | { | |
2690 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2691 | unsigned long irqflags; | |
abd58f01 BW |
2692 | |
2693 | if (!i915_pipe_enabled(dev, pipe)) | |
2694 | return; | |
2695 | ||
2696 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
7167d7c6 DV |
2697 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK; |
2698 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2699 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2700 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2701 | } | |
2702 | ||
893eead0 CW |
2703 | static u32 |
2704 | ring_last_seqno(struct intel_ring_buffer *ring) | |
852835f3 | 2705 | { |
893eead0 CW |
2706 | return list_entry(ring->request_list.prev, |
2707 | struct drm_i915_gem_request, list)->seqno; | |
2708 | } | |
2709 | ||
9107e9d2 CW |
2710 | static bool |
2711 | ring_idle(struct intel_ring_buffer *ring, u32 seqno) | |
2712 | { | |
2713 | return (list_empty(&ring->request_list) || | |
2714 | i915_seqno_passed(seqno, ring_last_seqno(ring))); | |
f65d9421 BG |
2715 | } |
2716 | ||
a028c4b0 DV |
2717 | static bool |
2718 | ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr) | |
2719 | { | |
2720 | if (INTEL_INFO(dev)->gen >= 8) { | |
2721 | /* | |
2722 | * FIXME: gen8 semaphore support - currently we don't emit | |
2723 | * semaphores on bdw anyway, but this needs to be addressed when | |
2724 | * we merge that code. | |
2725 | */ | |
2726 | return false; | |
2727 | } else { | |
2728 | ipehr &= ~MI_SEMAPHORE_SYNC_MASK; | |
2729 | return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | | |
2730 | MI_SEMAPHORE_REGISTER); | |
2731 | } | |
2732 | } | |
2733 | ||
921d42ea DV |
2734 | static struct intel_ring_buffer * |
2735 | semaphore_wait_to_signaller_ring(struct intel_ring_buffer *ring, u32 ipehr) | |
2736 | { | |
2737 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
2738 | struct intel_ring_buffer *signaller; | |
2739 | int i; | |
2740 | ||
2741 | if (INTEL_INFO(dev_priv->dev)->gen >= 8) { | |
2742 | /* | |
2743 | * FIXME: gen8 semaphore support - currently we don't emit | |
2744 | * semaphores on bdw anyway, but this needs to be addressed when | |
2745 | * we merge that code. | |
2746 | */ | |
2747 | return NULL; | |
2748 | } else { | |
2749 | u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK; | |
2750 | ||
2751 | for_each_ring(signaller, dev_priv, i) { | |
2752 | if(ring == signaller) | |
2753 | continue; | |
2754 | ||
ebc348b2 | 2755 | if (sync_bits == signaller->semaphore.mbox.wait[ring->id]) |
921d42ea DV |
2756 | return signaller; |
2757 | } | |
2758 | } | |
2759 | ||
2760 | DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x\n", | |
2761 | ring->id, ipehr); | |
2762 | ||
2763 | return NULL; | |
2764 | } | |
2765 | ||
6274f212 CW |
2766 | static struct intel_ring_buffer * |
2767 | semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno) | |
a24a11e6 CW |
2768 | { |
2769 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
88fe429d DV |
2770 | u32 cmd, ipehr, head; |
2771 | int i; | |
a24a11e6 CW |
2772 | |
2773 | ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); | |
a028c4b0 | 2774 | if (!ipehr_is_semaphore_wait(ring->dev, ipehr)) |
6274f212 | 2775 | return NULL; |
a24a11e6 | 2776 | |
88fe429d DV |
2777 | /* |
2778 | * HEAD is likely pointing to the dword after the actual command, | |
2779 | * so scan backwards until we find the MBOX. But limit it to just 3 | |
2780 | * dwords. Note that we don't care about ACTHD here since that might | |
2781 | * point at at batch, and semaphores are always emitted into the | |
2782 | * ringbuffer itself. | |
a24a11e6 | 2783 | */ |
88fe429d DV |
2784 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
2785 | ||
2786 | for (i = 4; i; --i) { | |
2787 | /* | |
2788 | * Be paranoid and presume the hw has gone off into the wild - | |
2789 | * our ring is smaller than what the hardware (and hence | |
2790 | * HEAD_ADDR) allows. Also handles wrap-around. | |
2791 | */ | |
2792 | head &= ring->size - 1; | |
2793 | ||
2794 | /* This here seems to blow up */ | |
2795 | cmd = ioread32(ring->virtual_start + head); | |
a24a11e6 CW |
2796 | if (cmd == ipehr) |
2797 | break; | |
2798 | ||
88fe429d DV |
2799 | head -= 4; |
2800 | } | |
a24a11e6 | 2801 | |
88fe429d DV |
2802 | if (!i) |
2803 | return NULL; | |
a24a11e6 | 2804 | |
88fe429d | 2805 | *seqno = ioread32(ring->virtual_start + head + 4) + 1; |
921d42ea | 2806 | return semaphore_wait_to_signaller_ring(ring, ipehr); |
a24a11e6 CW |
2807 | } |
2808 | ||
6274f212 CW |
2809 | static int semaphore_passed(struct intel_ring_buffer *ring) |
2810 | { | |
2811 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
2812 | struct intel_ring_buffer *signaller; | |
2813 | u32 seqno, ctl; | |
2814 | ||
2815 | ring->hangcheck.deadlock = true; | |
2816 | ||
2817 | signaller = semaphore_waits_for(ring, &seqno); | |
2818 | if (signaller == NULL || signaller->hangcheck.deadlock) | |
2819 | return -1; | |
2820 | ||
2821 | /* cursory check for an unkickable deadlock */ | |
2822 | ctl = I915_READ_CTL(signaller); | |
2823 | if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0) | |
2824 | return -1; | |
2825 | ||
2826 | return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno); | |
2827 | } | |
2828 | ||
2829 | static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) | |
2830 | { | |
2831 | struct intel_ring_buffer *ring; | |
2832 | int i; | |
2833 | ||
2834 | for_each_ring(ring, dev_priv, i) | |
2835 | ring->hangcheck.deadlock = false; | |
2836 | } | |
2837 | ||
ad8beaea | 2838 | static enum intel_ring_hangcheck_action |
50877445 | 2839 | ring_stuck(struct intel_ring_buffer *ring, u64 acthd) |
1ec14ad3 CW |
2840 | { |
2841 | struct drm_device *dev = ring->dev; | |
2842 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9107e9d2 CW |
2843 | u32 tmp; |
2844 | ||
6274f212 | 2845 | if (ring->hangcheck.acthd != acthd) |
f2f4d82f | 2846 | return HANGCHECK_ACTIVE; |
6274f212 | 2847 | |
9107e9d2 | 2848 | if (IS_GEN2(dev)) |
f2f4d82f | 2849 | return HANGCHECK_HUNG; |
9107e9d2 CW |
2850 | |
2851 | /* Is the chip hanging on a WAIT_FOR_EVENT? | |
2852 | * If so we can simply poke the RB_WAIT bit | |
2853 | * and break the hang. This should work on | |
2854 | * all but the second generation chipsets. | |
2855 | */ | |
2856 | tmp = I915_READ_CTL(ring); | |
1ec14ad3 | 2857 | if (tmp & RING_WAIT) { |
58174462 MK |
2858 | i915_handle_error(dev, false, |
2859 | "Kicking stuck wait on %s", | |
2860 | ring->name); | |
1ec14ad3 | 2861 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2862 | return HANGCHECK_KICK; |
6274f212 CW |
2863 | } |
2864 | ||
2865 | if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { | |
2866 | switch (semaphore_passed(ring)) { | |
2867 | default: | |
f2f4d82f | 2868 | return HANGCHECK_HUNG; |
6274f212 | 2869 | case 1: |
58174462 MK |
2870 | i915_handle_error(dev, false, |
2871 | "Kicking stuck semaphore on %s", | |
2872 | ring->name); | |
6274f212 | 2873 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2874 | return HANGCHECK_KICK; |
6274f212 | 2875 | case 0: |
f2f4d82f | 2876 | return HANGCHECK_WAIT; |
6274f212 | 2877 | } |
9107e9d2 | 2878 | } |
ed5cbb03 | 2879 | |
f2f4d82f | 2880 | return HANGCHECK_HUNG; |
ed5cbb03 MK |
2881 | } |
2882 | ||
f65d9421 BG |
2883 | /** |
2884 | * This is called when the chip hasn't reported back with completed | |
05407ff8 MK |
2885 | * batchbuffers in a long time. We keep track per ring seqno progress and |
2886 | * if there are no progress, hangcheck score for that ring is increased. | |
2887 | * Further, acthd is inspected to see if the ring is stuck. On stuck case | |
2888 | * we kick the ring. If we see no progress on three subsequent calls | |
2889 | * we assume chip is wedged and try to fix it by resetting the chip. | |
f65d9421 | 2890 | */ |
a658b5d2 | 2891 | static void i915_hangcheck_elapsed(unsigned long data) |
f65d9421 BG |
2892 | { |
2893 | struct drm_device *dev = (struct drm_device *)data; | |
2d1013dd | 2894 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 2895 | struct intel_ring_buffer *ring; |
b4519513 | 2896 | int i; |
05407ff8 | 2897 | int busy_count = 0, rings_hung = 0; |
9107e9d2 CW |
2898 | bool stuck[I915_NUM_RINGS] = { 0 }; |
2899 | #define BUSY 1 | |
2900 | #define KICK 5 | |
2901 | #define HUNG 20 | |
893eead0 | 2902 | |
d330a953 | 2903 | if (!i915.enable_hangcheck) |
3e0dc6b0 BW |
2904 | return; |
2905 | ||
b4519513 | 2906 | for_each_ring(ring, dev_priv, i) { |
50877445 CW |
2907 | u64 acthd; |
2908 | u32 seqno; | |
9107e9d2 | 2909 | bool busy = true; |
05407ff8 | 2910 | |
6274f212 CW |
2911 | semaphore_clear_deadlocks(dev_priv); |
2912 | ||
05407ff8 MK |
2913 | seqno = ring->get_seqno(ring, false); |
2914 | acthd = intel_ring_get_active_head(ring); | |
b4519513 | 2915 | |
9107e9d2 CW |
2916 | if (ring->hangcheck.seqno == seqno) { |
2917 | if (ring_idle(ring, seqno)) { | |
da661464 MK |
2918 | ring->hangcheck.action = HANGCHECK_IDLE; |
2919 | ||
9107e9d2 CW |
2920 | if (waitqueue_active(&ring->irq_queue)) { |
2921 | /* Issue a wake-up to catch stuck h/w. */ | |
094f9a54 | 2922 | if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) { |
f4adcd24 DV |
2923 | if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring))) |
2924 | DRM_ERROR("Hangcheck timer elapsed... %s idle\n", | |
2925 | ring->name); | |
2926 | else | |
2927 | DRM_INFO("Fake missed irq on %s\n", | |
2928 | ring->name); | |
094f9a54 CW |
2929 | wake_up_all(&ring->irq_queue); |
2930 | } | |
2931 | /* Safeguard against driver failure */ | |
2932 | ring->hangcheck.score += BUSY; | |
9107e9d2 CW |
2933 | } else |
2934 | busy = false; | |
05407ff8 | 2935 | } else { |
6274f212 CW |
2936 | /* We always increment the hangcheck score |
2937 | * if the ring is busy and still processing | |
2938 | * the same request, so that no single request | |
2939 | * can run indefinitely (such as a chain of | |
2940 | * batches). The only time we do not increment | |
2941 | * the hangcheck score on this ring, if this | |
2942 | * ring is in a legitimate wait for another | |
2943 | * ring. In that case the waiting ring is a | |
2944 | * victim and we want to be sure we catch the | |
2945 | * right culprit. Then every time we do kick | |
2946 | * the ring, add a small increment to the | |
2947 | * score so that we can catch a batch that is | |
2948 | * being repeatedly kicked and so responsible | |
2949 | * for stalling the machine. | |
2950 | */ | |
ad8beaea MK |
2951 | ring->hangcheck.action = ring_stuck(ring, |
2952 | acthd); | |
2953 | ||
2954 | switch (ring->hangcheck.action) { | |
da661464 | 2955 | case HANGCHECK_IDLE: |
f2f4d82f | 2956 | case HANGCHECK_WAIT: |
6274f212 | 2957 | break; |
f2f4d82f | 2958 | case HANGCHECK_ACTIVE: |
ea04cb31 | 2959 | ring->hangcheck.score += BUSY; |
6274f212 | 2960 | break; |
f2f4d82f | 2961 | case HANGCHECK_KICK: |
ea04cb31 | 2962 | ring->hangcheck.score += KICK; |
6274f212 | 2963 | break; |
f2f4d82f | 2964 | case HANGCHECK_HUNG: |
ea04cb31 | 2965 | ring->hangcheck.score += HUNG; |
6274f212 CW |
2966 | stuck[i] = true; |
2967 | break; | |
2968 | } | |
05407ff8 | 2969 | } |
9107e9d2 | 2970 | } else { |
da661464 MK |
2971 | ring->hangcheck.action = HANGCHECK_ACTIVE; |
2972 | ||
9107e9d2 CW |
2973 | /* Gradually reduce the count so that we catch DoS |
2974 | * attempts across multiple batches. | |
2975 | */ | |
2976 | if (ring->hangcheck.score > 0) | |
2977 | ring->hangcheck.score--; | |
d1e61e7f CW |
2978 | } |
2979 | ||
05407ff8 MK |
2980 | ring->hangcheck.seqno = seqno; |
2981 | ring->hangcheck.acthd = acthd; | |
9107e9d2 | 2982 | busy_count += busy; |
893eead0 | 2983 | } |
b9201c14 | 2984 | |
92cab734 | 2985 | for_each_ring(ring, dev_priv, i) { |
b6b0fac0 | 2986 | if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) { |
b8d88d1d DV |
2987 | DRM_INFO("%s on %s\n", |
2988 | stuck[i] ? "stuck" : "no progress", | |
2989 | ring->name); | |
a43adf07 | 2990 | rings_hung++; |
92cab734 MK |
2991 | } |
2992 | } | |
2993 | ||
05407ff8 | 2994 | if (rings_hung) |
58174462 | 2995 | return i915_handle_error(dev, true, "Ring hung"); |
f65d9421 | 2996 | |
05407ff8 MK |
2997 | if (busy_count) |
2998 | /* Reset timer case chip hangs without another request | |
2999 | * being added */ | |
10cd45b6 MK |
3000 | i915_queue_hangcheck(dev); |
3001 | } | |
3002 | ||
3003 | void i915_queue_hangcheck(struct drm_device *dev) | |
3004 | { | |
3005 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d330a953 | 3006 | if (!i915.enable_hangcheck) |
10cd45b6 MK |
3007 | return; |
3008 | ||
3009 | mod_timer(&dev_priv->gpu_error.hangcheck_timer, | |
3010 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); | |
f65d9421 BG |
3011 | } |
3012 | ||
1c69eb42 | 3013 | static void ibx_irq_reset(struct drm_device *dev) |
91738a95 PZ |
3014 | { |
3015 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3016 | ||
3017 | if (HAS_PCH_NOP(dev)) | |
3018 | return; | |
3019 | ||
f86f3fb0 | 3020 | GEN5_IRQ_RESET(SDE); |
105b122e PZ |
3021 | |
3022 | if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) | |
3023 | I915_WRITE(SERR_INT, 0xffffffff); | |
622364b6 | 3024 | } |
105b122e | 3025 | |
622364b6 PZ |
3026 | /* |
3027 | * SDEIER is also touched by the interrupt handler to work around missed PCH | |
3028 | * interrupts. Hence we can't update it after the interrupt handler is enabled - | |
3029 | * instead we unconditionally enable all PCH interrupt sources here, but then | |
3030 | * only unmask them as needed with SDEIMR. | |
3031 | * | |
3032 | * This function needs to be called before interrupts are enabled. | |
3033 | */ | |
3034 | static void ibx_irq_pre_postinstall(struct drm_device *dev) | |
3035 | { | |
3036 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3037 | ||
3038 | if (HAS_PCH_NOP(dev)) | |
3039 | return; | |
3040 | ||
3041 | WARN_ON(I915_READ(SDEIER) != 0); | |
91738a95 PZ |
3042 | I915_WRITE(SDEIER, 0xffffffff); |
3043 | POSTING_READ(SDEIER); | |
3044 | } | |
3045 | ||
7c4d664e | 3046 | static void gen5_gt_irq_reset(struct drm_device *dev) |
d18ea1b5 DV |
3047 | { |
3048 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3049 | ||
f86f3fb0 | 3050 | GEN5_IRQ_RESET(GT); |
a9d356a6 | 3051 | if (INTEL_INFO(dev)->gen >= 6) |
f86f3fb0 | 3052 | GEN5_IRQ_RESET(GEN6_PM); |
d18ea1b5 DV |
3053 | } |
3054 | ||
1da177e4 LT |
3055 | /* drm_dma.h hooks |
3056 | */ | |
be30b29f | 3057 | static void ironlake_irq_reset(struct drm_device *dev) |
036a4a7d | 3058 | { |
2d1013dd | 3059 | struct drm_i915_private *dev_priv = dev->dev_private; |
036a4a7d | 3060 | |
0c841212 | 3061 | I915_WRITE(HWSTAM, 0xffffffff); |
bdfcdb63 | 3062 | |
f86f3fb0 | 3063 | GEN5_IRQ_RESET(DE); |
c6d954c1 PZ |
3064 | if (IS_GEN7(dev)) |
3065 | I915_WRITE(GEN7_ERR_INT, 0xffffffff); | |
036a4a7d | 3066 | |
7c4d664e | 3067 | gen5_gt_irq_reset(dev); |
c650156a | 3068 | |
1c69eb42 | 3069 | ibx_irq_reset(dev); |
7d99163d | 3070 | } |
c650156a | 3071 | |
be30b29f PZ |
3072 | static void ironlake_irq_preinstall(struct drm_device *dev) |
3073 | { | |
be30b29f | 3074 | ironlake_irq_reset(dev); |
7d99163d BW |
3075 | } |
3076 | ||
7e231dbe JB |
3077 | static void valleyview_irq_preinstall(struct drm_device *dev) |
3078 | { | |
2d1013dd | 3079 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
3080 | int pipe; |
3081 | ||
7e231dbe JB |
3082 | /* VLV magic */ |
3083 | I915_WRITE(VLV_IMR, 0); | |
3084 | I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); | |
3085 | I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); | |
3086 | I915_WRITE(RING_IMR(BLT_RING_BASE), 0); | |
3087 | ||
7e231dbe JB |
3088 | /* and GT */ |
3089 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
3090 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
d18ea1b5 | 3091 | |
7c4d664e | 3092 | gen5_gt_irq_reset(dev); |
7e231dbe JB |
3093 | |
3094 | I915_WRITE(DPINVGTT, 0xff); | |
3095 | ||
3096 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3097 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3098 | for_each_pipe(pipe) | |
3099 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
3100 | I915_WRITE(VLV_IIR, 0xffffffff); | |
3101 | I915_WRITE(VLV_IMR, 0xffffffff); | |
3102 | I915_WRITE(VLV_IER, 0x0); | |
3103 | POSTING_READ(VLV_IER); | |
3104 | } | |
3105 | ||
823f6b38 | 3106 | static void gen8_irq_reset(struct drm_device *dev) |
abd58f01 BW |
3107 | { |
3108 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3109 | int pipe; | |
3110 | ||
abd58f01 BW |
3111 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
3112 | POSTING_READ(GEN8_MASTER_IRQ); | |
3113 | ||
f86f3fb0 PZ |
3114 | GEN8_IRQ_RESET_NDX(GT, 0); |
3115 | GEN8_IRQ_RESET_NDX(GT, 1); | |
3116 | GEN8_IRQ_RESET_NDX(GT, 2); | |
3117 | GEN8_IRQ_RESET_NDX(GT, 3); | |
abd58f01 | 3118 | |
823f6b38 | 3119 | for_each_pipe(pipe) |
f86f3fb0 | 3120 | GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); |
abd58f01 | 3121 | |
f86f3fb0 PZ |
3122 | GEN5_IRQ_RESET(GEN8_DE_PORT_); |
3123 | GEN5_IRQ_RESET(GEN8_DE_MISC_); | |
3124 | GEN5_IRQ_RESET(GEN8_PCU_); | |
abd58f01 | 3125 | |
1c69eb42 | 3126 | ibx_irq_reset(dev); |
abd58f01 | 3127 | } |
09f2344d | 3128 | |
823f6b38 PZ |
3129 | static void gen8_irq_preinstall(struct drm_device *dev) |
3130 | { | |
3131 | gen8_irq_reset(dev); | |
abd58f01 BW |
3132 | } |
3133 | ||
43f328d7 VS |
3134 | static void cherryview_irq_preinstall(struct drm_device *dev) |
3135 | { | |
3136 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3137 | int pipe; | |
3138 | ||
3139 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3140 | POSTING_READ(GEN8_MASTER_IRQ); | |
3141 | ||
3142 | GEN8_IRQ_RESET_NDX(GT, 0); | |
3143 | GEN8_IRQ_RESET_NDX(GT, 1); | |
3144 | GEN8_IRQ_RESET_NDX(GT, 2); | |
3145 | GEN8_IRQ_RESET_NDX(GT, 3); | |
3146 | ||
3147 | GEN5_IRQ_RESET(GEN8_PCU_); | |
3148 | ||
3149 | POSTING_READ(GEN8_PCU_IIR); | |
3150 | ||
3151 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV); | |
3152 | ||
3153 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3154 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3155 | ||
3156 | for_each_pipe(pipe) | |
3157 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
3158 | ||
3159 | I915_WRITE(VLV_IMR, 0xffffffff); | |
3160 | I915_WRITE(VLV_IER, 0x0); | |
3161 | I915_WRITE(VLV_IIR, 0xffffffff); | |
3162 | POSTING_READ(VLV_IIR); | |
3163 | } | |
3164 | ||
82a28bcf | 3165 | static void ibx_hpd_irq_setup(struct drm_device *dev) |
7fe0b973 | 3166 | { |
2d1013dd | 3167 | struct drm_i915_private *dev_priv = dev->dev_private; |
82a28bcf DV |
3168 | struct drm_mode_config *mode_config = &dev->mode_config; |
3169 | struct intel_encoder *intel_encoder; | |
fee884ed | 3170 | u32 hotplug_irqs, hotplug, enabled_irqs = 0; |
82a28bcf DV |
3171 | |
3172 | if (HAS_PCH_IBX(dev)) { | |
fee884ed | 3173 | hotplug_irqs = SDE_HOTPLUG_MASK; |
82a28bcf | 3174 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
cd569aed | 3175 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
fee884ed | 3176 | enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin]; |
82a28bcf | 3177 | } else { |
fee884ed | 3178 | hotplug_irqs = SDE_HOTPLUG_MASK_CPT; |
82a28bcf | 3179 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
cd569aed | 3180 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
fee884ed | 3181 | enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin]; |
82a28bcf | 3182 | } |
7fe0b973 | 3183 | |
fee884ed | 3184 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); |
82a28bcf DV |
3185 | |
3186 | /* | |
3187 | * Enable digital hotplug on the PCH, and configure the DP short pulse | |
3188 | * duration to 2ms (which is the minimum in the Display Port spec) | |
3189 | * | |
3190 | * This register is the same on all known PCH chips. | |
3191 | */ | |
7fe0b973 KP |
3192 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
3193 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); | |
3194 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; | |
3195 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; | |
3196 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; | |
3197 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); | |
3198 | } | |
3199 | ||
d46da437 PZ |
3200 | static void ibx_irq_postinstall(struct drm_device *dev) |
3201 | { | |
2d1013dd | 3202 | struct drm_i915_private *dev_priv = dev->dev_private; |
82a28bcf | 3203 | u32 mask; |
e5868a31 | 3204 | |
692a04cf DV |
3205 | if (HAS_PCH_NOP(dev)) |
3206 | return; | |
3207 | ||
105b122e | 3208 | if (HAS_PCH_IBX(dev)) |
5c673b60 | 3209 | mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; |
105b122e | 3210 | else |
5c673b60 | 3211 | mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; |
8664281b | 3212 | |
337ba017 | 3213 | GEN5_ASSERT_IIR_IS_ZERO(SDEIIR); |
d46da437 | 3214 | I915_WRITE(SDEIMR, ~mask); |
d46da437 PZ |
3215 | } |
3216 | ||
0a9a8c91 DV |
3217 | static void gen5_gt_irq_postinstall(struct drm_device *dev) |
3218 | { | |
3219 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3220 | u32 pm_irqs, gt_irqs; | |
3221 | ||
3222 | pm_irqs = gt_irqs = 0; | |
3223 | ||
3224 | dev_priv->gt_irq_mask = ~0; | |
040d2baa | 3225 | if (HAS_L3_DPF(dev)) { |
0a9a8c91 | 3226 | /* L3 parity interrupt is always unmasked. */ |
35a85ac6 BW |
3227 | dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev); |
3228 | gt_irqs |= GT_PARITY_ERROR(dev); | |
0a9a8c91 DV |
3229 | } |
3230 | ||
3231 | gt_irqs |= GT_RENDER_USER_INTERRUPT; | |
3232 | if (IS_GEN5(dev)) { | |
3233 | gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | | |
3234 | ILK_BSD_USER_INTERRUPT; | |
3235 | } else { | |
3236 | gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; | |
3237 | } | |
3238 | ||
35079899 | 3239 | GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); |
0a9a8c91 DV |
3240 | |
3241 | if (INTEL_INFO(dev)->gen >= 6) { | |
a6706b45 | 3242 | pm_irqs |= dev_priv->pm_rps_events; |
0a9a8c91 DV |
3243 | |
3244 | if (HAS_VEBOX(dev)) | |
3245 | pm_irqs |= PM_VEBOX_USER_INTERRUPT; | |
3246 | ||
605cd25b | 3247 | dev_priv->pm_irq_mask = 0xffffffff; |
35079899 | 3248 | GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs); |
0a9a8c91 DV |
3249 | } |
3250 | } | |
3251 | ||
f71d4af4 | 3252 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d | 3253 | { |
4bc9d430 | 3254 | unsigned long irqflags; |
2d1013dd | 3255 | struct drm_i915_private *dev_priv = dev->dev_private; |
8e76f8dc PZ |
3256 | u32 display_mask, extra_mask; |
3257 | ||
3258 | if (INTEL_INFO(dev)->gen >= 7) { | |
3259 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | | |
3260 | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | | |
3261 | DE_PLANEB_FLIP_DONE_IVB | | |
5c673b60 | 3262 | DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB); |
8e76f8dc | 3263 | extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | |
5c673b60 | 3264 | DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB); |
8e76f8dc PZ |
3265 | } else { |
3266 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | | |
3267 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | | |
5b3a856b | 3268 | DE_AUX_CHANNEL_A | |
5b3a856b DV |
3269 | DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE | |
3270 | DE_POISON); | |
5c673b60 DV |
3271 | extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT | |
3272 | DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN; | |
8e76f8dc | 3273 | } |
036a4a7d | 3274 | |
1ec14ad3 | 3275 | dev_priv->irq_mask = ~display_mask; |
036a4a7d | 3276 | |
0c841212 PZ |
3277 | I915_WRITE(HWSTAM, 0xeffe); |
3278 | ||
622364b6 PZ |
3279 | ibx_irq_pre_postinstall(dev); |
3280 | ||
35079899 | 3281 | GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); |
036a4a7d | 3282 | |
0a9a8c91 | 3283 | gen5_gt_irq_postinstall(dev); |
036a4a7d | 3284 | |
d46da437 | 3285 | ibx_irq_postinstall(dev); |
7fe0b973 | 3286 | |
f97108d1 | 3287 | if (IS_IRONLAKE_M(dev)) { |
6005ce42 DV |
3288 | /* Enable PCU event interrupts |
3289 | * | |
3290 | * spinlocking not required here for correctness since interrupt | |
4bc9d430 DV |
3291 | * setup is guaranteed to run in single-threaded context. But we |
3292 | * need it to make the assert_spin_locked happy. */ | |
3293 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
f97108d1 | 3294 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); |
4bc9d430 | 3295 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
f97108d1 JB |
3296 | } |
3297 | ||
036a4a7d ZW |
3298 | return 0; |
3299 | } | |
3300 | ||
f8b79e58 ID |
3301 | static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv) |
3302 | { | |
3303 | u32 pipestat_mask; | |
3304 | u32 iir_mask; | |
3305 | ||
3306 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | | |
3307 | PIPE_FIFO_UNDERRUN_STATUS; | |
3308 | ||
3309 | I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask); | |
3310 | I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask); | |
3311 | POSTING_READ(PIPESTAT(PIPE_A)); | |
3312 | ||
3313 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3314 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3315 | ||
3316 | i915_enable_pipestat(dev_priv, PIPE_A, pipestat_mask | | |
3317 | PIPE_GMBUS_INTERRUPT_STATUS); | |
3318 | i915_enable_pipestat(dev_priv, PIPE_B, pipestat_mask); | |
3319 | ||
3320 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3321 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3322 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
3323 | dev_priv->irq_mask &= ~iir_mask; | |
3324 | ||
3325 | I915_WRITE(VLV_IIR, iir_mask); | |
3326 | I915_WRITE(VLV_IIR, iir_mask); | |
3327 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); | |
3328 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); | |
3329 | POSTING_READ(VLV_IER); | |
3330 | } | |
3331 | ||
3332 | static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv) | |
3333 | { | |
3334 | u32 pipestat_mask; | |
3335 | u32 iir_mask; | |
3336 | ||
3337 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3338 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
6c7fba04 | 3339 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; |
f8b79e58 ID |
3340 | |
3341 | dev_priv->irq_mask |= iir_mask; | |
3342 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); | |
3343 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); | |
3344 | I915_WRITE(VLV_IIR, iir_mask); | |
3345 | I915_WRITE(VLV_IIR, iir_mask); | |
3346 | POSTING_READ(VLV_IIR); | |
3347 | ||
3348 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3349 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3350 | ||
3351 | i915_disable_pipestat(dev_priv, PIPE_A, pipestat_mask | | |
3352 | PIPE_GMBUS_INTERRUPT_STATUS); | |
3353 | i915_disable_pipestat(dev_priv, PIPE_B, pipestat_mask); | |
3354 | ||
3355 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | | |
3356 | PIPE_FIFO_UNDERRUN_STATUS; | |
3357 | I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask); | |
3358 | I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask); | |
3359 | POSTING_READ(PIPESTAT(PIPE_A)); | |
3360 | } | |
3361 | ||
3362 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) | |
3363 | { | |
3364 | assert_spin_locked(&dev_priv->irq_lock); | |
3365 | ||
3366 | if (dev_priv->display_irqs_enabled) | |
3367 | return; | |
3368 | ||
3369 | dev_priv->display_irqs_enabled = true; | |
3370 | ||
3371 | if (dev_priv->dev->irq_enabled) | |
3372 | valleyview_display_irqs_install(dev_priv); | |
3373 | } | |
3374 | ||
3375 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) | |
3376 | { | |
3377 | assert_spin_locked(&dev_priv->irq_lock); | |
3378 | ||
3379 | if (!dev_priv->display_irqs_enabled) | |
3380 | return; | |
3381 | ||
3382 | dev_priv->display_irqs_enabled = false; | |
3383 | ||
3384 | if (dev_priv->dev->irq_enabled) | |
3385 | valleyview_display_irqs_uninstall(dev_priv); | |
3386 | } | |
3387 | ||
7e231dbe JB |
3388 | static int valleyview_irq_postinstall(struct drm_device *dev) |
3389 | { | |
2d1013dd | 3390 | struct drm_i915_private *dev_priv = dev->dev_private; |
b79480ba | 3391 | unsigned long irqflags; |
7e231dbe | 3392 | |
f8b79e58 | 3393 | dev_priv->irq_mask = ~0; |
7e231dbe | 3394 | |
20afbda2 DV |
3395 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3396 | POSTING_READ(PORT_HOTPLUG_EN); | |
3397 | ||
7e231dbe | 3398 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
f8b79e58 | 3399 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); |
7e231dbe | 3400 | I915_WRITE(VLV_IIR, 0xffffffff); |
7e231dbe JB |
3401 | POSTING_READ(VLV_IER); |
3402 | ||
b79480ba DV |
3403 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3404 | * just to make the assert_spin_locked check happy. */ | |
3405 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
f8b79e58 ID |
3406 | if (dev_priv->display_irqs_enabled) |
3407 | valleyview_display_irqs_install(dev_priv); | |
b79480ba | 3408 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
31acc7f5 | 3409 | |
7e231dbe JB |
3410 | I915_WRITE(VLV_IIR, 0xffffffff); |
3411 | I915_WRITE(VLV_IIR, 0xffffffff); | |
3412 | ||
0a9a8c91 | 3413 | gen5_gt_irq_postinstall(dev); |
7e231dbe JB |
3414 | |
3415 | /* ack & enable invalid PTE error interrupts */ | |
3416 | #if 0 /* FIXME: add support to irq handler for checking these bits */ | |
3417 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); | |
3418 | I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); | |
3419 | #endif | |
3420 | ||
3421 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); | |
20afbda2 DV |
3422 | |
3423 | return 0; | |
3424 | } | |
3425 | ||
abd58f01 BW |
3426 | static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) |
3427 | { | |
3428 | int i; | |
3429 | ||
3430 | /* These are interrupts we'll toggle with the ring mask register */ | |
3431 | uint32_t gt_interrupts[] = { | |
3432 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | | |
3433 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT | | |
3434 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT, | |
3435 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | | |
3436 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT, | |
3437 | 0, | |
3438 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
3439 | }; | |
3440 | ||
337ba017 | 3441 | for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) |
35079899 | 3442 | GEN8_IRQ_INIT_NDX(GT, i, ~gt_interrupts[i], gt_interrupts[i]); |
0961021a BW |
3443 | |
3444 | dev_priv->pm_irq_mask = 0xffffffff; | |
abd58f01 BW |
3445 | } |
3446 | ||
3447 | static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) | |
3448 | { | |
3449 | struct drm_device *dev = dev_priv->dev; | |
d0e1f1cb | 3450 | uint32_t de_pipe_masked = GEN8_PIPE_PRIMARY_FLIP_DONE | |
13b3a0a7 | 3451 | GEN8_PIPE_CDCLK_CRC_DONE | |
13b3a0a7 | 3452 | GEN8_DE_PIPE_IRQ_FAULT_ERRORS; |
5c673b60 DV |
3453 | uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | |
3454 | GEN8_PIPE_FIFO_UNDERRUN; | |
abd58f01 | 3455 | int pipe; |
13b3a0a7 DV |
3456 | dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; |
3457 | dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; | |
3458 | dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; | |
abd58f01 | 3459 | |
337ba017 | 3460 | for_each_pipe(pipe) |
35079899 PZ |
3461 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, dev_priv->de_irq_mask[pipe], |
3462 | de_pipe_enables); | |
abd58f01 | 3463 | |
35079899 | 3464 | GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A); |
abd58f01 BW |
3465 | } |
3466 | ||
3467 | static int gen8_irq_postinstall(struct drm_device *dev) | |
3468 | { | |
3469 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3470 | ||
622364b6 PZ |
3471 | ibx_irq_pre_postinstall(dev); |
3472 | ||
abd58f01 BW |
3473 | gen8_gt_irq_postinstall(dev_priv); |
3474 | gen8_de_irq_postinstall(dev_priv); | |
3475 | ||
3476 | ibx_irq_postinstall(dev); | |
3477 | ||
3478 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); | |
3479 | POSTING_READ(GEN8_MASTER_IRQ); | |
3480 | ||
3481 | return 0; | |
3482 | } | |
3483 | ||
43f328d7 VS |
3484 | static int cherryview_irq_postinstall(struct drm_device *dev) |
3485 | { | |
3486 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3487 | u32 enable_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3488 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3489 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | | |
3490 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3491 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT | | |
3492 | I915_DISPLAY_PIPE_C_EVENT_INTERRUPT | | |
3493 | I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT; | |
3494 | u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV; | |
3495 | unsigned long irqflags; | |
3496 | int pipe; | |
3497 | ||
3498 | /* | |
3499 | * Leave vblank interrupts masked initially. enable/disable will | |
3500 | * toggle them based on usage. | |
3501 | */ | |
3502 | dev_priv->irq_mask = ~enable_mask | | |
3503 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | | |
3504 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT | | |
3505 | I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT; | |
3506 | ||
3507 | for_each_pipe(pipe) | |
3508 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
3509 | ||
3510 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3511 | i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE); | |
3512 | for_each_pipe(pipe) | |
3513 | i915_enable_pipestat(dev_priv, pipe, pipestat_enable); | |
3514 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3515 | ||
3516 | I915_WRITE(VLV_IIR, 0xffffffff); | |
3517 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); | |
3518 | I915_WRITE(VLV_IER, enable_mask); | |
3519 | ||
3520 | gen8_gt_irq_postinstall(dev_priv); | |
3521 | ||
3522 | I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE); | |
3523 | POSTING_READ(GEN8_MASTER_IRQ); | |
3524 | ||
3525 | return 0; | |
3526 | } | |
3527 | ||
abd58f01 BW |
3528 | static void gen8_irq_uninstall(struct drm_device *dev) |
3529 | { | |
3530 | struct drm_i915_private *dev_priv = dev->dev_private; | |
abd58f01 BW |
3531 | |
3532 | if (!dev_priv) | |
3533 | return; | |
3534 | ||
d4eb6b10 | 3535 | intel_hpd_irq_uninstall(dev_priv); |
abd58f01 | 3536 | |
823f6b38 | 3537 | gen8_irq_reset(dev); |
abd58f01 BW |
3538 | } |
3539 | ||
7e231dbe JB |
3540 | static void valleyview_irq_uninstall(struct drm_device *dev) |
3541 | { | |
2d1013dd | 3542 | struct drm_i915_private *dev_priv = dev->dev_private; |
f8b79e58 | 3543 | unsigned long irqflags; |
7e231dbe JB |
3544 | int pipe; |
3545 | ||
3546 | if (!dev_priv) | |
3547 | return; | |
3548 | ||
843d0e7d ID |
3549 | I915_WRITE(VLV_MASTER_IER, 0); |
3550 | ||
3ca1cced | 3551 | intel_hpd_irq_uninstall(dev_priv); |
ac4c16c5 | 3552 | |
7e231dbe JB |
3553 | for_each_pipe(pipe) |
3554 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
3555 | ||
3556 | I915_WRITE(HWSTAM, 0xffffffff); | |
3557 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3558 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
f8b79e58 ID |
3559 | |
3560 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3561 | if (dev_priv->display_irqs_enabled) | |
3562 | valleyview_display_irqs_uninstall(dev_priv); | |
3563 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3564 | ||
3565 | dev_priv->irq_mask = 0; | |
3566 | ||
7e231dbe JB |
3567 | I915_WRITE(VLV_IIR, 0xffffffff); |
3568 | I915_WRITE(VLV_IMR, 0xffffffff); | |
3569 | I915_WRITE(VLV_IER, 0x0); | |
3570 | POSTING_READ(VLV_IER); | |
3571 | } | |
3572 | ||
43f328d7 VS |
3573 | static void cherryview_irq_uninstall(struct drm_device *dev) |
3574 | { | |
3575 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3576 | int pipe; | |
3577 | ||
3578 | if (!dev_priv) | |
3579 | return; | |
3580 | ||
3581 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3582 | POSTING_READ(GEN8_MASTER_IRQ); | |
3583 | ||
3584 | #define GEN8_IRQ_FINI_NDX(type, which) \ | |
3585 | do { \ | |
3586 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ | |
3587 | I915_WRITE(GEN8_##type##_IER(which), 0); \ | |
3588 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
3589 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
3590 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
3591 | } while (0) | |
3592 | ||
3593 | #define GEN8_IRQ_FINI(type) \ | |
3594 | do { \ | |
3595 | I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \ | |
3596 | I915_WRITE(GEN8_##type##_IER, 0); \ | |
3597 | I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ | |
3598 | POSTING_READ(GEN8_##type##_IIR); \ | |
3599 | I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ | |
3600 | } while (0) | |
3601 | ||
3602 | GEN8_IRQ_FINI_NDX(GT, 0); | |
3603 | GEN8_IRQ_FINI_NDX(GT, 1); | |
3604 | GEN8_IRQ_FINI_NDX(GT, 2); | |
3605 | GEN8_IRQ_FINI_NDX(GT, 3); | |
3606 | ||
3607 | GEN8_IRQ_FINI(PCU); | |
3608 | ||
3609 | #undef GEN8_IRQ_FINI | |
3610 | #undef GEN8_IRQ_FINI_NDX | |
3611 | ||
3612 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3613 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3614 | ||
3615 | for_each_pipe(pipe) | |
3616 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
3617 | ||
3618 | I915_WRITE(VLV_IMR, 0xffffffff); | |
3619 | I915_WRITE(VLV_IER, 0x0); | |
3620 | I915_WRITE(VLV_IIR, 0xffffffff); | |
3621 | POSTING_READ(VLV_IIR); | |
3622 | } | |
3623 | ||
f71d4af4 | 3624 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d | 3625 | { |
2d1013dd | 3626 | struct drm_i915_private *dev_priv = dev->dev_private; |
4697995b JB |
3627 | |
3628 | if (!dev_priv) | |
3629 | return; | |
3630 | ||
3ca1cced | 3631 | intel_hpd_irq_uninstall(dev_priv); |
ac4c16c5 | 3632 | |
be30b29f | 3633 | ironlake_irq_reset(dev); |
036a4a7d ZW |
3634 | } |
3635 | ||
a266c7d5 | 3636 | static void i8xx_irq_preinstall(struct drm_device * dev) |
1da177e4 | 3637 | { |
2d1013dd | 3638 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 3639 | int pipe; |
91e3738e | 3640 | |
9db4a9c7 JB |
3641 | for_each_pipe(pipe) |
3642 | I915_WRITE(PIPESTAT(pipe), 0); | |
a266c7d5 CW |
3643 | I915_WRITE16(IMR, 0xffff); |
3644 | I915_WRITE16(IER, 0x0); | |
3645 | POSTING_READ16(IER); | |
c2798b19 CW |
3646 | } |
3647 | ||
3648 | static int i8xx_irq_postinstall(struct drm_device *dev) | |
3649 | { | |
2d1013dd | 3650 | struct drm_i915_private *dev_priv = dev->dev_private; |
379ef82d | 3651 | unsigned long irqflags; |
c2798b19 | 3652 | |
c2798b19 CW |
3653 | I915_WRITE16(EMR, |
3654 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); | |
3655 | ||
3656 | /* Unmask the interrupts that we always want on. */ | |
3657 | dev_priv->irq_mask = | |
3658 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3659 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3660 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3661 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3662 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3663 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
3664 | ||
3665 | I915_WRITE16(IER, | |
3666 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3667 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3668 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
3669 | I915_USER_INTERRUPT); | |
3670 | POSTING_READ16(IER); | |
3671 | ||
379ef82d DV |
3672 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3673 | * just to make the assert_spin_locked check happy. */ | |
3674 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
755e9019 ID |
3675 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3676 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
379ef82d DV |
3677 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
3678 | ||
c2798b19 CW |
3679 | return 0; |
3680 | } | |
3681 | ||
90a72f87 VS |
3682 | /* |
3683 | * Returns true when a page flip has completed. | |
3684 | */ | |
3685 | static bool i8xx_handle_vblank(struct drm_device *dev, | |
1f1c2e24 | 3686 | int plane, int pipe, u32 iir) |
90a72f87 | 3687 | { |
2d1013dd | 3688 | struct drm_i915_private *dev_priv = dev->dev_private; |
1f1c2e24 | 3689 | u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
90a72f87 | 3690 | |
8d7849db | 3691 | if (!intel_pipe_handle_vblank(dev, pipe)) |
90a72f87 VS |
3692 | return false; |
3693 | ||
3694 | if ((iir & flip_pending) == 0) | |
3695 | return false; | |
3696 | ||
1f1c2e24 | 3697 | intel_prepare_page_flip(dev, plane); |
90a72f87 VS |
3698 | |
3699 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
3700 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3701 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3702 | * the flip is completed (no longer pending). Since this doesn't raise | |
3703 | * an interrupt per se, we watch for the change at vblank. | |
3704 | */ | |
3705 | if (I915_READ16(ISR) & flip_pending) | |
3706 | return false; | |
3707 | ||
3708 | intel_finish_page_flip(dev, pipe); | |
3709 | ||
3710 | return true; | |
3711 | } | |
3712 | ||
ff1f525e | 3713 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
c2798b19 | 3714 | { |
45a83f84 | 3715 | struct drm_device *dev = arg; |
2d1013dd | 3716 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
3717 | u16 iir, new_iir; |
3718 | u32 pipe_stats[2]; | |
3719 | unsigned long irqflags; | |
c2798b19 CW |
3720 | int pipe; |
3721 | u16 flip_mask = | |
3722 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3723 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
3724 | ||
c2798b19 CW |
3725 | iir = I915_READ16(IIR); |
3726 | if (iir == 0) | |
3727 | return IRQ_NONE; | |
3728 | ||
3729 | while (iir & ~flip_mask) { | |
3730 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3731 | * have been cleared after the pipestat interrupt was received. | |
3732 | * It doesn't set the bit in iir again, but it still produces | |
3733 | * interrupts (for non-MSI). | |
3734 | */ | |
3735 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3736 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
58174462 MK |
3737 | i915_handle_error(dev, false, |
3738 | "Command parser error, iir 0x%08x", | |
3739 | iir); | |
c2798b19 CW |
3740 | |
3741 | for_each_pipe(pipe) { | |
3742 | int reg = PIPESTAT(pipe); | |
3743 | pipe_stats[pipe] = I915_READ(reg); | |
3744 | ||
3745 | /* | |
3746 | * Clear the PIPE*STAT regs before the IIR | |
3747 | */ | |
2d9d2b0b | 3748 | if (pipe_stats[pipe] & 0x8000ffff) |
c2798b19 | 3749 | I915_WRITE(reg, pipe_stats[pipe]); |
c2798b19 CW |
3750 | } |
3751 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3752 | ||
3753 | I915_WRITE16(IIR, iir & ~flip_mask); | |
3754 | new_iir = I915_READ16(IIR); /* Flush posted writes */ | |
3755 | ||
d05c617e | 3756 | i915_update_dri1_breadcrumb(dev); |
c2798b19 CW |
3757 | |
3758 | if (iir & I915_USER_INTERRUPT) | |
3759 | notify_ring(dev, &dev_priv->ring[RCS]); | |
3760 | ||
4356d586 | 3761 | for_each_pipe(pipe) { |
1f1c2e24 | 3762 | int plane = pipe; |
3a77c4c4 | 3763 | if (HAS_FBC(dev)) |
1f1c2e24 VS |
3764 | plane = !plane; |
3765 | ||
4356d586 | 3766 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
1f1c2e24 VS |
3767 | i8xx_handle_vblank(dev, plane, pipe, iir)) |
3768 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
c2798b19 | 3769 | |
4356d586 | 3770 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
277de95e | 3771 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b VS |
3772 | |
3773 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && | |
3774 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
fc2c807b | 3775 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); |
4356d586 | 3776 | } |
c2798b19 CW |
3777 | |
3778 | iir = new_iir; | |
3779 | } | |
3780 | ||
3781 | return IRQ_HANDLED; | |
3782 | } | |
3783 | ||
3784 | static void i8xx_irq_uninstall(struct drm_device * dev) | |
3785 | { | |
2d1013dd | 3786 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
3787 | int pipe; |
3788 | ||
c2798b19 CW |
3789 | for_each_pipe(pipe) { |
3790 | /* Clear enable bits; then clear status bits */ | |
3791 | I915_WRITE(PIPESTAT(pipe), 0); | |
3792 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); | |
3793 | } | |
3794 | I915_WRITE16(IMR, 0xffff); | |
3795 | I915_WRITE16(IER, 0x0); | |
3796 | I915_WRITE16(IIR, I915_READ16(IIR)); | |
3797 | } | |
3798 | ||
a266c7d5 CW |
3799 | static void i915_irq_preinstall(struct drm_device * dev) |
3800 | { | |
2d1013dd | 3801 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3802 | int pipe; |
3803 | ||
a266c7d5 CW |
3804 | if (I915_HAS_HOTPLUG(dev)) { |
3805 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3806 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3807 | } | |
3808 | ||
00d98ebd | 3809 | I915_WRITE16(HWSTAM, 0xeffe); |
a266c7d5 CW |
3810 | for_each_pipe(pipe) |
3811 | I915_WRITE(PIPESTAT(pipe), 0); | |
3812 | I915_WRITE(IMR, 0xffffffff); | |
3813 | I915_WRITE(IER, 0x0); | |
3814 | POSTING_READ(IER); | |
3815 | } | |
3816 | ||
3817 | static int i915_irq_postinstall(struct drm_device *dev) | |
3818 | { | |
2d1013dd | 3819 | struct drm_i915_private *dev_priv = dev->dev_private; |
38bde180 | 3820 | u32 enable_mask; |
379ef82d | 3821 | unsigned long irqflags; |
a266c7d5 | 3822 | |
38bde180 CW |
3823 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
3824 | ||
3825 | /* Unmask the interrupts that we always want on. */ | |
3826 | dev_priv->irq_mask = | |
3827 | ~(I915_ASLE_INTERRUPT | | |
3828 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3829 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3830 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3831 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3832 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3833 | ||
3834 | enable_mask = | |
3835 | I915_ASLE_INTERRUPT | | |
3836 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3837 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3838 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
3839 | I915_USER_INTERRUPT; | |
3840 | ||
a266c7d5 | 3841 | if (I915_HAS_HOTPLUG(dev)) { |
20afbda2 DV |
3842 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3843 | POSTING_READ(PORT_HOTPLUG_EN); | |
3844 | ||
a266c7d5 CW |
3845 | /* Enable in IER... */ |
3846 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
3847 | /* and unmask in IMR */ | |
3848 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; | |
3849 | } | |
3850 | ||
a266c7d5 CW |
3851 | I915_WRITE(IMR, dev_priv->irq_mask); |
3852 | I915_WRITE(IER, enable_mask); | |
3853 | POSTING_READ(IER); | |
3854 | ||
f49e38dd | 3855 | i915_enable_asle_pipestat(dev); |
20afbda2 | 3856 | |
379ef82d DV |
3857 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3858 | * just to make the assert_spin_locked check happy. */ | |
3859 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
755e9019 ID |
3860 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3861 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
379ef82d DV |
3862 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
3863 | ||
20afbda2 DV |
3864 | return 0; |
3865 | } | |
3866 | ||
90a72f87 VS |
3867 | /* |
3868 | * Returns true when a page flip has completed. | |
3869 | */ | |
3870 | static bool i915_handle_vblank(struct drm_device *dev, | |
3871 | int plane, int pipe, u32 iir) | |
3872 | { | |
2d1013dd | 3873 | struct drm_i915_private *dev_priv = dev->dev_private; |
90a72f87 VS |
3874 | u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
3875 | ||
8d7849db | 3876 | if (!intel_pipe_handle_vblank(dev, pipe)) |
90a72f87 VS |
3877 | return false; |
3878 | ||
3879 | if ((iir & flip_pending) == 0) | |
3880 | return false; | |
3881 | ||
3882 | intel_prepare_page_flip(dev, plane); | |
3883 | ||
3884 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
3885 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3886 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3887 | * the flip is completed (no longer pending). Since this doesn't raise | |
3888 | * an interrupt per se, we watch for the change at vblank. | |
3889 | */ | |
3890 | if (I915_READ(ISR) & flip_pending) | |
3891 | return false; | |
3892 | ||
3893 | intel_finish_page_flip(dev, pipe); | |
3894 | ||
3895 | return true; | |
3896 | } | |
3897 | ||
ff1f525e | 3898 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
a266c7d5 | 3899 | { |
45a83f84 | 3900 | struct drm_device *dev = arg; |
2d1013dd | 3901 | struct drm_i915_private *dev_priv = dev->dev_private; |
8291ee90 | 3902 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
a266c7d5 | 3903 | unsigned long irqflags; |
38bde180 CW |
3904 | u32 flip_mask = |
3905 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3906 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
38bde180 | 3907 | int pipe, ret = IRQ_NONE; |
a266c7d5 | 3908 | |
a266c7d5 | 3909 | iir = I915_READ(IIR); |
38bde180 CW |
3910 | do { |
3911 | bool irq_received = (iir & ~flip_mask) != 0; | |
8291ee90 | 3912 | bool blc_event = false; |
a266c7d5 CW |
3913 | |
3914 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3915 | * have been cleared after the pipestat interrupt was received. | |
3916 | * It doesn't set the bit in iir again, but it still produces | |
3917 | * interrupts (for non-MSI). | |
3918 | */ | |
3919 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3920 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
58174462 MK |
3921 | i915_handle_error(dev, false, |
3922 | "Command parser error, iir 0x%08x", | |
3923 | iir); | |
a266c7d5 CW |
3924 | |
3925 | for_each_pipe(pipe) { | |
3926 | int reg = PIPESTAT(pipe); | |
3927 | pipe_stats[pipe] = I915_READ(reg); | |
3928 | ||
38bde180 | 3929 | /* Clear the PIPE*STAT regs before the IIR */ |
a266c7d5 | 3930 | if (pipe_stats[pipe] & 0x8000ffff) { |
a266c7d5 | 3931 | I915_WRITE(reg, pipe_stats[pipe]); |
38bde180 | 3932 | irq_received = true; |
a266c7d5 CW |
3933 | } |
3934 | } | |
3935 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3936 | ||
3937 | if (!irq_received) | |
3938 | break; | |
3939 | ||
a266c7d5 | 3940 | /* Consume port. Then clear IIR or we'll miss events */ |
16c6c56b VS |
3941 | if (I915_HAS_HOTPLUG(dev) && |
3942 | iir & I915_DISPLAY_PORT_INTERRUPT) | |
3943 | i9xx_hpd_irq_handler(dev); | |
a266c7d5 | 3944 | |
38bde180 | 3945 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
3946 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
3947 | ||
a266c7d5 CW |
3948 | if (iir & I915_USER_INTERRUPT) |
3949 | notify_ring(dev, &dev_priv->ring[RCS]); | |
a266c7d5 | 3950 | |
a266c7d5 | 3951 | for_each_pipe(pipe) { |
38bde180 | 3952 | int plane = pipe; |
3a77c4c4 | 3953 | if (HAS_FBC(dev)) |
38bde180 | 3954 | plane = !plane; |
90a72f87 | 3955 | |
8291ee90 | 3956 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
3957 | i915_handle_vblank(dev, plane, pipe, iir)) |
3958 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
a266c7d5 CW |
3959 | |
3960 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
3961 | blc_event = true; | |
4356d586 DV |
3962 | |
3963 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 3964 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b VS |
3965 | |
3966 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && | |
3967 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
fc2c807b | 3968 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); |
a266c7d5 CW |
3969 | } |
3970 | ||
a266c7d5 CW |
3971 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
3972 | intel_opregion_asle_intr(dev); | |
3973 | ||
3974 | /* With MSI, interrupts are only generated when iir | |
3975 | * transitions from zero to nonzero. If another bit got | |
3976 | * set while we were handling the existing iir bits, then | |
3977 | * we would never get another interrupt. | |
3978 | * | |
3979 | * This is fine on non-MSI as well, as if we hit this path | |
3980 | * we avoid exiting the interrupt handler only to generate | |
3981 | * another one. | |
3982 | * | |
3983 | * Note that for MSI this could cause a stray interrupt report | |
3984 | * if an interrupt landed in the time between writing IIR and | |
3985 | * the posting read. This should be rare enough to never | |
3986 | * trigger the 99% of 100,000 interrupts test for disabling | |
3987 | * stray interrupts. | |
3988 | */ | |
38bde180 | 3989 | ret = IRQ_HANDLED; |
a266c7d5 | 3990 | iir = new_iir; |
38bde180 | 3991 | } while (iir & ~flip_mask); |
a266c7d5 | 3992 | |
d05c617e | 3993 | i915_update_dri1_breadcrumb(dev); |
8291ee90 | 3994 | |
a266c7d5 CW |
3995 | return ret; |
3996 | } | |
3997 | ||
3998 | static void i915_irq_uninstall(struct drm_device * dev) | |
3999 | { | |
2d1013dd | 4000 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4001 | int pipe; |
4002 | ||
3ca1cced | 4003 | intel_hpd_irq_uninstall(dev_priv); |
ac4c16c5 | 4004 | |
a266c7d5 CW |
4005 | if (I915_HAS_HOTPLUG(dev)) { |
4006 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
4007 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
4008 | } | |
4009 | ||
00d98ebd | 4010 | I915_WRITE16(HWSTAM, 0xffff); |
55b39755 CW |
4011 | for_each_pipe(pipe) { |
4012 | /* Clear enable bits; then clear status bits */ | |
a266c7d5 | 4013 | I915_WRITE(PIPESTAT(pipe), 0); |
55b39755 CW |
4014 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
4015 | } | |
a266c7d5 CW |
4016 | I915_WRITE(IMR, 0xffffffff); |
4017 | I915_WRITE(IER, 0x0); | |
4018 | ||
a266c7d5 CW |
4019 | I915_WRITE(IIR, I915_READ(IIR)); |
4020 | } | |
4021 | ||
4022 | static void i965_irq_preinstall(struct drm_device * dev) | |
4023 | { | |
2d1013dd | 4024 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4025 | int pipe; |
4026 | ||
adca4730 CW |
4027 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
4028 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
4029 | |
4030 | I915_WRITE(HWSTAM, 0xeffe); | |
4031 | for_each_pipe(pipe) | |
4032 | I915_WRITE(PIPESTAT(pipe), 0); | |
4033 | I915_WRITE(IMR, 0xffffffff); | |
4034 | I915_WRITE(IER, 0x0); | |
4035 | POSTING_READ(IER); | |
4036 | } | |
4037 | ||
4038 | static int i965_irq_postinstall(struct drm_device *dev) | |
4039 | { | |
2d1013dd | 4040 | struct drm_i915_private *dev_priv = dev->dev_private; |
bbba0a97 | 4041 | u32 enable_mask; |
a266c7d5 | 4042 | u32 error_mask; |
b79480ba | 4043 | unsigned long irqflags; |
a266c7d5 | 4044 | |
a266c7d5 | 4045 | /* Unmask the interrupts that we always want on. */ |
bbba0a97 | 4046 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
adca4730 | 4047 | I915_DISPLAY_PORT_INTERRUPT | |
bbba0a97 CW |
4048 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
4049 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
4050 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4051 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
4052 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
4053 | ||
4054 | enable_mask = ~dev_priv->irq_mask; | |
21ad8330 VS |
4055 | enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
4056 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); | |
bbba0a97 CW |
4057 | enable_mask |= I915_USER_INTERRUPT; |
4058 | ||
4059 | if (IS_G4X(dev)) | |
4060 | enable_mask |= I915_BSD_USER_INTERRUPT; | |
a266c7d5 | 4061 | |
b79480ba DV |
4062 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
4063 | * just to make the assert_spin_locked check happy. */ | |
4064 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
755e9019 ID |
4065 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
4066 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
4067 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
b79480ba | 4068 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
a266c7d5 | 4069 | |
a266c7d5 CW |
4070 | /* |
4071 | * Enable some error detection, note the instruction error mask | |
4072 | * bit is reserved, so we leave it masked. | |
4073 | */ | |
4074 | if (IS_G4X(dev)) { | |
4075 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
4076 | GM45_ERROR_MEM_PRIV | | |
4077 | GM45_ERROR_CP_PRIV | | |
4078 | I915_ERROR_MEMORY_REFRESH); | |
4079 | } else { | |
4080 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
4081 | I915_ERROR_MEMORY_REFRESH); | |
4082 | } | |
4083 | I915_WRITE(EMR, error_mask); | |
4084 | ||
4085 | I915_WRITE(IMR, dev_priv->irq_mask); | |
4086 | I915_WRITE(IER, enable_mask); | |
4087 | POSTING_READ(IER); | |
4088 | ||
20afbda2 DV |
4089 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
4090 | POSTING_READ(PORT_HOTPLUG_EN); | |
4091 | ||
f49e38dd | 4092 | i915_enable_asle_pipestat(dev); |
20afbda2 DV |
4093 | |
4094 | return 0; | |
4095 | } | |
4096 | ||
bac56d5b | 4097 | static void i915_hpd_irq_setup(struct drm_device *dev) |
20afbda2 | 4098 | { |
2d1013dd | 4099 | struct drm_i915_private *dev_priv = dev->dev_private; |
e5868a31 | 4100 | struct drm_mode_config *mode_config = &dev->mode_config; |
cd569aed | 4101 | struct intel_encoder *intel_encoder; |
20afbda2 DV |
4102 | u32 hotplug_en; |
4103 | ||
b5ea2d56 DV |
4104 | assert_spin_locked(&dev_priv->irq_lock); |
4105 | ||
bac56d5b EE |
4106 | if (I915_HAS_HOTPLUG(dev)) { |
4107 | hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
4108 | hotplug_en &= ~HOTPLUG_INT_EN_MASK; | |
4109 | /* Note HDMI and DP share hotplug bits */ | |
e5868a31 | 4110 | /* enable bits are the same for all generations */ |
cd569aed EE |
4111 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
4112 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) | |
4113 | hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin]; | |
bac56d5b EE |
4114 | /* Programming the CRT detection parameters tends |
4115 | to generate a spurious hotplug event about three | |
4116 | seconds later. So just do it once. | |
4117 | */ | |
4118 | if (IS_G4X(dev)) | |
4119 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
85fc95ba | 4120 | hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK; |
bac56d5b | 4121 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
a266c7d5 | 4122 | |
bac56d5b EE |
4123 | /* Ignore TV since it's buggy */ |
4124 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
4125 | } | |
a266c7d5 CW |
4126 | } |
4127 | ||
ff1f525e | 4128 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
a266c7d5 | 4129 | { |
45a83f84 | 4130 | struct drm_device *dev = arg; |
2d1013dd | 4131 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4132 | u32 iir, new_iir; |
4133 | u32 pipe_stats[I915_MAX_PIPES]; | |
a266c7d5 | 4134 | unsigned long irqflags; |
a266c7d5 | 4135 | int ret = IRQ_NONE, pipe; |
21ad8330 VS |
4136 | u32 flip_mask = |
4137 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4138 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
a266c7d5 | 4139 | |
a266c7d5 CW |
4140 | iir = I915_READ(IIR); |
4141 | ||
a266c7d5 | 4142 | for (;;) { |
501e01d7 | 4143 | bool irq_received = (iir & ~flip_mask) != 0; |
2c8ba29f CW |
4144 | bool blc_event = false; |
4145 | ||
a266c7d5 CW |
4146 | /* Can't rely on pipestat interrupt bit in iir as it might |
4147 | * have been cleared after the pipestat interrupt was received. | |
4148 | * It doesn't set the bit in iir again, but it still produces | |
4149 | * interrupts (for non-MSI). | |
4150 | */ | |
4151 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
4152 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
58174462 MK |
4153 | i915_handle_error(dev, false, |
4154 | "Command parser error, iir 0x%08x", | |
4155 | iir); | |
a266c7d5 CW |
4156 | |
4157 | for_each_pipe(pipe) { | |
4158 | int reg = PIPESTAT(pipe); | |
4159 | pipe_stats[pipe] = I915_READ(reg); | |
4160 | ||
4161 | /* | |
4162 | * Clear the PIPE*STAT regs before the IIR | |
4163 | */ | |
4164 | if (pipe_stats[pipe] & 0x8000ffff) { | |
a266c7d5 | 4165 | I915_WRITE(reg, pipe_stats[pipe]); |
501e01d7 | 4166 | irq_received = true; |
a266c7d5 CW |
4167 | } |
4168 | } | |
4169 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
4170 | ||
4171 | if (!irq_received) | |
4172 | break; | |
4173 | ||
4174 | ret = IRQ_HANDLED; | |
4175 | ||
4176 | /* Consume port. Then clear IIR or we'll miss events */ | |
16c6c56b VS |
4177 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
4178 | i9xx_hpd_irq_handler(dev); | |
a266c7d5 | 4179 | |
21ad8330 | 4180 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
4181 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
4182 | ||
a266c7d5 CW |
4183 | if (iir & I915_USER_INTERRUPT) |
4184 | notify_ring(dev, &dev_priv->ring[RCS]); | |
4185 | if (iir & I915_BSD_USER_INTERRUPT) | |
4186 | notify_ring(dev, &dev_priv->ring[VCS]); | |
4187 | ||
a266c7d5 | 4188 | for_each_pipe(pipe) { |
2c8ba29f | 4189 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
4190 | i915_handle_vblank(dev, pipe, pipe, iir)) |
4191 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); | |
a266c7d5 CW |
4192 | |
4193 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
4194 | blc_event = true; | |
4356d586 DV |
4195 | |
4196 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 4197 | i9xx_pipe_crc_irq_handler(dev, pipe); |
a266c7d5 | 4198 | |
2d9d2b0b VS |
4199 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && |
4200 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
fc2c807b | 4201 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); |
2d9d2b0b | 4202 | } |
a266c7d5 CW |
4203 | |
4204 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | |
4205 | intel_opregion_asle_intr(dev); | |
4206 | ||
515ac2bb DV |
4207 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
4208 | gmbus_irq_handler(dev); | |
4209 | ||
a266c7d5 CW |
4210 | /* With MSI, interrupts are only generated when iir |
4211 | * transitions from zero to nonzero. If another bit got | |
4212 | * set while we were handling the existing iir bits, then | |
4213 | * we would never get another interrupt. | |
4214 | * | |
4215 | * This is fine on non-MSI as well, as if we hit this path | |
4216 | * we avoid exiting the interrupt handler only to generate | |
4217 | * another one. | |
4218 | * | |
4219 | * Note that for MSI this could cause a stray interrupt report | |
4220 | * if an interrupt landed in the time between writing IIR and | |
4221 | * the posting read. This should be rare enough to never | |
4222 | * trigger the 99% of 100,000 interrupts test for disabling | |
4223 | * stray interrupts. | |
4224 | */ | |
4225 | iir = new_iir; | |
4226 | } | |
4227 | ||
d05c617e | 4228 | i915_update_dri1_breadcrumb(dev); |
2c8ba29f | 4229 | |
a266c7d5 CW |
4230 | return ret; |
4231 | } | |
4232 | ||
4233 | static void i965_irq_uninstall(struct drm_device * dev) | |
4234 | { | |
2d1013dd | 4235 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4236 | int pipe; |
4237 | ||
4238 | if (!dev_priv) | |
4239 | return; | |
4240 | ||
3ca1cced | 4241 | intel_hpd_irq_uninstall(dev_priv); |
ac4c16c5 | 4242 | |
adca4730 CW |
4243 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
4244 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
4245 | |
4246 | I915_WRITE(HWSTAM, 0xffffffff); | |
4247 | for_each_pipe(pipe) | |
4248 | I915_WRITE(PIPESTAT(pipe), 0); | |
4249 | I915_WRITE(IMR, 0xffffffff); | |
4250 | I915_WRITE(IER, 0x0); | |
4251 | ||
4252 | for_each_pipe(pipe) | |
4253 | I915_WRITE(PIPESTAT(pipe), | |
4254 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); | |
4255 | I915_WRITE(IIR, I915_READ(IIR)); | |
4256 | } | |
4257 | ||
3ca1cced | 4258 | static void intel_hpd_irq_reenable(unsigned long data) |
ac4c16c5 | 4259 | { |
2d1013dd | 4260 | struct drm_i915_private *dev_priv = (struct drm_i915_private *)data; |
ac4c16c5 EE |
4261 | struct drm_device *dev = dev_priv->dev; |
4262 | struct drm_mode_config *mode_config = &dev->mode_config; | |
4263 | unsigned long irqflags; | |
4264 | int i; | |
4265 | ||
4266 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
4267 | for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) { | |
4268 | struct drm_connector *connector; | |
4269 | ||
4270 | if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED) | |
4271 | continue; | |
4272 | ||
4273 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
4274 | ||
4275 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
4276 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4277 | ||
4278 | if (intel_connector->encoder->hpd_pin == i) { | |
4279 | if (connector->polled != intel_connector->polled) | |
4280 | DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n", | |
4281 | drm_get_connector_name(connector)); | |
4282 | connector->polled = intel_connector->polled; | |
4283 | if (!connector->polled) | |
4284 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
4285 | } | |
4286 | } | |
4287 | } | |
4288 | if (dev_priv->display.hpd_irq_setup) | |
4289 | dev_priv->display.hpd_irq_setup(dev); | |
4290 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
4291 | } | |
4292 | ||
f71d4af4 JB |
4293 | void intel_irq_init(struct drm_device *dev) |
4294 | { | |
8b2e326d CW |
4295 | struct drm_i915_private *dev_priv = dev->dev_private; |
4296 | ||
4297 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); | |
99584db3 | 4298 | INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func); |
c6a828d3 | 4299 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
a4da4fa4 | 4300 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
8b2e326d | 4301 | |
a6706b45 D |
4302 | /* Let's track the enabled rps events */ |
4303 | dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; | |
4304 | ||
99584db3 DV |
4305 | setup_timer(&dev_priv->gpu_error.hangcheck_timer, |
4306 | i915_hangcheck_elapsed, | |
61bac78e | 4307 | (unsigned long) dev); |
3ca1cced | 4308 | setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable, |
ac4c16c5 | 4309 | (unsigned long) dev_priv); |
61bac78e | 4310 | |
97a19a24 | 4311 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); |
9ee32fea | 4312 | |
4cdb83ec VS |
4313 | if (IS_GEN2(dev)) { |
4314 | dev->max_vblank_count = 0; | |
4315 | dev->driver->get_vblank_counter = i8xx_get_vblank_counter; | |
4316 | } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { | |
f71d4af4 JB |
4317 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
4318 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; | |
391f75e2 VS |
4319 | } else { |
4320 | dev->driver->get_vblank_counter = i915_get_vblank_counter; | |
4321 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
f71d4af4 JB |
4322 | } |
4323 | ||
c2baf4b7 | 4324 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
c3613de9 | 4325 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; |
c2baf4b7 VS |
4326 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; |
4327 | } | |
f71d4af4 | 4328 | |
43f328d7 VS |
4329 | if (IS_CHERRYVIEW(dev)) { |
4330 | dev->driver->irq_handler = cherryview_irq_handler; | |
4331 | dev->driver->irq_preinstall = cherryview_irq_preinstall; | |
4332 | dev->driver->irq_postinstall = cherryview_irq_postinstall; | |
4333 | dev->driver->irq_uninstall = cherryview_irq_uninstall; | |
4334 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4335 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
4336 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; | |
4337 | } else if (IS_VALLEYVIEW(dev)) { | |
7e231dbe JB |
4338 | dev->driver->irq_handler = valleyview_irq_handler; |
4339 | dev->driver->irq_preinstall = valleyview_irq_preinstall; | |
4340 | dev->driver->irq_postinstall = valleyview_irq_postinstall; | |
4341 | dev->driver->irq_uninstall = valleyview_irq_uninstall; | |
4342 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4343 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
fa00abe0 | 4344 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
abd58f01 BW |
4345 | } else if (IS_GEN8(dev)) { |
4346 | dev->driver->irq_handler = gen8_irq_handler; | |
4347 | dev->driver->irq_preinstall = gen8_irq_preinstall; | |
4348 | dev->driver->irq_postinstall = gen8_irq_postinstall; | |
4349 | dev->driver->irq_uninstall = gen8_irq_uninstall; | |
4350 | dev->driver->enable_vblank = gen8_enable_vblank; | |
4351 | dev->driver->disable_vblank = gen8_disable_vblank; | |
4352 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; | |
f71d4af4 JB |
4353 | } else if (HAS_PCH_SPLIT(dev)) { |
4354 | dev->driver->irq_handler = ironlake_irq_handler; | |
4355 | dev->driver->irq_preinstall = ironlake_irq_preinstall; | |
4356 | dev->driver->irq_postinstall = ironlake_irq_postinstall; | |
4357 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
4358 | dev->driver->enable_vblank = ironlake_enable_vblank; | |
4359 | dev->driver->disable_vblank = ironlake_disable_vblank; | |
82a28bcf | 4360 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; |
f71d4af4 | 4361 | } else { |
c2798b19 CW |
4362 | if (INTEL_INFO(dev)->gen == 2) { |
4363 | dev->driver->irq_preinstall = i8xx_irq_preinstall; | |
4364 | dev->driver->irq_postinstall = i8xx_irq_postinstall; | |
4365 | dev->driver->irq_handler = i8xx_irq_handler; | |
4366 | dev->driver->irq_uninstall = i8xx_irq_uninstall; | |
a266c7d5 CW |
4367 | } else if (INTEL_INFO(dev)->gen == 3) { |
4368 | dev->driver->irq_preinstall = i915_irq_preinstall; | |
4369 | dev->driver->irq_postinstall = i915_irq_postinstall; | |
4370 | dev->driver->irq_uninstall = i915_irq_uninstall; | |
4371 | dev->driver->irq_handler = i915_irq_handler; | |
20afbda2 | 4372 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
c2798b19 | 4373 | } else { |
a266c7d5 CW |
4374 | dev->driver->irq_preinstall = i965_irq_preinstall; |
4375 | dev->driver->irq_postinstall = i965_irq_postinstall; | |
4376 | dev->driver->irq_uninstall = i965_irq_uninstall; | |
4377 | dev->driver->irq_handler = i965_irq_handler; | |
bac56d5b | 4378 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
c2798b19 | 4379 | } |
f71d4af4 JB |
4380 | dev->driver->enable_vblank = i915_enable_vblank; |
4381 | dev->driver->disable_vblank = i915_disable_vblank; | |
4382 | } | |
4383 | } | |
20afbda2 DV |
4384 | |
4385 | void intel_hpd_init(struct drm_device *dev) | |
4386 | { | |
4387 | struct drm_i915_private *dev_priv = dev->dev_private; | |
821450c6 EE |
4388 | struct drm_mode_config *mode_config = &dev->mode_config; |
4389 | struct drm_connector *connector; | |
b5ea2d56 | 4390 | unsigned long irqflags; |
821450c6 | 4391 | int i; |
20afbda2 | 4392 | |
821450c6 EE |
4393 | for (i = 1; i < HPD_NUM_PINS; i++) { |
4394 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
4395 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
4396 | } | |
4397 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
4398 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4399 | connector->polled = intel_connector->polled; | |
4400 | if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE) | |
4401 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
4402 | } | |
b5ea2d56 DV |
4403 | |
4404 | /* Interrupt setup is already guaranteed to be single-threaded, this is | |
4405 | * just to make the assert_spin_locked checks happy. */ | |
4406 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
20afbda2 DV |
4407 | if (dev_priv->display.hpd_irq_setup) |
4408 | dev_priv->display.hpd_irq_setup(dev); | |
b5ea2d56 | 4409 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
20afbda2 | 4410 | } |
c67a470b | 4411 | |
5d584b2e | 4412 | /* Disable interrupts so we can allow runtime PM. */ |
730488b2 | 4413 | void intel_runtime_pm_disable_interrupts(struct drm_device *dev) |
c67a470b PZ |
4414 | { |
4415 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c67a470b | 4416 | |
730488b2 | 4417 | dev->driver->irq_uninstall(dev); |
5d584b2e | 4418 | dev_priv->pm.irqs_disabled = true; |
c67a470b PZ |
4419 | } |
4420 | ||
5d584b2e | 4421 | /* Restore interrupts so we can recover from runtime PM. */ |
730488b2 | 4422 | void intel_runtime_pm_restore_interrupts(struct drm_device *dev) |
c67a470b PZ |
4423 | { |
4424 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c67a470b | 4425 | |
5d584b2e | 4426 | dev_priv->pm.irqs_disabled = false; |
730488b2 PZ |
4427 | dev->driver->irq_preinstall(dev); |
4428 | dev->driver->irq_postinstall(dev); | |
c67a470b | 4429 | } |