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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
63eeaf38 | 31 | #include <linux/sysrq.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
b2c88f5b | 33 | #include <linux/circ_buf.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/i915_drm.h> | |
1da177e4 | 36 | #include "i915_drv.h" |
1c5d22f7 | 37 | #include "i915_trace.h" |
79e53945 | 38 | #include "intel_drv.h" |
1da177e4 | 39 | |
fca52a55 DV |
40 | /** |
41 | * DOC: interrupt handling | |
42 | * | |
43 | * These functions provide the basic support for enabling and disabling the | |
44 | * interrupt handling support. There's a lot more functionality in i915_irq.c | |
45 | * and related files, but that will be described in separate chapters. | |
46 | */ | |
47 | ||
e4ce95aa VS |
48 | static const u32 hpd_ilk[HPD_NUM_PINS] = { |
49 | [HPD_PORT_A] = DE_DP_A_HOTPLUG, | |
50 | }; | |
51 | ||
23bb4cb5 VS |
52 | static const u32 hpd_ivb[HPD_NUM_PINS] = { |
53 | [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB, | |
54 | }; | |
55 | ||
3a3b3c7d VS |
56 | static const u32 hpd_bdw[HPD_NUM_PINS] = { |
57 | [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG, | |
58 | }; | |
59 | ||
7c7e10db | 60 | static const u32 hpd_ibx[HPD_NUM_PINS] = { |
e5868a31 EE |
61 | [HPD_CRT] = SDE_CRT_HOTPLUG, |
62 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, | |
63 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG, | |
64 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG, | |
65 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG | |
66 | }; | |
67 | ||
7c7e10db | 68 | static const u32 hpd_cpt[HPD_NUM_PINS] = { |
e5868a31 | 69 | [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, |
73c352a2 | 70 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, |
e5868a31 EE |
71 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
72 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
73 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT | |
74 | }; | |
75 | ||
26951caf | 76 | static const u32 hpd_spt[HPD_NUM_PINS] = { |
74c0b395 | 77 | [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT, |
26951caf XZ |
78 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
79 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
80 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT, | |
81 | [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT | |
82 | }; | |
83 | ||
7c7e10db | 84 | static const u32 hpd_mask_i915[HPD_NUM_PINS] = { |
e5868a31 EE |
85 | [HPD_CRT] = CRT_HOTPLUG_INT_EN, |
86 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, | |
87 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, | |
88 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, | |
89 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, | |
90 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN | |
91 | }; | |
92 | ||
7c7e10db | 93 | static const u32 hpd_status_g4x[HPD_NUM_PINS] = { |
e5868a31 EE |
94 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
95 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, | |
96 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, | |
97 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
98 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
99 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
100 | }; | |
101 | ||
4bca26d0 | 102 | static const u32 hpd_status_i915[HPD_NUM_PINS] = { |
e5868a31 EE |
103 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
104 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, | |
105 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, | |
106 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
107 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
108 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
109 | }; | |
110 | ||
e0a20ad7 SS |
111 | /* BXT hpd list */ |
112 | static const u32 hpd_bxt[HPD_NUM_PINS] = { | |
7f3561be | 113 | [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA, |
e0a20ad7 SS |
114 | [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB, |
115 | [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC | |
116 | }; | |
117 | ||
5c502442 | 118 | /* IIR can theoretically queue up two events. Be paranoid. */ |
f86f3fb0 | 119 | #define GEN8_IRQ_RESET_NDX(type, which) do { \ |
5c502442 PZ |
120 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ |
121 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
122 | I915_WRITE(GEN8_##type##_IER(which), 0); \ | |
123 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
124 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
125 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
126 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
127 | } while (0) | |
128 | ||
f86f3fb0 | 129 | #define GEN5_IRQ_RESET(type) do { \ |
a9d356a6 | 130 | I915_WRITE(type##IMR, 0xffffffff); \ |
5c502442 | 131 | POSTING_READ(type##IMR); \ |
a9d356a6 | 132 | I915_WRITE(type##IER, 0); \ |
5c502442 PZ |
133 | I915_WRITE(type##IIR, 0xffffffff); \ |
134 | POSTING_READ(type##IIR); \ | |
135 | I915_WRITE(type##IIR, 0xffffffff); \ | |
136 | POSTING_READ(type##IIR); \ | |
a9d356a6 PZ |
137 | } while (0) |
138 | ||
337ba017 PZ |
139 | /* |
140 | * We should clear IMR at preinstall/uninstall, and just check at postinstall. | |
141 | */ | |
f0f59a00 VS |
142 | static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv, |
143 | i915_reg_t reg) | |
b51a2842 VS |
144 | { |
145 | u32 val = I915_READ(reg); | |
146 | ||
147 | if (val == 0) | |
148 | return; | |
149 | ||
150 | WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", | |
f0f59a00 | 151 | i915_mmio_reg_offset(reg), val); |
b51a2842 VS |
152 | I915_WRITE(reg, 0xffffffff); |
153 | POSTING_READ(reg); | |
154 | I915_WRITE(reg, 0xffffffff); | |
155 | POSTING_READ(reg); | |
156 | } | |
337ba017 | 157 | |
35079899 | 158 | #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \ |
b51a2842 | 159 | gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \ |
35079899 | 160 | I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \ |
7d1bd539 VS |
161 | I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \ |
162 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
35079899 PZ |
163 | } while (0) |
164 | ||
165 | #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \ | |
b51a2842 | 166 | gen5_assert_iir_is_zero(dev_priv, type##IIR); \ |
35079899 | 167 | I915_WRITE(type##IER, (ier_val)); \ |
7d1bd539 VS |
168 | I915_WRITE(type##IMR, (imr_val)); \ |
169 | POSTING_READ(type##IMR); \ | |
35079899 PZ |
170 | } while (0) |
171 | ||
c9a9a268 | 172 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir); |
26705e20 | 173 | static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir); |
c9a9a268 | 174 | |
0706f17c EE |
175 | /* For display hotplug interrupt */ |
176 | static inline void | |
177 | i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv, | |
178 | uint32_t mask, | |
179 | uint32_t bits) | |
180 | { | |
181 | uint32_t val; | |
182 | ||
67520415 | 183 | lockdep_assert_held(&dev_priv->irq_lock); |
0706f17c EE |
184 | WARN_ON(bits & ~mask); |
185 | ||
186 | val = I915_READ(PORT_HOTPLUG_EN); | |
187 | val &= ~mask; | |
188 | val |= bits; | |
189 | I915_WRITE(PORT_HOTPLUG_EN, val); | |
190 | } | |
191 | ||
192 | /** | |
193 | * i915_hotplug_interrupt_update - update hotplug interrupt enable | |
194 | * @dev_priv: driver private | |
195 | * @mask: bits to update | |
196 | * @bits: bits to enable | |
197 | * NOTE: the HPD enable bits are modified both inside and outside | |
198 | * of an interrupt context. To avoid that read-modify-write cycles | |
199 | * interfer, these bits are protected by a spinlock. Since this | |
200 | * function is usually not called from a context where the lock is | |
201 | * held already, this function acquires the lock itself. A non-locking | |
202 | * version is also available. | |
203 | */ | |
204 | void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, | |
205 | uint32_t mask, | |
206 | uint32_t bits) | |
207 | { | |
208 | spin_lock_irq(&dev_priv->irq_lock); | |
209 | i915_hotplug_interrupt_update_locked(dev_priv, mask, bits); | |
210 | spin_unlock_irq(&dev_priv->irq_lock); | |
211 | } | |
212 | ||
d9dc34f1 VS |
213 | /** |
214 | * ilk_update_display_irq - update DEIMR | |
215 | * @dev_priv: driver private | |
216 | * @interrupt_mask: mask of interrupt bits to update | |
217 | * @enabled_irq_mask: mask of interrupt bits to enable | |
218 | */ | |
fbdedaea VS |
219 | void ilk_update_display_irq(struct drm_i915_private *dev_priv, |
220 | uint32_t interrupt_mask, | |
221 | uint32_t enabled_irq_mask) | |
036a4a7d | 222 | { |
d9dc34f1 VS |
223 | uint32_t new_val; |
224 | ||
67520415 | 225 | lockdep_assert_held(&dev_priv->irq_lock); |
4bc9d430 | 226 | |
d9dc34f1 VS |
227 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
228 | ||
9df7575f | 229 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 230 | return; |
c67a470b | 231 | |
d9dc34f1 VS |
232 | new_val = dev_priv->irq_mask; |
233 | new_val &= ~interrupt_mask; | |
234 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
235 | ||
236 | if (new_val != dev_priv->irq_mask) { | |
237 | dev_priv->irq_mask = new_val; | |
1ec14ad3 | 238 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
3143a2bf | 239 | POSTING_READ(DEIMR); |
036a4a7d ZW |
240 | } |
241 | } | |
242 | ||
43eaea13 PZ |
243 | /** |
244 | * ilk_update_gt_irq - update GTIMR | |
245 | * @dev_priv: driver private | |
246 | * @interrupt_mask: mask of interrupt bits to update | |
247 | * @enabled_irq_mask: mask of interrupt bits to enable | |
248 | */ | |
249 | static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, | |
250 | uint32_t interrupt_mask, | |
251 | uint32_t enabled_irq_mask) | |
252 | { | |
67520415 | 253 | lockdep_assert_held(&dev_priv->irq_lock); |
43eaea13 | 254 | |
15a17aae DV |
255 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
256 | ||
9df7575f | 257 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 258 | return; |
c67a470b | 259 | |
43eaea13 PZ |
260 | dev_priv->gt_irq_mask &= ~interrupt_mask; |
261 | dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); | |
262 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
43eaea13 PZ |
263 | } |
264 | ||
480c8033 | 265 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
43eaea13 PZ |
266 | { |
267 | ilk_update_gt_irq(dev_priv, mask, mask); | |
31bb59cc | 268 | POSTING_READ_FW(GTIMR); |
43eaea13 PZ |
269 | } |
270 | ||
480c8033 | 271 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
43eaea13 PZ |
272 | { |
273 | ilk_update_gt_irq(dev_priv, mask, 0); | |
274 | } | |
275 | ||
f0f59a00 | 276 | static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv) |
b900b949 ID |
277 | { |
278 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; | |
279 | } | |
280 | ||
f0f59a00 | 281 | static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv) |
a72fbc3a ID |
282 | { |
283 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR; | |
284 | } | |
285 | ||
f0f59a00 | 286 | static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv) |
b900b949 ID |
287 | { |
288 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER; | |
289 | } | |
290 | ||
edbfdb45 | 291 | /** |
81fd874e VS |
292 | * snb_update_pm_irq - update GEN6_PMIMR |
293 | * @dev_priv: driver private | |
294 | * @interrupt_mask: mask of interrupt bits to update | |
295 | * @enabled_irq_mask: mask of interrupt bits to enable | |
296 | */ | |
edbfdb45 PZ |
297 | static void snb_update_pm_irq(struct drm_i915_private *dev_priv, |
298 | uint32_t interrupt_mask, | |
299 | uint32_t enabled_irq_mask) | |
300 | { | |
605cd25b | 301 | uint32_t new_val; |
edbfdb45 | 302 | |
15a17aae DV |
303 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
304 | ||
67520415 | 305 | lockdep_assert_held(&dev_priv->irq_lock); |
edbfdb45 | 306 | |
f4e9af4f | 307 | new_val = dev_priv->pm_imr; |
f52ecbcf PZ |
308 | new_val &= ~interrupt_mask; |
309 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
310 | ||
f4e9af4f AG |
311 | if (new_val != dev_priv->pm_imr) { |
312 | dev_priv->pm_imr = new_val; | |
313 | I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_imr); | |
a72fbc3a | 314 | POSTING_READ(gen6_pm_imr(dev_priv)); |
f52ecbcf | 315 | } |
edbfdb45 PZ |
316 | } |
317 | ||
f4e9af4f | 318 | void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask) |
edbfdb45 | 319 | { |
9939fba2 ID |
320 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
321 | return; | |
322 | ||
edbfdb45 PZ |
323 | snb_update_pm_irq(dev_priv, mask, mask); |
324 | } | |
325 | ||
f4e9af4f | 326 | static void __gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask) |
edbfdb45 PZ |
327 | { |
328 | snb_update_pm_irq(dev_priv, mask, 0); | |
329 | } | |
330 | ||
f4e9af4f | 331 | void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask) |
9939fba2 ID |
332 | { |
333 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) | |
334 | return; | |
335 | ||
f4e9af4f | 336 | __gen6_mask_pm_irq(dev_priv, mask); |
9939fba2 ID |
337 | } |
338 | ||
f4e9af4f | 339 | void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask) |
3cc134e3 | 340 | { |
f0f59a00 | 341 | i915_reg_t reg = gen6_pm_iir(dev_priv); |
3cc134e3 | 342 | |
67520415 | 343 | lockdep_assert_held(&dev_priv->irq_lock); |
f4e9af4f AG |
344 | |
345 | I915_WRITE(reg, reset_mask); | |
346 | I915_WRITE(reg, reset_mask); | |
3cc134e3 | 347 | POSTING_READ(reg); |
f4e9af4f AG |
348 | } |
349 | ||
350 | void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask) | |
351 | { | |
67520415 | 352 | lockdep_assert_held(&dev_priv->irq_lock); |
f4e9af4f AG |
353 | |
354 | dev_priv->pm_ier |= enable_mask; | |
355 | I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier); | |
356 | gen6_unmask_pm_irq(dev_priv, enable_mask); | |
357 | /* unmask_pm_irq provides an implicit barrier (POSTING_READ) */ | |
358 | } | |
359 | ||
360 | void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask) | |
361 | { | |
67520415 | 362 | lockdep_assert_held(&dev_priv->irq_lock); |
f4e9af4f AG |
363 | |
364 | dev_priv->pm_ier &= ~disable_mask; | |
365 | __gen6_mask_pm_irq(dev_priv, disable_mask); | |
366 | I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier); | |
367 | /* though a barrier is missing here, but don't really need a one */ | |
368 | } | |
369 | ||
370 | void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv) | |
371 | { | |
372 | spin_lock_irq(&dev_priv->irq_lock); | |
373 | gen6_reset_pm_iir(dev_priv, dev_priv->pm_rps_events); | |
096fad9e | 374 | dev_priv->rps.pm_iir = 0; |
3cc134e3 ID |
375 | spin_unlock_irq(&dev_priv->irq_lock); |
376 | } | |
377 | ||
91d14251 | 378 | void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv) |
b900b949 | 379 | { |
f2a91d1a CW |
380 | if (READ_ONCE(dev_priv->rps.interrupts_enabled)) |
381 | return; | |
382 | ||
b900b949 | 383 | spin_lock_irq(&dev_priv->irq_lock); |
c33d247d CW |
384 | WARN_ON_ONCE(dev_priv->rps.pm_iir); |
385 | WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events); | |
d4d70aa5 | 386 | dev_priv->rps.interrupts_enabled = true; |
b900b949 | 387 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
78e68d36 | 388 | |
b900b949 ID |
389 | spin_unlock_irq(&dev_priv->irq_lock); |
390 | } | |
391 | ||
91d14251 | 392 | void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv) |
b900b949 | 393 | { |
f2a91d1a CW |
394 | if (!READ_ONCE(dev_priv->rps.interrupts_enabled)) |
395 | return; | |
396 | ||
d4d70aa5 ID |
397 | spin_lock_irq(&dev_priv->irq_lock); |
398 | dev_priv->rps.interrupts_enabled = false; | |
9939fba2 | 399 | |
b20e3cfe | 400 | I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u)); |
9939fba2 | 401 | |
f4e9af4f | 402 | gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
58072ccb ID |
403 | |
404 | spin_unlock_irq(&dev_priv->irq_lock); | |
91c8a326 | 405 | synchronize_irq(dev_priv->drm.irq); |
c33d247d CW |
406 | |
407 | /* Now that we will not be generating any more work, flush any | |
408 | * outsanding tasks. As we are called on the RPS idle path, | |
409 | * we will reset the GPU to minimum frequencies, so the current | |
410 | * state of the worker can be discarded. | |
411 | */ | |
412 | cancel_work_sync(&dev_priv->rps.work); | |
413 | gen6_reset_rps_interrupts(dev_priv); | |
b900b949 ID |
414 | } |
415 | ||
26705e20 SAK |
416 | void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv) |
417 | { | |
418 | spin_lock_irq(&dev_priv->irq_lock); | |
419 | gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events); | |
420 | spin_unlock_irq(&dev_priv->irq_lock); | |
421 | } | |
422 | ||
423 | void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv) | |
424 | { | |
425 | spin_lock_irq(&dev_priv->irq_lock); | |
426 | if (!dev_priv->guc.interrupts_enabled) { | |
427 | WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & | |
428 | dev_priv->pm_guc_events); | |
429 | dev_priv->guc.interrupts_enabled = true; | |
430 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events); | |
431 | } | |
432 | spin_unlock_irq(&dev_priv->irq_lock); | |
433 | } | |
434 | ||
435 | void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv) | |
436 | { | |
437 | spin_lock_irq(&dev_priv->irq_lock); | |
438 | dev_priv->guc.interrupts_enabled = false; | |
439 | ||
440 | gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events); | |
441 | ||
442 | spin_unlock_irq(&dev_priv->irq_lock); | |
443 | synchronize_irq(dev_priv->drm.irq); | |
444 | ||
445 | gen9_reset_guc_interrupts(dev_priv); | |
446 | } | |
447 | ||
3a3b3c7d | 448 | /** |
81fd874e VS |
449 | * bdw_update_port_irq - update DE port interrupt |
450 | * @dev_priv: driver private | |
451 | * @interrupt_mask: mask of interrupt bits to update | |
452 | * @enabled_irq_mask: mask of interrupt bits to enable | |
453 | */ | |
3a3b3c7d VS |
454 | static void bdw_update_port_irq(struct drm_i915_private *dev_priv, |
455 | uint32_t interrupt_mask, | |
456 | uint32_t enabled_irq_mask) | |
457 | { | |
458 | uint32_t new_val; | |
459 | uint32_t old_val; | |
460 | ||
67520415 | 461 | lockdep_assert_held(&dev_priv->irq_lock); |
3a3b3c7d VS |
462 | |
463 | WARN_ON(enabled_irq_mask & ~interrupt_mask); | |
464 | ||
465 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) | |
466 | return; | |
467 | ||
468 | old_val = I915_READ(GEN8_DE_PORT_IMR); | |
469 | ||
470 | new_val = old_val; | |
471 | new_val &= ~interrupt_mask; | |
472 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
473 | ||
474 | if (new_val != old_val) { | |
475 | I915_WRITE(GEN8_DE_PORT_IMR, new_val); | |
476 | POSTING_READ(GEN8_DE_PORT_IMR); | |
477 | } | |
478 | } | |
479 | ||
013d3752 VS |
480 | /** |
481 | * bdw_update_pipe_irq - update DE pipe interrupt | |
482 | * @dev_priv: driver private | |
483 | * @pipe: pipe whose interrupt to update | |
484 | * @interrupt_mask: mask of interrupt bits to update | |
485 | * @enabled_irq_mask: mask of interrupt bits to enable | |
486 | */ | |
487 | void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, | |
488 | enum pipe pipe, | |
489 | uint32_t interrupt_mask, | |
490 | uint32_t enabled_irq_mask) | |
491 | { | |
492 | uint32_t new_val; | |
493 | ||
67520415 | 494 | lockdep_assert_held(&dev_priv->irq_lock); |
013d3752 VS |
495 | |
496 | WARN_ON(enabled_irq_mask & ~interrupt_mask); | |
497 | ||
498 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) | |
499 | return; | |
500 | ||
501 | new_val = dev_priv->de_irq_mask[pipe]; | |
502 | new_val &= ~interrupt_mask; | |
503 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
504 | ||
505 | if (new_val != dev_priv->de_irq_mask[pipe]) { | |
506 | dev_priv->de_irq_mask[pipe] = new_val; | |
507 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
508 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
509 | } | |
510 | } | |
511 | ||
fee884ed DV |
512 | /** |
513 | * ibx_display_interrupt_update - update SDEIMR | |
514 | * @dev_priv: driver private | |
515 | * @interrupt_mask: mask of interrupt bits to update | |
516 | * @enabled_irq_mask: mask of interrupt bits to enable | |
517 | */ | |
47339cd9 DV |
518 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
519 | uint32_t interrupt_mask, | |
520 | uint32_t enabled_irq_mask) | |
fee884ed DV |
521 | { |
522 | uint32_t sdeimr = I915_READ(SDEIMR); | |
523 | sdeimr &= ~interrupt_mask; | |
524 | sdeimr |= (~enabled_irq_mask & interrupt_mask); | |
525 | ||
15a17aae DV |
526 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
527 | ||
67520415 | 528 | lockdep_assert_held(&dev_priv->irq_lock); |
fee884ed | 529 | |
9df7575f | 530 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 531 | return; |
c67a470b | 532 | |
fee884ed DV |
533 | I915_WRITE(SDEIMR, sdeimr); |
534 | POSTING_READ(SDEIMR); | |
535 | } | |
8664281b | 536 | |
b5ea642a | 537 | static void |
755e9019 ID |
538 | __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
539 | u32 enable_mask, u32 status_mask) | |
7c463586 | 540 | { |
f0f59a00 | 541 | i915_reg_t reg = PIPESTAT(pipe); |
755e9019 | 542 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 543 | |
67520415 | 544 | lockdep_assert_held(&dev_priv->irq_lock); |
d518ce50 | 545 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
b79480ba | 546 | |
04feced9 VS |
547 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
548 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
549 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
550 | pipe_name(pipe), enable_mask, status_mask)) | |
755e9019 ID |
551 | return; |
552 | ||
553 | if ((pipestat & enable_mask) == enable_mask) | |
46c06a30 VS |
554 | return; |
555 | ||
91d181dd ID |
556 | dev_priv->pipestat_irq_mask[pipe] |= status_mask; |
557 | ||
46c06a30 | 558 | /* Enable the interrupt, clear any pending status */ |
755e9019 | 559 | pipestat |= enable_mask | status_mask; |
46c06a30 VS |
560 | I915_WRITE(reg, pipestat); |
561 | POSTING_READ(reg); | |
7c463586 KP |
562 | } |
563 | ||
b5ea642a | 564 | static void |
755e9019 ID |
565 | __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
566 | u32 enable_mask, u32 status_mask) | |
7c463586 | 567 | { |
f0f59a00 | 568 | i915_reg_t reg = PIPESTAT(pipe); |
755e9019 | 569 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 570 | |
67520415 | 571 | lockdep_assert_held(&dev_priv->irq_lock); |
d518ce50 | 572 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
b79480ba | 573 | |
04feced9 VS |
574 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
575 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
576 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
577 | pipe_name(pipe), enable_mask, status_mask)) | |
46c06a30 VS |
578 | return; |
579 | ||
755e9019 ID |
580 | if ((pipestat & enable_mask) == 0) |
581 | return; | |
582 | ||
91d181dd ID |
583 | dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; |
584 | ||
755e9019 | 585 | pipestat &= ~enable_mask; |
46c06a30 VS |
586 | I915_WRITE(reg, pipestat); |
587 | POSTING_READ(reg); | |
7c463586 KP |
588 | } |
589 | ||
10c59c51 ID |
590 | static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask) |
591 | { | |
592 | u32 enable_mask = status_mask << 16; | |
593 | ||
594 | /* | |
724a6905 VS |
595 | * On pipe A we don't support the PSR interrupt yet, |
596 | * on pipe B and C the same bit MBZ. | |
10c59c51 ID |
597 | */ |
598 | if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV)) | |
599 | return 0; | |
724a6905 VS |
600 | /* |
601 | * On pipe B and C we don't support the PSR interrupt yet, on pipe | |
602 | * A the same bit is for perf counters which we don't use either. | |
603 | */ | |
604 | if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV)) | |
605 | return 0; | |
10c59c51 ID |
606 | |
607 | enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | | |
608 | SPRITE0_FLIP_DONE_INT_EN_VLV | | |
609 | SPRITE1_FLIP_DONE_INT_EN_VLV); | |
610 | if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV) | |
611 | enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV; | |
612 | if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV) | |
613 | enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; | |
614 | ||
615 | return enable_mask; | |
616 | } | |
617 | ||
755e9019 ID |
618 | void |
619 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
620 | u32 status_mask) | |
621 | { | |
622 | u32 enable_mask; | |
623 | ||
666a4537 | 624 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
91c8a326 | 625 | enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm, |
10c59c51 ID |
626 | status_mask); |
627 | else | |
628 | enable_mask = status_mask << 16; | |
755e9019 ID |
629 | __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
630 | } | |
631 | ||
632 | void | |
633 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
634 | u32 status_mask) | |
635 | { | |
636 | u32 enable_mask; | |
637 | ||
666a4537 | 638 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
91c8a326 | 639 | enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm, |
10c59c51 ID |
640 | status_mask); |
641 | else | |
642 | enable_mask = status_mask << 16; | |
755e9019 ID |
643 | __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
644 | } | |
645 | ||
01c66889 | 646 | /** |
f49e38dd | 647 | * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion |
14bb2c11 | 648 | * @dev_priv: i915 device private |
01c66889 | 649 | */ |
91d14251 | 650 | static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv) |
01c66889 | 651 | { |
91d14251 | 652 | if (!dev_priv->opregion.asle || !IS_MOBILE(dev_priv)) |
f49e38dd JN |
653 | return; |
654 | ||
13321786 | 655 | spin_lock_irq(&dev_priv->irq_lock); |
01c66889 | 656 | |
755e9019 | 657 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); |
91d14251 | 658 | if (INTEL_GEN(dev_priv) >= 4) |
3b6c42e8 | 659 | i915_enable_pipestat(dev_priv, PIPE_A, |
755e9019 | 660 | PIPE_LEGACY_BLC_EVENT_STATUS); |
1ec14ad3 | 661 | |
13321786 | 662 | spin_unlock_irq(&dev_priv->irq_lock); |
01c66889 ZY |
663 | } |
664 | ||
f75f3746 VS |
665 | /* |
666 | * This timing diagram depicts the video signal in and | |
667 | * around the vertical blanking period. | |
668 | * | |
669 | * Assumptions about the fictitious mode used in this example: | |
670 | * vblank_start >= 3 | |
671 | * vsync_start = vblank_start + 1 | |
672 | * vsync_end = vblank_start + 2 | |
673 | * vtotal = vblank_start + 3 | |
674 | * | |
675 | * start of vblank: | |
676 | * latch double buffered registers | |
677 | * increment frame counter (ctg+) | |
678 | * generate start of vblank interrupt (gen4+) | |
679 | * | | |
680 | * | frame start: | |
681 | * | generate frame start interrupt (aka. vblank interrupt) (gmch) | |
682 | * | may be shifted forward 1-3 extra lines via PIPECONF | |
683 | * | | | |
684 | * | | start of vsync: | |
685 | * | | generate vsync interrupt | |
686 | * | | | | |
687 | * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx | |
688 | * . \hs/ . \hs/ \hs/ \hs/ . \hs/ | |
689 | * ----va---> <-----------------vb--------------------> <--------va------------- | |
690 | * | | <----vs-----> | | |
691 | * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2) | |
692 | * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+) | |
693 | * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi) | |
694 | * | | | | |
695 | * last visible pixel first visible pixel | |
696 | * | increment frame counter (gen3/4) | |
697 | * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4) | |
698 | * | |
699 | * x = horizontal active | |
700 | * _ = horizontal blanking | |
701 | * hs = horizontal sync | |
702 | * va = vertical active | |
703 | * vb = vertical blanking | |
704 | * vs = vertical sync | |
705 | * vbs = vblank_start (number) | |
706 | * | |
707 | * Summary: | |
708 | * - most events happen at the start of horizontal sync | |
709 | * - frame start happens at the start of horizontal blank, 1-4 lines | |
710 | * (depending on PIPECONF settings) after the start of vblank | |
711 | * - gen3/4 pixel and frame counter are synchronized with the start | |
712 | * of horizontal active on the first line of vertical active | |
713 | */ | |
714 | ||
42f52ef8 KP |
715 | /* Called from drm generic code, passed a 'crtc', which |
716 | * we use as a pipe index | |
717 | */ | |
88e72717 | 718 | static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe) |
0a3e67a4 | 719 | { |
fac5e23e | 720 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 721 | i915_reg_t high_frame, low_frame; |
0b2a8e09 | 722 | u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal; |
98187836 VS |
723 | struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv, |
724 | pipe); | |
fc467a22 | 725 | const struct drm_display_mode *mode = &intel_crtc->base.hwmode; |
694e409d | 726 | unsigned long irqflags; |
0a3e67a4 | 727 | |
f3a5c3f6 DV |
728 | htotal = mode->crtc_htotal; |
729 | hsync_start = mode->crtc_hsync_start; | |
730 | vbl_start = mode->crtc_vblank_start; | |
731 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
732 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
391f75e2 | 733 | |
0b2a8e09 VS |
734 | /* Convert to pixel count */ |
735 | vbl_start *= htotal; | |
736 | ||
737 | /* Start of vblank event occurs at start of hsync */ | |
738 | vbl_start -= htotal - hsync_start; | |
739 | ||
9db4a9c7 JB |
740 | high_frame = PIPEFRAME(pipe); |
741 | low_frame = PIPEFRAMEPIXEL(pipe); | |
5eddb70b | 742 | |
694e409d VS |
743 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
744 | ||
0a3e67a4 JB |
745 | /* |
746 | * High & low register fields aren't synchronized, so make sure | |
747 | * we get a low value that's stable across two reads of the high | |
748 | * register. | |
749 | */ | |
750 | do { | |
694e409d VS |
751 | high1 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK; |
752 | low = I915_READ_FW(low_frame); | |
753 | high2 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK; | |
0a3e67a4 JB |
754 | } while (high1 != high2); |
755 | ||
694e409d VS |
756 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
757 | ||
5eddb70b | 758 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
391f75e2 | 759 | pixel = low & PIPE_PIXEL_MASK; |
5eddb70b | 760 | low >>= PIPE_FRAME_LOW_SHIFT; |
391f75e2 VS |
761 | |
762 | /* | |
763 | * The frame counter increments at beginning of active. | |
764 | * Cook up a vblank counter by also checking the pixel | |
765 | * counter against vblank start. | |
766 | */ | |
edc08d0a | 767 | return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; |
0a3e67a4 JB |
768 | } |
769 | ||
974e59ba | 770 | static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe) |
9880b7a5 | 771 | { |
fac5e23e | 772 | struct drm_i915_private *dev_priv = to_i915(dev); |
9880b7a5 | 773 | |
649636ef | 774 | return I915_READ(PIPE_FRMCOUNT_G4X(pipe)); |
9880b7a5 JB |
775 | } |
776 | ||
75aa3f63 | 777 | /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */ |
a225f079 VS |
778 | static int __intel_get_crtc_scanline(struct intel_crtc *crtc) |
779 | { | |
780 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 781 | struct drm_i915_private *dev_priv = to_i915(dev); |
fc467a22 | 782 | const struct drm_display_mode *mode = &crtc->base.hwmode; |
a225f079 | 783 | enum pipe pipe = crtc->pipe; |
80715b2f | 784 | int position, vtotal; |
a225f079 | 785 | |
72259536 VS |
786 | if (!crtc->active) |
787 | return -1; | |
788 | ||
80715b2f | 789 | vtotal = mode->crtc_vtotal; |
a225f079 VS |
790 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
791 | vtotal /= 2; | |
792 | ||
91d14251 | 793 | if (IS_GEN2(dev_priv)) |
75aa3f63 | 794 | position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; |
a225f079 | 795 | else |
75aa3f63 | 796 | position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; |
a225f079 | 797 | |
41b578fb JB |
798 | /* |
799 | * On HSW, the DSL reg (0x70000) appears to return 0 if we | |
800 | * read it just before the start of vblank. So try it again | |
801 | * so we don't accidentally end up spanning a vblank frame | |
802 | * increment, causing the pipe_update_end() code to squak at us. | |
803 | * | |
804 | * The nature of this problem means we can't simply check the ISR | |
805 | * bit and return the vblank start value; nor can we use the scanline | |
806 | * debug register in the transcoder as it appears to have the same | |
807 | * problem. We may need to extend this to include other platforms, | |
808 | * but so far testing only shows the problem on HSW. | |
809 | */ | |
91d14251 | 810 | if (HAS_DDI(dev_priv) && !position) { |
41b578fb JB |
811 | int i, temp; |
812 | ||
813 | for (i = 0; i < 100; i++) { | |
814 | udelay(1); | |
707bdd3f | 815 | temp = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; |
41b578fb JB |
816 | if (temp != position) { |
817 | position = temp; | |
818 | break; | |
819 | } | |
820 | } | |
821 | } | |
822 | ||
a225f079 | 823 | /* |
80715b2f VS |
824 | * See update_scanline_offset() for the details on the |
825 | * scanline_offset adjustment. | |
a225f079 | 826 | */ |
80715b2f | 827 | return (position + crtc->scanline_offset) % vtotal; |
a225f079 VS |
828 | } |
829 | ||
88e72717 | 830 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, |
abca9e45 | 831 | unsigned int flags, int *vpos, int *hpos, |
3bb403bf VS |
832 | ktime_t *stime, ktime_t *etime, |
833 | const struct drm_display_mode *mode) | |
0af7e4df | 834 | { |
fac5e23e | 835 | struct drm_i915_private *dev_priv = to_i915(dev); |
98187836 VS |
836 | struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv, |
837 | pipe); | |
3aa18df8 | 838 | int position; |
78e8fc6b | 839 | int vbl_start, vbl_end, hsync_start, htotal, vtotal; |
0af7e4df MK |
840 | bool in_vbl = true; |
841 | int ret = 0; | |
ad3543ed | 842 | unsigned long irqflags; |
0af7e4df | 843 | |
fc467a22 | 844 | if (WARN_ON(!mode->crtc_clock)) { |
0af7e4df | 845 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
9db4a9c7 | 846 | "pipe %c\n", pipe_name(pipe)); |
0af7e4df MK |
847 | return 0; |
848 | } | |
849 | ||
c2baf4b7 | 850 | htotal = mode->crtc_htotal; |
78e8fc6b | 851 | hsync_start = mode->crtc_hsync_start; |
c2baf4b7 VS |
852 | vtotal = mode->crtc_vtotal; |
853 | vbl_start = mode->crtc_vblank_start; | |
854 | vbl_end = mode->crtc_vblank_end; | |
0af7e4df | 855 | |
d31faf65 VS |
856 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
857 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
858 | vbl_end /= 2; | |
859 | vtotal /= 2; | |
860 | } | |
861 | ||
c2baf4b7 VS |
862 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; |
863 | ||
ad3543ed MK |
864 | /* |
865 | * Lock uncore.lock, as we will do multiple timing critical raw | |
866 | * register reads, potentially with preemption disabled, so the | |
867 | * following code must not block on uncore.lock. | |
868 | */ | |
869 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
78e8fc6b | 870 | |
ad3543ed MK |
871 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ |
872 | ||
873 | /* Get optional system timestamp before query. */ | |
874 | if (stime) | |
875 | *stime = ktime_get(); | |
876 | ||
91d14251 | 877 | if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { |
0af7e4df MK |
878 | /* No obvious pixelcount register. Only query vertical |
879 | * scanout position from Display scan line register. | |
880 | */ | |
a225f079 | 881 | position = __intel_get_crtc_scanline(intel_crtc); |
0af7e4df MK |
882 | } else { |
883 | /* Have access to pixelcount since start of frame. | |
884 | * We can split this into vertical and horizontal | |
885 | * scanout position. | |
886 | */ | |
75aa3f63 | 887 | position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; |
0af7e4df | 888 | |
3aa18df8 VS |
889 | /* convert to pixel counts */ |
890 | vbl_start *= htotal; | |
891 | vbl_end *= htotal; | |
892 | vtotal *= htotal; | |
78e8fc6b | 893 | |
7e78f1cb VS |
894 | /* |
895 | * In interlaced modes, the pixel counter counts all pixels, | |
896 | * so one field will have htotal more pixels. In order to avoid | |
897 | * the reported position from jumping backwards when the pixel | |
898 | * counter is beyond the length of the shorter field, just | |
899 | * clamp the position the length of the shorter field. This | |
900 | * matches how the scanline counter based position works since | |
901 | * the scanline counter doesn't count the two half lines. | |
902 | */ | |
903 | if (position >= vtotal) | |
904 | position = vtotal - 1; | |
905 | ||
78e8fc6b VS |
906 | /* |
907 | * Start of vblank interrupt is triggered at start of hsync, | |
908 | * just prior to the first active line of vblank. However we | |
909 | * consider lines to start at the leading edge of horizontal | |
910 | * active. So, should we get here before we've crossed into | |
911 | * the horizontal active of the first line in vblank, we would | |
912 | * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that, | |
913 | * always add htotal-hsync_start to the current pixel position. | |
914 | */ | |
915 | position = (position + htotal - hsync_start) % vtotal; | |
0af7e4df MK |
916 | } |
917 | ||
ad3543ed MK |
918 | /* Get optional system timestamp after query. */ |
919 | if (etime) | |
920 | *etime = ktime_get(); | |
921 | ||
922 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ | |
923 | ||
924 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
925 | ||
3aa18df8 VS |
926 | in_vbl = position >= vbl_start && position < vbl_end; |
927 | ||
928 | /* | |
929 | * While in vblank, position will be negative | |
930 | * counting up towards 0 at vbl_end. And outside | |
931 | * vblank, position will be positive counting | |
932 | * up since vbl_end. | |
933 | */ | |
934 | if (position >= vbl_start) | |
935 | position -= vbl_end; | |
936 | else | |
937 | position += vtotal - vbl_end; | |
0af7e4df | 938 | |
91d14251 | 939 | if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { |
3aa18df8 VS |
940 | *vpos = position; |
941 | *hpos = 0; | |
942 | } else { | |
943 | *vpos = position / htotal; | |
944 | *hpos = position - (*vpos * htotal); | |
945 | } | |
0af7e4df | 946 | |
0af7e4df MK |
947 | /* In vblank? */ |
948 | if (in_vbl) | |
3d3cbd84 | 949 | ret |= DRM_SCANOUTPOS_IN_VBLANK; |
0af7e4df MK |
950 | |
951 | return ret; | |
952 | } | |
953 | ||
a225f079 VS |
954 | int intel_get_crtc_scanline(struct intel_crtc *crtc) |
955 | { | |
fac5e23e | 956 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
a225f079 VS |
957 | unsigned long irqflags; |
958 | int position; | |
959 | ||
960 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
961 | position = __intel_get_crtc_scanline(crtc); | |
962 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
963 | ||
964 | return position; | |
965 | } | |
966 | ||
88e72717 | 967 | static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe, |
0af7e4df MK |
968 | int *max_error, |
969 | struct timeval *vblank_time, | |
970 | unsigned flags) | |
971 | { | |
b91eb5cc | 972 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2af48c6 | 973 | struct intel_crtc *crtc; |
0af7e4df | 974 | |
b91eb5cc | 975 | if (pipe >= INTEL_INFO(dev_priv)->num_pipes) { |
88e72717 | 976 | DRM_ERROR("Invalid crtc %u\n", pipe); |
0af7e4df MK |
977 | return -EINVAL; |
978 | } | |
979 | ||
980 | /* Get drm_crtc to timestamp: */ | |
b91eb5cc | 981 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
4041b853 | 982 | if (crtc == NULL) { |
88e72717 | 983 | DRM_ERROR("Invalid crtc %u\n", pipe); |
4041b853 CW |
984 | return -EINVAL; |
985 | } | |
986 | ||
e2af48c6 | 987 | if (!crtc->base.hwmode.crtc_clock) { |
88e72717 | 988 | DRM_DEBUG_KMS("crtc %u is disabled\n", pipe); |
4041b853 CW |
989 | return -EBUSY; |
990 | } | |
0af7e4df MK |
991 | |
992 | /* Helper routine in DRM core does all the work: */ | |
4041b853 CW |
993 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
994 | vblank_time, flags, | |
e2af48c6 | 995 | &crtc->base.hwmode); |
0af7e4df MK |
996 | } |
997 | ||
91d14251 | 998 | static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv) |
f97108d1 | 999 | { |
b5b72e89 | 1000 | u32 busy_up, busy_down, max_avg, min_avg; |
9270388e | 1001 | u8 new_delay; |
9270388e | 1002 | |
d0ecd7e2 | 1003 | spin_lock(&mchdev_lock); |
f97108d1 | 1004 | |
73edd18f DV |
1005 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
1006 | ||
20e4d407 | 1007 | new_delay = dev_priv->ips.cur_delay; |
9270388e | 1008 | |
7648fa99 | 1009 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
1010 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
1011 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
1012 | max_avg = I915_READ(RCBMAXAVG); |
1013 | min_avg = I915_READ(RCBMINAVG); | |
1014 | ||
1015 | /* Handle RCS change request from hw */ | |
b5b72e89 | 1016 | if (busy_up > max_avg) { |
20e4d407 DV |
1017 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
1018 | new_delay = dev_priv->ips.cur_delay - 1; | |
1019 | if (new_delay < dev_priv->ips.max_delay) | |
1020 | new_delay = dev_priv->ips.max_delay; | |
b5b72e89 | 1021 | } else if (busy_down < min_avg) { |
20e4d407 DV |
1022 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
1023 | new_delay = dev_priv->ips.cur_delay + 1; | |
1024 | if (new_delay > dev_priv->ips.min_delay) | |
1025 | new_delay = dev_priv->ips.min_delay; | |
f97108d1 JB |
1026 | } |
1027 | ||
91d14251 | 1028 | if (ironlake_set_drps(dev_priv, new_delay)) |
20e4d407 | 1029 | dev_priv->ips.cur_delay = new_delay; |
f97108d1 | 1030 | |
d0ecd7e2 | 1031 | spin_unlock(&mchdev_lock); |
9270388e | 1032 | |
f97108d1 JB |
1033 | return; |
1034 | } | |
1035 | ||
0bc40be8 | 1036 | static void notify_ring(struct intel_engine_cs *engine) |
549f7365 | 1037 | { |
56299fb7 CW |
1038 | struct drm_i915_gem_request *rq = NULL; |
1039 | struct intel_wait *wait; | |
dffabc8f | 1040 | |
2246bea6 | 1041 | atomic_inc(&engine->irq_count); |
538b257d | 1042 | set_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted); |
56299fb7 | 1043 | |
61d3dc70 CW |
1044 | spin_lock(&engine->breadcrumbs.irq_lock); |
1045 | wait = engine->breadcrumbs.irq_wait; | |
56299fb7 CW |
1046 | if (wait) { |
1047 | /* We use a callback from the dma-fence to submit | |
1048 | * requests after waiting on our own requests. To | |
1049 | * ensure minimum delay in queuing the next request to | |
1050 | * hardware, signal the fence now rather than wait for | |
1051 | * the signaler to be woken up. We still wake up the | |
1052 | * waiter in order to handle the irq-seqno coherency | |
1053 | * issues (we may receive the interrupt before the | |
1054 | * seqno is written, see __i915_request_irq_complete()) | |
1055 | * and to handle coalescing of multiple seqno updates | |
1056 | * and many waiters. | |
1057 | */ | |
1058 | if (i915_seqno_passed(intel_engine_get_seqno(engine), | |
db93991b CW |
1059 | wait->seqno) && |
1060 | !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, | |
1061 | &wait->request->fence.flags)) | |
24754d75 | 1062 | rq = i915_gem_request_get(wait->request); |
56299fb7 CW |
1063 | |
1064 | wake_up_process(wait->tsk); | |
67b807a8 CW |
1065 | } else { |
1066 | __intel_engine_disarm_breadcrumbs(engine); | |
56299fb7 | 1067 | } |
61d3dc70 | 1068 | spin_unlock(&engine->breadcrumbs.irq_lock); |
56299fb7 | 1069 | |
24754d75 | 1070 | if (rq) { |
56299fb7 | 1071 | dma_fence_signal(&rq->fence); |
24754d75 CW |
1072 | i915_gem_request_put(rq); |
1073 | } | |
56299fb7 CW |
1074 | |
1075 | trace_intel_engine_notify(engine, wait); | |
549f7365 CW |
1076 | } |
1077 | ||
43cf3bf0 CW |
1078 | static void vlv_c0_read(struct drm_i915_private *dev_priv, |
1079 | struct intel_rps_ei *ei) | |
31685c25 | 1080 | { |
679cb6c1 | 1081 | ei->ktime = ktime_get_raw(); |
43cf3bf0 CW |
1082 | ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT); |
1083 | ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT); | |
1084 | } | |
31685c25 | 1085 | |
43cf3bf0 | 1086 | void gen6_rps_reset_ei(struct drm_i915_private *dev_priv) |
31685c25 | 1087 | { |
e0e8c7cb | 1088 | memset(&dev_priv->rps.ei, 0, sizeof(dev_priv->rps.ei)); |
43cf3bf0 | 1089 | } |
31685c25 | 1090 | |
43cf3bf0 CW |
1091 | static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir) |
1092 | { | |
e0e8c7cb | 1093 | const struct intel_rps_ei *prev = &dev_priv->rps.ei; |
43cf3bf0 CW |
1094 | struct intel_rps_ei now; |
1095 | u32 events = 0; | |
31685c25 | 1096 | |
e0e8c7cb | 1097 | if ((pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) == 0) |
43cf3bf0 | 1098 | return 0; |
31685c25 | 1099 | |
43cf3bf0 | 1100 | vlv_c0_read(dev_priv, &now); |
31685c25 | 1101 | |
679cb6c1 | 1102 | if (prev->ktime) { |
e0e8c7cb | 1103 | u64 time, c0; |
569884e3 | 1104 | u32 render, media; |
e0e8c7cb | 1105 | |
679cb6c1 | 1106 | time = ktime_us_delta(now.ktime, prev->ktime); |
8f68d591 | 1107 | |
e0e8c7cb CW |
1108 | time *= dev_priv->czclk_freq; |
1109 | ||
1110 | /* Workload can be split between render + media, | |
1111 | * e.g. SwapBuffers being blitted in X after being rendered in | |
1112 | * mesa. To account for this we need to combine both engines | |
1113 | * into our activity counter. | |
1114 | */ | |
569884e3 CW |
1115 | render = now.render_c0 - prev->render_c0; |
1116 | media = now.media_c0 - prev->media_c0; | |
1117 | c0 = max(render, media); | |
6b7f6aa7 | 1118 | c0 *= 1000 * 100 << 8; /* to usecs and scale to threshold% */ |
e0e8c7cb CW |
1119 | |
1120 | if (c0 > time * dev_priv->rps.up_threshold) | |
1121 | events = GEN6_PM_RP_UP_THRESHOLD; | |
1122 | else if (c0 < time * dev_priv->rps.down_threshold) | |
1123 | events = GEN6_PM_RP_DOWN_THRESHOLD; | |
31685c25 D |
1124 | } |
1125 | ||
e0e8c7cb | 1126 | dev_priv->rps.ei = now; |
43cf3bf0 | 1127 | return events; |
31685c25 D |
1128 | } |
1129 | ||
f5a4c67d CW |
1130 | static bool any_waiters(struct drm_i915_private *dev_priv) |
1131 | { | |
e2f80391 | 1132 | struct intel_engine_cs *engine; |
3b3f1650 | 1133 | enum intel_engine_id id; |
f5a4c67d | 1134 | |
3b3f1650 | 1135 | for_each_engine(engine, dev_priv, id) |
688e6c72 | 1136 | if (intel_engine_has_waiter(engine)) |
f5a4c67d CW |
1137 | return true; |
1138 | ||
1139 | return false; | |
1140 | } | |
1141 | ||
4912d041 | 1142 | static void gen6_pm_rps_work(struct work_struct *work) |
3b8d8d91 | 1143 | { |
2d1013dd JN |
1144 | struct drm_i915_private *dev_priv = |
1145 | container_of(work, struct drm_i915_private, rps.work); | |
7c0a16ad | 1146 | bool client_boost = false; |
8d3afd7d | 1147 | int new_delay, adj, min, max; |
7c0a16ad | 1148 | u32 pm_iir = 0; |
4912d041 | 1149 | |
59cdb63d | 1150 | spin_lock_irq(&dev_priv->irq_lock); |
7c0a16ad CW |
1151 | if (dev_priv->rps.interrupts_enabled) { |
1152 | pm_iir = fetch_and_zero(&dev_priv->rps.pm_iir); | |
1153 | client_boost = fetch_and_zero(&dev_priv->rps.client_boost); | |
d4d70aa5 | 1154 | } |
59cdb63d | 1155 | spin_unlock_irq(&dev_priv->irq_lock); |
3b8d8d91 | 1156 | |
60611c13 | 1157 | /* Make sure we didn't queue anything we're not going to process. */ |
a6706b45 | 1158 | WARN_ON(pm_iir & ~dev_priv->pm_rps_events); |
8d3afd7d | 1159 | if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost) |
7c0a16ad | 1160 | goto out; |
3b8d8d91 | 1161 | |
4fc688ce | 1162 | mutex_lock(&dev_priv->rps.hw_lock); |
7b9e0ae6 | 1163 | |
43cf3bf0 CW |
1164 | pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir); |
1165 | ||
dd75fdc8 | 1166 | adj = dev_priv->rps.last_adj; |
edcf284b | 1167 | new_delay = dev_priv->rps.cur_freq; |
8d3afd7d CW |
1168 | min = dev_priv->rps.min_freq_softlimit; |
1169 | max = dev_priv->rps.max_freq_softlimit; | |
29ecd78d CW |
1170 | if (client_boost || any_waiters(dev_priv)) |
1171 | max = dev_priv->rps.max_freq; | |
1172 | if (client_boost && new_delay < dev_priv->rps.boost_freq) { | |
1173 | new_delay = dev_priv->rps.boost_freq; | |
8d3afd7d CW |
1174 | adj = 0; |
1175 | } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { | |
dd75fdc8 CW |
1176 | if (adj > 0) |
1177 | adj *= 2; | |
edcf284b CW |
1178 | else /* CHV needs even encode values */ |
1179 | adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1; | |
7e79a683 SAK |
1180 | |
1181 | if (new_delay >= dev_priv->rps.max_freq_softlimit) | |
1182 | adj = 0; | |
29ecd78d | 1183 | } else if (client_boost || any_waiters(dev_priv)) { |
f5a4c67d | 1184 | adj = 0; |
dd75fdc8 | 1185 | } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { |
b39fb297 BW |
1186 | if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq) |
1187 | new_delay = dev_priv->rps.efficient_freq; | |
17136d54 | 1188 | else if (dev_priv->rps.cur_freq > dev_priv->rps.min_freq_softlimit) |
b39fb297 | 1189 | new_delay = dev_priv->rps.min_freq_softlimit; |
dd75fdc8 CW |
1190 | adj = 0; |
1191 | } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { | |
1192 | if (adj < 0) | |
1193 | adj *= 2; | |
edcf284b CW |
1194 | else /* CHV needs even encode values */ |
1195 | adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1; | |
7e79a683 SAK |
1196 | |
1197 | if (new_delay <= dev_priv->rps.min_freq_softlimit) | |
1198 | adj = 0; | |
dd75fdc8 | 1199 | } else { /* unknown event */ |
edcf284b | 1200 | adj = 0; |
dd75fdc8 | 1201 | } |
3b8d8d91 | 1202 | |
edcf284b CW |
1203 | dev_priv->rps.last_adj = adj; |
1204 | ||
79249636 BW |
1205 | /* sysfs frequency interfaces may have snuck in while servicing the |
1206 | * interrupt | |
1207 | */ | |
edcf284b | 1208 | new_delay += adj; |
8d3afd7d | 1209 | new_delay = clamp_t(int, new_delay, min, max); |
27544369 | 1210 | |
9fcee2f7 CW |
1211 | if (intel_set_rps(dev_priv, new_delay)) { |
1212 | DRM_DEBUG_DRIVER("Failed to set new GPU frequency\n"); | |
1213 | dev_priv->rps.last_adj = 0; | |
1214 | } | |
3b8d8d91 | 1215 | |
4fc688ce | 1216 | mutex_unlock(&dev_priv->rps.hw_lock); |
7c0a16ad CW |
1217 | |
1218 | out: | |
1219 | /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */ | |
1220 | spin_lock_irq(&dev_priv->irq_lock); | |
1221 | if (dev_priv->rps.interrupts_enabled) | |
1222 | gen6_unmask_pm_irq(dev_priv, dev_priv->pm_rps_events); | |
1223 | spin_unlock_irq(&dev_priv->irq_lock); | |
3b8d8d91 JB |
1224 | } |
1225 | ||
e3689190 BW |
1226 | |
1227 | /** | |
1228 | * ivybridge_parity_work - Workqueue called when a parity error interrupt | |
1229 | * occurred. | |
1230 | * @work: workqueue struct | |
1231 | * | |
1232 | * Doesn't actually do anything except notify userspace. As a consequence of | |
1233 | * this event, userspace should try to remap the bad rows since statistically | |
1234 | * it is likely the same row is more likely to go bad again. | |
1235 | */ | |
1236 | static void ivybridge_parity_work(struct work_struct *work) | |
1237 | { | |
2d1013dd JN |
1238 | struct drm_i915_private *dev_priv = |
1239 | container_of(work, struct drm_i915_private, l3_parity.error_work); | |
e3689190 | 1240 | u32 error_status, row, bank, subbank; |
35a85ac6 | 1241 | char *parity_event[6]; |
e3689190 | 1242 | uint32_t misccpctl; |
35a85ac6 | 1243 | uint8_t slice = 0; |
e3689190 BW |
1244 | |
1245 | /* We must turn off DOP level clock gating to access the L3 registers. | |
1246 | * In order to prevent a get/put style interface, acquire struct mutex | |
1247 | * any time we access those registers. | |
1248 | */ | |
91c8a326 | 1249 | mutex_lock(&dev_priv->drm.struct_mutex); |
e3689190 | 1250 | |
35a85ac6 BW |
1251 | /* If we've screwed up tracking, just let the interrupt fire again */ |
1252 | if (WARN_ON(!dev_priv->l3_parity.which_slice)) | |
1253 | goto out; | |
1254 | ||
e3689190 BW |
1255 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
1256 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
1257 | POSTING_READ(GEN7_MISCCPCTL); | |
1258 | ||
35a85ac6 | 1259 | while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { |
f0f59a00 | 1260 | i915_reg_t reg; |
e3689190 | 1261 | |
35a85ac6 | 1262 | slice--; |
2d1fe073 | 1263 | if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv))) |
35a85ac6 | 1264 | break; |
e3689190 | 1265 | |
35a85ac6 | 1266 | dev_priv->l3_parity.which_slice &= ~(1<<slice); |
e3689190 | 1267 | |
6fa1c5f1 | 1268 | reg = GEN7_L3CDERRST1(slice); |
e3689190 | 1269 | |
35a85ac6 BW |
1270 | error_status = I915_READ(reg); |
1271 | row = GEN7_PARITY_ERROR_ROW(error_status); | |
1272 | bank = GEN7_PARITY_ERROR_BANK(error_status); | |
1273 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); | |
1274 | ||
1275 | I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); | |
1276 | POSTING_READ(reg); | |
1277 | ||
1278 | parity_event[0] = I915_L3_PARITY_UEVENT "=1"; | |
1279 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); | |
1280 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); | |
1281 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); | |
1282 | parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); | |
1283 | parity_event[5] = NULL; | |
1284 | ||
91c8a326 | 1285 | kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj, |
35a85ac6 | 1286 | KOBJ_CHANGE, parity_event); |
e3689190 | 1287 | |
35a85ac6 BW |
1288 | DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", |
1289 | slice, row, bank, subbank); | |
e3689190 | 1290 | |
35a85ac6 BW |
1291 | kfree(parity_event[4]); |
1292 | kfree(parity_event[3]); | |
1293 | kfree(parity_event[2]); | |
1294 | kfree(parity_event[1]); | |
1295 | } | |
e3689190 | 1296 | |
35a85ac6 | 1297 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
e3689190 | 1298 | |
35a85ac6 BW |
1299 | out: |
1300 | WARN_ON(dev_priv->l3_parity.which_slice); | |
4cb21832 | 1301 | spin_lock_irq(&dev_priv->irq_lock); |
2d1fe073 | 1302 | gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv)); |
4cb21832 | 1303 | spin_unlock_irq(&dev_priv->irq_lock); |
35a85ac6 | 1304 | |
91c8a326 | 1305 | mutex_unlock(&dev_priv->drm.struct_mutex); |
e3689190 BW |
1306 | } |
1307 | ||
261e40b8 VS |
1308 | static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv, |
1309 | u32 iir) | |
e3689190 | 1310 | { |
261e40b8 | 1311 | if (!HAS_L3_DPF(dev_priv)) |
e3689190 BW |
1312 | return; |
1313 | ||
d0ecd7e2 | 1314 | spin_lock(&dev_priv->irq_lock); |
261e40b8 | 1315 | gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv)); |
d0ecd7e2 | 1316 | spin_unlock(&dev_priv->irq_lock); |
e3689190 | 1317 | |
261e40b8 | 1318 | iir &= GT_PARITY_ERROR(dev_priv); |
35a85ac6 BW |
1319 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) |
1320 | dev_priv->l3_parity.which_slice |= 1 << 1; | |
1321 | ||
1322 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) | |
1323 | dev_priv->l3_parity.which_slice |= 1 << 0; | |
1324 | ||
a4da4fa4 | 1325 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
e3689190 BW |
1326 | } |
1327 | ||
261e40b8 | 1328 | static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv, |
f1af8fc1 PZ |
1329 | u32 gt_iir) |
1330 | { | |
f8973c21 | 1331 | if (gt_iir & GT_RENDER_USER_INTERRUPT) |
3b3f1650 | 1332 | notify_ring(dev_priv->engine[RCS]); |
f1af8fc1 | 1333 | if (gt_iir & ILK_BSD_USER_INTERRUPT) |
3b3f1650 | 1334 | notify_ring(dev_priv->engine[VCS]); |
f1af8fc1 PZ |
1335 | } |
1336 | ||
261e40b8 | 1337 | static void snb_gt_irq_handler(struct drm_i915_private *dev_priv, |
e7b4c6b1 DV |
1338 | u32 gt_iir) |
1339 | { | |
f8973c21 | 1340 | if (gt_iir & GT_RENDER_USER_INTERRUPT) |
3b3f1650 | 1341 | notify_ring(dev_priv->engine[RCS]); |
cc609d5d | 1342 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
3b3f1650 | 1343 | notify_ring(dev_priv->engine[VCS]); |
cc609d5d | 1344 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
3b3f1650 | 1345 | notify_ring(dev_priv->engine[BCS]); |
e7b4c6b1 | 1346 | |
cc609d5d BW |
1347 | if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | |
1348 | GT_BSD_CS_ERROR_INTERRUPT | | |
aaecdf61 DV |
1349 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) |
1350 | DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir); | |
e3689190 | 1351 | |
261e40b8 VS |
1352 | if (gt_iir & GT_PARITY_ERROR(dev_priv)) |
1353 | ivybridge_parity_error_irq_handler(dev_priv, gt_iir); | |
e7b4c6b1 DV |
1354 | } |
1355 | ||
fbcc1a0c | 1356 | static __always_inline void |
0bc40be8 | 1357 | gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift) |
fbcc1a0c | 1358 | { |
31de7350 | 1359 | bool tasklet = false; |
f747026c CW |
1360 | |
1361 | if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift)) { | |
1362 | set_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); | |
31de7350 | 1363 | tasklet = true; |
f747026c | 1364 | } |
31de7350 CW |
1365 | |
1366 | if (iir & (GT_RENDER_USER_INTERRUPT << test_shift)) { | |
1367 | notify_ring(engine); | |
1368 | tasklet |= i915.enable_guc_submission; | |
1369 | } | |
1370 | ||
1371 | if (tasklet) | |
1372 | tasklet_hi_schedule(&engine->irq_tasklet); | |
fbcc1a0c NH |
1373 | } |
1374 | ||
e30e251a VS |
1375 | static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv, |
1376 | u32 master_ctl, | |
1377 | u32 gt_iir[4]) | |
abd58f01 | 1378 | { |
abd58f01 BW |
1379 | irqreturn_t ret = IRQ_NONE; |
1380 | ||
1381 | if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { | |
e30e251a VS |
1382 | gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0)); |
1383 | if (gt_iir[0]) { | |
1384 | I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]); | |
abd58f01 | 1385 | ret = IRQ_HANDLED; |
abd58f01 BW |
1386 | } else |
1387 | DRM_ERROR("The master control interrupt lied (GT0)!\n"); | |
1388 | } | |
1389 | ||
85f9b5f9 | 1390 | if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) { |
e30e251a VS |
1391 | gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1)); |
1392 | if (gt_iir[1]) { | |
1393 | I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]); | |
abd58f01 | 1394 | ret = IRQ_HANDLED; |
0961021a | 1395 | } else |
abd58f01 | 1396 | DRM_ERROR("The master control interrupt lied (GT1)!\n"); |
0961021a BW |
1397 | } |
1398 | ||
abd58f01 | 1399 | if (master_ctl & GEN8_GT_VECS_IRQ) { |
e30e251a VS |
1400 | gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3)); |
1401 | if (gt_iir[3]) { | |
1402 | I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]); | |
abd58f01 | 1403 | ret = IRQ_HANDLED; |
abd58f01 BW |
1404 | } else |
1405 | DRM_ERROR("The master control interrupt lied (GT3)!\n"); | |
1406 | } | |
1407 | ||
26705e20 | 1408 | if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) { |
e30e251a | 1409 | gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2)); |
26705e20 SAK |
1410 | if (gt_iir[2] & (dev_priv->pm_rps_events | |
1411 | dev_priv->pm_guc_events)) { | |
cb0d205e | 1412 | I915_WRITE_FW(GEN8_GT_IIR(2), |
26705e20 SAK |
1413 | gt_iir[2] & (dev_priv->pm_rps_events | |
1414 | dev_priv->pm_guc_events)); | |
38cc46d7 | 1415 | ret = IRQ_HANDLED; |
0961021a BW |
1416 | } else |
1417 | DRM_ERROR("The master control interrupt lied (PM)!\n"); | |
1418 | } | |
1419 | ||
abd58f01 BW |
1420 | return ret; |
1421 | } | |
1422 | ||
e30e251a VS |
1423 | static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv, |
1424 | u32 gt_iir[4]) | |
1425 | { | |
1426 | if (gt_iir[0]) { | |
3b3f1650 | 1427 | gen8_cs_irq_handler(dev_priv->engine[RCS], |
e30e251a | 1428 | gt_iir[0], GEN8_RCS_IRQ_SHIFT); |
3b3f1650 | 1429 | gen8_cs_irq_handler(dev_priv->engine[BCS], |
e30e251a VS |
1430 | gt_iir[0], GEN8_BCS_IRQ_SHIFT); |
1431 | } | |
1432 | ||
1433 | if (gt_iir[1]) { | |
3b3f1650 | 1434 | gen8_cs_irq_handler(dev_priv->engine[VCS], |
e30e251a | 1435 | gt_iir[1], GEN8_VCS1_IRQ_SHIFT); |
3b3f1650 | 1436 | gen8_cs_irq_handler(dev_priv->engine[VCS2], |
e30e251a VS |
1437 | gt_iir[1], GEN8_VCS2_IRQ_SHIFT); |
1438 | } | |
1439 | ||
1440 | if (gt_iir[3]) | |
3b3f1650 | 1441 | gen8_cs_irq_handler(dev_priv->engine[VECS], |
e30e251a VS |
1442 | gt_iir[3], GEN8_VECS_IRQ_SHIFT); |
1443 | ||
1444 | if (gt_iir[2] & dev_priv->pm_rps_events) | |
1445 | gen6_rps_irq_handler(dev_priv, gt_iir[2]); | |
26705e20 SAK |
1446 | |
1447 | if (gt_iir[2] & dev_priv->pm_guc_events) | |
1448 | gen9_guc_irq_handler(dev_priv, gt_iir[2]); | |
e30e251a VS |
1449 | } |
1450 | ||
63c88d22 ID |
1451 | static bool bxt_port_hotplug_long_detect(enum port port, u32 val) |
1452 | { | |
1453 | switch (port) { | |
1454 | case PORT_A: | |
195baa06 | 1455 | return val & PORTA_HOTPLUG_LONG_DETECT; |
63c88d22 ID |
1456 | case PORT_B: |
1457 | return val & PORTB_HOTPLUG_LONG_DETECT; | |
1458 | case PORT_C: | |
1459 | return val & PORTC_HOTPLUG_LONG_DETECT; | |
63c88d22 ID |
1460 | default: |
1461 | return false; | |
1462 | } | |
1463 | } | |
1464 | ||
6dbf30ce VS |
1465 | static bool spt_port_hotplug2_long_detect(enum port port, u32 val) |
1466 | { | |
1467 | switch (port) { | |
1468 | case PORT_E: | |
1469 | return val & PORTE_HOTPLUG_LONG_DETECT; | |
1470 | default: | |
1471 | return false; | |
1472 | } | |
1473 | } | |
1474 | ||
74c0b395 VS |
1475 | static bool spt_port_hotplug_long_detect(enum port port, u32 val) |
1476 | { | |
1477 | switch (port) { | |
1478 | case PORT_A: | |
1479 | return val & PORTA_HOTPLUG_LONG_DETECT; | |
1480 | case PORT_B: | |
1481 | return val & PORTB_HOTPLUG_LONG_DETECT; | |
1482 | case PORT_C: | |
1483 | return val & PORTC_HOTPLUG_LONG_DETECT; | |
1484 | case PORT_D: | |
1485 | return val & PORTD_HOTPLUG_LONG_DETECT; | |
1486 | default: | |
1487 | return false; | |
1488 | } | |
1489 | } | |
1490 | ||
e4ce95aa VS |
1491 | static bool ilk_port_hotplug_long_detect(enum port port, u32 val) |
1492 | { | |
1493 | switch (port) { | |
1494 | case PORT_A: | |
1495 | return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT; | |
1496 | default: | |
1497 | return false; | |
1498 | } | |
1499 | } | |
1500 | ||
676574df | 1501 | static bool pch_port_hotplug_long_detect(enum port port, u32 val) |
13cf5504 DA |
1502 | { |
1503 | switch (port) { | |
13cf5504 | 1504 | case PORT_B: |
676574df | 1505 | return val & PORTB_HOTPLUG_LONG_DETECT; |
13cf5504 | 1506 | case PORT_C: |
676574df | 1507 | return val & PORTC_HOTPLUG_LONG_DETECT; |
13cf5504 | 1508 | case PORT_D: |
676574df JN |
1509 | return val & PORTD_HOTPLUG_LONG_DETECT; |
1510 | default: | |
1511 | return false; | |
13cf5504 DA |
1512 | } |
1513 | } | |
1514 | ||
676574df | 1515 | static bool i9xx_port_hotplug_long_detect(enum port port, u32 val) |
13cf5504 DA |
1516 | { |
1517 | switch (port) { | |
13cf5504 | 1518 | case PORT_B: |
676574df | 1519 | return val & PORTB_HOTPLUG_INT_LONG_PULSE; |
13cf5504 | 1520 | case PORT_C: |
676574df | 1521 | return val & PORTC_HOTPLUG_INT_LONG_PULSE; |
13cf5504 | 1522 | case PORT_D: |
676574df JN |
1523 | return val & PORTD_HOTPLUG_INT_LONG_PULSE; |
1524 | default: | |
1525 | return false; | |
13cf5504 DA |
1526 | } |
1527 | } | |
1528 | ||
42db67d6 VS |
1529 | /* |
1530 | * Get a bit mask of pins that have triggered, and which ones may be long. | |
1531 | * This can be called multiple times with the same masks to accumulate | |
1532 | * hotplug detection results from several registers. | |
1533 | * | |
1534 | * Note that the caller is expected to zero out the masks initially. | |
1535 | */ | |
fd63e2a9 | 1536 | static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask, |
8c841e57 | 1537 | u32 hotplug_trigger, u32 dig_hotplug_reg, |
fd63e2a9 ID |
1538 | const u32 hpd[HPD_NUM_PINS], |
1539 | bool long_pulse_detect(enum port port, u32 val)) | |
676574df | 1540 | { |
8c841e57 | 1541 | enum port port; |
676574df JN |
1542 | int i; |
1543 | ||
676574df | 1544 | for_each_hpd_pin(i) { |
8c841e57 JN |
1545 | if ((hpd[i] & hotplug_trigger) == 0) |
1546 | continue; | |
676574df | 1547 | |
8c841e57 JN |
1548 | *pin_mask |= BIT(i); |
1549 | ||
cc24fcdc ID |
1550 | if (!intel_hpd_pin_to_port(i, &port)) |
1551 | continue; | |
1552 | ||
fd63e2a9 | 1553 | if (long_pulse_detect(port, dig_hotplug_reg)) |
8c841e57 | 1554 | *long_mask |= BIT(i); |
676574df JN |
1555 | } |
1556 | ||
1557 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n", | |
1558 | hotplug_trigger, dig_hotplug_reg, *pin_mask); | |
1559 | ||
1560 | } | |
1561 | ||
91d14251 | 1562 | static void gmbus_irq_handler(struct drm_i915_private *dev_priv) |
515ac2bb | 1563 | { |
28c70f16 | 1564 | wake_up_all(&dev_priv->gmbus_wait_queue); |
515ac2bb DV |
1565 | } |
1566 | ||
91d14251 | 1567 | static void dp_aux_irq_handler(struct drm_i915_private *dev_priv) |
ce99c256 | 1568 | { |
9ee32fea | 1569 | wake_up_all(&dev_priv->gmbus_wait_queue); |
ce99c256 DV |
1570 | } |
1571 | ||
8bf1e9f1 | 1572 | #if defined(CONFIG_DEBUG_FS) |
91d14251 TU |
1573 | static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, |
1574 | enum pipe pipe, | |
277de95e DV |
1575 | uint32_t crc0, uint32_t crc1, |
1576 | uint32_t crc2, uint32_t crc3, | |
1577 | uint32_t crc4) | |
8bf1e9f1 | 1578 | { |
8bf1e9f1 SH |
1579 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
1580 | struct intel_pipe_crc_entry *entry; | |
8c6b709d TV |
1581 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
1582 | struct drm_driver *driver = dev_priv->drm.driver; | |
1583 | uint32_t crcs[5]; | |
ac2300d4 | 1584 | int head, tail; |
b2c88f5b | 1585 | |
d538bbdf | 1586 | spin_lock(&pipe_crc->lock); |
8c6b709d TV |
1587 | if (pipe_crc->source) { |
1588 | if (!pipe_crc->entries) { | |
1589 | spin_unlock(&pipe_crc->lock); | |
1590 | DRM_DEBUG_KMS("spurious interrupt\n"); | |
1591 | return; | |
1592 | } | |
d538bbdf | 1593 | |
8c6b709d TV |
1594 | head = pipe_crc->head; |
1595 | tail = pipe_crc->tail; | |
b2c88f5b | 1596 | |
8c6b709d TV |
1597 | if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { |
1598 | spin_unlock(&pipe_crc->lock); | |
1599 | DRM_ERROR("CRC buffer overflowing\n"); | |
1600 | return; | |
1601 | } | |
b2c88f5b | 1602 | |
8c6b709d | 1603 | entry = &pipe_crc->entries[head]; |
8bf1e9f1 | 1604 | |
8c6b709d TV |
1605 | entry->frame = driver->get_vblank_counter(&dev_priv->drm, pipe); |
1606 | entry->crc[0] = crc0; | |
1607 | entry->crc[1] = crc1; | |
1608 | entry->crc[2] = crc2; | |
1609 | entry->crc[3] = crc3; | |
1610 | entry->crc[4] = crc4; | |
b2c88f5b | 1611 | |
8c6b709d TV |
1612 | head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); |
1613 | pipe_crc->head = head; | |
d538bbdf | 1614 | |
8c6b709d | 1615 | spin_unlock(&pipe_crc->lock); |
07144428 | 1616 | |
8c6b709d TV |
1617 | wake_up_interruptible(&pipe_crc->wq); |
1618 | } else { | |
1619 | /* | |
1620 | * For some not yet identified reason, the first CRC is | |
1621 | * bonkers. So let's just wait for the next vblank and read | |
1622 | * out the buggy result. | |
1623 | * | |
1624 | * On CHV sometimes the second CRC is bonkers as well, so | |
1625 | * don't trust that one either. | |
1626 | */ | |
1627 | if (pipe_crc->skipped == 0 || | |
1628 | (IS_CHERRYVIEW(dev_priv) && pipe_crc->skipped == 1)) { | |
1629 | pipe_crc->skipped++; | |
1630 | spin_unlock(&pipe_crc->lock); | |
1631 | return; | |
1632 | } | |
1633 | spin_unlock(&pipe_crc->lock); | |
1634 | crcs[0] = crc0; | |
1635 | crcs[1] = crc1; | |
1636 | crcs[2] = crc2; | |
1637 | crcs[3] = crc3; | |
1638 | crcs[4] = crc4; | |
246ee524 TV |
1639 | drm_crtc_add_crc_entry(&crtc->base, true, |
1640 | drm_accurate_vblank_count(&crtc->base), | |
1641 | crcs); | |
8c6b709d | 1642 | } |
8bf1e9f1 | 1643 | } |
277de95e DV |
1644 | #else |
1645 | static inline void | |
91d14251 TU |
1646 | display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, |
1647 | enum pipe pipe, | |
277de95e DV |
1648 | uint32_t crc0, uint32_t crc1, |
1649 | uint32_t crc2, uint32_t crc3, | |
1650 | uint32_t crc4) {} | |
1651 | #endif | |
1652 | ||
eba94eb9 | 1653 | |
91d14251 TU |
1654 | static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, |
1655 | enum pipe pipe) | |
5a69b89f | 1656 | { |
91d14251 | 1657 | display_pipe_crc_irq_handler(dev_priv, pipe, |
277de95e DV |
1658 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), |
1659 | 0, 0, 0, 0); | |
5a69b89f DV |
1660 | } |
1661 | ||
91d14251 TU |
1662 | static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, |
1663 | enum pipe pipe) | |
eba94eb9 | 1664 | { |
91d14251 | 1665 | display_pipe_crc_irq_handler(dev_priv, pipe, |
277de95e DV |
1666 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), |
1667 | I915_READ(PIPE_CRC_RES_2_IVB(pipe)), | |
1668 | I915_READ(PIPE_CRC_RES_3_IVB(pipe)), | |
1669 | I915_READ(PIPE_CRC_RES_4_IVB(pipe)), | |
1670 | I915_READ(PIPE_CRC_RES_5_IVB(pipe))); | |
eba94eb9 | 1671 | } |
5b3a856b | 1672 | |
91d14251 TU |
1673 | static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, |
1674 | enum pipe pipe) | |
5b3a856b | 1675 | { |
0b5c5ed0 DV |
1676 | uint32_t res1, res2; |
1677 | ||
91d14251 | 1678 | if (INTEL_GEN(dev_priv) >= 3) |
0b5c5ed0 DV |
1679 | res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); |
1680 | else | |
1681 | res1 = 0; | |
1682 | ||
91d14251 | 1683 | if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
0b5c5ed0 DV |
1684 | res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); |
1685 | else | |
1686 | res2 = 0; | |
5b3a856b | 1687 | |
91d14251 | 1688 | display_pipe_crc_irq_handler(dev_priv, pipe, |
277de95e DV |
1689 | I915_READ(PIPE_CRC_RES_RED(pipe)), |
1690 | I915_READ(PIPE_CRC_RES_GREEN(pipe)), | |
1691 | I915_READ(PIPE_CRC_RES_BLUE(pipe)), | |
1692 | res1, res2); | |
5b3a856b | 1693 | } |
8bf1e9f1 | 1694 | |
1403c0d4 PZ |
1695 | /* The RPS events need forcewake, so we add them to a work queue and mask their |
1696 | * IMR bits until the work is done. Other interrupts can be processed without | |
1697 | * the work queue. */ | |
1698 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) | |
baf02a1f | 1699 | { |
a6706b45 | 1700 | if (pm_iir & dev_priv->pm_rps_events) { |
59cdb63d | 1701 | spin_lock(&dev_priv->irq_lock); |
f4e9af4f | 1702 | gen6_mask_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); |
d4d70aa5 ID |
1703 | if (dev_priv->rps.interrupts_enabled) { |
1704 | dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; | |
c33d247d | 1705 | schedule_work(&dev_priv->rps.work); |
d4d70aa5 | 1706 | } |
59cdb63d | 1707 | spin_unlock(&dev_priv->irq_lock); |
baf02a1f | 1708 | } |
baf02a1f | 1709 | |
c9a9a268 ID |
1710 | if (INTEL_INFO(dev_priv)->gen >= 8) |
1711 | return; | |
1712 | ||
2d1fe073 | 1713 | if (HAS_VEBOX(dev_priv)) { |
1403c0d4 | 1714 | if (pm_iir & PM_VEBOX_USER_INTERRUPT) |
3b3f1650 | 1715 | notify_ring(dev_priv->engine[VECS]); |
12638c57 | 1716 | |
aaecdf61 DV |
1717 | if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) |
1718 | DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir); | |
12638c57 | 1719 | } |
baf02a1f BW |
1720 | } |
1721 | ||
26705e20 SAK |
1722 | static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir) |
1723 | { | |
1724 | if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT) { | |
4100b2ab SAK |
1725 | /* Sample the log buffer flush related bits & clear them out now |
1726 | * itself from the message identity register to minimize the | |
1727 | * probability of losing a flush interrupt, when there are back | |
1728 | * to back flush interrupts. | |
1729 | * There can be a new flush interrupt, for different log buffer | |
1730 | * type (like for ISR), whilst Host is handling one (for DPC). | |
1731 | * Since same bit is used in message register for ISR & DPC, it | |
1732 | * could happen that GuC sets the bit for 2nd interrupt but Host | |
1733 | * clears out the bit on handling the 1st interrupt. | |
1734 | */ | |
1735 | u32 msg, flush; | |
1736 | ||
1737 | msg = I915_READ(SOFT_SCRATCH(15)); | |
a80bc45f AH |
1738 | flush = msg & (INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED | |
1739 | INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER); | |
4100b2ab SAK |
1740 | if (flush) { |
1741 | /* Clear the message bits that are handled */ | |
1742 | I915_WRITE(SOFT_SCRATCH(15), msg & ~flush); | |
1743 | ||
1744 | /* Handle flush interrupt in bottom half */ | |
e7465473 OM |
1745 | queue_work(dev_priv->guc.log.runtime.flush_wq, |
1746 | &dev_priv->guc.log.runtime.flush_work); | |
5aa1ee4b AG |
1747 | |
1748 | dev_priv->guc.log.flush_interrupt_count++; | |
4100b2ab SAK |
1749 | } else { |
1750 | /* Not clearing of unhandled event bits won't result in | |
1751 | * re-triggering of the interrupt. | |
1752 | */ | |
1753 | } | |
26705e20 SAK |
1754 | } |
1755 | } | |
1756 | ||
5a21b665 | 1757 | static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv, |
91d14251 | 1758 | enum pipe pipe) |
8d7849db | 1759 | { |
5a21b665 DV |
1760 | bool ret; |
1761 | ||
91c8a326 | 1762 | ret = drm_handle_vblank(&dev_priv->drm, pipe); |
5a21b665 | 1763 | if (ret) |
51cbaf01 | 1764 | intel_finish_page_flip_mmio(dev_priv, pipe); |
5a21b665 DV |
1765 | |
1766 | return ret; | |
8d7849db VS |
1767 | } |
1768 | ||
91d14251 TU |
1769 | static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv, |
1770 | u32 iir, u32 pipe_stats[I915_MAX_PIPES]) | |
c1874ed7 | 1771 | { |
c1874ed7 ID |
1772 | int pipe; |
1773 | ||
58ead0d7 | 1774 | spin_lock(&dev_priv->irq_lock); |
1ca993d2 VS |
1775 | |
1776 | if (!dev_priv->display_irqs_enabled) { | |
1777 | spin_unlock(&dev_priv->irq_lock); | |
1778 | return; | |
1779 | } | |
1780 | ||
055e393f | 1781 | for_each_pipe(dev_priv, pipe) { |
f0f59a00 | 1782 | i915_reg_t reg; |
bbb5eebf | 1783 | u32 mask, iir_bit = 0; |
91d181dd | 1784 | |
bbb5eebf DV |
1785 | /* |
1786 | * PIPESTAT bits get signalled even when the interrupt is | |
1787 | * disabled with the mask bits, and some of the status bits do | |
1788 | * not generate interrupts at all (like the underrun bit). Hence | |
1789 | * we need to be careful that we only handle what we want to | |
1790 | * handle. | |
1791 | */ | |
0f239f4c DV |
1792 | |
1793 | /* fifo underruns are filterered in the underrun handler. */ | |
1794 | mask = PIPE_FIFO_UNDERRUN_STATUS; | |
bbb5eebf DV |
1795 | |
1796 | switch (pipe) { | |
1797 | case PIPE_A: | |
1798 | iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; | |
1799 | break; | |
1800 | case PIPE_B: | |
1801 | iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
1802 | break; | |
3278f67f VS |
1803 | case PIPE_C: |
1804 | iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
1805 | break; | |
bbb5eebf DV |
1806 | } |
1807 | if (iir & iir_bit) | |
1808 | mask |= dev_priv->pipestat_irq_mask[pipe]; | |
1809 | ||
1810 | if (!mask) | |
91d181dd ID |
1811 | continue; |
1812 | ||
1813 | reg = PIPESTAT(pipe); | |
bbb5eebf DV |
1814 | mask |= PIPESTAT_INT_ENABLE_MASK; |
1815 | pipe_stats[pipe] = I915_READ(reg) & mask; | |
c1874ed7 ID |
1816 | |
1817 | /* | |
1818 | * Clear the PIPE*STAT regs before the IIR | |
1819 | */ | |
91d181dd ID |
1820 | if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS | |
1821 | PIPESTAT_INT_STATUS_MASK)) | |
c1874ed7 ID |
1822 | I915_WRITE(reg, pipe_stats[pipe]); |
1823 | } | |
58ead0d7 | 1824 | spin_unlock(&dev_priv->irq_lock); |
2ecb8ca4 VS |
1825 | } |
1826 | ||
91d14251 | 1827 | static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv, |
2ecb8ca4 VS |
1828 | u32 pipe_stats[I915_MAX_PIPES]) |
1829 | { | |
2ecb8ca4 | 1830 | enum pipe pipe; |
c1874ed7 | 1831 | |
055e393f | 1832 | for_each_pipe(dev_priv, pipe) { |
5a21b665 DV |
1833 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
1834 | intel_pipe_handle_vblank(dev_priv, pipe)) | |
1835 | intel_check_page_flip(dev_priv, pipe); | |
c1874ed7 | 1836 | |
5251f04e | 1837 | if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) |
51cbaf01 | 1838 | intel_finish_page_flip_cs(dev_priv, pipe); |
c1874ed7 ID |
1839 | |
1840 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
91d14251 | 1841 | i9xx_pipe_crc_irq_handler(dev_priv, pipe); |
c1874ed7 | 1842 | |
1f7247c0 DV |
1843 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
1844 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
c1874ed7 ID |
1845 | } |
1846 | ||
1847 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) | |
91d14251 | 1848 | gmbus_irq_handler(dev_priv); |
c1874ed7 ID |
1849 | } |
1850 | ||
1ae3c34c | 1851 | static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv) |
16c6c56b | 1852 | { |
16c6c56b VS |
1853 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
1854 | ||
1ae3c34c VS |
1855 | if (hotplug_status) |
1856 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
16c6c56b | 1857 | |
1ae3c34c VS |
1858 | return hotplug_status; |
1859 | } | |
1860 | ||
91d14251 | 1861 | static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv, |
1ae3c34c VS |
1862 | u32 hotplug_status) |
1863 | { | |
1864 | u32 pin_mask = 0, long_mask = 0; | |
16c6c56b | 1865 | |
91d14251 TU |
1866 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
1867 | IS_CHERRYVIEW(dev_priv)) { | |
0d2e4297 | 1868 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; |
16c6c56b | 1869 | |
58f2cf24 VS |
1870 | if (hotplug_trigger) { |
1871 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
1872 | hotplug_trigger, hpd_status_g4x, | |
1873 | i9xx_port_hotplug_long_detect); | |
1874 | ||
91d14251 | 1875 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
58f2cf24 | 1876 | } |
369712e8 JN |
1877 | |
1878 | if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) | |
91d14251 | 1879 | dp_aux_irq_handler(dev_priv); |
0d2e4297 JN |
1880 | } else { |
1881 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; | |
16c6c56b | 1882 | |
58f2cf24 VS |
1883 | if (hotplug_trigger) { |
1884 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
44cc6c08 | 1885 | hotplug_trigger, hpd_status_i915, |
58f2cf24 | 1886 | i9xx_port_hotplug_long_detect); |
91d14251 | 1887 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
58f2cf24 | 1888 | } |
3ff60f89 | 1889 | } |
16c6c56b VS |
1890 | } |
1891 | ||
ff1f525e | 1892 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
7e231dbe | 1893 | { |
45a83f84 | 1894 | struct drm_device *dev = arg; |
fac5e23e | 1895 | struct drm_i915_private *dev_priv = to_i915(dev); |
7e231dbe | 1896 | irqreturn_t ret = IRQ_NONE; |
7e231dbe | 1897 | |
2dd2a883 ID |
1898 | if (!intel_irqs_enabled(dev_priv)) |
1899 | return IRQ_NONE; | |
1900 | ||
1f814dac ID |
1901 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
1902 | disable_rpm_wakeref_asserts(dev_priv); | |
1903 | ||
1e1cace9 | 1904 | do { |
6e814800 | 1905 | u32 iir, gt_iir, pm_iir; |
2ecb8ca4 | 1906 | u32 pipe_stats[I915_MAX_PIPES] = {}; |
1ae3c34c | 1907 | u32 hotplug_status = 0; |
a5e485a9 | 1908 | u32 ier = 0; |
3ff60f89 | 1909 | |
7e231dbe JB |
1910 | gt_iir = I915_READ(GTIIR); |
1911 | pm_iir = I915_READ(GEN6_PMIIR); | |
3ff60f89 | 1912 | iir = I915_READ(VLV_IIR); |
7e231dbe JB |
1913 | |
1914 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) | |
1e1cace9 | 1915 | break; |
7e231dbe JB |
1916 | |
1917 | ret = IRQ_HANDLED; | |
1918 | ||
a5e485a9 VS |
1919 | /* |
1920 | * Theory on interrupt generation, based on empirical evidence: | |
1921 | * | |
1922 | * x = ((VLV_IIR & VLV_IER) || | |
1923 | * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) && | |
1924 | * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE))); | |
1925 | * | |
1926 | * A CPU interrupt will only be raised when 'x' has a 0->1 edge. | |
1927 | * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to | |
1928 | * guarantee the CPU interrupt will be raised again even if we | |
1929 | * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR | |
1930 | * bits this time around. | |
1931 | */ | |
4a0a0202 | 1932 | I915_WRITE(VLV_MASTER_IER, 0); |
a5e485a9 VS |
1933 | ier = I915_READ(VLV_IER); |
1934 | I915_WRITE(VLV_IER, 0); | |
4a0a0202 VS |
1935 | |
1936 | if (gt_iir) | |
1937 | I915_WRITE(GTIIR, gt_iir); | |
1938 | if (pm_iir) | |
1939 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
1940 | ||
7ce4d1f2 | 1941 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
1ae3c34c | 1942 | hotplug_status = i9xx_hpd_irq_ack(dev_priv); |
7ce4d1f2 | 1943 | |
3ff60f89 OM |
1944 | /* Call regardless, as some status bits might not be |
1945 | * signalled in iir */ | |
91d14251 | 1946 | valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats); |
7ce4d1f2 | 1947 | |
eef57324 JA |
1948 | if (iir & (I915_LPE_PIPE_A_INTERRUPT | |
1949 | I915_LPE_PIPE_B_INTERRUPT)) | |
1950 | intel_lpe_audio_irq_handler(dev_priv); | |
1951 | ||
7ce4d1f2 VS |
1952 | /* |
1953 | * VLV_IIR is single buffered, and reflects the level | |
1954 | * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last. | |
1955 | */ | |
1956 | if (iir) | |
1957 | I915_WRITE(VLV_IIR, iir); | |
4a0a0202 | 1958 | |
a5e485a9 | 1959 | I915_WRITE(VLV_IER, ier); |
4a0a0202 VS |
1960 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); |
1961 | POSTING_READ(VLV_MASTER_IER); | |
1ae3c34c | 1962 | |
52894874 | 1963 | if (gt_iir) |
261e40b8 | 1964 | snb_gt_irq_handler(dev_priv, gt_iir); |
52894874 VS |
1965 | if (pm_iir) |
1966 | gen6_rps_irq_handler(dev_priv, pm_iir); | |
1967 | ||
1ae3c34c | 1968 | if (hotplug_status) |
91d14251 | 1969 | i9xx_hpd_irq_handler(dev_priv, hotplug_status); |
2ecb8ca4 | 1970 | |
91d14251 | 1971 | valleyview_pipestat_irq_handler(dev_priv, pipe_stats); |
1e1cace9 | 1972 | } while (0); |
7e231dbe | 1973 | |
1f814dac ID |
1974 | enable_rpm_wakeref_asserts(dev_priv); |
1975 | ||
7e231dbe JB |
1976 | return ret; |
1977 | } | |
1978 | ||
43f328d7 VS |
1979 | static irqreturn_t cherryview_irq_handler(int irq, void *arg) |
1980 | { | |
45a83f84 | 1981 | struct drm_device *dev = arg; |
fac5e23e | 1982 | struct drm_i915_private *dev_priv = to_i915(dev); |
43f328d7 | 1983 | irqreturn_t ret = IRQ_NONE; |
43f328d7 | 1984 | |
2dd2a883 ID |
1985 | if (!intel_irqs_enabled(dev_priv)) |
1986 | return IRQ_NONE; | |
1987 | ||
1f814dac ID |
1988 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
1989 | disable_rpm_wakeref_asserts(dev_priv); | |
1990 | ||
579de73b | 1991 | do { |
6e814800 | 1992 | u32 master_ctl, iir; |
e30e251a | 1993 | u32 gt_iir[4] = {}; |
2ecb8ca4 | 1994 | u32 pipe_stats[I915_MAX_PIPES] = {}; |
1ae3c34c | 1995 | u32 hotplug_status = 0; |
a5e485a9 VS |
1996 | u32 ier = 0; |
1997 | ||
8e5fd599 VS |
1998 | master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; |
1999 | iir = I915_READ(VLV_IIR); | |
43f328d7 | 2000 | |
8e5fd599 VS |
2001 | if (master_ctl == 0 && iir == 0) |
2002 | break; | |
43f328d7 | 2003 | |
27b6c122 OM |
2004 | ret = IRQ_HANDLED; |
2005 | ||
a5e485a9 VS |
2006 | /* |
2007 | * Theory on interrupt generation, based on empirical evidence: | |
2008 | * | |
2009 | * x = ((VLV_IIR & VLV_IER) || | |
2010 | * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) && | |
2011 | * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL))); | |
2012 | * | |
2013 | * A CPU interrupt will only be raised when 'x' has a 0->1 edge. | |
2014 | * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to | |
2015 | * guarantee the CPU interrupt will be raised again even if we | |
2016 | * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL | |
2017 | * bits this time around. | |
2018 | */ | |
8e5fd599 | 2019 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
a5e485a9 VS |
2020 | ier = I915_READ(VLV_IER); |
2021 | I915_WRITE(VLV_IER, 0); | |
43f328d7 | 2022 | |
e30e251a | 2023 | gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir); |
43f328d7 | 2024 | |
7ce4d1f2 | 2025 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
1ae3c34c | 2026 | hotplug_status = i9xx_hpd_irq_ack(dev_priv); |
7ce4d1f2 | 2027 | |
27b6c122 OM |
2028 | /* Call regardless, as some status bits might not be |
2029 | * signalled in iir */ | |
91d14251 | 2030 | valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats); |
43f328d7 | 2031 | |
eef57324 JA |
2032 | if (iir & (I915_LPE_PIPE_A_INTERRUPT | |
2033 | I915_LPE_PIPE_B_INTERRUPT | | |
2034 | I915_LPE_PIPE_C_INTERRUPT)) | |
2035 | intel_lpe_audio_irq_handler(dev_priv); | |
2036 | ||
7ce4d1f2 VS |
2037 | /* |
2038 | * VLV_IIR is single buffered, and reflects the level | |
2039 | * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last. | |
2040 | */ | |
2041 | if (iir) | |
2042 | I915_WRITE(VLV_IIR, iir); | |
2043 | ||
a5e485a9 | 2044 | I915_WRITE(VLV_IER, ier); |
e5328c43 | 2045 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
8e5fd599 | 2046 | POSTING_READ(GEN8_MASTER_IRQ); |
1ae3c34c | 2047 | |
e30e251a VS |
2048 | gen8_gt_irq_handler(dev_priv, gt_iir); |
2049 | ||
1ae3c34c | 2050 | if (hotplug_status) |
91d14251 | 2051 | i9xx_hpd_irq_handler(dev_priv, hotplug_status); |
2ecb8ca4 | 2052 | |
91d14251 | 2053 | valleyview_pipestat_irq_handler(dev_priv, pipe_stats); |
579de73b | 2054 | } while (0); |
3278f67f | 2055 | |
1f814dac ID |
2056 | enable_rpm_wakeref_asserts(dev_priv); |
2057 | ||
43f328d7 VS |
2058 | return ret; |
2059 | } | |
2060 | ||
91d14251 TU |
2061 | static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv, |
2062 | u32 hotplug_trigger, | |
40e56410 VS |
2063 | const u32 hpd[HPD_NUM_PINS]) |
2064 | { | |
40e56410 VS |
2065 | u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; |
2066 | ||
6a39d7c9 JN |
2067 | /* |
2068 | * Somehow the PCH doesn't seem to really ack the interrupt to the CPU | |
2069 | * unless we touch the hotplug register, even if hotplug_trigger is | |
2070 | * zero. Not acking leads to "The master control interrupt lied (SDE)!" | |
2071 | * errors. | |
2072 | */ | |
40e56410 | 2073 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); |
6a39d7c9 JN |
2074 | if (!hotplug_trigger) { |
2075 | u32 mask = PORTA_HOTPLUG_STATUS_MASK | | |
2076 | PORTD_HOTPLUG_STATUS_MASK | | |
2077 | PORTC_HOTPLUG_STATUS_MASK | | |
2078 | PORTB_HOTPLUG_STATUS_MASK; | |
2079 | dig_hotplug_reg &= ~mask; | |
2080 | } | |
2081 | ||
40e56410 | 2082 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); |
6a39d7c9 JN |
2083 | if (!hotplug_trigger) |
2084 | return; | |
40e56410 VS |
2085 | |
2086 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
2087 | dig_hotplug_reg, hpd, | |
2088 | pch_port_hotplug_long_detect); | |
2089 | ||
91d14251 | 2090 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
40e56410 VS |
2091 | } |
2092 | ||
91d14251 | 2093 | static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) |
776ad806 | 2094 | { |
9db4a9c7 | 2095 | int pipe; |
b543fb04 | 2096 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; |
13cf5504 | 2097 | |
91d14251 | 2098 | ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx); |
91d131d2 | 2099 | |
cfc33bf7 VS |
2100 | if (pch_iir & SDE_AUDIO_POWER_MASK) { |
2101 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> | |
2102 | SDE_AUDIO_POWER_SHIFT); | |
776ad806 | 2103 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
cfc33bf7 VS |
2104 | port_name(port)); |
2105 | } | |
776ad806 | 2106 | |
ce99c256 | 2107 | if (pch_iir & SDE_AUX_MASK) |
91d14251 | 2108 | dp_aux_irq_handler(dev_priv); |
ce99c256 | 2109 | |
776ad806 | 2110 | if (pch_iir & SDE_GMBUS) |
91d14251 | 2111 | gmbus_irq_handler(dev_priv); |
776ad806 JB |
2112 | |
2113 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
2114 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
2115 | ||
2116 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
2117 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
2118 | ||
2119 | if (pch_iir & SDE_POISON) | |
2120 | DRM_ERROR("PCH poison interrupt\n"); | |
2121 | ||
9db4a9c7 | 2122 | if (pch_iir & SDE_FDI_MASK) |
055e393f | 2123 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
2124 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
2125 | pipe_name(pipe), | |
2126 | I915_READ(FDI_RX_IIR(pipe))); | |
776ad806 JB |
2127 | |
2128 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
2129 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
2130 | ||
2131 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
2132 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
2133 | ||
776ad806 | 2134 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
1f7247c0 | 2135 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); |
8664281b PZ |
2136 | |
2137 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
1f7247c0 | 2138 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); |
8664281b PZ |
2139 | } |
2140 | ||
91d14251 | 2141 | static void ivb_err_int_handler(struct drm_i915_private *dev_priv) |
8664281b | 2142 | { |
8664281b | 2143 | u32 err_int = I915_READ(GEN7_ERR_INT); |
5a69b89f | 2144 | enum pipe pipe; |
8664281b | 2145 | |
de032bf4 PZ |
2146 | if (err_int & ERR_INT_POISON) |
2147 | DRM_ERROR("Poison interrupt\n"); | |
2148 | ||
055e393f | 2149 | for_each_pipe(dev_priv, pipe) { |
1f7247c0 DV |
2150 | if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) |
2151 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
8bf1e9f1 | 2152 | |
5a69b89f | 2153 | if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { |
91d14251 TU |
2154 | if (IS_IVYBRIDGE(dev_priv)) |
2155 | ivb_pipe_crc_irq_handler(dev_priv, pipe); | |
5a69b89f | 2156 | else |
91d14251 | 2157 | hsw_pipe_crc_irq_handler(dev_priv, pipe); |
5a69b89f DV |
2158 | } |
2159 | } | |
8bf1e9f1 | 2160 | |
8664281b PZ |
2161 | I915_WRITE(GEN7_ERR_INT, err_int); |
2162 | } | |
2163 | ||
91d14251 | 2164 | static void cpt_serr_int_handler(struct drm_i915_private *dev_priv) |
8664281b | 2165 | { |
8664281b PZ |
2166 | u32 serr_int = I915_READ(SERR_INT); |
2167 | ||
de032bf4 PZ |
2168 | if (serr_int & SERR_INT_POISON) |
2169 | DRM_ERROR("PCH poison interrupt\n"); | |
2170 | ||
8664281b | 2171 | if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) |
1f7247c0 | 2172 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); |
8664281b PZ |
2173 | |
2174 | if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) | |
1f7247c0 | 2175 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); |
8664281b PZ |
2176 | |
2177 | if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) | |
1f7247c0 | 2178 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C); |
8664281b PZ |
2179 | |
2180 | I915_WRITE(SERR_INT, serr_int); | |
776ad806 JB |
2181 | } |
2182 | ||
91d14251 | 2183 | static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) |
23e81d69 | 2184 | { |
23e81d69 | 2185 | int pipe; |
6dbf30ce | 2186 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; |
13cf5504 | 2187 | |
91d14251 | 2188 | ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt); |
91d131d2 | 2189 | |
cfc33bf7 VS |
2190 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { |
2191 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> | |
2192 | SDE_AUDIO_POWER_SHIFT_CPT); | |
2193 | DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", | |
2194 | port_name(port)); | |
2195 | } | |
23e81d69 AJ |
2196 | |
2197 | if (pch_iir & SDE_AUX_MASK_CPT) | |
91d14251 | 2198 | dp_aux_irq_handler(dev_priv); |
23e81d69 AJ |
2199 | |
2200 | if (pch_iir & SDE_GMBUS_CPT) | |
91d14251 | 2201 | gmbus_irq_handler(dev_priv); |
23e81d69 AJ |
2202 | |
2203 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) | |
2204 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); | |
2205 | ||
2206 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) | |
2207 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); | |
2208 | ||
2209 | if (pch_iir & SDE_FDI_MASK_CPT) | |
055e393f | 2210 | for_each_pipe(dev_priv, pipe) |
23e81d69 AJ |
2211 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
2212 | pipe_name(pipe), | |
2213 | I915_READ(FDI_RX_IIR(pipe))); | |
8664281b PZ |
2214 | |
2215 | if (pch_iir & SDE_ERROR_CPT) | |
91d14251 | 2216 | cpt_serr_int_handler(dev_priv); |
23e81d69 AJ |
2217 | } |
2218 | ||
91d14251 | 2219 | static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) |
6dbf30ce | 2220 | { |
6dbf30ce VS |
2221 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT & |
2222 | ~SDE_PORTE_HOTPLUG_SPT; | |
2223 | u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT; | |
2224 | u32 pin_mask = 0, long_mask = 0; | |
2225 | ||
2226 | if (hotplug_trigger) { | |
2227 | u32 dig_hotplug_reg; | |
2228 | ||
2229 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); | |
2230 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
2231 | ||
2232 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
2233 | dig_hotplug_reg, hpd_spt, | |
74c0b395 | 2234 | spt_port_hotplug_long_detect); |
6dbf30ce VS |
2235 | } |
2236 | ||
2237 | if (hotplug2_trigger) { | |
2238 | u32 dig_hotplug_reg; | |
2239 | ||
2240 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2); | |
2241 | I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg); | |
2242 | ||
2243 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger, | |
2244 | dig_hotplug_reg, hpd_spt, | |
2245 | spt_port_hotplug2_long_detect); | |
2246 | } | |
2247 | ||
2248 | if (pin_mask) | |
91d14251 | 2249 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
6dbf30ce VS |
2250 | |
2251 | if (pch_iir & SDE_GMBUS_CPT) | |
91d14251 | 2252 | gmbus_irq_handler(dev_priv); |
6dbf30ce VS |
2253 | } |
2254 | ||
91d14251 TU |
2255 | static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv, |
2256 | u32 hotplug_trigger, | |
40e56410 VS |
2257 | const u32 hpd[HPD_NUM_PINS]) |
2258 | { | |
40e56410 VS |
2259 | u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; |
2260 | ||
2261 | dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL); | |
2262 | I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg); | |
2263 | ||
2264 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
2265 | dig_hotplug_reg, hpd, | |
2266 | ilk_port_hotplug_long_detect); | |
2267 | ||
91d14251 | 2268 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
40e56410 VS |
2269 | } |
2270 | ||
91d14251 TU |
2271 | static void ilk_display_irq_handler(struct drm_i915_private *dev_priv, |
2272 | u32 de_iir) | |
c008bc6e | 2273 | { |
40da17c2 | 2274 | enum pipe pipe; |
e4ce95aa VS |
2275 | u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG; |
2276 | ||
40e56410 | 2277 | if (hotplug_trigger) |
91d14251 | 2278 | ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk); |
c008bc6e PZ |
2279 | |
2280 | if (de_iir & DE_AUX_CHANNEL_A) | |
91d14251 | 2281 | dp_aux_irq_handler(dev_priv); |
c008bc6e PZ |
2282 | |
2283 | if (de_iir & DE_GSE) | |
91d14251 | 2284 | intel_opregion_asle_intr(dev_priv); |
c008bc6e | 2285 | |
c008bc6e PZ |
2286 | if (de_iir & DE_POISON) |
2287 | DRM_ERROR("Poison interrupt\n"); | |
2288 | ||
055e393f | 2289 | for_each_pipe(dev_priv, pipe) { |
5a21b665 DV |
2290 | if (de_iir & DE_PIPE_VBLANK(pipe) && |
2291 | intel_pipe_handle_vblank(dev_priv, pipe)) | |
2292 | intel_check_page_flip(dev_priv, pipe); | |
5b3a856b | 2293 | |
40da17c2 | 2294 | if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) |
1f7247c0 | 2295 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); |
5b3a856b | 2296 | |
40da17c2 | 2297 | if (de_iir & DE_PIPE_CRC_DONE(pipe)) |
91d14251 | 2298 | i9xx_pipe_crc_irq_handler(dev_priv, pipe); |
c008bc6e | 2299 | |
40da17c2 | 2300 | /* plane/pipes map 1:1 on ilk+ */ |
5251f04e | 2301 | if (de_iir & DE_PLANE_FLIP_DONE(pipe)) |
51cbaf01 | 2302 | intel_finish_page_flip_cs(dev_priv, pipe); |
c008bc6e PZ |
2303 | } |
2304 | ||
2305 | /* check event from PCH */ | |
2306 | if (de_iir & DE_PCH_EVENT) { | |
2307 | u32 pch_iir = I915_READ(SDEIIR); | |
2308 | ||
91d14251 TU |
2309 | if (HAS_PCH_CPT(dev_priv)) |
2310 | cpt_irq_handler(dev_priv, pch_iir); | |
c008bc6e | 2311 | else |
91d14251 | 2312 | ibx_irq_handler(dev_priv, pch_iir); |
c008bc6e PZ |
2313 | |
2314 | /* should clear PCH hotplug event before clear CPU irq */ | |
2315 | I915_WRITE(SDEIIR, pch_iir); | |
2316 | } | |
2317 | ||
91d14251 TU |
2318 | if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT) |
2319 | ironlake_rps_change_irq_handler(dev_priv); | |
c008bc6e PZ |
2320 | } |
2321 | ||
91d14251 TU |
2322 | static void ivb_display_irq_handler(struct drm_i915_private *dev_priv, |
2323 | u32 de_iir) | |
9719fb98 | 2324 | { |
07d27e20 | 2325 | enum pipe pipe; |
23bb4cb5 VS |
2326 | u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB; |
2327 | ||
40e56410 | 2328 | if (hotplug_trigger) |
91d14251 | 2329 | ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb); |
9719fb98 PZ |
2330 | |
2331 | if (de_iir & DE_ERR_INT_IVB) | |
91d14251 | 2332 | ivb_err_int_handler(dev_priv); |
9719fb98 PZ |
2333 | |
2334 | if (de_iir & DE_AUX_CHANNEL_A_IVB) | |
91d14251 | 2335 | dp_aux_irq_handler(dev_priv); |
9719fb98 PZ |
2336 | |
2337 | if (de_iir & DE_GSE_IVB) | |
91d14251 | 2338 | intel_opregion_asle_intr(dev_priv); |
9719fb98 | 2339 | |
055e393f | 2340 | for_each_pipe(dev_priv, pipe) { |
5a21b665 DV |
2341 | if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) && |
2342 | intel_pipe_handle_vblank(dev_priv, pipe)) | |
2343 | intel_check_page_flip(dev_priv, pipe); | |
40da17c2 DV |
2344 | |
2345 | /* plane/pipes map 1:1 on ilk+ */ | |
5251f04e | 2346 | if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) |
51cbaf01 | 2347 | intel_finish_page_flip_cs(dev_priv, pipe); |
9719fb98 PZ |
2348 | } |
2349 | ||
2350 | /* check event from PCH */ | |
91d14251 | 2351 | if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) { |
9719fb98 PZ |
2352 | u32 pch_iir = I915_READ(SDEIIR); |
2353 | ||
91d14251 | 2354 | cpt_irq_handler(dev_priv, pch_iir); |
9719fb98 PZ |
2355 | |
2356 | /* clear PCH hotplug event before clear CPU irq */ | |
2357 | I915_WRITE(SDEIIR, pch_iir); | |
2358 | } | |
2359 | } | |
2360 | ||
72c90f62 OM |
2361 | /* |
2362 | * To handle irqs with the minimum potential races with fresh interrupts, we: | |
2363 | * 1 - Disable Master Interrupt Control. | |
2364 | * 2 - Find the source(s) of the interrupt. | |
2365 | * 3 - Clear the Interrupt Identity bits (IIR). | |
2366 | * 4 - Process the interrupt(s) that had bits set in the IIRs. | |
2367 | * 5 - Re-enable Master Interrupt Control. | |
2368 | */ | |
f1af8fc1 | 2369 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
b1f14ad0 | 2370 | { |
45a83f84 | 2371 | struct drm_device *dev = arg; |
fac5e23e | 2372 | struct drm_i915_private *dev_priv = to_i915(dev); |
f1af8fc1 | 2373 | u32 de_iir, gt_iir, de_ier, sde_ier = 0; |
0e43406b | 2374 | irqreturn_t ret = IRQ_NONE; |
b1f14ad0 | 2375 | |
2dd2a883 ID |
2376 | if (!intel_irqs_enabled(dev_priv)) |
2377 | return IRQ_NONE; | |
2378 | ||
1f814dac ID |
2379 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
2380 | disable_rpm_wakeref_asserts(dev_priv); | |
2381 | ||
b1f14ad0 JB |
2382 | /* disable master interrupt before clearing iir */ |
2383 | de_ier = I915_READ(DEIER); | |
2384 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
23a78516 | 2385 | POSTING_READ(DEIER); |
b1f14ad0 | 2386 | |
44498aea PZ |
2387 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
2388 | * interrupts will will be stored on its back queue, and then we'll be | |
2389 | * able to process them after we restore SDEIER (as soon as we restore | |
2390 | * it, we'll get an interrupt if SDEIIR still has something to process | |
2391 | * due to its back queue). */ | |
91d14251 | 2392 | if (!HAS_PCH_NOP(dev_priv)) { |
ab5c608b BW |
2393 | sde_ier = I915_READ(SDEIER); |
2394 | I915_WRITE(SDEIER, 0); | |
2395 | POSTING_READ(SDEIER); | |
2396 | } | |
44498aea | 2397 | |
72c90f62 OM |
2398 | /* Find, clear, then process each source of interrupt */ |
2399 | ||
b1f14ad0 | 2400 | gt_iir = I915_READ(GTIIR); |
0e43406b | 2401 | if (gt_iir) { |
72c90f62 OM |
2402 | I915_WRITE(GTIIR, gt_iir); |
2403 | ret = IRQ_HANDLED; | |
91d14251 | 2404 | if (INTEL_GEN(dev_priv) >= 6) |
261e40b8 | 2405 | snb_gt_irq_handler(dev_priv, gt_iir); |
d8fc8a47 | 2406 | else |
261e40b8 | 2407 | ilk_gt_irq_handler(dev_priv, gt_iir); |
b1f14ad0 JB |
2408 | } |
2409 | ||
0e43406b CW |
2410 | de_iir = I915_READ(DEIIR); |
2411 | if (de_iir) { | |
72c90f62 OM |
2412 | I915_WRITE(DEIIR, de_iir); |
2413 | ret = IRQ_HANDLED; | |
91d14251 TU |
2414 | if (INTEL_GEN(dev_priv) >= 7) |
2415 | ivb_display_irq_handler(dev_priv, de_iir); | |
f1af8fc1 | 2416 | else |
91d14251 | 2417 | ilk_display_irq_handler(dev_priv, de_iir); |
b1f14ad0 JB |
2418 | } |
2419 | ||
91d14251 | 2420 | if (INTEL_GEN(dev_priv) >= 6) { |
f1af8fc1 PZ |
2421 | u32 pm_iir = I915_READ(GEN6_PMIIR); |
2422 | if (pm_iir) { | |
f1af8fc1 PZ |
2423 | I915_WRITE(GEN6_PMIIR, pm_iir); |
2424 | ret = IRQ_HANDLED; | |
72c90f62 | 2425 | gen6_rps_irq_handler(dev_priv, pm_iir); |
f1af8fc1 | 2426 | } |
0e43406b | 2427 | } |
b1f14ad0 | 2428 | |
b1f14ad0 JB |
2429 | I915_WRITE(DEIER, de_ier); |
2430 | POSTING_READ(DEIER); | |
91d14251 | 2431 | if (!HAS_PCH_NOP(dev_priv)) { |
ab5c608b BW |
2432 | I915_WRITE(SDEIER, sde_ier); |
2433 | POSTING_READ(SDEIER); | |
2434 | } | |
b1f14ad0 | 2435 | |
1f814dac ID |
2436 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
2437 | enable_rpm_wakeref_asserts(dev_priv); | |
2438 | ||
b1f14ad0 JB |
2439 | return ret; |
2440 | } | |
2441 | ||
91d14251 TU |
2442 | static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv, |
2443 | u32 hotplug_trigger, | |
40e56410 | 2444 | const u32 hpd[HPD_NUM_PINS]) |
d04a492d | 2445 | { |
cebd87a0 | 2446 | u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; |
d04a492d | 2447 | |
a52bb15b VS |
2448 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); |
2449 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
d04a492d | 2450 | |
cebd87a0 | 2451 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, |
40e56410 | 2452 | dig_hotplug_reg, hpd, |
cebd87a0 | 2453 | bxt_port_hotplug_long_detect); |
40e56410 | 2454 | |
91d14251 | 2455 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
d04a492d SS |
2456 | } |
2457 | ||
f11a0f46 TU |
2458 | static irqreturn_t |
2459 | gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) | |
abd58f01 | 2460 | { |
abd58f01 | 2461 | irqreturn_t ret = IRQ_NONE; |
f11a0f46 | 2462 | u32 iir; |
c42664cc | 2463 | enum pipe pipe; |
88e04703 | 2464 | |
abd58f01 | 2465 | if (master_ctl & GEN8_DE_MISC_IRQ) { |
e32192e1 TU |
2466 | iir = I915_READ(GEN8_DE_MISC_IIR); |
2467 | if (iir) { | |
2468 | I915_WRITE(GEN8_DE_MISC_IIR, iir); | |
abd58f01 | 2469 | ret = IRQ_HANDLED; |
e32192e1 | 2470 | if (iir & GEN8_DE_MISC_GSE) |
91d14251 | 2471 | intel_opregion_asle_intr(dev_priv); |
38cc46d7 OM |
2472 | else |
2473 | DRM_ERROR("Unexpected DE Misc interrupt\n"); | |
abd58f01 | 2474 | } |
38cc46d7 OM |
2475 | else |
2476 | DRM_ERROR("The master control interrupt lied (DE MISC)!\n"); | |
abd58f01 BW |
2477 | } |
2478 | ||
6d766f02 | 2479 | if (master_ctl & GEN8_DE_PORT_IRQ) { |
e32192e1 TU |
2480 | iir = I915_READ(GEN8_DE_PORT_IIR); |
2481 | if (iir) { | |
2482 | u32 tmp_mask; | |
d04a492d | 2483 | bool found = false; |
cebd87a0 | 2484 | |
e32192e1 | 2485 | I915_WRITE(GEN8_DE_PORT_IIR, iir); |
6d766f02 | 2486 | ret = IRQ_HANDLED; |
88e04703 | 2487 | |
e32192e1 TU |
2488 | tmp_mask = GEN8_AUX_CHANNEL_A; |
2489 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2490 | tmp_mask |= GEN9_AUX_CHANNEL_B | | |
2491 | GEN9_AUX_CHANNEL_C | | |
2492 | GEN9_AUX_CHANNEL_D; | |
2493 | ||
2494 | if (iir & tmp_mask) { | |
91d14251 | 2495 | dp_aux_irq_handler(dev_priv); |
d04a492d SS |
2496 | found = true; |
2497 | } | |
2498 | ||
cc3f90f0 | 2499 | if (IS_GEN9_LP(dev_priv)) { |
e32192e1 TU |
2500 | tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK; |
2501 | if (tmp_mask) { | |
91d14251 TU |
2502 | bxt_hpd_irq_handler(dev_priv, tmp_mask, |
2503 | hpd_bxt); | |
e32192e1 TU |
2504 | found = true; |
2505 | } | |
2506 | } else if (IS_BROADWELL(dev_priv)) { | |
2507 | tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG; | |
2508 | if (tmp_mask) { | |
91d14251 TU |
2509 | ilk_hpd_irq_handler(dev_priv, |
2510 | tmp_mask, hpd_bdw); | |
e32192e1 TU |
2511 | found = true; |
2512 | } | |
d04a492d SS |
2513 | } |
2514 | ||
cc3f90f0 | 2515 | if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) { |
91d14251 | 2516 | gmbus_irq_handler(dev_priv); |
9e63743e SS |
2517 | found = true; |
2518 | } | |
2519 | ||
d04a492d | 2520 | if (!found) |
38cc46d7 | 2521 | DRM_ERROR("Unexpected DE Port interrupt\n"); |
6d766f02 | 2522 | } |
38cc46d7 OM |
2523 | else |
2524 | DRM_ERROR("The master control interrupt lied (DE PORT)!\n"); | |
6d766f02 DV |
2525 | } |
2526 | ||
055e393f | 2527 | for_each_pipe(dev_priv, pipe) { |
e32192e1 | 2528 | u32 flip_done, fault_errors; |
abd58f01 | 2529 | |
c42664cc DV |
2530 | if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) |
2531 | continue; | |
abd58f01 | 2532 | |
e32192e1 TU |
2533 | iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); |
2534 | if (!iir) { | |
2535 | DRM_ERROR("The master control interrupt lied (DE PIPE)!\n"); | |
2536 | continue; | |
2537 | } | |
770de83d | 2538 | |
e32192e1 TU |
2539 | ret = IRQ_HANDLED; |
2540 | I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir); | |
38cc46d7 | 2541 | |
5a21b665 DV |
2542 | if (iir & GEN8_PIPE_VBLANK && |
2543 | intel_pipe_handle_vblank(dev_priv, pipe)) | |
2544 | intel_check_page_flip(dev_priv, pipe); | |
770de83d | 2545 | |
e32192e1 TU |
2546 | flip_done = iir; |
2547 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2548 | flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE; | |
2549 | else | |
2550 | flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE; | |
38cc46d7 | 2551 | |
5251f04e | 2552 | if (flip_done) |
51cbaf01 | 2553 | intel_finish_page_flip_cs(dev_priv, pipe); |
38cc46d7 | 2554 | |
e32192e1 | 2555 | if (iir & GEN8_PIPE_CDCLK_CRC_DONE) |
91d14251 | 2556 | hsw_pipe_crc_irq_handler(dev_priv, pipe); |
38cc46d7 | 2557 | |
e32192e1 TU |
2558 | if (iir & GEN8_PIPE_FIFO_UNDERRUN) |
2559 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
770de83d | 2560 | |
e32192e1 TU |
2561 | fault_errors = iir; |
2562 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2563 | fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS; | |
2564 | else | |
2565 | fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
770de83d | 2566 | |
e32192e1 | 2567 | if (fault_errors) |
1353ec38 | 2568 | DRM_ERROR("Fault errors on pipe %c: 0x%08x\n", |
e32192e1 TU |
2569 | pipe_name(pipe), |
2570 | fault_errors); | |
abd58f01 BW |
2571 | } |
2572 | ||
91d14251 | 2573 | if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) && |
266ea3d9 | 2574 | master_ctl & GEN8_DE_PCH_IRQ) { |
92d03a80 DV |
2575 | /* |
2576 | * FIXME(BDW): Assume for now that the new interrupt handling | |
2577 | * scheme also closed the SDE interrupt handling race we've seen | |
2578 | * on older pch-split platforms. But this needs testing. | |
2579 | */ | |
e32192e1 TU |
2580 | iir = I915_READ(SDEIIR); |
2581 | if (iir) { | |
2582 | I915_WRITE(SDEIIR, iir); | |
92d03a80 | 2583 | ret = IRQ_HANDLED; |
6dbf30ce | 2584 | |
22dea0be | 2585 | if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv)) |
91d14251 | 2586 | spt_irq_handler(dev_priv, iir); |
6dbf30ce | 2587 | else |
91d14251 | 2588 | cpt_irq_handler(dev_priv, iir); |
2dfb0b81 JN |
2589 | } else { |
2590 | /* | |
2591 | * Like on previous PCH there seems to be something | |
2592 | * fishy going on with forwarding PCH interrupts. | |
2593 | */ | |
2594 | DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n"); | |
2595 | } | |
92d03a80 DV |
2596 | } |
2597 | ||
f11a0f46 TU |
2598 | return ret; |
2599 | } | |
2600 | ||
2601 | static irqreturn_t gen8_irq_handler(int irq, void *arg) | |
2602 | { | |
2603 | struct drm_device *dev = arg; | |
fac5e23e | 2604 | struct drm_i915_private *dev_priv = to_i915(dev); |
f11a0f46 | 2605 | u32 master_ctl; |
e30e251a | 2606 | u32 gt_iir[4] = {}; |
f11a0f46 TU |
2607 | irqreturn_t ret; |
2608 | ||
2609 | if (!intel_irqs_enabled(dev_priv)) | |
2610 | return IRQ_NONE; | |
2611 | ||
2612 | master_ctl = I915_READ_FW(GEN8_MASTER_IRQ); | |
2613 | master_ctl &= ~GEN8_MASTER_IRQ_CONTROL; | |
2614 | if (!master_ctl) | |
2615 | return IRQ_NONE; | |
2616 | ||
2617 | I915_WRITE_FW(GEN8_MASTER_IRQ, 0); | |
2618 | ||
2619 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ | |
2620 | disable_rpm_wakeref_asserts(dev_priv); | |
2621 | ||
2622 | /* Find, clear, then process each source of interrupt */ | |
e30e251a VS |
2623 | ret = gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir); |
2624 | gen8_gt_irq_handler(dev_priv, gt_iir); | |
f11a0f46 TU |
2625 | ret |= gen8_de_irq_handler(dev_priv, master_ctl); |
2626 | ||
cb0d205e CW |
2627 | I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
2628 | POSTING_READ_FW(GEN8_MASTER_IRQ); | |
abd58f01 | 2629 | |
1f814dac ID |
2630 | enable_rpm_wakeref_asserts(dev_priv); |
2631 | ||
abd58f01 BW |
2632 | return ret; |
2633 | } | |
2634 | ||
8a905236 | 2635 | /** |
b8d24a06 | 2636 | * i915_reset_and_wakeup - do process context error handling work |
14bb2c11 | 2637 | * @dev_priv: i915 device private |
8a905236 JB |
2638 | * |
2639 | * Fire an error uevent so userspace can see that a hang or error | |
2640 | * was detected. | |
2641 | */ | |
c033666a | 2642 | static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv) |
8a905236 | 2643 | { |
91c8a326 | 2644 | struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj; |
cce723ed BW |
2645 | char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; |
2646 | char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; | |
2647 | char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; | |
8a905236 | 2648 | |
c033666a | 2649 | kobject_uevent_env(kobj, KOBJ_CHANGE, error_event); |
f316a42c | 2650 | |
8af29b0c CW |
2651 | DRM_DEBUG_DRIVER("resetting chip\n"); |
2652 | kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event); | |
2653 | ||
8af29b0c | 2654 | intel_prepare_reset(dev_priv); |
7514747d | 2655 | |
8c185eca CW |
2656 | set_bit(I915_RESET_HANDOFF, &dev_priv->gpu_error.flags); |
2657 | wake_up_all(&dev_priv->gpu_error.wait_queue); | |
2658 | ||
780f262a CW |
2659 | do { |
2660 | /* | |
2661 | * All state reset _must_ be completed before we update the | |
2662 | * reset counter, for otherwise waiters might miss the reset | |
2663 | * pending state and not properly drop locks, resulting in | |
2664 | * deadlocks with the reset work. | |
2665 | */ | |
2666 | if (mutex_trylock(&dev_priv->drm.struct_mutex)) { | |
2667 | i915_reset(dev_priv); | |
2668 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
2669 | } | |
f69061be | 2670 | |
780f262a CW |
2671 | /* We need to wait for anyone holding the lock to wakeup */ |
2672 | } while (wait_on_bit_timeout(&dev_priv->gpu_error.flags, | |
8c185eca | 2673 | I915_RESET_HANDOFF, |
780f262a CW |
2674 | TASK_UNINTERRUPTIBLE, |
2675 | HZ)); | |
17e1df07 | 2676 | |
780f262a | 2677 | intel_finish_reset(dev_priv); |
f454c694 | 2678 | |
780f262a | 2679 | if (!test_bit(I915_WEDGED, &dev_priv->gpu_error.flags)) |
8af29b0c CW |
2680 | kobject_uevent_env(kobj, |
2681 | KOBJ_CHANGE, reset_done_event); | |
1f83fee0 | 2682 | |
8af29b0c CW |
2683 | /* |
2684 | * Note: The wake_up also serves as a memory barrier so that | |
2685 | * waiters see the updated value of the dev_priv->gpu_error. | |
2686 | */ | |
8c185eca | 2687 | clear_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags); |
8af29b0c | 2688 | wake_up_all(&dev_priv->gpu_error.reset_queue); |
8a905236 JB |
2689 | } |
2690 | ||
d636951e BW |
2691 | static inline void |
2692 | i915_err_print_instdone(struct drm_i915_private *dev_priv, | |
2693 | struct intel_instdone *instdone) | |
2694 | { | |
f9e61372 BW |
2695 | int slice; |
2696 | int subslice; | |
2697 | ||
d636951e BW |
2698 | pr_err(" INSTDONE: 0x%08x\n", instdone->instdone); |
2699 | ||
2700 | if (INTEL_GEN(dev_priv) <= 3) | |
2701 | return; | |
2702 | ||
2703 | pr_err(" SC_INSTDONE: 0x%08x\n", instdone->slice_common); | |
2704 | ||
2705 | if (INTEL_GEN(dev_priv) <= 6) | |
2706 | return; | |
2707 | ||
f9e61372 BW |
2708 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) |
2709 | pr_err(" SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", | |
2710 | slice, subslice, instdone->sampler[slice][subslice]); | |
2711 | ||
2712 | for_each_instdone_slice_subslice(dev_priv, slice, subslice) | |
2713 | pr_err(" ROW_INSTDONE[%d][%d]: 0x%08x\n", | |
2714 | slice, subslice, instdone->row[slice][subslice]); | |
d636951e BW |
2715 | } |
2716 | ||
eaa14c24 | 2717 | static void i915_clear_error_registers(struct drm_i915_private *dev_priv) |
8a905236 | 2718 | { |
eaa14c24 | 2719 | u32 eir; |
8a905236 | 2720 | |
eaa14c24 CW |
2721 | if (!IS_GEN2(dev_priv)) |
2722 | I915_WRITE(PGTBL_ER, I915_READ(PGTBL_ER)); | |
8a905236 | 2723 | |
eaa14c24 CW |
2724 | if (INTEL_GEN(dev_priv) < 4) |
2725 | I915_WRITE(IPEIR, I915_READ(IPEIR)); | |
2726 | else | |
2727 | I915_WRITE(IPEIR_I965, I915_READ(IPEIR_I965)); | |
8a905236 | 2728 | |
eaa14c24 | 2729 | I915_WRITE(EIR, I915_READ(EIR)); |
8a905236 JB |
2730 | eir = I915_READ(EIR); |
2731 | if (eir) { | |
2732 | /* | |
2733 | * some errors might have become stuck, | |
2734 | * mask them. | |
2735 | */ | |
eaa14c24 | 2736 | DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir); |
8a905236 JB |
2737 | I915_WRITE(EMR, I915_READ(EMR) | eir); |
2738 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2739 | } | |
35aed2e6 CW |
2740 | } |
2741 | ||
2742 | /** | |
b8d24a06 | 2743 | * i915_handle_error - handle a gpu error |
14bb2c11 | 2744 | * @dev_priv: i915 device private |
14b730fc | 2745 | * @engine_mask: mask representing engines that are hung |
87c390b6 MT |
2746 | * @fmt: Error message format string |
2747 | * | |
aafd8581 | 2748 | * Do some basic checking of register state at error time and |
35aed2e6 CW |
2749 | * dump it to the syslog. Also call i915_capture_error_state() to make |
2750 | * sure we get a record and make it available in debugfs. Fire a uevent | |
2751 | * so userspace knows something bad happened (should trigger collection | |
2752 | * of a ring dump etc.). | |
2753 | */ | |
c033666a CW |
2754 | void i915_handle_error(struct drm_i915_private *dev_priv, |
2755 | u32 engine_mask, | |
58174462 | 2756 | const char *fmt, ...) |
35aed2e6 | 2757 | { |
58174462 MK |
2758 | va_list args; |
2759 | char error_msg[80]; | |
35aed2e6 | 2760 | |
58174462 MK |
2761 | va_start(args, fmt); |
2762 | vscnprintf(error_msg, sizeof(error_msg), fmt, args); | |
2763 | va_end(args); | |
2764 | ||
1604a86d CW |
2765 | /* |
2766 | * In most cases it's guaranteed that we get here with an RPM | |
2767 | * reference held, for example because there is a pending GPU | |
2768 | * request that won't finish until the reset is done. This | |
2769 | * isn't the case at least when we get here by doing a | |
2770 | * simulated reset via debugfs, so get an RPM reference. | |
2771 | */ | |
2772 | intel_runtime_pm_get(dev_priv); | |
2773 | ||
c033666a | 2774 | i915_capture_error_state(dev_priv, engine_mask, error_msg); |
eaa14c24 | 2775 | i915_clear_error_registers(dev_priv); |
8a905236 | 2776 | |
8af29b0c | 2777 | if (!engine_mask) |
1604a86d | 2778 | goto out; |
ba1234d1 | 2779 | |
8c185eca | 2780 | if (test_and_set_bit(I915_RESET_BACKOFF, |
8af29b0c | 2781 | &dev_priv->gpu_error.flags)) |
1604a86d | 2782 | goto out; |
8af29b0c | 2783 | |
c033666a | 2784 | i915_reset_and_wakeup(dev_priv); |
1604a86d CW |
2785 | |
2786 | out: | |
2787 | intel_runtime_pm_put(dev_priv); | |
8a905236 JB |
2788 | } |
2789 | ||
42f52ef8 KP |
2790 | /* Called from drm generic code, passed 'crtc' which |
2791 | * we use as a pipe index | |
2792 | */ | |
86e83e35 | 2793 | static int i8xx_enable_vblank(struct drm_device *dev, unsigned int pipe) |
0a3e67a4 | 2794 | { |
fac5e23e | 2795 | struct drm_i915_private *dev_priv = to_i915(dev); |
e9d21d7f | 2796 | unsigned long irqflags; |
71e0ffa5 | 2797 | |
1ec14ad3 | 2798 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
86e83e35 | 2799 | i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS); |
1ec14ad3 | 2800 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
8692d00e | 2801 | |
0a3e67a4 JB |
2802 | return 0; |
2803 | } | |
2804 | ||
86e83e35 | 2805 | static int i965_enable_vblank(struct drm_device *dev, unsigned int pipe) |
f796cf8f | 2806 | { |
fac5e23e | 2807 | struct drm_i915_private *dev_priv = to_i915(dev); |
f796cf8f JB |
2808 | unsigned long irqflags; |
2809 | ||
f796cf8f | 2810 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
86e83e35 CW |
2811 | i915_enable_pipestat(dev_priv, pipe, |
2812 | PIPE_START_VBLANK_INTERRUPT_STATUS); | |
b1f14ad0 JB |
2813 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2814 | ||
2815 | return 0; | |
2816 | } | |
2817 | ||
86e83e35 | 2818 | static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe) |
7e231dbe | 2819 | { |
fac5e23e | 2820 | struct drm_i915_private *dev_priv = to_i915(dev); |
7e231dbe | 2821 | unsigned long irqflags; |
55b8f2a7 | 2822 | uint32_t bit = INTEL_GEN(dev_priv) >= 7 ? |
86e83e35 | 2823 | DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); |
7e231dbe | 2824 | |
7e231dbe | 2825 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
86e83e35 | 2826 | ilk_enable_display_irq(dev_priv, bit); |
7e231dbe JB |
2827 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2828 | ||
2829 | return 0; | |
2830 | } | |
2831 | ||
88e72717 | 2832 | static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe) |
abd58f01 | 2833 | { |
fac5e23e | 2834 | struct drm_i915_private *dev_priv = to_i915(dev); |
abd58f01 | 2835 | unsigned long irqflags; |
abd58f01 | 2836 | |
abd58f01 | 2837 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
013d3752 | 2838 | bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); |
abd58f01 | 2839 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
013d3752 | 2840 | |
abd58f01 BW |
2841 | return 0; |
2842 | } | |
2843 | ||
42f52ef8 KP |
2844 | /* Called from drm generic code, passed 'crtc' which |
2845 | * we use as a pipe index | |
2846 | */ | |
86e83e35 | 2847 | static void i8xx_disable_vblank(struct drm_device *dev, unsigned int pipe) |
0a3e67a4 | 2848 | { |
fac5e23e | 2849 | struct drm_i915_private *dev_priv = to_i915(dev); |
e9d21d7f | 2850 | unsigned long irqflags; |
0a3e67a4 | 2851 | |
1ec14ad3 | 2852 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
86e83e35 | 2853 | i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS); |
f796cf8f JB |
2854 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2855 | } | |
2856 | ||
86e83e35 | 2857 | static void i965_disable_vblank(struct drm_device *dev, unsigned int pipe) |
f796cf8f | 2858 | { |
fac5e23e | 2859 | struct drm_i915_private *dev_priv = to_i915(dev); |
f796cf8f JB |
2860 | unsigned long irqflags; |
2861 | ||
2862 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
86e83e35 CW |
2863 | i915_disable_pipestat(dev_priv, pipe, |
2864 | PIPE_START_VBLANK_INTERRUPT_STATUS); | |
b1f14ad0 JB |
2865 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2866 | } | |
2867 | ||
86e83e35 | 2868 | static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe) |
7e231dbe | 2869 | { |
fac5e23e | 2870 | struct drm_i915_private *dev_priv = to_i915(dev); |
7e231dbe | 2871 | unsigned long irqflags; |
55b8f2a7 | 2872 | uint32_t bit = INTEL_GEN(dev_priv) >= 7 ? |
86e83e35 | 2873 | DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); |
7e231dbe JB |
2874 | |
2875 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
86e83e35 | 2876 | ilk_disable_display_irq(dev_priv, bit); |
7e231dbe JB |
2877 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2878 | } | |
2879 | ||
88e72717 | 2880 | static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe) |
abd58f01 | 2881 | { |
fac5e23e | 2882 | struct drm_i915_private *dev_priv = to_i915(dev); |
abd58f01 | 2883 | unsigned long irqflags; |
abd58f01 | 2884 | |
abd58f01 | 2885 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
013d3752 | 2886 | bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); |
abd58f01 BW |
2887 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2888 | } | |
2889 | ||
b243f530 | 2890 | static void ibx_irq_reset(struct drm_i915_private *dev_priv) |
91738a95 | 2891 | { |
6e266956 | 2892 | if (HAS_PCH_NOP(dev_priv)) |
91738a95 PZ |
2893 | return; |
2894 | ||
f86f3fb0 | 2895 | GEN5_IRQ_RESET(SDE); |
105b122e | 2896 | |
6e266956 | 2897 | if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv)) |
105b122e | 2898 | I915_WRITE(SERR_INT, 0xffffffff); |
622364b6 | 2899 | } |
105b122e | 2900 | |
622364b6 PZ |
2901 | /* |
2902 | * SDEIER is also touched by the interrupt handler to work around missed PCH | |
2903 | * interrupts. Hence we can't update it after the interrupt handler is enabled - | |
2904 | * instead we unconditionally enable all PCH interrupt sources here, but then | |
2905 | * only unmask them as needed with SDEIMR. | |
2906 | * | |
2907 | * This function needs to be called before interrupts are enabled. | |
2908 | */ | |
2909 | static void ibx_irq_pre_postinstall(struct drm_device *dev) | |
2910 | { | |
fac5e23e | 2911 | struct drm_i915_private *dev_priv = to_i915(dev); |
622364b6 | 2912 | |
6e266956 | 2913 | if (HAS_PCH_NOP(dev_priv)) |
622364b6 PZ |
2914 | return; |
2915 | ||
2916 | WARN_ON(I915_READ(SDEIER) != 0); | |
91738a95 PZ |
2917 | I915_WRITE(SDEIER, 0xffffffff); |
2918 | POSTING_READ(SDEIER); | |
2919 | } | |
2920 | ||
b243f530 | 2921 | static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv) |
d18ea1b5 | 2922 | { |
f86f3fb0 | 2923 | GEN5_IRQ_RESET(GT); |
b243f530 | 2924 | if (INTEL_GEN(dev_priv) >= 6) |
f86f3fb0 | 2925 | GEN5_IRQ_RESET(GEN6_PM); |
d18ea1b5 DV |
2926 | } |
2927 | ||
70591a41 VS |
2928 | static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) |
2929 | { | |
2930 | enum pipe pipe; | |
2931 | ||
71b8b41d VS |
2932 | if (IS_CHERRYVIEW(dev_priv)) |
2933 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV); | |
2934 | else | |
2935 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); | |
2936 | ||
ad22d106 | 2937 | i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0); |
70591a41 VS |
2938 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
2939 | ||
ad22d106 VS |
2940 | for_each_pipe(dev_priv, pipe) { |
2941 | I915_WRITE(PIPESTAT(pipe), | |
2942 | PIPE_FIFO_UNDERRUN_STATUS | | |
2943 | PIPESTAT_INT_STATUS_MASK); | |
2944 | dev_priv->pipestat_irq_mask[pipe] = 0; | |
2945 | } | |
70591a41 VS |
2946 | |
2947 | GEN5_IRQ_RESET(VLV_); | |
ad22d106 | 2948 | dev_priv->irq_mask = ~0; |
70591a41 VS |
2949 | } |
2950 | ||
8bb61306 VS |
2951 | static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) |
2952 | { | |
2953 | u32 pipestat_mask; | |
9ab981f2 | 2954 | u32 enable_mask; |
8bb61306 VS |
2955 | enum pipe pipe; |
2956 | ||
8bb61306 VS |
2957 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | |
2958 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
2959 | ||
2960 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); | |
2961 | for_each_pipe(dev_priv, pipe) | |
2962 | i915_enable_pipestat(dev_priv, pipe, pipestat_mask); | |
2963 | ||
9ab981f2 VS |
2964 | enable_mask = I915_DISPLAY_PORT_INTERRUPT | |
2965 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
9bd95909 VS |
2966 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
2967 | I915_LPE_PIPE_A_INTERRUPT | | |
2968 | I915_LPE_PIPE_B_INTERRUPT; | |
2969 | ||
8bb61306 | 2970 | if (IS_CHERRYVIEW(dev_priv)) |
9bd95909 VS |
2971 | enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT | |
2972 | I915_LPE_PIPE_C_INTERRUPT; | |
6b7eafc1 VS |
2973 | |
2974 | WARN_ON(dev_priv->irq_mask != ~0); | |
2975 | ||
9ab981f2 VS |
2976 | dev_priv->irq_mask = ~enable_mask; |
2977 | ||
2978 | GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask); | |
8bb61306 VS |
2979 | } |
2980 | ||
2981 | /* drm_dma.h hooks | |
2982 | */ | |
2983 | static void ironlake_irq_reset(struct drm_device *dev) | |
2984 | { | |
fac5e23e | 2985 | struct drm_i915_private *dev_priv = to_i915(dev); |
8bb61306 VS |
2986 | |
2987 | I915_WRITE(HWSTAM, 0xffffffff); | |
2988 | ||
2989 | GEN5_IRQ_RESET(DE); | |
5db94019 | 2990 | if (IS_GEN7(dev_priv)) |
8bb61306 VS |
2991 | I915_WRITE(GEN7_ERR_INT, 0xffffffff); |
2992 | ||
b243f530 | 2993 | gen5_gt_irq_reset(dev_priv); |
8bb61306 | 2994 | |
b243f530 | 2995 | ibx_irq_reset(dev_priv); |
8bb61306 VS |
2996 | } |
2997 | ||
7e231dbe JB |
2998 | static void valleyview_irq_preinstall(struct drm_device *dev) |
2999 | { | |
fac5e23e | 3000 | struct drm_i915_private *dev_priv = to_i915(dev); |
7e231dbe | 3001 | |
34c7b8a7 VS |
3002 | I915_WRITE(VLV_MASTER_IER, 0); |
3003 | POSTING_READ(VLV_MASTER_IER); | |
3004 | ||
b243f530 | 3005 | gen5_gt_irq_reset(dev_priv); |
7e231dbe | 3006 | |
ad22d106 | 3007 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3008 | if (dev_priv->display_irqs_enabled) |
3009 | vlv_display_irq_reset(dev_priv); | |
ad22d106 | 3010 | spin_unlock_irq(&dev_priv->irq_lock); |
7e231dbe JB |
3011 | } |
3012 | ||
d6e3cca3 DV |
3013 | static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv) |
3014 | { | |
3015 | GEN8_IRQ_RESET_NDX(GT, 0); | |
3016 | GEN8_IRQ_RESET_NDX(GT, 1); | |
3017 | GEN8_IRQ_RESET_NDX(GT, 2); | |
3018 | GEN8_IRQ_RESET_NDX(GT, 3); | |
3019 | } | |
3020 | ||
823f6b38 | 3021 | static void gen8_irq_reset(struct drm_device *dev) |
abd58f01 | 3022 | { |
fac5e23e | 3023 | struct drm_i915_private *dev_priv = to_i915(dev); |
abd58f01 BW |
3024 | int pipe; |
3025 | ||
abd58f01 BW |
3026 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
3027 | POSTING_READ(GEN8_MASTER_IRQ); | |
3028 | ||
d6e3cca3 | 3029 | gen8_gt_irq_reset(dev_priv); |
abd58f01 | 3030 | |
055e393f | 3031 | for_each_pipe(dev_priv, pipe) |
f458ebbc DV |
3032 | if (intel_display_power_is_enabled(dev_priv, |
3033 | POWER_DOMAIN_PIPE(pipe))) | |
813bde43 | 3034 | GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); |
abd58f01 | 3035 | |
f86f3fb0 PZ |
3036 | GEN5_IRQ_RESET(GEN8_DE_PORT_); |
3037 | GEN5_IRQ_RESET(GEN8_DE_MISC_); | |
3038 | GEN5_IRQ_RESET(GEN8_PCU_); | |
abd58f01 | 3039 | |
6e266956 | 3040 | if (HAS_PCH_SPLIT(dev_priv)) |
b243f530 | 3041 | ibx_irq_reset(dev_priv); |
abd58f01 | 3042 | } |
09f2344d | 3043 | |
4c6c03be DL |
3044 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, |
3045 | unsigned int pipe_mask) | |
d49bdb0e | 3046 | { |
1180e206 | 3047 | uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; |
6831f3e3 | 3048 | enum pipe pipe; |
d49bdb0e | 3049 | |
13321786 | 3050 | spin_lock_irq(&dev_priv->irq_lock); |
6831f3e3 VS |
3051 | for_each_pipe_masked(dev_priv, pipe, pipe_mask) |
3052 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, | |
3053 | dev_priv->de_irq_mask[pipe], | |
3054 | ~dev_priv->de_irq_mask[pipe] | extra_ier); | |
13321786 | 3055 | spin_unlock_irq(&dev_priv->irq_lock); |
d49bdb0e PZ |
3056 | } |
3057 | ||
aae8ba84 VS |
3058 | void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, |
3059 | unsigned int pipe_mask) | |
3060 | { | |
6831f3e3 VS |
3061 | enum pipe pipe; |
3062 | ||
aae8ba84 | 3063 | spin_lock_irq(&dev_priv->irq_lock); |
6831f3e3 VS |
3064 | for_each_pipe_masked(dev_priv, pipe, pipe_mask) |
3065 | GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); | |
aae8ba84 VS |
3066 | spin_unlock_irq(&dev_priv->irq_lock); |
3067 | ||
3068 | /* make sure we're done processing display irqs */ | |
91c8a326 | 3069 | synchronize_irq(dev_priv->drm.irq); |
aae8ba84 VS |
3070 | } |
3071 | ||
43f328d7 VS |
3072 | static void cherryview_irq_preinstall(struct drm_device *dev) |
3073 | { | |
fac5e23e | 3074 | struct drm_i915_private *dev_priv = to_i915(dev); |
43f328d7 VS |
3075 | |
3076 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3077 | POSTING_READ(GEN8_MASTER_IRQ); | |
3078 | ||
d6e3cca3 | 3079 | gen8_gt_irq_reset(dev_priv); |
43f328d7 VS |
3080 | |
3081 | GEN5_IRQ_RESET(GEN8_PCU_); | |
3082 | ||
ad22d106 | 3083 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3084 | if (dev_priv->display_irqs_enabled) |
3085 | vlv_display_irq_reset(dev_priv); | |
ad22d106 | 3086 | spin_unlock_irq(&dev_priv->irq_lock); |
43f328d7 VS |
3087 | } |
3088 | ||
91d14251 | 3089 | static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv, |
87a02106 VS |
3090 | const u32 hpd[HPD_NUM_PINS]) |
3091 | { | |
87a02106 VS |
3092 | struct intel_encoder *encoder; |
3093 | u32 enabled_irqs = 0; | |
3094 | ||
91c8a326 | 3095 | for_each_intel_encoder(&dev_priv->drm, encoder) |
87a02106 VS |
3096 | if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED) |
3097 | enabled_irqs |= hpd[encoder->hpd_pin]; | |
3098 | ||
3099 | return enabled_irqs; | |
3100 | } | |
3101 | ||
1a56b1a2 | 3102 | static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv) |
7fe0b973 | 3103 | { |
1a56b1a2 | 3104 | u32 hotplug; |
82a28bcf DV |
3105 | |
3106 | /* | |
3107 | * Enable digital hotplug on the PCH, and configure the DP short pulse | |
6dbf30ce VS |
3108 | * duration to 2ms (which is the minimum in the Display Port spec). |
3109 | * The pulse duration bits are reserved on LPT+. | |
82a28bcf | 3110 | */ |
7fe0b973 | 3111 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
1a56b1a2 ID |
3112 | hotplug &= ~(PORTB_PULSE_DURATION_MASK | |
3113 | PORTC_PULSE_DURATION_MASK | | |
3114 | PORTD_PULSE_DURATION_MASK); | |
7fe0b973 | 3115 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; |
1a56b1a2 ID |
3116 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; |
3117 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; | |
0b2eb33e VS |
3118 | /* |
3119 | * When CPU and PCH are on the same package, port A | |
3120 | * HPD must be enabled in both north and south. | |
3121 | */ | |
91d14251 | 3122 | if (HAS_PCH_LPT_LP(dev_priv)) |
0b2eb33e | 3123 | hotplug |= PORTA_HOTPLUG_ENABLE; |
7fe0b973 | 3124 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
6dbf30ce | 3125 | } |
26951caf | 3126 | |
1a56b1a2 ID |
3127 | static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv) |
3128 | { | |
3129 | u32 hotplug_irqs, enabled_irqs; | |
3130 | ||
3131 | if (HAS_PCH_IBX(dev_priv)) { | |
3132 | hotplug_irqs = SDE_HOTPLUG_MASK; | |
3133 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx); | |
3134 | } else { | |
3135 | hotplug_irqs = SDE_HOTPLUG_MASK_CPT; | |
3136 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt); | |
3137 | } | |
3138 | ||
3139 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); | |
3140 | ||
3141 | ibx_hpd_detection_setup(dev_priv); | |
3142 | } | |
3143 | ||
2a57d9cc | 3144 | static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv) |
6dbf30ce | 3145 | { |
2a57d9cc | 3146 | u32 hotplug; |
6dbf30ce VS |
3147 | |
3148 | /* Enable digital hotplug on the PCH */ | |
3149 | hotplug = I915_READ(PCH_PORT_HOTPLUG); | |
2a57d9cc ID |
3150 | hotplug |= PORTA_HOTPLUG_ENABLE | |
3151 | PORTB_HOTPLUG_ENABLE | | |
3152 | PORTC_HOTPLUG_ENABLE | | |
3153 | PORTD_HOTPLUG_ENABLE; | |
6dbf30ce VS |
3154 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
3155 | ||
3156 | hotplug = I915_READ(PCH_PORT_HOTPLUG2); | |
3157 | hotplug |= PORTE_HOTPLUG_ENABLE; | |
3158 | I915_WRITE(PCH_PORT_HOTPLUG2, hotplug); | |
7fe0b973 KP |
3159 | } |
3160 | ||
2a57d9cc ID |
3161 | static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv) |
3162 | { | |
3163 | u32 hotplug_irqs, enabled_irqs; | |
3164 | ||
3165 | hotplug_irqs = SDE_HOTPLUG_MASK_SPT; | |
3166 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt); | |
3167 | ||
3168 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); | |
3169 | ||
3170 | spt_hpd_detection_setup(dev_priv); | |
3171 | } | |
3172 | ||
1a56b1a2 ID |
3173 | static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv) |
3174 | { | |
3175 | u32 hotplug; | |
3176 | ||
3177 | /* | |
3178 | * Enable digital hotplug on the CPU, and configure the DP short pulse | |
3179 | * duration to 2ms (which is the minimum in the Display Port spec) | |
3180 | * The pulse duration bits are reserved on HSW+. | |
3181 | */ | |
3182 | hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL); | |
3183 | hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK; | |
3184 | hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | | |
3185 | DIGITAL_PORTA_PULSE_DURATION_2ms; | |
3186 | I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug); | |
3187 | } | |
3188 | ||
91d14251 | 3189 | static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv) |
e4ce95aa | 3190 | { |
1a56b1a2 | 3191 | u32 hotplug_irqs, enabled_irqs; |
e4ce95aa | 3192 | |
91d14251 | 3193 | if (INTEL_GEN(dev_priv) >= 8) { |
3a3b3c7d | 3194 | hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG; |
91d14251 | 3195 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw); |
3a3b3c7d VS |
3196 | |
3197 | bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); | |
91d14251 | 3198 | } else if (INTEL_GEN(dev_priv) >= 7) { |
23bb4cb5 | 3199 | hotplug_irqs = DE_DP_A_HOTPLUG_IVB; |
91d14251 | 3200 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb); |
3a3b3c7d VS |
3201 | |
3202 | ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); | |
23bb4cb5 VS |
3203 | } else { |
3204 | hotplug_irqs = DE_DP_A_HOTPLUG; | |
91d14251 | 3205 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk); |
e4ce95aa | 3206 | |
3a3b3c7d VS |
3207 | ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); |
3208 | } | |
e4ce95aa | 3209 | |
1a56b1a2 | 3210 | ilk_hpd_detection_setup(dev_priv); |
e4ce95aa | 3211 | |
91d14251 | 3212 | ibx_hpd_irq_setup(dev_priv); |
e4ce95aa VS |
3213 | } |
3214 | ||
2a57d9cc ID |
3215 | static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv, |
3216 | u32 enabled_irqs) | |
e0a20ad7 | 3217 | { |
2a57d9cc | 3218 | u32 hotplug; |
e0a20ad7 | 3219 | |
a52bb15b | 3220 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
2a57d9cc ID |
3221 | hotplug |= PORTA_HOTPLUG_ENABLE | |
3222 | PORTB_HOTPLUG_ENABLE | | |
3223 | PORTC_HOTPLUG_ENABLE; | |
d252bf68 SS |
3224 | |
3225 | DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n", | |
3226 | hotplug, enabled_irqs); | |
3227 | hotplug &= ~BXT_DDI_HPD_INVERT_MASK; | |
3228 | ||
3229 | /* | |
3230 | * For BXT invert bit has to be set based on AOB design | |
3231 | * for HPD detection logic, update it based on VBT fields. | |
3232 | */ | |
d252bf68 SS |
3233 | if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) && |
3234 | intel_bios_is_port_hpd_inverted(dev_priv, PORT_A)) | |
3235 | hotplug |= BXT_DDIA_HPD_INVERT; | |
3236 | if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) && | |
3237 | intel_bios_is_port_hpd_inverted(dev_priv, PORT_B)) | |
3238 | hotplug |= BXT_DDIB_HPD_INVERT; | |
3239 | if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) && | |
3240 | intel_bios_is_port_hpd_inverted(dev_priv, PORT_C)) | |
3241 | hotplug |= BXT_DDIC_HPD_INVERT; | |
3242 | ||
a52bb15b | 3243 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
e0a20ad7 SS |
3244 | } |
3245 | ||
2a57d9cc ID |
3246 | static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv) |
3247 | { | |
3248 | __bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK); | |
3249 | } | |
3250 | ||
3251 | static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv) | |
3252 | { | |
3253 | u32 hotplug_irqs, enabled_irqs; | |
3254 | ||
3255 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt); | |
3256 | hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK; | |
3257 | ||
3258 | bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); | |
3259 | ||
3260 | __bxt_hpd_detection_setup(dev_priv, enabled_irqs); | |
3261 | } | |
3262 | ||
d46da437 PZ |
3263 | static void ibx_irq_postinstall(struct drm_device *dev) |
3264 | { | |
fac5e23e | 3265 | struct drm_i915_private *dev_priv = to_i915(dev); |
82a28bcf | 3266 | u32 mask; |
e5868a31 | 3267 | |
6e266956 | 3268 | if (HAS_PCH_NOP(dev_priv)) |
692a04cf DV |
3269 | return; |
3270 | ||
6e266956 | 3271 | if (HAS_PCH_IBX(dev_priv)) |
5c673b60 | 3272 | mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; |
105b122e | 3273 | else |
5c673b60 | 3274 | mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; |
8664281b | 3275 | |
b51a2842 | 3276 | gen5_assert_iir_is_zero(dev_priv, SDEIIR); |
d46da437 | 3277 | I915_WRITE(SDEIMR, ~mask); |
2a57d9cc ID |
3278 | |
3279 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || | |
3280 | HAS_PCH_LPT(dev_priv)) | |
1a56b1a2 | 3281 | ibx_hpd_detection_setup(dev_priv); |
2a57d9cc ID |
3282 | else |
3283 | spt_hpd_detection_setup(dev_priv); | |
d46da437 PZ |
3284 | } |
3285 | ||
0a9a8c91 DV |
3286 | static void gen5_gt_irq_postinstall(struct drm_device *dev) |
3287 | { | |
fac5e23e | 3288 | struct drm_i915_private *dev_priv = to_i915(dev); |
0a9a8c91 DV |
3289 | u32 pm_irqs, gt_irqs; |
3290 | ||
3291 | pm_irqs = gt_irqs = 0; | |
3292 | ||
3293 | dev_priv->gt_irq_mask = ~0; | |
3c9192bc | 3294 | if (HAS_L3_DPF(dev_priv)) { |
0a9a8c91 | 3295 | /* L3 parity interrupt is always unmasked. */ |
772c2a51 TU |
3296 | dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev_priv); |
3297 | gt_irqs |= GT_PARITY_ERROR(dev_priv); | |
0a9a8c91 DV |
3298 | } |
3299 | ||
3300 | gt_irqs |= GT_RENDER_USER_INTERRUPT; | |
5db94019 | 3301 | if (IS_GEN5(dev_priv)) { |
f8973c21 | 3302 | gt_irqs |= ILK_BSD_USER_INTERRUPT; |
0a9a8c91 DV |
3303 | } else { |
3304 | gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; | |
3305 | } | |
3306 | ||
35079899 | 3307 | GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); |
0a9a8c91 | 3308 | |
b243f530 | 3309 | if (INTEL_GEN(dev_priv) >= 6) { |
78e68d36 ID |
3310 | /* |
3311 | * RPS interrupts will get enabled/disabled on demand when RPS | |
3312 | * itself is enabled/disabled. | |
3313 | */ | |
f4e9af4f | 3314 | if (HAS_VEBOX(dev_priv)) { |
0a9a8c91 | 3315 | pm_irqs |= PM_VEBOX_USER_INTERRUPT; |
f4e9af4f AG |
3316 | dev_priv->pm_ier |= PM_VEBOX_USER_INTERRUPT; |
3317 | } | |
0a9a8c91 | 3318 | |
f4e9af4f AG |
3319 | dev_priv->pm_imr = 0xffffffff; |
3320 | GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_imr, pm_irqs); | |
0a9a8c91 DV |
3321 | } |
3322 | } | |
3323 | ||
f71d4af4 | 3324 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d | 3325 | { |
fac5e23e | 3326 | struct drm_i915_private *dev_priv = to_i915(dev); |
8e76f8dc PZ |
3327 | u32 display_mask, extra_mask; |
3328 | ||
b243f530 | 3329 | if (INTEL_GEN(dev_priv) >= 7) { |
8e76f8dc PZ |
3330 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | |
3331 | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | | |
3332 | DE_PLANEB_FLIP_DONE_IVB | | |
5c673b60 | 3333 | DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB); |
8e76f8dc | 3334 | extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | |
23bb4cb5 VS |
3335 | DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB | |
3336 | DE_DP_A_HOTPLUG_IVB); | |
8e76f8dc PZ |
3337 | } else { |
3338 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | | |
3339 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | | |
5b3a856b | 3340 | DE_AUX_CHANNEL_A | |
5b3a856b DV |
3341 | DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE | |
3342 | DE_POISON); | |
e4ce95aa VS |
3343 | extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT | |
3344 | DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN | | |
3345 | DE_DP_A_HOTPLUG); | |
8e76f8dc | 3346 | } |
036a4a7d | 3347 | |
1ec14ad3 | 3348 | dev_priv->irq_mask = ~display_mask; |
036a4a7d | 3349 | |
0c841212 PZ |
3350 | I915_WRITE(HWSTAM, 0xeffe); |
3351 | ||
622364b6 PZ |
3352 | ibx_irq_pre_postinstall(dev); |
3353 | ||
35079899 | 3354 | GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); |
036a4a7d | 3355 | |
0a9a8c91 | 3356 | gen5_gt_irq_postinstall(dev); |
036a4a7d | 3357 | |
1a56b1a2 ID |
3358 | ilk_hpd_detection_setup(dev_priv); |
3359 | ||
d46da437 | 3360 | ibx_irq_postinstall(dev); |
7fe0b973 | 3361 | |
50a0bc90 | 3362 | if (IS_IRONLAKE_M(dev_priv)) { |
6005ce42 DV |
3363 | /* Enable PCU event interrupts |
3364 | * | |
3365 | * spinlocking not required here for correctness since interrupt | |
4bc9d430 DV |
3366 | * setup is guaranteed to run in single-threaded context. But we |
3367 | * need it to make the assert_spin_locked happy. */ | |
d6207435 | 3368 | spin_lock_irq(&dev_priv->irq_lock); |
fbdedaea | 3369 | ilk_enable_display_irq(dev_priv, DE_PCU_EVENT); |
d6207435 | 3370 | spin_unlock_irq(&dev_priv->irq_lock); |
f97108d1 JB |
3371 | } |
3372 | ||
036a4a7d ZW |
3373 | return 0; |
3374 | } | |
3375 | ||
f8b79e58 ID |
3376 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) |
3377 | { | |
67520415 | 3378 | lockdep_assert_held(&dev_priv->irq_lock); |
f8b79e58 ID |
3379 | |
3380 | if (dev_priv->display_irqs_enabled) | |
3381 | return; | |
3382 | ||
3383 | dev_priv->display_irqs_enabled = true; | |
3384 | ||
d6c69803 VS |
3385 | if (intel_irqs_enabled(dev_priv)) { |
3386 | vlv_display_irq_reset(dev_priv); | |
ad22d106 | 3387 | vlv_display_irq_postinstall(dev_priv); |
d6c69803 | 3388 | } |
f8b79e58 ID |
3389 | } |
3390 | ||
3391 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) | |
3392 | { | |
67520415 | 3393 | lockdep_assert_held(&dev_priv->irq_lock); |
f8b79e58 ID |
3394 | |
3395 | if (!dev_priv->display_irqs_enabled) | |
3396 | return; | |
3397 | ||
3398 | dev_priv->display_irqs_enabled = false; | |
3399 | ||
950eabaf | 3400 | if (intel_irqs_enabled(dev_priv)) |
ad22d106 | 3401 | vlv_display_irq_reset(dev_priv); |
f8b79e58 ID |
3402 | } |
3403 | ||
0e6c9a9e VS |
3404 | |
3405 | static int valleyview_irq_postinstall(struct drm_device *dev) | |
3406 | { | |
fac5e23e | 3407 | struct drm_i915_private *dev_priv = to_i915(dev); |
0e6c9a9e | 3408 | |
0a9a8c91 | 3409 | gen5_gt_irq_postinstall(dev); |
7e231dbe | 3410 | |
ad22d106 | 3411 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3412 | if (dev_priv->display_irqs_enabled) |
3413 | vlv_display_irq_postinstall(dev_priv); | |
ad22d106 VS |
3414 | spin_unlock_irq(&dev_priv->irq_lock); |
3415 | ||
7e231dbe | 3416 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); |
34c7b8a7 | 3417 | POSTING_READ(VLV_MASTER_IER); |
20afbda2 DV |
3418 | |
3419 | return 0; | |
3420 | } | |
3421 | ||
abd58f01 BW |
3422 | static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) |
3423 | { | |
abd58f01 BW |
3424 | /* These are interrupts we'll toggle with the ring mask register */ |
3425 | uint32_t gt_interrupts[] = { | |
3426 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | | |
73d477f6 | 3427 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT | |
73d477f6 OM |
3428 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT | |
3429 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT, | |
abd58f01 | 3430 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
73d477f6 OM |
3431 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
3432 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT | | |
3433 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT, | |
abd58f01 | 3434 | 0, |
73d477f6 OM |
3435 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
3436 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
abd58f01 BW |
3437 | }; |
3438 | ||
98735739 TU |
3439 | if (HAS_L3_DPF(dev_priv)) |
3440 | gt_interrupts[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
3441 | ||
f4e9af4f AG |
3442 | dev_priv->pm_ier = 0x0; |
3443 | dev_priv->pm_imr = ~dev_priv->pm_ier; | |
9a2d2d87 D |
3444 | GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]); |
3445 | GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]); | |
78e68d36 ID |
3446 | /* |
3447 | * RPS interrupts will get enabled/disabled on demand when RPS itself | |
26705e20 | 3448 | * is enabled/disabled. Same wil be the case for GuC interrupts. |
78e68d36 | 3449 | */ |
f4e9af4f | 3450 | GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_imr, dev_priv->pm_ier); |
9a2d2d87 | 3451 | GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]); |
abd58f01 BW |
3452 | } |
3453 | ||
3454 | static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) | |
3455 | { | |
770de83d DL |
3456 | uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE; |
3457 | uint32_t de_pipe_enables; | |
3a3b3c7d VS |
3458 | u32 de_port_masked = GEN8_AUX_CHANNEL_A; |
3459 | u32 de_port_enables; | |
11825b0d | 3460 | u32 de_misc_masked = GEN8_DE_MISC_GSE; |
3a3b3c7d | 3461 | enum pipe pipe; |
770de83d | 3462 | |
b4834a50 | 3463 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
770de83d DL |
3464 | de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE | |
3465 | GEN9_DE_PIPE_IRQ_FAULT_ERRORS; | |
3a3b3c7d VS |
3466 | de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | |
3467 | GEN9_AUX_CHANNEL_D; | |
cc3f90f0 | 3468 | if (IS_GEN9_LP(dev_priv)) |
3a3b3c7d VS |
3469 | de_port_masked |= BXT_DE_PORT_GMBUS; |
3470 | } else { | |
770de83d DL |
3471 | de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE | |
3472 | GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
3a3b3c7d | 3473 | } |
770de83d DL |
3474 | |
3475 | de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | | |
3476 | GEN8_PIPE_FIFO_UNDERRUN; | |
3477 | ||
3a3b3c7d | 3478 | de_port_enables = de_port_masked; |
cc3f90f0 | 3479 | if (IS_GEN9_LP(dev_priv)) |
a52bb15b VS |
3480 | de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK; |
3481 | else if (IS_BROADWELL(dev_priv)) | |
3a3b3c7d VS |
3482 | de_port_enables |= GEN8_PORT_DP_A_HOTPLUG; |
3483 | ||
13b3a0a7 DV |
3484 | dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; |
3485 | dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; | |
3486 | dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; | |
abd58f01 | 3487 | |
055e393f | 3488 | for_each_pipe(dev_priv, pipe) |
f458ebbc | 3489 | if (intel_display_power_is_enabled(dev_priv, |
813bde43 PZ |
3490 | POWER_DOMAIN_PIPE(pipe))) |
3491 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, | |
3492 | dev_priv->de_irq_mask[pipe], | |
3493 | de_pipe_enables); | |
abd58f01 | 3494 | |
3a3b3c7d | 3495 | GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables); |
11825b0d | 3496 | GEN5_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked); |
2a57d9cc ID |
3497 | |
3498 | if (IS_GEN9_LP(dev_priv)) | |
3499 | bxt_hpd_detection_setup(dev_priv); | |
1a56b1a2 ID |
3500 | else if (IS_BROADWELL(dev_priv)) |
3501 | ilk_hpd_detection_setup(dev_priv); | |
abd58f01 BW |
3502 | } |
3503 | ||
3504 | static int gen8_irq_postinstall(struct drm_device *dev) | |
3505 | { | |
fac5e23e | 3506 | struct drm_i915_private *dev_priv = to_i915(dev); |
abd58f01 | 3507 | |
6e266956 | 3508 | if (HAS_PCH_SPLIT(dev_priv)) |
266ea3d9 | 3509 | ibx_irq_pre_postinstall(dev); |
622364b6 | 3510 | |
abd58f01 BW |
3511 | gen8_gt_irq_postinstall(dev_priv); |
3512 | gen8_de_irq_postinstall(dev_priv); | |
3513 | ||
6e266956 | 3514 | if (HAS_PCH_SPLIT(dev_priv)) |
266ea3d9 | 3515 | ibx_irq_postinstall(dev); |
abd58f01 | 3516 | |
e5328c43 | 3517 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
abd58f01 BW |
3518 | POSTING_READ(GEN8_MASTER_IRQ); |
3519 | ||
3520 | return 0; | |
3521 | } | |
3522 | ||
43f328d7 VS |
3523 | static int cherryview_irq_postinstall(struct drm_device *dev) |
3524 | { | |
fac5e23e | 3525 | struct drm_i915_private *dev_priv = to_i915(dev); |
43f328d7 | 3526 | |
43f328d7 VS |
3527 | gen8_gt_irq_postinstall(dev_priv); |
3528 | ||
ad22d106 | 3529 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3530 | if (dev_priv->display_irqs_enabled) |
3531 | vlv_display_irq_postinstall(dev_priv); | |
ad22d106 VS |
3532 | spin_unlock_irq(&dev_priv->irq_lock); |
3533 | ||
e5328c43 | 3534 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
43f328d7 VS |
3535 | POSTING_READ(GEN8_MASTER_IRQ); |
3536 | ||
3537 | return 0; | |
3538 | } | |
3539 | ||
abd58f01 BW |
3540 | static void gen8_irq_uninstall(struct drm_device *dev) |
3541 | { | |
fac5e23e | 3542 | struct drm_i915_private *dev_priv = to_i915(dev); |
abd58f01 BW |
3543 | |
3544 | if (!dev_priv) | |
3545 | return; | |
3546 | ||
823f6b38 | 3547 | gen8_irq_reset(dev); |
abd58f01 BW |
3548 | } |
3549 | ||
7e231dbe JB |
3550 | static void valleyview_irq_uninstall(struct drm_device *dev) |
3551 | { | |
fac5e23e | 3552 | struct drm_i915_private *dev_priv = to_i915(dev); |
7e231dbe JB |
3553 | |
3554 | if (!dev_priv) | |
3555 | return; | |
3556 | ||
843d0e7d | 3557 | I915_WRITE(VLV_MASTER_IER, 0); |
34c7b8a7 | 3558 | POSTING_READ(VLV_MASTER_IER); |
843d0e7d | 3559 | |
b243f530 | 3560 | gen5_gt_irq_reset(dev_priv); |
893fce8e | 3561 | |
7e231dbe | 3562 | I915_WRITE(HWSTAM, 0xffffffff); |
f8b79e58 | 3563 | |
ad22d106 | 3564 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3565 | if (dev_priv->display_irqs_enabled) |
3566 | vlv_display_irq_reset(dev_priv); | |
ad22d106 | 3567 | spin_unlock_irq(&dev_priv->irq_lock); |
7e231dbe JB |
3568 | } |
3569 | ||
43f328d7 VS |
3570 | static void cherryview_irq_uninstall(struct drm_device *dev) |
3571 | { | |
fac5e23e | 3572 | struct drm_i915_private *dev_priv = to_i915(dev); |
43f328d7 VS |
3573 | |
3574 | if (!dev_priv) | |
3575 | return; | |
3576 | ||
3577 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3578 | POSTING_READ(GEN8_MASTER_IRQ); | |
3579 | ||
a2c30fba | 3580 | gen8_gt_irq_reset(dev_priv); |
43f328d7 | 3581 | |
a2c30fba | 3582 | GEN5_IRQ_RESET(GEN8_PCU_); |
43f328d7 | 3583 | |
ad22d106 | 3584 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3585 | if (dev_priv->display_irqs_enabled) |
3586 | vlv_display_irq_reset(dev_priv); | |
ad22d106 | 3587 | spin_unlock_irq(&dev_priv->irq_lock); |
43f328d7 VS |
3588 | } |
3589 | ||
f71d4af4 | 3590 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d | 3591 | { |
fac5e23e | 3592 | struct drm_i915_private *dev_priv = to_i915(dev); |
4697995b JB |
3593 | |
3594 | if (!dev_priv) | |
3595 | return; | |
3596 | ||
be30b29f | 3597 | ironlake_irq_reset(dev); |
036a4a7d ZW |
3598 | } |
3599 | ||
a266c7d5 | 3600 | static void i8xx_irq_preinstall(struct drm_device * dev) |
1da177e4 | 3601 | { |
fac5e23e | 3602 | struct drm_i915_private *dev_priv = to_i915(dev); |
9db4a9c7 | 3603 | int pipe; |
91e3738e | 3604 | |
055e393f | 3605 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 | 3606 | I915_WRITE(PIPESTAT(pipe), 0); |
a266c7d5 CW |
3607 | I915_WRITE16(IMR, 0xffff); |
3608 | I915_WRITE16(IER, 0x0); | |
3609 | POSTING_READ16(IER); | |
c2798b19 CW |
3610 | } |
3611 | ||
3612 | static int i8xx_irq_postinstall(struct drm_device *dev) | |
3613 | { | |
fac5e23e | 3614 | struct drm_i915_private *dev_priv = to_i915(dev); |
c2798b19 | 3615 | |
c2798b19 CW |
3616 | I915_WRITE16(EMR, |
3617 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); | |
3618 | ||
3619 | /* Unmask the interrupts that we always want on. */ | |
3620 | dev_priv->irq_mask = | |
3621 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3622 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3623 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
37ef01ab | 3624 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); |
c2798b19 CW |
3625 | I915_WRITE16(IMR, dev_priv->irq_mask); |
3626 | ||
3627 | I915_WRITE16(IER, | |
3628 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3629 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
c2798b19 CW |
3630 | I915_USER_INTERRUPT); |
3631 | POSTING_READ16(IER); | |
3632 | ||
379ef82d DV |
3633 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3634 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3635 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
3636 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3637 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 3638 | spin_unlock_irq(&dev_priv->irq_lock); |
379ef82d | 3639 | |
c2798b19 CW |
3640 | return 0; |
3641 | } | |
3642 | ||
5a21b665 DV |
3643 | /* |
3644 | * Returns true when a page flip has completed. | |
3645 | */ | |
3646 | static bool i8xx_handle_vblank(struct drm_i915_private *dev_priv, | |
3647 | int plane, int pipe, u32 iir) | |
3648 | { | |
3649 | u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); | |
3650 | ||
3651 | if (!intel_pipe_handle_vblank(dev_priv, pipe)) | |
3652 | return false; | |
3653 | ||
3654 | if ((iir & flip_pending) == 0) | |
3655 | goto check_page_flip; | |
3656 | ||
3657 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
3658 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3659 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3660 | * the flip is completed (no longer pending). Since this doesn't raise | |
3661 | * an interrupt per se, we watch for the change at vblank. | |
3662 | */ | |
3663 | if (I915_READ16(ISR) & flip_pending) | |
3664 | goto check_page_flip; | |
3665 | ||
3666 | intel_finish_page_flip_cs(dev_priv, pipe); | |
3667 | return true; | |
3668 | ||
3669 | check_page_flip: | |
3670 | intel_check_page_flip(dev_priv, pipe); | |
3671 | return false; | |
3672 | } | |
3673 | ||
ff1f525e | 3674 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
c2798b19 | 3675 | { |
45a83f84 | 3676 | struct drm_device *dev = arg; |
fac5e23e | 3677 | struct drm_i915_private *dev_priv = to_i915(dev); |
c2798b19 CW |
3678 | u16 iir, new_iir; |
3679 | u32 pipe_stats[2]; | |
c2798b19 CW |
3680 | int pipe; |
3681 | u16 flip_mask = | |
3682 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3683 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
1f814dac | 3684 | irqreturn_t ret; |
c2798b19 | 3685 | |
2dd2a883 ID |
3686 | if (!intel_irqs_enabled(dev_priv)) |
3687 | return IRQ_NONE; | |
3688 | ||
1f814dac ID |
3689 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
3690 | disable_rpm_wakeref_asserts(dev_priv); | |
3691 | ||
3692 | ret = IRQ_NONE; | |
c2798b19 CW |
3693 | iir = I915_READ16(IIR); |
3694 | if (iir == 0) | |
1f814dac | 3695 | goto out; |
c2798b19 CW |
3696 | |
3697 | while (iir & ~flip_mask) { | |
3698 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3699 | * have been cleared after the pipestat interrupt was received. | |
3700 | * It doesn't set the bit in iir again, but it still produces | |
3701 | * interrupts (for non-MSI). | |
3702 | */ | |
222c7f51 | 3703 | spin_lock(&dev_priv->irq_lock); |
c2798b19 | 3704 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 3705 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
c2798b19 | 3706 | |
055e393f | 3707 | for_each_pipe(dev_priv, pipe) { |
f0f59a00 | 3708 | i915_reg_t reg = PIPESTAT(pipe); |
c2798b19 CW |
3709 | pipe_stats[pipe] = I915_READ(reg); |
3710 | ||
3711 | /* | |
3712 | * Clear the PIPE*STAT regs before the IIR | |
3713 | */ | |
2d9d2b0b | 3714 | if (pipe_stats[pipe] & 0x8000ffff) |
c2798b19 | 3715 | I915_WRITE(reg, pipe_stats[pipe]); |
c2798b19 | 3716 | } |
222c7f51 | 3717 | spin_unlock(&dev_priv->irq_lock); |
c2798b19 CW |
3718 | |
3719 | I915_WRITE16(IIR, iir & ~flip_mask); | |
3720 | new_iir = I915_READ16(IIR); /* Flush posted writes */ | |
3721 | ||
c2798b19 | 3722 | if (iir & I915_USER_INTERRUPT) |
3b3f1650 | 3723 | notify_ring(dev_priv->engine[RCS]); |
c2798b19 | 3724 | |
055e393f | 3725 | for_each_pipe(dev_priv, pipe) { |
5a21b665 DV |
3726 | int plane = pipe; |
3727 | if (HAS_FBC(dev_priv)) | |
3728 | plane = !plane; | |
3729 | ||
3730 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && | |
3731 | i8xx_handle_vblank(dev_priv, plane, pipe, iir)) | |
3732 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
c2798b19 | 3733 | |
4356d586 | 3734 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
91d14251 | 3735 | i9xx_pipe_crc_irq_handler(dev_priv, pipe); |
2d9d2b0b | 3736 | |
1f7247c0 DV |
3737 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
3738 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
3739 | pipe); | |
4356d586 | 3740 | } |
c2798b19 CW |
3741 | |
3742 | iir = new_iir; | |
3743 | } | |
1f814dac ID |
3744 | ret = IRQ_HANDLED; |
3745 | ||
3746 | out: | |
3747 | enable_rpm_wakeref_asserts(dev_priv); | |
c2798b19 | 3748 | |
1f814dac | 3749 | return ret; |
c2798b19 CW |
3750 | } |
3751 | ||
3752 | static void i8xx_irq_uninstall(struct drm_device * dev) | |
3753 | { | |
fac5e23e | 3754 | struct drm_i915_private *dev_priv = to_i915(dev); |
c2798b19 CW |
3755 | int pipe; |
3756 | ||
055e393f | 3757 | for_each_pipe(dev_priv, pipe) { |
c2798b19 CW |
3758 | /* Clear enable bits; then clear status bits */ |
3759 | I915_WRITE(PIPESTAT(pipe), 0); | |
3760 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); | |
3761 | } | |
3762 | I915_WRITE16(IMR, 0xffff); | |
3763 | I915_WRITE16(IER, 0x0); | |
3764 | I915_WRITE16(IIR, I915_READ16(IIR)); | |
3765 | } | |
3766 | ||
a266c7d5 CW |
3767 | static void i915_irq_preinstall(struct drm_device * dev) |
3768 | { | |
fac5e23e | 3769 | struct drm_i915_private *dev_priv = to_i915(dev); |
a266c7d5 CW |
3770 | int pipe; |
3771 | ||
56b857a5 | 3772 | if (I915_HAS_HOTPLUG(dev_priv)) { |
0706f17c | 3773 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
a266c7d5 CW |
3774 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
3775 | } | |
3776 | ||
00d98ebd | 3777 | I915_WRITE16(HWSTAM, 0xeffe); |
055e393f | 3778 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
3779 | I915_WRITE(PIPESTAT(pipe), 0); |
3780 | I915_WRITE(IMR, 0xffffffff); | |
3781 | I915_WRITE(IER, 0x0); | |
3782 | POSTING_READ(IER); | |
3783 | } | |
3784 | ||
3785 | static int i915_irq_postinstall(struct drm_device *dev) | |
3786 | { | |
fac5e23e | 3787 | struct drm_i915_private *dev_priv = to_i915(dev); |
38bde180 | 3788 | u32 enable_mask; |
a266c7d5 | 3789 | |
38bde180 CW |
3790 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
3791 | ||
3792 | /* Unmask the interrupts that we always want on. */ | |
3793 | dev_priv->irq_mask = | |
3794 | ~(I915_ASLE_INTERRUPT | | |
3795 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3796 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3797 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
37ef01ab | 3798 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); |
38bde180 CW |
3799 | |
3800 | enable_mask = | |
3801 | I915_ASLE_INTERRUPT | | |
3802 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3803 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
38bde180 CW |
3804 | I915_USER_INTERRUPT; |
3805 | ||
56b857a5 | 3806 | if (I915_HAS_HOTPLUG(dev_priv)) { |
0706f17c | 3807 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
20afbda2 DV |
3808 | POSTING_READ(PORT_HOTPLUG_EN); |
3809 | ||
a266c7d5 CW |
3810 | /* Enable in IER... */ |
3811 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
3812 | /* and unmask in IMR */ | |
3813 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; | |
3814 | } | |
3815 | ||
a266c7d5 CW |
3816 | I915_WRITE(IMR, dev_priv->irq_mask); |
3817 | I915_WRITE(IER, enable_mask); | |
3818 | POSTING_READ(IER); | |
3819 | ||
91d14251 | 3820 | i915_enable_asle_pipestat(dev_priv); |
20afbda2 | 3821 | |
379ef82d DV |
3822 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3823 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3824 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
3825 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3826 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 3827 | spin_unlock_irq(&dev_priv->irq_lock); |
379ef82d | 3828 | |
20afbda2 DV |
3829 | return 0; |
3830 | } | |
3831 | ||
5a21b665 DV |
3832 | /* |
3833 | * Returns true when a page flip has completed. | |
3834 | */ | |
3835 | static bool i915_handle_vblank(struct drm_i915_private *dev_priv, | |
3836 | int plane, int pipe, u32 iir) | |
3837 | { | |
3838 | u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); | |
3839 | ||
3840 | if (!intel_pipe_handle_vblank(dev_priv, pipe)) | |
3841 | return false; | |
3842 | ||
3843 | if ((iir & flip_pending) == 0) | |
3844 | goto check_page_flip; | |
3845 | ||
3846 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
3847 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3848 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3849 | * the flip is completed (no longer pending). Since this doesn't raise | |
3850 | * an interrupt per se, we watch for the change at vblank. | |
3851 | */ | |
3852 | if (I915_READ(ISR) & flip_pending) | |
3853 | goto check_page_flip; | |
3854 | ||
3855 | intel_finish_page_flip_cs(dev_priv, pipe); | |
3856 | return true; | |
3857 | ||
3858 | check_page_flip: | |
3859 | intel_check_page_flip(dev_priv, pipe); | |
3860 | return false; | |
3861 | } | |
3862 | ||
ff1f525e | 3863 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
a266c7d5 | 3864 | { |
45a83f84 | 3865 | struct drm_device *dev = arg; |
fac5e23e | 3866 | struct drm_i915_private *dev_priv = to_i915(dev); |
8291ee90 | 3867 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
38bde180 CW |
3868 | u32 flip_mask = |
3869 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3870 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
38bde180 | 3871 | int pipe, ret = IRQ_NONE; |
a266c7d5 | 3872 | |
2dd2a883 ID |
3873 | if (!intel_irqs_enabled(dev_priv)) |
3874 | return IRQ_NONE; | |
3875 | ||
1f814dac ID |
3876 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
3877 | disable_rpm_wakeref_asserts(dev_priv); | |
3878 | ||
a266c7d5 | 3879 | iir = I915_READ(IIR); |
38bde180 CW |
3880 | do { |
3881 | bool irq_received = (iir & ~flip_mask) != 0; | |
8291ee90 | 3882 | bool blc_event = false; |
a266c7d5 CW |
3883 | |
3884 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3885 | * have been cleared after the pipestat interrupt was received. | |
3886 | * It doesn't set the bit in iir again, but it still produces | |
3887 | * interrupts (for non-MSI). | |
3888 | */ | |
222c7f51 | 3889 | spin_lock(&dev_priv->irq_lock); |
a266c7d5 | 3890 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 3891 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
a266c7d5 | 3892 | |
055e393f | 3893 | for_each_pipe(dev_priv, pipe) { |
f0f59a00 | 3894 | i915_reg_t reg = PIPESTAT(pipe); |
a266c7d5 CW |
3895 | pipe_stats[pipe] = I915_READ(reg); |
3896 | ||
38bde180 | 3897 | /* Clear the PIPE*STAT regs before the IIR */ |
a266c7d5 | 3898 | if (pipe_stats[pipe] & 0x8000ffff) { |
a266c7d5 | 3899 | I915_WRITE(reg, pipe_stats[pipe]); |
38bde180 | 3900 | irq_received = true; |
a266c7d5 CW |
3901 | } |
3902 | } | |
222c7f51 | 3903 | spin_unlock(&dev_priv->irq_lock); |
a266c7d5 CW |
3904 | |
3905 | if (!irq_received) | |
3906 | break; | |
3907 | ||
a266c7d5 | 3908 | /* Consume port. Then clear IIR or we'll miss events */ |
91d14251 | 3909 | if (I915_HAS_HOTPLUG(dev_priv) && |
1ae3c34c VS |
3910 | iir & I915_DISPLAY_PORT_INTERRUPT) { |
3911 | u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv); | |
3912 | if (hotplug_status) | |
91d14251 | 3913 | i9xx_hpd_irq_handler(dev_priv, hotplug_status); |
1ae3c34c | 3914 | } |
a266c7d5 | 3915 | |
38bde180 | 3916 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
3917 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
3918 | ||
a266c7d5 | 3919 | if (iir & I915_USER_INTERRUPT) |
3b3f1650 | 3920 | notify_ring(dev_priv->engine[RCS]); |
a266c7d5 | 3921 | |
055e393f | 3922 | for_each_pipe(dev_priv, pipe) { |
5a21b665 DV |
3923 | int plane = pipe; |
3924 | if (HAS_FBC(dev_priv)) | |
3925 | plane = !plane; | |
3926 | ||
3927 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && | |
3928 | i915_handle_vblank(dev_priv, plane, pipe, iir)) | |
3929 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
a266c7d5 CW |
3930 | |
3931 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
3932 | blc_event = true; | |
4356d586 DV |
3933 | |
3934 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
91d14251 | 3935 | i9xx_pipe_crc_irq_handler(dev_priv, pipe); |
2d9d2b0b | 3936 | |
1f7247c0 DV |
3937 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
3938 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
3939 | pipe); | |
a266c7d5 CW |
3940 | } |
3941 | ||
a266c7d5 | 3942 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
91d14251 | 3943 | intel_opregion_asle_intr(dev_priv); |
a266c7d5 CW |
3944 | |
3945 | /* With MSI, interrupts are only generated when iir | |
3946 | * transitions from zero to nonzero. If another bit got | |
3947 | * set while we were handling the existing iir bits, then | |
3948 | * we would never get another interrupt. | |
3949 | * | |
3950 | * This is fine on non-MSI as well, as if we hit this path | |
3951 | * we avoid exiting the interrupt handler only to generate | |
3952 | * another one. | |
3953 | * | |
3954 | * Note that for MSI this could cause a stray interrupt report | |
3955 | * if an interrupt landed in the time between writing IIR and | |
3956 | * the posting read. This should be rare enough to never | |
3957 | * trigger the 99% of 100,000 interrupts test for disabling | |
3958 | * stray interrupts. | |
3959 | */ | |
38bde180 | 3960 | ret = IRQ_HANDLED; |
a266c7d5 | 3961 | iir = new_iir; |
38bde180 | 3962 | } while (iir & ~flip_mask); |
a266c7d5 | 3963 | |
1f814dac ID |
3964 | enable_rpm_wakeref_asserts(dev_priv); |
3965 | ||
a266c7d5 CW |
3966 | return ret; |
3967 | } | |
3968 | ||
3969 | static void i915_irq_uninstall(struct drm_device * dev) | |
3970 | { | |
fac5e23e | 3971 | struct drm_i915_private *dev_priv = to_i915(dev); |
a266c7d5 CW |
3972 | int pipe; |
3973 | ||
56b857a5 | 3974 | if (I915_HAS_HOTPLUG(dev_priv)) { |
0706f17c | 3975 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
a266c7d5 CW |
3976 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
3977 | } | |
3978 | ||
00d98ebd | 3979 | I915_WRITE16(HWSTAM, 0xffff); |
055e393f | 3980 | for_each_pipe(dev_priv, pipe) { |
55b39755 | 3981 | /* Clear enable bits; then clear status bits */ |
a266c7d5 | 3982 | I915_WRITE(PIPESTAT(pipe), 0); |
55b39755 CW |
3983 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
3984 | } | |
a266c7d5 CW |
3985 | I915_WRITE(IMR, 0xffffffff); |
3986 | I915_WRITE(IER, 0x0); | |
3987 | ||
a266c7d5 CW |
3988 | I915_WRITE(IIR, I915_READ(IIR)); |
3989 | } | |
3990 | ||
3991 | static void i965_irq_preinstall(struct drm_device * dev) | |
3992 | { | |
fac5e23e | 3993 | struct drm_i915_private *dev_priv = to_i915(dev); |
a266c7d5 CW |
3994 | int pipe; |
3995 | ||
0706f17c | 3996 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
adca4730 | 3997 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
a266c7d5 CW |
3998 | |
3999 | I915_WRITE(HWSTAM, 0xeffe); | |
055e393f | 4000 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4001 | I915_WRITE(PIPESTAT(pipe), 0); |
4002 | I915_WRITE(IMR, 0xffffffff); | |
4003 | I915_WRITE(IER, 0x0); | |
4004 | POSTING_READ(IER); | |
4005 | } | |
4006 | ||
4007 | static int i965_irq_postinstall(struct drm_device *dev) | |
4008 | { | |
fac5e23e | 4009 | struct drm_i915_private *dev_priv = to_i915(dev); |
bbba0a97 | 4010 | u32 enable_mask; |
a266c7d5 CW |
4011 | u32 error_mask; |
4012 | ||
a266c7d5 | 4013 | /* Unmask the interrupts that we always want on. */ |
bbba0a97 | 4014 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
adca4730 | 4015 | I915_DISPLAY_PORT_INTERRUPT | |
bbba0a97 CW |
4016 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
4017 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
4018 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4019 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
4020 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
4021 | ||
4022 | enable_mask = ~dev_priv->irq_mask; | |
21ad8330 VS |
4023 | enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
4024 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); | |
bbba0a97 CW |
4025 | enable_mask |= I915_USER_INTERRUPT; |
4026 | ||
91d14251 | 4027 | if (IS_G4X(dev_priv)) |
bbba0a97 | 4028 | enable_mask |= I915_BSD_USER_INTERRUPT; |
a266c7d5 | 4029 | |
b79480ba DV |
4030 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
4031 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 4032 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
4033 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
4034 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
4035 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 4036 | spin_unlock_irq(&dev_priv->irq_lock); |
a266c7d5 | 4037 | |
a266c7d5 CW |
4038 | /* |
4039 | * Enable some error detection, note the instruction error mask | |
4040 | * bit is reserved, so we leave it masked. | |
4041 | */ | |
91d14251 | 4042 | if (IS_G4X(dev_priv)) { |
a266c7d5 CW |
4043 | error_mask = ~(GM45_ERROR_PAGE_TABLE | |
4044 | GM45_ERROR_MEM_PRIV | | |
4045 | GM45_ERROR_CP_PRIV | | |
4046 | I915_ERROR_MEMORY_REFRESH); | |
4047 | } else { | |
4048 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
4049 | I915_ERROR_MEMORY_REFRESH); | |
4050 | } | |
4051 | I915_WRITE(EMR, error_mask); | |
4052 | ||
4053 | I915_WRITE(IMR, dev_priv->irq_mask); | |
4054 | I915_WRITE(IER, enable_mask); | |
4055 | POSTING_READ(IER); | |
4056 | ||
0706f17c | 4057 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
20afbda2 DV |
4058 | POSTING_READ(PORT_HOTPLUG_EN); |
4059 | ||
91d14251 | 4060 | i915_enable_asle_pipestat(dev_priv); |
20afbda2 DV |
4061 | |
4062 | return 0; | |
4063 | } | |
4064 | ||
91d14251 | 4065 | static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv) |
20afbda2 | 4066 | { |
20afbda2 DV |
4067 | u32 hotplug_en; |
4068 | ||
67520415 | 4069 | lockdep_assert_held(&dev_priv->irq_lock); |
b5ea2d56 | 4070 | |
778eb334 VS |
4071 | /* Note HDMI and DP share hotplug bits */ |
4072 | /* enable bits are the same for all generations */ | |
91d14251 | 4073 | hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915); |
778eb334 VS |
4074 | /* Programming the CRT detection parameters tends |
4075 | to generate a spurious hotplug event about three | |
4076 | seconds later. So just do it once. | |
4077 | */ | |
91d14251 | 4078 | if (IS_G4X(dev_priv)) |
778eb334 | 4079 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; |
778eb334 VS |
4080 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
4081 | ||
4082 | /* Ignore TV since it's buggy */ | |
0706f17c | 4083 | i915_hotplug_interrupt_update_locked(dev_priv, |
f9e3dc78 JN |
4084 | HOTPLUG_INT_EN_MASK | |
4085 | CRT_HOTPLUG_VOLTAGE_COMPARE_MASK | | |
4086 | CRT_HOTPLUG_ACTIVATION_PERIOD_64, | |
4087 | hotplug_en); | |
a266c7d5 CW |
4088 | } |
4089 | ||
ff1f525e | 4090 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
a266c7d5 | 4091 | { |
45a83f84 | 4092 | struct drm_device *dev = arg; |
fac5e23e | 4093 | struct drm_i915_private *dev_priv = to_i915(dev); |
a266c7d5 CW |
4094 | u32 iir, new_iir; |
4095 | u32 pipe_stats[I915_MAX_PIPES]; | |
a266c7d5 | 4096 | int ret = IRQ_NONE, pipe; |
21ad8330 VS |
4097 | u32 flip_mask = |
4098 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4099 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
a266c7d5 | 4100 | |
2dd2a883 ID |
4101 | if (!intel_irqs_enabled(dev_priv)) |
4102 | return IRQ_NONE; | |
4103 | ||
1f814dac ID |
4104 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
4105 | disable_rpm_wakeref_asserts(dev_priv); | |
4106 | ||
a266c7d5 CW |
4107 | iir = I915_READ(IIR); |
4108 | ||
a266c7d5 | 4109 | for (;;) { |
501e01d7 | 4110 | bool irq_received = (iir & ~flip_mask) != 0; |
2c8ba29f CW |
4111 | bool blc_event = false; |
4112 | ||
a266c7d5 CW |
4113 | /* Can't rely on pipestat interrupt bit in iir as it might |
4114 | * have been cleared after the pipestat interrupt was received. | |
4115 | * It doesn't set the bit in iir again, but it still produces | |
4116 | * interrupts (for non-MSI). | |
4117 | */ | |
222c7f51 | 4118 | spin_lock(&dev_priv->irq_lock); |
a266c7d5 | 4119 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 4120 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
a266c7d5 | 4121 | |
055e393f | 4122 | for_each_pipe(dev_priv, pipe) { |
f0f59a00 | 4123 | i915_reg_t reg = PIPESTAT(pipe); |
a266c7d5 CW |
4124 | pipe_stats[pipe] = I915_READ(reg); |
4125 | ||
4126 | /* | |
4127 | * Clear the PIPE*STAT regs before the IIR | |
4128 | */ | |
4129 | if (pipe_stats[pipe] & 0x8000ffff) { | |
a266c7d5 | 4130 | I915_WRITE(reg, pipe_stats[pipe]); |
501e01d7 | 4131 | irq_received = true; |
a266c7d5 CW |
4132 | } |
4133 | } | |
222c7f51 | 4134 | spin_unlock(&dev_priv->irq_lock); |
a266c7d5 CW |
4135 | |
4136 | if (!irq_received) | |
4137 | break; | |
4138 | ||
4139 | ret = IRQ_HANDLED; | |
4140 | ||
4141 | /* Consume port. Then clear IIR or we'll miss events */ | |
1ae3c34c VS |
4142 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { |
4143 | u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv); | |
4144 | if (hotplug_status) | |
91d14251 | 4145 | i9xx_hpd_irq_handler(dev_priv, hotplug_status); |
1ae3c34c | 4146 | } |
a266c7d5 | 4147 | |
21ad8330 | 4148 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
4149 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
4150 | ||
a266c7d5 | 4151 | if (iir & I915_USER_INTERRUPT) |
3b3f1650 | 4152 | notify_ring(dev_priv->engine[RCS]); |
a266c7d5 | 4153 | if (iir & I915_BSD_USER_INTERRUPT) |
3b3f1650 | 4154 | notify_ring(dev_priv->engine[VCS]); |
a266c7d5 | 4155 | |
055e393f | 4156 | for_each_pipe(dev_priv, pipe) { |
5a21b665 DV |
4157 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
4158 | i915_handle_vblank(dev_priv, pipe, pipe, iir)) | |
4159 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); | |
a266c7d5 CW |
4160 | |
4161 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
4162 | blc_event = true; | |
4356d586 DV |
4163 | |
4164 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
91d14251 | 4165 | i9xx_pipe_crc_irq_handler(dev_priv, pipe); |
a266c7d5 | 4166 | |
1f7247c0 DV |
4167 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
4168 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
2d9d2b0b | 4169 | } |
a266c7d5 CW |
4170 | |
4171 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | |
91d14251 | 4172 | intel_opregion_asle_intr(dev_priv); |
a266c7d5 | 4173 | |
515ac2bb | 4174 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
91d14251 | 4175 | gmbus_irq_handler(dev_priv); |
515ac2bb | 4176 | |
a266c7d5 CW |
4177 | /* With MSI, interrupts are only generated when iir |
4178 | * transitions from zero to nonzero. If another bit got | |
4179 | * set while we were handling the existing iir bits, then | |
4180 | * we would never get another interrupt. | |
4181 | * | |
4182 | * This is fine on non-MSI as well, as if we hit this path | |
4183 | * we avoid exiting the interrupt handler only to generate | |
4184 | * another one. | |
4185 | * | |
4186 | * Note that for MSI this could cause a stray interrupt report | |
4187 | * if an interrupt landed in the time between writing IIR and | |
4188 | * the posting read. This should be rare enough to never | |
4189 | * trigger the 99% of 100,000 interrupts test for disabling | |
4190 | * stray interrupts. | |
4191 | */ | |
4192 | iir = new_iir; | |
4193 | } | |
4194 | ||
1f814dac ID |
4195 | enable_rpm_wakeref_asserts(dev_priv); |
4196 | ||
a266c7d5 CW |
4197 | return ret; |
4198 | } | |
4199 | ||
4200 | static void i965_irq_uninstall(struct drm_device * dev) | |
4201 | { | |
fac5e23e | 4202 | struct drm_i915_private *dev_priv = to_i915(dev); |
a266c7d5 CW |
4203 | int pipe; |
4204 | ||
4205 | if (!dev_priv) | |
4206 | return; | |
4207 | ||
0706f17c | 4208 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
adca4730 | 4209 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
a266c7d5 CW |
4210 | |
4211 | I915_WRITE(HWSTAM, 0xffffffff); | |
055e393f | 4212 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4213 | I915_WRITE(PIPESTAT(pipe), 0); |
4214 | I915_WRITE(IMR, 0xffffffff); | |
4215 | I915_WRITE(IER, 0x0); | |
4216 | ||
055e393f | 4217 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4218 | I915_WRITE(PIPESTAT(pipe), |
4219 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); | |
4220 | I915_WRITE(IIR, I915_READ(IIR)); | |
4221 | } | |
4222 | ||
fca52a55 DV |
4223 | /** |
4224 | * intel_irq_init - initializes irq support | |
4225 | * @dev_priv: i915 device instance | |
4226 | * | |
4227 | * This function initializes all the irq support including work items, timers | |
4228 | * and all the vtables. It does not setup the interrupt itself though. | |
4229 | */ | |
b963291c | 4230 | void intel_irq_init(struct drm_i915_private *dev_priv) |
f71d4af4 | 4231 | { |
91c8a326 | 4232 | struct drm_device *dev = &dev_priv->drm; |
8b2e326d | 4233 | |
77913b39 JN |
4234 | intel_hpd_init_work(dev_priv); |
4235 | ||
c6a828d3 | 4236 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
a4da4fa4 | 4237 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
8b2e326d | 4238 | |
4805fe82 | 4239 | if (HAS_GUC_SCHED(dev_priv)) |
26705e20 SAK |
4240 | dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT; |
4241 | ||
a6706b45 | 4242 | /* Let's track the enabled rps events */ |
666a4537 | 4243 | if (IS_VALLEYVIEW(dev_priv)) |
6c65a587 | 4244 | /* WaGsvRC0ResidencyMethod:vlv */ |
e0e8c7cb | 4245 | dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED; |
31685c25 D |
4246 | else |
4247 | dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; | |
a6706b45 | 4248 | |
5dd04556 | 4249 | dev_priv->rps.pm_intrmsk_mbz = 0; |
1800ad25 SAK |
4250 | |
4251 | /* | |
acf2dc22 | 4252 | * SNB,IVB,HSW can while VLV,CHV may hard hang on looping batchbuffer |
1800ad25 SAK |
4253 | * if GEN6_PM_UP_EI_EXPIRED is masked. |
4254 | * | |
4255 | * TODO: verify if this can be reproduced on VLV,CHV. | |
4256 | */ | |
acf2dc22 | 4257 | if (INTEL_INFO(dev_priv)->gen <= 7) |
5dd04556 | 4258 | dev_priv->rps.pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED; |
1800ad25 SAK |
4259 | |
4260 | if (INTEL_INFO(dev_priv)->gen >= 8) | |
655d49ef | 4261 | dev_priv->rps.pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC; |
1800ad25 | 4262 | |
b963291c | 4263 | if (IS_GEN2(dev_priv)) { |
4194c088 | 4264 | /* Gen2 doesn't have a hardware frame counter */ |
4cdb83ec | 4265 | dev->max_vblank_count = 0; |
b963291c | 4266 | } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { |
f71d4af4 | 4267 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
fd8f507c | 4268 | dev->driver->get_vblank_counter = g4x_get_vblank_counter; |
391f75e2 VS |
4269 | } else { |
4270 | dev->driver->get_vblank_counter = i915_get_vblank_counter; | |
4271 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
f71d4af4 JB |
4272 | } |
4273 | ||
21da2700 VS |
4274 | /* |
4275 | * Opt out of the vblank disable timer on everything except gen2. | |
4276 | * Gen2 doesn't have a hardware frame counter and so depends on | |
4277 | * vblank interrupts to produce sane vblank seuquence numbers. | |
4278 | */ | |
b963291c | 4279 | if (!IS_GEN2(dev_priv)) |
21da2700 VS |
4280 | dev->vblank_disable_immediate = true; |
4281 | ||
262fd485 CW |
4282 | /* Most platforms treat the display irq block as an always-on |
4283 | * power domain. vlv/chv can disable it at runtime and need | |
4284 | * special care to avoid writing any of the display block registers | |
4285 | * outside of the power domain. We defer setting up the display irqs | |
4286 | * in this case to the runtime pm. | |
4287 | */ | |
4288 | dev_priv->display_irqs_enabled = true; | |
4289 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
4290 | dev_priv->display_irqs_enabled = false; | |
4291 | ||
317eaa95 L |
4292 | dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD; |
4293 | ||
f3a5c3f6 DV |
4294 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; |
4295 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; | |
f71d4af4 | 4296 | |
b963291c | 4297 | if (IS_CHERRYVIEW(dev_priv)) { |
43f328d7 VS |
4298 | dev->driver->irq_handler = cherryview_irq_handler; |
4299 | dev->driver->irq_preinstall = cherryview_irq_preinstall; | |
4300 | dev->driver->irq_postinstall = cherryview_irq_postinstall; | |
4301 | dev->driver->irq_uninstall = cherryview_irq_uninstall; | |
86e83e35 CW |
4302 | dev->driver->enable_vblank = i965_enable_vblank; |
4303 | dev->driver->disable_vblank = i965_disable_vblank; | |
43f328d7 | 4304 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
b963291c | 4305 | } else if (IS_VALLEYVIEW(dev_priv)) { |
7e231dbe JB |
4306 | dev->driver->irq_handler = valleyview_irq_handler; |
4307 | dev->driver->irq_preinstall = valleyview_irq_preinstall; | |
4308 | dev->driver->irq_postinstall = valleyview_irq_postinstall; | |
4309 | dev->driver->irq_uninstall = valleyview_irq_uninstall; | |
86e83e35 CW |
4310 | dev->driver->enable_vblank = i965_enable_vblank; |
4311 | dev->driver->disable_vblank = i965_disable_vblank; | |
fa00abe0 | 4312 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
b963291c | 4313 | } else if (INTEL_INFO(dev_priv)->gen >= 8) { |
abd58f01 | 4314 | dev->driver->irq_handler = gen8_irq_handler; |
723761b8 | 4315 | dev->driver->irq_preinstall = gen8_irq_reset; |
abd58f01 BW |
4316 | dev->driver->irq_postinstall = gen8_irq_postinstall; |
4317 | dev->driver->irq_uninstall = gen8_irq_uninstall; | |
4318 | dev->driver->enable_vblank = gen8_enable_vblank; | |
4319 | dev->driver->disable_vblank = gen8_disable_vblank; | |
cc3f90f0 | 4320 | if (IS_GEN9_LP(dev_priv)) |
e0a20ad7 | 4321 | dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup; |
6e266956 | 4322 | else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv)) |
6dbf30ce VS |
4323 | dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup; |
4324 | else | |
3a3b3c7d | 4325 | dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; |
6e266956 | 4326 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
f71d4af4 | 4327 | dev->driver->irq_handler = ironlake_irq_handler; |
723761b8 | 4328 | dev->driver->irq_preinstall = ironlake_irq_reset; |
f71d4af4 JB |
4329 | dev->driver->irq_postinstall = ironlake_irq_postinstall; |
4330 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
4331 | dev->driver->enable_vblank = ironlake_enable_vblank; | |
4332 | dev->driver->disable_vblank = ironlake_disable_vblank; | |
23bb4cb5 | 4333 | dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; |
f71d4af4 | 4334 | } else { |
7e22dbbb | 4335 | if (IS_GEN2(dev_priv)) { |
c2798b19 CW |
4336 | dev->driver->irq_preinstall = i8xx_irq_preinstall; |
4337 | dev->driver->irq_postinstall = i8xx_irq_postinstall; | |
4338 | dev->driver->irq_handler = i8xx_irq_handler; | |
4339 | dev->driver->irq_uninstall = i8xx_irq_uninstall; | |
86e83e35 CW |
4340 | dev->driver->enable_vblank = i8xx_enable_vblank; |
4341 | dev->driver->disable_vblank = i8xx_disable_vblank; | |
7e22dbbb | 4342 | } else if (IS_GEN3(dev_priv)) { |
a266c7d5 CW |
4343 | dev->driver->irq_preinstall = i915_irq_preinstall; |
4344 | dev->driver->irq_postinstall = i915_irq_postinstall; | |
4345 | dev->driver->irq_uninstall = i915_irq_uninstall; | |
4346 | dev->driver->irq_handler = i915_irq_handler; | |
86e83e35 CW |
4347 | dev->driver->enable_vblank = i8xx_enable_vblank; |
4348 | dev->driver->disable_vblank = i8xx_disable_vblank; | |
c2798b19 | 4349 | } else { |
a266c7d5 CW |
4350 | dev->driver->irq_preinstall = i965_irq_preinstall; |
4351 | dev->driver->irq_postinstall = i965_irq_postinstall; | |
4352 | dev->driver->irq_uninstall = i965_irq_uninstall; | |
4353 | dev->driver->irq_handler = i965_irq_handler; | |
86e83e35 CW |
4354 | dev->driver->enable_vblank = i965_enable_vblank; |
4355 | dev->driver->disable_vblank = i965_disable_vblank; | |
c2798b19 | 4356 | } |
778eb334 VS |
4357 | if (I915_HAS_HOTPLUG(dev_priv)) |
4358 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; | |
f71d4af4 JB |
4359 | } |
4360 | } | |
20afbda2 | 4361 | |
fca52a55 DV |
4362 | /** |
4363 | * intel_irq_install - enables the hardware interrupt | |
4364 | * @dev_priv: i915 device instance | |
4365 | * | |
4366 | * This function enables the hardware interrupt handling, but leaves the hotplug | |
4367 | * handling still disabled. It is called after intel_irq_init(). | |
4368 | * | |
4369 | * In the driver load and resume code we need working interrupts in a few places | |
4370 | * but don't want to deal with the hassle of concurrent probe and hotplug | |
4371 | * workers. Hence the split into this two-stage approach. | |
4372 | */ | |
2aeb7d3a DV |
4373 | int intel_irq_install(struct drm_i915_private *dev_priv) |
4374 | { | |
4375 | /* | |
4376 | * We enable some interrupt sources in our postinstall hooks, so mark | |
4377 | * interrupts as enabled _before_ actually enabling them to avoid | |
4378 | * special cases in our ordering checks. | |
4379 | */ | |
4380 | dev_priv->pm.irqs_enabled = true; | |
4381 | ||
91c8a326 | 4382 | return drm_irq_install(&dev_priv->drm, dev_priv->drm.pdev->irq); |
2aeb7d3a DV |
4383 | } |
4384 | ||
fca52a55 DV |
4385 | /** |
4386 | * intel_irq_uninstall - finilizes all irq handling | |
4387 | * @dev_priv: i915 device instance | |
4388 | * | |
4389 | * This stops interrupt and hotplug handling and unregisters and frees all | |
4390 | * resources acquired in the init functions. | |
4391 | */ | |
2aeb7d3a DV |
4392 | void intel_irq_uninstall(struct drm_i915_private *dev_priv) |
4393 | { | |
91c8a326 | 4394 | drm_irq_uninstall(&dev_priv->drm); |
2aeb7d3a DV |
4395 | intel_hpd_cancel_work(dev_priv); |
4396 | dev_priv->pm.irqs_enabled = false; | |
4397 | } | |
4398 | ||
fca52a55 DV |
4399 | /** |
4400 | * intel_runtime_pm_disable_interrupts - runtime interrupt disabling | |
4401 | * @dev_priv: i915 device instance | |
4402 | * | |
4403 | * This function is used to disable interrupts at runtime, both in the runtime | |
4404 | * pm and the system suspend/resume code. | |
4405 | */ | |
b963291c | 4406 | void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv) |
c67a470b | 4407 | { |
91c8a326 | 4408 | dev_priv->drm.driver->irq_uninstall(&dev_priv->drm); |
2aeb7d3a | 4409 | dev_priv->pm.irqs_enabled = false; |
91c8a326 | 4410 | synchronize_irq(dev_priv->drm.irq); |
c67a470b PZ |
4411 | } |
4412 | ||
fca52a55 DV |
4413 | /** |
4414 | * intel_runtime_pm_enable_interrupts - runtime interrupt enabling | |
4415 | * @dev_priv: i915 device instance | |
4416 | * | |
4417 | * This function is used to enable interrupts at runtime, both in the runtime | |
4418 | * pm and the system suspend/resume code. | |
4419 | */ | |
b963291c | 4420 | void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv) |
c67a470b | 4421 | { |
2aeb7d3a | 4422 | dev_priv->pm.irqs_enabled = true; |
91c8a326 CW |
4423 | dev_priv->drm.driver->irq_preinstall(&dev_priv->drm); |
4424 | dev_priv->drm.driver->irq_postinstall(&dev_priv->drm); | |
c67a470b | 4425 | } |