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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
63eeaf38 | 31 | #include <linux/sysrq.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
b2c88f5b | 33 | #include <linux/circ_buf.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/i915_drm.h> | |
1da177e4 | 36 | #include "i915_drv.h" |
1c5d22f7 | 37 | #include "i915_trace.h" |
79e53945 | 38 | #include "intel_drv.h" |
1da177e4 | 39 | |
fca52a55 DV |
40 | /** |
41 | * DOC: interrupt handling | |
42 | * | |
43 | * These functions provide the basic support for enabling and disabling the | |
44 | * interrupt handling support. There's a lot more functionality in i915_irq.c | |
45 | * and related files, but that will be described in separate chapters. | |
46 | */ | |
47 | ||
e5868a31 EE |
48 | static const u32 hpd_ibx[] = { |
49 | [HPD_CRT] = SDE_CRT_HOTPLUG, | |
50 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, | |
51 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG, | |
52 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG, | |
53 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG | |
54 | }; | |
55 | ||
56 | static const u32 hpd_cpt[] = { | |
57 | [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, | |
73c352a2 | 58 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, |
e5868a31 EE |
59 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
60 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
61 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT | |
62 | }; | |
63 | ||
64 | static const u32 hpd_mask_i915[] = { | |
65 | [HPD_CRT] = CRT_HOTPLUG_INT_EN, | |
66 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, | |
67 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, | |
68 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, | |
69 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, | |
70 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN | |
71 | }; | |
72 | ||
704cfb87 | 73 | static const u32 hpd_status_g4x[] = { |
e5868a31 EE |
74 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
75 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, | |
76 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, | |
77 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
78 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
79 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
80 | }; | |
81 | ||
e5868a31 EE |
82 | static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ |
83 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, | |
84 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, | |
85 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, | |
86 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
87 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
88 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
89 | }; | |
90 | ||
5c502442 | 91 | /* IIR can theoretically queue up two events. Be paranoid. */ |
f86f3fb0 | 92 | #define GEN8_IRQ_RESET_NDX(type, which) do { \ |
5c502442 PZ |
93 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ |
94 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
95 | I915_WRITE(GEN8_##type##_IER(which), 0); \ | |
96 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
97 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
98 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
99 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
100 | } while (0) | |
101 | ||
f86f3fb0 | 102 | #define GEN5_IRQ_RESET(type) do { \ |
a9d356a6 | 103 | I915_WRITE(type##IMR, 0xffffffff); \ |
5c502442 | 104 | POSTING_READ(type##IMR); \ |
a9d356a6 | 105 | I915_WRITE(type##IER, 0); \ |
5c502442 PZ |
106 | I915_WRITE(type##IIR, 0xffffffff); \ |
107 | POSTING_READ(type##IIR); \ | |
108 | I915_WRITE(type##IIR, 0xffffffff); \ | |
109 | POSTING_READ(type##IIR); \ | |
a9d356a6 PZ |
110 | } while (0) |
111 | ||
337ba017 PZ |
112 | /* |
113 | * We should clear IMR at preinstall/uninstall, and just check at postinstall. | |
114 | */ | |
115 | #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \ | |
116 | u32 val = I915_READ(reg); \ | |
117 | if (val) { \ | |
118 | WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \ | |
119 | (reg), val); \ | |
120 | I915_WRITE((reg), 0xffffffff); \ | |
121 | POSTING_READ(reg); \ | |
122 | I915_WRITE((reg), 0xffffffff); \ | |
123 | POSTING_READ(reg); \ | |
124 | } \ | |
125 | } while (0) | |
126 | ||
35079899 | 127 | #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \ |
337ba017 | 128 | GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \ |
35079899 | 129 | I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \ |
7d1bd539 VS |
130 | I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \ |
131 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
35079899 PZ |
132 | } while (0) |
133 | ||
134 | #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \ | |
337ba017 | 135 | GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \ |
35079899 | 136 | I915_WRITE(type##IER, (ier_val)); \ |
7d1bd539 VS |
137 | I915_WRITE(type##IMR, (imr_val)); \ |
138 | POSTING_READ(type##IMR); \ | |
35079899 PZ |
139 | } while (0) |
140 | ||
036a4a7d | 141 | /* For display hotplug interrupt */ |
47339cd9 | 142 | void |
2d1013dd | 143 | ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask) |
036a4a7d | 144 | { |
4bc9d430 DV |
145 | assert_spin_locked(&dev_priv->irq_lock); |
146 | ||
9df7575f | 147 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 148 | return; |
c67a470b | 149 | |
1ec14ad3 CW |
150 | if ((dev_priv->irq_mask & mask) != 0) { |
151 | dev_priv->irq_mask &= ~mask; | |
152 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 153 | POSTING_READ(DEIMR); |
036a4a7d ZW |
154 | } |
155 | } | |
156 | ||
47339cd9 | 157 | void |
2d1013dd | 158 | ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask) |
036a4a7d | 159 | { |
4bc9d430 DV |
160 | assert_spin_locked(&dev_priv->irq_lock); |
161 | ||
06ffc778 | 162 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 163 | return; |
c67a470b | 164 | |
1ec14ad3 CW |
165 | if ((dev_priv->irq_mask & mask) != mask) { |
166 | dev_priv->irq_mask |= mask; | |
167 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 168 | POSTING_READ(DEIMR); |
036a4a7d ZW |
169 | } |
170 | } | |
171 | ||
43eaea13 PZ |
172 | /** |
173 | * ilk_update_gt_irq - update GTIMR | |
174 | * @dev_priv: driver private | |
175 | * @interrupt_mask: mask of interrupt bits to update | |
176 | * @enabled_irq_mask: mask of interrupt bits to enable | |
177 | */ | |
178 | static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, | |
179 | uint32_t interrupt_mask, | |
180 | uint32_t enabled_irq_mask) | |
181 | { | |
182 | assert_spin_locked(&dev_priv->irq_lock); | |
183 | ||
9df7575f | 184 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 185 | return; |
c67a470b | 186 | |
43eaea13 PZ |
187 | dev_priv->gt_irq_mask &= ~interrupt_mask; |
188 | dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); | |
189 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
190 | POSTING_READ(GTIMR); | |
191 | } | |
192 | ||
480c8033 | 193 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
43eaea13 PZ |
194 | { |
195 | ilk_update_gt_irq(dev_priv, mask, mask); | |
196 | } | |
197 | ||
480c8033 | 198 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
43eaea13 PZ |
199 | { |
200 | ilk_update_gt_irq(dev_priv, mask, 0); | |
201 | } | |
202 | ||
edbfdb45 PZ |
203 | /** |
204 | * snb_update_pm_irq - update GEN6_PMIMR | |
205 | * @dev_priv: driver private | |
206 | * @interrupt_mask: mask of interrupt bits to update | |
207 | * @enabled_irq_mask: mask of interrupt bits to enable | |
208 | */ | |
209 | static void snb_update_pm_irq(struct drm_i915_private *dev_priv, | |
210 | uint32_t interrupt_mask, | |
211 | uint32_t enabled_irq_mask) | |
212 | { | |
605cd25b | 213 | uint32_t new_val; |
edbfdb45 PZ |
214 | |
215 | assert_spin_locked(&dev_priv->irq_lock); | |
216 | ||
9df7575f | 217 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 218 | return; |
c67a470b | 219 | |
605cd25b | 220 | new_val = dev_priv->pm_irq_mask; |
f52ecbcf PZ |
221 | new_val &= ~interrupt_mask; |
222 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
223 | ||
605cd25b PZ |
224 | if (new_val != dev_priv->pm_irq_mask) { |
225 | dev_priv->pm_irq_mask = new_val; | |
226 | I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask); | |
f52ecbcf PZ |
227 | POSTING_READ(GEN6_PMIMR); |
228 | } | |
edbfdb45 PZ |
229 | } |
230 | ||
480c8033 | 231 | void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
edbfdb45 PZ |
232 | { |
233 | snb_update_pm_irq(dev_priv, mask, mask); | |
234 | } | |
235 | ||
480c8033 | 236 | void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
edbfdb45 PZ |
237 | { |
238 | snb_update_pm_irq(dev_priv, mask, 0); | |
239 | } | |
240 | ||
0961021a BW |
241 | /** |
242 | * bdw_update_pm_irq - update GT interrupt 2 | |
243 | * @dev_priv: driver private | |
244 | * @interrupt_mask: mask of interrupt bits to update | |
245 | * @enabled_irq_mask: mask of interrupt bits to enable | |
246 | * | |
247 | * Copied from the snb function, updated with relevant register offsets | |
248 | */ | |
249 | static void bdw_update_pm_irq(struct drm_i915_private *dev_priv, | |
250 | uint32_t interrupt_mask, | |
251 | uint32_t enabled_irq_mask) | |
252 | { | |
253 | uint32_t new_val; | |
254 | ||
255 | assert_spin_locked(&dev_priv->irq_lock); | |
256 | ||
9df7575f | 257 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
0961021a BW |
258 | return; |
259 | ||
260 | new_val = dev_priv->pm_irq_mask; | |
261 | new_val &= ~interrupt_mask; | |
262 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
263 | ||
264 | if (new_val != dev_priv->pm_irq_mask) { | |
265 | dev_priv->pm_irq_mask = new_val; | |
266 | I915_WRITE(GEN8_GT_IMR(2), dev_priv->pm_irq_mask); | |
267 | POSTING_READ(GEN8_GT_IMR(2)); | |
268 | } | |
269 | } | |
270 | ||
480c8033 | 271 | void gen8_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
0961021a BW |
272 | { |
273 | bdw_update_pm_irq(dev_priv, mask, mask); | |
274 | } | |
275 | ||
480c8033 | 276 | void gen8_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
0961021a BW |
277 | { |
278 | bdw_update_pm_irq(dev_priv, mask, 0); | |
279 | } | |
280 | ||
fee884ed DV |
281 | /** |
282 | * ibx_display_interrupt_update - update SDEIMR | |
283 | * @dev_priv: driver private | |
284 | * @interrupt_mask: mask of interrupt bits to update | |
285 | * @enabled_irq_mask: mask of interrupt bits to enable | |
286 | */ | |
47339cd9 DV |
287 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
288 | uint32_t interrupt_mask, | |
289 | uint32_t enabled_irq_mask) | |
fee884ed DV |
290 | { |
291 | uint32_t sdeimr = I915_READ(SDEIMR); | |
292 | sdeimr &= ~interrupt_mask; | |
293 | sdeimr |= (~enabled_irq_mask & interrupt_mask); | |
294 | ||
295 | assert_spin_locked(&dev_priv->irq_lock); | |
296 | ||
9df7575f | 297 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 298 | return; |
c67a470b | 299 | |
fee884ed DV |
300 | I915_WRITE(SDEIMR, sdeimr); |
301 | POSTING_READ(SDEIMR); | |
302 | } | |
8664281b | 303 | |
b5ea642a | 304 | static void |
755e9019 ID |
305 | __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
306 | u32 enable_mask, u32 status_mask) | |
7c463586 | 307 | { |
46c06a30 | 308 | u32 reg = PIPESTAT(pipe); |
755e9019 | 309 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 310 | |
b79480ba | 311 | assert_spin_locked(&dev_priv->irq_lock); |
d518ce50 | 312 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
b79480ba | 313 | |
04feced9 VS |
314 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
315 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
316 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
317 | pipe_name(pipe), enable_mask, status_mask)) | |
755e9019 ID |
318 | return; |
319 | ||
320 | if ((pipestat & enable_mask) == enable_mask) | |
46c06a30 VS |
321 | return; |
322 | ||
91d181dd ID |
323 | dev_priv->pipestat_irq_mask[pipe] |= status_mask; |
324 | ||
46c06a30 | 325 | /* Enable the interrupt, clear any pending status */ |
755e9019 | 326 | pipestat |= enable_mask | status_mask; |
46c06a30 VS |
327 | I915_WRITE(reg, pipestat); |
328 | POSTING_READ(reg); | |
7c463586 KP |
329 | } |
330 | ||
b5ea642a | 331 | static void |
755e9019 ID |
332 | __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
333 | u32 enable_mask, u32 status_mask) | |
7c463586 | 334 | { |
46c06a30 | 335 | u32 reg = PIPESTAT(pipe); |
755e9019 | 336 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 337 | |
b79480ba | 338 | assert_spin_locked(&dev_priv->irq_lock); |
d518ce50 | 339 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
b79480ba | 340 | |
04feced9 VS |
341 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
342 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
343 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
344 | pipe_name(pipe), enable_mask, status_mask)) | |
46c06a30 VS |
345 | return; |
346 | ||
755e9019 ID |
347 | if ((pipestat & enable_mask) == 0) |
348 | return; | |
349 | ||
91d181dd ID |
350 | dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; |
351 | ||
755e9019 | 352 | pipestat &= ~enable_mask; |
46c06a30 VS |
353 | I915_WRITE(reg, pipestat); |
354 | POSTING_READ(reg); | |
7c463586 KP |
355 | } |
356 | ||
10c59c51 ID |
357 | static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask) |
358 | { | |
359 | u32 enable_mask = status_mask << 16; | |
360 | ||
361 | /* | |
724a6905 VS |
362 | * On pipe A we don't support the PSR interrupt yet, |
363 | * on pipe B and C the same bit MBZ. | |
10c59c51 ID |
364 | */ |
365 | if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV)) | |
366 | return 0; | |
724a6905 VS |
367 | /* |
368 | * On pipe B and C we don't support the PSR interrupt yet, on pipe | |
369 | * A the same bit is for perf counters which we don't use either. | |
370 | */ | |
371 | if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV)) | |
372 | return 0; | |
10c59c51 ID |
373 | |
374 | enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | | |
375 | SPRITE0_FLIP_DONE_INT_EN_VLV | | |
376 | SPRITE1_FLIP_DONE_INT_EN_VLV); | |
377 | if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV) | |
378 | enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV; | |
379 | if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV) | |
380 | enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; | |
381 | ||
382 | return enable_mask; | |
383 | } | |
384 | ||
755e9019 ID |
385 | void |
386 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
387 | u32 status_mask) | |
388 | { | |
389 | u32 enable_mask; | |
390 | ||
10c59c51 ID |
391 | if (IS_VALLEYVIEW(dev_priv->dev)) |
392 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, | |
393 | status_mask); | |
394 | else | |
395 | enable_mask = status_mask << 16; | |
755e9019 ID |
396 | __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
397 | } | |
398 | ||
399 | void | |
400 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
401 | u32 status_mask) | |
402 | { | |
403 | u32 enable_mask; | |
404 | ||
10c59c51 ID |
405 | if (IS_VALLEYVIEW(dev_priv->dev)) |
406 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, | |
407 | status_mask); | |
408 | else | |
409 | enable_mask = status_mask << 16; | |
755e9019 ID |
410 | __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
411 | } | |
412 | ||
01c66889 | 413 | /** |
f49e38dd | 414 | * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion |
01c66889 | 415 | */ |
f49e38dd | 416 | static void i915_enable_asle_pipestat(struct drm_device *dev) |
01c66889 | 417 | { |
2d1013dd | 418 | struct drm_i915_private *dev_priv = dev->dev_private; |
1ec14ad3 | 419 | |
f49e38dd JN |
420 | if (!dev_priv->opregion.asle || !IS_MOBILE(dev)) |
421 | return; | |
422 | ||
13321786 | 423 | spin_lock_irq(&dev_priv->irq_lock); |
01c66889 | 424 | |
755e9019 | 425 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); |
f898780b | 426 | if (INTEL_INFO(dev)->gen >= 4) |
3b6c42e8 | 427 | i915_enable_pipestat(dev_priv, PIPE_A, |
755e9019 | 428 | PIPE_LEGACY_BLC_EVENT_STATUS); |
1ec14ad3 | 429 | |
13321786 | 430 | spin_unlock_irq(&dev_priv->irq_lock); |
01c66889 ZY |
431 | } |
432 | ||
0a3e67a4 JB |
433 | /** |
434 | * i915_pipe_enabled - check if a pipe is enabled | |
435 | * @dev: DRM device | |
436 | * @pipe: pipe to check | |
437 | * | |
438 | * Reading certain registers when the pipe is disabled can hang the chip. | |
439 | * Use this routine to make sure the PLL is running and the pipe is active | |
440 | * before reading such registers if unsure. | |
441 | */ | |
442 | static int | |
443 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
444 | { | |
2d1013dd | 445 | struct drm_i915_private *dev_priv = dev->dev_private; |
702e7a56 | 446 | |
a01025af DV |
447 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
448 | /* Locking is horribly broken here, but whatever. */ | |
449 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
450 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
71f8ba6b | 451 | |
a01025af DV |
452 | return intel_crtc->active; |
453 | } else { | |
454 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; | |
455 | } | |
0a3e67a4 JB |
456 | } |
457 | ||
f75f3746 VS |
458 | /* |
459 | * This timing diagram depicts the video signal in and | |
460 | * around the vertical blanking period. | |
461 | * | |
462 | * Assumptions about the fictitious mode used in this example: | |
463 | * vblank_start >= 3 | |
464 | * vsync_start = vblank_start + 1 | |
465 | * vsync_end = vblank_start + 2 | |
466 | * vtotal = vblank_start + 3 | |
467 | * | |
468 | * start of vblank: | |
469 | * latch double buffered registers | |
470 | * increment frame counter (ctg+) | |
471 | * generate start of vblank interrupt (gen4+) | |
472 | * | | |
473 | * | frame start: | |
474 | * | generate frame start interrupt (aka. vblank interrupt) (gmch) | |
475 | * | may be shifted forward 1-3 extra lines via PIPECONF | |
476 | * | | | |
477 | * | | start of vsync: | |
478 | * | | generate vsync interrupt | |
479 | * | | | | |
480 | * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx | |
481 | * . \hs/ . \hs/ \hs/ \hs/ . \hs/ | |
482 | * ----va---> <-----------------vb--------------------> <--------va------------- | |
483 | * | | <----vs-----> | | |
484 | * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2) | |
485 | * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+) | |
486 | * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi) | |
487 | * | | | | |
488 | * last visible pixel first visible pixel | |
489 | * | increment frame counter (gen3/4) | |
490 | * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4) | |
491 | * | |
492 | * x = horizontal active | |
493 | * _ = horizontal blanking | |
494 | * hs = horizontal sync | |
495 | * va = vertical active | |
496 | * vb = vertical blanking | |
497 | * vs = vertical sync | |
498 | * vbs = vblank_start (number) | |
499 | * | |
500 | * Summary: | |
501 | * - most events happen at the start of horizontal sync | |
502 | * - frame start happens at the start of horizontal blank, 1-4 lines | |
503 | * (depending on PIPECONF settings) after the start of vblank | |
504 | * - gen3/4 pixel and frame counter are synchronized with the start | |
505 | * of horizontal active on the first line of vertical active | |
506 | */ | |
507 | ||
4cdb83ec VS |
508 | static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe) |
509 | { | |
510 | /* Gen2 doesn't have a hardware frame counter */ | |
511 | return 0; | |
512 | } | |
513 | ||
42f52ef8 KP |
514 | /* Called from drm generic code, passed a 'crtc', which |
515 | * we use as a pipe index | |
516 | */ | |
f71d4af4 | 517 | static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
0a3e67a4 | 518 | { |
2d1013dd | 519 | struct drm_i915_private *dev_priv = dev->dev_private; |
0a3e67a4 JB |
520 | unsigned long high_frame; |
521 | unsigned long low_frame; | |
0b2a8e09 | 522 | u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal; |
0a3e67a4 JB |
523 | |
524 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 525 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 526 | "pipe %c\n", pipe_name(pipe)); |
0a3e67a4 JB |
527 | return 0; |
528 | } | |
529 | ||
391f75e2 VS |
530 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
531 | struct intel_crtc *intel_crtc = | |
532 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
533 | const struct drm_display_mode *mode = | |
534 | &intel_crtc->config.adjusted_mode; | |
535 | ||
0b2a8e09 VS |
536 | htotal = mode->crtc_htotal; |
537 | hsync_start = mode->crtc_hsync_start; | |
538 | vbl_start = mode->crtc_vblank_start; | |
539 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
540 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
391f75e2 | 541 | } else { |
a2d213dd | 542 | enum transcoder cpu_transcoder = (enum transcoder) pipe; |
391f75e2 VS |
543 | |
544 | htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1; | |
0b2a8e09 | 545 | hsync_start = (I915_READ(HSYNC(cpu_transcoder)) & 0x1fff) + 1; |
391f75e2 | 546 | vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1; |
0b2a8e09 VS |
547 | if ((I915_READ(PIPECONF(cpu_transcoder)) & |
548 | PIPECONF_INTERLACE_MASK) != PIPECONF_PROGRESSIVE) | |
549 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
391f75e2 VS |
550 | } |
551 | ||
0b2a8e09 VS |
552 | /* Convert to pixel count */ |
553 | vbl_start *= htotal; | |
554 | ||
555 | /* Start of vblank event occurs at start of hsync */ | |
556 | vbl_start -= htotal - hsync_start; | |
557 | ||
9db4a9c7 JB |
558 | high_frame = PIPEFRAME(pipe); |
559 | low_frame = PIPEFRAMEPIXEL(pipe); | |
5eddb70b | 560 | |
0a3e67a4 JB |
561 | /* |
562 | * High & low register fields aren't synchronized, so make sure | |
563 | * we get a low value that's stable across two reads of the high | |
564 | * register. | |
565 | */ | |
566 | do { | |
5eddb70b | 567 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
391f75e2 | 568 | low = I915_READ(low_frame); |
5eddb70b | 569 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
0a3e67a4 JB |
570 | } while (high1 != high2); |
571 | ||
5eddb70b | 572 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
391f75e2 | 573 | pixel = low & PIPE_PIXEL_MASK; |
5eddb70b | 574 | low >>= PIPE_FRAME_LOW_SHIFT; |
391f75e2 VS |
575 | |
576 | /* | |
577 | * The frame counter increments at beginning of active. | |
578 | * Cook up a vblank counter by also checking the pixel | |
579 | * counter against vblank start. | |
580 | */ | |
edc08d0a | 581 | return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; |
0a3e67a4 JB |
582 | } |
583 | ||
f71d4af4 | 584 | static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
9880b7a5 | 585 | { |
2d1013dd | 586 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 587 | int reg = PIPE_FRMCOUNT_GM45(pipe); |
9880b7a5 JB |
588 | |
589 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 590 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 591 | "pipe %c\n", pipe_name(pipe)); |
9880b7a5 JB |
592 | return 0; |
593 | } | |
594 | ||
595 | return I915_READ(reg); | |
596 | } | |
597 | ||
ad3543ed MK |
598 | /* raw reads, only for fast reads of display block, no need for forcewake etc. */ |
599 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) | |
ad3543ed | 600 | |
a225f079 VS |
601 | static int __intel_get_crtc_scanline(struct intel_crtc *crtc) |
602 | { | |
603 | struct drm_device *dev = crtc->base.dev; | |
604 | struct drm_i915_private *dev_priv = dev->dev_private; | |
605 | const struct drm_display_mode *mode = &crtc->config.adjusted_mode; | |
606 | enum pipe pipe = crtc->pipe; | |
80715b2f | 607 | int position, vtotal; |
a225f079 | 608 | |
80715b2f | 609 | vtotal = mode->crtc_vtotal; |
a225f079 VS |
610 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
611 | vtotal /= 2; | |
612 | ||
613 | if (IS_GEN2(dev)) | |
614 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; | |
615 | else | |
616 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; | |
617 | ||
618 | /* | |
80715b2f VS |
619 | * See update_scanline_offset() for the details on the |
620 | * scanline_offset adjustment. | |
a225f079 | 621 | */ |
80715b2f | 622 | return (position + crtc->scanline_offset) % vtotal; |
a225f079 VS |
623 | } |
624 | ||
f71d4af4 | 625 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
abca9e45 VS |
626 | unsigned int flags, int *vpos, int *hpos, |
627 | ktime_t *stime, ktime_t *etime) | |
0af7e4df | 628 | { |
c2baf4b7 VS |
629 | struct drm_i915_private *dev_priv = dev->dev_private; |
630 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
631 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
632 | const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; | |
3aa18df8 | 633 | int position; |
78e8fc6b | 634 | int vbl_start, vbl_end, hsync_start, htotal, vtotal; |
0af7e4df MK |
635 | bool in_vbl = true; |
636 | int ret = 0; | |
ad3543ed | 637 | unsigned long irqflags; |
0af7e4df | 638 | |
c2baf4b7 | 639 | if (!intel_crtc->active) { |
0af7e4df | 640 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
9db4a9c7 | 641 | "pipe %c\n", pipe_name(pipe)); |
0af7e4df MK |
642 | return 0; |
643 | } | |
644 | ||
c2baf4b7 | 645 | htotal = mode->crtc_htotal; |
78e8fc6b | 646 | hsync_start = mode->crtc_hsync_start; |
c2baf4b7 VS |
647 | vtotal = mode->crtc_vtotal; |
648 | vbl_start = mode->crtc_vblank_start; | |
649 | vbl_end = mode->crtc_vblank_end; | |
0af7e4df | 650 | |
d31faf65 VS |
651 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
652 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
653 | vbl_end /= 2; | |
654 | vtotal /= 2; | |
655 | } | |
656 | ||
c2baf4b7 VS |
657 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; |
658 | ||
ad3543ed MK |
659 | /* |
660 | * Lock uncore.lock, as we will do multiple timing critical raw | |
661 | * register reads, potentially with preemption disabled, so the | |
662 | * following code must not block on uncore.lock. | |
663 | */ | |
664 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
78e8fc6b | 665 | |
ad3543ed MK |
666 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ |
667 | ||
668 | /* Get optional system timestamp before query. */ | |
669 | if (stime) | |
670 | *stime = ktime_get(); | |
671 | ||
7c06b08a | 672 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
0af7e4df MK |
673 | /* No obvious pixelcount register. Only query vertical |
674 | * scanout position from Display scan line register. | |
675 | */ | |
a225f079 | 676 | position = __intel_get_crtc_scanline(intel_crtc); |
0af7e4df MK |
677 | } else { |
678 | /* Have access to pixelcount since start of frame. | |
679 | * We can split this into vertical and horizontal | |
680 | * scanout position. | |
681 | */ | |
ad3543ed | 682 | position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; |
0af7e4df | 683 | |
3aa18df8 VS |
684 | /* convert to pixel counts */ |
685 | vbl_start *= htotal; | |
686 | vbl_end *= htotal; | |
687 | vtotal *= htotal; | |
78e8fc6b | 688 | |
7e78f1cb VS |
689 | /* |
690 | * In interlaced modes, the pixel counter counts all pixels, | |
691 | * so one field will have htotal more pixels. In order to avoid | |
692 | * the reported position from jumping backwards when the pixel | |
693 | * counter is beyond the length of the shorter field, just | |
694 | * clamp the position the length of the shorter field. This | |
695 | * matches how the scanline counter based position works since | |
696 | * the scanline counter doesn't count the two half lines. | |
697 | */ | |
698 | if (position >= vtotal) | |
699 | position = vtotal - 1; | |
700 | ||
78e8fc6b VS |
701 | /* |
702 | * Start of vblank interrupt is triggered at start of hsync, | |
703 | * just prior to the first active line of vblank. However we | |
704 | * consider lines to start at the leading edge of horizontal | |
705 | * active. So, should we get here before we've crossed into | |
706 | * the horizontal active of the first line in vblank, we would | |
707 | * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that, | |
708 | * always add htotal-hsync_start to the current pixel position. | |
709 | */ | |
710 | position = (position + htotal - hsync_start) % vtotal; | |
0af7e4df MK |
711 | } |
712 | ||
ad3543ed MK |
713 | /* Get optional system timestamp after query. */ |
714 | if (etime) | |
715 | *etime = ktime_get(); | |
716 | ||
717 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ | |
718 | ||
719 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
720 | ||
3aa18df8 VS |
721 | in_vbl = position >= vbl_start && position < vbl_end; |
722 | ||
723 | /* | |
724 | * While in vblank, position will be negative | |
725 | * counting up towards 0 at vbl_end. And outside | |
726 | * vblank, position will be positive counting | |
727 | * up since vbl_end. | |
728 | */ | |
729 | if (position >= vbl_start) | |
730 | position -= vbl_end; | |
731 | else | |
732 | position += vtotal - vbl_end; | |
0af7e4df | 733 | |
7c06b08a | 734 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
3aa18df8 VS |
735 | *vpos = position; |
736 | *hpos = 0; | |
737 | } else { | |
738 | *vpos = position / htotal; | |
739 | *hpos = position - (*vpos * htotal); | |
740 | } | |
0af7e4df | 741 | |
0af7e4df MK |
742 | /* In vblank? */ |
743 | if (in_vbl) | |
3d3cbd84 | 744 | ret |= DRM_SCANOUTPOS_IN_VBLANK; |
0af7e4df MK |
745 | |
746 | return ret; | |
747 | } | |
748 | ||
a225f079 VS |
749 | int intel_get_crtc_scanline(struct intel_crtc *crtc) |
750 | { | |
751 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
752 | unsigned long irqflags; | |
753 | int position; | |
754 | ||
755 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
756 | position = __intel_get_crtc_scanline(crtc); | |
757 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
758 | ||
759 | return position; | |
760 | } | |
761 | ||
f71d4af4 | 762 | static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
0af7e4df MK |
763 | int *max_error, |
764 | struct timeval *vblank_time, | |
765 | unsigned flags) | |
766 | { | |
4041b853 | 767 | struct drm_crtc *crtc; |
0af7e4df | 768 | |
7eb552ae | 769 | if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { |
4041b853 | 770 | DRM_ERROR("Invalid crtc %d\n", pipe); |
0af7e4df MK |
771 | return -EINVAL; |
772 | } | |
773 | ||
774 | /* Get drm_crtc to timestamp: */ | |
4041b853 CW |
775 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
776 | if (crtc == NULL) { | |
777 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
778 | return -EINVAL; | |
779 | } | |
780 | ||
781 | if (!crtc->enabled) { | |
782 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); | |
783 | return -EBUSY; | |
784 | } | |
0af7e4df MK |
785 | |
786 | /* Helper routine in DRM core does all the work: */ | |
4041b853 CW |
787 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
788 | vblank_time, flags, | |
7da903ef VS |
789 | crtc, |
790 | &to_intel_crtc(crtc)->config.adjusted_mode); | |
0af7e4df MK |
791 | } |
792 | ||
67c347ff JN |
793 | static bool intel_hpd_irq_event(struct drm_device *dev, |
794 | struct drm_connector *connector) | |
321a1b30 EE |
795 | { |
796 | enum drm_connector_status old_status; | |
797 | ||
798 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); | |
799 | old_status = connector->status; | |
800 | ||
801 | connector->status = connector->funcs->detect(connector, false); | |
67c347ff JN |
802 | if (old_status == connector->status) |
803 | return false; | |
804 | ||
805 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n", | |
321a1b30 | 806 | connector->base.id, |
c23cc417 | 807 | connector->name, |
67c347ff JN |
808 | drm_get_connector_status_name(old_status), |
809 | drm_get_connector_status_name(connector->status)); | |
810 | ||
811 | return true; | |
321a1b30 EE |
812 | } |
813 | ||
13cf5504 DA |
814 | static void i915_digport_work_func(struct work_struct *work) |
815 | { | |
816 | struct drm_i915_private *dev_priv = | |
817 | container_of(work, struct drm_i915_private, dig_port_work); | |
13cf5504 DA |
818 | u32 long_port_mask, short_port_mask; |
819 | struct intel_digital_port *intel_dig_port; | |
820 | int i, ret; | |
821 | u32 old_bits = 0; | |
822 | ||
4cb21832 | 823 | spin_lock_irq(&dev_priv->irq_lock); |
13cf5504 DA |
824 | long_port_mask = dev_priv->long_hpd_port_mask; |
825 | dev_priv->long_hpd_port_mask = 0; | |
826 | short_port_mask = dev_priv->short_hpd_port_mask; | |
827 | dev_priv->short_hpd_port_mask = 0; | |
4cb21832 | 828 | spin_unlock_irq(&dev_priv->irq_lock); |
13cf5504 DA |
829 | |
830 | for (i = 0; i < I915_MAX_PORTS; i++) { | |
831 | bool valid = false; | |
832 | bool long_hpd = false; | |
833 | intel_dig_port = dev_priv->hpd_irq_port[i]; | |
834 | if (!intel_dig_port || !intel_dig_port->hpd_pulse) | |
835 | continue; | |
836 | ||
837 | if (long_port_mask & (1 << i)) { | |
838 | valid = true; | |
839 | long_hpd = true; | |
840 | } else if (short_port_mask & (1 << i)) | |
841 | valid = true; | |
842 | ||
843 | if (valid) { | |
844 | ret = intel_dig_port->hpd_pulse(intel_dig_port, long_hpd); | |
845 | if (ret == true) { | |
846 | /* if we get true fallback to old school hpd */ | |
847 | old_bits |= (1 << intel_dig_port->base.hpd_pin); | |
848 | } | |
849 | } | |
850 | } | |
851 | ||
852 | if (old_bits) { | |
4cb21832 | 853 | spin_lock_irq(&dev_priv->irq_lock); |
13cf5504 | 854 | dev_priv->hpd_event_bits |= old_bits; |
4cb21832 | 855 | spin_unlock_irq(&dev_priv->irq_lock); |
13cf5504 DA |
856 | schedule_work(&dev_priv->hotplug_work); |
857 | } | |
858 | } | |
859 | ||
5ca58282 JB |
860 | /* |
861 | * Handle hotplug events outside the interrupt handler proper. | |
862 | */ | |
ac4c16c5 EE |
863 | #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000) |
864 | ||
5ca58282 JB |
865 | static void i915_hotplug_work_func(struct work_struct *work) |
866 | { | |
2d1013dd JN |
867 | struct drm_i915_private *dev_priv = |
868 | container_of(work, struct drm_i915_private, hotplug_work); | |
5ca58282 | 869 | struct drm_device *dev = dev_priv->dev; |
c31c4ba3 | 870 | struct drm_mode_config *mode_config = &dev->mode_config; |
cd569aed EE |
871 | struct intel_connector *intel_connector; |
872 | struct intel_encoder *intel_encoder; | |
873 | struct drm_connector *connector; | |
cd569aed | 874 | bool hpd_disabled = false; |
321a1b30 | 875 | bool changed = false; |
142e2398 | 876 | u32 hpd_event_bits; |
4ef69c7a | 877 | |
a65e34c7 | 878 | mutex_lock(&mode_config->mutex); |
e67189ab JB |
879 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); |
880 | ||
4cb21832 | 881 | spin_lock_irq(&dev_priv->irq_lock); |
142e2398 EE |
882 | |
883 | hpd_event_bits = dev_priv->hpd_event_bits; | |
884 | dev_priv->hpd_event_bits = 0; | |
cd569aed EE |
885 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
886 | intel_connector = to_intel_connector(connector); | |
36cd7444 DA |
887 | if (!intel_connector->encoder) |
888 | continue; | |
cd569aed EE |
889 | intel_encoder = intel_connector->encoder; |
890 | if (intel_encoder->hpd_pin > HPD_NONE && | |
891 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED && | |
892 | connector->polled == DRM_CONNECTOR_POLL_HPD) { | |
893 | DRM_INFO("HPD interrupt storm detected on connector %s: " | |
894 | "switching from hotplug detection to polling\n", | |
c23cc417 | 895 | connector->name); |
cd569aed EE |
896 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED; |
897 | connector->polled = DRM_CONNECTOR_POLL_CONNECT | |
898 | | DRM_CONNECTOR_POLL_DISCONNECT; | |
899 | hpd_disabled = true; | |
900 | } | |
142e2398 EE |
901 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { |
902 | DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n", | |
c23cc417 | 903 | connector->name, intel_encoder->hpd_pin); |
142e2398 | 904 | } |
cd569aed EE |
905 | } |
906 | /* if there were no outputs to poll, poll was disabled, | |
907 | * therefore make sure it's enabled when disabling HPD on | |
908 | * some connectors */ | |
ac4c16c5 | 909 | if (hpd_disabled) { |
cd569aed | 910 | drm_kms_helper_poll_enable(dev); |
6323751d ID |
911 | mod_delayed_work(system_wq, &dev_priv->hotplug_reenable_work, |
912 | msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY)); | |
ac4c16c5 | 913 | } |
cd569aed | 914 | |
4cb21832 | 915 | spin_unlock_irq(&dev_priv->irq_lock); |
cd569aed | 916 | |
321a1b30 EE |
917 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
918 | intel_connector = to_intel_connector(connector); | |
36cd7444 DA |
919 | if (!intel_connector->encoder) |
920 | continue; | |
321a1b30 EE |
921 | intel_encoder = intel_connector->encoder; |
922 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { | |
923 | if (intel_encoder->hot_plug) | |
924 | intel_encoder->hot_plug(intel_encoder); | |
925 | if (intel_hpd_irq_event(dev, connector)) | |
926 | changed = true; | |
927 | } | |
928 | } | |
40ee3381 KP |
929 | mutex_unlock(&mode_config->mutex); |
930 | ||
321a1b30 EE |
931 | if (changed) |
932 | drm_kms_helper_hotplug_event(dev); | |
5ca58282 JB |
933 | } |
934 | ||
d0ecd7e2 | 935 | static void ironlake_rps_change_irq_handler(struct drm_device *dev) |
f97108d1 | 936 | { |
2d1013dd | 937 | struct drm_i915_private *dev_priv = dev->dev_private; |
b5b72e89 | 938 | u32 busy_up, busy_down, max_avg, min_avg; |
9270388e | 939 | u8 new_delay; |
9270388e | 940 | |
d0ecd7e2 | 941 | spin_lock(&mchdev_lock); |
f97108d1 | 942 | |
73edd18f DV |
943 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
944 | ||
20e4d407 | 945 | new_delay = dev_priv->ips.cur_delay; |
9270388e | 946 | |
7648fa99 | 947 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
948 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
949 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
950 | max_avg = I915_READ(RCBMAXAVG); |
951 | min_avg = I915_READ(RCBMINAVG); | |
952 | ||
953 | /* Handle RCS change request from hw */ | |
b5b72e89 | 954 | if (busy_up > max_avg) { |
20e4d407 DV |
955 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
956 | new_delay = dev_priv->ips.cur_delay - 1; | |
957 | if (new_delay < dev_priv->ips.max_delay) | |
958 | new_delay = dev_priv->ips.max_delay; | |
b5b72e89 | 959 | } else if (busy_down < min_avg) { |
20e4d407 DV |
960 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
961 | new_delay = dev_priv->ips.cur_delay + 1; | |
962 | if (new_delay > dev_priv->ips.min_delay) | |
963 | new_delay = dev_priv->ips.min_delay; | |
f97108d1 JB |
964 | } |
965 | ||
7648fa99 | 966 | if (ironlake_set_drps(dev, new_delay)) |
20e4d407 | 967 | dev_priv->ips.cur_delay = new_delay; |
f97108d1 | 968 | |
d0ecd7e2 | 969 | spin_unlock(&mchdev_lock); |
9270388e | 970 | |
f97108d1 JB |
971 | return; |
972 | } | |
973 | ||
549f7365 | 974 | static void notify_ring(struct drm_device *dev, |
a4872ba6 | 975 | struct intel_engine_cs *ring) |
549f7365 | 976 | { |
93b0a4e0 | 977 | if (!intel_ring_initialized(ring)) |
475553de CW |
978 | return; |
979 | ||
814e9b57 | 980 | trace_i915_gem_request_complete(ring); |
9862e600 | 981 | |
84c33a64 SG |
982 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
983 | intel_notify_mmio_flip(ring); | |
984 | ||
549f7365 | 985 | wake_up_all(&ring->irq_queue); |
10cd45b6 | 986 | i915_queue_hangcheck(dev); |
549f7365 CW |
987 | } |
988 | ||
31685c25 | 989 | static u32 vlv_c0_residency(struct drm_i915_private *dev_priv, |
bf225f20 | 990 | struct intel_rps_ei *rps_ei) |
31685c25 D |
991 | { |
992 | u32 cz_ts, cz_freq_khz; | |
993 | u32 render_count, media_count; | |
994 | u32 elapsed_render, elapsed_media, elapsed_time; | |
995 | u32 residency = 0; | |
996 | ||
997 | cz_ts = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP); | |
998 | cz_freq_khz = DIV_ROUND_CLOSEST(dev_priv->mem_freq * 1000, 4); | |
999 | ||
1000 | render_count = I915_READ(VLV_RENDER_C0_COUNT_REG); | |
1001 | media_count = I915_READ(VLV_MEDIA_C0_COUNT_REG); | |
1002 | ||
bf225f20 CW |
1003 | if (rps_ei->cz_clock == 0) { |
1004 | rps_ei->cz_clock = cz_ts; | |
1005 | rps_ei->render_c0 = render_count; | |
1006 | rps_ei->media_c0 = media_count; | |
31685c25 D |
1007 | |
1008 | return dev_priv->rps.cur_freq; | |
1009 | } | |
1010 | ||
bf225f20 CW |
1011 | elapsed_time = cz_ts - rps_ei->cz_clock; |
1012 | rps_ei->cz_clock = cz_ts; | |
31685c25 | 1013 | |
bf225f20 CW |
1014 | elapsed_render = render_count - rps_ei->render_c0; |
1015 | rps_ei->render_c0 = render_count; | |
31685c25 | 1016 | |
bf225f20 CW |
1017 | elapsed_media = media_count - rps_ei->media_c0; |
1018 | rps_ei->media_c0 = media_count; | |
31685c25 D |
1019 | |
1020 | /* Convert all the counters into common unit of milli sec */ | |
1021 | elapsed_time /= VLV_CZ_CLOCK_TO_MILLI_SEC; | |
1022 | elapsed_render /= cz_freq_khz; | |
1023 | elapsed_media /= cz_freq_khz; | |
1024 | ||
1025 | /* | |
1026 | * Calculate overall C0 residency percentage | |
1027 | * only if elapsed time is non zero | |
1028 | */ | |
1029 | if (elapsed_time) { | |
1030 | residency = | |
1031 | ((max(elapsed_render, elapsed_media) * 100) | |
1032 | / elapsed_time); | |
1033 | } | |
1034 | ||
1035 | return residency; | |
1036 | } | |
1037 | ||
1038 | /** | |
1039 | * vlv_calc_delay_from_C0_counters - Increase/Decrease freq based on GPU | |
1040 | * busy-ness calculated from C0 counters of render & media power wells | |
1041 | * @dev_priv: DRM device private | |
1042 | * | |
1043 | */ | |
4fa79042 | 1044 | static int vlv_calc_delay_from_C0_counters(struct drm_i915_private *dev_priv) |
31685c25 D |
1045 | { |
1046 | u32 residency_C0_up = 0, residency_C0_down = 0; | |
4fa79042 | 1047 | int new_delay, adj; |
31685c25 D |
1048 | |
1049 | dev_priv->rps.ei_interrupt_count++; | |
1050 | ||
1051 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
1052 | ||
1053 | ||
bf225f20 CW |
1054 | if (dev_priv->rps.up_ei.cz_clock == 0) { |
1055 | vlv_c0_residency(dev_priv, &dev_priv->rps.up_ei); | |
1056 | vlv_c0_residency(dev_priv, &dev_priv->rps.down_ei); | |
31685c25 D |
1057 | return dev_priv->rps.cur_freq; |
1058 | } | |
1059 | ||
1060 | ||
1061 | /* | |
1062 | * To down throttle, C0 residency should be less than down threshold | |
1063 | * for continous EI intervals. So calculate down EI counters | |
1064 | * once in VLV_INT_COUNT_FOR_DOWN_EI | |
1065 | */ | |
1066 | if (dev_priv->rps.ei_interrupt_count == VLV_INT_COUNT_FOR_DOWN_EI) { | |
1067 | ||
1068 | dev_priv->rps.ei_interrupt_count = 0; | |
1069 | ||
1070 | residency_C0_down = vlv_c0_residency(dev_priv, | |
bf225f20 | 1071 | &dev_priv->rps.down_ei); |
31685c25 D |
1072 | } else { |
1073 | residency_C0_up = vlv_c0_residency(dev_priv, | |
bf225f20 | 1074 | &dev_priv->rps.up_ei); |
31685c25 D |
1075 | } |
1076 | ||
1077 | new_delay = dev_priv->rps.cur_freq; | |
1078 | ||
1079 | adj = dev_priv->rps.last_adj; | |
1080 | /* C0 residency is greater than UP threshold. Increase Frequency */ | |
1081 | if (residency_C0_up >= VLV_RP_UP_EI_THRESHOLD) { | |
1082 | if (adj > 0) | |
1083 | adj *= 2; | |
1084 | else | |
1085 | adj = 1; | |
1086 | ||
1087 | if (dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit) | |
1088 | new_delay = dev_priv->rps.cur_freq + adj; | |
1089 | ||
1090 | /* | |
1091 | * For better performance, jump directly | |
1092 | * to RPe if we're below it. | |
1093 | */ | |
1094 | if (new_delay < dev_priv->rps.efficient_freq) | |
1095 | new_delay = dev_priv->rps.efficient_freq; | |
1096 | ||
1097 | } else if (!dev_priv->rps.ei_interrupt_count && | |
1098 | (residency_C0_down < VLV_RP_DOWN_EI_THRESHOLD)) { | |
1099 | if (adj < 0) | |
1100 | adj *= 2; | |
1101 | else | |
1102 | adj = -1; | |
1103 | /* | |
1104 | * This means, C0 residency is less than down threshold over | |
1105 | * a period of VLV_INT_COUNT_FOR_DOWN_EI. So, reduce the freq | |
1106 | */ | |
1107 | if (dev_priv->rps.cur_freq > dev_priv->rps.min_freq_softlimit) | |
1108 | new_delay = dev_priv->rps.cur_freq + adj; | |
1109 | } | |
1110 | ||
1111 | return new_delay; | |
1112 | } | |
1113 | ||
4912d041 | 1114 | static void gen6_pm_rps_work(struct work_struct *work) |
3b8d8d91 | 1115 | { |
2d1013dd JN |
1116 | struct drm_i915_private *dev_priv = |
1117 | container_of(work, struct drm_i915_private, rps.work); | |
edbfdb45 | 1118 | u32 pm_iir; |
dd75fdc8 | 1119 | int new_delay, adj; |
4912d041 | 1120 | |
59cdb63d | 1121 | spin_lock_irq(&dev_priv->irq_lock); |
c6a828d3 DV |
1122 | pm_iir = dev_priv->rps.pm_iir; |
1123 | dev_priv->rps.pm_iir = 0; | |
6af257cd | 1124 | if (INTEL_INFO(dev_priv->dev)->gen >= 8) |
480c8033 | 1125 | gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
0961021a BW |
1126 | else { |
1127 | /* Make sure not to corrupt PMIMR state used by ringbuffer */ | |
480c8033 | 1128 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
0961021a | 1129 | } |
59cdb63d | 1130 | spin_unlock_irq(&dev_priv->irq_lock); |
3b8d8d91 | 1131 | |
60611c13 | 1132 | /* Make sure we didn't queue anything we're not going to process. */ |
a6706b45 | 1133 | WARN_ON(pm_iir & ~dev_priv->pm_rps_events); |
60611c13 | 1134 | |
a6706b45 | 1135 | if ((pm_iir & dev_priv->pm_rps_events) == 0) |
3b8d8d91 JB |
1136 | return; |
1137 | ||
4fc688ce | 1138 | mutex_lock(&dev_priv->rps.hw_lock); |
7b9e0ae6 | 1139 | |
dd75fdc8 | 1140 | adj = dev_priv->rps.last_adj; |
7425034a | 1141 | if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { |
dd75fdc8 CW |
1142 | if (adj > 0) |
1143 | adj *= 2; | |
13a5660c D |
1144 | else { |
1145 | /* CHV needs even encode values */ | |
1146 | adj = IS_CHERRYVIEW(dev_priv->dev) ? 2 : 1; | |
1147 | } | |
b39fb297 | 1148 | new_delay = dev_priv->rps.cur_freq + adj; |
7425034a VS |
1149 | |
1150 | /* | |
1151 | * For better performance, jump directly | |
1152 | * to RPe if we're below it. | |
1153 | */ | |
b39fb297 BW |
1154 | if (new_delay < dev_priv->rps.efficient_freq) |
1155 | new_delay = dev_priv->rps.efficient_freq; | |
dd75fdc8 | 1156 | } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { |
b39fb297 BW |
1157 | if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq) |
1158 | new_delay = dev_priv->rps.efficient_freq; | |
dd75fdc8 | 1159 | else |
b39fb297 | 1160 | new_delay = dev_priv->rps.min_freq_softlimit; |
dd75fdc8 | 1161 | adj = 0; |
31685c25 D |
1162 | } else if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) { |
1163 | new_delay = vlv_calc_delay_from_C0_counters(dev_priv); | |
dd75fdc8 CW |
1164 | } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { |
1165 | if (adj < 0) | |
1166 | adj *= 2; | |
13a5660c D |
1167 | else { |
1168 | /* CHV needs even encode values */ | |
1169 | adj = IS_CHERRYVIEW(dev_priv->dev) ? -2 : -1; | |
1170 | } | |
b39fb297 | 1171 | new_delay = dev_priv->rps.cur_freq + adj; |
dd75fdc8 | 1172 | } else { /* unknown event */ |
b39fb297 | 1173 | new_delay = dev_priv->rps.cur_freq; |
dd75fdc8 | 1174 | } |
3b8d8d91 | 1175 | |
79249636 BW |
1176 | /* sysfs frequency interfaces may have snuck in while servicing the |
1177 | * interrupt | |
1178 | */ | |
1272e7b8 | 1179 | new_delay = clamp_t(int, new_delay, |
b39fb297 BW |
1180 | dev_priv->rps.min_freq_softlimit, |
1181 | dev_priv->rps.max_freq_softlimit); | |
27544369 | 1182 | |
b39fb297 | 1183 | dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq; |
dd75fdc8 CW |
1184 | |
1185 | if (IS_VALLEYVIEW(dev_priv->dev)) | |
1186 | valleyview_set_rps(dev_priv->dev, new_delay); | |
1187 | else | |
1188 | gen6_set_rps(dev_priv->dev, new_delay); | |
3b8d8d91 | 1189 | |
4fc688ce | 1190 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 JB |
1191 | } |
1192 | ||
e3689190 BW |
1193 | |
1194 | /** | |
1195 | * ivybridge_parity_work - Workqueue called when a parity error interrupt | |
1196 | * occurred. | |
1197 | * @work: workqueue struct | |
1198 | * | |
1199 | * Doesn't actually do anything except notify userspace. As a consequence of | |
1200 | * this event, userspace should try to remap the bad rows since statistically | |
1201 | * it is likely the same row is more likely to go bad again. | |
1202 | */ | |
1203 | static void ivybridge_parity_work(struct work_struct *work) | |
1204 | { | |
2d1013dd JN |
1205 | struct drm_i915_private *dev_priv = |
1206 | container_of(work, struct drm_i915_private, l3_parity.error_work); | |
e3689190 | 1207 | u32 error_status, row, bank, subbank; |
35a85ac6 | 1208 | char *parity_event[6]; |
e3689190 | 1209 | uint32_t misccpctl; |
35a85ac6 | 1210 | uint8_t slice = 0; |
e3689190 BW |
1211 | |
1212 | /* We must turn off DOP level clock gating to access the L3 registers. | |
1213 | * In order to prevent a get/put style interface, acquire struct mutex | |
1214 | * any time we access those registers. | |
1215 | */ | |
1216 | mutex_lock(&dev_priv->dev->struct_mutex); | |
1217 | ||
35a85ac6 BW |
1218 | /* If we've screwed up tracking, just let the interrupt fire again */ |
1219 | if (WARN_ON(!dev_priv->l3_parity.which_slice)) | |
1220 | goto out; | |
1221 | ||
e3689190 BW |
1222 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
1223 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
1224 | POSTING_READ(GEN7_MISCCPCTL); | |
1225 | ||
35a85ac6 BW |
1226 | while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { |
1227 | u32 reg; | |
e3689190 | 1228 | |
35a85ac6 BW |
1229 | slice--; |
1230 | if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev))) | |
1231 | break; | |
e3689190 | 1232 | |
35a85ac6 | 1233 | dev_priv->l3_parity.which_slice &= ~(1<<slice); |
e3689190 | 1234 | |
35a85ac6 | 1235 | reg = GEN7_L3CDERRST1 + (slice * 0x200); |
e3689190 | 1236 | |
35a85ac6 BW |
1237 | error_status = I915_READ(reg); |
1238 | row = GEN7_PARITY_ERROR_ROW(error_status); | |
1239 | bank = GEN7_PARITY_ERROR_BANK(error_status); | |
1240 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); | |
1241 | ||
1242 | I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); | |
1243 | POSTING_READ(reg); | |
1244 | ||
1245 | parity_event[0] = I915_L3_PARITY_UEVENT "=1"; | |
1246 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); | |
1247 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); | |
1248 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); | |
1249 | parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); | |
1250 | parity_event[5] = NULL; | |
1251 | ||
5bdebb18 | 1252 | kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj, |
35a85ac6 | 1253 | KOBJ_CHANGE, parity_event); |
e3689190 | 1254 | |
35a85ac6 BW |
1255 | DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", |
1256 | slice, row, bank, subbank); | |
e3689190 | 1257 | |
35a85ac6 BW |
1258 | kfree(parity_event[4]); |
1259 | kfree(parity_event[3]); | |
1260 | kfree(parity_event[2]); | |
1261 | kfree(parity_event[1]); | |
1262 | } | |
e3689190 | 1263 | |
35a85ac6 | 1264 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
e3689190 | 1265 | |
35a85ac6 BW |
1266 | out: |
1267 | WARN_ON(dev_priv->l3_parity.which_slice); | |
4cb21832 | 1268 | spin_lock_irq(&dev_priv->irq_lock); |
480c8033 | 1269 | gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev)); |
4cb21832 | 1270 | spin_unlock_irq(&dev_priv->irq_lock); |
35a85ac6 BW |
1271 | |
1272 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
e3689190 BW |
1273 | } |
1274 | ||
35a85ac6 | 1275 | static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir) |
e3689190 | 1276 | { |
2d1013dd | 1277 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3689190 | 1278 | |
040d2baa | 1279 | if (!HAS_L3_DPF(dev)) |
e3689190 BW |
1280 | return; |
1281 | ||
d0ecd7e2 | 1282 | spin_lock(&dev_priv->irq_lock); |
480c8033 | 1283 | gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev)); |
d0ecd7e2 | 1284 | spin_unlock(&dev_priv->irq_lock); |
e3689190 | 1285 | |
35a85ac6 BW |
1286 | iir &= GT_PARITY_ERROR(dev); |
1287 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) | |
1288 | dev_priv->l3_parity.which_slice |= 1 << 1; | |
1289 | ||
1290 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) | |
1291 | dev_priv->l3_parity.which_slice |= 1 << 0; | |
1292 | ||
a4da4fa4 | 1293 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
e3689190 BW |
1294 | } |
1295 | ||
f1af8fc1 PZ |
1296 | static void ilk_gt_irq_handler(struct drm_device *dev, |
1297 | struct drm_i915_private *dev_priv, | |
1298 | u32 gt_iir) | |
1299 | { | |
1300 | if (gt_iir & | |
1301 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
1302 | notify_ring(dev, &dev_priv->ring[RCS]); | |
1303 | if (gt_iir & ILK_BSD_USER_INTERRUPT) | |
1304 | notify_ring(dev, &dev_priv->ring[VCS]); | |
1305 | } | |
1306 | ||
e7b4c6b1 DV |
1307 | static void snb_gt_irq_handler(struct drm_device *dev, |
1308 | struct drm_i915_private *dev_priv, | |
1309 | u32 gt_iir) | |
1310 | { | |
1311 | ||
cc609d5d BW |
1312 | if (gt_iir & |
1313 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
e7b4c6b1 | 1314 | notify_ring(dev, &dev_priv->ring[RCS]); |
cc609d5d | 1315 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
e7b4c6b1 | 1316 | notify_ring(dev, &dev_priv->ring[VCS]); |
cc609d5d | 1317 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
e7b4c6b1 DV |
1318 | notify_ring(dev, &dev_priv->ring[BCS]); |
1319 | ||
cc609d5d BW |
1320 | if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | |
1321 | GT_BSD_CS_ERROR_INTERRUPT | | |
1322 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) { | |
58174462 MK |
1323 | i915_handle_error(dev, false, "GT error interrupt 0x%08x", |
1324 | gt_iir); | |
e7b4c6b1 | 1325 | } |
e3689190 | 1326 | |
35a85ac6 BW |
1327 | if (gt_iir & GT_PARITY_ERROR(dev)) |
1328 | ivybridge_parity_error_irq_handler(dev, gt_iir); | |
e7b4c6b1 DV |
1329 | } |
1330 | ||
0961021a BW |
1331 | static void gen8_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) |
1332 | { | |
1333 | if ((pm_iir & dev_priv->pm_rps_events) == 0) | |
1334 | return; | |
1335 | ||
1336 | spin_lock(&dev_priv->irq_lock); | |
1337 | dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; | |
480c8033 | 1338 | gen8_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); |
0961021a BW |
1339 | spin_unlock(&dev_priv->irq_lock); |
1340 | ||
1341 | queue_work(dev_priv->wq, &dev_priv->rps.work); | |
1342 | } | |
1343 | ||
abd58f01 BW |
1344 | static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev, |
1345 | struct drm_i915_private *dev_priv, | |
1346 | u32 master_ctl) | |
1347 | { | |
e981e7b1 | 1348 | struct intel_engine_cs *ring; |
abd58f01 BW |
1349 | u32 rcs, bcs, vcs; |
1350 | uint32_t tmp = 0; | |
1351 | irqreturn_t ret = IRQ_NONE; | |
1352 | ||
1353 | if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { | |
1354 | tmp = I915_READ(GEN8_GT_IIR(0)); | |
1355 | if (tmp) { | |
38cc46d7 | 1356 | I915_WRITE(GEN8_GT_IIR(0), tmp); |
abd58f01 | 1357 | ret = IRQ_HANDLED; |
e981e7b1 | 1358 | |
abd58f01 | 1359 | rcs = tmp >> GEN8_RCS_IRQ_SHIFT; |
e981e7b1 | 1360 | ring = &dev_priv->ring[RCS]; |
abd58f01 | 1361 | if (rcs & GT_RENDER_USER_INTERRUPT) |
e981e7b1 TD |
1362 | notify_ring(dev, ring); |
1363 | if (rcs & GT_CONTEXT_SWITCH_INTERRUPT) | |
1364 | intel_execlists_handle_ctx_events(ring); | |
1365 | ||
1366 | bcs = tmp >> GEN8_BCS_IRQ_SHIFT; | |
1367 | ring = &dev_priv->ring[BCS]; | |
abd58f01 | 1368 | if (bcs & GT_RENDER_USER_INTERRUPT) |
e981e7b1 TD |
1369 | notify_ring(dev, ring); |
1370 | if (bcs & GT_CONTEXT_SWITCH_INTERRUPT) | |
1371 | intel_execlists_handle_ctx_events(ring); | |
abd58f01 BW |
1372 | } else |
1373 | DRM_ERROR("The master control interrupt lied (GT0)!\n"); | |
1374 | } | |
1375 | ||
85f9b5f9 | 1376 | if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) { |
abd58f01 BW |
1377 | tmp = I915_READ(GEN8_GT_IIR(1)); |
1378 | if (tmp) { | |
38cc46d7 | 1379 | I915_WRITE(GEN8_GT_IIR(1), tmp); |
abd58f01 | 1380 | ret = IRQ_HANDLED; |
e981e7b1 | 1381 | |
abd58f01 | 1382 | vcs = tmp >> GEN8_VCS1_IRQ_SHIFT; |
e981e7b1 | 1383 | ring = &dev_priv->ring[VCS]; |
abd58f01 | 1384 | if (vcs & GT_RENDER_USER_INTERRUPT) |
e981e7b1 | 1385 | notify_ring(dev, ring); |
73d477f6 | 1386 | if (vcs & GT_CONTEXT_SWITCH_INTERRUPT) |
e981e7b1 TD |
1387 | intel_execlists_handle_ctx_events(ring); |
1388 | ||
85f9b5f9 | 1389 | vcs = tmp >> GEN8_VCS2_IRQ_SHIFT; |
e981e7b1 | 1390 | ring = &dev_priv->ring[VCS2]; |
85f9b5f9 | 1391 | if (vcs & GT_RENDER_USER_INTERRUPT) |
e981e7b1 | 1392 | notify_ring(dev, ring); |
73d477f6 | 1393 | if (vcs & GT_CONTEXT_SWITCH_INTERRUPT) |
e981e7b1 | 1394 | intel_execlists_handle_ctx_events(ring); |
abd58f01 BW |
1395 | } else |
1396 | DRM_ERROR("The master control interrupt lied (GT1)!\n"); | |
1397 | } | |
1398 | ||
0961021a BW |
1399 | if (master_ctl & GEN8_GT_PM_IRQ) { |
1400 | tmp = I915_READ(GEN8_GT_IIR(2)); | |
1401 | if (tmp & dev_priv->pm_rps_events) { | |
0961021a BW |
1402 | I915_WRITE(GEN8_GT_IIR(2), |
1403 | tmp & dev_priv->pm_rps_events); | |
38cc46d7 OM |
1404 | ret = IRQ_HANDLED; |
1405 | gen8_rps_irq_handler(dev_priv, tmp); | |
0961021a BW |
1406 | } else |
1407 | DRM_ERROR("The master control interrupt lied (PM)!\n"); | |
1408 | } | |
1409 | ||
abd58f01 BW |
1410 | if (master_ctl & GEN8_GT_VECS_IRQ) { |
1411 | tmp = I915_READ(GEN8_GT_IIR(3)); | |
1412 | if (tmp) { | |
38cc46d7 | 1413 | I915_WRITE(GEN8_GT_IIR(3), tmp); |
abd58f01 | 1414 | ret = IRQ_HANDLED; |
e981e7b1 | 1415 | |
abd58f01 | 1416 | vcs = tmp >> GEN8_VECS_IRQ_SHIFT; |
e981e7b1 | 1417 | ring = &dev_priv->ring[VECS]; |
abd58f01 | 1418 | if (vcs & GT_RENDER_USER_INTERRUPT) |
e981e7b1 | 1419 | notify_ring(dev, ring); |
73d477f6 | 1420 | if (vcs & GT_CONTEXT_SWITCH_INTERRUPT) |
e981e7b1 | 1421 | intel_execlists_handle_ctx_events(ring); |
abd58f01 BW |
1422 | } else |
1423 | DRM_ERROR("The master control interrupt lied (GT3)!\n"); | |
1424 | } | |
1425 | ||
1426 | return ret; | |
1427 | } | |
1428 | ||
b543fb04 EE |
1429 | #define HPD_STORM_DETECT_PERIOD 1000 |
1430 | #define HPD_STORM_THRESHOLD 5 | |
1431 | ||
07c338ce | 1432 | static int pch_port_to_hotplug_shift(enum port port) |
13cf5504 DA |
1433 | { |
1434 | switch (port) { | |
1435 | case PORT_A: | |
1436 | case PORT_E: | |
1437 | default: | |
1438 | return -1; | |
1439 | case PORT_B: | |
1440 | return 0; | |
1441 | case PORT_C: | |
1442 | return 8; | |
1443 | case PORT_D: | |
1444 | return 16; | |
1445 | } | |
1446 | } | |
1447 | ||
07c338ce | 1448 | static int i915_port_to_hotplug_shift(enum port port) |
13cf5504 DA |
1449 | { |
1450 | switch (port) { | |
1451 | case PORT_A: | |
1452 | case PORT_E: | |
1453 | default: | |
1454 | return -1; | |
1455 | case PORT_B: | |
1456 | return 17; | |
1457 | case PORT_C: | |
1458 | return 19; | |
1459 | case PORT_D: | |
1460 | return 21; | |
1461 | } | |
1462 | } | |
1463 | ||
1464 | static inline enum port get_port_from_pin(enum hpd_pin pin) | |
1465 | { | |
1466 | switch (pin) { | |
1467 | case HPD_PORT_B: | |
1468 | return PORT_B; | |
1469 | case HPD_PORT_C: | |
1470 | return PORT_C; | |
1471 | case HPD_PORT_D: | |
1472 | return PORT_D; | |
1473 | default: | |
1474 | return PORT_A; /* no hpd */ | |
1475 | } | |
1476 | } | |
1477 | ||
10a504de | 1478 | static inline void intel_hpd_irq_handler(struct drm_device *dev, |
22062dba | 1479 | u32 hotplug_trigger, |
13cf5504 | 1480 | u32 dig_hotplug_reg, |
22062dba | 1481 | const u32 *hpd) |
b543fb04 | 1482 | { |
2d1013dd | 1483 | struct drm_i915_private *dev_priv = dev->dev_private; |
b543fb04 | 1484 | int i; |
13cf5504 | 1485 | enum port port; |
10a504de | 1486 | bool storm_detected = false; |
13cf5504 DA |
1487 | bool queue_dig = false, queue_hp = false; |
1488 | u32 dig_shift; | |
1489 | u32 dig_port_mask = 0; | |
b543fb04 | 1490 | |
91d131d2 DV |
1491 | if (!hotplug_trigger) |
1492 | return; | |
1493 | ||
13cf5504 DA |
1494 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x\n", |
1495 | hotplug_trigger, dig_hotplug_reg); | |
cc9bd499 | 1496 | |
b5ea2d56 | 1497 | spin_lock(&dev_priv->irq_lock); |
b543fb04 | 1498 | for (i = 1; i < HPD_NUM_PINS; i++) { |
13cf5504 DA |
1499 | if (!(hpd[i] & hotplug_trigger)) |
1500 | continue; | |
1501 | ||
1502 | port = get_port_from_pin(i); | |
1503 | if (port && dev_priv->hpd_irq_port[port]) { | |
1504 | bool long_hpd; | |
1505 | ||
07c338ce JN |
1506 | if (HAS_PCH_SPLIT(dev)) { |
1507 | dig_shift = pch_port_to_hotplug_shift(port); | |
13cf5504 | 1508 | long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT; |
07c338ce JN |
1509 | } else { |
1510 | dig_shift = i915_port_to_hotplug_shift(port); | |
1511 | long_hpd = (hotplug_trigger >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT; | |
13cf5504 DA |
1512 | } |
1513 | ||
26fbb774 VS |
1514 | DRM_DEBUG_DRIVER("digital hpd port %c - %s\n", |
1515 | port_name(port), | |
1516 | long_hpd ? "long" : "short"); | |
13cf5504 DA |
1517 | /* for long HPD pulses we want to have the digital queue happen, |
1518 | but we still want HPD storm detection to function. */ | |
1519 | if (long_hpd) { | |
1520 | dev_priv->long_hpd_port_mask |= (1 << port); | |
1521 | dig_port_mask |= hpd[i]; | |
1522 | } else { | |
1523 | /* for short HPD just trigger the digital queue */ | |
1524 | dev_priv->short_hpd_port_mask |= (1 << port); | |
1525 | hotplug_trigger &= ~hpd[i]; | |
1526 | } | |
1527 | queue_dig = true; | |
1528 | } | |
1529 | } | |
821450c6 | 1530 | |
13cf5504 | 1531 | for (i = 1; i < HPD_NUM_PINS; i++) { |
3ff04a16 DV |
1532 | if (hpd[i] & hotplug_trigger && |
1533 | dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) { | |
1534 | /* | |
1535 | * On GMCH platforms the interrupt mask bits only | |
1536 | * prevent irq generation, not the setting of the | |
1537 | * hotplug bits itself. So only WARN about unexpected | |
1538 | * interrupts on saner platforms. | |
1539 | */ | |
1540 | WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev), | |
1541 | "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n", | |
1542 | hotplug_trigger, i, hpd[i]); | |
1543 | ||
1544 | continue; | |
1545 | } | |
b8f102e8 | 1546 | |
b543fb04 EE |
1547 | if (!(hpd[i] & hotplug_trigger) || |
1548 | dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED) | |
1549 | continue; | |
1550 | ||
13cf5504 DA |
1551 | if (!(dig_port_mask & hpd[i])) { |
1552 | dev_priv->hpd_event_bits |= (1 << i); | |
1553 | queue_hp = true; | |
1554 | } | |
1555 | ||
b543fb04 EE |
1556 | if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies, |
1557 | dev_priv->hpd_stats[i].hpd_last_jiffies | |
1558 | + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) { | |
1559 | dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies; | |
1560 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
b8f102e8 | 1561 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i); |
b543fb04 EE |
1562 | } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) { |
1563 | dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED; | |
142e2398 | 1564 | dev_priv->hpd_event_bits &= ~(1 << i); |
b543fb04 | 1565 | DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i); |
10a504de | 1566 | storm_detected = true; |
b543fb04 EE |
1567 | } else { |
1568 | dev_priv->hpd_stats[i].hpd_cnt++; | |
b8f102e8 EE |
1569 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i, |
1570 | dev_priv->hpd_stats[i].hpd_cnt); | |
b543fb04 EE |
1571 | } |
1572 | } | |
1573 | ||
10a504de DV |
1574 | if (storm_detected) |
1575 | dev_priv->display.hpd_irq_setup(dev); | |
b5ea2d56 | 1576 | spin_unlock(&dev_priv->irq_lock); |
5876fa0d | 1577 | |
645416f5 DV |
1578 | /* |
1579 | * Our hotplug handler can grab modeset locks (by calling down into the | |
1580 | * fb helpers). Hence it must not be run on our own dev-priv->wq work | |
1581 | * queue for otherwise the flush_work in the pageflip code will | |
1582 | * deadlock. | |
1583 | */ | |
13cf5504 | 1584 | if (queue_dig) |
0e32b39c | 1585 | queue_work(dev_priv->dp_wq, &dev_priv->dig_port_work); |
13cf5504 DA |
1586 | if (queue_hp) |
1587 | schedule_work(&dev_priv->hotplug_work); | |
b543fb04 EE |
1588 | } |
1589 | ||
515ac2bb DV |
1590 | static void gmbus_irq_handler(struct drm_device *dev) |
1591 | { | |
2d1013dd | 1592 | struct drm_i915_private *dev_priv = dev->dev_private; |
28c70f16 | 1593 | |
28c70f16 | 1594 | wake_up_all(&dev_priv->gmbus_wait_queue); |
515ac2bb DV |
1595 | } |
1596 | ||
ce99c256 DV |
1597 | static void dp_aux_irq_handler(struct drm_device *dev) |
1598 | { | |
2d1013dd | 1599 | struct drm_i915_private *dev_priv = dev->dev_private; |
9ee32fea | 1600 | |
9ee32fea | 1601 | wake_up_all(&dev_priv->gmbus_wait_queue); |
ce99c256 DV |
1602 | } |
1603 | ||
8bf1e9f1 | 1604 | #if defined(CONFIG_DEBUG_FS) |
277de95e DV |
1605 | static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, |
1606 | uint32_t crc0, uint32_t crc1, | |
1607 | uint32_t crc2, uint32_t crc3, | |
1608 | uint32_t crc4) | |
8bf1e9f1 SH |
1609 | { |
1610 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1611 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; | |
1612 | struct intel_pipe_crc_entry *entry; | |
ac2300d4 | 1613 | int head, tail; |
b2c88f5b | 1614 | |
d538bbdf DL |
1615 | spin_lock(&pipe_crc->lock); |
1616 | ||
0c912c79 | 1617 | if (!pipe_crc->entries) { |
d538bbdf | 1618 | spin_unlock(&pipe_crc->lock); |
0c912c79 DL |
1619 | DRM_ERROR("spurious interrupt\n"); |
1620 | return; | |
1621 | } | |
1622 | ||
d538bbdf DL |
1623 | head = pipe_crc->head; |
1624 | tail = pipe_crc->tail; | |
b2c88f5b DL |
1625 | |
1626 | if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { | |
d538bbdf | 1627 | spin_unlock(&pipe_crc->lock); |
b2c88f5b DL |
1628 | DRM_ERROR("CRC buffer overflowing\n"); |
1629 | return; | |
1630 | } | |
1631 | ||
1632 | entry = &pipe_crc->entries[head]; | |
8bf1e9f1 | 1633 | |
8bc5e955 | 1634 | entry->frame = dev->driver->get_vblank_counter(dev, pipe); |
eba94eb9 DV |
1635 | entry->crc[0] = crc0; |
1636 | entry->crc[1] = crc1; | |
1637 | entry->crc[2] = crc2; | |
1638 | entry->crc[3] = crc3; | |
1639 | entry->crc[4] = crc4; | |
b2c88f5b DL |
1640 | |
1641 | head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
d538bbdf DL |
1642 | pipe_crc->head = head; |
1643 | ||
1644 | spin_unlock(&pipe_crc->lock); | |
07144428 DL |
1645 | |
1646 | wake_up_interruptible(&pipe_crc->wq); | |
8bf1e9f1 | 1647 | } |
277de95e DV |
1648 | #else |
1649 | static inline void | |
1650 | display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, | |
1651 | uint32_t crc0, uint32_t crc1, | |
1652 | uint32_t crc2, uint32_t crc3, | |
1653 | uint32_t crc4) {} | |
1654 | #endif | |
1655 | ||
eba94eb9 | 1656 | |
277de95e | 1657 | static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5a69b89f DV |
1658 | { |
1659 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1660 | ||
277de95e DV |
1661 | display_pipe_crc_irq_handler(dev, pipe, |
1662 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1663 | 0, 0, 0, 0); | |
5a69b89f DV |
1664 | } |
1665 | ||
277de95e | 1666 | static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
eba94eb9 DV |
1667 | { |
1668 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1669 | ||
277de95e DV |
1670 | display_pipe_crc_irq_handler(dev, pipe, |
1671 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1672 | I915_READ(PIPE_CRC_RES_2_IVB(pipe)), | |
1673 | I915_READ(PIPE_CRC_RES_3_IVB(pipe)), | |
1674 | I915_READ(PIPE_CRC_RES_4_IVB(pipe)), | |
1675 | I915_READ(PIPE_CRC_RES_5_IVB(pipe))); | |
eba94eb9 | 1676 | } |
5b3a856b | 1677 | |
277de95e | 1678 | static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5b3a856b DV |
1679 | { |
1680 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0b5c5ed0 DV |
1681 | uint32_t res1, res2; |
1682 | ||
1683 | if (INTEL_INFO(dev)->gen >= 3) | |
1684 | res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); | |
1685 | else | |
1686 | res1 = 0; | |
1687 | ||
1688 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
1689 | res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); | |
1690 | else | |
1691 | res2 = 0; | |
5b3a856b | 1692 | |
277de95e DV |
1693 | display_pipe_crc_irq_handler(dev, pipe, |
1694 | I915_READ(PIPE_CRC_RES_RED(pipe)), | |
1695 | I915_READ(PIPE_CRC_RES_GREEN(pipe)), | |
1696 | I915_READ(PIPE_CRC_RES_BLUE(pipe)), | |
1697 | res1, res2); | |
5b3a856b | 1698 | } |
8bf1e9f1 | 1699 | |
1403c0d4 PZ |
1700 | /* The RPS events need forcewake, so we add them to a work queue and mask their |
1701 | * IMR bits until the work is done. Other interrupts can be processed without | |
1702 | * the work queue. */ | |
1703 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) | |
baf02a1f | 1704 | { |
a6706b45 | 1705 | if (pm_iir & dev_priv->pm_rps_events) { |
59cdb63d | 1706 | spin_lock(&dev_priv->irq_lock); |
a6706b45 | 1707 | dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; |
480c8033 | 1708 | gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); |
59cdb63d | 1709 | spin_unlock(&dev_priv->irq_lock); |
2adbee62 DV |
1710 | |
1711 | queue_work(dev_priv->wq, &dev_priv->rps.work); | |
baf02a1f | 1712 | } |
baf02a1f | 1713 | |
1403c0d4 PZ |
1714 | if (HAS_VEBOX(dev_priv->dev)) { |
1715 | if (pm_iir & PM_VEBOX_USER_INTERRUPT) | |
1716 | notify_ring(dev_priv->dev, &dev_priv->ring[VECS]); | |
12638c57 | 1717 | |
1403c0d4 | 1718 | if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) { |
58174462 MK |
1719 | i915_handle_error(dev_priv->dev, false, |
1720 | "VEBOX CS error interrupt 0x%08x", | |
1721 | pm_iir); | |
1403c0d4 | 1722 | } |
12638c57 | 1723 | } |
baf02a1f BW |
1724 | } |
1725 | ||
8d7849db VS |
1726 | static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe) |
1727 | { | |
8d7849db VS |
1728 | if (!drm_handle_vblank(dev, pipe)) |
1729 | return false; | |
1730 | ||
8d7849db VS |
1731 | return true; |
1732 | } | |
1733 | ||
c1874ed7 ID |
1734 | static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir) |
1735 | { | |
1736 | struct drm_i915_private *dev_priv = dev->dev_private; | |
91d181dd | 1737 | u32 pipe_stats[I915_MAX_PIPES] = { }; |
c1874ed7 ID |
1738 | int pipe; |
1739 | ||
58ead0d7 | 1740 | spin_lock(&dev_priv->irq_lock); |
055e393f | 1741 | for_each_pipe(dev_priv, pipe) { |
91d181dd | 1742 | int reg; |
bbb5eebf | 1743 | u32 mask, iir_bit = 0; |
91d181dd | 1744 | |
bbb5eebf DV |
1745 | /* |
1746 | * PIPESTAT bits get signalled even when the interrupt is | |
1747 | * disabled with the mask bits, and some of the status bits do | |
1748 | * not generate interrupts at all (like the underrun bit). Hence | |
1749 | * we need to be careful that we only handle what we want to | |
1750 | * handle. | |
1751 | */ | |
0f239f4c DV |
1752 | |
1753 | /* fifo underruns are filterered in the underrun handler. */ | |
1754 | mask = PIPE_FIFO_UNDERRUN_STATUS; | |
bbb5eebf DV |
1755 | |
1756 | switch (pipe) { | |
1757 | case PIPE_A: | |
1758 | iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; | |
1759 | break; | |
1760 | case PIPE_B: | |
1761 | iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
1762 | break; | |
3278f67f VS |
1763 | case PIPE_C: |
1764 | iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
1765 | break; | |
bbb5eebf DV |
1766 | } |
1767 | if (iir & iir_bit) | |
1768 | mask |= dev_priv->pipestat_irq_mask[pipe]; | |
1769 | ||
1770 | if (!mask) | |
91d181dd ID |
1771 | continue; |
1772 | ||
1773 | reg = PIPESTAT(pipe); | |
bbb5eebf DV |
1774 | mask |= PIPESTAT_INT_ENABLE_MASK; |
1775 | pipe_stats[pipe] = I915_READ(reg) & mask; | |
c1874ed7 ID |
1776 | |
1777 | /* | |
1778 | * Clear the PIPE*STAT regs before the IIR | |
1779 | */ | |
91d181dd ID |
1780 | if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS | |
1781 | PIPESTAT_INT_STATUS_MASK)) | |
c1874ed7 ID |
1782 | I915_WRITE(reg, pipe_stats[pipe]); |
1783 | } | |
58ead0d7 | 1784 | spin_unlock(&dev_priv->irq_lock); |
c1874ed7 | 1785 | |
055e393f | 1786 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
1787 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
1788 | intel_pipe_handle_vblank(dev, pipe)) | |
1789 | intel_check_page_flip(dev, pipe); | |
c1874ed7 | 1790 | |
579a9b0e | 1791 | if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) { |
c1874ed7 ID |
1792 | intel_prepare_page_flip(dev, pipe); |
1793 | intel_finish_page_flip(dev, pipe); | |
1794 | } | |
1795 | ||
1796 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
1797 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
1798 | ||
1f7247c0 DV |
1799 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
1800 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
c1874ed7 ID |
1801 | } |
1802 | ||
1803 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) | |
1804 | gmbus_irq_handler(dev); | |
1805 | } | |
1806 | ||
16c6c56b VS |
1807 | static void i9xx_hpd_irq_handler(struct drm_device *dev) |
1808 | { | |
1809 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1810 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
1811 | ||
3ff60f89 OM |
1812 | if (hotplug_status) { |
1813 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
1814 | /* | |
1815 | * Make sure hotplug status is cleared before we clear IIR, or else we | |
1816 | * may miss hotplug events. | |
1817 | */ | |
1818 | POSTING_READ(PORT_HOTPLUG_STAT); | |
16c6c56b | 1819 | |
3ff60f89 OM |
1820 | if (IS_G4X(dev)) { |
1821 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; | |
16c6c56b | 1822 | |
13cf5504 | 1823 | intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_g4x); |
3ff60f89 OM |
1824 | } else { |
1825 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; | |
16c6c56b | 1826 | |
13cf5504 | 1827 | intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_i915); |
3ff60f89 | 1828 | } |
16c6c56b | 1829 | |
3ff60f89 OM |
1830 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && |
1831 | hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) | |
1832 | dp_aux_irq_handler(dev); | |
1833 | } | |
16c6c56b VS |
1834 | } |
1835 | ||
ff1f525e | 1836 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
7e231dbe | 1837 | { |
45a83f84 | 1838 | struct drm_device *dev = arg; |
2d1013dd | 1839 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
1840 | u32 iir, gt_iir, pm_iir; |
1841 | irqreturn_t ret = IRQ_NONE; | |
7e231dbe | 1842 | |
7e231dbe | 1843 | while (true) { |
3ff60f89 OM |
1844 | /* Find, clear, then process each source of interrupt */ |
1845 | ||
7e231dbe | 1846 | gt_iir = I915_READ(GTIIR); |
3ff60f89 OM |
1847 | if (gt_iir) |
1848 | I915_WRITE(GTIIR, gt_iir); | |
1849 | ||
7e231dbe | 1850 | pm_iir = I915_READ(GEN6_PMIIR); |
3ff60f89 OM |
1851 | if (pm_iir) |
1852 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
1853 | ||
1854 | iir = I915_READ(VLV_IIR); | |
1855 | if (iir) { | |
1856 | /* Consume port before clearing IIR or we'll miss events */ | |
1857 | if (iir & I915_DISPLAY_PORT_INTERRUPT) | |
1858 | i9xx_hpd_irq_handler(dev); | |
1859 | I915_WRITE(VLV_IIR, iir); | |
1860 | } | |
7e231dbe JB |
1861 | |
1862 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) | |
1863 | goto out; | |
1864 | ||
1865 | ret = IRQ_HANDLED; | |
1866 | ||
3ff60f89 OM |
1867 | if (gt_iir) |
1868 | snb_gt_irq_handler(dev, dev_priv, gt_iir); | |
60611c13 | 1869 | if (pm_iir) |
d0ecd7e2 | 1870 | gen6_rps_irq_handler(dev_priv, pm_iir); |
3ff60f89 OM |
1871 | /* Call regardless, as some status bits might not be |
1872 | * signalled in iir */ | |
1873 | valleyview_pipestat_irq_handler(dev, iir); | |
7e231dbe JB |
1874 | } |
1875 | ||
1876 | out: | |
1877 | return ret; | |
1878 | } | |
1879 | ||
43f328d7 VS |
1880 | static irqreturn_t cherryview_irq_handler(int irq, void *arg) |
1881 | { | |
45a83f84 | 1882 | struct drm_device *dev = arg; |
43f328d7 VS |
1883 | struct drm_i915_private *dev_priv = dev->dev_private; |
1884 | u32 master_ctl, iir; | |
1885 | irqreturn_t ret = IRQ_NONE; | |
43f328d7 | 1886 | |
8e5fd599 VS |
1887 | for (;;) { |
1888 | master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; | |
1889 | iir = I915_READ(VLV_IIR); | |
43f328d7 | 1890 | |
8e5fd599 VS |
1891 | if (master_ctl == 0 && iir == 0) |
1892 | break; | |
43f328d7 | 1893 | |
27b6c122 OM |
1894 | ret = IRQ_HANDLED; |
1895 | ||
8e5fd599 | 1896 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
43f328d7 | 1897 | |
27b6c122 | 1898 | /* Find, clear, then process each source of interrupt */ |
43f328d7 | 1899 | |
27b6c122 OM |
1900 | if (iir) { |
1901 | /* Consume port before clearing IIR or we'll miss events */ | |
1902 | if (iir & I915_DISPLAY_PORT_INTERRUPT) | |
1903 | i9xx_hpd_irq_handler(dev); | |
1904 | I915_WRITE(VLV_IIR, iir); | |
1905 | } | |
43f328d7 | 1906 | |
27b6c122 | 1907 | gen8_gt_irq_handler(dev, dev_priv, master_ctl); |
43f328d7 | 1908 | |
27b6c122 OM |
1909 | /* Call regardless, as some status bits might not be |
1910 | * signalled in iir */ | |
1911 | valleyview_pipestat_irq_handler(dev, iir); | |
43f328d7 | 1912 | |
8e5fd599 VS |
1913 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); |
1914 | POSTING_READ(GEN8_MASTER_IRQ); | |
8e5fd599 | 1915 | } |
3278f67f | 1916 | |
43f328d7 VS |
1917 | return ret; |
1918 | } | |
1919 | ||
23e81d69 | 1920 | static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) |
776ad806 | 1921 | { |
2d1013dd | 1922 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 1923 | int pipe; |
b543fb04 | 1924 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; |
13cf5504 DA |
1925 | u32 dig_hotplug_reg; |
1926 | ||
1927 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); | |
1928 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
776ad806 | 1929 | |
13cf5504 | 1930 | intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_ibx); |
91d131d2 | 1931 | |
cfc33bf7 VS |
1932 | if (pch_iir & SDE_AUDIO_POWER_MASK) { |
1933 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> | |
1934 | SDE_AUDIO_POWER_SHIFT); | |
776ad806 | 1935 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
cfc33bf7 VS |
1936 | port_name(port)); |
1937 | } | |
776ad806 | 1938 | |
ce99c256 DV |
1939 | if (pch_iir & SDE_AUX_MASK) |
1940 | dp_aux_irq_handler(dev); | |
1941 | ||
776ad806 | 1942 | if (pch_iir & SDE_GMBUS) |
515ac2bb | 1943 | gmbus_irq_handler(dev); |
776ad806 JB |
1944 | |
1945 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
1946 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
1947 | ||
1948 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
1949 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
1950 | ||
1951 | if (pch_iir & SDE_POISON) | |
1952 | DRM_ERROR("PCH poison interrupt\n"); | |
1953 | ||
9db4a9c7 | 1954 | if (pch_iir & SDE_FDI_MASK) |
055e393f | 1955 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
1956 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
1957 | pipe_name(pipe), | |
1958 | I915_READ(FDI_RX_IIR(pipe))); | |
776ad806 JB |
1959 | |
1960 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
1961 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
1962 | ||
1963 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
1964 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
1965 | ||
776ad806 | 1966 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
1f7247c0 | 1967 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); |
8664281b PZ |
1968 | |
1969 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
1f7247c0 | 1970 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); |
8664281b PZ |
1971 | } |
1972 | ||
1973 | static void ivb_err_int_handler(struct drm_device *dev) | |
1974 | { | |
1975 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1976 | u32 err_int = I915_READ(GEN7_ERR_INT); | |
5a69b89f | 1977 | enum pipe pipe; |
8664281b | 1978 | |
de032bf4 PZ |
1979 | if (err_int & ERR_INT_POISON) |
1980 | DRM_ERROR("Poison interrupt\n"); | |
1981 | ||
055e393f | 1982 | for_each_pipe(dev_priv, pipe) { |
1f7247c0 DV |
1983 | if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) |
1984 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
8bf1e9f1 | 1985 | |
5a69b89f DV |
1986 | if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { |
1987 | if (IS_IVYBRIDGE(dev)) | |
277de95e | 1988 | ivb_pipe_crc_irq_handler(dev, pipe); |
5a69b89f | 1989 | else |
277de95e | 1990 | hsw_pipe_crc_irq_handler(dev, pipe); |
5a69b89f DV |
1991 | } |
1992 | } | |
8bf1e9f1 | 1993 | |
8664281b PZ |
1994 | I915_WRITE(GEN7_ERR_INT, err_int); |
1995 | } | |
1996 | ||
1997 | static void cpt_serr_int_handler(struct drm_device *dev) | |
1998 | { | |
1999 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2000 | u32 serr_int = I915_READ(SERR_INT); | |
2001 | ||
de032bf4 PZ |
2002 | if (serr_int & SERR_INT_POISON) |
2003 | DRM_ERROR("PCH poison interrupt\n"); | |
2004 | ||
8664281b | 2005 | if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) |
1f7247c0 | 2006 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); |
8664281b PZ |
2007 | |
2008 | if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) | |
1f7247c0 | 2009 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); |
8664281b PZ |
2010 | |
2011 | if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) | |
1f7247c0 | 2012 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C); |
8664281b PZ |
2013 | |
2014 | I915_WRITE(SERR_INT, serr_int); | |
776ad806 JB |
2015 | } |
2016 | ||
23e81d69 AJ |
2017 | static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) |
2018 | { | |
2d1013dd | 2019 | struct drm_i915_private *dev_priv = dev->dev_private; |
23e81d69 | 2020 | int pipe; |
b543fb04 | 2021 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; |
13cf5504 DA |
2022 | u32 dig_hotplug_reg; |
2023 | ||
2024 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); | |
2025 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
23e81d69 | 2026 | |
13cf5504 | 2027 | intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_cpt); |
91d131d2 | 2028 | |
cfc33bf7 VS |
2029 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { |
2030 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> | |
2031 | SDE_AUDIO_POWER_SHIFT_CPT); | |
2032 | DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", | |
2033 | port_name(port)); | |
2034 | } | |
23e81d69 AJ |
2035 | |
2036 | if (pch_iir & SDE_AUX_MASK_CPT) | |
ce99c256 | 2037 | dp_aux_irq_handler(dev); |
23e81d69 AJ |
2038 | |
2039 | if (pch_iir & SDE_GMBUS_CPT) | |
515ac2bb | 2040 | gmbus_irq_handler(dev); |
23e81d69 AJ |
2041 | |
2042 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) | |
2043 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); | |
2044 | ||
2045 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) | |
2046 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); | |
2047 | ||
2048 | if (pch_iir & SDE_FDI_MASK_CPT) | |
055e393f | 2049 | for_each_pipe(dev_priv, pipe) |
23e81d69 AJ |
2050 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
2051 | pipe_name(pipe), | |
2052 | I915_READ(FDI_RX_IIR(pipe))); | |
8664281b PZ |
2053 | |
2054 | if (pch_iir & SDE_ERROR_CPT) | |
2055 | cpt_serr_int_handler(dev); | |
23e81d69 AJ |
2056 | } |
2057 | ||
c008bc6e PZ |
2058 | static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) |
2059 | { | |
2060 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40da17c2 | 2061 | enum pipe pipe; |
c008bc6e PZ |
2062 | |
2063 | if (de_iir & DE_AUX_CHANNEL_A) | |
2064 | dp_aux_irq_handler(dev); | |
2065 | ||
2066 | if (de_iir & DE_GSE) | |
2067 | intel_opregion_asle_intr(dev); | |
2068 | ||
c008bc6e PZ |
2069 | if (de_iir & DE_POISON) |
2070 | DRM_ERROR("Poison interrupt\n"); | |
2071 | ||
055e393f | 2072 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
2073 | if (de_iir & DE_PIPE_VBLANK(pipe) && |
2074 | intel_pipe_handle_vblank(dev, pipe)) | |
2075 | intel_check_page_flip(dev, pipe); | |
5b3a856b | 2076 | |
40da17c2 | 2077 | if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) |
1f7247c0 | 2078 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); |
5b3a856b | 2079 | |
40da17c2 DV |
2080 | if (de_iir & DE_PIPE_CRC_DONE(pipe)) |
2081 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
c008bc6e | 2082 | |
40da17c2 DV |
2083 | /* plane/pipes map 1:1 on ilk+ */ |
2084 | if (de_iir & DE_PLANE_FLIP_DONE(pipe)) { | |
2085 | intel_prepare_page_flip(dev, pipe); | |
2086 | intel_finish_page_flip_plane(dev, pipe); | |
2087 | } | |
c008bc6e PZ |
2088 | } |
2089 | ||
2090 | /* check event from PCH */ | |
2091 | if (de_iir & DE_PCH_EVENT) { | |
2092 | u32 pch_iir = I915_READ(SDEIIR); | |
2093 | ||
2094 | if (HAS_PCH_CPT(dev)) | |
2095 | cpt_irq_handler(dev, pch_iir); | |
2096 | else | |
2097 | ibx_irq_handler(dev, pch_iir); | |
2098 | ||
2099 | /* should clear PCH hotplug event before clear CPU irq */ | |
2100 | I915_WRITE(SDEIIR, pch_iir); | |
2101 | } | |
2102 | ||
2103 | if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) | |
2104 | ironlake_rps_change_irq_handler(dev); | |
2105 | } | |
2106 | ||
9719fb98 PZ |
2107 | static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir) |
2108 | { | |
2109 | struct drm_i915_private *dev_priv = dev->dev_private; | |
07d27e20 | 2110 | enum pipe pipe; |
9719fb98 PZ |
2111 | |
2112 | if (de_iir & DE_ERR_INT_IVB) | |
2113 | ivb_err_int_handler(dev); | |
2114 | ||
2115 | if (de_iir & DE_AUX_CHANNEL_A_IVB) | |
2116 | dp_aux_irq_handler(dev); | |
2117 | ||
2118 | if (de_iir & DE_GSE_IVB) | |
2119 | intel_opregion_asle_intr(dev); | |
2120 | ||
055e393f | 2121 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
2122 | if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) && |
2123 | intel_pipe_handle_vblank(dev, pipe)) | |
2124 | intel_check_page_flip(dev, pipe); | |
40da17c2 DV |
2125 | |
2126 | /* plane/pipes map 1:1 on ilk+ */ | |
07d27e20 DL |
2127 | if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) { |
2128 | intel_prepare_page_flip(dev, pipe); | |
2129 | intel_finish_page_flip_plane(dev, pipe); | |
9719fb98 PZ |
2130 | } |
2131 | } | |
2132 | ||
2133 | /* check event from PCH */ | |
2134 | if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) { | |
2135 | u32 pch_iir = I915_READ(SDEIIR); | |
2136 | ||
2137 | cpt_irq_handler(dev, pch_iir); | |
2138 | ||
2139 | /* clear PCH hotplug event before clear CPU irq */ | |
2140 | I915_WRITE(SDEIIR, pch_iir); | |
2141 | } | |
2142 | } | |
2143 | ||
72c90f62 OM |
2144 | /* |
2145 | * To handle irqs with the minimum potential races with fresh interrupts, we: | |
2146 | * 1 - Disable Master Interrupt Control. | |
2147 | * 2 - Find the source(s) of the interrupt. | |
2148 | * 3 - Clear the Interrupt Identity bits (IIR). | |
2149 | * 4 - Process the interrupt(s) that had bits set in the IIRs. | |
2150 | * 5 - Re-enable Master Interrupt Control. | |
2151 | */ | |
f1af8fc1 | 2152 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
b1f14ad0 | 2153 | { |
45a83f84 | 2154 | struct drm_device *dev = arg; |
2d1013dd | 2155 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1af8fc1 | 2156 | u32 de_iir, gt_iir, de_ier, sde_ier = 0; |
0e43406b | 2157 | irqreturn_t ret = IRQ_NONE; |
b1f14ad0 | 2158 | |
8664281b PZ |
2159 | /* We get interrupts on unclaimed registers, so check for this before we |
2160 | * do any I915_{READ,WRITE}. */ | |
907b28c5 | 2161 | intel_uncore_check_errors(dev); |
8664281b | 2162 | |
b1f14ad0 JB |
2163 | /* disable master interrupt before clearing iir */ |
2164 | de_ier = I915_READ(DEIER); | |
2165 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
23a78516 | 2166 | POSTING_READ(DEIER); |
b1f14ad0 | 2167 | |
44498aea PZ |
2168 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
2169 | * interrupts will will be stored on its back queue, and then we'll be | |
2170 | * able to process them after we restore SDEIER (as soon as we restore | |
2171 | * it, we'll get an interrupt if SDEIIR still has something to process | |
2172 | * due to its back queue). */ | |
ab5c608b BW |
2173 | if (!HAS_PCH_NOP(dev)) { |
2174 | sde_ier = I915_READ(SDEIER); | |
2175 | I915_WRITE(SDEIER, 0); | |
2176 | POSTING_READ(SDEIER); | |
2177 | } | |
44498aea | 2178 | |
72c90f62 OM |
2179 | /* Find, clear, then process each source of interrupt */ |
2180 | ||
b1f14ad0 | 2181 | gt_iir = I915_READ(GTIIR); |
0e43406b | 2182 | if (gt_iir) { |
72c90f62 OM |
2183 | I915_WRITE(GTIIR, gt_iir); |
2184 | ret = IRQ_HANDLED; | |
d8fc8a47 | 2185 | if (INTEL_INFO(dev)->gen >= 6) |
f1af8fc1 | 2186 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
d8fc8a47 PZ |
2187 | else |
2188 | ilk_gt_irq_handler(dev, dev_priv, gt_iir); | |
b1f14ad0 JB |
2189 | } |
2190 | ||
0e43406b CW |
2191 | de_iir = I915_READ(DEIIR); |
2192 | if (de_iir) { | |
72c90f62 OM |
2193 | I915_WRITE(DEIIR, de_iir); |
2194 | ret = IRQ_HANDLED; | |
f1af8fc1 PZ |
2195 | if (INTEL_INFO(dev)->gen >= 7) |
2196 | ivb_display_irq_handler(dev, de_iir); | |
2197 | else | |
2198 | ilk_display_irq_handler(dev, de_iir); | |
b1f14ad0 JB |
2199 | } |
2200 | ||
f1af8fc1 PZ |
2201 | if (INTEL_INFO(dev)->gen >= 6) { |
2202 | u32 pm_iir = I915_READ(GEN6_PMIIR); | |
2203 | if (pm_iir) { | |
f1af8fc1 PZ |
2204 | I915_WRITE(GEN6_PMIIR, pm_iir); |
2205 | ret = IRQ_HANDLED; | |
72c90f62 | 2206 | gen6_rps_irq_handler(dev_priv, pm_iir); |
f1af8fc1 | 2207 | } |
0e43406b | 2208 | } |
b1f14ad0 | 2209 | |
b1f14ad0 JB |
2210 | I915_WRITE(DEIER, de_ier); |
2211 | POSTING_READ(DEIER); | |
ab5c608b BW |
2212 | if (!HAS_PCH_NOP(dev)) { |
2213 | I915_WRITE(SDEIER, sde_ier); | |
2214 | POSTING_READ(SDEIER); | |
2215 | } | |
b1f14ad0 JB |
2216 | |
2217 | return ret; | |
2218 | } | |
2219 | ||
abd58f01 BW |
2220 | static irqreturn_t gen8_irq_handler(int irq, void *arg) |
2221 | { | |
2222 | struct drm_device *dev = arg; | |
2223 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2224 | u32 master_ctl; | |
2225 | irqreturn_t ret = IRQ_NONE; | |
2226 | uint32_t tmp = 0; | |
c42664cc | 2227 | enum pipe pipe; |
abd58f01 | 2228 | |
abd58f01 BW |
2229 | master_ctl = I915_READ(GEN8_MASTER_IRQ); |
2230 | master_ctl &= ~GEN8_MASTER_IRQ_CONTROL; | |
2231 | if (!master_ctl) | |
2232 | return IRQ_NONE; | |
2233 | ||
2234 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
2235 | POSTING_READ(GEN8_MASTER_IRQ); | |
2236 | ||
38cc46d7 OM |
2237 | /* Find, clear, then process each source of interrupt */ |
2238 | ||
abd58f01 BW |
2239 | ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl); |
2240 | ||
2241 | if (master_ctl & GEN8_DE_MISC_IRQ) { | |
2242 | tmp = I915_READ(GEN8_DE_MISC_IIR); | |
abd58f01 BW |
2243 | if (tmp) { |
2244 | I915_WRITE(GEN8_DE_MISC_IIR, tmp); | |
2245 | ret = IRQ_HANDLED; | |
38cc46d7 OM |
2246 | if (tmp & GEN8_DE_MISC_GSE) |
2247 | intel_opregion_asle_intr(dev); | |
2248 | else | |
2249 | DRM_ERROR("Unexpected DE Misc interrupt\n"); | |
abd58f01 | 2250 | } |
38cc46d7 OM |
2251 | else |
2252 | DRM_ERROR("The master control interrupt lied (DE MISC)!\n"); | |
abd58f01 BW |
2253 | } |
2254 | ||
6d766f02 DV |
2255 | if (master_ctl & GEN8_DE_PORT_IRQ) { |
2256 | tmp = I915_READ(GEN8_DE_PORT_IIR); | |
6d766f02 DV |
2257 | if (tmp) { |
2258 | I915_WRITE(GEN8_DE_PORT_IIR, tmp); | |
2259 | ret = IRQ_HANDLED; | |
38cc46d7 OM |
2260 | if (tmp & GEN8_AUX_CHANNEL_A) |
2261 | dp_aux_irq_handler(dev); | |
2262 | else | |
2263 | DRM_ERROR("Unexpected DE Port interrupt\n"); | |
6d766f02 | 2264 | } |
38cc46d7 OM |
2265 | else |
2266 | DRM_ERROR("The master control interrupt lied (DE PORT)!\n"); | |
6d766f02 DV |
2267 | } |
2268 | ||
055e393f | 2269 | for_each_pipe(dev_priv, pipe) { |
770de83d | 2270 | uint32_t pipe_iir, flip_done = 0, fault_errors = 0; |
abd58f01 | 2271 | |
c42664cc DV |
2272 | if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) |
2273 | continue; | |
abd58f01 | 2274 | |
c42664cc | 2275 | pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); |
c42664cc DV |
2276 | if (pipe_iir) { |
2277 | ret = IRQ_HANDLED; | |
2278 | I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir); | |
770de83d | 2279 | |
d6bbafa1 CW |
2280 | if (pipe_iir & GEN8_PIPE_VBLANK && |
2281 | intel_pipe_handle_vblank(dev, pipe)) | |
2282 | intel_check_page_flip(dev, pipe); | |
38cc46d7 | 2283 | |
770de83d DL |
2284 | if (IS_GEN9(dev)) |
2285 | flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE; | |
2286 | else | |
2287 | flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE; | |
2288 | ||
2289 | if (flip_done) { | |
38cc46d7 OM |
2290 | intel_prepare_page_flip(dev, pipe); |
2291 | intel_finish_page_flip_plane(dev, pipe); | |
2292 | } | |
2293 | ||
2294 | if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE) | |
2295 | hsw_pipe_crc_irq_handler(dev, pipe); | |
2296 | ||
1f7247c0 DV |
2297 | if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) |
2298 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
2299 | pipe); | |
38cc46d7 | 2300 | |
770de83d DL |
2301 | |
2302 | if (IS_GEN9(dev)) | |
2303 | fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS; | |
2304 | else | |
2305 | fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
2306 | ||
2307 | if (fault_errors) | |
38cc46d7 OM |
2308 | DRM_ERROR("Fault errors on pipe %c\n: 0x%08x", |
2309 | pipe_name(pipe), | |
2310 | pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS); | |
c42664cc | 2311 | } else |
abd58f01 BW |
2312 | DRM_ERROR("The master control interrupt lied (DE PIPE)!\n"); |
2313 | } | |
2314 | ||
92d03a80 DV |
2315 | if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) { |
2316 | /* | |
2317 | * FIXME(BDW): Assume for now that the new interrupt handling | |
2318 | * scheme also closed the SDE interrupt handling race we've seen | |
2319 | * on older pch-split platforms. But this needs testing. | |
2320 | */ | |
2321 | u32 pch_iir = I915_READ(SDEIIR); | |
92d03a80 DV |
2322 | if (pch_iir) { |
2323 | I915_WRITE(SDEIIR, pch_iir); | |
2324 | ret = IRQ_HANDLED; | |
38cc46d7 OM |
2325 | cpt_irq_handler(dev, pch_iir); |
2326 | } else | |
2327 | DRM_ERROR("The master control interrupt lied (SDE)!\n"); | |
2328 | ||
92d03a80 DV |
2329 | } |
2330 | ||
abd58f01 BW |
2331 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
2332 | POSTING_READ(GEN8_MASTER_IRQ); | |
2333 | ||
2334 | return ret; | |
2335 | } | |
2336 | ||
17e1df07 DV |
2337 | static void i915_error_wake_up(struct drm_i915_private *dev_priv, |
2338 | bool reset_completed) | |
2339 | { | |
a4872ba6 | 2340 | struct intel_engine_cs *ring; |
17e1df07 DV |
2341 | int i; |
2342 | ||
2343 | /* | |
2344 | * Notify all waiters for GPU completion events that reset state has | |
2345 | * been changed, and that they need to restart their wait after | |
2346 | * checking for potential errors (and bail out to drop locks if there is | |
2347 | * a gpu reset pending so that i915_error_work_func can acquire them). | |
2348 | */ | |
2349 | ||
2350 | /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */ | |
2351 | for_each_ring(ring, dev_priv, i) | |
2352 | wake_up_all(&ring->irq_queue); | |
2353 | ||
2354 | /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */ | |
2355 | wake_up_all(&dev_priv->pending_flip_queue); | |
2356 | ||
2357 | /* | |
2358 | * Signal tasks blocked in i915_gem_wait_for_error that the pending | |
2359 | * reset state is cleared. | |
2360 | */ | |
2361 | if (reset_completed) | |
2362 | wake_up_all(&dev_priv->gpu_error.reset_queue); | |
2363 | } | |
2364 | ||
8a905236 JB |
2365 | /** |
2366 | * i915_error_work_func - do process context error handling work | |
2367 | * @work: work struct | |
2368 | * | |
2369 | * Fire an error uevent so userspace can see that a hang or error | |
2370 | * was detected. | |
2371 | */ | |
2372 | static void i915_error_work_func(struct work_struct *work) | |
2373 | { | |
1f83fee0 DV |
2374 | struct i915_gpu_error *error = container_of(work, struct i915_gpu_error, |
2375 | work); | |
2d1013dd JN |
2376 | struct drm_i915_private *dev_priv = |
2377 | container_of(error, struct drm_i915_private, gpu_error); | |
8a905236 | 2378 | struct drm_device *dev = dev_priv->dev; |
cce723ed BW |
2379 | char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; |
2380 | char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; | |
2381 | char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; | |
17e1df07 | 2382 | int ret; |
8a905236 | 2383 | |
5bdebb18 | 2384 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event); |
f316a42c | 2385 | |
7db0ba24 DV |
2386 | /* |
2387 | * Note that there's only one work item which does gpu resets, so we | |
2388 | * need not worry about concurrent gpu resets potentially incrementing | |
2389 | * error->reset_counter twice. We only need to take care of another | |
2390 | * racing irq/hangcheck declaring the gpu dead for a second time. A | |
2391 | * quick check for that is good enough: schedule_work ensures the | |
2392 | * correct ordering between hang detection and this work item, and since | |
2393 | * the reset in-progress bit is only ever set by code outside of this | |
2394 | * work we don't need to worry about any other races. | |
2395 | */ | |
2396 | if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) { | |
f803aa55 | 2397 | DRM_DEBUG_DRIVER("resetting chip\n"); |
5bdebb18 | 2398 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, |
7db0ba24 | 2399 | reset_event); |
1f83fee0 | 2400 | |
f454c694 ID |
2401 | /* |
2402 | * In most cases it's guaranteed that we get here with an RPM | |
2403 | * reference held, for example because there is a pending GPU | |
2404 | * request that won't finish until the reset is done. This | |
2405 | * isn't the case at least when we get here by doing a | |
2406 | * simulated reset via debugs, so get an RPM reference. | |
2407 | */ | |
2408 | intel_runtime_pm_get(dev_priv); | |
17e1df07 DV |
2409 | /* |
2410 | * All state reset _must_ be completed before we update the | |
2411 | * reset counter, for otherwise waiters might miss the reset | |
2412 | * pending state and not properly drop locks, resulting in | |
2413 | * deadlocks with the reset work. | |
2414 | */ | |
f69061be DV |
2415 | ret = i915_reset(dev); |
2416 | ||
17e1df07 DV |
2417 | intel_display_handle_reset(dev); |
2418 | ||
f454c694 ID |
2419 | intel_runtime_pm_put(dev_priv); |
2420 | ||
f69061be DV |
2421 | if (ret == 0) { |
2422 | /* | |
2423 | * After all the gem state is reset, increment the reset | |
2424 | * counter and wake up everyone waiting for the reset to | |
2425 | * complete. | |
2426 | * | |
2427 | * Since unlock operations are a one-sided barrier only, | |
2428 | * we need to insert a barrier here to order any seqno | |
2429 | * updates before | |
2430 | * the counter increment. | |
2431 | */ | |
4e857c58 | 2432 | smp_mb__before_atomic(); |
f69061be DV |
2433 | atomic_inc(&dev_priv->gpu_error.reset_counter); |
2434 | ||
5bdebb18 | 2435 | kobject_uevent_env(&dev->primary->kdev->kobj, |
f69061be | 2436 | KOBJ_CHANGE, reset_done_event); |
1f83fee0 | 2437 | } else { |
2ac0f450 | 2438 | atomic_set_mask(I915_WEDGED, &error->reset_counter); |
f316a42c | 2439 | } |
1f83fee0 | 2440 | |
17e1df07 DV |
2441 | /* |
2442 | * Note: The wake_up also serves as a memory barrier so that | |
2443 | * waiters see the update value of the reset counter atomic_t. | |
2444 | */ | |
2445 | i915_error_wake_up(dev_priv, true); | |
f316a42c | 2446 | } |
8a905236 JB |
2447 | } |
2448 | ||
35aed2e6 | 2449 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
2450 | { |
2451 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bd9854f9 | 2452 | uint32_t instdone[I915_NUM_INSTDONE_REG]; |
8a905236 | 2453 | u32 eir = I915_READ(EIR); |
050ee91f | 2454 | int pipe, i; |
8a905236 | 2455 | |
35aed2e6 CW |
2456 | if (!eir) |
2457 | return; | |
8a905236 | 2458 | |
a70491cc | 2459 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
8a905236 | 2460 | |
bd9854f9 BW |
2461 | i915_get_extra_instdone(dev, instdone); |
2462 | ||
8a905236 JB |
2463 | if (IS_G4X(dev)) { |
2464 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
2465 | u32 ipeir = I915_READ(IPEIR_I965); | |
2466 | ||
a70491cc JP |
2467 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2468 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
050ee91f BW |
2469 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2470 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a70491cc | 2471 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2472 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2473 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2474 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2475 | } |
2476 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
2477 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2478 | pr_err("page table error\n"); |
2479 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2480 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2481 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2482 | } |
2483 | } | |
2484 | ||
a6c45cf0 | 2485 | if (!IS_GEN2(dev)) { |
8a905236 JB |
2486 | if (eir & I915_ERROR_PAGE_TABLE) { |
2487 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2488 | pr_err("page table error\n"); |
2489 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2490 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2491 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2492 | } |
2493 | } | |
2494 | ||
2495 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
a70491cc | 2496 | pr_err("memory refresh error:\n"); |
055e393f | 2497 | for_each_pipe(dev_priv, pipe) |
a70491cc | 2498 | pr_err("pipe %c stat: 0x%08x\n", |
9db4a9c7 | 2499 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
8a905236 JB |
2500 | /* pipestat has already been acked */ |
2501 | } | |
2502 | if (eir & I915_ERROR_INSTRUCTION) { | |
a70491cc JP |
2503 | pr_err("instruction error\n"); |
2504 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); | |
050ee91f BW |
2505 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2506 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a6c45cf0 | 2507 | if (INTEL_INFO(dev)->gen < 4) { |
8a905236 JB |
2508 | u32 ipeir = I915_READ(IPEIR); |
2509 | ||
a70491cc JP |
2510 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
2511 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); | |
a70491cc | 2512 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); |
8a905236 | 2513 | I915_WRITE(IPEIR, ipeir); |
3143a2bf | 2514 | POSTING_READ(IPEIR); |
8a905236 JB |
2515 | } else { |
2516 | u32 ipeir = I915_READ(IPEIR_I965); | |
2517 | ||
a70491cc JP |
2518 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2519 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
a70491cc | 2520 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2521 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2522 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2523 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2524 | } |
2525 | } | |
2526 | ||
2527 | I915_WRITE(EIR, eir); | |
3143a2bf | 2528 | POSTING_READ(EIR); |
8a905236 JB |
2529 | eir = I915_READ(EIR); |
2530 | if (eir) { | |
2531 | /* | |
2532 | * some errors might have become stuck, | |
2533 | * mask them. | |
2534 | */ | |
2535 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
2536 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
2537 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2538 | } | |
35aed2e6 CW |
2539 | } |
2540 | ||
2541 | /** | |
2542 | * i915_handle_error - handle an error interrupt | |
2543 | * @dev: drm device | |
2544 | * | |
2545 | * Do some basic checking of regsiter state at error interrupt time and | |
2546 | * dump it to the syslog. Also call i915_capture_error_state() to make | |
2547 | * sure we get a record and make it available in debugfs. Fire a uevent | |
2548 | * so userspace knows something bad happened (should trigger collection | |
2549 | * of a ring dump etc.). | |
2550 | */ | |
58174462 MK |
2551 | void i915_handle_error(struct drm_device *dev, bool wedged, |
2552 | const char *fmt, ...) | |
35aed2e6 CW |
2553 | { |
2554 | struct drm_i915_private *dev_priv = dev->dev_private; | |
58174462 MK |
2555 | va_list args; |
2556 | char error_msg[80]; | |
35aed2e6 | 2557 | |
58174462 MK |
2558 | va_start(args, fmt); |
2559 | vscnprintf(error_msg, sizeof(error_msg), fmt, args); | |
2560 | va_end(args); | |
2561 | ||
2562 | i915_capture_error_state(dev, wedged, error_msg); | |
35aed2e6 | 2563 | i915_report_and_clear_eir(dev); |
8a905236 | 2564 | |
ba1234d1 | 2565 | if (wedged) { |
f69061be DV |
2566 | atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG, |
2567 | &dev_priv->gpu_error.reset_counter); | |
ba1234d1 | 2568 | |
11ed50ec | 2569 | /* |
17e1df07 DV |
2570 | * Wakeup waiting processes so that the reset work function |
2571 | * i915_error_work_func doesn't deadlock trying to grab various | |
2572 | * locks. By bumping the reset counter first, the woken | |
2573 | * processes will see a reset in progress and back off, | |
2574 | * releasing their locks and then wait for the reset completion. | |
2575 | * We must do this for _all_ gpu waiters that might hold locks | |
2576 | * that the reset work needs to acquire. | |
2577 | * | |
2578 | * Note: The wake_up serves as the required memory barrier to | |
2579 | * ensure that the waiters see the updated value of the reset | |
2580 | * counter atomic_t. | |
11ed50ec | 2581 | */ |
17e1df07 | 2582 | i915_error_wake_up(dev_priv, false); |
11ed50ec BG |
2583 | } |
2584 | ||
122f46ba DV |
2585 | /* |
2586 | * Our reset work can grab modeset locks (since it needs to reset the | |
2587 | * state of outstanding pagelips). Hence it must not be run on our own | |
2588 | * dev-priv->wq work queue for otherwise the flush_work in the pageflip | |
2589 | * code will deadlock. | |
2590 | */ | |
2591 | schedule_work(&dev_priv->gpu_error.work); | |
8a905236 JB |
2592 | } |
2593 | ||
42f52ef8 KP |
2594 | /* Called from drm generic code, passed 'crtc' which |
2595 | * we use as a pipe index | |
2596 | */ | |
f71d4af4 | 2597 | static int i915_enable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 | 2598 | { |
2d1013dd | 2599 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2600 | unsigned long irqflags; |
71e0ffa5 | 2601 | |
5eddb70b | 2602 | if (!i915_pipe_enabled(dev, pipe)) |
71e0ffa5 | 2603 | return -EINVAL; |
0a3e67a4 | 2604 | |
1ec14ad3 | 2605 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2606 | if (INTEL_INFO(dev)->gen >= 4) |
7c463586 | 2607 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2608 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
e9d21d7f | 2609 | else |
7c463586 | 2610 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2611 | PIPE_VBLANK_INTERRUPT_STATUS); |
1ec14ad3 | 2612 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
8692d00e | 2613 | |
0a3e67a4 JB |
2614 | return 0; |
2615 | } | |
2616 | ||
f71d4af4 | 2617 | static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
f796cf8f | 2618 | { |
2d1013dd | 2619 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2620 | unsigned long irqflags; |
b518421f | 2621 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2622 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2623 | |
2624 | if (!i915_pipe_enabled(dev, pipe)) | |
2625 | return -EINVAL; | |
2626 | ||
2627 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 2628 | ironlake_enable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2629 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2630 | ||
2631 | return 0; | |
2632 | } | |
2633 | ||
7e231dbe JB |
2634 | static int valleyview_enable_vblank(struct drm_device *dev, int pipe) |
2635 | { | |
2d1013dd | 2636 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2637 | unsigned long irqflags; |
7e231dbe JB |
2638 | |
2639 | if (!i915_pipe_enabled(dev, pipe)) | |
2640 | return -EINVAL; | |
2641 | ||
2642 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 | 2643 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2644 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2645 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2646 | ||
2647 | return 0; | |
2648 | } | |
2649 | ||
abd58f01 BW |
2650 | static int gen8_enable_vblank(struct drm_device *dev, int pipe) |
2651 | { | |
2652 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2653 | unsigned long irqflags; | |
abd58f01 BW |
2654 | |
2655 | if (!i915_pipe_enabled(dev, pipe)) | |
2656 | return -EINVAL; | |
2657 | ||
2658 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
7167d7c6 DV |
2659 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK; |
2660 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2661 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2662 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2663 | return 0; | |
2664 | } | |
2665 | ||
42f52ef8 KP |
2666 | /* Called from drm generic code, passed 'crtc' which |
2667 | * we use as a pipe index | |
2668 | */ | |
f71d4af4 | 2669 | static void i915_disable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 | 2670 | { |
2d1013dd | 2671 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2672 | unsigned long irqflags; |
0a3e67a4 | 2673 | |
1ec14ad3 | 2674 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2675 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 ID |
2676 | PIPE_VBLANK_INTERRUPT_STATUS | |
2677 | PIPE_START_VBLANK_INTERRUPT_STATUS); | |
f796cf8f JB |
2678 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2679 | } | |
2680 | ||
f71d4af4 | 2681 | static void ironlake_disable_vblank(struct drm_device *dev, int pipe) |
f796cf8f | 2682 | { |
2d1013dd | 2683 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2684 | unsigned long irqflags; |
b518421f | 2685 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2686 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2687 | |
2688 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 2689 | ironlake_disable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2690 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2691 | } | |
2692 | ||
7e231dbe JB |
2693 | static void valleyview_disable_vblank(struct drm_device *dev, int pipe) |
2694 | { | |
2d1013dd | 2695 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2696 | unsigned long irqflags; |
7e231dbe JB |
2697 | |
2698 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 | 2699 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 | 2700 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2701 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2702 | } | |
2703 | ||
abd58f01 BW |
2704 | static void gen8_disable_vblank(struct drm_device *dev, int pipe) |
2705 | { | |
2706 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2707 | unsigned long irqflags; | |
abd58f01 BW |
2708 | |
2709 | if (!i915_pipe_enabled(dev, pipe)) | |
2710 | return; | |
2711 | ||
2712 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
7167d7c6 DV |
2713 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK; |
2714 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2715 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2716 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2717 | } | |
2718 | ||
893eead0 | 2719 | static u32 |
a4872ba6 | 2720 | ring_last_seqno(struct intel_engine_cs *ring) |
852835f3 | 2721 | { |
893eead0 CW |
2722 | return list_entry(ring->request_list.prev, |
2723 | struct drm_i915_gem_request, list)->seqno; | |
2724 | } | |
2725 | ||
9107e9d2 | 2726 | static bool |
a4872ba6 | 2727 | ring_idle(struct intel_engine_cs *ring, u32 seqno) |
9107e9d2 CW |
2728 | { |
2729 | return (list_empty(&ring->request_list) || | |
2730 | i915_seqno_passed(seqno, ring_last_seqno(ring))); | |
f65d9421 BG |
2731 | } |
2732 | ||
a028c4b0 DV |
2733 | static bool |
2734 | ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr) | |
2735 | { | |
2736 | if (INTEL_INFO(dev)->gen >= 8) { | |
a6cdb93a | 2737 | return (ipehr >> 23) == 0x1c; |
a028c4b0 DV |
2738 | } else { |
2739 | ipehr &= ~MI_SEMAPHORE_SYNC_MASK; | |
2740 | return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | | |
2741 | MI_SEMAPHORE_REGISTER); | |
2742 | } | |
2743 | } | |
2744 | ||
a4872ba6 | 2745 | static struct intel_engine_cs * |
a6cdb93a | 2746 | semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset) |
921d42ea DV |
2747 | { |
2748 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
a4872ba6 | 2749 | struct intel_engine_cs *signaller; |
921d42ea DV |
2750 | int i; |
2751 | ||
2752 | if (INTEL_INFO(dev_priv->dev)->gen >= 8) { | |
a6cdb93a RV |
2753 | for_each_ring(signaller, dev_priv, i) { |
2754 | if (ring == signaller) | |
2755 | continue; | |
2756 | ||
2757 | if (offset == signaller->semaphore.signal_ggtt[ring->id]) | |
2758 | return signaller; | |
2759 | } | |
921d42ea DV |
2760 | } else { |
2761 | u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK; | |
2762 | ||
2763 | for_each_ring(signaller, dev_priv, i) { | |
2764 | if(ring == signaller) | |
2765 | continue; | |
2766 | ||
ebc348b2 | 2767 | if (sync_bits == signaller->semaphore.mbox.wait[ring->id]) |
921d42ea DV |
2768 | return signaller; |
2769 | } | |
2770 | } | |
2771 | ||
a6cdb93a RV |
2772 | DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n", |
2773 | ring->id, ipehr, offset); | |
921d42ea DV |
2774 | |
2775 | return NULL; | |
2776 | } | |
2777 | ||
a4872ba6 OM |
2778 | static struct intel_engine_cs * |
2779 | semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno) | |
a24a11e6 CW |
2780 | { |
2781 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
88fe429d | 2782 | u32 cmd, ipehr, head; |
a6cdb93a RV |
2783 | u64 offset = 0; |
2784 | int i, backwards; | |
a24a11e6 CW |
2785 | |
2786 | ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); | |
a028c4b0 | 2787 | if (!ipehr_is_semaphore_wait(ring->dev, ipehr)) |
6274f212 | 2788 | return NULL; |
a24a11e6 | 2789 | |
88fe429d DV |
2790 | /* |
2791 | * HEAD is likely pointing to the dword after the actual command, | |
2792 | * so scan backwards until we find the MBOX. But limit it to just 3 | |
a6cdb93a RV |
2793 | * or 4 dwords depending on the semaphore wait command size. |
2794 | * Note that we don't care about ACTHD here since that might | |
88fe429d DV |
2795 | * point at at batch, and semaphores are always emitted into the |
2796 | * ringbuffer itself. | |
a24a11e6 | 2797 | */ |
88fe429d | 2798 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
a6cdb93a | 2799 | backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4; |
88fe429d | 2800 | |
a6cdb93a | 2801 | for (i = backwards; i; --i) { |
88fe429d DV |
2802 | /* |
2803 | * Be paranoid and presume the hw has gone off into the wild - | |
2804 | * our ring is smaller than what the hardware (and hence | |
2805 | * HEAD_ADDR) allows. Also handles wrap-around. | |
2806 | */ | |
ee1b1e5e | 2807 | head &= ring->buffer->size - 1; |
88fe429d DV |
2808 | |
2809 | /* This here seems to blow up */ | |
ee1b1e5e | 2810 | cmd = ioread32(ring->buffer->virtual_start + head); |
a24a11e6 CW |
2811 | if (cmd == ipehr) |
2812 | break; | |
2813 | ||
88fe429d DV |
2814 | head -= 4; |
2815 | } | |
a24a11e6 | 2816 | |
88fe429d DV |
2817 | if (!i) |
2818 | return NULL; | |
a24a11e6 | 2819 | |
ee1b1e5e | 2820 | *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1; |
a6cdb93a RV |
2821 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
2822 | offset = ioread32(ring->buffer->virtual_start + head + 12); | |
2823 | offset <<= 32; | |
2824 | offset = ioread32(ring->buffer->virtual_start + head + 8); | |
2825 | } | |
2826 | return semaphore_wait_to_signaller_ring(ring, ipehr, offset); | |
a24a11e6 CW |
2827 | } |
2828 | ||
a4872ba6 | 2829 | static int semaphore_passed(struct intel_engine_cs *ring) |
6274f212 CW |
2830 | { |
2831 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
a4872ba6 | 2832 | struct intel_engine_cs *signaller; |
a0d036b0 | 2833 | u32 seqno; |
6274f212 | 2834 | |
4be17381 | 2835 | ring->hangcheck.deadlock++; |
6274f212 CW |
2836 | |
2837 | signaller = semaphore_waits_for(ring, &seqno); | |
4be17381 CW |
2838 | if (signaller == NULL) |
2839 | return -1; | |
2840 | ||
2841 | /* Prevent pathological recursion due to driver bugs */ | |
2842 | if (signaller->hangcheck.deadlock >= I915_NUM_RINGS) | |
6274f212 CW |
2843 | return -1; |
2844 | ||
4be17381 CW |
2845 | if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno)) |
2846 | return 1; | |
2847 | ||
a0d036b0 CW |
2848 | /* cursory check for an unkickable deadlock */ |
2849 | if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE && | |
2850 | semaphore_passed(signaller) < 0) | |
4be17381 CW |
2851 | return -1; |
2852 | ||
2853 | return 0; | |
6274f212 CW |
2854 | } |
2855 | ||
2856 | static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) | |
2857 | { | |
a4872ba6 | 2858 | struct intel_engine_cs *ring; |
6274f212 CW |
2859 | int i; |
2860 | ||
2861 | for_each_ring(ring, dev_priv, i) | |
4be17381 | 2862 | ring->hangcheck.deadlock = 0; |
6274f212 CW |
2863 | } |
2864 | ||
ad8beaea | 2865 | static enum intel_ring_hangcheck_action |
a4872ba6 | 2866 | ring_stuck(struct intel_engine_cs *ring, u64 acthd) |
1ec14ad3 CW |
2867 | { |
2868 | struct drm_device *dev = ring->dev; | |
2869 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9107e9d2 CW |
2870 | u32 tmp; |
2871 | ||
f260fe7b MK |
2872 | if (acthd != ring->hangcheck.acthd) { |
2873 | if (acthd > ring->hangcheck.max_acthd) { | |
2874 | ring->hangcheck.max_acthd = acthd; | |
2875 | return HANGCHECK_ACTIVE; | |
2876 | } | |
2877 | ||
2878 | return HANGCHECK_ACTIVE_LOOP; | |
2879 | } | |
6274f212 | 2880 | |
9107e9d2 | 2881 | if (IS_GEN2(dev)) |
f2f4d82f | 2882 | return HANGCHECK_HUNG; |
9107e9d2 CW |
2883 | |
2884 | /* Is the chip hanging on a WAIT_FOR_EVENT? | |
2885 | * If so we can simply poke the RB_WAIT bit | |
2886 | * and break the hang. This should work on | |
2887 | * all but the second generation chipsets. | |
2888 | */ | |
2889 | tmp = I915_READ_CTL(ring); | |
1ec14ad3 | 2890 | if (tmp & RING_WAIT) { |
58174462 MK |
2891 | i915_handle_error(dev, false, |
2892 | "Kicking stuck wait on %s", | |
2893 | ring->name); | |
1ec14ad3 | 2894 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2895 | return HANGCHECK_KICK; |
6274f212 CW |
2896 | } |
2897 | ||
2898 | if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { | |
2899 | switch (semaphore_passed(ring)) { | |
2900 | default: | |
f2f4d82f | 2901 | return HANGCHECK_HUNG; |
6274f212 | 2902 | case 1: |
58174462 MK |
2903 | i915_handle_error(dev, false, |
2904 | "Kicking stuck semaphore on %s", | |
2905 | ring->name); | |
6274f212 | 2906 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2907 | return HANGCHECK_KICK; |
6274f212 | 2908 | case 0: |
f2f4d82f | 2909 | return HANGCHECK_WAIT; |
6274f212 | 2910 | } |
9107e9d2 | 2911 | } |
ed5cbb03 | 2912 | |
f2f4d82f | 2913 | return HANGCHECK_HUNG; |
ed5cbb03 MK |
2914 | } |
2915 | ||
f65d9421 BG |
2916 | /** |
2917 | * This is called when the chip hasn't reported back with completed | |
05407ff8 MK |
2918 | * batchbuffers in a long time. We keep track per ring seqno progress and |
2919 | * if there are no progress, hangcheck score for that ring is increased. | |
2920 | * Further, acthd is inspected to see if the ring is stuck. On stuck case | |
2921 | * we kick the ring. If we see no progress on three subsequent calls | |
2922 | * we assume chip is wedged and try to fix it by resetting the chip. | |
f65d9421 | 2923 | */ |
a658b5d2 | 2924 | static void i915_hangcheck_elapsed(unsigned long data) |
f65d9421 BG |
2925 | { |
2926 | struct drm_device *dev = (struct drm_device *)data; | |
2d1013dd | 2927 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2928 | struct intel_engine_cs *ring; |
b4519513 | 2929 | int i; |
05407ff8 | 2930 | int busy_count = 0, rings_hung = 0; |
9107e9d2 CW |
2931 | bool stuck[I915_NUM_RINGS] = { 0 }; |
2932 | #define BUSY 1 | |
2933 | #define KICK 5 | |
2934 | #define HUNG 20 | |
893eead0 | 2935 | |
d330a953 | 2936 | if (!i915.enable_hangcheck) |
3e0dc6b0 BW |
2937 | return; |
2938 | ||
b4519513 | 2939 | for_each_ring(ring, dev_priv, i) { |
50877445 CW |
2940 | u64 acthd; |
2941 | u32 seqno; | |
9107e9d2 | 2942 | bool busy = true; |
05407ff8 | 2943 | |
6274f212 CW |
2944 | semaphore_clear_deadlocks(dev_priv); |
2945 | ||
05407ff8 MK |
2946 | seqno = ring->get_seqno(ring, false); |
2947 | acthd = intel_ring_get_active_head(ring); | |
b4519513 | 2948 | |
9107e9d2 CW |
2949 | if (ring->hangcheck.seqno == seqno) { |
2950 | if (ring_idle(ring, seqno)) { | |
da661464 MK |
2951 | ring->hangcheck.action = HANGCHECK_IDLE; |
2952 | ||
9107e9d2 CW |
2953 | if (waitqueue_active(&ring->irq_queue)) { |
2954 | /* Issue a wake-up to catch stuck h/w. */ | |
094f9a54 | 2955 | if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) { |
f4adcd24 DV |
2956 | if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring))) |
2957 | DRM_ERROR("Hangcheck timer elapsed... %s idle\n", | |
2958 | ring->name); | |
2959 | else | |
2960 | DRM_INFO("Fake missed irq on %s\n", | |
2961 | ring->name); | |
094f9a54 CW |
2962 | wake_up_all(&ring->irq_queue); |
2963 | } | |
2964 | /* Safeguard against driver failure */ | |
2965 | ring->hangcheck.score += BUSY; | |
9107e9d2 CW |
2966 | } else |
2967 | busy = false; | |
05407ff8 | 2968 | } else { |
6274f212 CW |
2969 | /* We always increment the hangcheck score |
2970 | * if the ring is busy and still processing | |
2971 | * the same request, so that no single request | |
2972 | * can run indefinitely (such as a chain of | |
2973 | * batches). The only time we do not increment | |
2974 | * the hangcheck score on this ring, if this | |
2975 | * ring is in a legitimate wait for another | |
2976 | * ring. In that case the waiting ring is a | |
2977 | * victim and we want to be sure we catch the | |
2978 | * right culprit. Then every time we do kick | |
2979 | * the ring, add a small increment to the | |
2980 | * score so that we can catch a batch that is | |
2981 | * being repeatedly kicked and so responsible | |
2982 | * for stalling the machine. | |
2983 | */ | |
ad8beaea MK |
2984 | ring->hangcheck.action = ring_stuck(ring, |
2985 | acthd); | |
2986 | ||
2987 | switch (ring->hangcheck.action) { | |
da661464 | 2988 | case HANGCHECK_IDLE: |
f2f4d82f | 2989 | case HANGCHECK_WAIT: |
f2f4d82f | 2990 | case HANGCHECK_ACTIVE: |
f260fe7b MK |
2991 | break; |
2992 | case HANGCHECK_ACTIVE_LOOP: | |
ea04cb31 | 2993 | ring->hangcheck.score += BUSY; |
6274f212 | 2994 | break; |
f2f4d82f | 2995 | case HANGCHECK_KICK: |
ea04cb31 | 2996 | ring->hangcheck.score += KICK; |
6274f212 | 2997 | break; |
f2f4d82f | 2998 | case HANGCHECK_HUNG: |
ea04cb31 | 2999 | ring->hangcheck.score += HUNG; |
6274f212 CW |
3000 | stuck[i] = true; |
3001 | break; | |
3002 | } | |
05407ff8 | 3003 | } |
9107e9d2 | 3004 | } else { |
da661464 MK |
3005 | ring->hangcheck.action = HANGCHECK_ACTIVE; |
3006 | ||
9107e9d2 CW |
3007 | /* Gradually reduce the count so that we catch DoS |
3008 | * attempts across multiple batches. | |
3009 | */ | |
3010 | if (ring->hangcheck.score > 0) | |
3011 | ring->hangcheck.score--; | |
f260fe7b MK |
3012 | |
3013 | ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0; | |
d1e61e7f CW |
3014 | } |
3015 | ||
05407ff8 MK |
3016 | ring->hangcheck.seqno = seqno; |
3017 | ring->hangcheck.acthd = acthd; | |
9107e9d2 | 3018 | busy_count += busy; |
893eead0 | 3019 | } |
b9201c14 | 3020 | |
92cab734 | 3021 | for_each_ring(ring, dev_priv, i) { |
b6b0fac0 | 3022 | if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) { |
b8d88d1d DV |
3023 | DRM_INFO("%s on %s\n", |
3024 | stuck[i] ? "stuck" : "no progress", | |
3025 | ring->name); | |
a43adf07 | 3026 | rings_hung++; |
92cab734 MK |
3027 | } |
3028 | } | |
3029 | ||
05407ff8 | 3030 | if (rings_hung) |
58174462 | 3031 | return i915_handle_error(dev, true, "Ring hung"); |
f65d9421 | 3032 | |
05407ff8 MK |
3033 | if (busy_count) |
3034 | /* Reset timer case chip hangs without another request | |
3035 | * being added */ | |
10cd45b6 MK |
3036 | i915_queue_hangcheck(dev); |
3037 | } | |
3038 | ||
3039 | void i915_queue_hangcheck(struct drm_device *dev) | |
3040 | { | |
3041 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d330a953 | 3042 | if (!i915.enable_hangcheck) |
10cd45b6 MK |
3043 | return; |
3044 | ||
3045 | mod_timer(&dev_priv->gpu_error.hangcheck_timer, | |
3046 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); | |
f65d9421 BG |
3047 | } |
3048 | ||
1c69eb42 | 3049 | static void ibx_irq_reset(struct drm_device *dev) |
91738a95 PZ |
3050 | { |
3051 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3052 | ||
3053 | if (HAS_PCH_NOP(dev)) | |
3054 | return; | |
3055 | ||
f86f3fb0 | 3056 | GEN5_IRQ_RESET(SDE); |
105b122e PZ |
3057 | |
3058 | if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) | |
3059 | I915_WRITE(SERR_INT, 0xffffffff); | |
622364b6 | 3060 | } |
105b122e | 3061 | |
622364b6 PZ |
3062 | /* |
3063 | * SDEIER is also touched by the interrupt handler to work around missed PCH | |
3064 | * interrupts. Hence we can't update it after the interrupt handler is enabled - | |
3065 | * instead we unconditionally enable all PCH interrupt sources here, but then | |
3066 | * only unmask them as needed with SDEIMR. | |
3067 | * | |
3068 | * This function needs to be called before interrupts are enabled. | |
3069 | */ | |
3070 | static void ibx_irq_pre_postinstall(struct drm_device *dev) | |
3071 | { | |
3072 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3073 | ||
3074 | if (HAS_PCH_NOP(dev)) | |
3075 | return; | |
3076 | ||
3077 | WARN_ON(I915_READ(SDEIER) != 0); | |
91738a95 PZ |
3078 | I915_WRITE(SDEIER, 0xffffffff); |
3079 | POSTING_READ(SDEIER); | |
3080 | } | |
3081 | ||
7c4d664e | 3082 | static void gen5_gt_irq_reset(struct drm_device *dev) |
d18ea1b5 DV |
3083 | { |
3084 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3085 | ||
f86f3fb0 | 3086 | GEN5_IRQ_RESET(GT); |
a9d356a6 | 3087 | if (INTEL_INFO(dev)->gen >= 6) |
f86f3fb0 | 3088 | GEN5_IRQ_RESET(GEN6_PM); |
d18ea1b5 DV |
3089 | } |
3090 | ||
1da177e4 LT |
3091 | /* drm_dma.h hooks |
3092 | */ | |
be30b29f | 3093 | static void ironlake_irq_reset(struct drm_device *dev) |
036a4a7d | 3094 | { |
2d1013dd | 3095 | struct drm_i915_private *dev_priv = dev->dev_private; |
036a4a7d | 3096 | |
0c841212 | 3097 | I915_WRITE(HWSTAM, 0xffffffff); |
bdfcdb63 | 3098 | |
f86f3fb0 | 3099 | GEN5_IRQ_RESET(DE); |
c6d954c1 PZ |
3100 | if (IS_GEN7(dev)) |
3101 | I915_WRITE(GEN7_ERR_INT, 0xffffffff); | |
036a4a7d | 3102 | |
7c4d664e | 3103 | gen5_gt_irq_reset(dev); |
c650156a | 3104 | |
1c69eb42 | 3105 | ibx_irq_reset(dev); |
7d99163d | 3106 | } |
c650156a | 3107 | |
7e231dbe JB |
3108 | static void valleyview_irq_preinstall(struct drm_device *dev) |
3109 | { | |
2d1013dd | 3110 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
3111 | int pipe; |
3112 | ||
7e231dbe JB |
3113 | /* VLV magic */ |
3114 | I915_WRITE(VLV_IMR, 0); | |
3115 | I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); | |
3116 | I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); | |
3117 | I915_WRITE(RING_IMR(BLT_RING_BASE), 0); | |
3118 | ||
7e231dbe JB |
3119 | /* and GT */ |
3120 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
3121 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
d18ea1b5 | 3122 | |
7c4d664e | 3123 | gen5_gt_irq_reset(dev); |
7e231dbe | 3124 | |
7c4cde39 | 3125 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); |
7e231dbe JB |
3126 | |
3127 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3128 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
055e393f | 3129 | for_each_pipe(dev_priv, pipe) |
7e231dbe | 3130 | I915_WRITE(PIPESTAT(pipe), 0xffff); |
23a09c76 VS |
3131 | |
3132 | GEN5_IRQ_RESET(VLV_); | |
7e231dbe JB |
3133 | } |
3134 | ||
d6e3cca3 DV |
3135 | static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv) |
3136 | { | |
3137 | GEN8_IRQ_RESET_NDX(GT, 0); | |
3138 | GEN8_IRQ_RESET_NDX(GT, 1); | |
3139 | GEN8_IRQ_RESET_NDX(GT, 2); | |
3140 | GEN8_IRQ_RESET_NDX(GT, 3); | |
3141 | } | |
3142 | ||
823f6b38 | 3143 | static void gen8_irq_reset(struct drm_device *dev) |
abd58f01 BW |
3144 | { |
3145 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3146 | int pipe; | |
3147 | ||
abd58f01 BW |
3148 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
3149 | POSTING_READ(GEN8_MASTER_IRQ); | |
3150 | ||
d6e3cca3 | 3151 | gen8_gt_irq_reset(dev_priv); |
abd58f01 | 3152 | |
055e393f | 3153 | for_each_pipe(dev_priv, pipe) |
f458ebbc DV |
3154 | if (intel_display_power_is_enabled(dev_priv, |
3155 | POWER_DOMAIN_PIPE(pipe))) | |
813bde43 | 3156 | GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); |
abd58f01 | 3157 | |
f86f3fb0 PZ |
3158 | GEN5_IRQ_RESET(GEN8_DE_PORT_); |
3159 | GEN5_IRQ_RESET(GEN8_DE_MISC_); | |
3160 | GEN5_IRQ_RESET(GEN8_PCU_); | |
abd58f01 | 3161 | |
1c69eb42 | 3162 | ibx_irq_reset(dev); |
abd58f01 | 3163 | } |
09f2344d | 3164 | |
d49bdb0e PZ |
3165 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv) |
3166 | { | |
1180e206 | 3167 | uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; |
d49bdb0e | 3168 | |
13321786 | 3169 | spin_lock_irq(&dev_priv->irq_lock); |
d49bdb0e | 3170 | GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B], |
1180e206 | 3171 | ~dev_priv->de_irq_mask[PIPE_B] | extra_ier); |
d49bdb0e | 3172 | GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C], |
1180e206 | 3173 | ~dev_priv->de_irq_mask[PIPE_C] | extra_ier); |
13321786 | 3174 | spin_unlock_irq(&dev_priv->irq_lock); |
d49bdb0e PZ |
3175 | } |
3176 | ||
43f328d7 VS |
3177 | static void cherryview_irq_preinstall(struct drm_device *dev) |
3178 | { | |
3179 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3180 | int pipe; | |
3181 | ||
3182 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3183 | POSTING_READ(GEN8_MASTER_IRQ); | |
3184 | ||
d6e3cca3 | 3185 | gen8_gt_irq_reset(dev_priv); |
43f328d7 VS |
3186 | |
3187 | GEN5_IRQ_RESET(GEN8_PCU_); | |
3188 | ||
43f328d7 VS |
3189 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV); |
3190 | ||
3191 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3192 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3193 | ||
055e393f | 3194 | for_each_pipe(dev_priv, pipe) |
43f328d7 VS |
3195 | I915_WRITE(PIPESTAT(pipe), 0xffff); |
3196 | ||
23a09c76 | 3197 | GEN5_IRQ_RESET(VLV_); |
43f328d7 VS |
3198 | } |
3199 | ||
82a28bcf | 3200 | static void ibx_hpd_irq_setup(struct drm_device *dev) |
7fe0b973 | 3201 | { |
2d1013dd | 3202 | struct drm_i915_private *dev_priv = dev->dev_private; |
82a28bcf | 3203 | struct intel_encoder *intel_encoder; |
fee884ed | 3204 | u32 hotplug_irqs, hotplug, enabled_irqs = 0; |
82a28bcf DV |
3205 | |
3206 | if (HAS_PCH_IBX(dev)) { | |
fee884ed | 3207 | hotplug_irqs = SDE_HOTPLUG_MASK; |
b2784e15 | 3208 | for_each_intel_encoder(dev, intel_encoder) |
cd569aed | 3209 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
fee884ed | 3210 | enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin]; |
82a28bcf | 3211 | } else { |
fee884ed | 3212 | hotplug_irqs = SDE_HOTPLUG_MASK_CPT; |
b2784e15 | 3213 | for_each_intel_encoder(dev, intel_encoder) |
cd569aed | 3214 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
fee884ed | 3215 | enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin]; |
82a28bcf | 3216 | } |
7fe0b973 | 3217 | |
fee884ed | 3218 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); |
82a28bcf DV |
3219 | |
3220 | /* | |
3221 | * Enable digital hotplug on the PCH, and configure the DP short pulse | |
3222 | * duration to 2ms (which is the minimum in the Display Port spec) | |
3223 | * | |
3224 | * This register is the same on all known PCH chips. | |
3225 | */ | |
7fe0b973 KP |
3226 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
3227 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); | |
3228 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; | |
3229 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; | |
3230 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; | |
3231 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); | |
3232 | } | |
3233 | ||
d46da437 PZ |
3234 | static void ibx_irq_postinstall(struct drm_device *dev) |
3235 | { | |
2d1013dd | 3236 | struct drm_i915_private *dev_priv = dev->dev_private; |
82a28bcf | 3237 | u32 mask; |
e5868a31 | 3238 | |
692a04cf DV |
3239 | if (HAS_PCH_NOP(dev)) |
3240 | return; | |
3241 | ||
105b122e | 3242 | if (HAS_PCH_IBX(dev)) |
5c673b60 | 3243 | mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; |
105b122e | 3244 | else |
5c673b60 | 3245 | mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; |
8664281b | 3246 | |
337ba017 | 3247 | GEN5_ASSERT_IIR_IS_ZERO(SDEIIR); |
d46da437 | 3248 | I915_WRITE(SDEIMR, ~mask); |
d46da437 PZ |
3249 | } |
3250 | ||
0a9a8c91 DV |
3251 | static void gen5_gt_irq_postinstall(struct drm_device *dev) |
3252 | { | |
3253 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3254 | u32 pm_irqs, gt_irqs; | |
3255 | ||
3256 | pm_irqs = gt_irqs = 0; | |
3257 | ||
3258 | dev_priv->gt_irq_mask = ~0; | |
040d2baa | 3259 | if (HAS_L3_DPF(dev)) { |
0a9a8c91 | 3260 | /* L3 parity interrupt is always unmasked. */ |
35a85ac6 BW |
3261 | dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev); |
3262 | gt_irqs |= GT_PARITY_ERROR(dev); | |
0a9a8c91 DV |
3263 | } |
3264 | ||
3265 | gt_irqs |= GT_RENDER_USER_INTERRUPT; | |
3266 | if (IS_GEN5(dev)) { | |
3267 | gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | | |
3268 | ILK_BSD_USER_INTERRUPT; | |
3269 | } else { | |
3270 | gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; | |
3271 | } | |
3272 | ||
35079899 | 3273 | GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); |
0a9a8c91 DV |
3274 | |
3275 | if (INTEL_INFO(dev)->gen >= 6) { | |
a6706b45 | 3276 | pm_irqs |= dev_priv->pm_rps_events; |
0a9a8c91 DV |
3277 | |
3278 | if (HAS_VEBOX(dev)) | |
3279 | pm_irqs |= PM_VEBOX_USER_INTERRUPT; | |
3280 | ||
605cd25b | 3281 | dev_priv->pm_irq_mask = 0xffffffff; |
35079899 | 3282 | GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs); |
0a9a8c91 DV |
3283 | } |
3284 | } | |
3285 | ||
f71d4af4 | 3286 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d | 3287 | { |
2d1013dd | 3288 | struct drm_i915_private *dev_priv = dev->dev_private; |
8e76f8dc PZ |
3289 | u32 display_mask, extra_mask; |
3290 | ||
3291 | if (INTEL_INFO(dev)->gen >= 7) { | |
3292 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | | |
3293 | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | | |
3294 | DE_PLANEB_FLIP_DONE_IVB | | |
5c673b60 | 3295 | DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB); |
8e76f8dc | 3296 | extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | |
5c673b60 | 3297 | DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB); |
8e76f8dc PZ |
3298 | } else { |
3299 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | | |
3300 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | | |
5b3a856b | 3301 | DE_AUX_CHANNEL_A | |
5b3a856b DV |
3302 | DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE | |
3303 | DE_POISON); | |
5c673b60 DV |
3304 | extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT | |
3305 | DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN; | |
8e76f8dc | 3306 | } |
036a4a7d | 3307 | |
1ec14ad3 | 3308 | dev_priv->irq_mask = ~display_mask; |
036a4a7d | 3309 | |
0c841212 PZ |
3310 | I915_WRITE(HWSTAM, 0xeffe); |
3311 | ||
622364b6 PZ |
3312 | ibx_irq_pre_postinstall(dev); |
3313 | ||
35079899 | 3314 | GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); |
036a4a7d | 3315 | |
0a9a8c91 | 3316 | gen5_gt_irq_postinstall(dev); |
036a4a7d | 3317 | |
d46da437 | 3318 | ibx_irq_postinstall(dev); |
7fe0b973 | 3319 | |
f97108d1 | 3320 | if (IS_IRONLAKE_M(dev)) { |
6005ce42 DV |
3321 | /* Enable PCU event interrupts |
3322 | * | |
3323 | * spinlocking not required here for correctness since interrupt | |
4bc9d430 DV |
3324 | * setup is guaranteed to run in single-threaded context. But we |
3325 | * need it to make the assert_spin_locked happy. */ | |
d6207435 | 3326 | spin_lock_irq(&dev_priv->irq_lock); |
f97108d1 | 3327 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); |
d6207435 | 3328 | spin_unlock_irq(&dev_priv->irq_lock); |
f97108d1 JB |
3329 | } |
3330 | ||
036a4a7d ZW |
3331 | return 0; |
3332 | } | |
3333 | ||
f8b79e58 ID |
3334 | static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv) |
3335 | { | |
3336 | u32 pipestat_mask; | |
3337 | u32 iir_mask; | |
3338 | ||
3339 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | | |
3340 | PIPE_FIFO_UNDERRUN_STATUS; | |
3341 | ||
3342 | I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask); | |
3343 | I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask); | |
3344 | POSTING_READ(PIPESTAT(PIPE_A)); | |
3345 | ||
3346 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3347 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3348 | ||
3349 | i915_enable_pipestat(dev_priv, PIPE_A, pipestat_mask | | |
3350 | PIPE_GMBUS_INTERRUPT_STATUS); | |
3351 | i915_enable_pipestat(dev_priv, PIPE_B, pipestat_mask); | |
3352 | ||
3353 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3354 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3355 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
3356 | dev_priv->irq_mask &= ~iir_mask; | |
3357 | ||
3358 | I915_WRITE(VLV_IIR, iir_mask); | |
3359 | I915_WRITE(VLV_IIR, iir_mask); | |
f8b79e58 | 3360 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); |
76e41860 VS |
3361 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
3362 | POSTING_READ(VLV_IMR); | |
f8b79e58 ID |
3363 | } |
3364 | ||
3365 | static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv) | |
3366 | { | |
3367 | u32 pipestat_mask; | |
3368 | u32 iir_mask; | |
3369 | ||
3370 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3371 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
6c7fba04 | 3372 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; |
f8b79e58 ID |
3373 | |
3374 | dev_priv->irq_mask |= iir_mask; | |
f8b79e58 | 3375 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
76e41860 | 3376 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); |
f8b79e58 ID |
3377 | I915_WRITE(VLV_IIR, iir_mask); |
3378 | I915_WRITE(VLV_IIR, iir_mask); | |
3379 | POSTING_READ(VLV_IIR); | |
3380 | ||
3381 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3382 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3383 | ||
3384 | i915_disable_pipestat(dev_priv, PIPE_A, pipestat_mask | | |
3385 | PIPE_GMBUS_INTERRUPT_STATUS); | |
3386 | i915_disable_pipestat(dev_priv, PIPE_B, pipestat_mask); | |
3387 | ||
3388 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | | |
3389 | PIPE_FIFO_UNDERRUN_STATUS; | |
3390 | I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask); | |
3391 | I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask); | |
3392 | POSTING_READ(PIPESTAT(PIPE_A)); | |
3393 | } | |
3394 | ||
3395 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) | |
3396 | { | |
3397 | assert_spin_locked(&dev_priv->irq_lock); | |
3398 | ||
3399 | if (dev_priv->display_irqs_enabled) | |
3400 | return; | |
3401 | ||
3402 | dev_priv->display_irqs_enabled = true; | |
3403 | ||
950eabaf | 3404 | if (intel_irqs_enabled(dev_priv)) |
f8b79e58 ID |
3405 | valleyview_display_irqs_install(dev_priv); |
3406 | } | |
3407 | ||
3408 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) | |
3409 | { | |
3410 | assert_spin_locked(&dev_priv->irq_lock); | |
3411 | ||
3412 | if (!dev_priv->display_irqs_enabled) | |
3413 | return; | |
3414 | ||
3415 | dev_priv->display_irqs_enabled = false; | |
3416 | ||
950eabaf | 3417 | if (intel_irqs_enabled(dev_priv)) |
f8b79e58 ID |
3418 | valleyview_display_irqs_uninstall(dev_priv); |
3419 | } | |
3420 | ||
7e231dbe JB |
3421 | static int valleyview_irq_postinstall(struct drm_device *dev) |
3422 | { | |
2d1013dd | 3423 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 3424 | |
f8b79e58 | 3425 | dev_priv->irq_mask = ~0; |
7e231dbe | 3426 | |
20afbda2 DV |
3427 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3428 | POSTING_READ(PORT_HOTPLUG_EN); | |
3429 | ||
7e231dbe | 3430 | I915_WRITE(VLV_IIR, 0xffffffff); |
76e41860 VS |
3431 | I915_WRITE(VLV_IIR, 0xffffffff); |
3432 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); | |
3433 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); | |
3434 | POSTING_READ(VLV_IMR); | |
7e231dbe | 3435 | |
b79480ba DV |
3436 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3437 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3438 | spin_lock_irq(&dev_priv->irq_lock); |
f8b79e58 ID |
3439 | if (dev_priv->display_irqs_enabled) |
3440 | valleyview_display_irqs_install(dev_priv); | |
d6207435 | 3441 | spin_unlock_irq(&dev_priv->irq_lock); |
31acc7f5 | 3442 | |
7e231dbe JB |
3443 | I915_WRITE(VLV_IIR, 0xffffffff); |
3444 | I915_WRITE(VLV_IIR, 0xffffffff); | |
3445 | ||
0a9a8c91 | 3446 | gen5_gt_irq_postinstall(dev); |
7e231dbe JB |
3447 | |
3448 | /* ack & enable invalid PTE error interrupts */ | |
3449 | #if 0 /* FIXME: add support to irq handler for checking these bits */ | |
3450 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); | |
3451 | I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); | |
3452 | #endif | |
3453 | ||
3454 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); | |
20afbda2 DV |
3455 | |
3456 | return 0; | |
3457 | } | |
3458 | ||
abd58f01 BW |
3459 | static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) |
3460 | { | |
abd58f01 BW |
3461 | /* These are interrupts we'll toggle with the ring mask register */ |
3462 | uint32_t gt_interrupts[] = { | |
3463 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | | |
73d477f6 | 3464 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT | |
abd58f01 | 3465 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT | |
73d477f6 OM |
3466 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT | |
3467 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT, | |
abd58f01 | 3468 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
73d477f6 OM |
3469 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
3470 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT | | |
3471 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT, | |
abd58f01 | 3472 | 0, |
73d477f6 OM |
3473 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
3474 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
abd58f01 BW |
3475 | }; |
3476 | ||
0961021a | 3477 | dev_priv->pm_irq_mask = 0xffffffff; |
9a2d2d87 D |
3478 | GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]); |
3479 | GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]); | |
3480 | GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, dev_priv->pm_rps_events); | |
3481 | GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]); | |
abd58f01 BW |
3482 | } |
3483 | ||
3484 | static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) | |
3485 | { | |
770de83d DL |
3486 | uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE; |
3487 | uint32_t de_pipe_enables; | |
abd58f01 | 3488 | int pipe; |
770de83d DL |
3489 | |
3490 | if (IS_GEN9(dev_priv)) | |
3491 | de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE | | |
3492 | GEN9_DE_PIPE_IRQ_FAULT_ERRORS; | |
3493 | else | |
3494 | de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE | | |
3495 | GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
3496 | ||
3497 | de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | | |
3498 | GEN8_PIPE_FIFO_UNDERRUN; | |
3499 | ||
13b3a0a7 DV |
3500 | dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; |
3501 | dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; | |
3502 | dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; | |
abd58f01 | 3503 | |
055e393f | 3504 | for_each_pipe(dev_priv, pipe) |
f458ebbc | 3505 | if (intel_display_power_is_enabled(dev_priv, |
813bde43 PZ |
3506 | POWER_DOMAIN_PIPE(pipe))) |
3507 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, | |
3508 | dev_priv->de_irq_mask[pipe], | |
3509 | de_pipe_enables); | |
abd58f01 | 3510 | |
35079899 | 3511 | GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A); |
abd58f01 BW |
3512 | } |
3513 | ||
3514 | static int gen8_irq_postinstall(struct drm_device *dev) | |
3515 | { | |
3516 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3517 | ||
622364b6 PZ |
3518 | ibx_irq_pre_postinstall(dev); |
3519 | ||
abd58f01 BW |
3520 | gen8_gt_irq_postinstall(dev_priv); |
3521 | gen8_de_irq_postinstall(dev_priv); | |
3522 | ||
3523 | ibx_irq_postinstall(dev); | |
3524 | ||
3525 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); | |
3526 | POSTING_READ(GEN8_MASTER_IRQ); | |
3527 | ||
3528 | return 0; | |
3529 | } | |
3530 | ||
43f328d7 VS |
3531 | static int cherryview_irq_postinstall(struct drm_device *dev) |
3532 | { | |
3533 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3534 | u32 enable_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3535 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
43f328d7 | 3536 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
3278f67f VS |
3537 | I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; |
3538 | u32 pipestat_enable = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3539 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
43f328d7 VS |
3540 | int pipe; |
3541 | ||
3542 | /* | |
3543 | * Leave vblank interrupts masked initially. enable/disable will | |
3544 | * toggle them based on usage. | |
3545 | */ | |
3278f67f | 3546 | dev_priv->irq_mask = ~enable_mask; |
43f328d7 | 3547 | |
055e393f | 3548 | for_each_pipe(dev_priv, pipe) |
43f328d7 VS |
3549 | I915_WRITE(PIPESTAT(pipe), 0xffff); |
3550 | ||
d6207435 | 3551 | spin_lock_irq(&dev_priv->irq_lock); |
3278f67f | 3552 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
055e393f | 3553 | for_each_pipe(dev_priv, pipe) |
43f328d7 | 3554 | i915_enable_pipestat(dev_priv, pipe, pipestat_enable); |
d6207435 | 3555 | spin_unlock_irq(&dev_priv->irq_lock); |
43f328d7 VS |
3556 | |
3557 | I915_WRITE(VLV_IIR, 0xffffffff); | |
76e41860 | 3558 | I915_WRITE(VLV_IIR, 0xffffffff); |
43f328d7 | 3559 | I915_WRITE(VLV_IER, enable_mask); |
76e41860 VS |
3560 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
3561 | POSTING_READ(VLV_IMR); | |
43f328d7 VS |
3562 | |
3563 | gen8_gt_irq_postinstall(dev_priv); | |
3564 | ||
3565 | I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE); | |
3566 | POSTING_READ(GEN8_MASTER_IRQ); | |
3567 | ||
3568 | return 0; | |
3569 | } | |
3570 | ||
abd58f01 BW |
3571 | static void gen8_irq_uninstall(struct drm_device *dev) |
3572 | { | |
3573 | struct drm_i915_private *dev_priv = dev->dev_private; | |
abd58f01 BW |
3574 | |
3575 | if (!dev_priv) | |
3576 | return; | |
3577 | ||
823f6b38 | 3578 | gen8_irq_reset(dev); |
abd58f01 BW |
3579 | } |
3580 | ||
7e231dbe JB |
3581 | static void valleyview_irq_uninstall(struct drm_device *dev) |
3582 | { | |
2d1013dd | 3583 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
3584 | int pipe; |
3585 | ||
3586 | if (!dev_priv) | |
3587 | return; | |
3588 | ||
843d0e7d ID |
3589 | I915_WRITE(VLV_MASTER_IER, 0); |
3590 | ||
893fce8e VS |
3591 | gen5_gt_irq_reset(dev); |
3592 | ||
055e393f | 3593 | for_each_pipe(dev_priv, pipe) |
7e231dbe JB |
3594 | I915_WRITE(PIPESTAT(pipe), 0xffff); |
3595 | ||
3596 | I915_WRITE(HWSTAM, 0xffffffff); | |
3597 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3598 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
f8b79e58 | 3599 | |
d6207435 DV |
3600 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3601 | * just to make the assert_spin_locked check happy. */ | |
3602 | spin_lock_irq(&dev_priv->irq_lock); | |
f8b79e58 ID |
3603 | if (dev_priv->display_irqs_enabled) |
3604 | valleyview_display_irqs_uninstall(dev_priv); | |
d6207435 | 3605 | spin_unlock_irq(&dev_priv->irq_lock); |
f8b79e58 ID |
3606 | |
3607 | dev_priv->irq_mask = 0; | |
3608 | ||
23a09c76 | 3609 | GEN5_IRQ_RESET(VLV_); |
7e231dbe JB |
3610 | } |
3611 | ||
43f328d7 VS |
3612 | static void cherryview_irq_uninstall(struct drm_device *dev) |
3613 | { | |
3614 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3615 | int pipe; | |
3616 | ||
3617 | if (!dev_priv) | |
3618 | return; | |
3619 | ||
3620 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3621 | POSTING_READ(GEN8_MASTER_IRQ); | |
3622 | ||
a2c30fba | 3623 | gen8_gt_irq_reset(dev_priv); |
43f328d7 | 3624 | |
a2c30fba | 3625 | GEN5_IRQ_RESET(GEN8_PCU_); |
43f328d7 VS |
3626 | |
3627 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3628 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3629 | ||
055e393f | 3630 | for_each_pipe(dev_priv, pipe) |
43f328d7 VS |
3631 | I915_WRITE(PIPESTAT(pipe), 0xffff); |
3632 | ||
23a09c76 | 3633 | GEN5_IRQ_RESET(VLV_); |
43f328d7 VS |
3634 | } |
3635 | ||
f71d4af4 | 3636 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d | 3637 | { |
2d1013dd | 3638 | struct drm_i915_private *dev_priv = dev->dev_private; |
4697995b JB |
3639 | |
3640 | if (!dev_priv) | |
3641 | return; | |
3642 | ||
be30b29f | 3643 | ironlake_irq_reset(dev); |
036a4a7d ZW |
3644 | } |
3645 | ||
a266c7d5 | 3646 | static void i8xx_irq_preinstall(struct drm_device * dev) |
1da177e4 | 3647 | { |
2d1013dd | 3648 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 3649 | int pipe; |
91e3738e | 3650 | |
055e393f | 3651 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 | 3652 | I915_WRITE(PIPESTAT(pipe), 0); |
a266c7d5 CW |
3653 | I915_WRITE16(IMR, 0xffff); |
3654 | I915_WRITE16(IER, 0x0); | |
3655 | POSTING_READ16(IER); | |
c2798b19 CW |
3656 | } |
3657 | ||
3658 | static int i8xx_irq_postinstall(struct drm_device *dev) | |
3659 | { | |
2d1013dd | 3660 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 | 3661 | |
c2798b19 CW |
3662 | I915_WRITE16(EMR, |
3663 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); | |
3664 | ||
3665 | /* Unmask the interrupts that we always want on. */ | |
3666 | dev_priv->irq_mask = | |
3667 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3668 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3669 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3670 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3671 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3672 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
3673 | ||
3674 | I915_WRITE16(IER, | |
3675 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3676 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3677 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
3678 | I915_USER_INTERRUPT); | |
3679 | POSTING_READ16(IER); | |
3680 | ||
379ef82d DV |
3681 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3682 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3683 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
3684 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3685 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 3686 | spin_unlock_irq(&dev_priv->irq_lock); |
379ef82d | 3687 | |
c2798b19 CW |
3688 | return 0; |
3689 | } | |
3690 | ||
90a72f87 VS |
3691 | /* |
3692 | * Returns true when a page flip has completed. | |
3693 | */ | |
3694 | static bool i8xx_handle_vblank(struct drm_device *dev, | |
1f1c2e24 | 3695 | int plane, int pipe, u32 iir) |
90a72f87 | 3696 | { |
2d1013dd | 3697 | struct drm_i915_private *dev_priv = dev->dev_private; |
1f1c2e24 | 3698 | u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
90a72f87 | 3699 | |
8d7849db | 3700 | if (!intel_pipe_handle_vblank(dev, pipe)) |
90a72f87 VS |
3701 | return false; |
3702 | ||
3703 | if ((iir & flip_pending) == 0) | |
d6bbafa1 | 3704 | goto check_page_flip; |
90a72f87 | 3705 | |
1f1c2e24 | 3706 | intel_prepare_page_flip(dev, plane); |
90a72f87 VS |
3707 | |
3708 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
3709 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3710 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3711 | * the flip is completed (no longer pending). Since this doesn't raise | |
3712 | * an interrupt per se, we watch for the change at vblank. | |
3713 | */ | |
3714 | if (I915_READ16(ISR) & flip_pending) | |
d6bbafa1 | 3715 | goto check_page_flip; |
90a72f87 VS |
3716 | |
3717 | intel_finish_page_flip(dev, pipe); | |
90a72f87 | 3718 | return true; |
d6bbafa1 CW |
3719 | |
3720 | check_page_flip: | |
3721 | intel_check_page_flip(dev, pipe); | |
3722 | return false; | |
90a72f87 VS |
3723 | } |
3724 | ||
ff1f525e | 3725 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
c2798b19 | 3726 | { |
45a83f84 | 3727 | struct drm_device *dev = arg; |
2d1013dd | 3728 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
3729 | u16 iir, new_iir; |
3730 | u32 pipe_stats[2]; | |
c2798b19 CW |
3731 | int pipe; |
3732 | u16 flip_mask = | |
3733 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3734 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
3735 | ||
c2798b19 CW |
3736 | iir = I915_READ16(IIR); |
3737 | if (iir == 0) | |
3738 | return IRQ_NONE; | |
3739 | ||
3740 | while (iir & ~flip_mask) { | |
3741 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3742 | * have been cleared after the pipestat interrupt was received. | |
3743 | * It doesn't set the bit in iir again, but it still produces | |
3744 | * interrupts (for non-MSI). | |
3745 | */ | |
222c7f51 | 3746 | spin_lock(&dev_priv->irq_lock); |
c2798b19 | 3747 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
58174462 MK |
3748 | i915_handle_error(dev, false, |
3749 | "Command parser error, iir 0x%08x", | |
3750 | iir); | |
c2798b19 | 3751 | |
055e393f | 3752 | for_each_pipe(dev_priv, pipe) { |
c2798b19 CW |
3753 | int reg = PIPESTAT(pipe); |
3754 | pipe_stats[pipe] = I915_READ(reg); | |
3755 | ||
3756 | /* | |
3757 | * Clear the PIPE*STAT regs before the IIR | |
3758 | */ | |
2d9d2b0b | 3759 | if (pipe_stats[pipe] & 0x8000ffff) |
c2798b19 | 3760 | I915_WRITE(reg, pipe_stats[pipe]); |
c2798b19 | 3761 | } |
222c7f51 | 3762 | spin_unlock(&dev_priv->irq_lock); |
c2798b19 CW |
3763 | |
3764 | I915_WRITE16(IIR, iir & ~flip_mask); | |
3765 | new_iir = I915_READ16(IIR); /* Flush posted writes */ | |
3766 | ||
d05c617e | 3767 | i915_update_dri1_breadcrumb(dev); |
c2798b19 CW |
3768 | |
3769 | if (iir & I915_USER_INTERRUPT) | |
3770 | notify_ring(dev, &dev_priv->ring[RCS]); | |
3771 | ||
055e393f | 3772 | for_each_pipe(dev_priv, pipe) { |
1f1c2e24 | 3773 | int plane = pipe; |
3a77c4c4 | 3774 | if (HAS_FBC(dev)) |
1f1c2e24 VS |
3775 | plane = !plane; |
3776 | ||
4356d586 | 3777 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
1f1c2e24 VS |
3778 | i8xx_handle_vblank(dev, plane, pipe, iir)) |
3779 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
c2798b19 | 3780 | |
4356d586 | 3781 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
277de95e | 3782 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b | 3783 | |
1f7247c0 DV |
3784 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
3785 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
3786 | pipe); | |
4356d586 | 3787 | } |
c2798b19 CW |
3788 | |
3789 | iir = new_iir; | |
3790 | } | |
3791 | ||
3792 | return IRQ_HANDLED; | |
3793 | } | |
3794 | ||
3795 | static void i8xx_irq_uninstall(struct drm_device * dev) | |
3796 | { | |
2d1013dd | 3797 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
3798 | int pipe; |
3799 | ||
055e393f | 3800 | for_each_pipe(dev_priv, pipe) { |
c2798b19 CW |
3801 | /* Clear enable bits; then clear status bits */ |
3802 | I915_WRITE(PIPESTAT(pipe), 0); | |
3803 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); | |
3804 | } | |
3805 | I915_WRITE16(IMR, 0xffff); | |
3806 | I915_WRITE16(IER, 0x0); | |
3807 | I915_WRITE16(IIR, I915_READ16(IIR)); | |
3808 | } | |
3809 | ||
a266c7d5 CW |
3810 | static void i915_irq_preinstall(struct drm_device * dev) |
3811 | { | |
2d1013dd | 3812 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3813 | int pipe; |
3814 | ||
a266c7d5 CW |
3815 | if (I915_HAS_HOTPLUG(dev)) { |
3816 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3817 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3818 | } | |
3819 | ||
00d98ebd | 3820 | I915_WRITE16(HWSTAM, 0xeffe); |
055e393f | 3821 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
3822 | I915_WRITE(PIPESTAT(pipe), 0); |
3823 | I915_WRITE(IMR, 0xffffffff); | |
3824 | I915_WRITE(IER, 0x0); | |
3825 | POSTING_READ(IER); | |
3826 | } | |
3827 | ||
3828 | static int i915_irq_postinstall(struct drm_device *dev) | |
3829 | { | |
2d1013dd | 3830 | struct drm_i915_private *dev_priv = dev->dev_private; |
38bde180 | 3831 | u32 enable_mask; |
a266c7d5 | 3832 | |
38bde180 CW |
3833 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
3834 | ||
3835 | /* Unmask the interrupts that we always want on. */ | |
3836 | dev_priv->irq_mask = | |
3837 | ~(I915_ASLE_INTERRUPT | | |
3838 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3839 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3840 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3841 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3842 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3843 | ||
3844 | enable_mask = | |
3845 | I915_ASLE_INTERRUPT | | |
3846 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3847 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3848 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
3849 | I915_USER_INTERRUPT; | |
3850 | ||
a266c7d5 | 3851 | if (I915_HAS_HOTPLUG(dev)) { |
20afbda2 DV |
3852 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3853 | POSTING_READ(PORT_HOTPLUG_EN); | |
3854 | ||
a266c7d5 CW |
3855 | /* Enable in IER... */ |
3856 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
3857 | /* and unmask in IMR */ | |
3858 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; | |
3859 | } | |
3860 | ||
a266c7d5 CW |
3861 | I915_WRITE(IMR, dev_priv->irq_mask); |
3862 | I915_WRITE(IER, enable_mask); | |
3863 | POSTING_READ(IER); | |
3864 | ||
f49e38dd | 3865 | i915_enable_asle_pipestat(dev); |
20afbda2 | 3866 | |
379ef82d DV |
3867 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3868 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3869 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
3870 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3871 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 3872 | spin_unlock_irq(&dev_priv->irq_lock); |
379ef82d | 3873 | |
20afbda2 DV |
3874 | return 0; |
3875 | } | |
3876 | ||
90a72f87 VS |
3877 | /* |
3878 | * Returns true when a page flip has completed. | |
3879 | */ | |
3880 | static bool i915_handle_vblank(struct drm_device *dev, | |
3881 | int plane, int pipe, u32 iir) | |
3882 | { | |
2d1013dd | 3883 | struct drm_i915_private *dev_priv = dev->dev_private; |
90a72f87 VS |
3884 | u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
3885 | ||
8d7849db | 3886 | if (!intel_pipe_handle_vblank(dev, pipe)) |
90a72f87 VS |
3887 | return false; |
3888 | ||
3889 | if ((iir & flip_pending) == 0) | |
d6bbafa1 | 3890 | goto check_page_flip; |
90a72f87 VS |
3891 | |
3892 | intel_prepare_page_flip(dev, plane); | |
3893 | ||
3894 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
3895 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3896 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3897 | * the flip is completed (no longer pending). Since this doesn't raise | |
3898 | * an interrupt per se, we watch for the change at vblank. | |
3899 | */ | |
3900 | if (I915_READ(ISR) & flip_pending) | |
d6bbafa1 | 3901 | goto check_page_flip; |
90a72f87 VS |
3902 | |
3903 | intel_finish_page_flip(dev, pipe); | |
90a72f87 | 3904 | return true; |
d6bbafa1 CW |
3905 | |
3906 | check_page_flip: | |
3907 | intel_check_page_flip(dev, pipe); | |
3908 | return false; | |
90a72f87 VS |
3909 | } |
3910 | ||
ff1f525e | 3911 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
a266c7d5 | 3912 | { |
45a83f84 | 3913 | struct drm_device *dev = arg; |
2d1013dd | 3914 | struct drm_i915_private *dev_priv = dev->dev_private; |
8291ee90 | 3915 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
38bde180 CW |
3916 | u32 flip_mask = |
3917 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3918 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
38bde180 | 3919 | int pipe, ret = IRQ_NONE; |
a266c7d5 | 3920 | |
a266c7d5 | 3921 | iir = I915_READ(IIR); |
38bde180 CW |
3922 | do { |
3923 | bool irq_received = (iir & ~flip_mask) != 0; | |
8291ee90 | 3924 | bool blc_event = false; |
a266c7d5 CW |
3925 | |
3926 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3927 | * have been cleared after the pipestat interrupt was received. | |
3928 | * It doesn't set the bit in iir again, but it still produces | |
3929 | * interrupts (for non-MSI). | |
3930 | */ | |
222c7f51 | 3931 | spin_lock(&dev_priv->irq_lock); |
a266c7d5 | 3932 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
58174462 MK |
3933 | i915_handle_error(dev, false, |
3934 | "Command parser error, iir 0x%08x", | |
3935 | iir); | |
a266c7d5 | 3936 | |
055e393f | 3937 | for_each_pipe(dev_priv, pipe) { |
a266c7d5 CW |
3938 | int reg = PIPESTAT(pipe); |
3939 | pipe_stats[pipe] = I915_READ(reg); | |
3940 | ||
38bde180 | 3941 | /* Clear the PIPE*STAT regs before the IIR */ |
a266c7d5 | 3942 | if (pipe_stats[pipe] & 0x8000ffff) { |
a266c7d5 | 3943 | I915_WRITE(reg, pipe_stats[pipe]); |
38bde180 | 3944 | irq_received = true; |
a266c7d5 CW |
3945 | } |
3946 | } | |
222c7f51 | 3947 | spin_unlock(&dev_priv->irq_lock); |
a266c7d5 CW |
3948 | |
3949 | if (!irq_received) | |
3950 | break; | |
3951 | ||
a266c7d5 | 3952 | /* Consume port. Then clear IIR or we'll miss events */ |
16c6c56b VS |
3953 | if (I915_HAS_HOTPLUG(dev) && |
3954 | iir & I915_DISPLAY_PORT_INTERRUPT) | |
3955 | i9xx_hpd_irq_handler(dev); | |
a266c7d5 | 3956 | |
38bde180 | 3957 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
3958 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
3959 | ||
a266c7d5 CW |
3960 | if (iir & I915_USER_INTERRUPT) |
3961 | notify_ring(dev, &dev_priv->ring[RCS]); | |
a266c7d5 | 3962 | |
055e393f | 3963 | for_each_pipe(dev_priv, pipe) { |
38bde180 | 3964 | int plane = pipe; |
3a77c4c4 | 3965 | if (HAS_FBC(dev)) |
38bde180 | 3966 | plane = !plane; |
90a72f87 | 3967 | |
8291ee90 | 3968 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
3969 | i915_handle_vblank(dev, plane, pipe, iir)) |
3970 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
a266c7d5 CW |
3971 | |
3972 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
3973 | blc_event = true; | |
4356d586 DV |
3974 | |
3975 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 3976 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b | 3977 | |
1f7247c0 DV |
3978 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
3979 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
3980 | pipe); | |
a266c7d5 CW |
3981 | } |
3982 | ||
a266c7d5 CW |
3983 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
3984 | intel_opregion_asle_intr(dev); | |
3985 | ||
3986 | /* With MSI, interrupts are only generated when iir | |
3987 | * transitions from zero to nonzero. If another bit got | |
3988 | * set while we were handling the existing iir bits, then | |
3989 | * we would never get another interrupt. | |
3990 | * | |
3991 | * This is fine on non-MSI as well, as if we hit this path | |
3992 | * we avoid exiting the interrupt handler only to generate | |
3993 | * another one. | |
3994 | * | |
3995 | * Note that for MSI this could cause a stray interrupt report | |
3996 | * if an interrupt landed in the time between writing IIR and | |
3997 | * the posting read. This should be rare enough to never | |
3998 | * trigger the 99% of 100,000 interrupts test for disabling | |
3999 | * stray interrupts. | |
4000 | */ | |
38bde180 | 4001 | ret = IRQ_HANDLED; |
a266c7d5 | 4002 | iir = new_iir; |
38bde180 | 4003 | } while (iir & ~flip_mask); |
a266c7d5 | 4004 | |
d05c617e | 4005 | i915_update_dri1_breadcrumb(dev); |
8291ee90 | 4006 | |
a266c7d5 CW |
4007 | return ret; |
4008 | } | |
4009 | ||
4010 | static void i915_irq_uninstall(struct drm_device * dev) | |
4011 | { | |
2d1013dd | 4012 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4013 | int pipe; |
4014 | ||
a266c7d5 CW |
4015 | if (I915_HAS_HOTPLUG(dev)) { |
4016 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
4017 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
4018 | } | |
4019 | ||
00d98ebd | 4020 | I915_WRITE16(HWSTAM, 0xffff); |
055e393f | 4021 | for_each_pipe(dev_priv, pipe) { |
55b39755 | 4022 | /* Clear enable bits; then clear status bits */ |
a266c7d5 | 4023 | I915_WRITE(PIPESTAT(pipe), 0); |
55b39755 CW |
4024 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
4025 | } | |
a266c7d5 CW |
4026 | I915_WRITE(IMR, 0xffffffff); |
4027 | I915_WRITE(IER, 0x0); | |
4028 | ||
a266c7d5 CW |
4029 | I915_WRITE(IIR, I915_READ(IIR)); |
4030 | } | |
4031 | ||
4032 | static void i965_irq_preinstall(struct drm_device * dev) | |
4033 | { | |
2d1013dd | 4034 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4035 | int pipe; |
4036 | ||
adca4730 CW |
4037 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
4038 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
4039 | |
4040 | I915_WRITE(HWSTAM, 0xeffe); | |
055e393f | 4041 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4042 | I915_WRITE(PIPESTAT(pipe), 0); |
4043 | I915_WRITE(IMR, 0xffffffff); | |
4044 | I915_WRITE(IER, 0x0); | |
4045 | POSTING_READ(IER); | |
4046 | } | |
4047 | ||
4048 | static int i965_irq_postinstall(struct drm_device *dev) | |
4049 | { | |
2d1013dd | 4050 | struct drm_i915_private *dev_priv = dev->dev_private; |
bbba0a97 | 4051 | u32 enable_mask; |
a266c7d5 CW |
4052 | u32 error_mask; |
4053 | ||
a266c7d5 | 4054 | /* Unmask the interrupts that we always want on. */ |
bbba0a97 | 4055 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
adca4730 | 4056 | I915_DISPLAY_PORT_INTERRUPT | |
bbba0a97 CW |
4057 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
4058 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
4059 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4060 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
4061 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
4062 | ||
4063 | enable_mask = ~dev_priv->irq_mask; | |
21ad8330 VS |
4064 | enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
4065 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); | |
bbba0a97 CW |
4066 | enable_mask |= I915_USER_INTERRUPT; |
4067 | ||
4068 | if (IS_G4X(dev)) | |
4069 | enable_mask |= I915_BSD_USER_INTERRUPT; | |
a266c7d5 | 4070 | |
b79480ba DV |
4071 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
4072 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 4073 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
4074 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
4075 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
4076 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 4077 | spin_unlock_irq(&dev_priv->irq_lock); |
a266c7d5 | 4078 | |
a266c7d5 CW |
4079 | /* |
4080 | * Enable some error detection, note the instruction error mask | |
4081 | * bit is reserved, so we leave it masked. | |
4082 | */ | |
4083 | if (IS_G4X(dev)) { | |
4084 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
4085 | GM45_ERROR_MEM_PRIV | | |
4086 | GM45_ERROR_CP_PRIV | | |
4087 | I915_ERROR_MEMORY_REFRESH); | |
4088 | } else { | |
4089 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
4090 | I915_ERROR_MEMORY_REFRESH); | |
4091 | } | |
4092 | I915_WRITE(EMR, error_mask); | |
4093 | ||
4094 | I915_WRITE(IMR, dev_priv->irq_mask); | |
4095 | I915_WRITE(IER, enable_mask); | |
4096 | POSTING_READ(IER); | |
4097 | ||
20afbda2 DV |
4098 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
4099 | POSTING_READ(PORT_HOTPLUG_EN); | |
4100 | ||
f49e38dd | 4101 | i915_enable_asle_pipestat(dev); |
20afbda2 DV |
4102 | |
4103 | return 0; | |
4104 | } | |
4105 | ||
bac56d5b | 4106 | static void i915_hpd_irq_setup(struct drm_device *dev) |
20afbda2 | 4107 | { |
2d1013dd | 4108 | struct drm_i915_private *dev_priv = dev->dev_private; |
cd569aed | 4109 | struct intel_encoder *intel_encoder; |
20afbda2 DV |
4110 | u32 hotplug_en; |
4111 | ||
b5ea2d56 DV |
4112 | assert_spin_locked(&dev_priv->irq_lock); |
4113 | ||
bac56d5b EE |
4114 | if (I915_HAS_HOTPLUG(dev)) { |
4115 | hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
4116 | hotplug_en &= ~HOTPLUG_INT_EN_MASK; | |
4117 | /* Note HDMI and DP share hotplug bits */ | |
e5868a31 | 4118 | /* enable bits are the same for all generations */ |
b2784e15 | 4119 | for_each_intel_encoder(dev, intel_encoder) |
cd569aed EE |
4120 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
4121 | hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin]; | |
bac56d5b EE |
4122 | /* Programming the CRT detection parameters tends |
4123 | to generate a spurious hotplug event about three | |
4124 | seconds later. So just do it once. | |
4125 | */ | |
4126 | if (IS_G4X(dev)) | |
4127 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
85fc95ba | 4128 | hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK; |
bac56d5b | 4129 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
a266c7d5 | 4130 | |
bac56d5b EE |
4131 | /* Ignore TV since it's buggy */ |
4132 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
4133 | } | |
a266c7d5 CW |
4134 | } |
4135 | ||
ff1f525e | 4136 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
a266c7d5 | 4137 | { |
45a83f84 | 4138 | struct drm_device *dev = arg; |
2d1013dd | 4139 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4140 | u32 iir, new_iir; |
4141 | u32 pipe_stats[I915_MAX_PIPES]; | |
a266c7d5 | 4142 | int ret = IRQ_NONE, pipe; |
21ad8330 VS |
4143 | u32 flip_mask = |
4144 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4145 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
a266c7d5 | 4146 | |
a266c7d5 CW |
4147 | iir = I915_READ(IIR); |
4148 | ||
a266c7d5 | 4149 | for (;;) { |
501e01d7 | 4150 | bool irq_received = (iir & ~flip_mask) != 0; |
2c8ba29f CW |
4151 | bool blc_event = false; |
4152 | ||
a266c7d5 CW |
4153 | /* Can't rely on pipestat interrupt bit in iir as it might |
4154 | * have been cleared after the pipestat interrupt was received. | |
4155 | * It doesn't set the bit in iir again, but it still produces | |
4156 | * interrupts (for non-MSI). | |
4157 | */ | |
222c7f51 | 4158 | spin_lock(&dev_priv->irq_lock); |
a266c7d5 | 4159 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
58174462 MK |
4160 | i915_handle_error(dev, false, |
4161 | "Command parser error, iir 0x%08x", | |
4162 | iir); | |
a266c7d5 | 4163 | |
055e393f | 4164 | for_each_pipe(dev_priv, pipe) { |
a266c7d5 CW |
4165 | int reg = PIPESTAT(pipe); |
4166 | pipe_stats[pipe] = I915_READ(reg); | |
4167 | ||
4168 | /* | |
4169 | * Clear the PIPE*STAT regs before the IIR | |
4170 | */ | |
4171 | if (pipe_stats[pipe] & 0x8000ffff) { | |
a266c7d5 | 4172 | I915_WRITE(reg, pipe_stats[pipe]); |
501e01d7 | 4173 | irq_received = true; |
a266c7d5 CW |
4174 | } |
4175 | } | |
222c7f51 | 4176 | spin_unlock(&dev_priv->irq_lock); |
a266c7d5 CW |
4177 | |
4178 | if (!irq_received) | |
4179 | break; | |
4180 | ||
4181 | ret = IRQ_HANDLED; | |
4182 | ||
4183 | /* Consume port. Then clear IIR or we'll miss events */ | |
16c6c56b VS |
4184 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
4185 | i9xx_hpd_irq_handler(dev); | |
a266c7d5 | 4186 | |
21ad8330 | 4187 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
4188 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
4189 | ||
a266c7d5 CW |
4190 | if (iir & I915_USER_INTERRUPT) |
4191 | notify_ring(dev, &dev_priv->ring[RCS]); | |
4192 | if (iir & I915_BSD_USER_INTERRUPT) | |
4193 | notify_ring(dev, &dev_priv->ring[VCS]); | |
4194 | ||
055e393f | 4195 | for_each_pipe(dev_priv, pipe) { |
2c8ba29f | 4196 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
4197 | i915_handle_vblank(dev, pipe, pipe, iir)) |
4198 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); | |
a266c7d5 CW |
4199 | |
4200 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
4201 | blc_event = true; | |
4356d586 DV |
4202 | |
4203 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 4204 | i9xx_pipe_crc_irq_handler(dev, pipe); |
a266c7d5 | 4205 | |
1f7247c0 DV |
4206 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
4207 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
2d9d2b0b | 4208 | } |
a266c7d5 CW |
4209 | |
4210 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | |
4211 | intel_opregion_asle_intr(dev); | |
4212 | ||
515ac2bb DV |
4213 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
4214 | gmbus_irq_handler(dev); | |
4215 | ||
a266c7d5 CW |
4216 | /* With MSI, interrupts are only generated when iir |
4217 | * transitions from zero to nonzero. If another bit got | |
4218 | * set while we were handling the existing iir bits, then | |
4219 | * we would never get another interrupt. | |
4220 | * | |
4221 | * This is fine on non-MSI as well, as if we hit this path | |
4222 | * we avoid exiting the interrupt handler only to generate | |
4223 | * another one. | |
4224 | * | |
4225 | * Note that for MSI this could cause a stray interrupt report | |
4226 | * if an interrupt landed in the time between writing IIR and | |
4227 | * the posting read. This should be rare enough to never | |
4228 | * trigger the 99% of 100,000 interrupts test for disabling | |
4229 | * stray interrupts. | |
4230 | */ | |
4231 | iir = new_iir; | |
4232 | } | |
4233 | ||
d05c617e | 4234 | i915_update_dri1_breadcrumb(dev); |
2c8ba29f | 4235 | |
a266c7d5 CW |
4236 | return ret; |
4237 | } | |
4238 | ||
4239 | static void i965_irq_uninstall(struct drm_device * dev) | |
4240 | { | |
2d1013dd | 4241 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4242 | int pipe; |
4243 | ||
4244 | if (!dev_priv) | |
4245 | return; | |
4246 | ||
adca4730 CW |
4247 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
4248 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
4249 | |
4250 | I915_WRITE(HWSTAM, 0xffffffff); | |
055e393f | 4251 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4252 | I915_WRITE(PIPESTAT(pipe), 0); |
4253 | I915_WRITE(IMR, 0xffffffff); | |
4254 | I915_WRITE(IER, 0x0); | |
4255 | ||
055e393f | 4256 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4257 | I915_WRITE(PIPESTAT(pipe), |
4258 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); | |
4259 | I915_WRITE(IIR, I915_READ(IIR)); | |
4260 | } | |
4261 | ||
4cb21832 | 4262 | static void intel_hpd_irq_reenable_work(struct work_struct *work) |
ac4c16c5 | 4263 | { |
6323751d ID |
4264 | struct drm_i915_private *dev_priv = |
4265 | container_of(work, typeof(*dev_priv), | |
4266 | hotplug_reenable_work.work); | |
ac4c16c5 EE |
4267 | struct drm_device *dev = dev_priv->dev; |
4268 | struct drm_mode_config *mode_config = &dev->mode_config; | |
ac4c16c5 EE |
4269 | int i; |
4270 | ||
6323751d ID |
4271 | intel_runtime_pm_get(dev_priv); |
4272 | ||
4cb21832 | 4273 | spin_lock_irq(&dev_priv->irq_lock); |
ac4c16c5 EE |
4274 | for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) { |
4275 | struct drm_connector *connector; | |
4276 | ||
4277 | if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED) | |
4278 | continue; | |
4279 | ||
4280 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
4281 | ||
4282 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
4283 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4284 | ||
4285 | if (intel_connector->encoder->hpd_pin == i) { | |
4286 | if (connector->polled != intel_connector->polled) | |
4287 | DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n", | |
c23cc417 | 4288 | connector->name); |
ac4c16c5 EE |
4289 | connector->polled = intel_connector->polled; |
4290 | if (!connector->polled) | |
4291 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
4292 | } | |
4293 | } | |
4294 | } | |
4295 | if (dev_priv->display.hpd_irq_setup) | |
4296 | dev_priv->display.hpd_irq_setup(dev); | |
4cb21832 | 4297 | spin_unlock_irq(&dev_priv->irq_lock); |
6323751d ID |
4298 | |
4299 | intel_runtime_pm_put(dev_priv); | |
ac4c16c5 EE |
4300 | } |
4301 | ||
fca52a55 DV |
4302 | /** |
4303 | * intel_irq_init - initializes irq support | |
4304 | * @dev_priv: i915 device instance | |
4305 | * | |
4306 | * This function initializes all the irq support including work items, timers | |
4307 | * and all the vtables. It does not setup the interrupt itself though. | |
4308 | */ | |
b963291c | 4309 | void intel_irq_init(struct drm_i915_private *dev_priv) |
f71d4af4 | 4310 | { |
b963291c | 4311 | struct drm_device *dev = dev_priv->dev; |
8b2e326d CW |
4312 | |
4313 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); | |
13cf5504 | 4314 | INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func); |
99584db3 | 4315 | INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func); |
c6a828d3 | 4316 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
a4da4fa4 | 4317 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
8b2e326d | 4318 | |
a6706b45 | 4319 | /* Let's track the enabled rps events */ |
b963291c | 4320 | if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) |
6c65a587 | 4321 | /* WaGsvRC0ResidencyMethod:vlv */ |
31685c25 D |
4322 | dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED; |
4323 | else | |
4324 | dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; | |
a6706b45 | 4325 | |
99584db3 DV |
4326 | setup_timer(&dev_priv->gpu_error.hangcheck_timer, |
4327 | i915_hangcheck_elapsed, | |
61bac78e | 4328 | (unsigned long) dev); |
6323751d | 4329 | INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work, |
4cb21832 | 4330 | intel_hpd_irq_reenable_work); |
61bac78e | 4331 | |
97a19a24 | 4332 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); |
9ee32fea | 4333 | |
b963291c | 4334 | if (IS_GEN2(dev_priv)) { |
4cdb83ec VS |
4335 | dev->max_vblank_count = 0; |
4336 | dev->driver->get_vblank_counter = i8xx_get_vblank_counter; | |
b963291c | 4337 | } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { |
f71d4af4 JB |
4338 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
4339 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; | |
391f75e2 VS |
4340 | } else { |
4341 | dev->driver->get_vblank_counter = i915_get_vblank_counter; | |
4342 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
f71d4af4 JB |
4343 | } |
4344 | ||
21da2700 VS |
4345 | /* |
4346 | * Opt out of the vblank disable timer on everything except gen2. | |
4347 | * Gen2 doesn't have a hardware frame counter and so depends on | |
4348 | * vblank interrupts to produce sane vblank seuquence numbers. | |
4349 | */ | |
b963291c | 4350 | if (!IS_GEN2(dev_priv)) |
21da2700 VS |
4351 | dev->vblank_disable_immediate = true; |
4352 | ||
c2baf4b7 | 4353 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
c3613de9 | 4354 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; |
c2baf4b7 VS |
4355 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; |
4356 | } | |
f71d4af4 | 4357 | |
b963291c | 4358 | if (IS_CHERRYVIEW(dev_priv)) { |
43f328d7 VS |
4359 | dev->driver->irq_handler = cherryview_irq_handler; |
4360 | dev->driver->irq_preinstall = cherryview_irq_preinstall; | |
4361 | dev->driver->irq_postinstall = cherryview_irq_postinstall; | |
4362 | dev->driver->irq_uninstall = cherryview_irq_uninstall; | |
4363 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4364 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
4365 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; | |
b963291c | 4366 | } else if (IS_VALLEYVIEW(dev_priv)) { |
7e231dbe JB |
4367 | dev->driver->irq_handler = valleyview_irq_handler; |
4368 | dev->driver->irq_preinstall = valleyview_irq_preinstall; | |
4369 | dev->driver->irq_postinstall = valleyview_irq_postinstall; | |
4370 | dev->driver->irq_uninstall = valleyview_irq_uninstall; | |
4371 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4372 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
fa00abe0 | 4373 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
b963291c | 4374 | } else if (INTEL_INFO(dev_priv)->gen >= 8) { |
abd58f01 | 4375 | dev->driver->irq_handler = gen8_irq_handler; |
723761b8 | 4376 | dev->driver->irq_preinstall = gen8_irq_reset; |
abd58f01 BW |
4377 | dev->driver->irq_postinstall = gen8_irq_postinstall; |
4378 | dev->driver->irq_uninstall = gen8_irq_uninstall; | |
4379 | dev->driver->enable_vblank = gen8_enable_vblank; | |
4380 | dev->driver->disable_vblank = gen8_disable_vblank; | |
4381 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; | |
f71d4af4 JB |
4382 | } else if (HAS_PCH_SPLIT(dev)) { |
4383 | dev->driver->irq_handler = ironlake_irq_handler; | |
723761b8 | 4384 | dev->driver->irq_preinstall = ironlake_irq_reset; |
f71d4af4 JB |
4385 | dev->driver->irq_postinstall = ironlake_irq_postinstall; |
4386 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
4387 | dev->driver->enable_vblank = ironlake_enable_vblank; | |
4388 | dev->driver->disable_vblank = ironlake_disable_vblank; | |
82a28bcf | 4389 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; |
f71d4af4 | 4390 | } else { |
b963291c | 4391 | if (INTEL_INFO(dev_priv)->gen == 2) { |
c2798b19 CW |
4392 | dev->driver->irq_preinstall = i8xx_irq_preinstall; |
4393 | dev->driver->irq_postinstall = i8xx_irq_postinstall; | |
4394 | dev->driver->irq_handler = i8xx_irq_handler; | |
4395 | dev->driver->irq_uninstall = i8xx_irq_uninstall; | |
b963291c | 4396 | } else if (INTEL_INFO(dev_priv)->gen == 3) { |
a266c7d5 CW |
4397 | dev->driver->irq_preinstall = i915_irq_preinstall; |
4398 | dev->driver->irq_postinstall = i915_irq_postinstall; | |
4399 | dev->driver->irq_uninstall = i915_irq_uninstall; | |
4400 | dev->driver->irq_handler = i915_irq_handler; | |
20afbda2 | 4401 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
c2798b19 | 4402 | } else { |
a266c7d5 CW |
4403 | dev->driver->irq_preinstall = i965_irq_preinstall; |
4404 | dev->driver->irq_postinstall = i965_irq_postinstall; | |
4405 | dev->driver->irq_uninstall = i965_irq_uninstall; | |
4406 | dev->driver->irq_handler = i965_irq_handler; | |
bac56d5b | 4407 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
c2798b19 | 4408 | } |
f71d4af4 JB |
4409 | dev->driver->enable_vblank = i915_enable_vblank; |
4410 | dev->driver->disable_vblank = i915_disable_vblank; | |
4411 | } | |
4412 | } | |
20afbda2 | 4413 | |
fca52a55 DV |
4414 | /** |
4415 | * intel_hpd_init - initializes and enables hpd support | |
4416 | * @dev_priv: i915 device instance | |
4417 | * | |
4418 | * This function enables the hotplug support. It requires that interrupts have | |
4419 | * already been enabled with intel_irq_init_hw(). From this point on hotplug and | |
4420 | * poll request can run concurrently to other code, so locking rules must be | |
4421 | * obeyed. | |
4422 | * | |
4423 | * This is a separate step from interrupt enabling to simplify the locking rules | |
4424 | * in the driver load and resume code. | |
4425 | */ | |
b963291c | 4426 | void intel_hpd_init(struct drm_i915_private *dev_priv) |
20afbda2 | 4427 | { |
b963291c | 4428 | struct drm_device *dev = dev_priv->dev; |
821450c6 EE |
4429 | struct drm_mode_config *mode_config = &dev->mode_config; |
4430 | struct drm_connector *connector; | |
4431 | int i; | |
20afbda2 | 4432 | |
821450c6 EE |
4433 | for (i = 1; i < HPD_NUM_PINS; i++) { |
4434 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
4435 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
4436 | } | |
4437 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
4438 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4439 | connector->polled = intel_connector->polled; | |
0e32b39c DA |
4440 | if (connector->encoder && !connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE) |
4441 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
4442 | if (intel_connector->mst_port) | |
821450c6 EE |
4443 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
4444 | } | |
b5ea2d56 DV |
4445 | |
4446 | /* Interrupt setup is already guaranteed to be single-threaded, this is | |
4447 | * just to make the assert_spin_locked checks happy. */ | |
d6207435 | 4448 | spin_lock_irq(&dev_priv->irq_lock); |
20afbda2 DV |
4449 | if (dev_priv->display.hpd_irq_setup) |
4450 | dev_priv->display.hpd_irq_setup(dev); | |
d6207435 | 4451 | spin_unlock_irq(&dev_priv->irq_lock); |
20afbda2 | 4452 | } |
c67a470b | 4453 | |
fca52a55 DV |
4454 | /** |
4455 | * intel_irq_install - enables the hardware interrupt | |
4456 | * @dev_priv: i915 device instance | |
4457 | * | |
4458 | * This function enables the hardware interrupt handling, but leaves the hotplug | |
4459 | * handling still disabled. It is called after intel_irq_init(). | |
4460 | * | |
4461 | * In the driver load and resume code we need working interrupts in a few places | |
4462 | * but don't want to deal with the hassle of concurrent probe and hotplug | |
4463 | * workers. Hence the split into this two-stage approach. | |
4464 | */ | |
2aeb7d3a DV |
4465 | int intel_irq_install(struct drm_i915_private *dev_priv) |
4466 | { | |
4467 | /* | |
4468 | * We enable some interrupt sources in our postinstall hooks, so mark | |
4469 | * interrupts as enabled _before_ actually enabling them to avoid | |
4470 | * special cases in our ordering checks. | |
4471 | */ | |
4472 | dev_priv->pm.irqs_enabled = true; | |
4473 | ||
4474 | return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq); | |
4475 | } | |
4476 | ||
fca52a55 DV |
4477 | /** |
4478 | * intel_irq_uninstall - finilizes all irq handling | |
4479 | * @dev_priv: i915 device instance | |
4480 | * | |
4481 | * This stops interrupt and hotplug handling and unregisters and frees all | |
4482 | * resources acquired in the init functions. | |
4483 | */ | |
2aeb7d3a DV |
4484 | void intel_irq_uninstall(struct drm_i915_private *dev_priv) |
4485 | { | |
4486 | drm_irq_uninstall(dev_priv->dev); | |
4487 | intel_hpd_cancel_work(dev_priv); | |
4488 | dev_priv->pm.irqs_enabled = false; | |
4489 | } | |
4490 | ||
fca52a55 DV |
4491 | /** |
4492 | * intel_runtime_pm_disable_interrupts - runtime interrupt disabling | |
4493 | * @dev_priv: i915 device instance | |
4494 | * | |
4495 | * This function is used to disable interrupts at runtime, both in the runtime | |
4496 | * pm and the system suspend/resume code. | |
4497 | */ | |
b963291c | 4498 | void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv) |
c67a470b | 4499 | { |
b963291c | 4500 | dev_priv->dev->driver->irq_uninstall(dev_priv->dev); |
2aeb7d3a | 4501 | dev_priv->pm.irqs_enabled = false; |
c67a470b PZ |
4502 | } |
4503 | ||
fca52a55 DV |
4504 | /** |
4505 | * intel_runtime_pm_enable_interrupts - runtime interrupt enabling | |
4506 | * @dev_priv: i915 device instance | |
4507 | * | |
4508 | * This function is used to enable interrupts at runtime, both in the runtime | |
4509 | * pm and the system suspend/resume code. | |
4510 | */ | |
b963291c | 4511 | void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv) |
c67a470b | 4512 | { |
2aeb7d3a | 4513 | dev_priv->pm.irqs_enabled = true; |
b963291c DV |
4514 | dev_priv->dev->driver->irq_preinstall(dev_priv->dev); |
4515 | dev_priv->dev->driver->irq_postinstall(dev_priv->dev); | |
c67a470b | 4516 | } |