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drm/i915: Fix build warning on 32-bit
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / i915_irq.c
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0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
b2c88f5b 33#include <linux/circ_buf.h>
760285e7
DH		 34#include <drm/drmP.h>
35#include <drm/i915_drm.h>
1da177e4 36#include "i915_drv.h"
1c5d22f7 37#include "i915_trace.h"
79e53945 38#include "intel_drv.h"
1da177e4 39
fca52a55
DV		 40/**
41 * DOC: interrupt handling
42 *
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
46 */
47
7c7e10db 48static const u32 hpd_ibx[HPD_NUM_PINS] = {
e5868a31
EE		 49 [HPD_CRT] = SDE_CRT_HOTPLUG,
50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
54};
55
7c7e10db 56static const u32 hpd_cpt[HPD_NUM_PINS] = {
e5868a31 57 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
73c352a2 58 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
e5868a31
EE		 59 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
60 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
61 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
62};
63
7c7e10db 64static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
e5868a31
EE		 65 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
66 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
67 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
68 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
69 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
70 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
71};
72
7c7e10db 73static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
e5868a31
EE		 74 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
75 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
76 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
77 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
78 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
79 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
80};
81
4bca26d0 82static const u32 hpd_status_i915[HPD_NUM_PINS] = {
e5868a31
EE		 83 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
84 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
85 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
86 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
87 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
88 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
89};
90
e0a20ad7
SS		 91/* BXT hpd list */
92static const u32 hpd_bxt[HPD_NUM_PINS] = {
93 [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
94 [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
95};
96
5c502442 97/* IIR can theoretically queue up two events. Be paranoid. */
f86f3fb0 98#define GEN8_IRQ_RESET_NDX(type, which) do { \
5c502442
PZ		 99 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
100 POSTING_READ(GEN8_##type##_IMR(which)); \
101 I915_WRITE(GEN8_##type##_IER(which), 0); \
102 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
103 POSTING_READ(GEN8_##type##_IIR(which)); \
104 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
105 POSTING_READ(GEN8_##type##_IIR(which)); \
106} while (0)
107
f86f3fb0 108#define GEN5_IRQ_RESET(type) do { \
a9d356a6 109 I915_WRITE(type##IMR, 0xffffffff); \
5c502442 110 POSTING_READ(type##IMR); \
a9d356a6 111 I915_WRITE(type##IER, 0); \
5c502442
PZ		 112 I915_WRITE(type##IIR, 0xffffffff); \
113 POSTING_READ(type##IIR); \
114 I915_WRITE(type##IIR, 0xffffffff); \
115 POSTING_READ(type##IIR); \
a9d356a6
PZ		 116} while (0)
117
337ba017
PZ		 118/*
119 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
120 */
121#define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
122 u32 val = I915_READ(reg); \
123 if (val) { \
124 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
125 (reg), val); \
126 I915_WRITE((reg), 0xffffffff); \
127 POSTING_READ(reg); \
128 I915_WRITE((reg), 0xffffffff); \
129 POSTING_READ(reg); \
130 } \
131} while (0)
132
35079899 133#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
337ba017 134 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
35079899 135 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
7d1bd539
VS		 136 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
137 POSTING_READ(GEN8_##type##_IMR(which)); \
35079899
PZ		 138} while (0)
139
140#define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
337ba017 141 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
35079899 142 I915_WRITE(type##IER, (ier_val)); \
7d1bd539
VS		 143 I915_WRITE(type##IMR, (imr_val)); \
144 POSTING_READ(type##IMR); \
35079899
PZ		 145} while (0)
146
c9a9a268
ID		 147static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
148
036a4a7d 149/* For display hotplug interrupt */
47339cd9 150void
2d1013dd 151ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
036a4a7d 152{
4bc9d430
DV		 153 assert_spin_locked(&dev_priv->irq_lock);
154
9df7575f 155 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
c67a470b 156 return;
c67a470b 157
1ec14ad3
CW		 158 if ((dev_priv->irq_mask & mask) != 0) {
159 dev_priv->irq_mask &= ~mask;
160 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 161 POSTING_READ(DEIMR);
036a4a7d
ZW		 162 }
163}
164
47339cd9 165void
2d1013dd 166ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
036a4a7d 167{
4bc9d430
DV		 168 assert_spin_locked(&dev_priv->irq_lock);
169
06ffc778 170 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
c67a470b 171 return;
c67a470b 172
1ec14ad3
CW		 173 if ((dev_priv->irq_mask & mask) != mask) {
174 dev_priv->irq_mask |= mask;
175 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 176 POSTING_READ(DEIMR);
036a4a7d
ZW		 177 }
178}
179
43eaea13
PZ		 180/**
181 * ilk_update_gt_irq - update GTIMR
182 * @dev_priv: driver private
183 * @interrupt_mask: mask of interrupt bits to update
184 * @enabled_irq_mask: mask of interrupt bits to enable
185 */
186static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
187 uint32_t interrupt_mask,
188 uint32_t enabled_irq_mask)
189{
190 assert_spin_locked(&dev_priv->irq_lock);
191
15a17aae
DV		 192 WARN_ON(enabled_irq_mask & ~interrupt_mask);
193
9df7575f 194 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
c67a470b 195 return;
c67a470b 196
43eaea13
PZ		 197 dev_priv->gt_irq_mask &= ~interrupt_mask;
198 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
199 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
200 POSTING_READ(GTIMR);
201}
202
480c8033 203void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
43eaea13
PZ		 204{
205 ilk_update_gt_irq(dev_priv, mask, mask);
206}
207
480c8033 208void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
43eaea13
PZ		 209{
210 ilk_update_gt_irq(dev_priv, mask, 0);
211}
212
b900b949
ID		 213static u32 gen6_pm_iir(struct drm_i915_private *dev_priv)
214{
215 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
216}
217
a72fbc3a
ID		 218static u32 gen6_pm_imr(struct drm_i915_private *dev_priv)
219{
220 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
221}
222
b900b949
ID		 223static u32 gen6_pm_ier(struct drm_i915_private *dev_priv)
224{
225 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
226}
227
edbfdb45
PZ		 228/**
229 * snb_update_pm_irq - update GEN6_PMIMR
230 * @dev_priv: driver private
231 * @interrupt_mask: mask of interrupt bits to update
232 * @enabled_irq_mask: mask of interrupt bits to enable
233 */
234static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
235 uint32_t interrupt_mask,
236 uint32_t enabled_irq_mask)
237{
605cd25b 238 uint32_t new_val;
edbfdb45 239
15a17aae
DV		 240 WARN_ON(enabled_irq_mask & ~interrupt_mask);
241
edbfdb45
PZ		 242 assert_spin_locked(&dev_priv->irq_lock);
243
605cd25b 244 new_val = dev_priv->pm_irq_mask;
f52ecbcf
PZ		 245 new_val &= ~interrupt_mask;
246 new_val |= (~enabled_irq_mask & interrupt_mask);
247
605cd25b
PZ		 248 if (new_val != dev_priv->pm_irq_mask) {
249 dev_priv->pm_irq_mask = new_val;
a72fbc3a
ID		 250 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
251 POSTING_READ(gen6_pm_imr(dev_priv));
f52ecbcf 252 }
edbfdb45
PZ		 253}
254
480c8033 255void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
edbfdb45 256{
9939fba2
ID		 257 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
258 return;
259
edbfdb45
PZ		 260 snb_update_pm_irq(dev_priv, mask, mask);
261}
262
9939fba2
ID		 263static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
264 uint32_t mask)
edbfdb45
PZ		 265{
266 snb_update_pm_irq(dev_priv, mask, 0);
267}
268
9939fba2
ID		 269void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
270{
271 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
272 return;
273
274 __gen6_disable_pm_irq(dev_priv, mask);
275}
276
3cc134e3
ID		 277void gen6_reset_rps_interrupts(struct drm_device *dev)
278{
279 struct drm_i915_private *dev_priv = dev->dev_private;
280 uint32_t reg = gen6_pm_iir(dev_priv);
281
282 spin_lock_irq(&dev_priv->irq_lock);
283 I915_WRITE(reg, dev_priv->pm_rps_events);
284 I915_WRITE(reg, dev_priv->pm_rps_events);
285 POSTING_READ(reg);
096fad9e 286 dev_priv->rps.pm_iir = 0;
3cc134e3
ID		 287 spin_unlock_irq(&dev_priv->irq_lock);
288}
289
b900b949
ID		 290void gen6_enable_rps_interrupts(struct drm_device *dev)
291{
292 struct drm_i915_private *dev_priv = dev->dev_private;
293
294 spin_lock_irq(&dev_priv->irq_lock);
78e68d36 295
b900b949 296 WARN_ON(dev_priv->rps.pm_iir);
3cc134e3 297 WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
d4d70aa5 298 dev_priv->rps.interrupts_enabled = true;
78e68d36
ID		 299 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
300 dev_priv->pm_rps_events);
b900b949 301 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
78e68d36 302
b900b949
ID		 303 spin_unlock_irq(&dev_priv->irq_lock);
304}
305
59d02a1f
ID		 306u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
307{
308 /*
f24eeb19 309 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
59d02a1f 310 * if GEN6_PM_UP_EI_EXPIRED is masked.
f24eeb19
ID		 311 *
312 * TODO: verify if this can be reproduced on VLV,CHV.
59d02a1f
ID		 313 */
314 if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
315 mask &= ~GEN6_PM_RP_UP_EI_EXPIRED;
316
317 if (INTEL_INFO(dev_priv)->gen >= 8)
318 mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
319
320 return mask;
321}
322
b900b949
ID		 323void gen6_disable_rps_interrupts(struct drm_device *dev)
324{
325 struct drm_i915_private *dev_priv = dev->dev_private;
326
d4d70aa5
ID		 327 spin_lock_irq(&dev_priv->irq_lock);
328 dev_priv->rps.interrupts_enabled = false;
329 spin_unlock_irq(&dev_priv->irq_lock);
330
331 cancel_work_sync(&dev_priv->rps.work);
332
9939fba2
ID		 333 spin_lock_irq(&dev_priv->irq_lock);
334
59d02a1f 335 I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
9939fba2
ID		 336
337 __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
b900b949
ID		 338 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
339 ~dev_priv->pm_rps_events);
58072ccb
ID		 340
341 spin_unlock_irq(&dev_priv->irq_lock);
342
343 synchronize_irq(dev->irq);
b900b949
ID		 344}
345
fee884ed
DV		 346/**
347 * ibx_display_interrupt_update - update SDEIMR
348 * @dev_priv: driver private
349 * @interrupt_mask: mask of interrupt bits to update
350 * @enabled_irq_mask: mask of interrupt bits to enable
351 */
47339cd9
DV		 352void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
353 uint32_t interrupt_mask,
354 uint32_t enabled_irq_mask)
fee884ed
DV		 355{
356 uint32_t sdeimr = I915_READ(SDEIMR);
357 sdeimr &= ~interrupt_mask;
358 sdeimr |= (~enabled_irq_mask & interrupt_mask);
359
15a17aae
DV		 360 WARN_ON(enabled_irq_mask & ~interrupt_mask);
361
fee884ed
DV		 362 assert_spin_locked(&dev_priv->irq_lock);
363
9df7575f 364 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
c67a470b 365 return;
c67a470b 366
fee884ed
DV		 367 I915_WRITE(SDEIMR, sdeimr);
368 POSTING_READ(SDEIMR);
369}
8664281b 370
b5ea642a 371static void
755e9019
ID		 372__i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
373 u32 enable_mask, u32 status_mask)
7c463586 374{
46c06a30 375 u32 reg = PIPESTAT(pipe);
755e9019 376 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
7c463586 377
b79480ba 378 assert_spin_locked(&dev_priv->irq_lock);
d518ce50 379 WARN_ON(!intel_irqs_enabled(dev_priv));
b79480ba 380
04feced9
VS		 381 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
382 status_mask & ~PIPESTAT_INT_STATUS_MASK,
383 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
384 pipe_name(pipe), enable_mask, status_mask))
755e9019
ID		 385 return;
386
387 if ((pipestat & enable_mask) == enable_mask)
46c06a30
VS		 388 return;
389
91d181dd
ID		 390 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
391
46c06a30 392 /* Enable the interrupt, clear any pending status */
755e9019 393 pipestat |= enable_mask | status_mask;
46c06a30
VS		 394 I915_WRITE(reg, pipestat);
395 POSTING_READ(reg);
7c463586
KP		 396}
397
b5ea642a 398static void
755e9019
ID		 399__i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
400 u32 enable_mask, u32 status_mask)
7c463586 401{
46c06a30 402 u32 reg = PIPESTAT(pipe);
755e9019 403 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
7c463586 404
b79480ba 405 assert_spin_locked(&dev_priv->irq_lock);
d518ce50 406 WARN_ON(!intel_irqs_enabled(dev_priv));
b79480ba 407
04feced9
VS		 408 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
409 status_mask & ~PIPESTAT_INT_STATUS_MASK,
410 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
411 pipe_name(pipe), enable_mask, status_mask))
46c06a30
VS		 412 return;
413
755e9019
ID		 414 if ((pipestat & enable_mask) == 0)
415 return;
416
91d181dd
ID		 417 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
418
755e9019 419 pipestat &= ~enable_mask;
46c06a30
VS		 420 I915_WRITE(reg, pipestat);
421 POSTING_READ(reg);
7c463586
KP		 422}
423
10c59c51
ID		 424static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
425{
426 u32 enable_mask = status_mask << 16;
427
428 /*
724a6905
VS		 429 * On pipe A we don't support the PSR interrupt yet,
430 * on pipe B and C the same bit MBZ.
10c59c51
ID		 431 */
432 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
433 return 0;
724a6905
VS		 434 /*
435 * On pipe B and C we don't support the PSR interrupt yet, on pipe
436 * A the same bit is for perf counters which we don't use either.
437 */
438 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
439 return 0;
10c59c51
ID		 440
441 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
442 SPRITE0_FLIP_DONE_INT_EN_VLV |
443 SPRITE1_FLIP_DONE_INT_EN_VLV);
444 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
445 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
446 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
447 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
448
449 return enable_mask;
450}
451
755e9019
ID		 452void
453i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
454 u32 status_mask)
455{
456 u32 enable_mask;
457
10c59c51
ID		 458 if (IS_VALLEYVIEW(dev_priv->dev))
459 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
460 status_mask);
461 else
462 enable_mask = status_mask << 16;
755e9019
ID		 463 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
464}
465
466void
467i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
468 u32 status_mask)
469{
470 u32 enable_mask;
471
10c59c51
ID		 472 if (IS_VALLEYVIEW(dev_priv->dev))
473 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
474 status_mask);
475 else
476 enable_mask = status_mask << 16;
755e9019
ID		 477 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
478}
479
01c66889 480/**
f49e38dd 481 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
01c66889 482 */
f49e38dd 483static void i915_enable_asle_pipestat(struct drm_device *dev)
01c66889 484{
2d1013dd 485 struct drm_i915_private *dev_priv = dev->dev_private;
1ec14ad3 486
f49e38dd
JN		 487 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
488 return;
489
13321786 490 spin_lock_irq(&dev_priv->irq_lock);
01c66889 491
755e9019 492 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
f898780b 493 if (INTEL_INFO(dev)->gen >= 4)
3b6c42e8 494 i915_enable_pipestat(dev_priv, PIPE_A,
755e9019 495 PIPE_LEGACY_BLC_EVENT_STATUS);
1ec14ad3 496
13321786 497 spin_unlock_irq(&dev_priv->irq_lock);
01c66889
ZY		 498}
499
f75f3746
VS		 500/*
501 * This timing diagram depicts the video signal in and
502 * around the vertical blanking period.
503 *
504 * Assumptions about the fictitious mode used in this example:
505 * vblank_start >= 3
506 * vsync_start = vblank_start + 1
507 * vsync_end = vblank_start + 2
508 * vtotal = vblank_start + 3
509 *
510 * start of vblank:
511 * latch double buffered registers
512 * increment frame counter (ctg+)
513 * generate start of vblank interrupt (gen4+)
514 * |
515 * | frame start:
516 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
517 * | may be shifted forward 1-3 extra lines via PIPECONF
518 * | |
519 * | | start of vsync:
520 * | | generate vsync interrupt
521 * | | |
522 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
523 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
524 * ----va---> <-----------------vb--------------------> <--------va-------------
525 * | | <----vs-----> |
526 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
527 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
528 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
529 * | | |
530 * last visible pixel first visible pixel
531 * | increment frame counter (gen3/4)
532 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
533 *
534 * x = horizontal active
535 * _ = horizontal blanking
536 * hs = horizontal sync
537 * va = vertical active
538 * vb = vertical blanking
539 * vs = vertical sync
540 * vbs = vblank_start (number)
541 *
542 * Summary:
543 * - most events happen at the start of horizontal sync
544 * - frame start happens at the start of horizontal blank, 1-4 lines
545 * (depending on PIPECONF settings) after the start of vblank
546 * - gen3/4 pixel and frame counter are synchronized with the start
547 * of horizontal active on the first line of vertical active
548 */
549
4cdb83ec
VS		 550static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
551{
552 /* Gen2 doesn't have a hardware frame counter */
553 return 0;
554}
555
42f52ef8
KP		 556/* Called from drm generic code, passed a 'crtc', which
557 * we use as a pipe index
558 */
f71d4af4 559static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4 560{
2d1013dd 561 struct drm_i915_private *dev_priv = dev->dev_private;
0a3e67a4
JB		 562 unsigned long high_frame;
563 unsigned long low_frame;
0b2a8e09 564 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
f3a5c3f6
DV		 565 struct intel_crtc *intel_crtc =
566 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
fc467a22 567 const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
0a3e67a4 568
f3a5c3f6
DV		 569 htotal = mode->crtc_htotal;
570 hsync_start = mode->crtc_hsync_start;
571 vbl_start = mode->crtc_vblank_start;
572 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
573 vbl_start = DIV_ROUND_UP(vbl_start, 2);
391f75e2 574
0b2a8e09
VS		 575 /* Convert to pixel count */
576 vbl_start *= htotal;
577
578 /* Start of vblank event occurs at start of hsync */
579 vbl_start -= htotal - hsync_start;
580
9db4a9c7
JB		 581 high_frame = PIPEFRAME(pipe);
582 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 583
0a3e67a4
JB		 584 /*
585 * High & low register fields aren't synchronized, so make sure
586 * we get a low value that's stable across two reads of the high
587 * register.
588 */
589 do {
5eddb70b 590 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
391f75e2 591 low = I915_READ(low_frame);
5eddb70b 592 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 593 } while (high1 != high2);
594
5eddb70b 595 high1 >>= PIPE_FRAME_HIGH_SHIFT;
391f75e2 596 pixel = low & PIPE_PIXEL_MASK;
5eddb70b 597 low >>= PIPE_FRAME_LOW_SHIFT;
391f75e2
VS		 598
599 /*
600 * The frame counter increments at beginning of active.
601 * Cook up a vblank counter by also checking the pixel
602 * counter against vblank start.
603 */
edc08d0a 604 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
0a3e67a4
JB		 605}
606
f71d4af4 607static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5 608{
2d1013dd 609 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 610 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5 611
9880b7a5
JB		 612 return I915_READ(reg);
613}
614
ad3543ed
MK		 615/* raw reads, only for fast reads of display block, no need for forcewake etc. */
616#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
ad3543ed 617
a225f079
VS		 618static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
619{
620 struct drm_device *dev = crtc->base.dev;
621 struct drm_i915_private *dev_priv = dev->dev_private;
fc467a22 622 const struct drm_display_mode *mode = &crtc->base.hwmode;
a225f079 623 enum pipe pipe = crtc->pipe;
80715b2f 624 int position, vtotal;
a225f079 625
80715b2f 626 vtotal = mode->crtc_vtotal;
a225f079
VS		 627 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
628 vtotal /= 2;
629
630 if (IS_GEN2(dev))
631 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
632 else
633 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
634
635 /*
80715b2f
VS		 636 * See update_scanline_offset() for the details on the
637 * scanline_offset adjustment.
a225f079 638 */
80715b2f 639 return (position + crtc->scanline_offset) % vtotal;
a225f079
VS		 640}
641
f71d4af4 642static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
abca9e45
VS		 643 unsigned int flags, int *vpos, int *hpos,
644 ktime_t *stime, ktime_t *etime)
0af7e4df 645{
c2baf4b7
VS		 646 struct drm_i915_private *dev_priv = dev->dev_private;
647 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fc467a22 649 const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
3aa18df8 650 int position;
78e8fc6b 651 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
0af7e4df
MK		 652 bool in_vbl = true;
653 int ret = 0;
ad3543ed 654 unsigned long irqflags;
0af7e4df 655
fc467a22 656 if (WARN_ON(!mode->crtc_clock)) {
0af7e4df 657 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 658 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 659 return 0;
660 }
661
c2baf4b7 662 htotal = mode->crtc_htotal;
78e8fc6b 663 hsync_start = mode->crtc_hsync_start;
c2baf4b7
VS		 664 vtotal = mode->crtc_vtotal;
665 vbl_start = mode->crtc_vblank_start;
666 vbl_end = mode->crtc_vblank_end;
0af7e4df 667
d31faf65
VS		 668 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
669 vbl_start = DIV_ROUND_UP(vbl_start, 2);
670 vbl_end /= 2;
671 vtotal /= 2;
672 }
673
c2baf4b7
VS		 674 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
675
ad3543ed
MK		 676 /*
677 * Lock uncore.lock, as we will do multiple timing critical raw
678 * register reads, potentially with preemption disabled, so the
679 * following code must not block on uncore.lock.
680 */
681 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
78e8fc6b 682
ad3543ed
MK		 683 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
684
685 /* Get optional system timestamp before query. */
686 if (stime)
687 *stime = ktime_get();
688
7c06b08a 689 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
0af7e4df
MK		 690 /* No obvious pixelcount register. Only query vertical
691 * scanout position from Display scan line register.
692 */
a225f079 693 position = __intel_get_crtc_scanline(intel_crtc);
0af7e4df
MK		 694 } else {
695 /* Have access to pixelcount since start of frame.
696 * We can split this into vertical and horizontal
697 * scanout position.
698 */
ad3543ed 699 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
0af7e4df 700
3aa18df8
VS		 701 /* convert to pixel counts */
702 vbl_start *= htotal;
703 vbl_end *= htotal;
704 vtotal *= htotal;
78e8fc6b 705
7e78f1cb
VS		 706 /*
707 * In interlaced modes, the pixel counter counts all pixels,
708 * so one field will have htotal more pixels. In order to avoid
709 * the reported position from jumping backwards when the pixel
710 * counter is beyond the length of the shorter field, just
711 * clamp the position the length of the shorter field. This
712 * matches how the scanline counter based position works since
713 * the scanline counter doesn't count the two half lines.
714 */
715 if (position >= vtotal)
716 position = vtotal - 1;
717
78e8fc6b
VS		 718 /*
719 * Start of vblank interrupt is triggered at start of hsync,
720 * just prior to the first active line of vblank. However we
721 * consider lines to start at the leading edge of horizontal
722 * active. So, should we get here before we've crossed into
723 * the horizontal active of the first line in vblank, we would
724 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
725 * always add htotal-hsync_start to the current pixel position.
726 */
727 position = (position + htotal - hsync_start) % vtotal;
0af7e4df
MK		 728 }
729
ad3543ed
MK		 730 /* Get optional system timestamp after query. */
731 if (etime)
732 *etime = ktime_get();
733
734 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
735
736 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
737
3aa18df8
VS		 738 in_vbl = position >= vbl_start && position < vbl_end;
739
740 /*
741 * While in vblank, position will be negative
742 * counting up towards 0 at vbl_end. And outside
743 * vblank, position will be positive counting
744 * up since vbl_end.
745 */
746 if (position >= vbl_start)
747 position -= vbl_end;
748 else
749 position += vtotal - vbl_end;
0af7e4df 750
7c06b08a 751 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
3aa18df8
VS		 752 *vpos = position;
753 *hpos = 0;
754 } else {
755 *vpos = position / htotal;
756 *hpos = position - (*vpos * htotal);
757 }
0af7e4df 758
0af7e4df
MK		 759 /* In vblank? */
760 if (in_vbl)
3d3cbd84 761 ret |= DRM_SCANOUTPOS_IN_VBLANK;
0af7e4df
MK		 762
763 return ret;
764}
765
a225f079
VS		 766int intel_get_crtc_scanline(struct intel_crtc *crtc)
767{
768 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
769 unsigned long irqflags;
770 int position;
771
772 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
773 position = __intel_get_crtc_scanline(crtc);
774 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
775
776 return position;
777}
778
f71d4af4 779static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 780 int *max_error,
781 struct timeval *vblank_time,
782 unsigned flags)
783{
4041b853 784 struct drm_crtc *crtc;
0af7e4df 785
7eb552ae 786 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
4041b853 787 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 788 return -EINVAL;
789 }
790
791 /* Get drm_crtc to timestamp: */
4041b853
CW		 792 crtc = intel_get_crtc_for_pipe(dev, pipe);
793 if (crtc == NULL) {
794 DRM_ERROR("Invalid crtc %d\n", pipe);
795 return -EINVAL;
796 }
797
fc467a22 798 if (!crtc->hwmode.crtc_clock) {
4041b853
CW		 799 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
800 return -EBUSY;
801 }
0af7e4df
MK		 802
803 /* Helper routine in DRM core does all the work: */
4041b853
CW		 804 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
805 vblank_time, flags,
7da903ef 806 crtc,
fc467a22 807 &crtc->hwmode);
0af7e4df
MK		 808}
809
d0ecd7e2 810static void ironlake_rps_change_irq_handler(struct drm_device *dev)
f97108d1 811{
2d1013dd 812 struct drm_i915_private *dev_priv = dev->dev_private;
b5b72e89 813 u32 busy_up, busy_down, max_avg, min_avg;
9270388e 814 u8 new_delay;
9270388e 815
d0ecd7e2 816 spin_lock(&mchdev_lock);
f97108d1 817
73edd18f
DV		 818 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
819
20e4d407 820 new_delay = dev_priv->ips.cur_delay;
9270388e 821
7648fa99 822 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 823 busy_up = I915_READ(RCPREVBSYTUPAVG);
824 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 825 max_avg = I915_READ(RCBMAXAVG);
826 min_avg = I915_READ(RCBMINAVG);
827
828 /* Handle RCS change request from hw */
b5b72e89 829 if (busy_up > max_avg) {
20e4d407
DV		 830 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
831 new_delay = dev_priv->ips.cur_delay - 1;
832 if (new_delay < dev_priv->ips.max_delay)
833 new_delay = dev_priv->ips.max_delay;
b5b72e89 834 } else if (busy_down < min_avg) {
20e4d407
DV		 835 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
836 new_delay = dev_priv->ips.cur_delay + 1;
837 if (new_delay > dev_priv->ips.min_delay)
838 new_delay = dev_priv->ips.min_delay;
f97108d1
JB		 839 }
840
7648fa99 841 if (ironlake_set_drps(dev, new_delay))
20e4d407 842 dev_priv->ips.cur_delay = new_delay;
f97108d1 843
d0ecd7e2 844 spin_unlock(&mchdev_lock);
9270388e 845
f97108d1
JB		 846 return;
847}
848
74cdb337 849static void notify_ring(struct intel_engine_cs *ring)
549f7365 850{
93b0a4e0 851 if (!intel_ring_initialized(ring))
475553de
CW		 852 return;
853
bcfcc8ba 854 trace_i915_gem_request_notify(ring);
9862e600 855
549f7365 856 wake_up_all(&ring->irq_queue);
549f7365
CW		 857}
858
43cf3bf0
CW		 859static void vlv_c0_read(struct drm_i915_private *dev_priv,
860 struct intel_rps_ei *ei)
31685c25 861{
43cf3bf0
CW		 862 ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
863 ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
864 ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
865}
31685c25 866
43cf3bf0
CW		 867static bool vlv_c0_above(struct drm_i915_private *dev_priv,
868 const struct intel_rps_ei *old,
869 const struct intel_rps_ei *now,
870 int threshold)
871{
872 u64 time, c0;
31685c25 873
43cf3bf0
CW		 874 if (old->cz_clock == 0)
875 return false;
31685c25 876
43cf3bf0
CW		 877 time = now->cz_clock - old->cz_clock;
878 time *= threshold * dev_priv->mem_freq;
31685c25 879
43cf3bf0
CW		 880 /* Workload can be split between render + media, e.g. SwapBuffers
881 * being blitted in X after being rendered in mesa. To account for
882 * this we need to combine both engines into our activity counter.
31685c25 883 */
43cf3bf0
CW		 884 c0 = now->render_c0 - old->render_c0;
885 c0 += now->media_c0 - old->media_c0;
886 c0 *= 100 * VLV_CZ_CLOCK_TO_MILLI_SEC * 4 / 1000;
31685c25 887
43cf3bf0 888 return c0 >= time;
31685c25
D		 889}
890
43cf3bf0 891void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
31685c25 892{
43cf3bf0
CW		 893 vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
894 dev_priv->rps.up_ei = dev_priv->rps.down_ei;
43cf3bf0 895}
31685c25 896
43cf3bf0
CW		 897static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
898{
899 struct intel_rps_ei now;
900 u32 events = 0;
31685c25 901
6f4b12f8 902 if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
43cf3bf0 903 return 0;
31685c25 904
43cf3bf0
CW		 905 vlv_c0_read(dev_priv, &now);
906 if (now.cz_clock == 0)
907 return 0;
31685c25 908
43cf3bf0
CW		 909 if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
910 if (!vlv_c0_above(dev_priv,
911 &dev_priv->rps.down_ei, &now,
8fb55197 912 dev_priv->rps.down_threshold))
43cf3bf0
CW		 913 events |= GEN6_PM_RP_DOWN_THRESHOLD;
914 dev_priv->rps.down_ei = now;
915 }
31685c25 916
43cf3bf0
CW		 917 if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
918 if (vlv_c0_above(dev_priv,
919 &dev_priv->rps.up_ei, &now,
8fb55197 920 dev_priv->rps.up_threshold))
43cf3bf0
CW		 921 events |= GEN6_PM_RP_UP_THRESHOLD;
922 dev_priv->rps.up_ei = now;
31685c25
D		 923 }
924
43cf3bf0 925 return events;
31685c25
D		 926}
927
f5a4c67d
CW		 928static bool any_waiters(struct drm_i915_private *dev_priv)
929{
930 struct intel_engine_cs *ring;
931 int i;
932
933 for_each_ring(ring, dev_priv, i)
934 if (ring->irq_refcount)
935 return true;
936
937 return false;
938}
939
4912d041 940static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 941{
2d1013dd
JN		 942 struct drm_i915_private *dev_priv =
943 container_of(work, struct drm_i915_private, rps.work);
8d3afd7d
CW		 944 bool client_boost;
945 int new_delay, adj, min, max;
edbfdb45 946 u32 pm_iir;
4912d041 947
59cdb63d 948 spin_lock_irq(&dev_priv->irq_lock);
d4d70aa5
ID		 949 /* Speed up work cancelation during disabling rps interrupts. */
950 if (!dev_priv->rps.interrupts_enabled) {
951 spin_unlock_irq(&dev_priv->irq_lock);
952 return;
953 }
c6a828d3
DV		 954 pm_iir = dev_priv->rps.pm_iir;
955 dev_priv->rps.pm_iir = 0;
a72fbc3a
ID		 956 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
957 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
8d3afd7d
CW		 958 client_boost = dev_priv->rps.client_boost;
959 dev_priv->rps.client_boost = false;
59cdb63d 960 spin_unlock_irq(&dev_priv->irq_lock);
3b8d8d91 961
60611c13 962 /* Make sure we didn't queue anything we're not going to process. */
a6706b45 963 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
60611c13 964
8d3afd7d 965 if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
3b8d8d91
JB		 966 return;
967
4fc688ce 968 mutex_lock(&dev_priv->rps.hw_lock);
7b9e0ae6 969
43cf3bf0
CW		 970 pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
971
dd75fdc8 972 adj = dev_priv->rps.last_adj;
edcf284b 973 new_delay = dev_priv->rps.cur_freq;
8d3afd7d
CW		 974 min = dev_priv->rps.min_freq_softlimit;
975 max = dev_priv->rps.max_freq_softlimit;
976
977 if (client_boost) {
978 new_delay = dev_priv->rps.max_freq_softlimit;
979 adj = 0;
980 } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
dd75fdc8
CW		 981 if (adj > 0)
982 adj *= 2;
edcf284b
CW		 983 else /* CHV needs even encode values */
984 adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
7425034a
VS		 985 /*
986 * For better performance, jump directly
987 * to RPe if we're below it.
988 */
edcf284b 989 if (new_delay < dev_priv->rps.efficient_freq - adj) {
b39fb297 990 new_delay = dev_priv->rps.efficient_freq;
edcf284b
CW		 991 adj = 0;
992 }
f5a4c67d
CW		 993 } else if (any_waiters(dev_priv)) {
994 adj = 0;
dd75fdc8 995 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
b39fb297
BW		 996 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
997 new_delay = dev_priv->rps.efficient_freq;
dd75fdc8 998 else
b39fb297 999 new_delay = dev_priv->rps.min_freq_softlimit;
dd75fdc8
CW		 1000 adj = 0;
1001 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1002 if (adj < 0)
1003 adj *= 2;
edcf284b
CW		 1004 else /* CHV needs even encode values */
1005 adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
dd75fdc8 1006 } else { /* unknown event */
edcf284b 1007 adj = 0;
dd75fdc8 1008 }
3b8d8d91 1009
edcf284b
CW		 1010 dev_priv->rps.last_adj = adj;
1011
79249636
BW		 1012 /* sysfs frequency interfaces may have snuck in while servicing the
1013 * interrupt
1014 */
edcf284b 1015 new_delay += adj;
8d3afd7d 1016 new_delay = clamp_t(int, new_delay, min, max);
27544369 1017
ffe02b40 1018 intel_set_rps(dev_priv->dev, new_delay);
3b8d8d91 1019
4fc688ce 1020 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91
JB		 1021}
1022
e3689190
BW		 1023
1024/**
1025 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1026 * occurred.
1027 * @work: workqueue struct
1028 *
1029 * Doesn't actually do anything except notify userspace. As a consequence of
1030 * this event, userspace should try to remap the bad rows since statistically
1031 * it is likely the same row is more likely to go bad again.
1032 */
1033static void ivybridge_parity_work(struct work_struct *work)
1034{
2d1013dd
JN		 1035 struct drm_i915_private *dev_priv =
1036 container_of(work, struct drm_i915_private, l3_parity.error_work);
e3689190 1037 u32 error_status, row, bank, subbank;
35a85ac6 1038 char *parity_event[6];
e3689190 1039 uint32_t misccpctl;
35a85ac6 1040 uint8_t slice = 0;
e3689190
BW		 1041
1042 /* We must turn off DOP level clock gating to access the L3 registers.
1043 * In order to prevent a get/put style interface, acquire struct mutex
1044 * any time we access those registers.
1045 */
1046 mutex_lock(&dev_priv->dev->struct_mutex);
1047
35a85ac6
BW		 1048 /* If we've screwed up tracking, just let the interrupt fire again */
1049 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1050 goto out;
1051
e3689190
BW		 1052 misccpctl = I915_READ(GEN7_MISCCPCTL);
1053 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1054 POSTING_READ(GEN7_MISCCPCTL);
1055
35a85ac6
BW		 1056 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1057 u32 reg;
e3689190 1058
35a85ac6
BW		 1059 slice--;
1060 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1061 break;
e3689190 1062
35a85ac6 1063 dev_priv->l3_parity.which_slice &= ~(1<<slice);
e3689190 1064
35a85ac6 1065 reg = GEN7_L3CDERRST1 + (slice * 0x200);
e3689190 1066
35a85ac6
BW		 1067 error_status = I915_READ(reg);
1068 row = GEN7_PARITY_ERROR_ROW(error_status);
1069 bank = GEN7_PARITY_ERROR_BANK(error_status);
1070 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1071
1072 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1073 POSTING_READ(reg);
1074
1075 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1076 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1077 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1078 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1079 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1080 parity_event[5] = NULL;
1081
5bdebb18 1082 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
35a85ac6 1083 KOBJ_CHANGE, parity_event);
e3689190 1084
35a85ac6
BW		 1085 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1086 slice, row, bank, subbank);
e3689190 1087
35a85ac6
BW		 1088 kfree(parity_event[4]);
1089 kfree(parity_event[3]);
1090 kfree(parity_event[2]);
1091 kfree(parity_event[1]);
1092 }
e3689190 1093
35a85ac6 1094 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
e3689190 1095
35a85ac6
BW		 1096out:
1097 WARN_ON(dev_priv->l3_parity.which_slice);
4cb21832 1098 spin_lock_irq(&dev_priv->irq_lock);
480c8033 1099 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
4cb21832 1100 spin_unlock_irq(&dev_priv->irq_lock);
35a85ac6
BW		 1101
1102 mutex_unlock(&dev_priv->dev->struct_mutex);
e3689190
BW		 1103}
1104
35a85ac6 1105static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
e3689190 1106{
2d1013dd 1107 struct drm_i915_private *dev_priv = dev->dev_private;
e3689190 1108
040d2baa 1109 if (!HAS_L3_DPF(dev))
e3689190
BW		 1110 return;
1111
d0ecd7e2 1112 spin_lock(&dev_priv->irq_lock);
480c8033 1113 gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
d0ecd7e2 1114 spin_unlock(&dev_priv->irq_lock);
e3689190 1115
35a85ac6
BW		 1116 iir &= GT_PARITY_ERROR(dev);
1117 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1118 dev_priv->l3_parity.which_slice |= 1 << 1;
1119
1120 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1121 dev_priv->l3_parity.which_slice |= 1 << 0;
1122
a4da4fa4 1123 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
e3689190
BW		 1124}
1125
f1af8fc1
PZ		 1126static void ilk_gt_irq_handler(struct drm_device *dev,
1127 struct drm_i915_private *dev_priv,
1128 u32 gt_iir)
1129{
1130 if (gt_iir &
1131 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
74cdb337 1132 notify_ring(&dev_priv->ring[RCS]);
f1af8fc1 1133 if (gt_iir & ILK_BSD_USER_INTERRUPT)
74cdb337 1134 notify_ring(&dev_priv->ring[VCS]);
f1af8fc1
PZ		 1135}
1136
e7b4c6b1
DV		 1137static void snb_gt_irq_handler(struct drm_device *dev,
1138 struct drm_i915_private *dev_priv,
1139 u32 gt_iir)
1140{
1141
cc609d5d
BW		 1142 if (gt_iir &
1143 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
74cdb337 1144 notify_ring(&dev_priv->ring[RCS]);
cc609d5d 1145 if (gt_iir & GT_BSD_USER_INTERRUPT)
74cdb337 1146 notify_ring(&dev_priv->ring[VCS]);
cc609d5d 1147 if (gt_iir & GT_BLT_USER_INTERRUPT)
74cdb337 1148 notify_ring(&dev_priv->ring[BCS]);
e7b4c6b1 1149
cc609d5d
BW		 1150 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1151 GT_BSD_CS_ERROR_INTERRUPT |
aaecdf61
DV		 1152 GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1153 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
e3689190 1154
35a85ac6
BW		 1155 if (gt_iir & GT_PARITY_ERROR(dev))
1156 ivybridge_parity_error_irq_handler(dev, gt_iir);
e7b4c6b1
DV		 1157}
1158
74cdb337 1159static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
abd58f01
BW		 1160 u32 master_ctl)
1161{
abd58f01
BW		 1162 irqreturn_t ret = IRQ_NONE;
1163
1164 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
74cdb337 1165 u32 tmp = I915_READ_FW(GEN8_GT_IIR(0));
abd58f01 1166 if (tmp) {
cb0d205e 1167 I915_WRITE_FW(GEN8_GT_IIR(0), tmp);
abd58f01 1168 ret = IRQ_HANDLED;
e981e7b1 1169
74cdb337
CW		 1170 if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
1171 intel_lrc_irq_handler(&dev_priv->ring[RCS]);
1172 if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
1173 notify_ring(&dev_priv->ring[RCS]);
1174
1175 if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
1176 intel_lrc_irq_handler(&dev_priv->ring[BCS]);
1177 if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
1178 notify_ring(&dev_priv->ring[BCS]);
abd58f01
BW		 1179 } else
1180 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1181 }
1182
85f9b5f9 1183 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
74cdb337 1184 u32 tmp = I915_READ_FW(GEN8_GT_IIR(1));
abd58f01 1185 if (tmp) {
cb0d205e 1186 I915_WRITE_FW(GEN8_GT_IIR(1), tmp);
abd58f01 1187 ret = IRQ_HANDLED;
e981e7b1 1188
74cdb337
CW		 1189 if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
1190 intel_lrc_irq_handler(&dev_priv->ring[VCS]);
1191 if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
1192 notify_ring(&dev_priv->ring[VCS]);
abd58f01 1193
74cdb337
CW		 1194 if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
1195 intel_lrc_irq_handler(&dev_priv->ring[VCS2]);
1196 if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
1197 notify_ring(&dev_priv->ring[VCS2]);
0961021a 1198 } else
abd58f01 1199 DRM_ERROR("The master control interrupt lied (GT1)!\n");
0961021a
BW		 1200 }
1201
abd58f01 1202 if (master_ctl & GEN8_GT_VECS_IRQ) {
74cdb337 1203 u32 tmp = I915_READ_FW(GEN8_GT_IIR(3));
abd58f01 1204 if (tmp) {
74cdb337 1205 I915_WRITE_FW(GEN8_GT_IIR(3), tmp);
abd58f01 1206 ret = IRQ_HANDLED;
e981e7b1 1207
74cdb337
CW		 1208 if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
1209 intel_lrc_irq_handler(&dev_priv->ring[VECS]);
1210 if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
1211 notify_ring(&dev_priv->ring[VECS]);
abd58f01
BW		 1212 } else
1213 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1214 }
1215
0961021a 1216 if (master_ctl & GEN8_GT_PM_IRQ) {
74cdb337 1217 u32 tmp = I915_READ_FW(GEN8_GT_IIR(2));
0961021a 1218 if (tmp & dev_priv->pm_rps_events) {
cb0d205e
CW		 1219 I915_WRITE_FW(GEN8_GT_IIR(2),
1220 tmp & dev_priv->pm_rps_events);
38cc46d7 1221 ret = IRQ_HANDLED;
c9a9a268 1222 gen6_rps_irq_handler(dev_priv, tmp);
0961021a
BW		 1223 } else
1224 DRM_ERROR("The master control interrupt lied (PM)!\n");
1225 }
1226
abd58f01
BW		 1227 return ret;
1228}
1229
63c88d22
ID		 1230static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
1231{
1232 switch (port) {
1233 case PORT_A:
1234 return val & BXT_PORTA_HOTPLUG_LONG_DETECT;
1235 case PORT_B:
1236 return val & PORTB_HOTPLUG_LONG_DETECT;
1237 case PORT_C:
1238 return val & PORTC_HOTPLUG_LONG_DETECT;
1239 case PORT_D:
1240 return val & PORTD_HOTPLUG_LONG_DETECT;
1241 default:
1242 return false;
1243 }
1244}
1245
676574df 1246static bool pch_port_hotplug_long_detect(enum port port, u32 val)
13cf5504
DA		 1247{
1248 switch (port) {
13cf5504 1249 case PORT_B:
676574df 1250 return val & PORTB_HOTPLUG_LONG_DETECT;
13cf5504 1251 case PORT_C:
676574df 1252 return val & PORTC_HOTPLUG_LONG_DETECT;
13cf5504 1253 case PORT_D:
676574df
JN		 1254 return val & PORTD_HOTPLUG_LONG_DETECT;
1255 default:
1256 return false;
13cf5504
DA		 1257 }
1258}
1259
676574df 1260static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
13cf5504
DA		 1261{
1262 switch (port) {
13cf5504 1263 case PORT_B:
676574df 1264 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
13cf5504 1265 case PORT_C:
676574df 1266 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
13cf5504 1267 case PORT_D:
676574df
JN		 1268 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1269 default:
1270 return false;
13cf5504
DA		 1271 }
1272}
1273
676574df 1274/* Get a bit mask of pins that have triggered, and which ones may be long. */
fd63e2a9 1275static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
8c841e57 1276 u32 hotplug_trigger, u32 dig_hotplug_reg,
fd63e2a9
ID		 1277 const u32 hpd[HPD_NUM_PINS],
1278 bool long_pulse_detect(enum port port, u32 val))
676574df 1279{
8c841e57 1280 enum port port;
676574df
JN		 1281 int i;
1282
1283 *pin_mask = 0;
1284 *long_mask = 0;
1285
676574df 1286 for_each_hpd_pin(i) {
8c841e57
JN		 1287 if ((hpd[i] & hotplug_trigger) == 0)
1288 continue;
676574df 1289
8c841e57
JN		 1290 *pin_mask |= BIT(i);
1291
cc24fcdc
ID		 1292 if (!intel_hpd_pin_to_port(i, &port))
1293 continue;
1294
fd63e2a9 1295 if (long_pulse_detect(port, dig_hotplug_reg))
8c841e57 1296 *long_mask |= BIT(i);
676574df
JN		 1297 }
1298
1299 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1300 hotplug_trigger, dig_hotplug_reg, *pin_mask);
1301
1302}
1303
515ac2bb
DV		 1304static void gmbus_irq_handler(struct drm_device *dev)
1305{
2d1013dd 1306 struct drm_i915_private *dev_priv = dev->dev_private;
28c70f16 1307
28c70f16 1308 wake_up_all(&dev_priv->gmbus_wait_queue);
515ac2bb
DV		 1309}
1310
ce99c256
DV		 1311static void dp_aux_irq_handler(struct drm_device *dev)
1312{
2d1013dd 1313 struct drm_i915_private *dev_priv = dev->dev_private;
9ee32fea 1314
9ee32fea 1315 wake_up_all(&dev_priv->gmbus_wait_queue);
ce99c256
DV		 1316}
1317
8bf1e9f1 1318#if defined(CONFIG_DEBUG_FS)
277de95e
DV		 1319static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1320 uint32_t crc0, uint32_t crc1,
1321 uint32_t crc2, uint32_t crc3,
1322 uint32_t crc4)
8bf1e9f1
SH		 1323{
1324 struct drm_i915_private *dev_priv = dev->dev_private;
1325 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1326 struct intel_pipe_crc_entry *entry;
ac2300d4 1327 int head, tail;
b2c88f5b 1328
d538bbdf
DL		 1329 spin_lock(&pipe_crc->lock);
1330
0c912c79 1331 if (!pipe_crc->entries) {
d538bbdf 1332 spin_unlock(&pipe_crc->lock);
34273620 1333 DRM_DEBUG_KMS("spurious interrupt\n");
0c912c79
DL		 1334 return;
1335 }
1336
d538bbdf
DL		 1337 head = pipe_crc->head;
1338 tail = pipe_crc->tail;
b2c88f5b
DL		 1339
1340 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
d538bbdf 1341 spin_unlock(&pipe_crc->lock);
b2c88f5b
DL		 1342 DRM_ERROR("CRC buffer overflowing\n");
1343 return;
1344 }
1345
1346 entry = &pipe_crc->entries[head];
8bf1e9f1 1347
8bc5e955 1348 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
eba94eb9
DV		 1349 entry->crc[0] = crc0;
1350 entry->crc[1] = crc1;
1351 entry->crc[2] = crc2;
1352 entry->crc[3] = crc3;
1353 entry->crc[4] = crc4;
b2c88f5b
DL		 1354
1355 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
d538bbdf
DL		 1356 pipe_crc->head = head;
1357
1358 spin_unlock(&pipe_crc->lock);
07144428
DL		 1359
1360 wake_up_interruptible(&pipe_crc->wq);
8bf1e9f1 1361}
277de95e
DV		 1362#else
1363static inline void
1364display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1365 uint32_t crc0, uint32_t crc1,
1366 uint32_t crc2, uint32_t crc3,
1367 uint32_t crc4) {}
1368#endif
1369
eba94eb9 1370
277de95e 1371static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
5a69b89f
DV		 1372{
1373 struct drm_i915_private *dev_priv = dev->dev_private;
1374
277de95e
DV		 1375 display_pipe_crc_irq_handler(dev, pipe,
1376 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1377 0, 0, 0, 0);
5a69b89f
DV		 1378}
1379
277de95e 1380static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
eba94eb9
DV		 1381{
1382 struct drm_i915_private *dev_priv = dev->dev_private;
1383
277de95e
DV		 1384 display_pipe_crc_irq_handler(dev, pipe,
1385 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1386 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1387 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1388 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1389 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
eba94eb9 1390}
5b3a856b 1391
277de95e 1392static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
5b3a856b
DV		 1393{
1394 struct drm_i915_private *dev_priv = dev->dev_private;
0b5c5ed0
DV		 1395 uint32_t res1, res2;
1396
1397 if (INTEL_INFO(dev)->gen >= 3)
1398 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1399 else
1400 res1 = 0;
1401
1402 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1403 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1404 else
1405 res2 = 0;
5b3a856b 1406
277de95e
DV		 1407 display_pipe_crc_irq_handler(dev, pipe,
1408 I915_READ(PIPE_CRC_RES_RED(pipe)),
1409 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1410 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1411 res1, res2);
5b3a856b 1412}
8bf1e9f1 1413
1403c0d4
PZ		 1414/* The RPS events need forcewake, so we add them to a work queue and mask their
1415 * IMR bits until the work is done. Other interrupts can be processed without
1416 * the work queue. */
1417static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
baf02a1f 1418{
a6706b45 1419 if (pm_iir & dev_priv->pm_rps_events) {
59cdb63d 1420 spin_lock(&dev_priv->irq_lock);
480c8033 1421 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
d4d70aa5
ID		 1422 if (dev_priv->rps.interrupts_enabled) {
1423 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1424 queue_work(dev_priv->wq, &dev_priv->rps.work);
1425 }
59cdb63d 1426 spin_unlock(&dev_priv->irq_lock);
baf02a1f 1427 }
baf02a1f 1428
c9a9a268
ID		 1429 if (INTEL_INFO(dev_priv)->gen >= 8)
1430 return;
1431
1403c0d4
PZ		 1432 if (HAS_VEBOX(dev_priv->dev)) {
1433 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
74cdb337 1434 notify_ring(&dev_priv->ring[VECS]);
12638c57 1435
aaecdf61
DV		 1436 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1437 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
12638c57 1438 }
baf02a1f
BW		 1439}
1440
8d7849db
VS		 1441static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
1442{
8d7849db
VS		 1443 if (!drm_handle_vblank(dev, pipe))
1444 return false;
1445
8d7849db
VS		 1446 return true;
1447}
1448
c1874ed7
ID		 1449static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1450{
1451 struct drm_i915_private *dev_priv = dev->dev_private;
91d181dd 1452 u32 pipe_stats[I915_MAX_PIPES] = { };
c1874ed7
ID		 1453 int pipe;
1454
58ead0d7 1455 spin_lock(&dev_priv->irq_lock);
055e393f 1456 for_each_pipe(dev_priv, pipe) {
91d181dd 1457 int reg;
bbb5eebf 1458 u32 mask, iir_bit = 0;
91d181dd 1459
bbb5eebf
DV		 1460 /*
1461 * PIPESTAT bits get signalled even when the interrupt is
1462 * disabled with the mask bits, and some of the status bits do
1463 * not generate interrupts at all (like the underrun bit). Hence
1464 * we need to be careful that we only handle what we want to
1465 * handle.
1466 */
0f239f4c
DV		 1467
1468 /* fifo underruns are filterered in the underrun handler. */
1469 mask = PIPE_FIFO_UNDERRUN_STATUS;
bbb5eebf
DV		 1470
1471 switch (pipe) {
1472 case PIPE_A:
1473 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1474 break;
1475 case PIPE_B:
1476 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1477 break;
3278f67f
VS		 1478 case PIPE_C:
1479 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1480 break;
bbb5eebf
DV		 1481 }
1482 if (iir & iir_bit)
1483 mask |= dev_priv->pipestat_irq_mask[pipe];
1484
1485 if (!mask)
91d181dd
ID		 1486 continue;
1487
1488 reg = PIPESTAT(pipe);
bbb5eebf
DV		 1489 mask |= PIPESTAT_INT_ENABLE_MASK;
1490 pipe_stats[pipe] = I915_READ(reg) & mask;
c1874ed7
ID		 1491
1492 /*
1493 * Clear the PIPE*STAT regs before the IIR
1494 */
91d181dd
ID		 1495 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1496 PIPESTAT_INT_STATUS_MASK))
c1874ed7
ID		 1497 I915_WRITE(reg, pipe_stats[pipe]);
1498 }
58ead0d7 1499 spin_unlock(&dev_priv->irq_lock);
c1874ed7 1500
055e393f 1501 for_each_pipe(dev_priv, pipe) {
d6bbafa1
CW		 1502 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1503 intel_pipe_handle_vblank(dev, pipe))
1504 intel_check_page_flip(dev, pipe);
c1874ed7 1505
579a9b0e 1506 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
c1874ed7
ID		 1507 intel_prepare_page_flip(dev, pipe);
1508 intel_finish_page_flip(dev, pipe);
1509 }
1510
1511 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1512 i9xx_pipe_crc_irq_handler(dev, pipe);
1513
1f7247c0
DV		 1514 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1515 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
c1874ed7
ID		 1516 }
1517
1518 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1519 gmbus_irq_handler(dev);
1520}
1521
16c6c56b
VS		 1522static void i9xx_hpd_irq_handler(struct drm_device *dev)
1523{
1524 struct drm_i915_private *dev_priv = dev->dev_private;
1525 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
676574df 1526 u32 pin_mask, long_mask;
16c6c56b 1527
0d2e4297
JN		 1528 if (!hotplug_status)
1529 return;
16c6c56b 1530
0d2e4297
JN		 1531 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1532 /*
1533 * Make sure hotplug status is cleared before we clear IIR, or else we
1534 * may miss hotplug events.
1535 */
1536 POSTING_READ(PORT_HOTPLUG_STAT);
16c6c56b 1537
0d2e4297
JN		 1538 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
1539 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
16c6c56b 1540
fd63e2a9
ID		 1541 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1542 hotplug_trigger, hpd_status_g4x,
1543 i9xx_port_hotplug_long_detect);
676574df 1544 intel_hpd_irq_handler(dev, pin_mask, long_mask);
369712e8
JN		 1545
1546 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1547 dp_aux_irq_handler(dev);
0d2e4297
JN		 1548 } else {
1549 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
16c6c56b 1550
fd63e2a9
ID		 1551 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1552 hotplug_trigger, hpd_status_g4x,
1553 i9xx_port_hotplug_long_detect);
676574df 1554 intel_hpd_irq_handler(dev, pin_mask, long_mask);
3ff60f89 1555 }
16c6c56b
VS		 1556}
1557
ff1f525e 1558static irqreturn_t valleyview_irq_handler(int irq, void *arg)
7e231dbe 1559{
45a83f84 1560 struct drm_device *dev = arg;
2d1013dd 1561 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe
JB		 1562 u32 iir, gt_iir, pm_iir;
1563 irqreturn_t ret = IRQ_NONE;
7e231dbe 1564
2dd2a883
ID		 1565 if (!intel_irqs_enabled(dev_priv))
1566 return IRQ_NONE;
1567
7e231dbe 1568 while (true) {
3ff60f89
OM		 1569 /* Find, clear, then process each source of interrupt */
1570
7e231dbe 1571 gt_iir = I915_READ(GTIIR);
3ff60f89
OM		 1572 if (gt_iir)
1573 I915_WRITE(GTIIR, gt_iir);
1574
7e231dbe 1575 pm_iir = I915_READ(GEN6_PMIIR);
3ff60f89
OM		 1576 if (pm_iir)
1577 I915_WRITE(GEN6_PMIIR, pm_iir);
1578
1579 iir = I915_READ(VLV_IIR);
1580 if (iir) {
1581 /* Consume port before clearing IIR or we'll miss events */
1582 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1583 i9xx_hpd_irq_handler(dev);
1584 I915_WRITE(VLV_IIR, iir);
1585 }
7e231dbe
JB		 1586
1587 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1588 goto out;
1589
1590 ret = IRQ_HANDLED;
1591
3ff60f89
OM		 1592 if (gt_iir)
1593 snb_gt_irq_handler(dev, dev_priv, gt_iir);
60611c13 1594 if (pm_iir)
d0ecd7e2 1595 gen6_rps_irq_handler(dev_priv, pm_iir);
3ff60f89
OM		 1596 /* Call regardless, as some status bits might not be
1597 * signalled in iir */
1598 valleyview_pipestat_irq_handler(dev, iir);
7e231dbe
JB		 1599 }
1600
1601out:
1602 return ret;
1603}
1604
43f328d7
VS		 1605static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1606{
45a83f84 1607 struct drm_device *dev = arg;
43f328d7
VS		 1608 struct drm_i915_private *dev_priv = dev->dev_private;
1609 u32 master_ctl, iir;
1610 irqreturn_t ret = IRQ_NONE;
43f328d7 1611
2dd2a883
ID		 1612 if (!intel_irqs_enabled(dev_priv))
1613 return IRQ_NONE;
1614
8e5fd599
VS		 1615 for (;;) {
1616 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1617 iir = I915_READ(VLV_IIR);
43f328d7 1618
8e5fd599
VS		 1619 if (master_ctl == 0 && iir == 0)
1620 break;
43f328d7 1621
27b6c122
OM		 1622 ret = IRQ_HANDLED;
1623
8e5fd599 1624 I915_WRITE(GEN8_MASTER_IRQ, 0);
43f328d7 1625
27b6c122 1626 /* Find, clear, then process each source of interrupt */
43f328d7 1627
27b6c122
OM		 1628 if (iir) {
1629 /* Consume port before clearing IIR or we'll miss events */
1630 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1631 i9xx_hpd_irq_handler(dev);
1632 I915_WRITE(VLV_IIR, iir);
1633 }
43f328d7 1634
74cdb337 1635 gen8_gt_irq_handler(dev_priv, master_ctl);
43f328d7 1636
27b6c122
OM		 1637 /* Call regardless, as some status bits might not be
1638 * signalled in iir */
1639 valleyview_pipestat_irq_handler(dev, iir);
43f328d7 1640
8e5fd599
VS		 1641 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
1642 POSTING_READ(GEN8_MASTER_IRQ);
8e5fd599 1643 }
3278f67f 1644
43f328d7
VS		 1645 return ret;
1646}
1647
23e81d69 1648static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806 1649{
2d1013dd 1650 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 1651 int pipe;
b543fb04 1652 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
13cf5504 1653
aaf5ec2e
SJ		 1654 if (hotplug_trigger) {
1655 u32 dig_hotplug_reg, pin_mask, long_mask;
1656
1657 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1658 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
776ad806 1659
fd63e2a9
ID		 1660 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1661 dig_hotplug_reg, hpd_ibx,
1662 pch_port_hotplug_long_detect);
aaf5ec2e
SJ		 1663 intel_hpd_irq_handler(dev, pin_mask, long_mask);
1664 }
91d131d2 1665
cfc33bf7
VS		 1666 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1667 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1668 SDE_AUDIO_POWER_SHIFT);
776ad806 1669 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
cfc33bf7
VS		 1670 port_name(port));
1671 }
776ad806 1672
ce99c256
DV		 1673 if (pch_iir & SDE_AUX_MASK)
1674 dp_aux_irq_handler(dev);
1675
776ad806 1676 if (pch_iir & SDE_GMBUS)
515ac2bb 1677 gmbus_irq_handler(dev);
776ad806
JB		 1678
1679 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1680 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1681
1682 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1683 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1684
1685 if (pch_iir & SDE_POISON)
1686 DRM_ERROR("PCH poison interrupt\n");
1687
9db4a9c7 1688 if (pch_iir & SDE_FDI_MASK)
055e393f 1689 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 1690 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1691 pipe_name(pipe),
1692 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 1693
1694 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1695 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1696
1697 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1698 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1699
776ad806 1700 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1f7247c0 1701 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
8664281b
PZ		 1702
1703 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1f7247c0 1704 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
8664281b
PZ		 1705}
1706
1707static void ivb_err_int_handler(struct drm_device *dev)
1708{
1709 struct drm_i915_private *dev_priv = dev->dev_private;
1710 u32 err_int = I915_READ(GEN7_ERR_INT);
5a69b89f 1711 enum pipe pipe;
8664281b 1712
de032bf4
PZ		 1713 if (err_int & ERR_INT_POISON)
1714 DRM_ERROR("Poison interrupt\n");
1715
055e393f 1716 for_each_pipe(dev_priv, pipe) {
1f7247c0
DV		 1717 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
1718 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
8bf1e9f1 1719
5a69b89f
DV		 1720 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1721 if (IS_IVYBRIDGE(dev))
277de95e 1722 ivb_pipe_crc_irq_handler(dev, pipe);
5a69b89f 1723 else
277de95e 1724 hsw_pipe_crc_irq_handler(dev, pipe);
5a69b89f
DV		 1725 }
1726 }
8bf1e9f1 1727
8664281b
PZ		 1728 I915_WRITE(GEN7_ERR_INT, err_int);
1729}
1730
1731static void cpt_serr_int_handler(struct drm_device *dev)
1732{
1733 struct drm_i915_private *dev_priv = dev->dev_private;
1734 u32 serr_int = I915_READ(SERR_INT);
1735
de032bf4
PZ		 1736 if (serr_int & SERR_INT_POISON)
1737 DRM_ERROR("PCH poison interrupt\n");
1738
8664281b 1739 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1f7247c0 1740 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
8664281b
PZ		 1741
1742 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1f7247c0 1743 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
8664281b
PZ		 1744
1745 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1f7247c0 1746 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
8664281b
PZ		 1747
1748 I915_WRITE(SERR_INT, serr_int);
776ad806
JB		 1749}
1750
23e81d69
AJ		 1751static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1752{
2d1013dd 1753 struct drm_i915_private *dev_priv = dev->dev_private;
23e81d69 1754 int pipe;
b543fb04 1755 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
13cf5504 1756
aaf5ec2e
SJ		 1757 if (hotplug_trigger) {
1758 u32 dig_hotplug_reg, pin_mask, long_mask;
23e81d69 1759
aaf5ec2e
SJ		 1760 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1761 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
fd63e2a9
ID		 1762
1763 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1764 dig_hotplug_reg, hpd_cpt,
1765 pch_port_hotplug_long_detect);
aaf5ec2e
SJ		 1766 intel_hpd_irq_handler(dev, pin_mask, long_mask);
1767 }
91d131d2 1768
cfc33bf7
VS		 1769 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1770 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1771 SDE_AUDIO_POWER_SHIFT_CPT);
1772 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1773 port_name(port));
1774 }
23e81d69
AJ		 1775
1776 if (pch_iir & SDE_AUX_MASK_CPT)
ce99c256 1777 dp_aux_irq_handler(dev);
23e81d69
AJ		 1778
1779 if (pch_iir & SDE_GMBUS_CPT)
515ac2bb 1780 gmbus_irq_handler(dev);
23e81d69
AJ		 1781
1782 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1783 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1784
1785 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1786 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1787
1788 if (pch_iir & SDE_FDI_MASK_CPT)
055e393f 1789 for_each_pipe(dev_priv, pipe)
23e81d69
AJ		 1790 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1791 pipe_name(pipe),
1792 I915_READ(FDI_RX_IIR(pipe)));
8664281b
PZ		 1793
1794 if (pch_iir & SDE_ERROR_CPT)
1795 cpt_serr_int_handler(dev);
23e81d69
AJ		 1796}
1797
c008bc6e
PZ		 1798static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1799{
1800 struct drm_i915_private *dev_priv = dev->dev_private;
40da17c2 1801 enum pipe pipe;
c008bc6e
PZ		 1802
1803 if (de_iir & DE_AUX_CHANNEL_A)
1804 dp_aux_irq_handler(dev);
1805
1806 if (de_iir & DE_GSE)
1807 intel_opregion_asle_intr(dev);
1808
c008bc6e
PZ		 1809 if (de_iir & DE_POISON)
1810 DRM_ERROR("Poison interrupt\n");
1811
055e393f 1812 for_each_pipe(dev_priv, pipe) {
d6bbafa1
CW		 1813 if (de_iir & DE_PIPE_VBLANK(pipe) &&
1814 intel_pipe_handle_vblank(dev, pipe))
1815 intel_check_page_flip(dev, pipe);
5b3a856b 1816
40da17c2 1817 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
1f7247c0 1818 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
5b3a856b 1819
40da17c2
DV		 1820 if (de_iir & DE_PIPE_CRC_DONE(pipe))
1821 i9xx_pipe_crc_irq_handler(dev, pipe);
c008bc6e 1822
40da17c2
DV		 1823 /* plane/pipes map 1:1 on ilk+ */
1824 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
1825 intel_prepare_page_flip(dev, pipe);
1826 intel_finish_page_flip_plane(dev, pipe);
1827 }
c008bc6e
PZ		 1828 }
1829
1830 /* check event from PCH */
1831 if (de_iir & DE_PCH_EVENT) {
1832 u32 pch_iir = I915_READ(SDEIIR);
1833
1834 if (HAS_PCH_CPT(dev))
1835 cpt_irq_handler(dev, pch_iir);
1836 else
1837 ibx_irq_handler(dev, pch_iir);
1838
1839 /* should clear PCH hotplug event before clear CPU irq */
1840 I915_WRITE(SDEIIR, pch_iir);
1841 }
1842
1843 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1844 ironlake_rps_change_irq_handler(dev);
1845}
1846
9719fb98
PZ		 1847static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
1848{
1849 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 1850 enum pipe pipe;
9719fb98
PZ		 1851
1852 if (de_iir & DE_ERR_INT_IVB)
1853 ivb_err_int_handler(dev);
1854
1855 if (de_iir & DE_AUX_CHANNEL_A_IVB)
1856 dp_aux_irq_handler(dev);
1857
1858 if (de_iir & DE_GSE_IVB)
1859 intel_opregion_asle_intr(dev);
1860
055e393f 1861 for_each_pipe(dev_priv, pipe) {
d6bbafa1
CW		 1862 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
1863 intel_pipe_handle_vblank(dev, pipe))
1864 intel_check_page_flip(dev, pipe);
40da17c2
DV		 1865
1866 /* plane/pipes map 1:1 on ilk+ */
07d27e20
DL		 1867 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
1868 intel_prepare_page_flip(dev, pipe);
1869 intel_finish_page_flip_plane(dev, pipe);
9719fb98
PZ		 1870 }
1871 }
1872
1873 /* check event from PCH */
1874 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1875 u32 pch_iir = I915_READ(SDEIIR);
1876
1877 cpt_irq_handler(dev, pch_iir);
1878
1879 /* clear PCH hotplug event before clear CPU irq */
1880 I915_WRITE(SDEIIR, pch_iir);
1881 }
1882}
1883
72c90f62
OM		 1884/*
1885 * To handle irqs with the minimum potential races with fresh interrupts, we:
1886 * 1 - Disable Master Interrupt Control.
1887 * 2 - Find the source(s) of the interrupt.
1888 * 3 - Clear the Interrupt Identity bits (IIR).
1889 * 4 - Process the interrupt(s) that had bits set in the IIRs.
1890 * 5 - Re-enable Master Interrupt Control.
1891 */
f1af8fc1 1892static irqreturn_t ironlake_irq_handler(int irq, void *arg)
b1f14ad0 1893{
45a83f84 1894 struct drm_device *dev = arg;
2d1013dd 1895 struct drm_i915_private *dev_priv = dev->dev_private;
f1af8fc1 1896 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
0e43406b 1897 irqreturn_t ret = IRQ_NONE;
b1f14ad0 1898
2dd2a883
ID		 1899 if (!intel_irqs_enabled(dev_priv))
1900 return IRQ_NONE;
1901
8664281b
PZ		 1902 /* We get interrupts on unclaimed registers, so check for this before we
1903 * do any I915_{READ,WRITE}. */
907b28c5 1904 intel_uncore_check_errors(dev);
8664281b 1905
b1f14ad0
JB		 1906 /* disable master interrupt before clearing iir */
1907 de_ier = I915_READ(DEIER);
1908 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
23a78516 1909 POSTING_READ(DEIER);
b1f14ad0 1910
44498aea
PZ		 1911 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1912 * interrupts will will be stored on its back queue, and then we'll be
1913 * able to process them after we restore SDEIER (as soon as we restore
1914 * it, we'll get an interrupt if SDEIIR still has something to process
1915 * due to its back queue). */
ab5c608b
BW		 1916 if (!HAS_PCH_NOP(dev)) {
1917 sde_ier = I915_READ(SDEIER);
1918 I915_WRITE(SDEIER, 0);
1919 POSTING_READ(SDEIER);
1920 }
44498aea 1921
72c90f62
OM		 1922 /* Find, clear, then process each source of interrupt */
1923
b1f14ad0 1924 gt_iir = I915_READ(GTIIR);
0e43406b 1925 if (gt_iir) {
72c90f62
OM		 1926 I915_WRITE(GTIIR, gt_iir);
1927 ret = IRQ_HANDLED;
d8fc8a47 1928 if (INTEL_INFO(dev)->gen >= 6)
f1af8fc1 1929 snb_gt_irq_handler(dev, dev_priv, gt_iir);
d8fc8a47
PZ		 1930 else
1931 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
b1f14ad0
JB		 1932 }
1933
0e43406b
CW		 1934 de_iir = I915_READ(DEIIR);
1935 if (de_iir) {
72c90f62
OM		 1936 I915_WRITE(DEIIR, de_iir);
1937 ret = IRQ_HANDLED;
f1af8fc1
PZ		 1938 if (INTEL_INFO(dev)->gen >= 7)
1939 ivb_display_irq_handler(dev, de_iir);
1940 else
1941 ilk_display_irq_handler(dev, de_iir);
b1f14ad0
JB		 1942 }
1943
f1af8fc1
PZ		 1944 if (INTEL_INFO(dev)->gen >= 6) {
1945 u32 pm_iir = I915_READ(GEN6_PMIIR);
1946 if (pm_iir) {
f1af8fc1
PZ		 1947 I915_WRITE(GEN6_PMIIR, pm_iir);
1948 ret = IRQ_HANDLED;
72c90f62 1949 gen6_rps_irq_handler(dev_priv, pm_iir);
f1af8fc1 1950 }
0e43406b 1951 }
b1f14ad0 1952
b1f14ad0
JB		 1953 I915_WRITE(DEIER, de_ier);
1954 POSTING_READ(DEIER);
ab5c608b
BW		 1955 if (!HAS_PCH_NOP(dev)) {
1956 I915_WRITE(SDEIER, sde_ier);
1957 POSTING_READ(SDEIER);
1958 }
b1f14ad0
JB		 1959
1960 return ret;
1961}
1962
d04a492d
SS		 1963static void bxt_hpd_handler(struct drm_device *dev, uint32_t iir_status)
1964{
1965 struct drm_i915_private *dev_priv = dev->dev_private;
676574df
JN		 1966 u32 hp_control, hp_trigger;
1967 u32 pin_mask, long_mask;
d04a492d
SS		 1968
1969 /* Get the status */
1970 hp_trigger = iir_status & BXT_DE_PORT_HOTPLUG_MASK;
1971 hp_control = I915_READ(BXT_HOTPLUG_CTL);
1972
1973 /* Hotplug not enabled ? */
1974 if (!(hp_control & BXT_HOTPLUG_CTL_MASK)) {
1975 DRM_ERROR("Interrupt when HPD disabled\n");
1976 return;
1977 }
1978
475c2e3b
JN		 1979 /* Clear sticky bits in hpd status */
1980 I915_WRITE(BXT_HOTPLUG_CTL, hp_control);
d04a492d 1981
fd63e2a9 1982 intel_get_hpd_pins(&pin_mask, &long_mask, hp_trigger, hp_control,
63c88d22 1983 hpd_bxt, bxt_port_hotplug_long_detect);
676574df 1984 intel_hpd_irq_handler(dev, pin_mask, long_mask);
d04a492d
SS		 1985}
1986
abd58f01
BW		 1987static irqreturn_t gen8_irq_handler(int irq, void *arg)
1988{
1989 struct drm_device *dev = arg;
1990 struct drm_i915_private *dev_priv = dev->dev_private;
1991 u32 master_ctl;
1992 irqreturn_t ret = IRQ_NONE;
1993 uint32_t tmp = 0;
c42664cc 1994 enum pipe pipe;
88e04703
JB		 1995 u32 aux_mask = GEN8_AUX_CHANNEL_A;
1996
2dd2a883
ID		 1997 if (!intel_irqs_enabled(dev_priv))
1998 return IRQ_NONE;
1999
88e04703
JB		 2000 if (IS_GEN9(dev))
2001 aux_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
2002 GEN9_AUX_CHANNEL_D;
abd58f01 2003
cb0d205e 2004 master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
abd58f01
BW		 2005 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2006 if (!master_ctl)
2007 return IRQ_NONE;
2008
cb0d205e 2009 I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
abd58f01 2010
38cc46d7
OM		 2011 /* Find, clear, then process each source of interrupt */
2012
74cdb337 2013 ret = gen8_gt_irq_handler(dev_priv, master_ctl);
abd58f01
BW		 2014
2015 if (master_ctl & GEN8_DE_MISC_IRQ) {
2016 tmp = I915_READ(GEN8_DE_MISC_IIR);
abd58f01
BW		 2017 if (tmp) {
2018 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2019 ret = IRQ_HANDLED;
38cc46d7
OM		 2020 if (tmp & GEN8_DE_MISC_GSE)
2021 intel_opregion_asle_intr(dev);
2022 else
2023 DRM_ERROR("Unexpected DE Misc interrupt\n");
abd58f01 2024 }
38cc46d7
OM		 2025 else
2026 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
abd58f01
BW		 2027 }
2028
6d766f02
DV		 2029 if (master_ctl & GEN8_DE_PORT_IRQ) {
2030 tmp = I915_READ(GEN8_DE_PORT_IIR);
6d766f02 2031 if (tmp) {
d04a492d
SS		 2032 bool found = false;
2033
6d766f02
DV		 2034 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2035 ret = IRQ_HANDLED;
88e04703 2036
d04a492d 2037 if (tmp & aux_mask) {
38cc46d7 2038 dp_aux_irq_handler(dev);
d04a492d
SS		 2039 found = true;
2040 }
2041
2042 if (IS_BROXTON(dev) && tmp & BXT_DE_PORT_HOTPLUG_MASK) {
2043 bxt_hpd_handler(dev, tmp);
2044 found = true;
2045 }
2046
9e63743e
SS		 2047 if (IS_BROXTON(dev) && (tmp & BXT_DE_PORT_GMBUS)) {
2048 gmbus_irq_handler(dev);
2049 found = true;
2050 }
2051
d04a492d 2052 if (!found)
38cc46d7 2053 DRM_ERROR("Unexpected DE Port interrupt\n");
6d766f02 2054 }
38cc46d7
OM		 2055 else
2056 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
6d766f02
DV		 2057 }
2058
055e393f 2059 for_each_pipe(dev_priv, pipe) {
770de83d 2060 uint32_t pipe_iir, flip_done = 0, fault_errors = 0;
abd58f01 2061
c42664cc
DV		 2062 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2063 continue;
abd58f01 2064
c42664cc 2065 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
c42664cc
DV		 2066 if (pipe_iir) {
2067 ret = IRQ_HANDLED;
2068 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
770de83d 2069
d6bbafa1
CW		 2070 if (pipe_iir & GEN8_PIPE_VBLANK &&
2071 intel_pipe_handle_vblank(dev, pipe))
2072 intel_check_page_flip(dev, pipe);
38cc46d7 2073
770de83d
DL		 2074 if (IS_GEN9(dev))
2075 flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE;
2076 else
2077 flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE;
2078
2079 if (flip_done) {
38cc46d7
OM		 2080 intel_prepare_page_flip(dev, pipe);
2081 intel_finish_page_flip_plane(dev, pipe);
2082 }
2083
2084 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2085 hsw_pipe_crc_irq_handler(dev, pipe);
2086
1f7247c0
DV		 2087 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN)
2088 intel_cpu_fifo_underrun_irq_handler(dev_priv,
2089 pipe);
38cc46d7 2090
770de83d
DL		 2091
2092 if (IS_GEN9(dev))
2093 fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2094 else
2095 fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2096
2097 if (fault_errors)
38cc46d7
OM		 2098 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2099 pipe_name(pipe),
2100 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
c42664cc 2101 } else
abd58f01
BW		 2102 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2103 }
2104
266ea3d9
SS		 2105 if (HAS_PCH_SPLIT(dev) && !HAS_PCH_NOP(dev) &&
2106 master_ctl & GEN8_DE_PCH_IRQ) {
92d03a80
DV		 2107 /*
2108 * FIXME(BDW): Assume for now that the new interrupt handling
2109 * scheme also closed the SDE interrupt handling race we've seen
2110 * on older pch-split platforms. But this needs testing.
2111 */
2112 u32 pch_iir = I915_READ(SDEIIR);
92d03a80
DV		 2113 if (pch_iir) {
2114 I915_WRITE(SDEIIR, pch_iir);
2115 ret = IRQ_HANDLED;
38cc46d7
OM		 2116 cpt_irq_handler(dev, pch_iir);
2117 } else
2118 DRM_ERROR("The master control interrupt lied (SDE)!\n");
2119
92d03a80
DV		 2120 }
2121
cb0d205e
CW		 2122 I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2123 POSTING_READ_FW(GEN8_MASTER_IRQ);
abd58f01
BW		 2124
2125 return ret;
2126}
2127
17e1df07
DV		 2128static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2129 bool reset_completed)
2130{
a4872ba6 2131 struct intel_engine_cs *ring;
17e1df07
DV		 2132 int i;
2133
2134 /*
2135 * Notify all waiters for GPU completion events that reset state has
2136 * been changed, and that they need to restart their wait after
2137 * checking for potential errors (and bail out to drop locks if there is
2138 * a gpu reset pending so that i915_error_work_func can acquire them).
2139 */
2140
2141 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2142 for_each_ring(ring, dev_priv, i)
2143 wake_up_all(&ring->irq_queue);
2144
2145 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2146 wake_up_all(&dev_priv->pending_flip_queue);
2147
2148 /*
2149 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2150 * reset state is cleared.
2151 */
2152 if (reset_completed)
2153 wake_up_all(&dev_priv->gpu_error.reset_queue);
2154}
2155
8a905236 2156/**
b8d24a06 2157 * i915_reset_and_wakeup - do process context error handling work
8a905236
JB		 2158 *
2159 * Fire an error uevent so userspace can see that a hang or error
2160 * was detected.
2161 */
b8d24a06 2162static void i915_reset_and_wakeup(struct drm_device *dev)
8a905236 2163{
b8d24a06
MK		 2164 struct drm_i915_private *dev_priv = to_i915(dev);
2165 struct i915_gpu_error *error = &dev_priv->gpu_error;
cce723ed
BW		 2166 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2167 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2168 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
17e1df07 2169 int ret;
8a905236 2170
5bdebb18 2171 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
f316a42c 2172
7db0ba24
DV		 2173 /*
2174 * Note that there's only one work item which does gpu resets, so we
2175 * need not worry about concurrent gpu resets potentially incrementing
2176 * error->reset_counter twice. We only need to take care of another
2177 * racing irq/hangcheck declaring the gpu dead for a second time. A
2178 * quick check for that is good enough: schedule_work ensures the
2179 * correct ordering between hang detection and this work item, and since
2180 * the reset in-progress bit is only ever set by code outside of this
2181 * work we don't need to worry about any other races.
2182 */
2183 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
f803aa55 2184 DRM_DEBUG_DRIVER("resetting chip\n");
5bdebb18 2185 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
7db0ba24 2186 reset_event);
1f83fee0 2187
f454c694
ID		 2188 /*
2189 * In most cases it's guaranteed that we get here with an RPM
2190 * reference held, for example because there is a pending GPU
2191 * request that won't finish until the reset is done. This
2192 * isn't the case at least when we get here by doing a
2193 * simulated reset via debugs, so get an RPM reference.
2194 */
2195 intel_runtime_pm_get(dev_priv);
7514747d
VS		 2196
2197 intel_prepare_reset(dev);
2198
17e1df07
DV		 2199 /*
2200 * All state reset _must_ be completed before we update the
2201 * reset counter, for otherwise waiters might miss the reset
2202 * pending state and not properly drop locks, resulting in
2203 * deadlocks with the reset work.
2204 */
f69061be
DV		 2205 ret = i915_reset(dev);
2206
7514747d 2207 intel_finish_reset(dev);
17e1df07 2208
f454c694
ID		 2209 intel_runtime_pm_put(dev_priv);
2210
f69061be
DV		 2211 if (ret == 0) {
2212 /*
2213 * After all the gem state is reset, increment the reset
2214 * counter and wake up everyone waiting for the reset to
2215 * complete.
2216 *
2217 * Since unlock operations are a one-sided barrier only,
2218 * we need to insert a barrier here to order any seqno
2219 * updates before
2220 * the counter increment.
2221 */
4e857c58 2222 smp_mb__before_atomic();
f69061be
DV		 2223 atomic_inc(&dev_priv->gpu_error.reset_counter);
2224
5bdebb18 2225 kobject_uevent_env(&dev->primary->kdev->kobj,
f69061be 2226 KOBJ_CHANGE, reset_done_event);
1f83fee0 2227 } else {
2ac0f450 2228 atomic_set_mask(I915_WEDGED, &error->reset_counter);
f316a42c 2229 }
1f83fee0 2230
17e1df07
DV		 2231 /*
2232 * Note: The wake_up also serves as a memory barrier so that
2233 * waiters see the update value of the reset counter atomic_t.
2234 */
2235 i915_error_wake_up(dev_priv, true);
f316a42c 2236 }
8a905236
JB		 2237}
2238
35aed2e6 2239static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 2240{
2241 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 2242 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 2243 u32 eir = I915_READ(EIR);
050ee91f 2244 int pipe, i;
8a905236 2245
35aed2e6
CW		 2246 if (!eir)
2247 return;
8a905236 2248
a70491cc 2249 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 2250
bd9854f9
BW		 2251 i915_get_extra_instdone(dev, instdone);
2252
8a905236
JB		 2253 if (IS_G4X(dev)) {
2254 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2255 u32 ipeir = I915_READ(IPEIR_I965);
2256
a70491cc
JP		 2257 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2258 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 2259 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2260 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 2261 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 2262 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 2263 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 2264 POSTING_READ(IPEIR_I965);
8a905236
JB		 2265 }
2266 if (eir & GM45_ERROR_PAGE_TABLE) {
2267 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 2268 pr_err("page table error\n");
2269 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 2270 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 2271 POSTING_READ(PGTBL_ER);
8a905236
JB		 2272 }
2273 }
2274
a6c45cf0 2275 if (!IS_GEN2(dev)) {
8a905236
JB		 2276 if (eir & I915_ERROR_PAGE_TABLE) {
2277 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 2278 pr_err("page table error\n");
2279 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 2280 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 2281 POSTING_READ(PGTBL_ER);
8a905236
JB		 2282 }
2283 }
2284
2285 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 2286 pr_err("memory refresh error:\n");
055e393f 2287 for_each_pipe(dev_priv, pipe)
a70491cc 2288 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 2289 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 2290 /* pipestat has already been acked */
2291 }
2292 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 2293 pr_err("instruction error\n");
2294 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 2295 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2296 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 2297 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 2298 u32 ipeir = I915_READ(IPEIR);
2299
a70491cc
JP		 2300 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2301 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 2302 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 2303 I915_WRITE(IPEIR, ipeir);
3143a2bf 2304 POSTING_READ(IPEIR);
8a905236
JB		 2305 } else {
2306 u32 ipeir = I915_READ(IPEIR_I965);
2307
a70491cc
JP		 2308 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2309 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 2310 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 2311 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 2312 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 2313 POSTING_READ(IPEIR_I965);
8a905236
JB		 2314 }
2315 }
2316
2317 I915_WRITE(EIR, eir);
3143a2bf 2318 POSTING_READ(EIR);
8a905236
JB		 2319 eir = I915_READ(EIR);
2320 if (eir) {
2321 /*
2322 * some errors might have become stuck,
2323 * mask them.
2324 */
2325 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2326 I915_WRITE(EMR, I915_READ(EMR) | eir);
2327 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2328 }
35aed2e6
CW		 2329}
2330
2331/**
b8d24a06 2332 * i915_handle_error - handle a gpu error
35aed2e6
CW		 2333 * @dev: drm device
2334 *
b8d24a06 2335 * Do some basic checking of regsiter state at error time and
35aed2e6
CW		 2336 * dump it to the syslog. Also call i915_capture_error_state() to make
2337 * sure we get a record and make it available in debugfs. Fire a uevent
2338 * so userspace knows something bad happened (should trigger collection
2339 * of a ring dump etc.).
2340 */
58174462
MK		 2341void i915_handle_error(struct drm_device *dev, bool wedged,
2342 const char *fmt, ...)
35aed2e6
CW		 2343{
2344 struct drm_i915_private *dev_priv = dev->dev_private;
58174462
MK		 2345 va_list args;
2346 char error_msg[80];
35aed2e6 2347
58174462
MK		 2348 va_start(args, fmt);
2349 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2350 va_end(args);
2351
2352 i915_capture_error_state(dev, wedged, error_msg);
35aed2e6 2353 i915_report_and_clear_eir(dev);
8a905236 2354
ba1234d1 2355 if (wedged) {
f69061be
DV		 2356 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2357 &dev_priv->gpu_error.reset_counter);
ba1234d1 2358
11ed50ec 2359 /*
b8d24a06
MK		 2360 * Wakeup waiting processes so that the reset function
2361 * i915_reset_and_wakeup doesn't deadlock trying to grab
2362 * various locks. By bumping the reset counter first, the woken
17e1df07
DV		 2363 * processes will see a reset in progress and back off,
2364 * releasing their locks and then wait for the reset completion.
2365 * We must do this for _all_ gpu waiters that might hold locks
2366 * that the reset work needs to acquire.
2367 *
2368 * Note: The wake_up serves as the required memory barrier to
2369 * ensure that the waiters see the updated value of the reset
2370 * counter atomic_t.
11ed50ec 2371 */
17e1df07 2372 i915_error_wake_up(dev_priv, false);
11ed50ec
BG		 2373 }
2374
b8d24a06 2375 i915_reset_and_wakeup(dev);
8a905236
JB		 2376}
2377
42f52ef8
KP		 2378/* Called from drm generic code, passed 'crtc' which
2379 * we use as a pipe index
2380 */
f71d4af4 2381static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4 2382{
2d1013dd 2383 struct drm_i915_private *dev_priv = dev->dev_private;
e9d21d7f 2384 unsigned long irqflags;
71e0ffa5 2385
1ec14ad3 2386 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 2387 if (INTEL_INFO(dev)->gen >= 4)
7c463586 2388 i915_enable_pipestat(dev_priv, pipe,
755e9019 2389 PIPE_START_VBLANK_INTERRUPT_STATUS);
e9d21d7f 2390 else
7c463586 2391 i915_enable_pipestat(dev_priv, pipe,
755e9019 2392 PIPE_VBLANK_INTERRUPT_STATUS);
1ec14ad3 2393 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 2394
0a3e67a4
JB		 2395 return 0;
2396}
2397
f71d4af4 2398static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f 2399{
2d1013dd 2400 struct drm_i915_private *dev_priv = dev->dev_private;
f796cf8f 2401 unsigned long irqflags;
b518421f 2402 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
40da17c2 2403 DE_PIPE_VBLANK(pipe);
f796cf8f 2404
f796cf8f 2405 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b518421f 2406 ironlake_enable_display_irq(dev_priv, bit);
b1f14ad0
JB		 2407 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2408
2409 return 0;
2410}
2411
7e231dbe
JB		 2412static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2413{
2d1013dd 2414 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe 2415 unsigned long irqflags;
7e231dbe 2416
7e231dbe 2417 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5 2418 i915_enable_pipestat(dev_priv, pipe,
755e9019 2419 PIPE_START_VBLANK_INTERRUPT_STATUS);
7e231dbe
JB		 2420 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2421
2422 return 0;
2423}
2424
abd58f01
BW		 2425static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2426{
2427 struct drm_i915_private *dev_priv = dev->dev_private;
2428 unsigned long irqflags;
abd58f01 2429
abd58f01 2430 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7167d7c6
DV		 2431 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2432 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2433 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
abd58f01
BW		 2434 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2435 return 0;
2436}
2437
42f52ef8
KP		 2438/* Called from drm generic code, passed 'crtc' which
2439 * we use as a pipe index
2440 */
f71d4af4 2441static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4 2442{
2d1013dd 2443 struct drm_i915_private *dev_priv = dev->dev_private;
e9d21d7f 2444 unsigned long irqflags;
0a3e67a4 2445
1ec14ad3 2446 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 2447 i915_disable_pipestat(dev_priv, pipe,
755e9019
ID		 2448 PIPE_VBLANK_INTERRUPT_STATUS |
2449 PIPE_START_VBLANK_INTERRUPT_STATUS);
f796cf8f
JB		 2450 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2451}
2452
f71d4af4 2453static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f 2454{
2d1013dd 2455 struct drm_i915_private *dev_priv = dev->dev_private;
f796cf8f 2456 unsigned long irqflags;
b518421f 2457 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
40da17c2 2458 DE_PIPE_VBLANK(pipe);
f796cf8f
JB		 2459
2460 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b518421f 2461 ironlake_disable_display_irq(dev_priv, bit);
b1f14ad0
JB		 2462 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2463}
2464
7e231dbe
JB		 2465static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2466{
2d1013dd 2467 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe 2468 unsigned long irqflags;
7e231dbe
JB		 2469
2470 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5 2471 i915_disable_pipestat(dev_priv, pipe,
755e9019 2472 PIPE_START_VBLANK_INTERRUPT_STATUS);
7e231dbe
JB		 2473 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2474}
2475
abd58f01
BW		 2476static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2477{
2478 struct drm_i915_private *dev_priv = dev->dev_private;
2479 unsigned long irqflags;
abd58f01 2480
abd58f01 2481 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7167d7c6
DV		 2482 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2483 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2484 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
abd58f01
BW		 2485 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2486}
2487
9107e9d2 2488static bool
94f7bbe1 2489ring_idle(struct intel_engine_cs *ring, u32 seqno)
9107e9d2
CW		 2490{
2491 return (list_empty(&ring->request_list) ||
94f7bbe1 2492 i915_seqno_passed(seqno, ring->last_submitted_seqno));
f65d9421
BG		 2493}
2494
a028c4b0
DV		 2495static bool
2496ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2497{
2498 if (INTEL_INFO(dev)->gen >= 8) {
a6cdb93a 2499 return (ipehr >> 23) == 0x1c;
a028c4b0
DV		 2500 } else {
2501 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2502 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2503 MI_SEMAPHORE_REGISTER);
2504 }
2505}
2506
a4872ba6 2507static struct intel_engine_cs *
a6cdb93a 2508semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset)
921d42ea
DV		 2509{
2510 struct drm_i915_private *dev_priv = ring->dev->dev_private;
a4872ba6 2511 struct intel_engine_cs *signaller;
921d42ea
DV		 2512 int i;
2513
2514 if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
a6cdb93a
RV		 2515 for_each_ring(signaller, dev_priv, i) {
2516 if (ring == signaller)
2517 continue;
2518
2519 if (offset == signaller->semaphore.signal_ggtt[ring->id])
2520 return signaller;
2521 }
921d42ea
DV		 2522 } else {
2523 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2524
2525 for_each_ring(signaller, dev_priv, i) {
2526 if(ring == signaller)
2527 continue;
2528
ebc348b2 2529 if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
921d42ea
DV		 2530 return signaller;
2531 }
2532 }
2533
a6cdb93a
RV		 2534 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2535 ring->id, ipehr, offset);
921d42ea
DV		 2536
2537 return NULL;
2538}
2539
a4872ba6
OM		 2540static struct intel_engine_cs *
2541semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
a24a11e6
CW		 2542{
2543 struct drm_i915_private *dev_priv = ring->dev->dev_private;
88fe429d 2544 u32 cmd, ipehr, head;
a6cdb93a
RV		 2545 u64 offset = 0;
2546 int i, backwards;
a24a11e6
CW		 2547
2548 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
a028c4b0 2549 if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
6274f212 2550 return NULL;
a24a11e6 2551
88fe429d
DV		 2552 /*
2553 * HEAD is likely pointing to the dword after the actual command,
2554 * so scan backwards until we find the MBOX. But limit it to just 3
a6cdb93a
RV		 2555 * or 4 dwords depending on the semaphore wait command size.
2556 * Note that we don't care about ACTHD here since that might
88fe429d
DV		 2557 * point at at batch, and semaphores are always emitted into the
2558 * ringbuffer itself.
a24a11e6 2559 */
88fe429d 2560 head = I915_READ_HEAD(ring) & HEAD_ADDR;
a6cdb93a 2561 backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4;
88fe429d 2562
a6cdb93a 2563 for (i = backwards; i; --i) {
88fe429d
DV		 2564 /*
2565 * Be paranoid and presume the hw has gone off into the wild -
2566 * our ring is smaller than what the hardware (and hence
2567 * HEAD_ADDR) allows. Also handles wrap-around.
2568 */
ee1b1e5e 2569 head &= ring->buffer->size - 1;
88fe429d
DV		 2570
2571 /* This here seems to blow up */
ee1b1e5e 2572 cmd = ioread32(ring->buffer->virtual_start + head);
a24a11e6
CW		 2573 if (cmd == ipehr)
2574 break;
2575
88fe429d
DV		 2576 head -= 4;
2577 }
a24a11e6 2578
88fe429d
DV		 2579 if (!i)
2580 return NULL;
a24a11e6 2581
ee1b1e5e 2582 *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
a6cdb93a
RV		 2583 if (INTEL_INFO(ring->dev)->gen >= 8) {
2584 offset = ioread32(ring->buffer->virtual_start + head + 12);
2585 offset <<= 32;
2586 offset = ioread32(ring->buffer->virtual_start + head + 8);
2587 }
2588 return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
a24a11e6
CW		 2589}
2590
a4872ba6 2591static int semaphore_passed(struct intel_engine_cs *ring)
6274f212
CW		 2592{
2593 struct drm_i915_private *dev_priv = ring->dev->dev_private;
a4872ba6 2594 struct intel_engine_cs *signaller;
a0d036b0 2595 u32 seqno;
6274f212 2596
4be17381 2597 ring->hangcheck.deadlock++;
6274f212
CW		 2598
2599 signaller = semaphore_waits_for(ring, &seqno);
4be17381
CW		 2600 if (signaller == NULL)
2601 return -1;
2602
2603 /* Prevent pathological recursion due to driver bugs */
2604 if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
6274f212
CW		 2605 return -1;
2606
4be17381
CW		 2607 if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
2608 return 1;
2609
a0d036b0
CW		 2610 /* cursory check for an unkickable deadlock */
2611 if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2612 semaphore_passed(signaller) < 0)
4be17381
CW		 2613 return -1;
2614
2615 return 0;
6274f212
CW		 2616}
2617
2618static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2619{
a4872ba6 2620 struct intel_engine_cs *ring;
6274f212
CW		 2621 int i;
2622
2623 for_each_ring(ring, dev_priv, i)
4be17381 2624 ring->hangcheck.deadlock = 0;
6274f212
CW		 2625}
2626
ad8beaea 2627static enum intel_ring_hangcheck_action
a4872ba6 2628ring_stuck(struct intel_engine_cs *ring, u64 acthd)
1ec14ad3
CW		 2629{
2630 struct drm_device *dev = ring->dev;
2631 struct drm_i915_private *dev_priv = dev->dev_private;
9107e9d2
CW		 2632 u32 tmp;
2633
f260fe7b
MK		 2634 if (acthd != ring->hangcheck.acthd) {
2635 if (acthd > ring->hangcheck.max_acthd) {
2636 ring->hangcheck.max_acthd = acthd;
2637 return HANGCHECK_ACTIVE;
2638 }
2639
2640 return HANGCHECK_ACTIVE_LOOP;
2641 }
6274f212 2642
9107e9d2 2643 if (IS_GEN2(dev))
f2f4d82f 2644 return HANGCHECK_HUNG;
9107e9d2
CW		 2645
2646 /* Is the chip hanging on a WAIT_FOR_EVENT?
2647 * If so we can simply poke the RB_WAIT bit
2648 * and break the hang. This should work on
2649 * all but the second generation chipsets.
2650 */
2651 tmp = I915_READ_CTL(ring);
1ec14ad3 2652 if (tmp & RING_WAIT) {
58174462
MK		 2653 i915_handle_error(dev, false,
2654 "Kicking stuck wait on %s",
2655 ring->name);
1ec14ad3 2656 I915_WRITE_CTL(ring, tmp);
f2f4d82f 2657 return HANGCHECK_KICK;
6274f212
CW		 2658 }
2659
2660 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2661 switch (semaphore_passed(ring)) {
2662 default:
f2f4d82f 2663 return HANGCHECK_HUNG;
6274f212 2664 case 1:
58174462
MK		 2665 i915_handle_error(dev, false,
2666 "Kicking stuck semaphore on %s",
2667 ring->name);
6274f212 2668 I915_WRITE_CTL(ring, tmp);
f2f4d82f 2669 return HANGCHECK_KICK;
6274f212 2670 case 0:
f2f4d82f 2671 return HANGCHECK_WAIT;
6274f212 2672 }
9107e9d2 2673 }
ed5cbb03 2674
f2f4d82f 2675 return HANGCHECK_HUNG;
ed5cbb03
MK		 2676}
2677
737b1506 2678/*
f65d9421 2679 * This is called when the chip hasn't reported back with completed
05407ff8
MK		 2680 * batchbuffers in a long time. We keep track per ring seqno progress and
2681 * if there are no progress, hangcheck score for that ring is increased.
2682 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2683 * we kick the ring. If we see no progress on three subsequent calls
2684 * we assume chip is wedged and try to fix it by resetting the chip.
f65d9421 2685 */
737b1506 2686static void i915_hangcheck_elapsed(struct work_struct *work)
f65d9421 2687{
737b1506
CW		 2688 struct drm_i915_private *dev_priv =
2689 container_of(work, typeof(*dev_priv),
2690 gpu_error.hangcheck_work.work);
2691 struct drm_device *dev = dev_priv->dev;
a4872ba6 2692 struct intel_engine_cs *ring;
b4519513 2693 int i;
05407ff8 2694 int busy_count = 0, rings_hung = 0;
9107e9d2
CW		 2695 bool stuck[I915_NUM_RINGS] = { 0 };
2696#define BUSY 1
2697#define KICK 5
2698#define HUNG 20
893eead0 2699
d330a953 2700 if (!i915.enable_hangcheck)
3e0dc6b0
BW		 2701 return;
2702
b4519513 2703 for_each_ring(ring, dev_priv, i) {
50877445
CW		 2704 u64 acthd;
2705 u32 seqno;
9107e9d2 2706 bool busy = true;
05407ff8 2707
6274f212
CW		 2708 semaphore_clear_deadlocks(dev_priv);
2709
05407ff8
MK		 2710 seqno = ring->get_seqno(ring, false);
2711 acthd = intel_ring_get_active_head(ring);
b4519513 2712
9107e9d2 2713 if (ring->hangcheck.seqno == seqno) {
94f7bbe1 2714 if (ring_idle(ring, seqno)) {
da661464
MK		 2715 ring->hangcheck.action = HANGCHECK_IDLE;
2716
9107e9d2
CW		 2717 if (waitqueue_active(&ring->irq_queue)) {
2718 /* Issue a wake-up to catch stuck h/w. */
094f9a54 2719 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
f4adcd24
DV		 2720 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2721 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2722 ring->name);
2723 else
2724 DRM_INFO("Fake missed irq on %s\n",
2725 ring->name);
094f9a54
CW		 2726 wake_up_all(&ring->irq_queue);
2727 }
2728 /* Safeguard against driver failure */
2729 ring->hangcheck.score += BUSY;
9107e9d2
CW		 2730 } else
2731 busy = false;
05407ff8 2732 } else {
6274f212
CW		 2733 /* We always increment the hangcheck score
2734 * if the ring is busy and still processing
2735 * the same request, so that no single request
2736 * can run indefinitely (such as a chain of
2737 * batches). The only time we do not increment
2738 * the hangcheck score on this ring, if this
2739 * ring is in a legitimate wait for another
2740 * ring. In that case the waiting ring is a
2741 * victim and we want to be sure we catch the
2742 * right culprit. Then every time we do kick
2743 * the ring, add a small increment to the
2744 * score so that we can catch a batch that is
2745 * being repeatedly kicked and so responsible
2746 * for stalling the machine.
2747 */
ad8beaea
MK		 2748 ring->hangcheck.action = ring_stuck(ring,
2749 acthd);
2750
2751 switch (ring->hangcheck.action) {
da661464 2752 case HANGCHECK_IDLE:
f2f4d82f 2753 case HANGCHECK_WAIT:
f2f4d82f 2754 case HANGCHECK_ACTIVE:
f260fe7b
MK		 2755 break;
2756 case HANGCHECK_ACTIVE_LOOP:
ea04cb31 2757 ring->hangcheck.score += BUSY;
6274f212 2758 break;
f2f4d82f 2759 case HANGCHECK_KICK:
ea04cb31 2760 ring->hangcheck.score += KICK;
6274f212 2761 break;
f2f4d82f 2762 case HANGCHECK_HUNG:
ea04cb31 2763 ring->hangcheck.score += HUNG;
6274f212
CW		 2764 stuck[i] = true;
2765 break;
2766 }
05407ff8 2767 }
9107e9d2 2768 } else {
da661464
MK		 2769 ring->hangcheck.action = HANGCHECK_ACTIVE;
2770
9107e9d2
CW		 2771 /* Gradually reduce the count so that we catch DoS
2772 * attempts across multiple batches.
2773 */
2774 if (ring->hangcheck.score > 0)
2775 ring->hangcheck.score--;
f260fe7b
MK		 2776
2777 ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
d1e61e7f
CW		 2778 }
2779
05407ff8
MK		 2780 ring->hangcheck.seqno = seqno;
2781 ring->hangcheck.acthd = acthd;
9107e9d2 2782 busy_count += busy;
893eead0 2783 }
b9201c14 2784
92cab734 2785 for_each_ring(ring, dev_priv, i) {
b6b0fac0 2786 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
b8d88d1d
DV		 2787 DRM_INFO("%s on %s\n",
2788 stuck[i] ? "stuck" : "no progress",
2789 ring->name);
a43adf07 2790 rings_hung++;
92cab734
MK		 2791 }
2792 }
2793
05407ff8 2794 if (rings_hung)
58174462 2795 return i915_handle_error(dev, true, "Ring hung");
f65d9421 2796
05407ff8
MK		 2797 if (busy_count)
2798 /* Reset timer case chip hangs without another request
2799 * being added */
10cd45b6
MK		 2800 i915_queue_hangcheck(dev);
2801}
2802
2803void i915_queue_hangcheck(struct drm_device *dev)
2804{
737b1506 2805 struct i915_gpu_error *e = &to_i915(dev)->gpu_error;
672e7b7c 2806
d330a953 2807 if (!i915.enable_hangcheck)
10cd45b6
MK		 2808 return;
2809
737b1506
CW		 2810 /* Don't continually defer the hangcheck so that it is always run at
2811 * least once after work has been scheduled on any ring. Otherwise,
2812 * we will ignore a hung ring if a second ring is kept busy.
2813 */
2814
2815 queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work,
2816 round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES));
f65d9421
BG		 2817}
2818
1c69eb42 2819static void ibx_irq_reset(struct drm_device *dev)
91738a95
PZ		 2820{
2821 struct drm_i915_private *dev_priv = dev->dev_private;
2822
2823 if (HAS_PCH_NOP(dev))
2824 return;
2825
f86f3fb0 2826 GEN5_IRQ_RESET(SDE);
105b122e
PZ		 2827
2828 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
2829 I915_WRITE(SERR_INT, 0xffffffff);
622364b6 2830}
105b122e 2831
622364b6
PZ		 2832/*
2833 * SDEIER is also touched by the interrupt handler to work around missed PCH
2834 * interrupts. Hence we can't update it after the interrupt handler is enabled -
2835 * instead we unconditionally enable all PCH interrupt sources here, but then
2836 * only unmask them as needed with SDEIMR.
2837 *
2838 * This function needs to be called before interrupts are enabled.
2839 */
2840static void ibx_irq_pre_postinstall(struct drm_device *dev)
2841{
2842 struct drm_i915_private *dev_priv = dev->dev_private;
2843
2844 if (HAS_PCH_NOP(dev))
2845 return;
2846
2847 WARN_ON(I915_READ(SDEIER) != 0);
91738a95
PZ		 2848 I915_WRITE(SDEIER, 0xffffffff);
2849 POSTING_READ(SDEIER);
2850}
2851
7c4d664e 2852static void gen5_gt_irq_reset(struct drm_device *dev)
d18ea1b5
DV		 2853{
2854 struct drm_i915_private *dev_priv = dev->dev_private;
2855
f86f3fb0 2856 GEN5_IRQ_RESET(GT);
a9d356a6 2857 if (INTEL_INFO(dev)->gen >= 6)
f86f3fb0 2858 GEN5_IRQ_RESET(GEN6_PM);
d18ea1b5
DV		 2859}
2860
1da177e4
LT		 2861/* drm_dma.h hooks
2862*/
be30b29f 2863static void ironlake_irq_reset(struct drm_device *dev)
036a4a7d 2864{
2d1013dd 2865 struct drm_i915_private *dev_priv = dev->dev_private;
036a4a7d 2866
0c841212 2867 I915_WRITE(HWSTAM, 0xffffffff);
bdfcdb63 2868
f86f3fb0 2869 GEN5_IRQ_RESET(DE);
c6d954c1
PZ		 2870 if (IS_GEN7(dev))
2871 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
036a4a7d 2872
7c4d664e 2873 gen5_gt_irq_reset(dev);
c650156a 2874
1c69eb42 2875 ibx_irq_reset(dev);
7d99163d 2876}
c650156a 2877
70591a41
VS		 2878static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
2879{
2880 enum pipe pipe;
2881
2882 I915_WRITE(PORT_HOTPLUG_EN, 0);
2883 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2884
2885 for_each_pipe(dev_priv, pipe)
2886 I915_WRITE(PIPESTAT(pipe), 0xffff);
2887
2888 GEN5_IRQ_RESET(VLV_);
2889}
2890
7e231dbe
JB		 2891static void valleyview_irq_preinstall(struct drm_device *dev)
2892{
2d1013dd 2893 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe 2894
7e231dbe
JB		 2895 /* VLV magic */
2896 I915_WRITE(VLV_IMR, 0);
2897 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2898 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2899 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2900
7c4d664e 2901 gen5_gt_irq_reset(dev);
7e231dbe 2902
7c4cde39 2903 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
7e231dbe 2904
70591a41 2905 vlv_display_irq_reset(dev_priv);
7e231dbe
JB		 2906}
2907
d6e3cca3
DV		 2908static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
2909{
2910 GEN8_IRQ_RESET_NDX(GT, 0);
2911 GEN8_IRQ_RESET_NDX(GT, 1);
2912 GEN8_IRQ_RESET_NDX(GT, 2);
2913 GEN8_IRQ_RESET_NDX(GT, 3);
2914}
2915
823f6b38 2916static void gen8_irq_reset(struct drm_device *dev)
abd58f01
BW		 2917{
2918 struct drm_i915_private *dev_priv = dev->dev_private;
2919 int pipe;
2920
abd58f01
BW		 2921 I915_WRITE(GEN8_MASTER_IRQ, 0);
2922 POSTING_READ(GEN8_MASTER_IRQ);
2923
d6e3cca3 2924 gen8_gt_irq_reset(dev_priv);
abd58f01 2925
055e393f 2926 for_each_pipe(dev_priv, pipe)
f458ebbc
DV		 2927 if (intel_display_power_is_enabled(dev_priv,
2928 POWER_DOMAIN_PIPE(pipe)))
813bde43 2929 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
abd58f01 2930
f86f3fb0
PZ		 2931 GEN5_IRQ_RESET(GEN8_DE_PORT_);
2932 GEN5_IRQ_RESET(GEN8_DE_MISC_);
2933 GEN5_IRQ_RESET(GEN8_PCU_);
abd58f01 2934
266ea3d9
SS		 2935 if (HAS_PCH_SPLIT(dev))
2936 ibx_irq_reset(dev);
abd58f01 2937}
09f2344d 2938
4c6c03be
DL		 2939void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
2940 unsigned int pipe_mask)
d49bdb0e 2941{
1180e206 2942 uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
d49bdb0e 2943
13321786 2944 spin_lock_irq(&dev_priv->irq_lock);
d14c0343
DL		 2945 if (pipe_mask & 1 << PIPE_A)
2946 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_A,
2947 dev_priv->de_irq_mask[PIPE_A],
2948 ~dev_priv->de_irq_mask[PIPE_A] | extra_ier);
4c6c03be
DL		 2949 if (pipe_mask & 1 << PIPE_B)
2950 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B,
2951 dev_priv->de_irq_mask[PIPE_B],
2952 ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
2953 if (pipe_mask & 1 << PIPE_C)
2954 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C,
2955 dev_priv->de_irq_mask[PIPE_C],
2956 ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
13321786 2957 spin_unlock_irq(&dev_priv->irq_lock);
d49bdb0e
PZ		 2958}
2959
43f328d7
VS		 2960static void cherryview_irq_preinstall(struct drm_device *dev)
2961{
2962 struct drm_i915_private *dev_priv = dev->dev_private;
43f328d7
VS		 2963
2964 I915_WRITE(GEN8_MASTER_IRQ, 0);
2965 POSTING_READ(GEN8_MASTER_IRQ);
2966
d6e3cca3 2967 gen8_gt_irq_reset(dev_priv);
43f328d7
VS		 2968
2969 GEN5_IRQ_RESET(GEN8_PCU_);
2970
43f328d7
VS		 2971 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
2972
70591a41 2973 vlv_display_irq_reset(dev_priv);
43f328d7
VS		 2974}
2975
82a28bcf 2976static void ibx_hpd_irq_setup(struct drm_device *dev)
7fe0b973 2977{
2d1013dd 2978 struct drm_i915_private *dev_priv = dev->dev_private;
82a28bcf 2979 struct intel_encoder *intel_encoder;
fee884ed 2980 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
82a28bcf
DV		 2981
2982 if (HAS_PCH_IBX(dev)) {
fee884ed 2983 hotplug_irqs = SDE_HOTPLUG_MASK;
b2784e15 2984 for_each_intel_encoder(dev, intel_encoder)
5fcece80 2985 if (dev_priv->hotplug.stats[intel_encoder->hpd_pin].state == HPD_ENABLED)
fee884ed 2986 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
82a28bcf 2987 } else {
fee884ed 2988 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
b2784e15 2989 for_each_intel_encoder(dev, intel_encoder)
5fcece80 2990 if (dev_priv->hotplug.stats[intel_encoder->hpd_pin].state == HPD_ENABLED)
fee884ed 2991 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
82a28bcf 2992 }
7fe0b973 2993
fee884ed 2994 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
82a28bcf
DV		 2995
2996 /*
2997 * Enable digital hotplug on the PCH, and configure the DP short pulse
2998 * duration to 2ms (which is the minimum in the Display Port spec)
2999 *
3000 * This register is the same on all known PCH chips.
3001 */
7fe0b973
KP		 3002 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3003 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3004 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3005 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3006 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3007 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3008}
3009
e0a20ad7
SS		 3010static void bxt_hpd_irq_setup(struct drm_device *dev)
3011{
3012 struct drm_i915_private *dev_priv = dev->dev_private;
3013 struct intel_encoder *intel_encoder;
3014 u32 hotplug_port = 0;
3015 u32 hotplug_ctrl;
3016
3017 /* Now, enable HPD */
3018 for_each_intel_encoder(dev, intel_encoder) {
5fcece80 3019 if (dev_priv->hotplug.stats[intel_encoder->hpd_pin].state
e0a20ad7
SS		 3020 == HPD_ENABLED)
3021 hotplug_port |= hpd_bxt[intel_encoder->hpd_pin];
3022 }
3023
3024 /* Mask all HPD control bits */
3025 hotplug_ctrl = I915_READ(BXT_HOTPLUG_CTL) & ~BXT_HOTPLUG_CTL_MASK;
3026
3027 /* Enable requested port in hotplug control */
3028 /* TODO: implement (short) HPD support on port A */
3029 WARN_ON_ONCE(hotplug_port & BXT_DE_PORT_HP_DDIA);
3030 if (hotplug_port & BXT_DE_PORT_HP_DDIB)
3031 hotplug_ctrl |= BXT_DDIB_HPD_ENABLE;
3032 if (hotplug_port & BXT_DE_PORT_HP_DDIC)
3033 hotplug_ctrl |= BXT_DDIC_HPD_ENABLE;
3034 I915_WRITE(BXT_HOTPLUG_CTL, hotplug_ctrl);
3035
3036 /* Unmask DDI hotplug in IMR */
3037 hotplug_ctrl = I915_READ(GEN8_DE_PORT_IMR) & ~hotplug_port;
3038 I915_WRITE(GEN8_DE_PORT_IMR, hotplug_ctrl);
3039
3040 /* Enable DDI hotplug in IER */
3041 hotplug_ctrl = I915_READ(GEN8_DE_PORT_IER) | hotplug_port;
3042 I915_WRITE(GEN8_DE_PORT_IER, hotplug_ctrl);
3043 POSTING_READ(GEN8_DE_PORT_IER);
3044}
3045
d46da437
PZ		 3046static void ibx_irq_postinstall(struct drm_device *dev)
3047{
2d1013dd 3048 struct drm_i915_private *dev_priv = dev->dev_private;
82a28bcf 3049 u32 mask;
e5868a31 3050
692a04cf
DV		 3051 if (HAS_PCH_NOP(dev))
3052 return;
3053
105b122e 3054 if (HAS_PCH_IBX(dev))
5c673b60 3055 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
105b122e 3056 else
5c673b60 3057 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
8664281b 3058
337ba017 3059 GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
d46da437 3060 I915_WRITE(SDEIMR, ~mask);
d46da437
PZ		 3061}
3062
0a9a8c91
DV		 3063static void gen5_gt_irq_postinstall(struct drm_device *dev)
3064{
3065 struct drm_i915_private *dev_priv = dev->dev_private;
3066 u32 pm_irqs, gt_irqs;
3067
3068 pm_irqs = gt_irqs = 0;
3069
3070 dev_priv->gt_irq_mask = ~0;
040d2baa 3071 if (HAS_L3_DPF(dev)) {
0a9a8c91 3072 /* L3 parity interrupt is always unmasked. */
35a85ac6
BW		 3073 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3074 gt_irqs |= GT_PARITY_ERROR(dev);
0a9a8c91
DV		 3075 }
3076
3077 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3078 if (IS_GEN5(dev)) {
3079 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3080 ILK_BSD_USER_INTERRUPT;
3081 } else {
3082 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3083 }
3084
35079899 3085 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
0a9a8c91
DV		 3086
3087 if (INTEL_INFO(dev)->gen >= 6) {
78e68d36
ID		 3088 /*
3089 * RPS interrupts will get enabled/disabled on demand when RPS
3090 * itself is enabled/disabled.
3091 */
0a9a8c91
DV		 3092 if (HAS_VEBOX(dev))
3093 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3094
605cd25b 3095 dev_priv->pm_irq_mask = 0xffffffff;
35079899 3096 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
0a9a8c91
DV		 3097 }
3098}
3099
f71d4af4 3100static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d 3101{
2d1013dd 3102 struct drm_i915_private *dev_priv = dev->dev_private;
8e76f8dc
PZ		 3103 u32 display_mask, extra_mask;
3104
3105 if (INTEL_INFO(dev)->gen >= 7) {
3106 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3107 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3108 DE_PLANEB_FLIP_DONE_IVB |
5c673b60 3109 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
8e76f8dc 3110 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
5c673b60 3111 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
8e76f8dc
PZ		 3112 } else {
3113 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3114 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
5b3a856b 3115 DE_AUX_CHANNEL_A |
5b3a856b
DV		 3116 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3117 DE_POISON);
5c673b60
DV		 3118 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3119 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
8e76f8dc 3120 }
036a4a7d 3121
1ec14ad3 3122 dev_priv->irq_mask = ~display_mask;
036a4a7d 3123
0c841212
PZ		 3124 I915_WRITE(HWSTAM, 0xeffe);
3125
622364b6
PZ		 3126 ibx_irq_pre_postinstall(dev);
3127
35079899 3128 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
036a4a7d 3129
0a9a8c91 3130 gen5_gt_irq_postinstall(dev);
036a4a7d 3131
d46da437 3132 ibx_irq_postinstall(dev);
7fe0b973 3133
f97108d1 3134 if (IS_IRONLAKE_M(dev)) {
6005ce42
DV		 3135 /* Enable PCU event interrupts
3136 *
3137 * spinlocking not required here for correctness since interrupt
4bc9d430
DV		 3138 * setup is guaranteed to run in single-threaded context. But we
3139 * need it to make the assert_spin_locked happy. */
d6207435 3140 spin_lock_irq(&dev_priv->irq_lock);
f97108d1 3141 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
d6207435 3142 spin_unlock_irq(&dev_priv->irq_lock);
f97108d1
JB		 3143 }
3144
036a4a7d
ZW		 3145 return 0;
3146}
3147
f8b79e58
ID		 3148static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3149{
3150 u32 pipestat_mask;
3151 u32 iir_mask;
120dda4f 3152 enum pipe pipe;
f8b79e58
ID		 3153
3154 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3155 PIPE_FIFO_UNDERRUN_STATUS;
3156
120dda4f
VS		 3157 for_each_pipe(dev_priv, pipe)
3158 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
f8b79e58
ID		 3159 POSTING_READ(PIPESTAT(PIPE_A));
3160
3161 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3162 PIPE_CRC_DONE_INTERRUPT_STATUS;
3163
120dda4f
VS		 3164 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3165 for_each_pipe(dev_priv, pipe)
3166 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
f8b79e58
ID		 3167
3168 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3169 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3170 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
120dda4f
VS		 3171 if (IS_CHERRYVIEW(dev_priv))
3172 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
f8b79e58
ID		 3173 dev_priv->irq_mask &= ~iir_mask;
3174
3175 I915_WRITE(VLV_IIR, iir_mask);
3176 I915_WRITE(VLV_IIR, iir_mask);
f8b79e58 3177 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
76e41860
VS		 3178 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3179 POSTING_READ(VLV_IMR);
f8b79e58
ID		 3180}
3181
3182static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3183{
3184 u32 pipestat_mask;
3185 u32 iir_mask;
120dda4f 3186 enum pipe pipe;
f8b79e58
ID		 3187
3188 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3189 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
6c7fba04 3190 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
120dda4f
VS		 3191 if (IS_CHERRYVIEW(dev_priv))
3192 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
f8b79e58
ID		 3193
3194 dev_priv->irq_mask |= iir_mask;
f8b79e58 3195 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
76e41860 3196 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
f8b79e58
ID		 3197 I915_WRITE(VLV_IIR, iir_mask);
3198 I915_WRITE(VLV_IIR, iir_mask);
3199 POSTING_READ(VLV_IIR);
3200
3201 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3202 PIPE_CRC_DONE_INTERRUPT_STATUS;
3203
120dda4f
VS		 3204 i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3205 for_each_pipe(dev_priv, pipe)
3206 i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
f8b79e58
ID		 3207
3208 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3209 PIPE_FIFO_UNDERRUN_STATUS;
120dda4f
VS		 3210
3211 for_each_pipe(dev_priv, pipe)
3212 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
f8b79e58
ID		 3213 POSTING_READ(PIPESTAT(PIPE_A));
3214}
3215
3216void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3217{
3218 assert_spin_locked(&dev_priv->irq_lock);
3219
3220 if (dev_priv->display_irqs_enabled)
3221 return;
3222
3223 dev_priv->display_irqs_enabled = true;
3224
950eabaf 3225 if (intel_irqs_enabled(dev_priv))
f8b79e58
ID		 3226 valleyview_display_irqs_install(dev_priv);
3227}
3228
3229void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3230{
3231 assert_spin_locked(&dev_priv->irq_lock);
3232
3233 if (!dev_priv->display_irqs_enabled)
3234 return;
3235
3236 dev_priv->display_irqs_enabled = false;
3237
950eabaf 3238 if (intel_irqs_enabled(dev_priv))
f8b79e58
ID		 3239 valleyview_display_irqs_uninstall(dev_priv);
3240}
3241
0e6c9a9e 3242static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
7e231dbe 3243{
f8b79e58 3244 dev_priv->irq_mask = ~0;
7e231dbe 3245
20afbda2
DV		 3246 I915_WRITE(PORT_HOTPLUG_EN, 0);
3247 POSTING_READ(PORT_HOTPLUG_EN);
3248
7e231dbe 3249 I915_WRITE(VLV_IIR, 0xffffffff);
76e41860
VS		 3250 I915_WRITE(VLV_IIR, 0xffffffff);
3251 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3252 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3253 POSTING_READ(VLV_IMR);
7e231dbe 3254
b79480ba
DV		 3255 /* Interrupt setup is already guaranteed to be single-threaded, this is
3256 * just to make the assert_spin_locked check happy. */
d6207435 3257 spin_lock_irq(&dev_priv->irq_lock);
f8b79e58
ID		 3258 if (dev_priv->display_irqs_enabled)
3259 valleyview_display_irqs_install(dev_priv);
d6207435 3260 spin_unlock_irq(&dev_priv->irq_lock);
0e6c9a9e
VS		 3261}
3262
3263static int valleyview_irq_postinstall(struct drm_device *dev)
3264{
3265 struct drm_i915_private *dev_priv = dev->dev_private;
3266
3267 vlv_display_irq_postinstall(dev_priv);
7e231dbe 3268
0a9a8c91 3269 gen5_gt_irq_postinstall(dev);
7e231dbe
JB		 3270
3271 /* ack & enable invalid PTE error interrupts */
3272#if 0 /* FIXME: add support to irq handler for checking these bits */
3273 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3274 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3275#endif
3276
3277 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
20afbda2
DV		 3278
3279 return 0;
3280}
3281
abd58f01
BW		 3282static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3283{
abd58f01
BW		 3284 /* These are interrupts we'll toggle with the ring mask register */
3285 uint32_t gt_interrupts[] = {
3286 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
73d477f6 3287 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
abd58f01 3288 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
73d477f6
OM		 3289 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3290 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
abd58f01 3291 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
73d477f6
OM		 3292 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3293 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3294 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
abd58f01 3295 0,
73d477f6
OM		 3296 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3297 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
abd58f01
BW		 3298 };
3299
0961021a 3300 dev_priv->pm_irq_mask = 0xffffffff;
9a2d2d87
D		 3301 GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3302 GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
78e68d36
ID		 3303 /*
3304 * RPS interrupts will get enabled/disabled on demand when RPS itself
3305 * is enabled/disabled.
3306 */
3307 GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
9a2d2d87 3308 GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
abd58f01
BW		 3309}
3310
3311static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3312{
770de83d
DL		 3313 uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3314 uint32_t de_pipe_enables;
abd58f01 3315 int pipe;
9e63743e 3316 u32 de_port_en = GEN8_AUX_CHANNEL_A;
770de83d 3317
88e04703 3318 if (IS_GEN9(dev_priv)) {
770de83d
DL		 3319 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3320 GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
9e63743e 3321 de_port_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
88e04703 3322 GEN9_AUX_CHANNEL_D;
9e63743e
SS		 3323
3324 if (IS_BROXTON(dev_priv))
3325 de_port_en |= BXT_DE_PORT_GMBUS;
88e04703 3326 } else
770de83d
DL		 3327 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3328 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3329
3330 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3331 GEN8_PIPE_FIFO_UNDERRUN;
3332
13b3a0a7
DV		 3333 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3334 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3335 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
abd58f01 3336
055e393f 3337 for_each_pipe(dev_priv, pipe)
f458ebbc 3338 if (intel_display_power_is_enabled(dev_priv,
813bde43
PZ		 3339 POWER_DOMAIN_PIPE(pipe)))
3340 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3341 dev_priv->de_irq_mask[pipe],
3342 de_pipe_enables);
abd58f01 3343
9e63743e 3344 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_en, de_port_en);
abd58f01
BW		 3345}
3346
3347static int gen8_irq_postinstall(struct drm_device *dev)
3348{
3349 struct drm_i915_private *dev_priv = dev->dev_private;
3350
266ea3d9
SS		 3351 if (HAS_PCH_SPLIT(dev))
3352 ibx_irq_pre_postinstall(dev);
622364b6 3353
abd58f01
BW		 3354 gen8_gt_irq_postinstall(dev_priv);
3355 gen8_de_irq_postinstall(dev_priv);
3356
266ea3d9
SS		 3357 if (HAS_PCH_SPLIT(dev))
3358 ibx_irq_postinstall(dev);
abd58f01
BW		 3359
3360 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3361 POSTING_READ(GEN8_MASTER_IRQ);
3362
3363 return 0;
3364}
3365
43f328d7
VS		 3366static int cherryview_irq_postinstall(struct drm_device *dev)
3367{
3368 struct drm_i915_private *dev_priv = dev->dev_private;
43f328d7 3369
c2b66797 3370 vlv_display_irq_postinstall(dev_priv);
43f328d7
VS		 3371
3372 gen8_gt_irq_postinstall(dev_priv);
3373
3374 I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
3375 POSTING_READ(GEN8_MASTER_IRQ);
3376
3377 return 0;
3378}
3379
abd58f01
BW		 3380static void gen8_irq_uninstall(struct drm_device *dev)
3381{
3382 struct drm_i915_private *dev_priv = dev->dev_private;
abd58f01
BW		 3383
3384 if (!dev_priv)
3385 return;
3386
823f6b38 3387 gen8_irq_reset(dev);
abd58f01
BW		 3388}
3389
8ea0be4f
VS		 3390static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv)
3391{
3392 /* Interrupt setup is already guaranteed to be single-threaded, this is
3393 * just to make the assert_spin_locked check happy. */
3394 spin_lock_irq(&dev_priv->irq_lock);
3395 if (dev_priv->display_irqs_enabled)
3396 valleyview_display_irqs_uninstall(dev_priv);
3397 spin_unlock_irq(&dev_priv->irq_lock);
3398
3399 vlv_display_irq_reset(dev_priv);
3400
c352d1ba 3401 dev_priv->irq_mask = ~0;
8ea0be4f
VS		 3402}
3403
7e231dbe
JB		 3404static void valleyview_irq_uninstall(struct drm_device *dev)
3405{
2d1013dd 3406 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe
JB		 3407
3408 if (!dev_priv)
3409 return;
3410
843d0e7d
ID		 3411 I915_WRITE(VLV_MASTER_IER, 0);
3412
893fce8e
VS		 3413 gen5_gt_irq_reset(dev);
3414
7e231dbe 3415 I915_WRITE(HWSTAM, 0xffffffff);
f8b79e58 3416
8ea0be4f 3417 vlv_display_irq_uninstall(dev_priv);
7e231dbe
JB		 3418}
3419
43f328d7
VS		 3420static void cherryview_irq_uninstall(struct drm_device *dev)
3421{
3422 struct drm_i915_private *dev_priv = dev->dev_private;
43f328d7
VS		 3423
3424 if (!dev_priv)
3425 return;
3426
3427 I915_WRITE(GEN8_MASTER_IRQ, 0);
3428 POSTING_READ(GEN8_MASTER_IRQ);
3429
a2c30fba 3430 gen8_gt_irq_reset(dev_priv);
43f328d7 3431
a2c30fba 3432 GEN5_IRQ_RESET(GEN8_PCU_);
43f328d7 3433
c2b66797 3434 vlv_display_irq_uninstall(dev_priv);
43f328d7
VS		 3435}
3436
f71d4af4 3437static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d 3438{
2d1013dd 3439 struct drm_i915_private *dev_priv = dev->dev_private;
4697995b
JB		 3440
3441 if (!dev_priv)
3442 return;
3443
be30b29f 3444 ironlake_irq_reset(dev);
036a4a7d
ZW		 3445}
3446
a266c7d5 3447static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4 3448{
2d1013dd 3449 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 3450 int pipe;
91e3738e 3451
055e393f 3452 for_each_pipe(dev_priv, pipe)
9db4a9c7 3453 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 3454 I915_WRITE16(IMR, 0xffff);
3455 I915_WRITE16(IER, 0x0);
3456 POSTING_READ16(IER);
c2798b19
CW		 3457}
3458
3459static int i8xx_irq_postinstall(struct drm_device *dev)
3460{
2d1013dd 3461 struct drm_i915_private *dev_priv = dev->dev_private;
c2798b19 3462
c2798b19
CW		 3463 I915_WRITE16(EMR,
3464 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3465
3466 /* Unmask the interrupts that we always want on. */
3467 dev_priv->irq_mask =
3468 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3469 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3470 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
37ef01ab 3471 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
c2798b19
CW		 3472 I915_WRITE16(IMR, dev_priv->irq_mask);
3473
3474 I915_WRITE16(IER,
3475 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3476 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
c2798b19
CW		 3477 I915_USER_INTERRUPT);
3478 POSTING_READ16(IER);
3479
379ef82d
DV		 3480 /* Interrupt setup is already guaranteed to be single-threaded, this is
3481 * just to make the assert_spin_locked check happy. */
d6207435 3482 spin_lock_irq(&dev_priv->irq_lock);
755e9019
ID		 3483 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3484 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
d6207435 3485 spin_unlock_irq(&dev_priv->irq_lock);
379ef82d 3486
c2798b19
CW		 3487 return 0;
3488}
3489
90a72f87
VS		 3490/*
3491 * Returns true when a page flip has completed.
3492 */
3493static bool i8xx_handle_vblank(struct drm_device *dev,
1f1c2e24 3494 int plane, int pipe, u32 iir)
90a72f87 3495{
2d1013dd 3496 struct drm_i915_private *dev_priv = dev->dev_private;
1f1c2e24 3497 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
90a72f87 3498
8d7849db 3499 if (!intel_pipe_handle_vblank(dev, pipe))
90a72f87
VS		 3500 return false;
3501
3502 if ((iir & flip_pending) == 0)
d6bbafa1 3503 goto check_page_flip;
90a72f87 3504
90a72f87
VS		 3505 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3506 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3507 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3508 * the flip is completed (no longer pending). Since this doesn't raise
3509 * an interrupt per se, we watch for the change at vblank.
3510 */
3511 if (I915_READ16(ISR) & flip_pending)
d6bbafa1 3512 goto check_page_flip;
90a72f87 3513
7d47559e 3514 intel_prepare_page_flip(dev, plane);
90a72f87 3515 intel_finish_page_flip(dev, pipe);
90a72f87 3516 return true;
d6bbafa1
CW		 3517
3518check_page_flip:
3519 intel_check_page_flip(dev, pipe);
3520 return false;
90a72f87
VS		 3521}
3522
ff1f525e 3523static irqreturn_t i8xx_irq_handler(int irq, void *arg)
c2798b19 3524{
45a83f84 3525 struct drm_device *dev = arg;
2d1013dd 3526 struct drm_i915_private *dev_priv = dev->dev_private;
c2798b19
CW		 3527 u16 iir, new_iir;
3528 u32 pipe_stats[2];
c2798b19
CW		 3529 int pipe;
3530 u16 flip_mask =
3531 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3532 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3533
2dd2a883
ID		 3534 if (!intel_irqs_enabled(dev_priv))
3535 return IRQ_NONE;
3536
c2798b19
CW		 3537 iir = I915_READ16(IIR);
3538 if (iir == 0)
3539 return IRQ_NONE;
3540
3541 while (iir & ~flip_mask) {
3542 /* Can't rely on pipestat interrupt bit in iir as it might
3543 * have been cleared after the pipestat interrupt was received.
3544 * It doesn't set the bit in iir again, but it still produces
3545 * interrupts (for non-MSI).
3546 */
222c7f51 3547 spin_lock(&dev_priv->irq_lock);
c2798b19 3548 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
aaecdf61 3549 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
c2798b19 3550
055e393f 3551 for_each_pipe(dev_priv, pipe) {
c2798b19
CW		 3552 int reg = PIPESTAT(pipe);
3553 pipe_stats[pipe] = I915_READ(reg);
3554
3555 /*
3556 * Clear the PIPE*STAT regs before the IIR
3557 */
2d9d2b0b 3558 if (pipe_stats[pipe] & 0x8000ffff)
c2798b19 3559 I915_WRITE(reg, pipe_stats[pipe]);
c2798b19 3560 }
222c7f51 3561 spin_unlock(&dev_priv->irq_lock);
c2798b19
CW		 3562
3563 I915_WRITE16(IIR, iir & ~flip_mask);
3564 new_iir = I915_READ16(IIR); /* Flush posted writes */
3565
c2798b19 3566 if (iir & I915_USER_INTERRUPT)
74cdb337 3567 notify_ring(&dev_priv->ring[RCS]);
c2798b19 3568
055e393f 3569 for_each_pipe(dev_priv, pipe) {
1f1c2e24 3570 int plane = pipe;
3a77c4c4 3571 if (HAS_FBC(dev))
1f1c2e24
VS		 3572 plane = !plane;
3573
4356d586 3574 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
1f1c2e24
VS		 3575 i8xx_handle_vblank(dev, plane, pipe, iir))
3576 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
c2798b19 3577
4356d586 3578 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
277de95e 3579 i9xx_pipe_crc_irq_handler(dev, pipe);
2d9d2b0b 3580
1f7247c0
DV		 3581 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3582 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3583 pipe);
4356d586 3584 }
c2798b19
CW		 3585
3586 iir = new_iir;
3587 }
3588
3589 return IRQ_HANDLED;
3590}
3591
3592static void i8xx_irq_uninstall(struct drm_device * dev)
3593{
2d1013dd 3594 struct drm_i915_private *dev_priv = dev->dev_private;
c2798b19
CW		 3595 int pipe;
3596
055e393f 3597 for_each_pipe(dev_priv, pipe) {
c2798b19
CW		 3598 /* Clear enable bits; then clear status bits */
3599 I915_WRITE(PIPESTAT(pipe), 0);
3600 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3601 }
3602 I915_WRITE16(IMR, 0xffff);
3603 I915_WRITE16(IER, 0x0);
3604 I915_WRITE16(IIR, I915_READ16(IIR));
3605}
3606
a266c7d5
CW		 3607static void i915_irq_preinstall(struct drm_device * dev)
3608{
2d1013dd 3609 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 3610 int pipe;
3611
a266c7d5
CW		 3612 if (I915_HAS_HOTPLUG(dev)) {
3613 I915_WRITE(PORT_HOTPLUG_EN, 0);
3614 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3615 }
3616
00d98ebd 3617 I915_WRITE16(HWSTAM, 0xeffe);
055e393f 3618 for_each_pipe(dev_priv, pipe)
a266c7d5
CW		 3619 I915_WRITE(PIPESTAT(pipe), 0);
3620 I915_WRITE(IMR, 0xffffffff);
3621 I915_WRITE(IER, 0x0);
3622 POSTING_READ(IER);
3623}
3624
3625static int i915_irq_postinstall(struct drm_device *dev)
3626{
2d1013dd 3627 struct drm_i915_private *dev_priv = dev->dev_private;
38bde180 3628 u32 enable_mask;
a266c7d5 3629
38bde180
CW		 3630 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3631
3632 /* Unmask the interrupts that we always want on. */
3633 dev_priv->irq_mask =
3634 ~(I915_ASLE_INTERRUPT |
3635 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3636 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3637 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
37ef01ab 3638 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
38bde180
CW		 3639
3640 enable_mask =
3641 I915_ASLE_INTERRUPT |
3642 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3643 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
38bde180
CW		 3644 I915_USER_INTERRUPT;
3645
a266c7d5 3646 if (I915_HAS_HOTPLUG(dev)) {
20afbda2
DV		 3647 I915_WRITE(PORT_HOTPLUG_EN, 0);
3648 POSTING_READ(PORT_HOTPLUG_EN);
3649
a266c7d5
CW		 3650 /* Enable in IER... */
3651 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3652 /* and unmask in IMR */
3653 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3654 }
3655
a266c7d5
CW		 3656 I915_WRITE(IMR, dev_priv->irq_mask);
3657 I915_WRITE(IER, enable_mask);
3658 POSTING_READ(IER);
3659
f49e38dd 3660 i915_enable_asle_pipestat(dev);
20afbda2 3661
379ef82d
DV		 3662 /* Interrupt setup is already guaranteed to be single-threaded, this is
3663 * just to make the assert_spin_locked check happy. */
d6207435 3664 spin_lock_irq(&dev_priv->irq_lock);
755e9019
ID		 3665 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3666 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
d6207435 3667 spin_unlock_irq(&dev_priv->irq_lock);
379ef82d 3668
20afbda2
DV		 3669 return 0;
3670}
3671
90a72f87
VS		 3672/*
3673 * Returns true when a page flip has completed.
3674 */
3675static bool i915_handle_vblank(struct drm_device *dev,
3676 int plane, int pipe, u32 iir)
3677{
2d1013dd 3678 struct drm_i915_private *dev_priv = dev->dev_private;
90a72f87
VS		 3679 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3680
8d7849db 3681 if (!intel_pipe_handle_vblank(dev, pipe))
90a72f87
VS		 3682 return false;
3683
3684 if ((iir & flip_pending) == 0)
d6bbafa1 3685 goto check_page_flip;
90a72f87 3686
90a72f87
VS		 3687 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3688 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3689 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3690 * the flip is completed (no longer pending). Since this doesn't raise
3691 * an interrupt per se, we watch for the change at vblank.
3692 */
3693 if (I915_READ(ISR) & flip_pending)
d6bbafa1 3694 goto check_page_flip;
90a72f87 3695
7d47559e 3696 intel_prepare_page_flip(dev, plane);
90a72f87 3697 intel_finish_page_flip(dev, pipe);
90a72f87 3698 return true;
d6bbafa1
CW		 3699
3700check_page_flip:
3701 intel_check_page_flip(dev, pipe);
3702 return false;
90a72f87
VS		 3703}
3704
ff1f525e 3705static irqreturn_t i915_irq_handler(int irq, void *arg)
a266c7d5 3706{
45a83f84 3707 struct drm_device *dev = arg;
2d1013dd 3708 struct drm_i915_private *dev_priv = dev->dev_private;
8291ee90 3709 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
38bde180
CW		 3710 u32 flip_mask =
3711 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3712 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
38bde180 3713 int pipe, ret = IRQ_NONE;
a266c7d5 3714
2dd2a883
ID		 3715 if (!intel_irqs_enabled(dev_priv))
3716 return IRQ_NONE;
3717
a266c7d5 3718 iir = I915_READ(IIR);
38bde180
CW		 3719 do {
3720 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 3721 bool blc_event = false;
a266c7d5
CW		 3722
3723 /* Can't rely on pipestat interrupt bit in iir as it might
3724 * have been cleared after the pipestat interrupt was received.
3725 * It doesn't set the bit in iir again, but it still produces
3726 * interrupts (for non-MSI).
3727 */
222c7f51 3728 spin_lock(&dev_priv->irq_lock);
a266c7d5 3729 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
aaecdf61 3730 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
a266c7d5 3731
055e393f 3732 for_each_pipe(dev_priv, pipe) {
a266c7d5
CW		 3733 int reg = PIPESTAT(pipe);
3734 pipe_stats[pipe] = I915_READ(reg);
3735
38bde180 3736 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5 3737 if (pipe_stats[pipe] & 0x8000ffff) {
a266c7d5 3738 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 3739 irq_received = true;
a266c7d5
CW		 3740 }
3741 }
222c7f51 3742 spin_unlock(&dev_priv->irq_lock);
a266c7d5
CW		 3743
3744 if (!irq_received)
3745 break;
3746
a266c7d5 3747 /* Consume port. Then clear IIR or we'll miss events */
16c6c56b
VS		 3748 if (I915_HAS_HOTPLUG(dev) &&
3749 iir & I915_DISPLAY_PORT_INTERRUPT)
3750 i9xx_hpd_irq_handler(dev);
a266c7d5 3751
38bde180 3752 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 3753 new_iir = I915_READ(IIR); /* Flush posted writes */
3754
a266c7d5 3755 if (iir & I915_USER_INTERRUPT)
74cdb337 3756 notify_ring(&dev_priv->ring[RCS]);
a266c7d5 3757
055e393f 3758 for_each_pipe(dev_priv, pipe) {
38bde180 3759 int plane = pipe;
3a77c4c4 3760 if (HAS_FBC(dev))
38bde180 3761 plane = !plane;
90a72f87 3762
8291ee90 3763 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3764 i915_handle_vblank(dev, plane, pipe, iir))
3765 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
a266c7d5
CW		 3766
3767 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3768 blc_event = true;
4356d586
DV		 3769
3770 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
277de95e 3771 i9xx_pipe_crc_irq_handler(dev, pipe);
2d9d2b0b 3772
1f7247c0
DV		 3773 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3774 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3775 pipe);
a266c7d5
CW		 3776 }
3777
a266c7d5
CW		 3778 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3779 intel_opregion_asle_intr(dev);
3780
3781 /* With MSI, interrupts are only generated when iir
3782 * transitions from zero to nonzero. If another bit got
3783 * set while we were handling the existing iir bits, then
3784 * we would never get another interrupt.
3785 *
3786 * This is fine on non-MSI as well, as if we hit this path
3787 * we avoid exiting the interrupt handler only to generate
3788 * another one.
3789 *
3790 * Note that for MSI this could cause a stray interrupt report
3791 * if an interrupt landed in the time between writing IIR and
3792 * the posting read. This should be rare enough to never
3793 * trigger the 99% of 100,000 interrupts test for disabling
3794 * stray interrupts.
3795 */
38bde180 3796 ret = IRQ_HANDLED;
a266c7d5 3797 iir = new_iir;
38bde180 3798 } while (iir & ~flip_mask);
a266c7d5
CW		 3799
3800 return ret;
3801}
3802
3803static void i915_irq_uninstall(struct drm_device * dev)
3804{
2d1013dd 3805 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 3806 int pipe;
3807
a266c7d5
CW		 3808 if (I915_HAS_HOTPLUG(dev)) {
3809 I915_WRITE(PORT_HOTPLUG_EN, 0);
3810 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3811 }
3812
00d98ebd 3813 I915_WRITE16(HWSTAM, 0xffff);
055e393f 3814 for_each_pipe(dev_priv, pipe) {
55b39755 3815 /* Clear enable bits; then clear status bits */
a266c7d5 3816 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 3817 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3818 }
a266c7d5
CW		 3819 I915_WRITE(IMR, 0xffffffff);
3820 I915_WRITE(IER, 0x0);
3821
a266c7d5
CW		 3822 I915_WRITE(IIR, I915_READ(IIR));
3823}
3824
3825static void i965_irq_preinstall(struct drm_device * dev)
3826{
2d1013dd 3827 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 3828 int pipe;
3829
adca4730
CW		 3830 I915_WRITE(PORT_HOTPLUG_EN, 0);
3831 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 3832
3833 I915_WRITE(HWSTAM, 0xeffe);
055e393f 3834 for_each_pipe(dev_priv, pipe)
a266c7d5
CW		 3835 I915_WRITE(PIPESTAT(pipe), 0);
3836 I915_WRITE(IMR, 0xffffffff);
3837 I915_WRITE(IER, 0x0);
3838 POSTING_READ(IER);
3839}
3840
3841static int i965_irq_postinstall(struct drm_device *dev)
3842{
2d1013dd 3843 struct drm_i915_private *dev_priv = dev->dev_private;
bbba0a97 3844 u32 enable_mask;
a266c7d5
CW		 3845 u32 error_mask;
3846
a266c7d5 3847 /* Unmask the interrupts that we always want on. */
bbba0a97 3848 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 3849 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 3850 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3851 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3852 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3853 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3854 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3855
3856 enable_mask = ~dev_priv->irq_mask;
21ad8330
VS		 3857 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3858 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
bbba0a97
CW		 3859 enable_mask |= I915_USER_INTERRUPT;
3860
3861 if (IS_G4X(dev))
3862 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5 3863
b79480ba
DV		 3864 /* Interrupt setup is already guaranteed to be single-threaded, this is
3865 * just to make the assert_spin_locked check happy. */
d6207435 3866 spin_lock_irq(&dev_priv->irq_lock);
755e9019
ID		 3867 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3868 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3869 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
d6207435 3870 spin_unlock_irq(&dev_priv->irq_lock);
a266c7d5 3871
a266c7d5
CW		 3872 /*
3873 * Enable some error detection, note the instruction error mask
3874 * bit is reserved, so we leave it masked.
3875 */
3876 if (IS_G4X(dev)) {
3877 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3878 GM45_ERROR_MEM_PRIV |
3879 GM45_ERROR_CP_PRIV |
3880 I915_ERROR_MEMORY_REFRESH);
3881 } else {
3882 error_mask = ~(I915_ERROR_PAGE_TABLE |
3883 I915_ERROR_MEMORY_REFRESH);
3884 }
3885 I915_WRITE(EMR, error_mask);
3886
3887 I915_WRITE(IMR, dev_priv->irq_mask);
3888 I915_WRITE(IER, enable_mask);
3889 POSTING_READ(IER);
3890
20afbda2
DV		 3891 I915_WRITE(PORT_HOTPLUG_EN, 0);
3892 POSTING_READ(PORT_HOTPLUG_EN);
3893
f49e38dd 3894 i915_enable_asle_pipestat(dev);
20afbda2
DV		 3895
3896 return 0;
3897}
3898
bac56d5b 3899static void i915_hpd_irq_setup(struct drm_device *dev)
20afbda2 3900{
2d1013dd 3901 struct drm_i915_private *dev_priv = dev->dev_private;
cd569aed 3902 struct intel_encoder *intel_encoder;
20afbda2
DV		 3903 u32 hotplug_en;
3904
b5ea2d56
DV		 3905 assert_spin_locked(&dev_priv->irq_lock);
3906
778eb334
VS		 3907 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3908 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3909 /* Note HDMI and DP share hotplug bits */
3910 /* enable bits are the same for all generations */
3911 for_each_intel_encoder(dev, intel_encoder)
5fcece80 3912 if (dev_priv->hotplug.stats[intel_encoder->hpd_pin].state == HPD_ENABLED)
778eb334
VS		 3913 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
3914 /* Programming the CRT detection parameters tends
3915 to generate a spurious hotplug event about three
3916 seconds later. So just do it once.
3917 */
3918 if (IS_G4X(dev))
3919 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
3920 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
3921 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
3922
3923 /* Ignore TV since it's buggy */
3924 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
a266c7d5
CW		 3925}
3926
ff1f525e 3927static irqreturn_t i965_irq_handler(int irq, void *arg)
a266c7d5 3928{
45a83f84 3929 struct drm_device *dev = arg;
2d1013dd 3930 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 3931 u32 iir, new_iir;
3932 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5 3933 int ret = IRQ_NONE, pipe;
21ad8330
VS		 3934 u32 flip_mask =
3935 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3936 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
a266c7d5 3937
2dd2a883
ID		 3938 if (!intel_irqs_enabled(dev_priv))
3939 return IRQ_NONE;
3940
a266c7d5
CW		 3941 iir = I915_READ(IIR);
3942
a266c7d5 3943 for (;;) {
501e01d7 3944 bool irq_received = (iir & ~flip_mask) != 0;
2c8ba29f
CW		 3945 bool blc_event = false;
3946
a266c7d5
CW		 3947 /* Can't rely on pipestat interrupt bit in iir as it might
3948 * have been cleared after the pipestat interrupt was received.
3949 * It doesn't set the bit in iir again, but it still produces
3950 * interrupts (for non-MSI).
3951 */
222c7f51 3952 spin_lock(&dev_priv->irq_lock);
a266c7d5 3953 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
aaecdf61 3954 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
a266c7d5 3955
055e393f 3956 for_each_pipe(dev_priv, pipe) {
a266c7d5
CW		 3957 int reg = PIPESTAT(pipe);
3958 pipe_stats[pipe] = I915_READ(reg);
3959
3960 /*
3961 * Clear the PIPE*STAT regs before the IIR
3962 */
3963 if (pipe_stats[pipe] & 0x8000ffff) {
a266c7d5 3964 I915_WRITE(reg, pipe_stats[pipe]);
501e01d7 3965 irq_received = true;
a266c7d5
CW		 3966 }
3967 }
222c7f51 3968 spin_unlock(&dev_priv->irq_lock);
a266c7d5
CW		 3969
3970 if (!irq_received)
3971 break;
3972
3973 ret = IRQ_HANDLED;
3974
3975 /* Consume port. Then clear IIR or we'll miss events */
16c6c56b
VS		 3976 if (iir & I915_DISPLAY_PORT_INTERRUPT)
3977 i9xx_hpd_irq_handler(dev);
a266c7d5 3978
21ad8330 3979 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 3980 new_iir = I915_READ(IIR); /* Flush posted writes */
3981
a266c7d5 3982 if (iir & I915_USER_INTERRUPT)
74cdb337 3983 notify_ring(&dev_priv->ring[RCS]);
a266c7d5 3984 if (iir & I915_BSD_USER_INTERRUPT)
74cdb337 3985 notify_ring(&dev_priv->ring[VCS]);
a266c7d5 3986
055e393f 3987 for_each_pipe(dev_priv, pipe) {
2c8ba29f 3988 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3989 i915_handle_vblank(dev, pipe, pipe, iir))
3990 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
a266c7d5
CW		 3991
3992 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3993 blc_event = true;
4356d586
DV		 3994
3995 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
277de95e 3996 i9xx_pipe_crc_irq_handler(dev, pipe);
a266c7d5 3997
1f7247c0
DV		 3998 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3999 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2d9d2b0b 4000 }
a266c7d5
CW		 4001
4002 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4003 intel_opregion_asle_intr(dev);
4004
515ac2bb
DV		 4005 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4006 gmbus_irq_handler(dev);
4007
a266c7d5
CW		 4008 /* With MSI, interrupts are only generated when iir
4009 * transitions from zero to nonzero. If another bit got
4010 * set while we were handling the existing iir bits, then
4011 * we would never get another interrupt.
4012 *
4013 * This is fine on non-MSI as well, as if we hit this path
4014 * we avoid exiting the interrupt handler only to generate
4015 * another one.
4016 *
4017 * Note that for MSI this could cause a stray interrupt report
4018 * if an interrupt landed in the time between writing IIR and
4019 * the posting read. This should be rare enough to never
4020 * trigger the 99% of 100,000 interrupts test for disabling
4021 * stray interrupts.
4022 */
4023 iir = new_iir;
4024 }
4025
4026 return ret;
4027}
4028
4029static void i965_irq_uninstall(struct drm_device * dev)
4030{
2d1013dd 4031 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 4032 int pipe;
4033
4034 if (!dev_priv)
4035 return;
4036
adca4730
CW		 4037 I915_WRITE(PORT_HOTPLUG_EN, 0);
4038 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 4039
4040 I915_WRITE(HWSTAM, 0xffffffff);
055e393f 4041 for_each_pipe(dev_priv, pipe)
a266c7d5
CW		 4042 I915_WRITE(PIPESTAT(pipe), 0);
4043 I915_WRITE(IMR, 0xffffffff);
4044 I915_WRITE(IER, 0x0);
4045
055e393f 4046 for_each_pipe(dev_priv, pipe)
a266c7d5
CW		 4047 I915_WRITE(PIPESTAT(pipe),
4048 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4049 I915_WRITE(IIR, I915_READ(IIR));
4050}
4051
fca52a55
DV		 4052/**
4053 * intel_irq_init - initializes irq support
4054 * @dev_priv: i915 device instance
4055 *
4056 * This function initializes all the irq support including work items, timers
4057 * and all the vtables. It does not setup the interrupt itself though.
4058 */
b963291c 4059void intel_irq_init(struct drm_i915_private *dev_priv)
f71d4af4 4060{
b963291c 4061 struct drm_device *dev = dev_priv->dev;
8b2e326d 4062
77913b39
JN		 4063 intel_hpd_init_work(dev_priv);
4064
c6a828d3 4065 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
a4da4fa4 4066 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
8b2e326d 4067
a6706b45 4068 /* Let's track the enabled rps events */
b963291c 4069 if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
6c65a587 4070 /* WaGsvRC0ResidencyMethod:vlv */
6f4b12f8 4071 dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
31685c25
D		 4072 else
4073 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
a6706b45 4074
737b1506
CW		 4075 INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
4076 i915_hangcheck_elapsed);
61bac78e 4077
97a19a24 4078 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
9ee32fea 4079
b963291c 4080 if (IS_GEN2(dev_priv)) {
4cdb83ec
VS		 4081 dev->max_vblank_count = 0;
4082 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
b963291c 4083 } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
f71d4af4
JB		 4084 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4085 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
391f75e2
VS		 4086 } else {
4087 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4088 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
f71d4af4
JB		 4089 }
4090
21da2700
VS		 4091 /*
4092 * Opt out of the vblank disable timer on everything except gen2.
4093 * Gen2 doesn't have a hardware frame counter and so depends on
4094 * vblank interrupts to produce sane vblank seuquence numbers.
4095 */
b963291c 4096 if (!IS_GEN2(dev_priv))
21da2700
VS		 4097 dev->vblank_disable_immediate = true;
4098
f3a5c3f6
DV		 4099 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4100 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
f71d4af4 4101
b963291c 4102 if (IS_CHERRYVIEW(dev_priv)) {
43f328d7
VS		 4103 dev->driver->irq_handler = cherryview_irq_handler;
4104 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4105 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4106 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4107 dev->driver->enable_vblank = valleyview_enable_vblank;
4108 dev->driver->disable_vblank = valleyview_disable_vblank;
4109 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
b963291c 4110 } else if (IS_VALLEYVIEW(dev_priv)) {
7e231dbe
JB		 4111 dev->driver->irq_handler = valleyview_irq_handler;
4112 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4113 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4114 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4115 dev->driver->enable_vblank = valleyview_enable_vblank;
4116 dev->driver->disable_vblank = valleyview_disable_vblank;
fa00abe0 4117 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
b963291c 4118 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
abd58f01 4119 dev->driver->irq_handler = gen8_irq_handler;
723761b8 4120 dev->driver->irq_preinstall = gen8_irq_reset;
abd58f01
BW		 4121 dev->driver->irq_postinstall = gen8_irq_postinstall;
4122 dev->driver->irq_uninstall = gen8_irq_uninstall;
4123 dev->driver->enable_vblank = gen8_enable_vblank;
4124 dev->driver->disable_vblank = gen8_disable_vblank;
e0a20ad7
SS		 4125 if (HAS_PCH_SPLIT(dev))
4126 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4127 else
4128 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
f71d4af4
JB		 4129 } else if (HAS_PCH_SPLIT(dev)) {
4130 dev->driver->irq_handler = ironlake_irq_handler;
723761b8 4131 dev->driver->irq_preinstall = ironlake_irq_reset;
f71d4af4
JB		 4132 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4133 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4134 dev->driver->enable_vblank = ironlake_enable_vblank;
4135 dev->driver->disable_vblank = ironlake_disable_vblank;
82a28bcf 4136 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4 4137 } else {
b963291c 4138 if (INTEL_INFO(dev_priv)->gen == 2) {
c2798b19
CW		 4139 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4140 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4141 dev->driver->irq_handler = i8xx_irq_handler;
4142 dev->driver->irq_uninstall = i8xx_irq_uninstall;
b963291c 4143 } else if (INTEL_INFO(dev_priv)->gen == 3) {
a266c7d5
CW		 4144 dev->driver->irq_preinstall = i915_irq_preinstall;
4145 dev->driver->irq_postinstall = i915_irq_postinstall;
4146 dev->driver->irq_uninstall = i915_irq_uninstall;
4147 dev->driver->irq_handler = i915_irq_handler;
c2798b19 4148 } else {
a266c7d5
CW		 4149 dev->driver->irq_preinstall = i965_irq_preinstall;
4150 dev->driver->irq_postinstall = i965_irq_postinstall;
4151 dev->driver->irq_uninstall = i965_irq_uninstall;
4152 dev->driver->irq_handler = i965_irq_handler;
c2798b19 4153 }
778eb334
VS		 4154 if (I915_HAS_HOTPLUG(dev_priv))
4155 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
f71d4af4
JB		 4156 dev->driver->enable_vblank = i915_enable_vblank;
4157 dev->driver->disable_vblank = i915_disable_vblank;
4158 }
4159}
20afbda2 4160
fca52a55
DV		 4161/**
4162 * intel_irq_install - enables the hardware interrupt
4163 * @dev_priv: i915 device instance
4164 *
4165 * This function enables the hardware interrupt handling, but leaves the hotplug
4166 * handling still disabled. It is called after intel_irq_init().
4167 *
4168 * In the driver load and resume code we need working interrupts in a few places
4169 * but don't want to deal with the hassle of concurrent probe and hotplug
4170 * workers. Hence the split into this two-stage approach.
4171 */
2aeb7d3a
DV		 4172int intel_irq_install(struct drm_i915_private *dev_priv)
4173{
4174 /*
4175 * We enable some interrupt sources in our postinstall hooks, so mark
4176 * interrupts as enabled _before_ actually enabling them to avoid
4177 * special cases in our ordering checks.
4178 */
4179 dev_priv->pm.irqs_enabled = true;
4180
4181 return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
4182}
4183
fca52a55
DV		 4184/**
4185 * intel_irq_uninstall - finilizes all irq handling
4186 * @dev_priv: i915 device instance
4187 *
4188 * This stops interrupt and hotplug handling and unregisters and frees all
4189 * resources acquired in the init functions.
4190 */
2aeb7d3a
DV		 4191void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4192{
4193 drm_irq_uninstall(dev_priv->dev);
4194 intel_hpd_cancel_work(dev_priv);
4195 dev_priv->pm.irqs_enabled = false;
4196}
4197
fca52a55
DV		 4198/**
4199 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4200 * @dev_priv: i915 device instance
4201 *
4202 * This function is used to disable interrupts at runtime, both in the runtime
4203 * pm and the system suspend/resume code.
4204 */
b963291c 4205void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
c67a470b 4206{
b963291c 4207 dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
2aeb7d3a 4208 dev_priv->pm.irqs_enabled = false;
2dd2a883 4209 synchronize_irq(dev_priv->dev->irq);
c67a470b
PZ		 4210}
4211
fca52a55
DV		 4212/**
4213 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4214 * @dev_priv: i915 device instance
4215 *
4216 * This function is used to enable interrupts at runtime, both in the runtime
4217 * pm and the system suspend/resume code.
4218 */
b963291c 4219void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
c67a470b 4220{
2aeb7d3a 4221 dev_priv->pm.irqs_enabled = true;
b963291c
DV		 4222 dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
4223 dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
c67a470b 4224}
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