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drm/i915: Refactor gen2 to gen4 vblank interrupt handling
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/i915_drm.h>
1da177e4 35#include "i915_drv.h"
1c5d22f7 36#include "i915_trace.h"
79e53945 37#include "intel_drv.h"
1da177e4 38
036a4a7d 39/* For display hotplug interrupt */
995b6762 40static void
f2b115e6 41ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 42{
1ec14ad3
CW		 43 if ((dev_priv->irq_mask & mask) != 0) {
44 dev_priv->irq_mask &= ~mask;
45 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 46 POSTING_READ(DEIMR);
036a4a7d
ZW		 47 }
48}
49
50static inline void
f2b115e6 51ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 52{
1ec14ad3
CW		 53 if ((dev_priv->irq_mask & mask) != mask) {
54 dev_priv->irq_mask |= mask;
55 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 56 POSTING_READ(DEIMR);
036a4a7d
ZW		 57 }
58}
59
7c463586
KP		 60void
61i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
62{
63 if ((dev_priv->pipestat[pipe] & mask) != mask) {
9db4a9c7 64 u32 reg = PIPESTAT(pipe);
7c463586
KP		 65
66 dev_priv->pipestat[pipe] |= mask;
67 /* Enable the interrupt, clear any pending status */
68 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
3143a2bf 69 POSTING_READ(reg);
7c463586
KP		 70 }
71}
72
73void
74i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
75{
76 if ((dev_priv->pipestat[pipe] & mask) != 0) {
9db4a9c7 77 u32 reg = PIPESTAT(pipe);
7c463586
KP		 78
79 dev_priv->pipestat[pipe] &= ~mask;
80 I915_WRITE(reg, dev_priv->pipestat[pipe]);
3143a2bf 81 POSTING_READ(reg);
7c463586
KP		 82 }
83}
84
01c66889
ZY		 85/**
86 * intel_enable_asle - enable ASLE interrupt for OpRegion
87 */
1ec14ad3 88void intel_enable_asle(struct drm_device *dev)
01c66889 89{
1ec14ad3
CW		 90 drm_i915_private_t *dev_priv = dev->dev_private;
91 unsigned long irqflags;
92
7e231dbe
JB		 93 /* FIXME: opregion/asle for VLV */
94 if (IS_VALLEYVIEW(dev))
95 return;
96
1ec14ad3 97 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 98
c619eed4 99 if (HAS_PCH_SPLIT(dev))
f2b115e6 100 ironlake_enable_display_irq(dev_priv, DE_GSE);
edcb49ca 101 else {
01c66889 102 i915_enable_pipestat(dev_priv, 1,
d874bcff 103 PIPE_LEGACY_BLC_EVENT_ENABLE);
a6c45cf0 104 if (INTEL_INFO(dev)->gen >= 4)
edcb49ca 105 i915_enable_pipestat(dev_priv, 0,
d874bcff 106 PIPE_LEGACY_BLC_EVENT_ENABLE);
edcb49ca 107 }
1ec14ad3
CW		 108
109 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 110}
111
0a3e67a4
JB		 112/**
113 * i915_pipe_enabled - check if a pipe is enabled
114 * @dev: DRM device
115 * @pipe: pipe to check
116 *
117 * Reading certain registers when the pipe is disabled can hang the chip.
118 * Use this routine to make sure the PLL is running and the pipe is active
119 * before reading such registers if unsure.
120 */
121static int
122i915_pipe_enabled(struct drm_device *dev, int pipe)
123{
124 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
702e7a56
PZ		 125 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
126 pipe);
127
128 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
0a3e67a4
JB		 129}
130
42f52ef8
KP		 131/* Called from drm generic code, passed a 'crtc', which
132 * we use as a pipe index
133 */
f71d4af4 134static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 135{
136 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
137 unsigned long high_frame;
138 unsigned long low_frame;
5eddb70b 139 u32 high1, high2, low;
0a3e67a4
JB		 140
141 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 142 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 143 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 144 return 0;
145 }
146
9db4a9c7
JB		 147 high_frame = PIPEFRAME(pipe);
148 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 149
0a3e67a4
JB		 150 /*
151 * High & low register fields aren't synchronized, so make sure
152 * we get a low value that's stable across two reads of the high
153 * register.
154 */
155 do {
5eddb70b
CW		 156 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
157 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
158 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 159 } while (high1 != high2);
160
5eddb70b
CW		 161 high1 >>= PIPE_FRAME_HIGH_SHIFT;
162 low >>= PIPE_FRAME_LOW_SHIFT;
163 return (high1 << 8) | low;
0a3e67a4
JB		 164}
165
f71d4af4 166static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 167{
168 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 169 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 170
171 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 172 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 173 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 174 return 0;
175 }
176
177 return I915_READ(reg);
178}
179
f71d4af4 180static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 181 int *vpos, int *hpos)
182{
183 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
184 u32 vbl = 0, position = 0;
185 int vbl_start, vbl_end, htotal, vtotal;
186 bool in_vbl = true;
187 int ret = 0;
fe2b8f9d
PZ		 188 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
189 pipe);
0af7e4df
MK		 190
191 if (!i915_pipe_enabled(dev, pipe)) {
192 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 193 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 194 return 0;
195 }
196
197 /* Get vtotal. */
fe2b8f9d 198 vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 199
200 if (INTEL_INFO(dev)->gen >= 4) {
201 /* No obvious pixelcount register. Only query vertical
202 * scanout position from Display scan line register.
203 */
204 position = I915_READ(PIPEDSL(pipe));
205
206 /* Decode into vertical scanout position. Don't have
207 * horizontal scanout position.
208 */
209 *vpos = position & 0x1fff;
210 *hpos = 0;
211 } else {
212 /* Have access to pixelcount since start of frame.
213 * We can split this into vertical and horizontal
214 * scanout position.
215 */
216 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
217
fe2b8f9d 218 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 219 *vpos = position / htotal;
220 *hpos = position - (*vpos * htotal);
221 }
222
223 /* Query vblank area. */
fe2b8f9d 224 vbl = I915_READ(VBLANK(cpu_transcoder));
0af7e4df
MK		 225
226 /* Test position against vblank region. */
227 vbl_start = vbl & 0x1fff;
228 vbl_end = (vbl >> 16) & 0x1fff;
229
230 if ((*vpos < vbl_start) || (*vpos > vbl_end))
231 in_vbl = false;
232
233 /* Inside "upper part" of vblank area? Apply corrective offset: */
234 if (in_vbl && (*vpos >= vbl_start))
235 *vpos = *vpos - vtotal;
236
237 /* Readouts valid? */
238 if (vbl > 0)
239 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
240
241 /* In vblank? */
242 if (in_vbl)
243 ret |= DRM_SCANOUTPOS_INVBL;
244
245 return ret;
246}
247
f71d4af4 248static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 249 int *max_error,
250 struct timeval *vblank_time,
251 unsigned flags)
252{
4041b853
CW		 253 struct drm_i915_private *dev_priv = dev->dev_private;
254 struct drm_crtc *crtc;
0af7e4df 255
4041b853
CW		 256 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
257 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 258 return -EINVAL;
259 }
260
261 /* Get drm_crtc to timestamp: */
4041b853
CW		 262 crtc = intel_get_crtc_for_pipe(dev, pipe);
263 if (crtc == NULL) {
264 DRM_ERROR("Invalid crtc %d\n", pipe);
265 return -EINVAL;
266 }
267
268 if (!crtc->enabled) {
269 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
270 return -EBUSY;
271 }
0af7e4df
MK		 272
273 /* Helper routine in DRM core does all the work: */
4041b853
CW		 274 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
275 vblank_time, flags,
276 crtc);
0af7e4df
MK		 277}
278
5ca58282
JB		 279/*
280 * Handle hotplug events outside the interrupt handler proper.
281 */
282static void i915_hotplug_work_func(struct work_struct *work)
283{
284 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
285 hotplug_work);
286 struct drm_device *dev = dev_priv->dev;
c31c4ba3 287 struct drm_mode_config *mode_config = &dev->mode_config;
4ef69c7a
CW		 288 struct intel_encoder *encoder;
289
52d7eced
DV		 290 /* HPD irq before everything is fully set up. */
291 if (!dev_priv->enable_hotplug_processing)
292 return;
293
a65e34c7 294 mutex_lock(&mode_config->mutex);
e67189ab
JB		 295 DRM_DEBUG_KMS("running encoder hotplug functions\n");
296
4ef69c7a
CW		 297 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
298 if (encoder->hot_plug)
299 encoder->hot_plug(encoder);
300
40ee3381
KP		 301 mutex_unlock(&mode_config->mutex);
302
5ca58282 303 /* Just fire off a uevent and let userspace tell us what to do */
eb1f8e4f 304 drm_helper_hpd_irq_event(dev);
5ca58282
JB		 305}
306
73edd18f 307static void ironlake_handle_rps_change(struct drm_device *dev)
f97108d1
JB		 308{
309 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 310 u32 busy_up, busy_down, max_avg, min_avg;
9270388e
DV		 311 u8 new_delay;
312 unsigned long flags;
313
314 spin_lock_irqsave(&mchdev_lock, flags);
f97108d1 315
73edd18f
DV		 316 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
317
20e4d407 318 new_delay = dev_priv->ips.cur_delay;
9270388e 319
7648fa99 320 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 321 busy_up = I915_READ(RCPREVBSYTUPAVG);
322 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 323 max_avg = I915_READ(RCBMAXAVG);
324 min_avg = I915_READ(RCBMINAVG);
325
326 /* Handle RCS change request from hw */
b5b72e89 327 if (busy_up > max_avg) {
20e4d407
DV		 328 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
329 new_delay = dev_priv->ips.cur_delay - 1;
330 if (new_delay < dev_priv->ips.max_delay)
331 new_delay = dev_priv->ips.max_delay;
b5b72e89 332 } else if (busy_down < min_avg) {
20e4d407
DV		 333 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
334 new_delay = dev_priv->ips.cur_delay + 1;
335 if (new_delay > dev_priv->ips.min_delay)
336 new_delay = dev_priv->ips.min_delay;
f97108d1
JB		 337 }
338
7648fa99 339 if (ironlake_set_drps(dev, new_delay))
20e4d407 340 dev_priv->ips.cur_delay = new_delay;
f97108d1 341
9270388e
DV		 342 spin_unlock_irqrestore(&mchdev_lock, flags);
343
f97108d1
JB		 344 return;
345}
346
549f7365
CW		 347static void notify_ring(struct drm_device *dev,
348 struct intel_ring_buffer *ring)
349{
350 struct drm_i915_private *dev_priv = dev->dev_private;
9862e600 351
475553de
CW		 352 if (ring->obj == NULL)
353 return;
354
b2eadbc8 355 trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
9862e600 356
549f7365 357 wake_up_all(&ring->irq_queue);
3e0dc6b0 358 if (i915_enable_hangcheck) {
99584db3
DV		 359 dev_priv->gpu_error.hangcheck_count = 0;
360 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
cecc21fe 361 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
3e0dc6b0 362 }
549f7365
CW		 363}
364
4912d041 365static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 366{
4912d041 367 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
c6a828d3 368 rps.work);
4912d041 369 u32 pm_iir, pm_imr;
7b9e0ae6 370 u8 new_delay;
4912d041 371
c6a828d3
DV		 372 spin_lock_irq(&dev_priv->rps.lock);
373 pm_iir = dev_priv->rps.pm_iir;
374 dev_priv->rps.pm_iir = 0;
4912d041 375 pm_imr = I915_READ(GEN6_PMIMR);
a9e2641d 376 I915_WRITE(GEN6_PMIMR, 0);
c6a828d3 377 spin_unlock_irq(&dev_priv->rps.lock);
3b8d8d91 378
7b9e0ae6 379 if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
3b8d8d91
JB		 380 return;
381
4fc688ce 382 mutex_lock(&dev_priv->rps.hw_lock);
7b9e0ae6
CW		 383
384 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
c6a828d3 385 new_delay = dev_priv->rps.cur_delay + 1;
7b9e0ae6 386 else
c6a828d3 387 new_delay = dev_priv->rps.cur_delay - 1;
3b8d8d91 388
79249636
BW		 389 /* sysfs frequency interfaces may have snuck in while servicing the
390 * interrupt
391 */
392 if (!(new_delay > dev_priv->rps.max_delay ||
393 new_delay < dev_priv->rps.min_delay)) {
394 gen6_set_rps(dev_priv->dev, new_delay);
395 }
3b8d8d91 396
4fc688ce 397 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91
JB		 398}
399
e3689190
BW		 400
401/**
402 * ivybridge_parity_work - Workqueue called when a parity error interrupt
403 * occurred.
404 * @work: workqueue struct
405 *
406 * Doesn't actually do anything except notify userspace. As a consequence of
407 * this event, userspace should try to remap the bad rows since statistically
408 * it is likely the same row is more likely to go bad again.
409 */
410static void ivybridge_parity_work(struct work_struct *work)
411{
412 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
a4da4fa4 413 l3_parity.error_work);
e3689190
BW		 414 u32 error_status, row, bank, subbank;
415 char *parity_event[5];
416 uint32_t misccpctl;
417 unsigned long flags;
418
419 /* We must turn off DOP level clock gating to access the L3 registers.
420 * In order to prevent a get/put style interface, acquire struct mutex
421 * any time we access those registers.
422 */
423 mutex_lock(&dev_priv->dev->struct_mutex);
424
425 misccpctl = I915_READ(GEN7_MISCCPCTL);
426 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
427 POSTING_READ(GEN7_MISCCPCTL);
428
429 error_status = I915_READ(GEN7_L3CDERRST1);
430 row = GEN7_PARITY_ERROR_ROW(error_status);
431 bank = GEN7_PARITY_ERROR_BANK(error_status);
432 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
433
434 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
435 GEN7_L3CDERRST1_ENABLE);
436 POSTING_READ(GEN7_L3CDERRST1);
437
438 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
439
440 spin_lock_irqsave(&dev_priv->irq_lock, flags);
441 dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
442 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
443 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
444
445 mutex_unlock(&dev_priv->dev->struct_mutex);
446
447 parity_event[0] = "L3_PARITY_ERROR=1";
448 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
449 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
450 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
451 parity_event[4] = NULL;
452
453 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
454 KOBJ_CHANGE, parity_event);
455
456 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
457 row, bank, subbank);
458
459 kfree(parity_event[3]);
460 kfree(parity_event[2]);
461 kfree(parity_event[1]);
462}
463
d2ba8470 464static void ivybridge_handle_parity_error(struct drm_device *dev)
e3689190
BW		 465{
466 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
467 unsigned long flags;
468
e1ef7cc2 469 if (!HAS_L3_GPU_CACHE(dev))
e3689190
BW		 470 return;
471
472 spin_lock_irqsave(&dev_priv->irq_lock, flags);
473 dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
474 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
475 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
476
a4da4fa4 477 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
e3689190
BW		 478}
479
e7b4c6b1
DV		 480static void snb_gt_irq_handler(struct drm_device *dev,
481 struct drm_i915_private *dev_priv,
482 u32 gt_iir)
483{
484
485 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
486 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
487 notify_ring(dev, &dev_priv->ring[RCS]);
488 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
489 notify_ring(dev, &dev_priv->ring[VCS]);
490 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
491 notify_ring(dev, &dev_priv->ring[BCS]);
492
493 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
494 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
495 GT_RENDER_CS_ERROR_INTERRUPT)) {
496 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
497 i915_handle_error(dev, false);
498 }
e3689190
BW		 499
500 if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
501 ivybridge_handle_parity_error(dev);
e7b4c6b1
DV		 502}
503
fc6826d1
CW		 504static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
505 u32 pm_iir)
506{
507 unsigned long flags;
508
509 /*
510 * IIR bits should never already be set because IMR should
511 * prevent an interrupt from being shown in IIR. The warning
512 * displays a case where we've unsafely cleared
c6a828d3 513 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
fc6826d1
CW		 514 * type is not a problem, it displays a problem in the logic.
515 *
c6a828d3 516 * The mask bit in IMR is cleared by dev_priv->rps.work.
fc6826d1
CW		 517 */
518
c6a828d3 519 spin_lock_irqsave(&dev_priv->rps.lock, flags);
c6a828d3
DV		 520 dev_priv->rps.pm_iir |= pm_iir;
521 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
fc6826d1 522 POSTING_READ(GEN6_PMIMR);
c6a828d3 523 spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
fc6826d1 524
c6a828d3 525 queue_work(dev_priv->wq, &dev_priv->rps.work);
fc6826d1
CW		 526}
527
515ac2bb
DV		 528static void gmbus_irq_handler(struct drm_device *dev)
529{
28c70f16
DV		 530 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
531
28c70f16 532 wake_up_all(&dev_priv->gmbus_wait_queue);
515ac2bb
DV		 533}
534
ce99c256
DV		 535static void dp_aux_irq_handler(struct drm_device *dev)
536{
9ee32fea
DV		 537 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
538
9ee32fea 539 wake_up_all(&dev_priv->gmbus_wait_queue);
ce99c256
DV		 540}
541
ff1f525e 542static irqreturn_t valleyview_irq_handler(int irq, void *arg)
7e231dbe
JB		 543{
544 struct drm_device *dev = (struct drm_device *) arg;
545 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
546 u32 iir, gt_iir, pm_iir;
547 irqreturn_t ret = IRQ_NONE;
548 unsigned long irqflags;
549 int pipe;
550 u32 pipe_stats[I915_MAX_PIPES];
7e231dbe
JB		 551
552 atomic_inc(&dev_priv->irq_received);
553
7e231dbe
JB		 554 while (true) {
555 iir = I915_READ(VLV_IIR);
556 gt_iir = I915_READ(GTIIR);
557 pm_iir = I915_READ(GEN6_PMIIR);
558
559 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
560 goto out;
561
562 ret = IRQ_HANDLED;
563
e7b4c6b1 564 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 565
566 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
567 for_each_pipe(pipe) {
568 int reg = PIPESTAT(pipe);
569 pipe_stats[pipe] = I915_READ(reg);
570
571 /*
572 * Clear the PIPE*STAT regs before the IIR
573 */
574 if (pipe_stats[pipe] & 0x8000ffff) {
575 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
576 DRM_DEBUG_DRIVER("pipe %c underrun\n",
577 pipe_name(pipe));
578 I915_WRITE(reg, pipe_stats[pipe]);
579 }
580 }
581 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
582
31acc7f5
JB		 583 for_each_pipe(pipe) {
584 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
585 drm_handle_vblank(dev, pipe);
586
587 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
588 intel_prepare_page_flip(dev, pipe);
589 intel_finish_page_flip(dev, pipe);
590 }
591 }
592
7e231dbe
JB		 593 /* Consume port. Then clear IIR or we'll miss events */
594 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
595 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
596
597 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
598 hotplug_status);
599 if (hotplug_status & dev_priv->hotplug_supported_mask)
600 queue_work(dev_priv->wq,
601 &dev_priv->hotplug_work);
602
603 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
604 I915_READ(PORT_HOTPLUG_STAT);
605 }
606
515ac2bb
DV		 607 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
608 gmbus_irq_handler(dev);
7e231dbe 609
fc6826d1
CW		 610 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
611 gen6_queue_rps_work(dev_priv, pm_iir);
7e231dbe
JB		 612
613 I915_WRITE(GTIIR, gt_iir);
614 I915_WRITE(GEN6_PMIIR, pm_iir);
615 I915_WRITE(VLV_IIR, iir);
616 }
617
618out:
619 return ret;
620}
621
23e81d69 622static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 623{
624 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 625 int pipe;
776ad806 626
76e43830
DV		 627 if (pch_iir & SDE_HOTPLUG_MASK)
628 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
629
776ad806
JB		 630 if (pch_iir & SDE_AUDIO_POWER_MASK)
631 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
632 (pch_iir & SDE_AUDIO_POWER_MASK) >>
633 SDE_AUDIO_POWER_SHIFT);
634
ce99c256
DV		 635 if (pch_iir & SDE_AUX_MASK)
636 dp_aux_irq_handler(dev);
637
776ad806 638 if (pch_iir & SDE_GMBUS)
515ac2bb 639 gmbus_irq_handler(dev);
776ad806
JB		 640
641 if (pch_iir & SDE_AUDIO_HDCP_MASK)
642 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
643
644 if (pch_iir & SDE_AUDIO_TRANS_MASK)
645 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
646
647 if (pch_iir & SDE_POISON)
648 DRM_ERROR("PCH poison interrupt\n");
649
9db4a9c7
JB		 650 if (pch_iir & SDE_FDI_MASK)
651 for_each_pipe(pipe)
652 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
653 pipe_name(pipe),
654 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 655
656 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
657 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
658
659 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
660 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
661
662 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
663 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
664 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
665 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
666}
667
23e81d69
AJ		 668static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
669{
670 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
671 int pipe;
672
76e43830
DV		 673 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
674 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
675
23e81d69
AJ		 676 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
677 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
678 (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
679 SDE_AUDIO_POWER_SHIFT_CPT);
680
681 if (pch_iir & SDE_AUX_MASK_CPT)
ce99c256 682 dp_aux_irq_handler(dev);
23e81d69
AJ		 683
684 if (pch_iir & SDE_GMBUS_CPT)
515ac2bb 685 gmbus_irq_handler(dev);
23e81d69
AJ		 686
687 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
688 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
689
690 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
691 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
692
693 if (pch_iir & SDE_FDI_MASK_CPT)
694 for_each_pipe(pipe)
695 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
696 pipe_name(pipe),
697 I915_READ(FDI_RX_IIR(pipe)));
698}
699
ff1f525e 700static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
b1f14ad0
JB		 701{
702 struct drm_device *dev = (struct drm_device *) arg;
703 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
0e43406b
CW		 704 u32 de_iir, gt_iir, de_ier, pm_iir;
705 irqreturn_t ret = IRQ_NONE;
706 int i;
b1f14ad0
JB		 707
708 atomic_inc(&dev_priv->irq_received);
709
710 /* disable master interrupt before clearing iir */
711 de_ier = I915_READ(DEIER);
712 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
b1f14ad0 713
b1f14ad0 714 gt_iir = I915_READ(GTIIR);
0e43406b
CW		 715 if (gt_iir) {
716 snb_gt_irq_handler(dev, dev_priv, gt_iir);
717 I915_WRITE(GTIIR, gt_iir);
718 ret = IRQ_HANDLED;
b1f14ad0
JB		 719 }
720
0e43406b
CW		 721 de_iir = I915_READ(DEIIR);
722 if (de_iir) {
ce99c256
DV		 723 if (de_iir & DE_AUX_CHANNEL_A_IVB)
724 dp_aux_irq_handler(dev);
725
0e43406b
CW		 726 if (de_iir & DE_GSE_IVB)
727 intel_opregion_gse_intr(dev);
728
729 for (i = 0; i < 3; i++) {
74d44445
DV		 730 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
731 drm_handle_vblank(dev, i);
0e43406b
CW		 732 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
733 intel_prepare_page_flip(dev, i);
734 intel_finish_page_flip_plane(dev, i);
735 }
0e43406b 736 }
b615b57a 737
0e43406b
CW		 738 /* check event from PCH */
739 if (de_iir & DE_PCH_EVENT_IVB) {
740 u32 pch_iir = I915_READ(SDEIIR);
b1f14ad0 741
23e81d69 742 cpt_irq_handler(dev, pch_iir);
b1f14ad0 743
0e43406b
CW		 744 /* clear PCH hotplug event before clear CPU irq */
745 I915_WRITE(SDEIIR, pch_iir);
746 }
b615b57a 747
0e43406b
CW		 748 I915_WRITE(DEIIR, de_iir);
749 ret = IRQ_HANDLED;
b1f14ad0
JB		 750 }
751
0e43406b
CW		 752 pm_iir = I915_READ(GEN6_PMIIR);
753 if (pm_iir) {
754 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
755 gen6_queue_rps_work(dev_priv, pm_iir);
756 I915_WRITE(GEN6_PMIIR, pm_iir);
757 ret = IRQ_HANDLED;
758 }
b1f14ad0 759
b1f14ad0
JB		 760 I915_WRITE(DEIER, de_ier);
761 POSTING_READ(DEIER);
762
763 return ret;
764}
765
e7b4c6b1
DV		 766static void ilk_gt_irq_handler(struct drm_device *dev,
767 struct drm_i915_private *dev_priv,
768 u32 gt_iir)
769{
770 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
771 notify_ring(dev, &dev_priv->ring[RCS]);
772 if (gt_iir & GT_BSD_USER_INTERRUPT)
773 notify_ring(dev, &dev_priv->ring[VCS]);
774}
775
ff1f525e 776static irqreturn_t ironlake_irq_handler(int irq, void *arg)
036a4a7d 777{
4697995b 778 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 779 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
780 int ret = IRQ_NONE;
acd15b6c 781 u32 de_iir, gt_iir, de_ier, pm_iir;
881f47b6 782
4697995b
JB		 783 atomic_inc(&dev_priv->irq_received);
784
2d109a84
ZN		 785 /* disable master interrupt before clearing iir */
786 de_ier = I915_READ(DEIER);
787 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 788 POSTING_READ(DEIER);
2d109a84 789
036a4a7d
ZW		 790 de_iir = I915_READ(DEIIR);
791 gt_iir = I915_READ(GTIIR);
3b8d8d91 792 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 793
acd15b6c 794 if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 795 goto done;
036a4a7d 796
c7c85101 797 ret = IRQ_HANDLED;
036a4a7d 798
e7b4c6b1
DV		 799 if (IS_GEN5(dev))
800 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
801 else
802 snb_gt_irq_handler(dev, dev_priv, gt_iir);
01c66889 803
ce99c256
DV		 804 if (de_iir & DE_AUX_CHANNEL_A)
805 dp_aux_irq_handler(dev);
806
c7c85101 807 if (de_iir & DE_GSE)
3b617967 808 intel_opregion_gse_intr(dev);
c650156a 809
74d44445
DV		 810 if (de_iir & DE_PIPEA_VBLANK)
811 drm_handle_vblank(dev, 0);
812
813 if (de_iir & DE_PIPEB_VBLANK)
814 drm_handle_vblank(dev, 1);
815
f072d2e7 816 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 817 intel_prepare_page_flip(dev, 0);
2bbda389 818 intel_finish_page_flip_plane(dev, 0);
f072d2e7 819 }
013d5aa2 820
f072d2e7 821 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 822 intel_prepare_page_flip(dev, 1);
2bbda389 823 intel_finish_page_flip_plane(dev, 1);
f072d2e7 824 }
013d5aa2 825
c7c85101 826 /* check event from PCH */
776ad806 827 if (de_iir & DE_PCH_EVENT) {
acd15b6c
DV		 828 u32 pch_iir = I915_READ(SDEIIR);
829
23e81d69
AJ		 830 if (HAS_PCH_CPT(dev))
831 cpt_irq_handler(dev, pch_iir);
832 else
833 ibx_irq_handler(dev, pch_iir);
acd15b6c
DV		 834
835 /* should clear PCH hotplug event before clear CPU irq */
836 I915_WRITE(SDEIIR, pch_iir);
776ad806 837 }
036a4a7d 838
73edd18f
DV		 839 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
840 ironlake_handle_rps_change(dev);
f97108d1 841
fc6826d1
CW		 842 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
843 gen6_queue_rps_work(dev_priv, pm_iir);
3b8d8d91 844
c7c85101
ZN		 845 I915_WRITE(GTIIR, gt_iir);
846 I915_WRITE(DEIIR, de_iir);
4912d041 847 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 848
849done:
2d109a84 850 I915_WRITE(DEIER, de_ier);
3143a2bf 851 POSTING_READ(DEIER);
2d109a84 852
036a4a7d
ZW		 853 return ret;
854}
855
8a905236
JB		 856/**
857 * i915_error_work_func - do process context error handling work
858 * @work: work struct
859 *
860 * Fire an error uevent so userspace can see that a hang or error
861 * was detected.
862 */
863static void i915_error_work_func(struct work_struct *work)
864{
1f83fee0
DV		 865 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
866 work);
867 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
868 gpu_error);
8a905236 869 struct drm_device *dev = dev_priv->dev;
f69061be 870 struct intel_ring_buffer *ring;
f316a42c
BG		 871 char *error_event[] = { "ERROR=1", NULL };
872 char *reset_event[] = { "RESET=1", NULL };
873 char *reset_done_event[] = { "ERROR=0", NULL };
f69061be 874 int i, ret;
8a905236 875
f316a42c
BG		 876 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
877
7db0ba24
DV		 878 /*
879 * Note that there's only one work item which does gpu resets, so we
880 * need not worry about concurrent gpu resets potentially incrementing
881 * error->reset_counter twice. We only need to take care of another
882 * racing irq/hangcheck declaring the gpu dead for a second time. A
883 * quick check for that is good enough: schedule_work ensures the
884 * correct ordering between hang detection and this work item, and since
885 * the reset in-progress bit is only ever set by code outside of this
886 * work we don't need to worry about any other races.
887 */
888 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
f803aa55 889 DRM_DEBUG_DRIVER("resetting chip\n");
7db0ba24
DV		 890 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
891 reset_event);
1f83fee0 892
f69061be
DV		 893 ret = i915_reset(dev);
894
895 if (ret == 0) {
896 /*
897 * After all the gem state is reset, increment the reset
898 * counter and wake up everyone waiting for the reset to
899 * complete.
900 *
901 * Since unlock operations are a one-sided barrier only,
902 * we need to insert a barrier here to order any seqno
903 * updates before
904 * the counter increment.
905 */
906 smp_mb__before_atomic_inc();
907 atomic_inc(&dev_priv->gpu_error.reset_counter);
908
909 kobject_uevent_env(&dev->primary->kdev.kobj,
910 KOBJ_CHANGE, reset_done_event);
1f83fee0
DV		 911 } else {
912 atomic_set(&error->reset_counter, I915_WEDGED);
f316a42c 913 }
1f83fee0 914
f69061be
DV		 915 for_each_ring(ring, dev_priv, i)
916 wake_up_all(&ring->irq_queue);
917
96a02917
VS		 918 intel_display_handle_reset(dev);
919
1f83fee0 920 wake_up_all(&dev_priv->gpu_error.reset_queue);
f316a42c 921 }
8a905236
JB		 922}
923
85f9e50d
DV		 924/* NB: please notice the memset */
925static void i915_get_extra_instdone(struct drm_device *dev,
926 uint32_t *instdone)
927{
928 struct drm_i915_private *dev_priv = dev->dev_private;
929 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
930
931 switch(INTEL_INFO(dev)->gen) {
932 case 2:
933 case 3:
934 instdone[0] = I915_READ(INSTDONE);
935 break;
936 case 4:
937 case 5:
938 case 6:
939 instdone[0] = I915_READ(INSTDONE_I965);
940 instdone[1] = I915_READ(INSTDONE1);
941 break;
942 default:
943 WARN_ONCE(1, "Unsupported platform\n");
944 case 7:
945 instdone[0] = I915_READ(GEN7_INSTDONE_1);
946 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
947 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
948 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
949 break;
950 }
951}
952
3bd3c932 953#ifdef CONFIG_DEBUG_FS
9df30794 954static struct drm_i915_error_object *
bcfb2e28 955i915_error_object_create(struct drm_i915_private *dev_priv,
05394f39 956 struct drm_i915_gem_object *src)
9df30794
CW		 957{
958 struct drm_i915_error_object *dst;
9da3da66 959 int i, count;
e56660dd 960 u32 reloc_offset;
9df30794 961
05394f39 962 if (src == NULL || src->pages == NULL)
9df30794
CW		 963 return NULL;
964
9da3da66 965 count = src->base.size / PAGE_SIZE;
9df30794 966
9da3da66 967 dst = kmalloc(sizeof(*dst) + count * sizeof(u32 *), GFP_ATOMIC);
9df30794
CW		 968 if (dst == NULL)
969 return NULL;
970
05394f39 971 reloc_offset = src->gtt_offset;
9da3da66 972 for (i = 0; i < count; i++) {
788885ae 973 unsigned long flags;
e56660dd 974 void *d;
788885ae 975
e56660dd 976 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 977 if (d == NULL)
978 goto unwind;
e56660dd 979
788885ae 980 local_irq_save(flags);
5d4545ae 981 if (reloc_offset < dev_priv->gtt.mappable_end &&
74898d7e 982 src->has_global_gtt_mapping) {
172975aa
CW		 983 void __iomem *s;
984
985 /* Simply ignore tiling or any overlapping fence.
986 * It's part of the error state, and this hopefully
987 * captures what the GPU read.
988 */
989
5d4545ae 990 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
172975aa
CW		 991 reloc_offset);
992 memcpy_fromio(d, s, PAGE_SIZE);
993 io_mapping_unmap_atomic(s);
960e3564
CW		 994 } else if (src->stolen) {
995 unsigned long offset;
996
997 offset = dev_priv->mm.stolen_base;
998 offset += src->stolen->start;
999 offset += i << PAGE_SHIFT;
1000
1a240d4d 1001 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
172975aa 1002 } else {
9da3da66 1003 struct page *page;
172975aa
CW		 1004 void *s;
1005
9da3da66 1006 page = i915_gem_object_get_page(src, i);
172975aa 1007
9da3da66
CW		 1008 drm_clflush_pages(&page, 1);
1009
1010 s = kmap_atomic(page);
172975aa
CW		 1011 memcpy(d, s, PAGE_SIZE);
1012 kunmap_atomic(s);
1013
9da3da66 1014 drm_clflush_pages(&page, 1);
172975aa 1015 }
788885ae 1016 local_irq_restore(flags);
e56660dd 1017
9da3da66 1018 dst->pages[i] = d;
e56660dd
CW		 1019
1020 reloc_offset += PAGE_SIZE;
9df30794 1021 }
9da3da66 1022 dst->page_count = count;
05394f39 1023 dst->gtt_offset = src->gtt_offset;
9df30794
CW		 1024
1025 return dst;
1026
1027unwind:
9da3da66
CW		 1028 while (i--)
1029 kfree(dst->pages[i]);
9df30794
CW		 1030 kfree(dst);
1031 return NULL;
1032}
1033
1034static void
1035i915_error_object_free(struct drm_i915_error_object *obj)
1036{
1037 int page;
1038
1039 if (obj == NULL)
1040 return;
1041
1042 for (page = 0; page < obj->page_count; page++)
1043 kfree(obj->pages[page]);
1044
1045 kfree(obj);
1046}
1047
742cbee8
DV		 1048void
1049i915_error_state_free(struct kref *error_ref)
9df30794 1050{
742cbee8
DV		 1051 struct drm_i915_error_state *error = container_of(error_ref,
1052 typeof(*error), ref);
e2f973d5
CW		 1053 int i;
1054
52d39a21
CW		 1055 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
1056 i915_error_object_free(error->ring[i].batchbuffer);
1057 i915_error_object_free(error->ring[i].ringbuffer);
1058 kfree(error->ring[i].requests);
1059 }
e2f973d5 1060
9df30794 1061 kfree(error->active_bo);
6ef3d427 1062 kfree(error->overlay);
9df30794
CW		 1063 kfree(error);
1064}
1b50247a
CW		 1065static void capture_bo(struct drm_i915_error_buffer *err,
1066 struct drm_i915_gem_object *obj)
1067{
1068 err->size = obj->base.size;
1069 err->name = obj->base.name;
0201f1ec
CW		 1070 err->rseqno = obj->last_read_seqno;
1071 err->wseqno = obj->last_write_seqno;
1b50247a
CW		 1072 err->gtt_offset = obj->gtt_offset;
1073 err->read_domains = obj->base.read_domains;
1074 err->write_domain = obj->base.write_domain;
1075 err->fence_reg = obj->fence_reg;
1076 err->pinned = 0;
1077 if (obj->pin_count > 0)
1078 err->pinned = 1;
1079 if (obj->user_pin_count > 0)
1080 err->pinned = -1;
1081 err->tiling = obj->tiling_mode;
1082 err->dirty = obj->dirty;
1083 err->purgeable = obj->madv != I915_MADV_WILLNEED;
1084 err->ring = obj->ring ? obj->ring->id : -1;
1085 err->cache_level = obj->cache_level;
1086}
9df30794 1087
1b50247a
CW		 1088static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1089 int count, struct list_head *head)
c724e8a9
CW		 1090{
1091 struct drm_i915_gem_object *obj;
1092 int i = 0;
1093
1094 list_for_each_entry(obj, head, mm_list) {
1b50247a 1095 capture_bo(err++, obj);
c724e8a9
CW		 1096 if (++i == count)
1097 break;
1b50247a
CW		 1098 }
1099
1100 return i;
1101}
1102
1103static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1104 int count, struct list_head *head)
1105{
1106 struct drm_i915_gem_object *obj;
1107 int i = 0;
1108
1109 list_for_each_entry(obj, head, gtt_list) {
1110 if (obj->pin_count == 0)
1111 continue;
c724e8a9 1112
1b50247a
CW		 1113 capture_bo(err++, obj);
1114 if (++i == count)
1115 break;
c724e8a9
CW		 1116 }
1117
1118 return i;
1119}
1120
748ebc60
CW		 1121static void i915_gem_record_fences(struct drm_device *dev,
1122 struct drm_i915_error_state *error)
1123{
1124 struct drm_i915_private *dev_priv = dev->dev_private;
1125 int i;
1126
1127 /* Fences */
1128 switch (INTEL_INFO(dev)->gen) {
775d17b6 1129 case 7:
748ebc60
CW		 1130 case 6:
1131 for (i = 0; i < 16; i++)
1132 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1133 break;
1134 case 5:
1135 case 4:
1136 for (i = 0; i < 16; i++)
1137 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1138 break;
1139 case 3:
1140 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1141 for (i = 0; i < 8; i++)
1142 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1143 case 2:
1144 for (i = 0; i < 8; i++)
1145 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1146 break;
1147
7dbf9d6e
BW		 1148 default:
1149 BUG();
748ebc60
CW		 1150 }
1151}
1152
bcfb2e28
CW		 1153static struct drm_i915_error_object *
1154i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1155 struct intel_ring_buffer *ring)
1156{
1157 struct drm_i915_gem_object *obj;
1158 u32 seqno;
1159
1160 if (!ring->get_seqno)
1161 return NULL;
1162
b45305fc
DV		 1163 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
1164 u32 acthd = I915_READ(ACTHD);
1165
1166 if (WARN_ON(ring->id != RCS))
1167 return NULL;
1168
1169 obj = ring->private;
1170 if (acthd >= obj->gtt_offset &&
1171 acthd < obj->gtt_offset + obj->base.size)
1172 return i915_error_object_create(dev_priv, obj);
1173 }
1174
b2eadbc8 1175 seqno = ring->get_seqno(ring, false);
bcfb2e28
CW		 1176 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1177 if (obj->ring != ring)
1178 continue;
1179
0201f1ec 1180 if (i915_seqno_passed(seqno, obj->last_read_seqno))
bcfb2e28
CW		 1181 continue;
1182
1183 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1184 continue;
1185
1186 /* We need to copy these to an anonymous buffer as the simplest
1187 * method to avoid being overwritten by userspace.
1188 */
1189 return i915_error_object_create(dev_priv, obj);
1190 }
1191
1192 return NULL;
1193}
1194
d27b1e0e
DV		 1195static void i915_record_ring_state(struct drm_device *dev,
1196 struct drm_i915_error_state *error,
1197 struct intel_ring_buffer *ring)
1198{
1199 struct drm_i915_private *dev_priv = dev->dev_private;
1200
33f3f518 1201 if (INTEL_INFO(dev)->gen >= 6) {
12f55818 1202 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
33f3f518 1203 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
7e3b8737
DV		 1204 error->semaphore_mboxes[ring->id][0]
1205 = I915_READ(RING_SYNC_0(ring->mmio_base));
1206 error->semaphore_mboxes[ring->id][1]
1207 = I915_READ(RING_SYNC_1(ring->mmio_base));
df2b23d9
CW		 1208 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
1209 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
33f3f518 1210 }
c1cd90ed 1211
d27b1e0e 1212 if (INTEL_INFO(dev)->gen >= 4) {
9d2f41fa 1213 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
d27b1e0e
DV		 1214 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1215 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1216 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
c1cd90ed 1217 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
050ee91f 1218 if (ring->id == RCS)
d27b1e0e 1219 error->bbaddr = I915_READ64(BB_ADDR);
d27b1e0e 1220 } else {
9d2f41fa 1221 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
d27b1e0e
DV		 1222 error->ipeir[ring->id] = I915_READ(IPEIR);
1223 error->ipehr[ring->id] = I915_READ(IPEHR);
1224 error->instdone[ring->id] = I915_READ(INSTDONE);
d27b1e0e
DV		 1225 }
1226
9574b3fe 1227 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
c1cd90ed 1228 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
b2eadbc8 1229 error->seqno[ring->id] = ring->get_seqno(ring, false);
d27b1e0e 1230 error->acthd[ring->id] = intel_ring_get_active_head(ring);
c1cd90ed
DV		 1231 error->head[ring->id] = I915_READ_HEAD(ring);
1232 error->tail[ring->id] = I915_READ_TAIL(ring);
0f3b6849 1233 error->ctl[ring->id] = I915_READ_CTL(ring);
7e3b8737
DV		 1234
1235 error->cpu_ring_head[ring->id] = ring->head;
1236 error->cpu_ring_tail[ring->id] = ring->tail;
d27b1e0e
DV		 1237}
1238
52d39a21
CW		 1239static void i915_gem_record_rings(struct drm_device *dev,
1240 struct drm_i915_error_state *error)
1241{
1242 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 1243 struct intel_ring_buffer *ring;
52d39a21
CW		 1244 struct drm_i915_gem_request *request;
1245 int i, count;
1246
b4519513 1247 for_each_ring(ring, dev_priv, i) {
52d39a21
CW		 1248 i915_record_ring_state(dev, error, ring);
1249
1250 error->ring[i].batchbuffer =
1251 i915_error_first_batchbuffer(dev_priv, ring);
1252
1253 error->ring[i].ringbuffer =
1254 i915_error_object_create(dev_priv, ring->obj);
1255
1256 count = 0;
1257 list_for_each_entry(request, &ring->request_list, list)
1258 count++;
1259
1260 error->ring[i].num_requests = count;
1261 error->ring[i].requests =
1262 kmalloc(count*sizeof(struct drm_i915_error_request),
1263 GFP_ATOMIC);
1264 if (error->ring[i].requests == NULL) {
1265 error->ring[i].num_requests = 0;
1266 continue;
1267 }
1268
1269 count = 0;
1270 list_for_each_entry(request, &ring->request_list, list) {
1271 struct drm_i915_error_request *erq;
1272
1273 erq = &error->ring[i].requests[count++];
1274 erq->seqno = request->seqno;
1275 erq->jiffies = request->emitted_jiffies;
ee4f42b1 1276 erq->tail = request->tail;
52d39a21
CW		 1277 }
1278 }
1279}
1280
8a905236
JB		 1281/**
1282 * i915_capture_error_state - capture an error record for later analysis
1283 * @dev: drm device
1284 *
1285 * Should be called when an error is detected (either a hang or an error
1286 * interrupt) to capture error state from the time of the error. Fills
1287 * out a structure which becomes available in debugfs for user level tools
1288 * to pick up.
1289 */
63eeaf38
JB		 1290static void i915_capture_error_state(struct drm_device *dev)
1291{
1292 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1293 struct drm_i915_gem_object *obj;
63eeaf38
JB		 1294 struct drm_i915_error_state *error;
1295 unsigned long flags;
9db4a9c7 1296 int i, pipe;
63eeaf38 1297
99584db3
DV		 1298 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1299 error = dev_priv->gpu_error.first_error;
1300 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 1301 if (error)
1302 return;
63eeaf38 1303
9db4a9c7 1304 /* Account for pipe specific data like PIPE*STAT */
33f3f518 1305 error = kzalloc(sizeof(*error), GFP_ATOMIC);
63eeaf38 1306 if (!error) {
9df30794
CW		 1307 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1308 return;
63eeaf38
JB		 1309 }
1310
2f86f191
BW		 1311 DRM_INFO("capturing error event; look for more information in"
1312 "/sys/kernel/debug/dri/%d/i915_error_state\n",
b6f7833b 1313 dev->primary->index);
2fa772f3 1314
742cbee8 1315 kref_init(&error->ref);
63eeaf38
JB		 1316 error->eir = I915_READ(EIR);
1317 error->pgtbl_er = I915_READ(PGTBL_ER);
b9a3906b 1318 error->ccid = I915_READ(CCID);
be998e2e
BW		 1319
1320 if (HAS_PCH_SPLIT(dev))
1321 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1322 else if (IS_VALLEYVIEW(dev))
1323 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1324 else if (IS_GEN2(dev))
1325 error->ier = I915_READ16(IER);
1326 else
1327 error->ier = I915_READ(IER);
1328
0f3b6849
CW		 1329 if (INTEL_INFO(dev)->gen >= 6)
1330 error->derrmr = I915_READ(DERRMR);
1331
1332 if (IS_VALLEYVIEW(dev))
1333 error->forcewake = I915_READ(FORCEWAKE_VLV);
1334 else if (INTEL_INFO(dev)->gen >= 7)
1335 error->forcewake = I915_READ(FORCEWAKE_MT);
1336 else if (INTEL_INFO(dev)->gen == 6)
1337 error->forcewake = I915_READ(FORCEWAKE);
1338
9db4a9c7
JB		 1339 for_each_pipe(pipe)
1340 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
d27b1e0e 1341
33f3f518 1342 if (INTEL_INFO(dev)->gen >= 6) {
f406839f 1343 error->error = I915_READ(ERROR_GEN6);
33f3f518
DV		 1344 error->done_reg = I915_READ(DONE_REG);
1345 }
d27b1e0e 1346
71e172e8
BW		 1347 if (INTEL_INFO(dev)->gen == 7)
1348 error->err_int = I915_READ(GEN7_ERR_INT);
1349
050ee91f
BW		 1350 i915_get_extra_instdone(dev, error->extra_instdone);
1351
748ebc60 1352 i915_gem_record_fences(dev, error);
52d39a21 1353 i915_gem_record_rings(dev, error);
9df30794 1354
c724e8a9 1355 /* Record buffers on the active and pinned lists. */
9df30794 1356 error->active_bo = NULL;
c724e8a9 1357 error->pinned_bo = NULL;
9df30794 1358
bcfb2e28
CW		 1359 i = 0;
1360 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1361 i++;
1362 error->active_bo_count = i;
6c085a72 1363 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
1b50247a
CW		 1364 if (obj->pin_count)
1365 i++;
bcfb2e28 1366 error->pinned_bo_count = i - error->active_bo_count;
c724e8a9 1367
8e934dbf
CW		 1368 error->active_bo = NULL;
1369 error->pinned_bo = NULL;
bcfb2e28
CW		 1370 if (i) {
1371 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
9df30794 1372 GFP_ATOMIC);
c724e8a9
CW		 1373 if (error->active_bo)
1374 error->pinned_bo =
1375 error->active_bo + error->active_bo_count;
9df30794
CW		 1376 }
1377
c724e8a9
CW		 1378 if (error->active_bo)
1379 error->active_bo_count =
1b50247a
CW		 1380 capture_active_bo(error->active_bo,
1381 error->active_bo_count,
1382 &dev_priv->mm.active_list);
c724e8a9
CW		 1383
1384 if (error->pinned_bo)
1385 error->pinned_bo_count =
1b50247a
CW		 1386 capture_pinned_bo(error->pinned_bo,
1387 error->pinned_bo_count,
6c085a72 1388 &dev_priv->mm.bound_list);
c724e8a9 1389
9df30794
CW		 1390 do_gettimeofday(&error->time);
1391
6ef3d427 1392 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 1393 error->display = intel_display_capture_error_state(dev);
6ef3d427 1394
99584db3
DV		 1395 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1396 if (dev_priv->gpu_error.first_error == NULL) {
1397 dev_priv->gpu_error.first_error = error;
9df30794
CW		 1398 error = NULL;
1399 }
99584db3 1400 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 1401
1402 if (error)
742cbee8 1403 i915_error_state_free(&error->ref);
9df30794
CW		 1404}
1405
1406void i915_destroy_error_state(struct drm_device *dev)
1407{
1408 struct drm_i915_private *dev_priv = dev->dev_private;
1409 struct drm_i915_error_state *error;
6dc0e816 1410 unsigned long flags;
9df30794 1411
99584db3
DV		 1412 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1413 error = dev_priv->gpu_error.first_error;
1414 dev_priv->gpu_error.first_error = NULL;
1415 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 1416
1417 if (error)
742cbee8 1418 kref_put(&error->ref, i915_error_state_free);
63eeaf38 1419}
3bd3c932
CW		 1420#else
1421#define i915_capture_error_state(x)
1422#endif
63eeaf38 1423
35aed2e6 1424static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1425{
1426 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 1427 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 1428 u32 eir = I915_READ(EIR);
050ee91f 1429 int pipe, i;
8a905236 1430
35aed2e6
CW		 1431 if (!eir)
1432 return;
8a905236 1433
a70491cc 1434 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 1435
bd9854f9
BW		 1436 i915_get_extra_instdone(dev, instdone);
1437
8a905236
JB		 1438 if (IS_G4X(dev)) {
1439 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1440 u32 ipeir = I915_READ(IPEIR_I965);
1441
a70491cc
JP		 1442 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1443 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 1444 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1445 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 1446 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1447 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1448 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1449 POSTING_READ(IPEIR_I965);
8a905236
JB		 1450 }
1451 if (eir & GM45_ERROR_PAGE_TABLE) {
1452 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1453 pr_err("page table error\n");
1454 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1455 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1456 POSTING_READ(PGTBL_ER);
8a905236
JB		 1457 }
1458 }
1459
a6c45cf0 1460 if (!IS_GEN2(dev)) {
8a905236
JB		 1461 if (eir & I915_ERROR_PAGE_TABLE) {
1462 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1463 pr_err("page table error\n");
1464 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1465 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1466 POSTING_READ(PGTBL_ER);
8a905236
JB		 1467 }
1468 }
1469
1470 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 1471 pr_err("memory refresh error:\n");
9db4a9c7 1472 for_each_pipe(pipe)
a70491cc 1473 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 1474 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 1475 /* pipestat has already been acked */
1476 }
1477 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 1478 pr_err("instruction error\n");
1479 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 1480 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1481 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 1482 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 1483 u32 ipeir = I915_READ(IPEIR);
1484
a70491cc
JP		 1485 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1486 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 1487 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 1488 I915_WRITE(IPEIR, ipeir);
3143a2bf 1489 POSTING_READ(IPEIR);
8a905236
JB		 1490 } else {
1491 u32 ipeir = I915_READ(IPEIR_I965);
1492
a70491cc
JP		 1493 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1494 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 1495 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1496 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1497 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1498 POSTING_READ(IPEIR_I965);
8a905236
JB		 1499 }
1500 }
1501
1502 I915_WRITE(EIR, eir);
3143a2bf 1503 POSTING_READ(EIR);
8a905236
JB		 1504 eir = I915_READ(EIR);
1505 if (eir) {
1506 /*
1507 * some errors might have become stuck,
1508 * mask them.
1509 */
1510 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1511 I915_WRITE(EMR, I915_READ(EMR) | eir);
1512 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1513 }
35aed2e6
CW		 1514}
1515
1516/**
1517 * i915_handle_error - handle an error interrupt
1518 * @dev: drm device
1519 *
1520 * Do some basic checking of regsiter state at error interrupt time and
1521 * dump it to the syslog. Also call i915_capture_error_state() to make
1522 * sure we get a record and make it available in debugfs. Fire a uevent
1523 * so userspace knows something bad happened (should trigger collection
1524 * of a ring dump etc.).
1525 */
527f9e90 1526void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 1527{
1528 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513
CW		 1529 struct intel_ring_buffer *ring;
1530 int i;
35aed2e6
CW		 1531
1532 i915_capture_error_state(dev);
1533 i915_report_and_clear_eir(dev);
8a905236 1534
ba1234d1 1535 if (wedged) {
f69061be
DV		 1536 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
1537 &dev_priv->gpu_error.reset_counter);
ba1234d1 1538
11ed50ec 1539 /*
1f83fee0
DV		 1540 * Wakeup waiting processes so that the reset work item
1541 * doesn't deadlock trying to grab various locks.
11ed50ec 1542 */
b4519513
CW		 1543 for_each_ring(ring, dev_priv, i)
1544 wake_up_all(&ring->irq_queue);
11ed50ec
BG		 1545 }
1546
99584db3 1547 queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
8a905236
JB		 1548}
1549
21ad8330 1550static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
4e5359cd
SF		 1551{
1552 drm_i915_private_t *dev_priv = dev->dev_private;
1553 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1554 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 1555 struct drm_i915_gem_object *obj;
4e5359cd
SF		 1556 struct intel_unpin_work *work;
1557 unsigned long flags;
1558 bool stall_detected;
1559
1560 /* Ignore early vblank irqs */
1561 if (intel_crtc == NULL)
1562 return;
1563
1564 spin_lock_irqsave(&dev->event_lock, flags);
1565 work = intel_crtc->unpin_work;
1566
e7d841ca
CW		 1567 if (work == NULL ||
1568 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
1569 !work->enable_stall_check) {
4e5359cd
SF		 1570 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1571 spin_unlock_irqrestore(&dev->event_lock, flags);
1572 return;
1573 }
1574
1575 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 1576 obj = work->pending_flip_obj;
a6c45cf0 1577 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 1578 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545
AR		 1579 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1580 obj->gtt_offset;
4e5359cd 1581 } else {
9db4a9c7 1582 int dspaddr = DSPADDR(intel_crtc->plane);
05394f39 1583 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
01f2c773 1584 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 1585 crtc->x * crtc->fb->bits_per_pixel/8);
1586 }
1587
1588 spin_unlock_irqrestore(&dev->event_lock, flags);
1589
1590 if (stall_detected) {
1591 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1592 intel_prepare_page_flip(dev, intel_crtc->plane);
1593 }
1594}
1595
42f52ef8
KP		 1596/* Called from drm generic code, passed 'crtc' which
1597 * we use as a pipe index
1598 */
f71d4af4 1599static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1600{
1601 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1602 unsigned long irqflags;
71e0ffa5 1603
5eddb70b 1604 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 1605 return -EINVAL;
0a3e67a4 1606
1ec14ad3 1607 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 1608 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 1609 i915_enable_pipestat(dev_priv, pipe,
1610 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 1611 else
7c463586
KP		 1612 i915_enable_pipestat(dev_priv, pipe,
1613 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 1614
1615 /* maintain vblank delivery even in deep C-states */
1616 if (dev_priv->info->gen == 3)
6b26c86d 1617 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 1618 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 1619
0a3e67a4
JB		 1620 return 0;
1621}
1622
f71d4af4 1623static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1624{
1625 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1626 unsigned long irqflags;
1627
1628 if (!i915_pipe_enabled(dev, pipe))
1629 return -EINVAL;
1630
1631 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1632 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1633 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
f796cf8f
JB		 1634 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1635
1636 return 0;
1637}
1638
f71d4af4 1639static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1640{
1641 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1642 unsigned long irqflags;
1643
1644 if (!i915_pipe_enabled(dev, pipe))
1645 return -EINVAL;
1646
1647 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1648 ironlake_enable_display_irq(dev_priv,
1649 DE_PIPEA_VBLANK_IVB << (5 * pipe));
b1f14ad0
JB		 1650 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1651
1652 return 0;
1653}
1654
7e231dbe
JB		 1655static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1656{
1657 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1658 unsigned long irqflags;
31acc7f5 1659 u32 imr;
7e231dbe
JB		 1660
1661 if (!i915_pipe_enabled(dev, pipe))
1662 return -EINVAL;
1663
1664 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7e231dbe 1665 imr = I915_READ(VLV_IMR);
31acc7f5 1666 if (pipe == 0)
7e231dbe 1667 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1668 else
7e231dbe 1669 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1670 I915_WRITE(VLV_IMR, imr);
31acc7f5
JB		 1671 i915_enable_pipestat(dev_priv, pipe,
1672 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe
JB		 1673 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1674
1675 return 0;
1676}
1677
42f52ef8
KP		 1678/* Called from drm generic code, passed 'crtc' which
1679 * we use as a pipe index
1680 */
f71d4af4 1681static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1682{
1683 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1684 unsigned long irqflags;
0a3e67a4 1685
1ec14ad3 1686 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 1687 if (dev_priv->info->gen == 3)
6b26c86d 1688 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 1689
f796cf8f
JB		 1690 i915_disable_pipestat(dev_priv, pipe,
1691 PIPE_VBLANK_INTERRUPT_ENABLE |
1692 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1693 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1694}
1695
f71d4af4 1696static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1697{
1698 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1699 unsigned long irqflags;
1700
1701 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1702 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1703 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1ec14ad3 1704 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 1705}
1706
f71d4af4 1707static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1708{
1709 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1710 unsigned long irqflags;
1711
1712 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1713 ironlake_disable_display_irq(dev_priv,
1714 DE_PIPEA_VBLANK_IVB << (pipe * 5));
b1f14ad0
JB		 1715 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1716}
1717
7e231dbe
JB		 1718static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1719{
1720 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1721 unsigned long irqflags;
31acc7f5 1722 u32 imr;
7e231dbe
JB		 1723
1724 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5
JB		 1725 i915_disable_pipestat(dev_priv, pipe,
1726 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe 1727 imr = I915_READ(VLV_IMR);
31acc7f5 1728 if (pipe == 0)
7e231dbe 1729 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1730 else
7e231dbe 1731 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1732 I915_WRITE(VLV_IMR, imr);
7e231dbe
JB		 1733 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1734}
1735
893eead0
CW		 1736static u32
1737ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 1738{
893eead0
CW		 1739 return list_entry(ring->request_list.prev,
1740 struct drm_i915_gem_request, list)->seqno;
1741}
1742
1743static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1744{
1745 if (list_empty(&ring->request_list) ||
b2eadbc8
CW		 1746 i915_seqno_passed(ring->get_seqno(ring, false),
1747 ring_last_seqno(ring))) {
893eead0 1748 /* Issue a wake-up to catch stuck h/w. */
9574b3fe
BW		 1749 if (waitqueue_active(&ring->irq_queue)) {
1750 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1751 ring->name);
893eead0
CW		 1752 wake_up_all(&ring->irq_queue);
1753 *err = true;
1754 }
1755 return true;
1756 }
1757 return false;
f65d9421
BG		 1758}
1759
1ec14ad3
CW		 1760static bool kick_ring(struct intel_ring_buffer *ring)
1761{
1762 struct drm_device *dev = ring->dev;
1763 struct drm_i915_private *dev_priv = dev->dev_private;
1764 u32 tmp = I915_READ_CTL(ring);
1765 if (tmp & RING_WAIT) {
1766 DRM_ERROR("Kicking stuck wait on %s\n",
1767 ring->name);
1768 I915_WRITE_CTL(ring, tmp);
1769 return true;
1770 }
1ec14ad3
CW		 1771 return false;
1772}
1773
d1e61e7f
CW		 1774static bool i915_hangcheck_hung(struct drm_device *dev)
1775{
1776 drm_i915_private_t *dev_priv = dev->dev_private;
1777
99584db3 1778 if (dev_priv->gpu_error.hangcheck_count++ > 1) {
b4519513
CW		 1779 bool hung = true;
1780
d1e61e7f
CW		 1781 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1782 i915_handle_error(dev, true);
1783
1784 if (!IS_GEN2(dev)) {
b4519513
CW		 1785 struct intel_ring_buffer *ring;
1786 int i;
1787
d1e61e7f
CW		 1788 /* Is the chip hanging on a WAIT_FOR_EVENT?
1789 * If so we can simply poke the RB_WAIT bit
1790 * and break the hang. This should work on
1791 * all but the second generation chipsets.
1792 */
b4519513
CW		 1793 for_each_ring(ring, dev_priv, i)
1794 hung &= !kick_ring(ring);
d1e61e7f
CW		 1795 }
1796
b4519513 1797 return hung;
d1e61e7f
CW		 1798 }
1799
1800 return false;
1801}
1802
f65d9421
BG		 1803/**
1804 * This is called when the chip hasn't reported back with completed
1805 * batchbuffers in a long time. The first time this is called we simply record
1806 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1807 * again, we assume the chip is wedged and try to fix it.
1808 */
1809void i915_hangcheck_elapsed(unsigned long data)
1810{
1811 struct drm_device *dev = (struct drm_device *)data;
1812 drm_i915_private_t *dev_priv = dev->dev_private;
bd9854f9 1813 uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
b4519513
CW		 1814 struct intel_ring_buffer *ring;
1815 bool err = false, idle;
1816 int i;
893eead0 1817
3e0dc6b0
BW		 1818 if (!i915_enable_hangcheck)
1819 return;
1820
b4519513
CW		 1821 memset(acthd, 0, sizeof(acthd));
1822 idle = true;
1823 for_each_ring(ring, dev_priv, i) {
1824 idle &= i915_hangcheck_ring_idle(ring, &err);
1825 acthd[i] = intel_ring_get_active_head(ring);
1826 }
1827
893eead0 1828 /* If all work is done then ACTHD clearly hasn't advanced. */
b4519513 1829 if (idle) {
d1e61e7f
CW		 1830 if (err) {
1831 if (i915_hangcheck_hung(dev))
1832 return;
1833
893eead0 1834 goto repeat;
d1e61e7f
CW		 1835 }
1836
99584db3 1837 dev_priv->gpu_error.hangcheck_count = 0;
893eead0
CW		 1838 return;
1839 }
b9201c14 1840
bd9854f9 1841 i915_get_extra_instdone(dev, instdone);
99584db3
DV		 1842 if (memcmp(dev_priv->gpu_error.last_acthd, acthd,
1843 sizeof(acthd)) == 0 &&
1844 memcmp(dev_priv->gpu_error.prev_instdone, instdone,
1845 sizeof(instdone)) == 0) {
d1e61e7f 1846 if (i915_hangcheck_hung(dev))
cbb465e7 1847 return;
cbb465e7 1848 } else {
99584db3 1849 dev_priv->gpu_error.hangcheck_count = 0;
cbb465e7 1850
99584db3
DV		 1851 memcpy(dev_priv->gpu_error.last_acthd, acthd,
1852 sizeof(acthd));
1853 memcpy(dev_priv->gpu_error.prev_instdone, instdone,
1854 sizeof(instdone));
cbb465e7 1855 }
f65d9421 1856
893eead0 1857repeat:
f65d9421 1858 /* Reset timer case chip hangs without another request being added */
99584db3 1859 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
cecc21fe 1860 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
f65d9421
BG		 1861}
1862
1da177e4
LT		 1863/* drm_dma.h hooks
1864*/
f71d4af4 1865static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 1866{
1867 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1868
4697995b
JB		 1869 atomic_set(&dev_priv->irq_received, 0);
1870
036a4a7d 1871 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 1872
036a4a7d
ZW		 1873 /* XXX hotplug from PCH */
1874
1875 I915_WRITE(DEIMR, 0xffffffff);
1876 I915_WRITE(DEIER, 0x0);
3143a2bf 1877 POSTING_READ(DEIER);
036a4a7d
ZW		 1878
1879 /* and GT */
1880 I915_WRITE(GTIMR, 0xffffffff);
1881 I915_WRITE(GTIER, 0x0);
3143a2bf 1882 POSTING_READ(GTIER);
c650156a
ZW		 1883
1884 /* south display irq */
1885 I915_WRITE(SDEIMR, 0xffffffff);
1886 I915_WRITE(SDEIER, 0x0);
3143a2bf 1887 POSTING_READ(SDEIER);
036a4a7d
ZW		 1888}
1889
7e231dbe
JB		 1890static void valleyview_irq_preinstall(struct drm_device *dev)
1891{
1892 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1893 int pipe;
1894
1895 atomic_set(&dev_priv->irq_received, 0);
1896
7e231dbe
JB		 1897 /* VLV magic */
1898 I915_WRITE(VLV_IMR, 0);
1899 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1900 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1901 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1902
7e231dbe
JB		 1903 /* and GT */
1904 I915_WRITE(GTIIR, I915_READ(GTIIR));
1905 I915_WRITE(GTIIR, I915_READ(GTIIR));
1906 I915_WRITE(GTIMR, 0xffffffff);
1907 I915_WRITE(GTIER, 0x0);
1908 POSTING_READ(GTIER);
1909
1910 I915_WRITE(DPINVGTT, 0xff);
1911
1912 I915_WRITE(PORT_HOTPLUG_EN, 0);
1913 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1914 for_each_pipe(pipe)
1915 I915_WRITE(PIPESTAT(pipe), 0xffff);
1916 I915_WRITE(VLV_IIR, 0xffffffff);
1917 I915_WRITE(VLV_IMR, 0xffffffff);
1918 I915_WRITE(VLV_IER, 0x0);
1919 POSTING_READ(VLV_IER);
1920}
1921
7fe0b973
KP		 1922/*
1923 * Enable digital hotplug on the PCH, and configure the DP short pulse
1924 * duration to 2ms (which is the minimum in the Display Port spec)
1925 *
1926 * This register is the same on all known PCH chips.
1927 */
1928
d46da437 1929static void ibx_enable_hotplug(struct drm_device *dev)
7fe0b973
KP		 1930{
1931 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1932 u32 hotplug;
1933
1934 hotplug = I915_READ(PCH_PORT_HOTPLUG);
1935 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1936 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1937 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1938 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1939 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1940}
1941
d46da437
PZ		 1942static void ibx_irq_postinstall(struct drm_device *dev)
1943{
1944 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1945 u32 mask;
1946
1947 if (HAS_PCH_IBX(dev))
1948 mask = SDE_HOTPLUG_MASK |
1949 SDE_GMBUS |
1950 SDE_AUX_MASK;
1951 else
1952 mask = SDE_HOTPLUG_MASK_CPT |
1953 SDE_GMBUS_CPT |
1954 SDE_AUX_MASK_CPT;
1955
1956 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1957 I915_WRITE(SDEIMR, ~mask);
1958 I915_WRITE(SDEIER, mask);
1959 POSTING_READ(SDEIER);
1960
1961 ibx_enable_hotplug(dev);
1962}
1963
f71d4af4 1964static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d
ZW		 1965{
1966 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1967 /* enable kind of interrupts always enabled */
013d5aa2 1968 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
ce99c256
DV		 1969 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
1970 DE_AUX_CHANNEL_A;
1ec14ad3 1971 u32 render_irqs;
036a4a7d 1972
1ec14ad3 1973 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 1974
1975 /* should always can generate irq */
1976 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3
CW		 1977 I915_WRITE(DEIMR, dev_priv->irq_mask);
1978 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
3143a2bf 1979 POSTING_READ(DEIER);
036a4a7d 1980
1ec14ad3 1981 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 1982
1983 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 1984 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 1985
1ec14ad3
CW		 1986 if (IS_GEN6(dev))
1987 render_irqs =
1988 GT_USER_INTERRUPT |
e2a1e2f0
BW		 1989 GEN6_BSD_USER_INTERRUPT |
1990 GEN6_BLITTER_USER_INTERRUPT;
1ec14ad3
CW		 1991 else
1992 render_irqs =
88f23b8f 1993 GT_USER_INTERRUPT |
c6df541c 1994 GT_PIPE_NOTIFY |
1ec14ad3
CW		 1995 GT_BSD_USER_INTERRUPT;
1996 I915_WRITE(GTIER, render_irqs);
3143a2bf 1997 POSTING_READ(GTIER);
036a4a7d 1998
d46da437 1999 ibx_irq_postinstall(dev);
7fe0b973 2000
f97108d1
JB		 2001 if (IS_IRONLAKE_M(dev)) {
2002 /* Clear & enable PCU event interrupts */
2003 I915_WRITE(DEIIR, DE_PCU_EVENT);
2004 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
2005 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2006 }
2007
036a4a7d
ZW		 2008 return 0;
2009}
2010
f71d4af4 2011static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 2012{
2013 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2014 /* enable kind of interrupts always enabled */
b615b57a
CW		 2015 u32 display_mask =
2016 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
2017 DE_PLANEC_FLIP_DONE_IVB |
2018 DE_PLANEB_FLIP_DONE_IVB |
ce99c256
DV		 2019 DE_PLANEA_FLIP_DONE_IVB |
2020 DE_AUX_CHANNEL_A_IVB;
b1f14ad0 2021 u32 render_irqs;
b1f14ad0 2022
b1f14ad0
JB		 2023 dev_priv->irq_mask = ~display_mask;
2024
2025 /* should always can generate irq */
2026 I915_WRITE(DEIIR, I915_READ(DEIIR));
2027 I915_WRITE(DEIMR, dev_priv->irq_mask);
b615b57a
CW		 2028 I915_WRITE(DEIER,
2029 display_mask |
2030 DE_PIPEC_VBLANK_IVB |
2031 DE_PIPEB_VBLANK_IVB |
2032 DE_PIPEA_VBLANK_IVB);
b1f14ad0
JB		 2033 POSTING_READ(DEIER);
2034
15b9f80e 2035 dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 2036
2037 I915_WRITE(GTIIR, I915_READ(GTIIR));
2038 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2039
e2a1e2f0 2040 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
15b9f80e 2041 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 2042 I915_WRITE(GTIER, render_irqs);
2043 POSTING_READ(GTIER);
2044
d46da437 2045 ibx_irq_postinstall(dev);
7fe0b973 2046
b1f14ad0
JB		 2047 return 0;
2048}
2049
7e231dbe
JB		 2050static int valleyview_irq_postinstall(struct drm_device *dev)
2051{
2052 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7e231dbe 2053 u32 enable_mask;
31acc7f5 2054 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
3bcedbe5 2055 u32 render_irqs;
7e231dbe
JB		 2056 u16 msid;
2057
2058 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
31acc7f5
JB		 2059 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2060 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2061 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
7e231dbe
JB		 2062 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2063
31acc7f5
JB		 2064 /*
2065 *Leave vblank interrupts masked initially. enable/disable will
2066 * toggle them based on usage.
2067 */
2068 dev_priv->irq_mask = (~enable_mask) |
2069 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2070 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2071
7e231dbe
JB		 2072 dev_priv->pipestat[0] = 0;
2073 dev_priv->pipestat[1] = 0;
2074
7e231dbe
JB		 2075 /* Hack for broken MSIs on VLV */
2076 pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
2077 pci_read_config_word(dev->pdev, 0x98, &msid);
2078 msid &= 0xff; /* mask out delivery bits */
2079 msid |= (1<<14);
2080 pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
2081
20afbda2
DV		 2082 I915_WRITE(PORT_HOTPLUG_EN, 0);
2083 POSTING_READ(PORT_HOTPLUG_EN);
2084
7e231dbe
JB		 2085 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2086 I915_WRITE(VLV_IER, enable_mask);
2087 I915_WRITE(VLV_IIR, 0xffffffff);
2088 I915_WRITE(PIPESTAT(0), 0xffff);
2089 I915_WRITE(PIPESTAT(1), 0xffff);
2090 POSTING_READ(VLV_IER);
2091
31acc7f5 2092 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
515ac2bb 2093 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
31acc7f5
JB		 2094 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
2095
7e231dbe
JB		 2096 I915_WRITE(VLV_IIR, 0xffffffff);
2097 I915_WRITE(VLV_IIR, 0xffffffff);
2098
7e231dbe 2099 I915_WRITE(GTIIR, I915_READ(GTIIR));
31acc7f5 2100 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
3bcedbe5
JB		 2101
2102 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2103 GEN6_BLITTER_USER_INTERRUPT;
2104 I915_WRITE(GTIER, render_irqs);
7e231dbe
JB		 2105 POSTING_READ(GTIER);
2106
2107 /* ack & enable invalid PTE error interrupts */
2108#if 0 /* FIXME: add support to irq handler for checking these bits */
2109 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2110 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2111#endif
2112
2113 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
20afbda2
DV		 2114
2115 return 0;
2116}
2117
2118static void valleyview_hpd_irq_setup(struct drm_device *dev)
2119{
2120 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2121 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2122
7e231dbe 2123 /* Note HDMI and DP share bits */
26739f12
DV		 2124 if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS)
2125 hotplug_en |= PORTB_HOTPLUG_INT_EN;
2126 if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS)
2127 hotplug_en |= PORTC_HOTPLUG_INT_EN;
2128 if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS)
2129 hotplug_en |= PORTD_HOTPLUG_INT_EN;
ae33cdcf 2130 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
7e231dbe 2131 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
ae33cdcf 2132 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
7e231dbe
JB		 2133 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2134 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2135 hotplug_en |= CRT_HOTPLUG_INT_EN;
2136 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2137 }
7e231dbe
JB		 2138
2139 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
7e231dbe
JB		 2140}
2141
7e231dbe
JB		 2142static void valleyview_irq_uninstall(struct drm_device *dev)
2143{
2144 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2145 int pipe;
2146
2147 if (!dev_priv)
2148 return;
2149
7e231dbe
JB		 2150 for_each_pipe(pipe)
2151 I915_WRITE(PIPESTAT(pipe), 0xffff);
2152
2153 I915_WRITE(HWSTAM, 0xffffffff);
2154 I915_WRITE(PORT_HOTPLUG_EN, 0);
2155 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2156 for_each_pipe(pipe)
2157 I915_WRITE(PIPESTAT(pipe), 0xffff);
2158 I915_WRITE(VLV_IIR, 0xffffffff);
2159 I915_WRITE(VLV_IMR, 0xffffffff);
2160 I915_WRITE(VLV_IER, 0x0);
2161 POSTING_READ(VLV_IER);
2162}
2163
f71d4af4 2164static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 2165{
2166 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 2167
2168 if (!dev_priv)
2169 return;
2170
036a4a7d
ZW		 2171 I915_WRITE(HWSTAM, 0xffffffff);
2172
2173 I915_WRITE(DEIMR, 0xffffffff);
2174 I915_WRITE(DEIER, 0x0);
2175 I915_WRITE(DEIIR, I915_READ(DEIIR));
2176
2177 I915_WRITE(GTIMR, 0xffffffff);
2178 I915_WRITE(GTIER, 0x0);
2179 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f
KP		 2180
2181 I915_WRITE(SDEIMR, 0xffffffff);
2182 I915_WRITE(SDEIER, 0x0);
2183 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
036a4a7d
ZW		 2184}
2185
a266c7d5 2186static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 2187{
2188 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2189 int pipe;
91e3738e 2190
a266c7d5 2191 atomic_set(&dev_priv->irq_received, 0);
5ca58282 2192
9db4a9c7
JB		 2193 for_each_pipe(pipe)
2194 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 2195 I915_WRITE16(IMR, 0xffff);
2196 I915_WRITE16(IER, 0x0);
2197 POSTING_READ16(IER);
c2798b19
CW		 2198}
2199
2200static int i8xx_irq_postinstall(struct drm_device *dev)
2201{
2202 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2203
c2798b19
CW		 2204 dev_priv->pipestat[0] = 0;
2205 dev_priv->pipestat[1] = 0;
2206
2207 I915_WRITE16(EMR,
2208 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2209
2210 /* Unmask the interrupts that we always want on. */
2211 dev_priv->irq_mask =
2212 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2213 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2214 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2215 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2216 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2217 I915_WRITE16(IMR, dev_priv->irq_mask);
2218
2219 I915_WRITE16(IER,
2220 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2221 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2222 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2223 I915_USER_INTERRUPT);
2224 POSTING_READ16(IER);
2225
2226 return 0;
2227}
2228
90a72f87
VS		 2229/*
2230 * Returns true when a page flip has completed.
2231 */
2232static bool i8xx_handle_vblank(struct drm_device *dev,
2233 int pipe, u16 iir)
2234{
2235 drm_i915_private_t *dev_priv = dev->dev_private;
2236 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
2237
2238 if (!drm_handle_vblank(dev, pipe))
2239 return false;
2240
2241 if ((iir & flip_pending) == 0)
2242 return false;
2243
2244 intel_prepare_page_flip(dev, pipe);
2245
2246 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2247 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2248 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2249 * the flip is completed (no longer pending). Since this doesn't raise
2250 * an interrupt per se, we watch for the change at vblank.
2251 */
2252 if (I915_READ16(ISR) & flip_pending)
2253 return false;
2254
2255 intel_finish_page_flip(dev, pipe);
2256
2257 return true;
2258}
2259
ff1f525e 2260static irqreturn_t i8xx_irq_handler(int irq, void *arg)
c2798b19
CW		 2261{
2262 struct drm_device *dev = (struct drm_device *) arg;
2263 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 2264 u16 iir, new_iir;
2265 u32 pipe_stats[2];
2266 unsigned long irqflags;
2267 int irq_received;
2268 int pipe;
2269 u16 flip_mask =
2270 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2271 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2272
2273 atomic_inc(&dev_priv->irq_received);
2274
2275 iir = I915_READ16(IIR);
2276 if (iir == 0)
2277 return IRQ_NONE;
2278
2279 while (iir & ~flip_mask) {
2280 /* Can't rely on pipestat interrupt bit in iir as it might
2281 * have been cleared after the pipestat interrupt was received.
2282 * It doesn't set the bit in iir again, but it still produces
2283 * interrupts (for non-MSI).
2284 */
2285 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2286 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2287 i915_handle_error(dev, false);
2288
2289 for_each_pipe(pipe) {
2290 int reg = PIPESTAT(pipe);
2291 pipe_stats[pipe] = I915_READ(reg);
2292
2293 /*
2294 * Clear the PIPE*STAT regs before the IIR
2295 */
2296 if (pipe_stats[pipe] & 0x8000ffff) {
2297 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2298 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2299 pipe_name(pipe));
2300 I915_WRITE(reg, pipe_stats[pipe]);
2301 irq_received = 1;
2302 }
2303 }
2304 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2305
2306 I915_WRITE16(IIR, iir & ~flip_mask);
2307 new_iir = I915_READ16(IIR); /* Flush posted writes */
2308
d05c617e 2309 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 2310
2311 if (iir & I915_USER_INTERRUPT)
2312 notify_ring(dev, &dev_priv->ring[RCS]);
2313
2314 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2315 i8xx_handle_vblank(dev, 0, iir))
2316 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
c2798b19
CW		 2317
2318 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2319 i8xx_handle_vblank(dev, 1, iir))
2320 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
c2798b19
CW		 2321
2322 iir = new_iir;
2323 }
2324
2325 return IRQ_HANDLED;
2326}
2327
2328static void i8xx_irq_uninstall(struct drm_device * dev)
2329{
2330 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2331 int pipe;
2332
c2798b19
CW		 2333 for_each_pipe(pipe) {
2334 /* Clear enable bits; then clear status bits */
2335 I915_WRITE(PIPESTAT(pipe), 0);
2336 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2337 }
2338 I915_WRITE16(IMR, 0xffff);
2339 I915_WRITE16(IER, 0x0);
2340 I915_WRITE16(IIR, I915_READ16(IIR));
2341}
2342
a266c7d5
CW		 2343static void i915_irq_preinstall(struct drm_device * dev)
2344{
2345 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2346 int pipe;
2347
2348 atomic_set(&dev_priv->irq_received, 0);
2349
2350 if (I915_HAS_HOTPLUG(dev)) {
2351 I915_WRITE(PORT_HOTPLUG_EN, 0);
2352 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2353 }
2354
00d98ebd 2355 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 2356 for_each_pipe(pipe)
2357 I915_WRITE(PIPESTAT(pipe), 0);
2358 I915_WRITE(IMR, 0xffffffff);
2359 I915_WRITE(IER, 0x0);
2360 POSTING_READ(IER);
2361}
2362
2363static int i915_irq_postinstall(struct drm_device *dev)
2364{
2365 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 2366 u32 enable_mask;
a266c7d5 2367
a266c7d5
CW		 2368 dev_priv->pipestat[0] = 0;
2369 dev_priv->pipestat[1] = 0;
2370
38bde180
CW		 2371 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2372
2373 /* Unmask the interrupts that we always want on. */
2374 dev_priv->irq_mask =
2375 ~(I915_ASLE_INTERRUPT |
2376 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2377 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2378 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2379 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2380 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2381
2382 enable_mask =
2383 I915_ASLE_INTERRUPT |
2384 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2385 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2386 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2387 I915_USER_INTERRUPT;
2388
a266c7d5 2389 if (I915_HAS_HOTPLUG(dev)) {
20afbda2
DV		 2390 I915_WRITE(PORT_HOTPLUG_EN, 0);
2391 POSTING_READ(PORT_HOTPLUG_EN);
2392
a266c7d5
CW		 2393 /* Enable in IER... */
2394 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2395 /* and unmask in IMR */
2396 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2397 }
2398
a266c7d5
CW		 2399 I915_WRITE(IMR, dev_priv->irq_mask);
2400 I915_WRITE(IER, enable_mask);
2401 POSTING_READ(IER);
2402
20afbda2
DV		 2403 intel_opregion_enable_asle(dev);
2404
2405 return 0;
2406}
2407
2408static void i915_hpd_irq_setup(struct drm_device *dev)
2409{
2410 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2411 u32 hotplug_en;
2412
a266c7d5 2413 if (I915_HAS_HOTPLUG(dev)) {
20afbda2 2414 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
a266c7d5 2415
26739f12
DV		 2416 if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS)
2417 hotplug_en |= PORTB_HOTPLUG_INT_EN;
2418 if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS)
2419 hotplug_en |= PORTC_HOTPLUG_INT_EN;
2420 if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS)
2421 hotplug_en |= PORTD_HOTPLUG_INT_EN;
084b612e 2422 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
a266c7d5 2423 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
084b612e 2424 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
a266c7d5
CW		 2425 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2426 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2427 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5
CW		 2428 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2429 }
2430
2431 /* Ignore TV since it's buggy */
2432
2433 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2434 }
a266c7d5
CW		 2435}
2436
90a72f87
VS		 2437/*
2438 * Returns true when a page flip has completed.
2439 */
2440static bool i915_handle_vblank(struct drm_device *dev,
2441 int plane, int pipe, u32 iir)
2442{
2443 drm_i915_private_t *dev_priv = dev->dev_private;
2444 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
2445
2446 if (!drm_handle_vblank(dev, pipe))
2447 return false;
2448
2449 if ((iir & flip_pending) == 0)
2450 return false;
2451
2452 intel_prepare_page_flip(dev, plane);
2453
2454 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2455 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2456 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2457 * the flip is completed (no longer pending). Since this doesn't raise
2458 * an interrupt per se, we watch for the change at vblank.
2459 */
2460 if (I915_READ(ISR) & flip_pending)
2461 return false;
2462
2463 intel_finish_page_flip(dev, pipe);
2464
2465 return true;
2466}
2467
ff1f525e 2468static irqreturn_t i915_irq_handler(int irq, void *arg)
a266c7d5
CW		 2469{
2470 struct drm_device *dev = (struct drm_device *) arg;
2471 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 2472 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 2473 unsigned long irqflags;
38bde180
CW		 2474 u32 flip_mask =
2475 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2476 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
38bde180 2477 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 2478
2479 atomic_inc(&dev_priv->irq_received);
2480
2481 iir = I915_READ(IIR);
38bde180
CW		 2482 do {
2483 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 2484 bool blc_event = false;
a266c7d5
CW		 2485
2486 /* Can't rely on pipestat interrupt bit in iir as it might
2487 * have been cleared after the pipestat interrupt was received.
2488 * It doesn't set the bit in iir again, but it still produces
2489 * interrupts (for non-MSI).
2490 */
2491 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2492 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2493 i915_handle_error(dev, false);
2494
2495 for_each_pipe(pipe) {
2496 int reg = PIPESTAT(pipe);
2497 pipe_stats[pipe] = I915_READ(reg);
2498
38bde180 2499 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 2500 if (pipe_stats[pipe] & 0x8000ffff) {
2501 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2502 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2503 pipe_name(pipe));
2504 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 2505 irq_received = true;
a266c7d5
CW		 2506 }
2507 }
2508 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2509
2510 if (!irq_received)
2511 break;
2512
a266c7d5
CW		 2513 /* Consume port. Then clear IIR or we'll miss events */
2514 if ((I915_HAS_HOTPLUG(dev)) &&
2515 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2516 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2517
2518 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2519 hotplug_status);
2520 if (hotplug_status & dev_priv->hotplug_supported_mask)
2521 queue_work(dev_priv->wq,
2522 &dev_priv->hotplug_work);
2523
2524 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 2525 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 2526 }
2527
38bde180 2528 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2529 new_iir = I915_READ(IIR); /* Flush posted writes */
2530
a266c7d5
CW		 2531 if (iir & I915_USER_INTERRUPT)
2532 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 2533
a266c7d5 2534 for_each_pipe(pipe) {
38bde180
CW		 2535 int plane = pipe;
2536 if (IS_MOBILE(dev))
2537 plane = !plane;
90a72f87 2538
8291ee90 2539 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2540 i915_handle_vblank(dev, plane, pipe, iir))
2541 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
a266c7d5
CW		 2542
2543 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2544 blc_event = true;
2545 }
2546
a266c7d5
CW		 2547 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2548 intel_opregion_asle_intr(dev);
2549
2550 /* With MSI, interrupts are only generated when iir
2551 * transitions from zero to nonzero. If another bit got
2552 * set while we were handling the existing iir bits, then
2553 * we would never get another interrupt.
2554 *
2555 * This is fine on non-MSI as well, as if we hit this path
2556 * we avoid exiting the interrupt handler only to generate
2557 * another one.
2558 *
2559 * Note that for MSI this could cause a stray interrupt report
2560 * if an interrupt landed in the time between writing IIR and
2561 * the posting read. This should be rare enough to never
2562 * trigger the 99% of 100,000 interrupts test for disabling
2563 * stray interrupts.
2564 */
38bde180 2565 ret = IRQ_HANDLED;
a266c7d5 2566 iir = new_iir;
38bde180 2567 } while (iir & ~flip_mask);
a266c7d5 2568
d05c617e 2569 i915_update_dri1_breadcrumb(dev);
8291ee90 2570
a266c7d5
CW		 2571 return ret;
2572}
2573
2574static void i915_irq_uninstall(struct drm_device * dev)
2575{
2576 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2577 int pipe;
2578
a266c7d5
CW		 2579 if (I915_HAS_HOTPLUG(dev)) {
2580 I915_WRITE(PORT_HOTPLUG_EN, 0);
2581 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2582 }
2583
00d98ebd 2584 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 2585 for_each_pipe(pipe) {
2586 /* Clear enable bits; then clear status bits */
a266c7d5 2587 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 2588 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2589 }
a266c7d5
CW		 2590 I915_WRITE(IMR, 0xffffffff);
2591 I915_WRITE(IER, 0x0);
2592
a266c7d5
CW		 2593 I915_WRITE(IIR, I915_READ(IIR));
2594}
2595
2596static void i965_irq_preinstall(struct drm_device * dev)
2597{
2598 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2599 int pipe;
2600
2601 atomic_set(&dev_priv->irq_received, 0);
2602
adca4730
CW		 2603 I915_WRITE(PORT_HOTPLUG_EN, 0);
2604 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2605
2606 I915_WRITE(HWSTAM, 0xeffe);
2607 for_each_pipe(pipe)
2608 I915_WRITE(PIPESTAT(pipe), 0);
2609 I915_WRITE(IMR, 0xffffffff);
2610 I915_WRITE(IER, 0x0);
2611 POSTING_READ(IER);
2612}
2613
2614static int i965_irq_postinstall(struct drm_device *dev)
2615{
2616 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
bbba0a97 2617 u32 enable_mask;
a266c7d5
CW		 2618 u32 error_mask;
2619
a266c7d5 2620 /* Unmask the interrupts that we always want on. */
bbba0a97 2621 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 2622 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 2623 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2624 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2625 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2626 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2627 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2628
2629 enable_mask = ~dev_priv->irq_mask;
21ad8330
VS		 2630 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2631 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
bbba0a97
CW		 2632 enable_mask |= I915_USER_INTERRUPT;
2633
2634 if (IS_G4X(dev))
2635 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5
CW		 2636
2637 dev_priv->pipestat[0] = 0;
2638 dev_priv->pipestat[1] = 0;
515ac2bb 2639 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
a266c7d5 2640
a266c7d5
CW		 2641 /*
2642 * Enable some error detection, note the instruction error mask
2643 * bit is reserved, so we leave it masked.
2644 */
2645 if (IS_G4X(dev)) {
2646 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2647 GM45_ERROR_MEM_PRIV |
2648 GM45_ERROR_CP_PRIV |
2649 I915_ERROR_MEMORY_REFRESH);
2650 } else {
2651 error_mask = ~(I915_ERROR_PAGE_TABLE |
2652 I915_ERROR_MEMORY_REFRESH);
2653 }
2654 I915_WRITE(EMR, error_mask);
2655
2656 I915_WRITE(IMR, dev_priv->irq_mask);
2657 I915_WRITE(IER, enable_mask);
2658 POSTING_READ(IER);
2659
20afbda2
DV		 2660 I915_WRITE(PORT_HOTPLUG_EN, 0);
2661 POSTING_READ(PORT_HOTPLUG_EN);
2662
2663 intel_opregion_enable_asle(dev);
2664
2665 return 0;
2666}
2667
2668static void i965_hpd_irq_setup(struct drm_device *dev)
2669{
2670 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2671 u32 hotplug_en;
2672
adca4730
CW		 2673 /* Note HDMI and DP share hotplug bits */
2674 hotplug_en = 0;
26739f12
DV		 2675 if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS)
2676 hotplug_en |= PORTB_HOTPLUG_INT_EN;
2677 if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS)
2678 hotplug_en |= PORTC_HOTPLUG_INT_EN;
2679 if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS)
2680 hotplug_en |= PORTD_HOTPLUG_INT_EN;
084b612e
CW		 2681 if (IS_G4X(dev)) {
2682 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
2683 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2684 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
2685 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2686 } else {
2687 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
2688 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2689 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
2690 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2691 }
adca4730
CW		 2692 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2693 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5 2694
adca4730
CW		 2695 /* Programming the CRT detection parameters tends
2696 to generate a spurious hotplug event about three
2697 seconds later. So just do it once.
2698 */
2699 if (IS_G4X(dev))
2700 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2701 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2702 }
a266c7d5 2703
adca4730 2704 /* Ignore TV since it's buggy */
a266c7d5 2705
adca4730 2706 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
a266c7d5
CW		 2707}
2708
ff1f525e 2709static irqreturn_t i965_irq_handler(int irq, void *arg)
a266c7d5
CW		 2710{
2711 struct drm_device *dev = (struct drm_device *) arg;
2712 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 2713 u32 iir, new_iir;
2714 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 2715 unsigned long irqflags;
2716 int irq_received;
2717 int ret = IRQ_NONE, pipe;
21ad8330
VS		 2718 u32 flip_mask =
2719 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2720 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
a266c7d5
CW		 2721
2722 atomic_inc(&dev_priv->irq_received);
2723
2724 iir = I915_READ(IIR);
2725
a266c7d5 2726 for (;;) {
2c8ba29f
CW		 2727 bool blc_event = false;
2728
21ad8330 2729 irq_received = (iir & ~flip_mask) != 0;
a266c7d5
CW		 2730
2731 /* Can't rely on pipestat interrupt bit in iir as it might
2732 * have been cleared after the pipestat interrupt was received.
2733 * It doesn't set the bit in iir again, but it still produces
2734 * interrupts (for non-MSI).
2735 */
2736 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2737 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2738 i915_handle_error(dev, false);
2739
2740 for_each_pipe(pipe) {
2741 int reg = PIPESTAT(pipe);
2742 pipe_stats[pipe] = I915_READ(reg);
2743
2744 /*
2745 * Clear the PIPE*STAT regs before the IIR
2746 */
2747 if (pipe_stats[pipe] & 0x8000ffff) {
2748 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2749 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2750 pipe_name(pipe));
2751 I915_WRITE(reg, pipe_stats[pipe]);
2752 irq_received = 1;
2753 }
2754 }
2755 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2756
2757 if (!irq_received)
2758 break;
2759
2760 ret = IRQ_HANDLED;
2761
2762 /* Consume port. Then clear IIR or we'll miss events */
adca4730 2763 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
a266c7d5
CW		 2764 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2765
2766 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2767 hotplug_status);
2768 if (hotplug_status & dev_priv->hotplug_supported_mask)
2769 queue_work(dev_priv->wq,
2770 &dev_priv->hotplug_work);
2771
2772 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2773 I915_READ(PORT_HOTPLUG_STAT);
2774 }
2775
21ad8330 2776 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2777 new_iir = I915_READ(IIR); /* Flush posted writes */
2778
a266c7d5
CW		 2779 if (iir & I915_USER_INTERRUPT)
2780 notify_ring(dev, &dev_priv->ring[RCS]);
2781 if (iir & I915_BSD_USER_INTERRUPT)
2782 notify_ring(dev, &dev_priv->ring[VCS]);
2783
a266c7d5 2784 for_each_pipe(pipe) {
2c8ba29f 2785 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2786 i915_handle_vblank(dev, pipe, pipe, iir))
2787 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
a266c7d5
CW		 2788
2789 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2790 blc_event = true;
2791 }
2792
2793
2794 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2795 intel_opregion_asle_intr(dev);
2796
515ac2bb
DV		 2797 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
2798 gmbus_irq_handler(dev);
2799
a266c7d5
CW		 2800 /* With MSI, interrupts are only generated when iir
2801 * transitions from zero to nonzero. If another bit got
2802 * set while we were handling the existing iir bits, then
2803 * we would never get another interrupt.
2804 *
2805 * This is fine on non-MSI as well, as if we hit this path
2806 * we avoid exiting the interrupt handler only to generate
2807 * another one.
2808 *
2809 * Note that for MSI this could cause a stray interrupt report
2810 * if an interrupt landed in the time between writing IIR and
2811 * the posting read. This should be rare enough to never
2812 * trigger the 99% of 100,000 interrupts test for disabling
2813 * stray interrupts.
2814 */
2815 iir = new_iir;
2816 }
2817
d05c617e 2818 i915_update_dri1_breadcrumb(dev);
2c8ba29f 2819
a266c7d5
CW		 2820 return ret;
2821}
2822
2823static void i965_irq_uninstall(struct drm_device * dev)
2824{
2825 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2826 int pipe;
2827
2828 if (!dev_priv)
2829 return;
2830
adca4730
CW		 2831 I915_WRITE(PORT_HOTPLUG_EN, 0);
2832 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2833
2834 I915_WRITE(HWSTAM, 0xffffffff);
2835 for_each_pipe(pipe)
2836 I915_WRITE(PIPESTAT(pipe), 0);
2837 I915_WRITE(IMR, 0xffffffff);
2838 I915_WRITE(IER, 0x0);
2839
2840 for_each_pipe(pipe)
2841 I915_WRITE(PIPESTAT(pipe),
2842 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2843 I915_WRITE(IIR, I915_READ(IIR));
2844}
2845
f71d4af4
JB		 2846void intel_irq_init(struct drm_device *dev)
2847{
8b2e326d
CW		 2848 struct drm_i915_private *dev_priv = dev->dev_private;
2849
2850 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
99584db3 2851 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
c6a828d3 2852 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
a4da4fa4 2853 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
8b2e326d 2854
99584db3
DV		 2855 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
2856 i915_hangcheck_elapsed,
61bac78e
DV		 2857 (unsigned long) dev);
2858
97a19a24 2859 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
9ee32fea 2860
f71d4af4
JB		 2861 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2862 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7d4e146f 2863 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 2864 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2865 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2866 }
2867
c3613de9
KP		 2868 if (drm_core_check_feature(dev, DRIVER_MODESET))
2869 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2870 else
2871 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 2872 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2873
7e231dbe
JB		 2874 if (IS_VALLEYVIEW(dev)) {
2875 dev->driver->irq_handler = valleyview_irq_handler;
2876 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2877 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2878 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2879 dev->driver->enable_vblank = valleyview_enable_vblank;
2880 dev->driver->disable_vblank = valleyview_disable_vblank;
20afbda2 2881 dev_priv->display.hpd_irq_setup = valleyview_hpd_irq_setup;
4a06e201 2882 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
f71d4af4
JB		 2883 /* Share pre & uninstall handlers with ILK/SNB */
2884 dev->driver->irq_handler = ivybridge_irq_handler;
2885 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2886 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2887 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2888 dev->driver->enable_vblank = ivybridge_enable_vblank;
2889 dev->driver->disable_vblank = ivybridge_disable_vblank;
2890 } else if (HAS_PCH_SPLIT(dev)) {
2891 dev->driver->irq_handler = ironlake_irq_handler;
2892 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2893 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2894 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2895 dev->driver->enable_vblank = ironlake_enable_vblank;
2896 dev->driver->disable_vblank = ironlake_disable_vblank;
2897 } else {
c2798b19
CW		 2898 if (INTEL_INFO(dev)->gen == 2) {
2899 dev->driver->irq_preinstall = i8xx_irq_preinstall;
2900 dev->driver->irq_postinstall = i8xx_irq_postinstall;
2901 dev->driver->irq_handler = i8xx_irq_handler;
2902 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5
CW		 2903 } else if (INTEL_INFO(dev)->gen == 3) {
2904 dev->driver->irq_preinstall = i915_irq_preinstall;
2905 dev->driver->irq_postinstall = i915_irq_postinstall;
2906 dev->driver->irq_uninstall = i915_irq_uninstall;
2907 dev->driver->irq_handler = i915_irq_handler;
20afbda2 2908 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 2909 } else {
a266c7d5
CW		 2910 dev->driver->irq_preinstall = i965_irq_preinstall;
2911 dev->driver->irq_postinstall = i965_irq_postinstall;
2912 dev->driver->irq_uninstall = i965_irq_uninstall;
2913 dev->driver->irq_handler = i965_irq_handler;
20afbda2 2914 dev_priv->display.hpd_irq_setup = i965_hpd_irq_setup;
c2798b19 2915 }
f71d4af4
JB		 2916 dev->driver->enable_vblank = i915_enable_vblank;
2917 dev->driver->disable_vblank = i915_disable_vblank;
2918 }
2919}
20afbda2
DV		 2920
2921void intel_hpd_init(struct drm_device *dev)
2922{
2923 struct drm_i915_private *dev_priv = dev->dev_private;
2924
2925 if (dev_priv->display.hpd_irq_setup)
2926 dev_priv->display.hpd_irq_setup(dev);
2927}
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