]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/gpu/drm/i915/i915_irq.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: Avoid a double-read of PCH_IIR during interrupt handling
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
1da177e4
LT		 33#include "drmP.h"
34#include "drm.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
1c5d22f7 37#include "i915_trace.h"
79e53945 38#include "intel_drv.h"
1da177e4 39
036a4a7d 40/* For display hotplug interrupt */
995b6762 41static void
f2b115e6 42ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 43{
1ec14ad3
CW		 44 if ((dev_priv->irq_mask & mask) != 0) {
45 dev_priv->irq_mask &= ~mask;
46 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 47 POSTING_READ(DEIMR);
036a4a7d
ZW		 48 }
49}
50
51static inline void
f2b115e6 52ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 53{
1ec14ad3
CW		 54 if ((dev_priv->irq_mask & mask) != mask) {
55 dev_priv->irq_mask |= mask;
56 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 57 POSTING_READ(DEIMR);
036a4a7d
ZW		 58 }
59}
60
7c463586
KP		 61void
62i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
63{
64 if ((dev_priv->pipestat[pipe] & mask) != mask) {
9db4a9c7 65 u32 reg = PIPESTAT(pipe);
7c463586
KP		 66
67 dev_priv->pipestat[pipe] |= mask;
68 /* Enable the interrupt, clear any pending status */
69 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
3143a2bf 70 POSTING_READ(reg);
7c463586
KP		 71 }
72}
73
74void
75i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
76{
77 if ((dev_priv->pipestat[pipe] & mask) != 0) {
9db4a9c7 78 u32 reg = PIPESTAT(pipe);
7c463586
KP		 79
80 dev_priv->pipestat[pipe] &= ~mask;
81 I915_WRITE(reg, dev_priv->pipestat[pipe]);
3143a2bf 82 POSTING_READ(reg);
7c463586
KP		 83 }
84}
85
01c66889
ZY		 86/**
87 * intel_enable_asle - enable ASLE interrupt for OpRegion
88 */
1ec14ad3 89void intel_enable_asle(struct drm_device *dev)
01c66889 90{
1ec14ad3
CW		 91 drm_i915_private_t *dev_priv = dev->dev_private;
92 unsigned long irqflags;
93
7e231dbe
JB		 94 /* FIXME: opregion/asle for VLV */
95 if (IS_VALLEYVIEW(dev))
96 return;
97
1ec14ad3 98 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 99
c619eed4 100 if (HAS_PCH_SPLIT(dev))
f2b115e6 101 ironlake_enable_display_irq(dev_priv, DE_GSE);
edcb49ca 102 else {
01c66889 103 i915_enable_pipestat(dev_priv, 1,
d874bcff 104 PIPE_LEGACY_BLC_EVENT_ENABLE);
a6c45cf0 105 if (INTEL_INFO(dev)->gen >= 4)
edcb49ca 106 i915_enable_pipestat(dev_priv, 0,
d874bcff 107 PIPE_LEGACY_BLC_EVENT_ENABLE);
edcb49ca 108 }
1ec14ad3
CW		 109
110 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 111}
112
0a3e67a4
JB		 113/**
114 * i915_pipe_enabled - check if a pipe is enabled
115 * @dev: DRM device
116 * @pipe: pipe to check
117 *
118 * Reading certain registers when the pipe is disabled can hang the chip.
119 * Use this routine to make sure the PLL is running and the pipe is active
120 * before reading such registers if unsure.
121 */
122static int
123i915_pipe_enabled(struct drm_device *dev, int pipe)
124{
125 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
5eddb70b 126 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
0a3e67a4
JB		 127}
128
42f52ef8
KP		 129/* Called from drm generic code, passed a 'crtc', which
130 * we use as a pipe index
131 */
f71d4af4 132static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 133{
134 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
135 unsigned long high_frame;
136 unsigned long low_frame;
5eddb70b 137 u32 high1, high2, low;
0a3e67a4
JB		 138
139 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 140 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 141 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 142 return 0;
143 }
144
9db4a9c7
JB		 145 high_frame = PIPEFRAME(pipe);
146 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 147
0a3e67a4
JB		 148 /*
149 * High & low register fields aren't synchronized, so make sure
150 * we get a low value that's stable across two reads of the high
151 * register.
152 */
153 do {
5eddb70b
CW		 154 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
155 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
156 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 157 } while (high1 != high2);
158
5eddb70b
CW		 159 high1 >>= PIPE_FRAME_HIGH_SHIFT;
160 low >>= PIPE_FRAME_LOW_SHIFT;
161 return (high1 << 8) | low;
0a3e67a4
JB		 162}
163
f71d4af4 164static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 165{
166 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 167 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 168
169 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 170 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 171 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 172 return 0;
173 }
174
175 return I915_READ(reg);
176}
177
f71d4af4 178static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 179 int *vpos, int *hpos)
180{
181 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
182 u32 vbl = 0, position = 0;
183 int vbl_start, vbl_end, htotal, vtotal;
184 bool in_vbl = true;
185 int ret = 0;
186
187 if (!i915_pipe_enabled(dev, pipe)) {
188 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 189 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 190 return 0;
191 }
192
193 /* Get vtotal. */
194 vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
195
196 if (INTEL_INFO(dev)->gen >= 4) {
197 /* No obvious pixelcount register. Only query vertical
198 * scanout position from Display scan line register.
199 */
200 position = I915_READ(PIPEDSL(pipe));
201
202 /* Decode into vertical scanout position. Don't have
203 * horizontal scanout position.
204 */
205 *vpos = position & 0x1fff;
206 *hpos = 0;
207 } else {
208 /* Have access to pixelcount since start of frame.
209 * We can split this into vertical and horizontal
210 * scanout position.
211 */
212 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
213
214 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
215 *vpos = position / htotal;
216 *hpos = position - (*vpos * htotal);
217 }
218
219 /* Query vblank area. */
220 vbl = I915_READ(VBLANK(pipe));
221
222 /* Test position against vblank region. */
223 vbl_start = vbl & 0x1fff;
224 vbl_end = (vbl >> 16) & 0x1fff;
225
226 if ((*vpos < vbl_start) || (*vpos > vbl_end))
227 in_vbl = false;
228
229 /* Inside "upper part" of vblank area? Apply corrective offset: */
230 if (in_vbl && (*vpos >= vbl_start))
231 *vpos = *vpos - vtotal;
232
233 /* Readouts valid? */
234 if (vbl > 0)
235 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
236
237 /* In vblank? */
238 if (in_vbl)
239 ret |= DRM_SCANOUTPOS_INVBL;
240
241 return ret;
242}
243
f71d4af4 244static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 245 int *max_error,
246 struct timeval *vblank_time,
247 unsigned flags)
248{
4041b853
CW		 249 struct drm_i915_private *dev_priv = dev->dev_private;
250 struct drm_crtc *crtc;
0af7e4df 251
4041b853
CW		 252 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
253 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 254 return -EINVAL;
255 }
256
257 /* Get drm_crtc to timestamp: */
4041b853
CW		 258 crtc = intel_get_crtc_for_pipe(dev, pipe);
259 if (crtc == NULL) {
260 DRM_ERROR("Invalid crtc %d\n", pipe);
261 return -EINVAL;
262 }
263
264 if (!crtc->enabled) {
265 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
266 return -EBUSY;
267 }
0af7e4df
MK		 268
269 /* Helper routine in DRM core does all the work: */
4041b853
CW		 270 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
271 vblank_time, flags,
272 crtc);
0af7e4df
MK		 273}
274
5ca58282
JB		 275/*
276 * Handle hotplug events outside the interrupt handler proper.
277 */
278static void i915_hotplug_work_func(struct work_struct *work)
279{
280 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
281 hotplug_work);
282 struct drm_device *dev = dev_priv->dev;
c31c4ba3 283 struct drm_mode_config *mode_config = &dev->mode_config;
4ef69c7a
CW		 284 struct intel_encoder *encoder;
285
a65e34c7 286 mutex_lock(&mode_config->mutex);
e67189ab
JB		 287 DRM_DEBUG_KMS("running encoder hotplug functions\n");
288
4ef69c7a
CW		 289 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
290 if (encoder->hot_plug)
291 encoder->hot_plug(encoder);
292
40ee3381
KP		 293 mutex_unlock(&mode_config->mutex);
294
5ca58282 295 /* Just fire off a uevent and let userspace tell us what to do */
eb1f8e4f 296 drm_helper_hpd_irq_event(dev);
5ca58282
JB		 297}
298
f97108d1
JB		 299static void i915_handle_rps_change(struct drm_device *dev)
300{
301 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 302 u32 busy_up, busy_down, max_avg, min_avg;
f97108d1
JB		 303 u8 new_delay = dev_priv->cur_delay;
304
7648fa99 305 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 306 busy_up = I915_READ(RCPREVBSYTUPAVG);
307 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 308 max_avg = I915_READ(RCBMAXAVG);
309 min_avg = I915_READ(RCBMINAVG);
310
311 /* Handle RCS change request from hw */
b5b72e89 312 if (busy_up > max_avg) {
f97108d1
JB		 313 if (dev_priv->cur_delay != dev_priv->max_delay)
314 new_delay = dev_priv->cur_delay - 1;
315 if (new_delay < dev_priv->max_delay)
316 new_delay = dev_priv->max_delay;
b5b72e89 317 } else if (busy_down < min_avg) {
f97108d1
JB		 318 if (dev_priv->cur_delay != dev_priv->min_delay)
319 new_delay = dev_priv->cur_delay + 1;
320 if (new_delay > dev_priv->min_delay)
321 new_delay = dev_priv->min_delay;
322 }
323
7648fa99
JB		 324 if (ironlake_set_drps(dev, new_delay))
325 dev_priv->cur_delay = new_delay;
f97108d1
JB		 326
327 return;
328}
329
549f7365
CW		 330static void notify_ring(struct drm_device *dev,
331 struct intel_ring_buffer *ring)
332{
333 struct drm_i915_private *dev_priv = dev->dev_private;
9862e600 334
475553de
CW		 335 if (ring->obj == NULL)
336 return;
337
6d171cb4 338 trace_i915_gem_request_complete(ring, ring->get_seqno(ring));
9862e600 339
549f7365 340 wake_up_all(&ring->irq_queue);
3e0dc6b0
BW		 341 if (i915_enable_hangcheck) {
342 dev_priv->hangcheck_count = 0;
343 mod_timer(&dev_priv->hangcheck_timer,
344 jiffies +
345 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
346 }
549f7365
CW		 347}
348
4912d041 349static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 350{
4912d041
BW		 351 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
352 rps_work);
3b8d8d91 353 u8 new_delay = dev_priv->cur_delay;
4912d041
BW		 354 u32 pm_iir, pm_imr;
355
356 spin_lock_irq(&dev_priv->rps_lock);
357 pm_iir = dev_priv->pm_iir;
358 dev_priv->pm_iir = 0;
359 pm_imr = I915_READ(GEN6_PMIMR);
a9e2641d 360 I915_WRITE(GEN6_PMIMR, 0);
4912d041 361 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91 362
3b8d8d91
JB		 363 if (!pm_iir)
364 return;
365
4912d041 366 mutex_lock(&dev_priv->dev->struct_mutex);
3b8d8d91
JB		 367 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
368 if (dev_priv->cur_delay != dev_priv->max_delay)
369 new_delay = dev_priv->cur_delay + 1;
370 if (new_delay > dev_priv->max_delay)
371 new_delay = dev_priv->max_delay;
372 } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
4912d041 373 gen6_gt_force_wake_get(dev_priv);
3b8d8d91
JB		 374 if (dev_priv->cur_delay != dev_priv->min_delay)
375 new_delay = dev_priv->cur_delay - 1;
376 if (new_delay < dev_priv->min_delay) {
377 new_delay = dev_priv->min_delay;
378 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
379 I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
380 ((new_delay << 16) & 0x3f0000));
381 } else {
382 /* Make sure we continue to get down interrupts
383 * until we hit the minimum frequency */
384 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
385 I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
386 }
4912d041 387 gen6_gt_force_wake_put(dev_priv);
3b8d8d91
JB		 388 }
389
4912d041 390 gen6_set_rps(dev_priv->dev, new_delay);
3b8d8d91
JB		 391 dev_priv->cur_delay = new_delay;
392
4912d041
BW		 393 /*
394 * rps_lock not held here because clearing is non-destructive. There is
395 * an *extremely* unlikely race with gen6_rps_enable() that is prevented
396 * by holding struct_mutex for the duration of the write.
397 */
4912d041 398 mutex_unlock(&dev_priv->dev->struct_mutex);
3b8d8d91
JB		 399}
400
e7b4c6b1
DV		 401static void snb_gt_irq_handler(struct drm_device *dev,
402 struct drm_i915_private *dev_priv,
403 u32 gt_iir)
404{
405
406 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
407 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
408 notify_ring(dev, &dev_priv->ring[RCS]);
409 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
410 notify_ring(dev, &dev_priv->ring[VCS]);
411 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
412 notify_ring(dev, &dev_priv->ring[BCS]);
413
414 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
415 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
416 GT_RENDER_CS_ERROR_INTERRUPT)) {
417 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
418 i915_handle_error(dev, false);
419 }
420}
421
fc6826d1
CW		 422static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
423 u32 pm_iir)
424{
425 unsigned long flags;
426
427 /*
428 * IIR bits should never already be set because IMR should
429 * prevent an interrupt from being shown in IIR. The warning
430 * displays a case where we've unsafely cleared
431 * dev_priv->pm_iir. Although missing an interrupt of the same
432 * type is not a problem, it displays a problem in the logic.
433 *
434 * The mask bit in IMR is cleared by rps_work.
435 */
436
437 spin_lock_irqsave(&dev_priv->rps_lock, flags);
438 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
439 dev_priv->pm_iir |= pm_iir;
440 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
441 POSTING_READ(GEN6_PMIMR);
442 spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
443
444 queue_work(dev_priv->wq, &dev_priv->rps_work);
445}
446
7e231dbe
JB		 447static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
448{
449 struct drm_device *dev = (struct drm_device *) arg;
450 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
451 u32 iir, gt_iir, pm_iir;
452 irqreturn_t ret = IRQ_NONE;
453 unsigned long irqflags;
454 int pipe;
455 u32 pipe_stats[I915_MAX_PIPES];
456 u32 vblank_status;
457 int vblank = 0;
458 bool blc_event;
459
460 atomic_inc(&dev_priv->irq_received);
461
462 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS |
463 PIPE_VBLANK_INTERRUPT_STATUS;
464
465 while (true) {
466 iir = I915_READ(VLV_IIR);
467 gt_iir = I915_READ(GTIIR);
468 pm_iir = I915_READ(GEN6_PMIIR);
469
470 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
471 goto out;
472
473 ret = IRQ_HANDLED;
474
e7b4c6b1 475 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 476
477 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
478 for_each_pipe(pipe) {
479 int reg = PIPESTAT(pipe);
480 pipe_stats[pipe] = I915_READ(reg);
481
482 /*
483 * Clear the PIPE*STAT regs before the IIR
484 */
485 if (pipe_stats[pipe] & 0x8000ffff) {
486 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
487 DRM_DEBUG_DRIVER("pipe %c underrun\n",
488 pipe_name(pipe));
489 I915_WRITE(reg, pipe_stats[pipe]);
490 }
491 }
492 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
493
494 /* Consume port. Then clear IIR or we'll miss events */
495 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
496 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
497
498 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
499 hotplug_status);
500 if (hotplug_status & dev_priv->hotplug_supported_mask)
501 queue_work(dev_priv->wq,
502 &dev_priv->hotplug_work);
503
504 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
505 I915_READ(PORT_HOTPLUG_STAT);
506 }
507
508
509 if (iir & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) {
510 drm_handle_vblank(dev, 0);
511 vblank++;
e0f608d7 512 intel_finish_page_flip(dev, 0);
7e231dbe
JB		 513 }
514
515 if (iir & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) {
516 drm_handle_vblank(dev, 1);
517 vblank++;
e0f608d7 518 intel_finish_page_flip(dev, 0);
7e231dbe
JB		 519 }
520
521 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
522 blc_event = true;
523
fc6826d1
CW		 524 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
525 gen6_queue_rps_work(dev_priv, pm_iir);
7e231dbe
JB		 526
527 I915_WRITE(GTIIR, gt_iir);
528 I915_WRITE(GEN6_PMIIR, pm_iir);
529 I915_WRITE(VLV_IIR, iir);
530 }
531
532out:
533 return ret;
534}
535
9adab8b5 536static void pch_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 537{
538 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 539 int pipe;
776ad806 540
776ad806
JB		 541 if (pch_iir & SDE_AUDIO_POWER_MASK)
542 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
543 (pch_iir & SDE_AUDIO_POWER_MASK) >>
544 SDE_AUDIO_POWER_SHIFT);
545
546 if (pch_iir & SDE_GMBUS)
547 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
548
549 if (pch_iir & SDE_AUDIO_HDCP_MASK)
550 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
551
552 if (pch_iir & SDE_AUDIO_TRANS_MASK)
553 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
554
555 if (pch_iir & SDE_POISON)
556 DRM_ERROR("PCH poison interrupt\n");
557
9db4a9c7
JB		 558 if (pch_iir & SDE_FDI_MASK)
559 for_each_pipe(pipe)
560 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
561 pipe_name(pipe),
562 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 563
564 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
565 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
566
567 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
568 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
569
570 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
571 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
572 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
573 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
574}
575
f71d4af4 576static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
b1f14ad0
JB		 577{
578 struct drm_device *dev = (struct drm_device *) arg;
579 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
580 int ret = IRQ_NONE;
581 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
b1f14ad0
JB		 582
583 atomic_inc(&dev_priv->irq_received);
584
585 /* disable master interrupt before clearing iir */
586 de_ier = I915_READ(DEIER);
587 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
588 POSTING_READ(DEIER);
589
590 de_iir = I915_READ(DEIIR);
591 gt_iir = I915_READ(GTIIR);
592 pch_iir = I915_READ(SDEIIR);
593 pm_iir = I915_READ(GEN6_PMIIR);
594
595 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && pm_iir == 0)
596 goto done;
597
598 ret = IRQ_HANDLED;
599
e7b4c6b1 600 snb_gt_irq_handler(dev, dev_priv, gt_iir);
b1f14ad0
JB		 601
602 if (de_iir & DE_GSE_IVB)
603 intel_opregion_gse_intr(dev);
604
605 if (de_iir & DE_PLANEA_FLIP_DONE_IVB) {
606 intel_prepare_page_flip(dev, 0);
607 intel_finish_page_flip_plane(dev, 0);
608 }
609
610 if (de_iir & DE_PLANEB_FLIP_DONE_IVB) {
611 intel_prepare_page_flip(dev, 1);
612 intel_finish_page_flip_plane(dev, 1);
613 }
614
b615b57a
CW		 615 if (de_iir & DE_PLANEC_FLIP_DONE_IVB) {
616 intel_prepare_page_flip(dev, 2);
617 intel_finish_page_flip_plane(dev, 2);
618 }
619
b1f14ad0
JB		 620 if (de_iir & DE_PIPEA_VBLANK_IVB)
621 drm_handle_vblank(dev, 0);
622
f6b07f45 623 if (de_iir & DE_PIPEB_VBLANK_IVB)
b1f14ad0
JB		 624 drm_handle_vblank(dev, 1);
625
b615b57a
CW		 626 if (de_iir & DE_PIPEC_VBLANK_IVB)
627 drm_handle_vblank(dev, 2);
628
b1f14ad0
JB		 629 /* check event from PCH */
630 if (de_iir & DE_PCH_EVENT_IVB) {
631 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
632 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
9adab8b5 633 pch_irq_handler(dev, pch_iir);
b1f14ad0
JB		 634 }
635
fc6826d1
CW		 636 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
637 gen6_queue_rps_work(dev_priv, pm_iir);
b1f14ad0
JB		 638
639 /* should clear PCH hotplug event before clear CPU irq */
640 I915_WRITE(SDEIIR, pch_iir);
641 I915_WRITE(GTIIR, gt_iir);
642 I915_WRITE(DEIIR, de_iir);
643 I915_WRITE(GEN6_PMIIR, pm_iir);
644
645done:
646 I915_WRITE(DEIER, de_ier);
647 POSTING_READ(DEIER);
648
649 return ret;
650}
651
e7b4c6b1
DV		 652static void ilk_gt_irq_handler(struct drm_device *dev,
653 struct drm_i915_private *dev_priv,
654 u32 gt_iir)
655{
656 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
657 notify_ring(dev, &dev_priv->ring[RCS]);
658 if (gt_iir & GT_BSD_USER_INTERRUPT)
659 notify_ring(dev, &dev_priv->ring[VCS]);
660}
661
f71d4af4 662static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
036a4a7d 663{
4697995b 664 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 665 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
666 int ret = IRQ_NONE;
3b8d8d91 667 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
2d7b8366 668 u32 hotplug_mask;
881f47b6 669
4697995b
JB		 670 atomic_inc(&dev_priv->irq_received);
671
2d109a84
ZN		 672 /* disable master interrupt before clearing iir */
673 de_ier = I915_READ(DEIER);
674 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 675 POSTING_READ(DEIER);
2d109a84 676
036a4a7d
ZW		 677 de_iir = I915_READ(DEIIR);
678 gt_iir = I915_READ(GTIIR);
c650156a 679 pch_iir = I915_READ(SDEIIR);
3b8d8d91 680 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 681
3b8d8d91
JB		 682 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
683 (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 684 goto done;
036a4a7d 685
2d7b8366
YL		 686 if (HAS_PCH_CPT(dev))
687 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
688 else
689 hotplug_mask = SDE_HOTPLUG_MASK;
690
c7c85101 691 ret = IRQ_HANDLED;
036a4a7d 692
e7b4c6b1
DV		 693 if (IS_GEN5(dev))
694 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
695 else
696 snb_gt_irq_handler(dev, dev_priv, gt_iir);
01c66889 697
c7c85101 698 if (de_iir & DE_GSE)
3b617967 699 intel_opregion_gse_intr(dev);
c650156a 700
f072d2e7 701 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 702 intel_prepare_page_flip(dev, 0);
2bbda389 703 intel_finish_page_flip_plane(dev, 0);
f072d2e7 704 }
013d5aa2 705
f072d2e7 706 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 707 intel_prepare_page_flip(dev, 1);
2bbda389 708 intel_finish_page_flip_plane(dev, 1);
f072d2e7 709 }
013d5aa2 710
f072d2e7 711 if (de_iir & DE_PIPEA_VBLANK)
c062df61
LP		 712 drm_handle_vblank(dev, 0);
713
f072d2e7 714 if (de_iir & DE_PIPEB_VBLANK)
c062df61
LP		 715 drm_handle_vblank(dev, 1);
716
c7c85101 717 /* check event from PCH */
776ad806
JB		 718 if (de_iir & DE_PCH_EVENT) {
719 if (pch_iir & hotplug_mask)
720 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
9adab8b5 721 pch_irq_handler(dev, pch_iir);
776ad806 722 }
036a4a7d 723
f97108d1 724 if (de_iir & DE_PCU_EVENT) {
7648fa99 725 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
f97108d1
JB		 726 i915_handle_rps_change(dev);
727 }
728
fc6826d1
CW		 729 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
730 gen6_queue_rps_work(dev_priv, pm_iir);
3b8d8d91 731
c7c85101
ZN		 732 /* should clear PCH hotplug event before clear CPU irq */
733 I915_WRITE(SDEIIR, pch_iir);
734 I915_WRITE(GTIIR, gt_iir);
735 I915_WRITE(DEIIR, de_iir);
4912d041 736 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 737
738done:
2d109a84 739 I915_WRITE(DEIER, de_ier);
3143a2bf 740 POSTING_READ(DEIER);
2d109a84 741
036a4a7d
ZW		 742 return ret;
743}
744
8a905236
JB		 745/**
746 * i915_error_work_func - do process context error handling work
747 * @work: work struct
748 *
749 * Fire an error uevent so userspace can see that a hang or error
750 * was detected.
751 */
752static void i915_error_work_func(struct work_struct *work)
753{
754 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
755 error_work);
756 struct drm_device *dev = dev_priv->dev;
f316a42c
BG		 757 char *error_event[] = { "ERROR=1", NULL };
758 char *reset_event[] = { "RESET=1", NULL };
759 char *reset_done_event[] = { "ERROR=0", NULL };
8a905236 760
f316a42c
BG		 761 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
762
ba1234d1 763 if (atomic_read(&dev_priv->mm.wedged)) {
f803aa55
CW		 764 DRM_DEBUG_DRIVER("resetting chip\n");
765 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
d4b8bb2a 766 if (!i915_reset(dev)) {
f803aa55
CW		 767 atomic_set(&dev_priv->mm.wedged, 0);
768 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
f316a42c 769 }
30dbf0c0 770 complete_all(&dev_priv->error_completion);
f316a42c 771 }
8a905236
JB		 772}
773
3bd3c932 774#ifdef CONFIG_DEBUG_FS
9df30794 775static struct drm_i915_error_object *
bcfb2e28 776i915_error_object_create(struct drm_i915_private *dev_priv,
05394f39 777 struct drm_i915_gem_object *src)
9df30794
CW		 778{
779 struct drm_i915_error_object *dst;
9df30794 780 int page, page_count;
e56660dd 781 u32 reloc_offset;
9df30794 782
05394f39 783 if (src == NULL || src->pages == NULL)
9df30794
CW		 784 return NULL;
785
05394f39 786 page_count = src->base.size / PAGE_SIZE;
9df30794 787
0206e353 788 dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
9df30794
CW		 789 if (dst == NULL)
790 return NULL;
791
05394f39 792 reloc_offset = src->gtt_offset;
9df30794 793 for (page = 0; page < page_count; page++) {
788885ae 794 unsigned long flags;
e56660dd 795 void *d;
788885ae 796
e56660dd 797 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 798 if (d == NULL)
799 goto unwind;
e56660dd 800
788885ae 801 local_irq_save(flags);
74898d7e
DV		 802 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
803 src->has_global_gtt_mapping) {
172975aa
CW		 804 void __iomem *s;
805
806 /* Simply ignore tiling or any overlapping fence.
807 * It's part of the error state, and this hopefully
808 * captures what the GPU read.
809 */
810
811 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
812 reloc_offset);
813 memcpy_fromio(d, s, PAGE_SIZE);
814 io_mapping_unmap_atomic(s);
815 } else {
816 void *s;
817
818 drm_clflush_pages(&src->pages[page], 1);
819
820 s = kmap_atomic(src->pages[page]);
821 memcpy(d, s, PAGE_SIZE);
822 kunmap_atomic(s);
823
824 drm_clflush_pages(&src->pages[page], 1);
825 }
788885ae 826 local_irq_restore(flags);
e56660dd 827
9df30794 828 dst->pages[page] = d;
e56660dd
CW		 829
830 reloc_offset += PAGE_SIZE;
9df30794
CW		 831 }
832 dst->page_count = page_count;
05394f39 833 dst->gtt_offset = src->gtt_offset;
9df30794
CW		 834
835 return dst;
836
837unwind:
838 while (page--)
839 kfree(dst->pages[page]);
840 kfree(dst);
841 return NULL;
842}
843
844static void
845i915_error_object_free(struct drm_i915_error_object *obj)
846{
847 int page;
848
849 if (obj == NULL)
850 return;
851
852 for (page = 0; page < obj->page_count; page++)
853 kfree(obj->pages[page]);
854
855 kfree(obj);
856}
857
742cbee8
DV		 858void
859i915_error_state_free(struct kref *error_ref)
9df30794 860{
742cbee8
DV		 861 struct drm_i915_error_state *error = container_of(error_ref,
862 typeof(*error), ref);
e2f973d5
CW		 863 int i;
864
52d39a21
CW		 865 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
866 i915_error_object_free(error->ring[i].batchbuffer);
867 i915_error_object_free(error->ring[i].ringbuffer);
868 kfree(error->ring[i].requests);
869 }
e2f973d5 870
9df30794 871 kfree(error->active_bo);
6ef3d427 872 kfree(error->overlay);
9df30794
CW		 873 kfree(error);
874}
1b50247a
CW		 875static void capture_bo(struct drm_i915_error_buffer *err,
876 struct drm_i915_gem_object *obj)
877{
878 err->size = obj->base.size;
879 err->name = obj->base.name;
880 err->seqno = obj->last_rendering_seqno;
881 err->gtt_offset = obj->gtt_offset;
882 err->read_domains = obj->base.read_domains;
883 err->write_domain = obj->base.write_domain;
884 err->fence_reg = obj->fence_reg;
885 err->pinned = 0;
886 if (obj->pin_count > 0)
887 err->pinned = 1;
888 if (obj->user_pin_count > 0)
889 err->pinned = -1;
890 err->tiling = obj->tiling_mode;
891 err->dirty = obj->dirty;
892 err->purgeable = obj->madv != I915_MADV_WILLNEED;
893 err->ring = obj->ring ? obj->ring->id : -1;
894 err->cache_level = obj->cache_level;
895}
9df30794 896
1b50247a
CW		 897static u32 capture_active_bo(struct drm_i915_error_buffer *err,
898 int count, struct list_head *head)
c724e8a9
CW		 899{
900 struct drm_i915_gem_object *obj;
901 int i = 0;
902
903 list_for_each_entry(obj, head, mm_list) {
1b50247a 904 capture_bo(err++, obj);
c724e8a9
CW		 905 if (++i == count)
906 break;
1b50247a
CW		 907 }
908
909 return i;
910}
911
912static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
913 int count, struct list_head *head)
914{
915 struct drm_i915_gem_object *obj;
916 int i = 0;
917
918 list_for_each_entry(obj, head, gtt_list) {
919 if (obj->pin_count == 0)
920 continue;
c724e8a9 921
1b50247a
CW		 922 capture_bo(err++, obj);
923 if (++i == count)
924 break;
c724e8a9
CW		 925 }
926
927 return i;
928}
929
748ebc60
CW		 930static void i915_gem_record_fences(struct drm_device *dev,
931 struct drm_i915_error_state *error)
932{
933 struct drm_i915_private *dev_priv = dev->dev_private;
934 int i;
935
936 /* Fences */
937 switch (INTEL_INFO(dev)->gen) {
775d17b6 938 case 7:
748ebc60
CW		 939 case 6:
940 for (i = 0; i < 16; i++)
941 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
942 break;
943 case 5:
944 case 4:
945 for (i = 0; i < 16; i++)
946 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
947 break;
948 case 3:
949 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
950 for (i = 0; i < 8; i++)
951 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
952 case 2:
953 for (i = 0; i < 8; i++)
954 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
955 break;
956
957 }
958}
959
bcfb2e28
CW		 960static struct drm_i915_error_object *
961i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
962 struct intel_ring_buffer *ring)
963{
964 struct drm_i915_gem_object *obj;
965 u32 seqno;
966
967 if (!ring->get_seqno)
968 return NULL;
969
970 seqno = ring->get_seqno(ring);
971 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
972 if (obj->ring != ring)
973 continue;
974
c37d9a5d 975 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
bcfb2e28
CW		 976 continue;
977
978 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
979 continue;
980
981 /* We need to copy these to an anonymous buffer as the simplest
982 * method to avoid being overwritten by userspace.
983 */
984 return i915_error_object_create(dev_priv, obj);
985 }
986
987 return NULL;
988}
989
d27b1e0e
DV		 990static void i915_record_ring_state(struct drm_device *dev,
991 struct drm_i915_error_state *error,
992 struct intel_ring_buffer *ring)
993{
994 struct drm_i915_private *dev_priv = dev->dev_private;
995
33f3f518 996 if (INTEL_INFO(dev)->gen >= 6) {
33f3f518 997 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
7e3b8737
DV		 998 error->semaphore_mboxes[ring->id][0]
999 = I915_READ(RING_SYNC_0(ring->mmio_base));
1000 error->semaphore_mboxes[ring->id][1]
1001 = I915_READ(RING_SYNC_1(ring->mmio_base));
33f3f518 1002 }
c1cd90ed 1003
d27b1e0e 1004 if (INTEL_INFO(dev)->gen >= 4) {
9d2f41fa 1005 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
d27b1e0e
DV		 1006 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1007 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1008 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
c1cd90ed 1009 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
d27b1e0e 1010 if (ring->id == RCS) {
d27b1e0e
DV		 1011 error->instdone1 = I915_READ(INSTDONE1);
1012 error->bbaddr = I915_READ64(BB_ADDR);
1013 }
1014 } else {
9d2f41fa 1015 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
d27b1e0e
DV		 1016 error->ipeir[ring->id] = I915_READ(IPEIR);
1017 error->ipehr[ring->id] = I915_READ(IPEHR);
1018 error->instdone[ring->id] = I915_READ(INSTDONE);
d27b1e0e
DV		 1019 }
1020
9574b3fe 1021 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
c1cd90ed 1022 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
d27b1e0e
DV		 1023 error->seqno[ring->id] = ring->get_seqno(ring);
1024 error->acthd[ring->id] = intel_ring_get_active_head(ring);
c1cd90ed
DV		 1025 error->head[ring->id] = I915_READ_HEAD(ring);
1026 error->tail[ring->id] = I915_READ_TAIL(ring);
7e3b8737
DV		 1027
1028 error->cpu_ring_head[ring->id] = ring->head;
1029 error->cpu_ring_tail[ring->id] = ring->tail;
d27b1e0e
DV		 1030}
1031
52d39a21
CW		 1032static void i915_gem_record_rings(struct drm_device *dev,
1033 struct drm_i915_error_state *error)
1034{
1035 struct drm_i915_private *dev_priv = dev->dev_private;
1036 struct drm_i915_gem_request *request;
1037 int i, count;
1038
1039 for (i = 0; i < I915_NUM_RINGS; i++) {
1040 struct intel_ring_buffer *ring = &dev_priv->ring[i];
1041
1042 if (ring->obj == NULL)
1043 continue;
1044
1045 i915_record_ring_state(dev, error, ring);
1046
1047 error->ring[i].batchbuffer =
1048 i915_error_first_batchbuffer(dev_priv, ring);
1049
1050 error->ring[i].ringbuffer =
1051 i915_error_object_create(dev_priv, ring->obj);
1052
1053 count = 0;
1054 list_for_each_entry(request, &ring->request_list, list)
1055 count++;
1056
1057 error->ring[i].num_requests = count;
1058 error->ring[i].requests =
1059 kmalloc(count*sizeof(struct drm_i915_error_request),
1060 GFP_ATOMIC);
1061 if (error->ring[i].requests == NULL) {
1062 error->ring[i].num_requests = 0;
1063 continue;
1064 }
1065
1066 count = 0;
1067 list_for_each_entry(request, &ring->request_list, list) {
1068 struct drm_i915_error_request *erq;
1069
1070 erq = &error->ring[i].requests[count++];
1071 erq->seqno = request->seqno;
1072 erq->jiffies = request->emitted_jiffies;
ee4f42b1 1073 erq->tail = request->tail;
52d39a21
CW		 1074 }
1075 }
1076}
1077
8a905236
JB		 1078/**
1079 * i915_capture_error_state - capture an error record for later analysis
1080 * @dev: drm device
1081 *
1082 * Should be called when an error is detected (either a hang or an error
1083 * interrupt) to capture error state from the time of the error. Fills
1084 * out a structure which becomes available in debugfs for user level tools
1085 * to pick up.
1086 */
63eeaf38
JB		 1087static void i915_capture_error_state(struct drm_device *dev)
1088{
1089 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1090 struct drm_i915_gem_object *obj;
63eeaf38
JB		 1091 struct drm_i915_error_state *error;
1092 unsigned long flags;
9db4a9c7 1093 int i, pipe;
63eeaf38
JB		 1094
1095 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1096 error = dev_priv->first_error;
1097 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1098 if (error)
1099 return;
63eeaf38 1100
9db4a9c7 1101 /* Account for pipe specific data like PIPE*STAT */
33f3f518 1102 error = kzalloc(sizeof(*error), GFP_ATOMIC);
63eeaf38 1103 if (!error) {
9df30794
CW		 1104 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1105 return;
63eeaf38
JB		 1106 }
1107
b6f7833b
CW		 1108 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1109 dev->primary->index);
2fa772f3 1110
742cbee8 1111 kref_init(&error->ref);
63eeaf38
JB		 1112 error->eir = I915_READ(EIR);
1113 error->pgtbl_er = I915_READ(PGTBL_ER);
be998e2e
BW		 1114
1115 if (HAS_PCH_SPLIT(dev))
1116 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1117 else if (IS_VALLEYVIEW(dev))
1118 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1119 else if (IS_GEN2(dev))
1120 error->ier = I915_READ16(IER);
1121 else
1122 error->ier = I915_READ(IER);
1123
9db4a9c7
JB		 1124 for_each_pipe(pipe)
1125 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
d27b1e0e 1126
33f3f518 1127 if (INTEL_INFO(dev)->gen >= 6) {
f406839f 1128 error->error = I915_READ(ERROR_GEN6);
33f3f518
DV		 1129 error->done_reg = I915_READ(DONE_REG);
1130 }
d27b1e0e 1131
748ebc60 1132 i915_gem_record_fences(dev, error);
52d39a21 1133 i915_gem_record_rings(dev, error);
9df30794 1134
c724e8a9 1135 /* Record buffers on the active and pinned lists. */
9df30794 1136 error->active_bo = NULL;
c724e8a9 1137 error->pinned_bo = NULL;
9df30794 1138
bcfb2e28
CW		 1139 i = 0;
1140 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1141 i++;
1142 error->active_bo_count = i;
1b50247a
CW		 1143 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
1144 if (obj->pin_count)
1145 i++;
bcfb2e28 1146 error->pinned_bo_count = i - error->active_bo_count;
c724e8a9 1147
8e934dbf
CW		 1148 error->active_bo = NULL;
1149 error->pinned_bo = NULL;
bcfb2e28
CW		 1150 if (i) {
1151 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
9df30794 1152 GFP_ATOMIC);
c724e8a9
CW		 1153 if (error->active_bo)
1154 error->pinned_bo =
1155 error->active_bo + error->active_bo_count;
9df30794
CW		 1156 }
1157
c724e8a9
CW		 1158 if (error->active_bo)
1159 error->active_bo_count =
1b50247a
CW		 1160 capture_active_bo(error->active_bo,
1161 error->active_bo_count,
1162 &dev_priv->mm.active_list);
c724e8a9
CW		 1163
1164 if (error->pinned_bo)
1165 error->pinned_bo_count =
1b50247a
CW		 1166 capture_pinned_bo(error->pinned_bo,
1167 error->pinned_bo_count,
1168 &dev_priv->mm.gtt_list);
c724e8a9 1169
9df30794
CW		 1170 do_gettimeofday(&error->time);
1171
6ef3d427 1172 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 1173 error->display = intel_display_capture_error_state(dev);
6ef3d427 1174
9df30794
CW		 1175 spin_lock_irqsave(&dev_priv->error_lock, flags);
1176 if (dev_priv->first_error == NULL) {
1177 dev_priv->first_error = error;
1178 error = NULL;
1179 }
63eeaf38 1180 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1181
1182 if (error)
742cbee8 1183 i915_error_state_free(&error->ref);
9df30794
CW		 1184}
1185
1186void i915_destroy_error_state(struct drm_device *dev)
1187{
1188 struct drm_i915_private *dev_priv = dev->dev_private;
1189 struct drm_i915_error_state *error;
6dc0e816 1190 unsigned long flags;
9df30794 1191
6dc0e816 1192 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1193 error = dev_priv->first_error;
1194 dev_priv->first_error = NULL;
6dc0e816 1195 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1196
1197 if (error)
742cbee8 1198 kref_put(&error->ref, i915_error_state_free);
63eeaf38 1199}
3bd3c932
CW		 1200#else
1201#define i915_capture_error_state(x)
1202#endif
63eeaf38 1203
35aed2e6 1204static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1205{
1206 struct drm_i915_private *dev_priv = dev->dev_private;
1207 u32 eir = I915_READ(EIR);
9db4a9c7 1208 int pipe;
8a905236 1209
35aed2e6
CW		 1210 if (!eir)
1211 return;
8a905236 1212
a70491cc 1213 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236
JB		 1214
1215 if (IS_G4X(dev)) {
1216 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1217 u32 ipeir = I915_READ(IPEIR_I965);
1218
a70491cc
JP		 1219 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1220 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1221 pr_err(" INSTDONE: 0x%08x\n",
8a905236 1222 I915_READ(INSTDONE_I965));
a70491cc
JP		 1223 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1224 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1225 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1226 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1227 POSTING_READ(IPEIR_I965);
8a905236
JB		 1228 }
1229 if (eir & GM45_ERROR_PAGE_TABLE) {
1230 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1231 pr_err("page table error\n");
1232 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1233 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1234 POSTING_READ(PGTBL_ER);
8a905236
JB		 1235 }
1236 }
1237
a6c45cf0 1238 if (!IS_GEN2(dev)) {
8a905236
JB		 1239 if (eir & I915_ERROR_PAGE_TABLE) {
1240 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1241 pr_err("page table error\n");
1242 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1243 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1244 POSTING_READ(PGTBL_ER);
8a905236
JB		 1245 }
1246 }
1247
1248 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 1249 pr_err("memory refresh error:\n");
9db4a9c7 1250 for_each_pipe(pipe)
a70491cc 1251 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 1252 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 1253 /* pipestat has already been acked */
1254 }
1255 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 1256 pr_err("instruction error\n");
1257 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
a6c45cf0 1258 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 1259 u32 ipeir = I915_READ(IPEIR);
1260
a70491cc
JP		 1261 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1262 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
1263 pr_err(" INSTDONE: 0x%08x\n", I915_READ(INSTDONE));
1264 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 1265 I915_WRITE(IPEIR, ipeir);
3143a2bf 1266 POSTING_READ(IPEIR);
8a905236
JB		 1267 } else {
1268 u32 ipeir = I915_READ(IPEIR_I965);
1269
a70491cc
JP		 1270 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1271 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1272 pr_err(" INSTDONE: 0x%08x\n",
8a905236 1273 I915_READ(INSTDONE_I965));
a70491cc
JP		 1274 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1275 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1276 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1277 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1278 POSTING_READ(IPEIR_I965);
8a905236
JB		 1279 }
1280 }
1281
1282 I915_WRITE(EIR, eir);
3143a2bf 1283 POSTING_READ(EIR);
8a905236
JB		 1284 eir = I915_READ(EIR);
1285 if (eir) {
1286 /*
1287 * some errors might have become stuck,
1288 * mask them.
1289 */
1290 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1291 I915_WRITE(EMR, I915_READ(EMR) | eir);
1292 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1293 }
35aed2e6
CW		 1294}
1295
1296/**
1297 * i915_handle_error - handle an error interrupt
1298 * @dev: drm device
1299 *
1300 * Do some basic checking of regsiter state at error interrupt time and
1301 * dump it to the syslog. Also call i915_capture_error_state() to make
1302 * sure we get a record and make it available in debugfs. Fire a uevent
1303 * so userspace knows something bad happened (should trigger collection
1304 * of a ring dump etc.).
1305 */
527f9e90 1306void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 1307{
1308 struct drm_i915_private *dev_priv = dev->dev_private;
1309
1310 i915_capture_error_state(dev);
1311 i915_report_and_clear_eir(dev);
8a905236 1312
ba1234d1 1313 if (wedged) {
30dbf0c0 1314 INIT_COMPLETION(dev_priv->error_completion);
ba1234d1
BG		 1315 atomic_set(&dev_priv->mm.wedged, 1);
1316
11ed50ec
BG		 1317 /*
1318 * Wakeup waiting processes so they don't hang
1319 */
1ec14ad3 1320 wake_up_all(&dev_priv->ring[RCS].irq_queue);
f787a5f5 1321 if (HAS_BSD(dev))
1ec14ad3 1322 wake_up_all(&dev_priv->ring[VCS].irq_queue);
549f7365 1323 if (HAS_BLT(dev))
1ec14ad3 1324 wake_up_all(&dev_priv->ring[BCS].irq_queue);
11ed50ec
BG		 1325 }
1326
9c9fe1f8 1327 queue_work(dev_priv->wq, &dev_priv->error_work);
8a905236
JB		 1328}
1329
4e5359cd
SF		 1330static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1331{
1332 drm_i915_private_t *dev_priv = dev->dev_private;
1333 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 1335 struct drm_i915_gem_object *obj;
4e5359cd
SF		 1336 struct intel_unpin_work *work;
1337 unsigned long flags;
1338 bool stall_detected;
1339
1340 /* Ignore early vblank irqs */
1341 if (intel_crtc == NULL)
1342 return;
1343
1344 spin_lock_irqsave(&dev->event_lock, flags);
1345 work = intel_crtc->unpin_work;
1346
1347 if (work == NULL || work->pending || !work->enable_stall_check) {
1348 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1349 spin_unlock_irqrestore(&dev->event_lock, flags);
1350 return;
1351 }
1352
1353 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 1354 obj = work->pending_flip_obj;
a6c45cf0 1355 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 1356 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545
AR		 1357 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1358 obj->gtt_offset;
4e5359cd 1359 } else {
9db4a9c7 1360 int dspaddr = DSPADDR(intel_crtc->plane);
05394f39 1361 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
01f2c773 1362 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 1363 crtc->x * crtc->fb->bits_per_pixel/8);
1364 }
1365
1366 spin_unlock_irqrestore(&dev->event_lock, flags);
1367
1368 if (stall_detected) {
1369 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1370 intel_prepare_page_flip(dev, intel_crtc->plane);
1371 }
1372}
1373
42f52ef8
KP		 1374/* Called from drm generic code, passed 'crtc' which
1375 * we use as a pipe index
1376 */
f71d4af4 1377static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1378{
1379 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1380 unsigned long irqflags;
71e0ffa5 1381
5eddb70b 1382 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 1383 return -EINVAL;
0a3e67a4 1384
1ec14ad3 1385 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 1386 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 1387 i915_enable_pipestat(dev_priv, pipe,
1388 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 1389 else
7c463586
KP		 1390 i915_enable_pipestat(dev_priv, pipe,
1391 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 1392
1393 /* maintain vblank delivery even in deep C-states */
1394 if (dev_priv->info->gen == 3)
6b26c86d 1395 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 1396 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 1397
0a3e67a4
JB		 1398 return 0;
1399}
1400
f71d4af4 1401static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1402{
1403 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1404 unsigned long irqflags;
1405
1406 if (!i915_pipe_enabled(dev, pipe))
1407 return -EINVAL;
1408
1409 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1410 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1411 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
f796cf8f
JB		 1412 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1413
1414 return 0;
1415}
1416
f71d4af4 1417static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1418{
1419 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1420 unsigned long irqflags;
1421
1422 if (!i915_pipe_enabled(dev, pipe))
1423 return -EINVAL;
1424
1425 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1426 ironlake_enable_display_irq(dev_priv,
1427 DE_PIPEA_VBLANK_IVB << (5 * pipe));
b1f14ad0
JB		 1428 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1429
1430 return 0;
1431}
1432
7e231dbe
JB		 1433static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1434{
1435 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1436 unsigned long irqflags;
1437 u32 dpfl, imr;
1438
1439 if (!i915_pipe_enabled(dev, pipe))
1440 return -EINVAL;
1441
1442 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1443 dpfl = I915_READ(VLV_DPFLIPSTAT);
1444 imr = I915_READ(VLV_IMR);
1445 if (pipe == 0) {
1446 dpfl |= PIPEA_VBLANK_INT_EN;
1447 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1448 } else {
1449 dpfl |= PIPEA_VBLANK_INT_EN;
1450 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1451 }
1452 I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1453 I915_WRITE(VLV_IMR, imr);
1454 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1455
1456 return 0;
1457}
1458
42f52ef8
KP		 1459/* Called from drm generic code, passed 'crtc' which
1460 * we use as a pipe index
1461 */
f71d4af4 1462static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1463{
1464 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1465 unsigned long irqflags;
0a3e67a4 1466
1ec14ad3 1467 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 1468 if (dev_priv->info->gen == 3)
6b26c86d 1469 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 1470
f796cf8f
JB		 1471 i915_disable_pipestat(dev_priv, pipe,
1472 PIPE_VBLANK_INTERRUPT_ENABLE |
1473 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1474 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1475}
1476
f71d4af4 1477static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1478{
1479 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1480 unsigned long irqflags;
1481
1482 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1483 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1484 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1ec14ad3 1485 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 1486}
1487
f71d4af4 1488static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1489{
1490 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1491 unsigned long irqflags;
1492
1493 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1494 ironlake_disable_display_irq(dev_priv,
1495 DE_PIPEA_VBLANK_IVB << (pipe * 5));
b1f14ad0
JB		 1496 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1497}
1498
7e231dbe
JB		 1499static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1500{
1501 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1502 unsigned long irqflags;
1503 u32 dpfl, imr;
1504
1505 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1506 dpfl = I915_READ(VLV_DPFLIPSTAT);
1507 imr = I915_READ(VLV_IMR);
1508 if (pipe == 0) {
1509 dpfl &= ~PIPEA_VBLANK_INT_EN;
1510 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1511 } else {
1512 dpfl &= ~PIPEB_VBLANK_INT_EN;
1513 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1514 }
1515 I915_WRITE(VLV_IMR, imr);
1516 I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1517 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1518}
1519
893eead0
CW		 1520static u32
1521ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 1522{
893eead0
CW		 1523 return list_entry(ring->request_list.prev,
1524 struct drm_i915_gem_request, list)->seqno;
1525}
1526
1527static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1528{
9574b3fe
BW		 1529 /* We don't check whether the ring even exists before calling this
1530 * function. Hence check whether it's initialized. */
1531 if (ring->obj == NULL)
1532 return true;
1533
893eead0
CW		 1534 if (list_empty(&ring->request_list) ||
1535 i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1536 /* Issue a wake-up to catch stuck h/w. */
9574b3fe
BW		 1537 if (waitqueue_active(&ring->irq_queue)) {
1538 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1539 ring->name);
893eead0
CW		 1540 wake_up_all(&ring->irq_queue);
1541 *err = true;
1542 }
1543 return true;
1544 }
1545 return false;
f65d9421
BG		 1546}
1547
1ec14ad3
CW		 1548static bool kick_ring(struct intel_ring_buffer *ring)
1549{
1550 struct drm_device *dev = ring->dev;
1551 struct drm_i915_private *dev_priv = dev->dev_private;
1552 u32 tmp = I915_READ_CTL(ring);
1553 if (tmp & RING_WAIT) {
1554 DRM_ERROR("Kicking stuck wait on %s\n",
1555 ring->name);
1556 I915_WRITE_CTL(ring, tmp);
1557 return true;
1558 }
1ec14ad3
CW		 1559 return false;
1560}
1561
d1e61e7f
CW		 1562static bool i915_hangcheck_hung(struct drm_device *dev)
1563{
1564 drm_i915_private_t *dev_priv = dev->dev_private;
1565
1566 if (dev_priv->hangcheck_count++ > 1) {
1567 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1568 i915_handle_error(dev, true);
1569
1570 if (!IS_GEN2(dev)) {
1571 /* Is the chip hanging on a WAIT_FOR_EVENT?
1572 * If so we can simply poke the RB_WAIT bit
1573 * and break the hang. This should work on
1574 * all but the second generation chipsets.
1575 */
1576 if (kick_ring(&dev_priv->ring[RCS]))
1577 return false;
1578
1579 if (HAS_BSD(dev) && kick_ring(&dev_priv->ring[VCS]))
1580 return false;
1581
1582 if (HAS_BLT(dev) && kick_ring(&dev_priv->ring[BCS]))
1583 return false;
1584 }
1585
1586 return true;
1587 }
1588
1589 return false;
1590}
1591
f65d9421
BG		 1592/**
1593 * This is called when the chip hasn't reported back with completed
1594 * batchbuffers in a long time. The first time this is called we simply record
1595 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1596 * again, we assume the chip is wedged and try to fix it.
1597 */
1598void i915_hangcheck_elapsed(unsigned long data)
1599{
1600 struct drm_device *dev = (struct drm_device *)data;
1601 drm_i915_private_t *dev_priv = dev->dev_private;
097354eb 1602 uint32_t acthd, instdone, instdone1, acthd_bsd, acthd_blt;
893eead0
CW		 1603 bool err = false;
1604
3e0dc6b0
BW		 1605 if (!i915_enable_hangcheck)
1606 return;
1607
893eead0 1608 /* If all work is done then ACTHD clearly hasn't advanced. */
1ec14ad3
CW		 1609 if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) &&
1610 i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) &&
1611 i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) {
d1e61e7f
CW		 1612 if (err) {
1613 if (i915_hangcheck_hung(dev))
1614 return;
1615
893eead0 1616 goto repeat;
d1e61e7f
CW		 1617 }
1618
1619 dev_priv->hangcheck_count = 0;
893eead0
CW		 1620 return;
1621 }
b9201c14 1622
a6c45cf0 1623 if (INTEL_INFO(dev)->gen < 4) {
cbb465e7
CW		 1624 instdone = I915_READ(INSTDONE);
1625 instdone1 = 0;
1626 } else {
cbb465e7
CW		 1627 instdone = I915_READ(INSTDONE_I965);
1628 instdone1 = I915_READ(INSTDONE1);
1629 }
097354eb
DV		 1630 acthd = intel_ring_get_active_head(&dev_priv->ring[RCS]);
1631 acthd_bsd = HAS_BSD(dev) ?
1632 intel_ring_get_active_head(&dev_priv->ring[VCS]) : 0;
1633 acthd_blt = HAS_BLT(dev) ?
1634 intel_ring_get_active_head(&dev_priv->ring[BCS]) : 0;
f65d9421 1635
cbb465e7 1636 if (dev_priv->last_acthd == acthd &&
097354eb
DV		 1637 dev_priv->last_acthd_bsd == acthd_bsd &&
1638 dev_priv->last_acthd_blt == acthd_blt &&
cbb465e7
CW		 1639 dev_priv->last_instdone == instdone &&
1640 dev_priv->last_instdone1 == instdone1) {
d1e61e7f 1641 if (i915_hangcheck_hung(dev))
cbb465e7 1642 return;
cbb465e7
CW		 1643 } else {
1644 dev_priv->hangcheck_count = 0;
1645
1646 dev_priv->last_acthd = acthd;
097354eb
DV		 1647 dev_priv->last_acthd_bsd = acthd_bsd;
1648 dev_priv->last_acthd_blt = acthd_blt;
cbb465e7
CW		 1649 dev_priv->last_instdone = instdone;
1650 dev_priv->last_instdone1 = instdone1;
1651 }
f65d9421 1652
893eead0 1653repeat:
f65d9421 1654 /* Reset timer case chip hangs without another request being added */
b3b079db
CW		 1655 mod_timer(&dev_priv->hangcheck_timer,
1656 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
f65d9421
BG		 1657}
1658
1da177e4
LT		 1659/* drm_dma.h hooks
1660*/
f71d4af4 1661static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 1662{
1663 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1664
4697995b
JB		 1665 atomic_set(&dev_priv->irq_received, 0);
1666
4697995b 1667
036a4a7d 1668 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 1669
036a4a7d
ZW		 1670 /* XXX hotplug from PCH */
1671
1672 I915_WRITE(DEIMR, 0xffffffff);
1673 I915_WRITE(DEIER, 0x0);
3143a2bf 1674 POSTING_READ(DEIER);
036a4a7d
ZW		 1675
1676 /* and GT */
1677 I915_WRITE(GTIMR, 0xffffffff);
1678 I915_WRITE(GTIER, 0x0);
3143a2bf 1679 POSTING_READ(GTIER);
c650156a
ZW		 1680
1681 /* south display irq */
1682 I915_WRITE(SDEIMR, 0xffffffff);
1683 I915_WRITE(SDEIER, 0x0);
3143a2bf 1684 POSTING_READ(SDEIER);
036a4a7d
ZW		 1685}
1686
7e231dbe
JB		 1687static void valleyview_irq_preinstall(struct drm_device *dev)
1688{
1689 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1690 int pipe;
1691
1692 atomic_set(&dev_priv->irq_received, 0);
1693
7e231dbe
JB		 1694 /* VLV magic */
1695 I915_WRITE(VLV_IMR, 0);
1696 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1697 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1698 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1699
7e231dbe
JB		 1700 /* and GT */
1701 I915_WRITE(GTIIR, I915_READ(GTIIR));
1702 I915_WRITE(GTIIR, I915_READ(GTIIR));
1703 I915_WRITE(GTIMR, 0xffffffff);
1704 I915_WRITE(GTIER, 0x0);
1705 POSTING_READ(GTIER);
1706
1707 I915_WRITE(DPINVGTT, 0xff);
1708
1709 I915_WRITE(PORT_HOTPLUG_EN, 0);
1710 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1711 for_each_pipe(pipe)
1712 I915_WRITE(PIPESTAT(pipe), 0xffff);
1713 I915_WRITE(VLV_IIR, 0xffffffff);
1714 I915_WRITE(VLV_IMR, 0xffffffff);
1715 I915_WRITE(VLV_IER, 0x0);
1716 POSTING_READ(VLV_IER);
1717}
1718
7fe0b973
KP		 1719/*
1720 * Enable digital hotplug on the PCH, and configure the DP short pulse
1721 * duration to 2ms (which is the minimum in the Display Port spec)
1722 *
1723 * This register is the same on all known PCH chips.
1724 */
1725
1726static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1727{
1728 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1729 u32 hotplug;
1730
1731 hotplug = I915_READ(PCH_PORT_HOTPLUG);
1732 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1733 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1734 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1735 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1736 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1737}
1738
f71d4af4 1739static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d
ZW		 1740{
1741 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1742 /* enable kind of interrupts always enabled */
013d5aa2
JB		 1743 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1744 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1ec14ad3 1745 u32 render_irqs;
2d7b8366 1746 u32 hotplug_mask;
036a4a7d 1747
1ec14ad3 1748 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 1749
1750 /* should always can generate irq */
1751 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3
CW		 1752 I915_WRITE(DEIMR, dev_priv->irq_mask);
1753 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
3143a2bf 1754 POSTING_READ(DEIER);
036a4a7d 1755
1ec14ad3 1756 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 1757
1758 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 1759 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 1760
1ec14ad3
CW		 1761 if (IS_GEN6(dev))
1762 render_irqs =
1763 GT_USER_INTERRUPT |
e2a1e2f0
BW		 1764 GEN6_BSD_USER_INTERRUPT |
1765 GEN6_BLITTER_USER_INTERRUPT;
1ec14ad3
CW		 1766 else
1767 render_irqs =
88f23b8f 1768 GT_USER_INTERRUPT |
c6df541c 1769 GT_PIPE_NOTIFY |
1ec14ad3
CW		 1770 GT_BSD_USER_INTERRUPT;
1771 I915_WRITE(GTIER, render_irqs);
3143a2bf 1772 POSTING_READ(GTIER);
036a4a7d 1773
2d7b8366 1774 if (HAS_PCH_CPT(dev)) {
9035a97a
CW		 1775 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1776 SDE_PORTB_HOTPLUG_CPT |
1777 SDE_PORTC_HOTPLUG_CPT |
1778 SDE_PORTD_HOTPLUG_CPT);
2d7b8366 1779 } else {
9035a97a
CW		 1780 hotplug_mask = (SDE_CRT_HOTPLUG |
1781 SDE_PORTB_HOTPLUG |
1782 SDE_PORTC_HOTPLUG |
1783 SDE_PORTD_HOTPLUG |
1784 SDE_AUX_MASK);
2d7b8366
YL		 1785 }
1786
1ec14ad3 1787 dev_priv->pch_irq_mask = ~hotplug_mask;
c650156a
ZW		 1788
1789 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1ec14ad3
CW		 1790 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1791 I915_WRITE(SDEIER, hotplug_mask);
3143a2bf 1792 POSTING_READ(SDEIER);
c650156a 1793
7fe0b973
KP		 1794 ironlake_enable_pch_hotplug(dev);
1795
f97108d1
JB		 1796 if (IS_IRONLAKE_M(dev)) {
1797 /* Clear & enable PCU event interrupts */
1798 I915_WRITE(DEIIR, DE_PCU_EVENT);
1799 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1800 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1801 }
1802
036a4a7d
ZW		 1803 return 0;
1804}
1805
f71d4af4 1806static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 1807{
1808 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1809 /* enable kind of interrupts always enabled */
b615b57a
CW		 1810 u32 display_mask =
1811 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
1812 DE_PLANEC_FLIP_DONE_IVB |
1813 DE_PLANEB_FLIP_DONE_IVB |
1814 DE_PLANEA_FLIP_DONE_IVB;
b1f14ad0
JB		 1815 u32 render_irqs;
1816 u32 hotplug_mask;
1817
b1f14ad0
JB		 1818 dev_priv->irq_mask = ~display_mask;
1819
1820 /* should always can generate irq */
1821 I915_WRITE(DEIIR, I915_READ(DEIIR));
1822 I915_WRITE(DEIMR, dev_priv->irq_mask);
b615b57a
CW		 1823 I915_WRITE(DEIER,
1824 display_mask |
1825 DE_PIPEC_VBLANK_IVB |
1826 DE_PIPEB_VBLANK_IVB |
1827 DE_PIPEA_VBLANK_IVB);
b1f14ad0
JB		 1828 POSTING_READ(DEIER);
1829
1830 dev_priv->gt_irq_mask = ~0;
1831
1832 I915_WRITE(GTIIR, I915_READ(GTIIR));
1833 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1834
e2a1e2f0
BW		 1835 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
1836 GEN6_BLITTER_USER_INTERRUPT;
b1f14ad0
JB		 1837 I915_WRITE(GTIER, render_irqs);
1838 POSTING_READ(GTIER);
1839
1840 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1841 SDE_PORTB_HOTPLUG_CPT |
1842 SDE_PORTC_HOTPLUG_CPT |
1843 SDE_PORTD_HOTPLUG_CPT);
1844 dev_priv->pch_irq_mask = ~hotplug_mask;
1845
1846 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1847 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1848 I915_WRITE(SDEIER, hotplug_mask);
1849 POSTING_READ(SDEIER);
1850
7fe0b973
KP		 1851 ironlake_enable_pch_hotplug(dev);
1852
b1f14ad0
JB		 1853 return 0;
1854}
1855
7e231dbe
JB		 1856static int valleyview_irq_postinstall(struct drm_device *dev)
1857{
1858 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1859 u32 render_irqs;
1860 u32 enable_mask;
1861 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1862 u16 msid;
1863
1864 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
1865 enable_mask |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1866 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1867
1868 dev_priv->irq_mask = ~enable_mask;
1869
7e231dbe
JB		 1870 dev_priv->pipestat[0] = 0;
1871 dev_priv->pipestat[1] = 0;
1872
7e231dbe
JB		 1873 /* Hack for broken MSIs on VLV */
1874 pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
1875 pci_read_config_word(dev->pdev, 0x98, &msid);
1876 msid &= 0xff; /* mask out delivery bits */
1877 msid |= (1<<14);
1878 pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
1879
1880 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
1881 I915_WRITE(VLV_IER, enable_mask);
1882 I915_WRITE(VLV_IIR, 0xffffffff);
1883 I915_WRITE(PIPESTAT(0), 0xffff);
1884 I915_WRITE(PIPESTAT(1), 0xffff);
1885 POSTING_READ(VLV_IER);
1886
1887 I915_WRITE(VLV_IIR, 0xffffffff);
1888 I915_WRITE(VLV_IIR, 0xffffffff);
1889
1890 render_irqs = GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
1891 GT_GEN6_BLT_CS_ERROR_INTERRUPT |
e2a1e2f0 1892 GT_GEN6_BLT_USER_INTERRUPT |
7e231dbe
JB		 1893 GT_GEN6_BSD_USER_INTERRUPT |
1894 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
1895 GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
1896 GT_PIPE_NOTIFY |
1897 GT_RENDER_CS_ERROR_INTERRUPT |
1898 GT_SYNC_STATUS |
1899 GT_USER_INTERRUPT;
1900
1901 dev_priv->gt_irq_mask = ~render_irqs;
1902
1903 I915_WRITE(GTIIR, I915_READ(GTIIR));
1904 I915_WRITE(GTIIR, I915_READ(GTIIR));
1905 I915_WRITE(GTIMR, 0);
1906 I915_WRITE(GTIER, render_irqs);
1907 POSTING_READ(GTIER);
1908
1909 /* ack & enable invalid PTE error interrupts */
1910#if 0 /* FIXME: add support to irq handler for checking these bits */
1911 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
1912 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
1913#endif
1914
1915 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1916#if 0 /* FIXME: check register definitions; some have moved */
1917 /* Note HDMI and DP share bits */
1918 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1919 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1920 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1921 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1922 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1923 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1924 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1925 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1926 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1927 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1928 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1929 hotplug_en |= CRT_HOTPLUG_INT_EN;
1930 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1931 }
1932#endif
1933
1934 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1935
1936 return 0;
1937}
1938
7e231dbe
JB		 1939static void valleyview_irq_uninstall(struct drm_device *dev)
1940{
1941 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1942 int pipe;
1943
1944 if (!dev_priv)
1945 return;
1946
7e231dbe
JB		 1947 for_each_pipe(pipe)
1948 I915_WRITE(PIPESTAT(pipe), 0xffff);
1949
1950 I915_WRITE(HWSTAM, 0xffffffff);
1951 I915_WRITE(PORT_HOTPLUG_EN, 0);
1952 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1953 for_each_pipe(pipe)
1954 I915_WRITE(PIPESTAT(pipe), 0xffff);
1955 I915_WRITE(VLV_IIR, 0xffffffff);
1956 I915_WRITE(VLV_IMR, 0xffffffff);
1957 I915_WRITE(VLV_IER, 0x0);
1958 POSTING_READ(VLV_IER);
1959}
1960
f71d4af4 1961static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 1962{
1963 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 1964
1965 if (!dev_priv)
1966 return;
1967
036a4a7d
ZW		 1968 I915_WRITE(HWSTAM, 0xffffffff);
1969
1970 I915_WRITE(DEIMR, 0xffffffff);
1971 I915_WRITE(DEIER, 0x0);
1972 I915_WRITE(DEIIR, I915_READ(DEIIR));
1973
1974 I915_WRITE(GTIMR, 0xffffffff);
1975 I915_WRITE(GTIER, 0x0);
1976 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f
KP		 1977
1978 I915_WRITE(SDEIMR, 0xffffffff);
1979 I915_WRITE(SDEIER, 0x0);
1980 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
036a4a7d
ZW		 1981}
1982
a266c7d5 1983static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 1984{
1985 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 1986 int pipe;
91e3738e 1987
a266c7d5 1988 atomic_set(&dev_priv->irq_received, 0);
5ca58282 1989
9db4a9c7
JB		 1990 for_each_pipe(pipe)
1991 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 1992 I915_WRITE16(IMR, 0xffff);
1993 I915_WRITE16(IER, 0x0);
1994 POSTING_READ16(IER);
c2798b19
CW		 1995}
1996
1997static int i8xx_irq_postinstall(struct drm_device *dev)
1998{
1999 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2000
c2798b19
CW		 2001 dev_priv->pipestat[0] = 0;
2002 dev_priv->pipestat[1] = 0;
2003
2004 I915_WRITE16(EMR,
2005 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2006
2007 /* Unmask the interrupts that we always want on. */
2008 dev_priv->irq_mask =
2009 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2010 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2011 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2012 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2013 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2014 I915_WRITE16(IMR, dev_priv->irq_mask);
2015
2016 I915_WRITE16(IER,
2017 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2018 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2019 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2020 I915_USER_INTERRUPT);
2021 POSTING_READ16(IER);
2022
2023 return 0;
2024}
2025
2026static irqreturn_t i8xx_irq_handler(DRM_IRQ_ARGS)
2027{
2028 struct drm_device *dev = (struct drm_device *) arg;
2029 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 2030 u16 iir, new_iir;
2031 u32 pipe_stats[2];
2032 unsigned long irqflags;
2033 int irq_received;
2034 int pipe;
2035 u16 flip_mask =
2036 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2037 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2038
2039 atomic_inc(&dev_priv->irq_received);
2040
2041 iir = I915_READ16(IIR);
2042 if (iir == 0)
2043 return IRQ_NONE;
2044
2045 while (iir & ~flip_mask) {
2046 /* Can't rely on pipestat interrupt bit in iir as it might
2047 * have been cleared after the pipestat interrupt was received.
2048 * It doesn't set the bit in iir again, but it still produces
2049 * interrupts (for non-MSI).
2050 */
2051 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2052 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2053 i915_handle_error(dev, false);
2054
2055 for_each_pipe(pipe) {
2056 int reg = PIPESTAT(pipe);
2057 pipe_stats[pipe] = I915_READ(reg);
2058
2059 /*
2060 * Clear the PIPE*STAT regs before the IIR
2061 */
2062 if (pipe_stats[pipe] & 0x8000ffff) {
2063 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2064 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2065 pipe_name(pipe));
2066 I915_WRITE(reg, pipe_stats[pipe]);
2067 irq_received = 1;
2068 }
2069 }
2070 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2071
2072 I915_WRITE16(IIR, iir & ~flip_mask);
2073 new_iir = I915_READ16(IIR); /* Flush posted writes */
2074
d05c617e 2075 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 2076
2077 if (iir & I915_USER_INTERRUPT)
2078 notify_ring(dev, &dev_priv->ring[RCS]);
2079
2080 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2081 drm_handle_vblank(dev, 0)) {
2082 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2083 intel_prepare_page_flip(dev, 0);
2084 intel_finish_page_flip(dev, 0);
2085 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2086 }
2087 }
2088
2089 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2090 drm_handle_vblank(dev, 1)) {
2091 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2092 intel_prepare_page_flip(dev, 1);
2093 intel_finish_page_flip(dev, 1);
2094 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2095 }
2096 }
2097
2098 iir = new_iir;
2099 }
2100
2101 return IRQ_HANDLED;
2102}
2103
2104static void i8xx_irq_uninstall(struct drm_device * dev)
2105{
2106 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2107 int pipe;
2108
c2798b19
CW		 2109 for_each_pipe(pipe) {
2110 /* Clear enable bits; then clear status bits */
2111 I915_WRITE(PIPESTAT(pipe), 0);
2112 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2113 }
2114 I915_WRITE16(IMR, 0xffff);
2115 I915_WRITE16(IER, 0x0);
2116 I915_WRITE16(IIR, I915_READ16(IIR));
2117}
2118
a266c7d5
CW		 2119static void i915_irq_preinstall(struct drm_device * dev)
2120{
2121 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2122 int pipe;
2123
2124 atomic_set(&dev_priv->irq_received, 0);
2125
2126 if (I915_HAS_HOTPLUG(dev)) {
2127 I915_WRITE(PORT_HOTPLUG_EN, 0);
2128 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2129 }
2130
00d98ebd 2131 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 2132 for_each_pipe(pipe)
2133 I915_WRITE(PIPESTAT(pipe), 0);
2134 I915_WRITE(IMR, 0xffffffff);
2135 I915_WRITE(IER, 0x0);
2136 POSTING_READ(IER);
2137}
2138
2139static int i915_irq_postinstall(struct drm_device *dev)
2140{
2141 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 2142 u32 enable_mask;
a266c7d5 2143
a266c7d5
CW		 2144 dev_priv->pipestat[0] = 0;
2145 dev_priv->pipestat[1] = 0;
2146
38bde180
CW		 2147 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2148
2149 /* Unmask the interrupts that we always want on. */
2150 dev_priv->irq_mask =
2151 ~(I915_ASLE_INTERRUPT |
2152 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2153 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2154 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2155 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2156 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2157
2158 enable_mask =
2159 I915_ASLE_INTERRUPT |
2160 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2161 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2162 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2163 I915_USER_INTERRUPT;
2164
a266c7d5
CW		 2165 if (I915_HAS_HOTPLUG(dev)) {
2166 /* Enable in IER... */
2167 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2168 /* and unmask in IMR */
2169 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2170 }
2171
a266c7d5
CW		 2172 I915_WRITE(IMR, dev_priv->irq_mask);
2173 I915_WRITE(IER, enable_mask);
2174 POSTING_READ(IER);
2175
2176 if (I915_HAS_HOTPLUG(dev)) {
2177 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2178
a266c7d5
CW		 2179 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2180 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2181 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2182 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2183 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2184 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2185 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2186 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2187 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2188 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2189 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2190 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5
CW		 2191 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2192 }
2193
2194 /* Ignore TV since it's buggy */
2195
2196 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2197 }
2198
2199 intel_opregion_enable_asle(dev);
2200
2201 return 0;
2202}
2203
2204static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
2205{
2206 struct drm_device *dev = (struct drm_device *) arg;
2207 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 2208 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 2209 unsigned long irqflags;
38bde180
CW		 2210 u32 flip_mask =
2211 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2212 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2213 u32 flip[2] = {
2214 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2215 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2216 };
2217 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 2218
2219 atomic_inc(&dev_priv->irq_received);
2220
2221 iir = I915_READ(IIR);
38bde180
CW		 2222 do {
2223 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 2224 bool blc_event = false;
a266c7d5
CW		 2225
2226 /* Can't rely on pipestat interrupt bit in iir as it might
2227 * have been cleared after the pipestat interrupt was received.
2228 * It doesn't set the bit in iir again, but it still produces
2229 * interrupts (for non-MSI).
2230 */
2231 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2232 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2233 i915_handle_error(dev, false);
2234
2235 for_each_pipe(pipe) {
2236 int reg = PIPESTAT(pipe);
2237 pipe_stats[pipe] = I915_READ(reg);
2238
38bde180 2239 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 2240 if (pipe_stats[pipe] & 0x8000ffff) {
2241 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2242 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2243 pipe_name(pipe));
2244 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 2245 irq_received = true;
a266c7d5
CW		 2246 }
2247 }
2248 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2249
2250 if (!irq_received)
2251 break;
2252
a266c7d5
CW		 2253 /* Consume port. Then clear IIR or we'll miss events */
2254 if ((I915_HAS_HOTPLUG(dev)) &&
2255 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2256 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2257
2258 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2259 hotplug_status);
2260 if (hotplug_status & dev_priv->hotplug_supported_mask)
2261 queue_work(dev_priv->wq,
2262 &dev_priv->hotplug_work);
2263
2264 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 2265 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 2266 }
2267
38bde180 2268 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2269 new_iir = I915_READ(IIR); /* Flush posted writes */
2270
a266c7d5
CW		 2271 if (iir & I915_USER_INTERRUPT)
2272 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 2273
a266c7d5 2274 for_each_pipe(pipe) {
38bde180
CW		 2275 int plane = pipe;
2276 if (IS_MOBILE(dev))
2277 plane = !plane;
8291ee90 2278 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2279 drm_handle_vblank(dev, pipe)) {
38bde180
CW		 2280 if (iir & flip[plane]) {
2281 intel_prepare_page_flip(dev, plane);
2282 intel_finish_page_flip(dev, pipe);
2283 flip_mask &= ~flip[plane];
2284 }
a266c7d5
CW		 2285 }
2286
2287 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2288 blc_event = true;
2289 }
2290
a266c7d5
CW		 2291 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2292 intel_opregion_asle_intr(dev);
2293
2294 /* With MSI, interrupts are only generated when iir
2295 * transitions from zero to nonzero. If another bit got
2296 * set while we were handling the existing iir bits, then
2297 * we would never get another interrupt.
2298 *
2299 * This is fine on non-MSI as well, as if we hit this path
2300 * we avoid exiting the interrupt handler only to generate
2301 * another one.
2302 *
2303 * Note that for MSI this could cause a stray interrupt report
2304 * if an interrupt landed in the time between writing IIR and
2305 * the posting read. This should be rare enough to never
2306 * trigger the 99% of 100,000 interrupts test for disabling
2307 * stray interrupts.
2308 */
38bde180 2309 ret = IRQ_HANDLED;
a266c7d5 2310 iir = new_iir;
38bde180 2311 } while (iir & ~flip_mask);
a266c7d5 2312
d05c617e 2313 i915_update_dri1_breadcrumb(dev);
8291ee90 2314
a266c7d5
CW		 2315 return ret;
2316}
2317
2318static void i915_irq_uninstall(struct drm_device * dev)
2319{
2320 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2321 int pipe;
2322
a266c7d5
CW		 2323 if (I915_HAS_HOTPLUG(dev)) {
2324 I915_WRITE(PORT_HOTPLUG_EN, 0);
2325 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2326 }
2327
00d98ebd 2328 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 2329 for_each_pipe(pipe) {
2330 /* Clear enable bits; then clear status bits */
a266c7d5 2331 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 2332 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2333 }
a266c7d5
CW		 2334 I915_WRITE(IMR, 0xffffffff);
2335 I915_WRITE(IER, 0x0);
2336
a266c7d5
CW		 2337 I915_WRITE(IIR, I915_READ(IIR));
2338}
2339
2340static void i965_irq_preinstall(struct drm_device * dev)
2341{
2342 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2343 int pipe;
2344
2345 atomic_set(&dev_priv->irq_received, 0);
2346
2347 if (I915_HAS_HOTPLUG(dev)) {
2348 I915_WRITE(PORT_HOTPLUG_EN, 0);
2349 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2350 }
2351
2352 I915_WRITE(HWSTAM, 0xeffe);
2353 for_each_pipe(pipe)
2354 I915_WRITE(PIPESTAT(pipe), 0);
2355 I915_WRITE(IMR, 0xffffffff);
2356 I915_WRITE(IER, 0x0);
2357 POSTING_READ(IER);
2358}
2359
2360static int i965_irq_postinstall(struct drm_device *dev)
2361{
2362 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
bbba0a97 2363 u32 enable_mask;
a266c7d5
CW		 2364 u32 error_mask;
2365
a266c7d5 2366 /* Unmask the interrupts that we always want on. */
bbba0a97
CW		 2367 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2368 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2369 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2370 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2371 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2372 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2373
2374 enable_mask = ~dev_priv->irq_mask;
2375 enable_mask |= I915_USER_INTERRUPT;
2376
2377 if (IS_G4X(dev))
2378 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5
CW		 2379
2380 dev_priv->pipestat[0] = 0;
2381 dev_priv->pipestat[1] = 0;
2382
2383 if (I915_HAS_HOTPLUG(dev)) {
2384 /* Enable in IER... */
2385 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2386 /* and unmask in IMR */
2387 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2388 }
2389
2390 /*
2391 * Enable some error detection, note the instruction error mask
2392 * bit is reserved, so we leave it masked.
2393 */
2394 if (IS_G4X(dev)) {
2395 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2396 GM45_ERROR_MEM_PRIV |
2397 GM45_ERROR_CP_PRIV |
2398 I915_ERROR_MEMORY_REFRESH);
2399 } else {
2400 error_mask = ~(I915_ERROR_PAGE_TABLE |
2401 I915_ERROR_MEMORY_REFRESH);
2402 }
2403 I915_WRITE(EMR, error_mask);
2404
2405 I915_WRITE(IMR, dev_priv->irq_mask);
2406 I915_WRITE(IER, enable_mask);
2407 POSTING_READ(IER);
2408
2409 if (I915_HAS_HOTPLUG(dev)) {
2410 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2411
2412 /* Note HDMI and DP share bits */
2413 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2414 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2415 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2416 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2417 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2418 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2419 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2420 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2421 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2422 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2423 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2424 hotplug_en |= CRT_HOTPLUG_INT_EN;
2425
2426 /* Programming the CRT detection parameters tends
2427 to generate a spurious hotplug event about three
2428 seconds later. So just do it once.
2429 */
2430 if (IS_G4X(dev))
2431 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2432 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2433 }
2434
2435 /* Ignore TV since it's buggy */
2436
2437 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2438 }
2439
2440 intel_opregion_enable_asle(dev);
2441
2442 return 0;
2443}
2444
2445static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS)
2446{
2447 struct drm_device *dev = (struct drm_device *) arg;
2448 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 2449 u32 iir, new_iir;
2450 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 2451 unsigned long irqflags;
2452 int irq_received;
2453 int ret = IRQ_NONE, pipe;
a266c7d5
CW		 2454
2455 atomic_inc(&dev_priv->irq_received);
2456
2457 iir = I915_READ(IIR);
2458
a266c7d5 2459 for (;;) {
2c8ba29f
CW		 2460 bool blc_event = false;
2461
a266c7d5
CW		 2462 irq_received = iir != 0;
2463
2464 /* Can't rely on pipestat interrupt bit in iir as it might
2465 * have been cleared after the pipestat interrupt was received.
2466 * It doesn't set the bit in iir again, but it still produces
2467 * interrupts (for non-MSI).
2468 */
2469 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2470 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2471 i915_handle_error(dev, false);
2472
2473 for_each_pipe(pipe) {
2474 int reg = PIPESTAT(pipe);
2475 pipe_stats[pipe] = I915_READ(reg);
2476
2477 /*
2478 * Clear the PIPE*STAT regs before the IIR
2479 */
2480 if (pipe_stats[pipe] & 0x8000ffff) {
2481 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2482 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2483 pipe_name(pipe));
2484 I915_WRITE(reg, pipe_stats[pipe]);
2485 irq_received = 1;
2486 }
2487 }
2488 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2489
2490 if (!irq_received)
2491 break;
2492
2493 ret = IRQ_HANDLED;
2494
2495 /* Consume port. Then clear IIR or we'll miss events */
2496 if ((I915_HAS_HOTPLUG(dev)) &&
2497 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2498 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2499
2500 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2501 hotplug_status);
2502 if (hotplug_status & dev_priv->hotplug_supported_mask)
2503 queue_work(dev_priv->wq,
2504 &dev_priv->hotplug_work);
2505
2506 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2507 I915_READ(PORT_HOTPLUG_STAT);
2508 }
2509
2510 I915_WRITE(IIR, iir);
2511 new_iir = I915_READ(IIR); /* Flush posted writes */
2512
a266c7d5
CW		 2513 if (iir & I915_USER_INTERRUPT)
2514 notify_ring(dev, &dev_priv->ring[RCS]);
2515 if (iir & I915_BSD_USER_INTERRUPT)
2516 notify_ring(dev, &dev_priv->ring[VCS]);
2517
4f7d1e79 2518 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
a266c7d5 2519 intel_prepare_page_flip(dev, 0);
a266c7d5 2520
4f7d1e79 2521 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
a266c7d5 2522 intel_prepare_page_flip(dev, 1);
a266c7d5
CW		 2523
2524 for_each_pipe(pipe) {
2c8ba29f 2525 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2526 drm_handle_vblank(dev, pipe)) {
4f7d1e79
CW		 2527 i915_pageflip_stall_check(dev, pipe);
2528 intel_finish_page_flip(dev, pipe);
a266c7d5
CW		 2529 }
2530
2531 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2532 blc_event = true;
2533 }
2534
2535
2536 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2537 intel_opregion_asle_intr(dev);
2538
2539 /* With MSI, interrupts are only generated when iir
2540 * transitions from zero to nonzero. If another bit got
2541 * set while we were handling the existing iir bits, then
2542 * we would never get another interrupt.
2543 *
2544 * This is fine on non-MSI as well, as if we hit this path
2545 * we avoid exiting the interrupt handler only to generate
2546 * another one.
2547 *
2548 * Note that for MSI this could cause a stray interrupt report
2549 * if an interrupt landed in the time between writing IIR and
2550 * the posting read. This should be rare enough to never
2551 * trigger the 99% of 100,000 interrupts test for disabling
2552 * stray interrupts.
2553 */
2554 iir = new_iir;
2555 }
2556
d05c617e 2557 i915_update_dri1_breadcrumb(dev);
2c8ba29f 2558
a266c7d5
CW		 2559 return ret;
2560}
2561
2562static void i965_irq_uninstall(struct drm_device * dev)
2563{
2564 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2565 int pipe;
2566
2567 if (!dev_priv)
2568 return;
2569
a266c7d5
CW		 2570 if (I915_HAS_HOTPLUG(dev)) {
2571 I915_WRITE(PORT_HOTPLUG_EN, 0);
2572 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2573 }
2574
2575 I915_WRITE(HWSTAM, 0xffffffff);
2576 for_each_pipe(pipe)
2577 I915_WRITE(PIPESTAT(pipe), 0);
2578 I915_WRITE(IMR, 0xffffffff);
2579 I915_WRITE(IER, 0x0);
2580
2581 for_each_pipe(pipe)
2582 I915_WRITE(PIPESTAT(pipe),
2583 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2584 I915_WRITE(IIR, I915_READ(IIR));
2585}
2586
f71d4af4
JB		 2587void intel_irq_init(struct drm_device *dev)
2588{
8b2e326d
CW		 2589 struct drm_i915_private *dev_priv = dev->dev_private;
2590
2591 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2592 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
2593 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
2594
f71d4af4
JB		 2595 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2596 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7e231dbe
JB		 2597 if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev) ||
2598 IS_VALLEYVIEW(dev)) {
f71d4af4
JB		 2599 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2600 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2601 }
2602
c3613de9
KP		 2603 if (drm_core_check_feature(dev, DRIVER_MODESET))
2604 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2605 else
2606 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 2607 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2608
7e231dbe
JB		 2609 if (IS_VALLEYVIEW(dev)) {
2610 dev->driver->irq_handler = valleyview_irq_handler;
2611 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2612 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2613 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2614 dev->driver->enable_vblank = valleyview_enable_vblank;
2615 dev->driver->disable_vblank = valleyview_disable_vblank;
2616 } else if (IS_IVYBRIDGE(dev)) {
f71d4af4
JB		 2617 /* Share pre & uninstall handlers with ILK/SNB */
2618 dev->driver->irq_handler = ivybridge_irq_handler;
2619 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2620 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2621 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2622 dev->driver->enable_vblank = ivybridge_enable_vblank;
2623 dev->driver->disable_vblank = ivybridge_disable_vblank;
2624 } else if (HAS_PCH_SPLIT(dev)) {
2625 dev->driver->irq_handler = ironlake_irq_handler;
2626 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2627 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2628 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2629 dev->driver->enable_vblank = ironlake_enable_vblank;
2630 dev->driver->disable_vblank = ironlake_disable_vblank;
2631 } else {
c2798b19
CW		 2632 if (INTEL_INFO(dev)->gen == 2) {
2633 dev->driver->irq_preinstall = i8xx_irq_preinstall;
2634 dev->driver->irq_postinstall = i8xx_irq_postinstall;
2635 dev->driver->irq_handler = i8xx_irq_handler;
2636 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5 2637 } else if (INTEL_INFO(dev)->gen == 3) {
4f7d1e79
CW		 2638 /* IIR "flip pending" means done if this bit is set */
2639 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
2640
a266c7d5
CW		 2641 dev->driver->irq_preinstall = i915_irq_preinstall;
2642 dev->driver->irq_postinstall = i915_irq_postinstall;
2643 dev->driver->irq_uninstall = i915_irq_uninstall;
2644 dev->driver->irq_handler = i915_irq_handler;
c2798b19 2645 } else {
a266c7d5
CW		 2646 dev->driver->irq_preinstall = i965_irq_preinstall;
2647 dev->driver->irq_postinstall = i965_irq_postinstall;
2648 dev->driver->irq_uninstall = i965_irq_uninstall;
2649 dev->driver->irq_handler = i965_irq_handler;
c2798b19 2650 }
f71d4af4
JB		 2651 dev->driver->enable_vblank = i915_enable_vblank;
2652 dev->driver->disable_vblank = i915_disable_vblank;
2653 }
2654}
Ubuntu Artful kernel mirror