]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/gpu/drm/i915/i915_irq.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: factor out valleyview_pipestat_irq_handler
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
b2c88f5b 33#include <linux/circ_buf.h>
760285e7
DH		 34#include <drm/drmP.h>
35#include <drm/i915_drm.h>
1da177e4 36#include "i915_drv.h"
1c5d22f7 37#include "i915_trace.h"
79e53945 38#include "intel_drv.h"
1da177e4 39
e5868a31
EE		 40static const u32 hpd_ibx[] = {
41 [HPD_CRT] = SDE_CRT_HOTPLUG,
42 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
43 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
44 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
45 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
46};
47
48static const u32 hpd_cpt[] = {
49 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
73c352a2 50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
e5868a31
EE		 51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
54};
55
56static const u32 hpd_mask_i915[] = {
57 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
58 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
59 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
60 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
61 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
62 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
63};
64
704cfb87 65static const u32 hpd_status_g4x[] = {
e5868a31
EE		 66 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
67 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
68 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
69 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
70 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
71 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
72};
73
e5868a31
EE		 74static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
75 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
76 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
77 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
78 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
79 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
80 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
81};
82
036a4a7d 83/* For display hotplug interrupt */
995b6762 84static void
f2b115e6 85ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 86{
4bc9d430
DV		 87 assert_spin_locked(&dev_priv->irq_lock);
88
c67a470b
PZ		 89 if (dev_priv->pc8.irqs_disabled) {
90 WARN(1, "IRQs disabled\n");
91 dev_priv->pc8.regsave.deimr &= ~mask;
92 return;
93 }
94
1ec14ad3
CW		 95 if ((dev_priv->irq_mask & mask) != 0) {
96 dev_priv->irq_mask &= ~mask;
97 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 98 POSTING_READ(DEIMR);
036a4a7d
ZW		 99 }
100}
101
0ff9800a 102static void
f2b115e6 103ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 104{
4bc9d430
DV		 105 assert_spin_locked(&dev_priv->irq_lock);
106
c67a470b
PZ		 107 if (dev_priv->pc8.irqs_disabled) {
108 WARN(1, "IRQs disabled\n");
109 dev_priv->pc8.regsave.deimr |= mask;
110 return;
111 }
112
1ec14ad3
CW		 113 if ((dev_priv->irq_mask & mask) != mask) {
114 dev_priv->irq_mask |= mask;
115 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 116 POSTING_READ(DEIMR);
036a4a7d
ZW		 117 }
118}
119
43eaea13
PZ		 120/**
121 * ilk_update_gt_irq - update GTIMR
122 * @dev_priv: driver private
123 * @interrupt_mask: mask of interrupt bits to update
124 * @enabled_irq_mask: mask of interrupt bits to enable
125 */
126static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
127 uint32_t interrupt_mask,
128 uint32_t enabled_irq_mask)
129{
130 assert_spin_locked(&dev_priv->irq_lock);
131
c67a470b
PZ		 132 if (dev_priv->pc8.irqs_disabled) {
133 WARN(1, "IRQs disabled\n");
134 dev_priv->pc8.regsave.gtimr &= ~interrupt_mask;
135 dev_priv->pc8.regsave.gtimr |= (~enabled_irq_mask &
136 interrupt_mask);
137 return;
138 }
139
43eaea13
PZ		 140 dev_priv->gt_irq_mask &= ~interrupt_mask;
141 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
142 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
143 POSTING_READ(GTIMR);
144}
145
146void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
147{
148 ilk_update_gt_irq(dev_priv, mask, mask);
149}
150
151void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
152{
153 ilk_update_gt_irq(dev_priv, mask, 0);
154}
155
edbfdb45
PZ		 156/**
157 * snb_update_pm_irq - update GEN6_PMIMR
158 * @dev_priv: driver private
159 * @interrupt_mask: mask of interrupt bits to update
160 * @enabled_irq_mask: mask of interrupt bits to enable
161 */
162static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
163 uint32_t interrupt_mask,
164 uint32_t enabled_irq_mask)
165{
605cd25b 166 uint32_t new_val;
edbfdb45
PZ		 167
168 assert_spin_locked(&dev_priv->irq_lock);
169
c67a470b
PZ		 170 if (dev_priv->pc8.irqs_disabled) {
171 WARN(1, "IRQs disabled\n");
172 dev_priv->pc8.regsave.gen6_pmimr &= ~interrupt_mask;
173 dev_priv->pc8.regsave.gen6_pmimr |= (~enabled_irq_mask &
174 interrupt_mask);
175 return;
176 }
177
605cd25b 178 new_val = dev_priv->pm_irq_mask;
f52ecbcf
PZ		 179 new_val &= ~interrupt_mask;
180 new_val |= (~enabled_irq_mask & interrupt_mask);
181
605cd25b
PZ		 182 if (new_val != dev_priv->pm_irq_mask) {
183 dev_priv->pm_irq_mask = new_val;
184 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
f52ecbcf
PZ		 185 POSTING_READ(GEN6_PMIMR);
186 }
edbfdb45
PZ		 187}
188
189void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
190{
191 snb_update_pm_irq(dev_priv, mask, mask);
192}
193
194void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
195{
196 snb_update_pm_irq(dev_priv, mask, 0);
197}
198
8664281b
PZ		 199static bool ivb_can_enable_err_int(struct drm_device *dev)
200{
201 struct drm_i915_private *dev_priv = dev->dev_private;
202 struct intel_crtc *crtc;
203 enum pipe pipe;
204
4bc9d430
DV		 205 assert_spin_locked(&dev_priv->irq_lock);
206
8664281b
PZ		 207 for_each_pipe(pipe) {
208 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
209
210 if (crtc->cpu_fifo_underrun_disabled)
211 return false;
212 }
213
214 return true;
215}
216
217static bool cpt_can_enable_serr_int(struct drm_device *dev)
218{
219 struct drm_i915_private *dev_priv = dev->dev_private;
220 enum pipe pipe;
221 struct intel_crtc *crtc;
222
fee884ed
DV		 223 assert_spin_locked(&dev_priv->irq_lock);
224
8664281b
PZ		 225 for_each_pipe(pipe) {
226 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
227
228 if (crtc->pch_fifo_underrun_disabled)
229 return false;
230 }
231
232 return true;
233}
234
2d9d2b0b
VS		 235static void i9xx_clear_fifo_underrun(struct drm_device *dev, enum pipe pipe)
236{
237 struct drm_i915_private *dev_priv = dev->dev_private;
238 u32 reg = PIPESTAT(pipe);
239 u32 pipestat = I915_READ(reg) & 0x7fff0000;
240
241 assert_spin_locked(&dev_priv->irq_lock);
242
243 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
244 POSTING_READ(reg);
245}
246
8664281b
PZ		 247static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
248 enum pipe pipe, bool enable)
249{
250 struct drm_i915_private *dev_priv = dev->dev_private;
251 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
252 DE_PIPEB_FIFO_UNDERRUN;
253
254 if (enable)
255 ironlake_enable_display_irq(dev_priv, bit);
256 else
257 ironlake_disable_display_irq(dev_priv, bit);
258}
259
260static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
7336df65 261 enum pipe pipe, bool enable)
8664281b
PZ		 262{
263 struct drm_i915_private *dev_priv = dev->dev_private;
8664281b 264 if (enable) {
7336df65
DV		 265 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
266
8664281b
PZ		 267 if (!ivb_can_enable_err_int(dev))
268 return;
269
8664281b
PZ		 270 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
271 } else {
7336df65
DV		 272 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
273
274 /* Change the state _after_ we've read out the current one. */
8664281b 275 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
7336df65
DV		 276
277 if (!was_enabled &&
278 (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
279 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
280 pipe_name(pipe));
281 }
8664281b
PZ		 282 }
283}
284
38d83c96
DV		 285static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
286 enum pipe pipe, bool enable)
287{
288 struct drm_i915_private *dev_priv = dev->dev_private;
289
290 assert_spin_locked(&dev_priv->irq_lock);
291
292 if (enable)
293 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
294 else
295 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
296 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
297 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
298}
299
fee884ed
DV		 300/**
301 * ibx_display_interrupt_update - update SDEIMR
302 * @dev_priv: driver private
303 * @interrupt_mask: mask of interrupt bits to update
304 * @enabled_irq_mask: mask of interrupt bits to enable
305 */
306static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
307 uint32_t interrupt_mask,
308 uint32_t enabled_irq_mask)
309{
310 uint32_t sdeimr = I915_READ(SDEIMR);
311 sdeimr &= ~interrupt_mask;
312 sdeimr |= (~enabled_irq_mask & interrupt_mask);
313
314 assert_spin_locked(&dev_priv->irq_lock);
315
c67a470b
PZ		 316 if (dev_priv->pc8.irqs_disabled &&
317 (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) {
318 WARN(1, "IRQs disabled\n");
319 dev_priv->pc8.regsave.sdeimr &= ~interrupt_mask;
320 dev_priv->pc8.regsave.sdeimr |= (~enabled_irq_mask &
321 interrupt_mask);
322 return;
323 }
324
fee884ed
DV		 325 I915_WRITE(SDEIMR, sdeimr);
326 POSTING_READ(SDEIMR);
327}
328#define ibx_enable_display_interrupt(dev_priv, bits) \
329 ibx_display_interrupt_update((dev_priv), (bits), (bits))
330#define ibx_disable_display_interrupt(dev_priv, bits) \
331 ibx_display_interrupt_update((dev_priv), (bits), 0)
332
de28075d
DV		 333static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
334 enum transcoder pch_transcoder,
8664281b
PZ		 335 bool enable)
336{
8664281b 337 struct drm_i915_private *dev_priv = dev->dev_private;
de28075d
DV		 338 uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
339 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
8664281b
PZ		 340
341 if (enable)
fee884ed 342 ibx_enable_display_interrupt(dev_priv, bit);
8664281b 343 else
fee884ed 344 ibx_disable_display_interrupt(dev_priv, bit);
8664281b
PZ		 345}
346
347static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
348 enum transcoder pch_transcoder,
349 bool enable)
350{
351 struct drm_i915_private *dev_priv = dev->dev_private;
352
353 if (enable) {
1dd246fb
DV		 354 I915_WRITE(SERR_INT,
355 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
356
8664281b
PZ		 357 if (!cpt_can_enable_serr_int(dev))
358 return;
359
fee884ed 360 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
8664281b 361 } else {
1dd246fb
DV		 362 uint32_t tmp = I915_READ(SERR_INT);
363 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
364
365 /* Change the state _after_ we've read out the current one. */
fee884ed 366 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
1dd246fb
DV		 367
368 if (!was_enabled &&
369 (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
370 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
371 transcoder_name(pch_transcoder));
372 }
8664281b 373 }
8664281b
PZ		 374}
375
376/**
377 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
378 * @dev: drm device
379 * @pipe: pipe
380 * @enable: true if we want to report FIFO underrun errors, false otherwise
381 *
382 * This function makes us disable or enable CPU fifo underruns for a specific
383 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
384 * reporting for one pipe may also disable all the other CPU error interruts for
385 * the other pipes, due to the fact that there's just one interrupt mask/enable
386 * bit for all the pipes.
387 *
388 * Returns the previous state of underrun reporting.
389 */
390bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
391 enum pipe pipe, bool enable)
392{
393 struct drm_i915_private *dev_priv = dev->dev_private;
394 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
396 unsigned long flags;
397 bool ret;
398
399 spin_lock_irqsave(&dev_priv->irq_lock, flags);
400
401 ret = !intel_crtc->cpu_fifo_underrun_disabled;
402
403 if (enable == ret)
404 goto done;
405
406 intel_crtc->cpu_fifo_underrun_disabled = !enable;
407
2d9d2b0b
VS		 408 if (enable && (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)))
409 i9xx_clear_fifo_underrun(dev, pipe);
410 else if (IS_GEN5(dev) || IS_GEN6(dev))
8664281b
PZ		 411 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
412 else if (IS_GEN7(dev))
7336df65 413 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
38d83c96
DV		 414 else if (IS_GEN8(dev))
415 broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
8664281b
PZ		 416
417done:
418 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
419 return ret;
420}
421
422/**
423 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
424 * @dev: drm device
425 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
426 * @enable: true if we want to report FIFO underrun errors, false otherwise
427 *
428 * This function makes us disable or enable PCH fifo underruns for a specific
429 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
430 * underrun reporting for one transcoder may also disable all the other PCH
431 * error interruts for the other transcoders, due to the fact that there's just
432 * one interrupt mask/enable bit for all the transcoders.
433 *
434 * Returns the previous state of underrun reporting.
435 */
436bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
437 enum transcoder pch_transcoder,
438 bool enable)
439{
440 struct drm_i915_private *dev_priv = dev->dev_private;
de28075d
DV		 441 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
442 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8664281b
PZ		 443 unsigned long flags;
444 bool ret;
445
de28075d
DV		 446 /*
447 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
448 * has only one pch transcoder A that all pipes can use. To avoid racy
449 * pch transcoder -> pipe lookups from interrupt code simply store the
450 * underrun statistics in crtc A. Since we never expose this anywhere
451 * nor use it outside of the fifo underrun code here using the "wrong"
452 * crtc on LPT won't cause issues.
453 */
8664281b
PZ		 454
455 spin_lock_irqsave(&dev_priv->irq_lock, flags);
456
457 ret = !intel_crtc->pch_fifo_underrun_disabled;
458
459 if (enable == ret)
460 goto done;
461
462 intel_crtc->pch_fifo_underrun_disabled = !enable;
463
464 if (HAS_PCH_IBX(dev))
de28075d 465 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
8664281b
PZ		 466 else
467 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
468
469done:
470 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
471 return ret;
472}
473
474
7c463586 475void
3b6c42e8 476i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask)
7c463586 477{
46c06a30
VS		 478 u32 reg = PIPESTAT(pipe);
479 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 480
b79480ba
DV		 481 assert_spin_locked(&dev_priv->irq_lock);
482
46c06a30
VS		 483 if ((pipestat & mask) == mask)
484 return;
485
486 /* Enable the interrupt, clear any pending status */
487 pipestat |= mask | (mask >> 16);
488 I915_WRITE(reg, pipestat);
489 POSTING_READ(reg);
7c463586
KP		 490}
491
492void
3b6c42e8 493i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask)
7c463586 494{
46c06a30
VS		 495 u32 reg = PIPESTAT(pipe);
496 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 497
b79480ba
DV		 498 assert_spin_locked(&dev_priv->irq_lock);
499
46c06a30
VS		 500 if ((pipestat & mask) == 0)
501 return;
502
503 pipestat &= ~mask;
504 I915_WRITE(reg, pipestat);
505 POSTING_READ(reg);
7c463586
KP		 506}
507
01c66889 508/**
f49e38dd 509 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
01c66889 510 */
f49e38dd 511static void i915_enable_asle_pipestat(struct drm_device *dev)
01c66889 512{
1ec14ad3
CW		 513 drm_i915_private_t *dev_priv = dev->dev_private;
514 unsigned long irqflags;
515
f49e38dd
JN		 516 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
517 return;
518
1ec14ad3 519 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 520
3b6c42e8 521 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_ENABLE);
f898780b 522 if (INTEL_INFO(dev)->gen >= 4)
3b6c42e8
DV		 523 i915_enable_pipestat(dev_priv, PIPE_A,
524 PIPE_LEGACY_BLC_EVENT_ENABLE);
1ec14ad3
CW		 525
526 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 527}
528
0a3e67a4
JB		 529/**
530 * i915_pipe_enabled - check if a pipe is enabled
531 * @dev: DRM device
532 * @pipe: pipe to check
533 *
534 * Reading certain registers when the pipe is disabled can hang the chip.
535 * Use this routine to make sure the PLL is running and the pipe is active
536 * before reading such registers if unsure.
537 */
538static int
539i915_pipe_enabled(struct drm_device *dev, int pipe)
540{
541 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
702e7a56 542
a01025af
DV		 543 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
544 /* Locking is horribly broken here, but whatever. */
545 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
546 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
71f8ba6b 547
a01025af
DV		 548 return intel_crtc->active;
549 } else {
550 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
551 }
0a3e67a4
JB		 552}
553
4cdb83ec
VS		 554static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
555{
556 /* Gen2 doesn't have a hardware frame counter */
557 return 0;
558}
559
42f52ef8
KP		 560/* Called from drm generic code, passed a 'crtc', which
561 * we use as a pipe index
562 */
f71d4af4 563static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 564{
565 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
566 unsigned long high_frame;
567 unsigned long low_frame;
391f75e2 568 u32 high1, high2, low, pixel, vbl_start;
0a3e67a4
JB		 569
570 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 571 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 572 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 573 return 0;
574 }
575
391f75e2
VS		 576 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
577 struct intel_crtc *intel_crtc =
578 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
579 const struct drm_display_mode *mode =
580 &intel_crtc->config.adjusted_mode;
581
582 vbl_start = mode->crtc_vblank_start * mode->crtc_htotal;
583 } else {
584 enum transcoder cpu_transcoder =
585 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
586 u32 htotal;
587
588 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
589 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
590
591 vbl_start *= htotal;
592 }
593
9db4a9c7
JB		 594 high_frame = PIPEFRAME(pipe);
595 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 596
0a3e67a4
JB		 597 /*
598 * High & low register fields aren't synchronized, so make sure
599 * we get a low value that's stable across two reads of the high
600 * register.
601 */
602 do {
5eddb70b 603 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
391f75e2 604 low = I915_READ(low_frame);
5eddb70b 605 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 606 } while (high1 != high2);
607
5eddb70b 608 high1 >>= PIPE_FRAME_HIGH_SHIFT;
391f75e2 609 pixel = low & PIPE_PIXEL_MASK;
5eddb70b 610 low >>= PIPE_FRAME_LOW_SHIFT;
391f75e2
VS		 611
612 /*
613 * The frame counter increments at beginning of active.
614 * Cook up a vblank counter by also checking the pixel
615 * counter against vblank start.
616 */
edc08d0a 617 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
0a3e67a4
JB		 618}
619
f71d4af4 620static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 621{
622 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 623 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 624
625 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 626 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 627 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 628 return 0;
629 }
630
631 return I915_READ(reg);
632}
633
ad3543ed
MK		 634/* raw reads, only for fast reads of display block, no need for forcewake etc. */
635#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
636#define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
637
095163ba 638static bool ilk_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe)
54ddcbd2
VS		 639{
640 struct drm_i915_private *dev_priv = dev->dev_private;
641 uint32_t status;
642
095163ba 643 if (INTEL_INFO(dev)->gen < 7) {
54ddcbd2
VS		 644 status = pipe == PIPE_A ?
645 DE_PIPEA_VBLANK :
646 DE_PIPEB_VBLANK;
54ddcbd2
VS		 647 } else {
648 switch (pipe) {
649 default:
650 case PIPE_A:
651 status = DE_PIPEA_VBLANK_IVB;
652 break;
653 case PIPE_B:
654 status = DE_PIPEB_VBLANK_IVB;
655 break;
656 case PIPE_C:
657 status = DE_PIPEC_VBLANK_IVB;
658 break;
659 }
54ddcbd2 660 }
ad3543ed 661
095163ba 662 return __raw_i915_read32(dev_priv, DEISR) & status;
54ddcbd2
VS		 663}
664
f71d4af4 665static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
abca9e45
VS		 666 unsigned int flags, int *vpos, int *hpos,
667 ktime_t *stime, ktime_t *etime)
0af7e4df 668{
c2baf4b7
VS		 669 struct drm_i915_private *dev_priv = dev->dev_private;
670 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
672 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
3aa18df8 673 int position;
0af7e4df
MK		 674 int vbl_start, vbl_end, htotal, vtotal;
675 bool in_vbl = true;
676 int ret = 0;
ad3543ed 677 unsigned long irqflags;
0af7e4df 678
c2baf4b7 679 if (!intel_crtc->active) {
0af7e4df 680 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 681 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 682 return 0;
683 }
684
c2baf4b7
VS		 685 htotal = mode->crtc_htotal;
686 vtotal = mode->crtc_vtotal;
687 vbl_start = mode->crtc_vblank_start;
688 vbl_end = mode->crtc_vblank_end;
0af7e4df 689
d31faf65
VS		 690 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
691 vbl_start = DIV_ROUND_UP(vbl_start, 2);
692 vbl_end /= 2;
693 vtotal /= 2;
694 }
695
c2baf4b7
VS		 696 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
697
ad3543ed
MK		 698 /*
699 * Lock uncore.lock, as we will do multiple timing critical raw
700 * register reads, potentially with preemption disabled, so the
701 * following code must not block on uncore.lock.
702 */
703 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
704
705 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
706
707 /* Get optional system timestamp before query. */
708 if (stime)
709 *stime = ktime_get();
710
7c06b08a 711 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
0af7e4df
MK		 712 /* No obvious pixelcount register. Only query vertical
713 * scanout position from Display scan line register.
714 */
7c06b08a 715 if (IS_GEN2(dev))
ad3543ed 716 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
7c06b08a 717 else
ad3543ed 718 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
54ddcbd2 719
095163ba
VS		 720 if (HAS_PCH_SPLIT(dev)) {
721 /*
722 * The scanline counter increments at the leading edge
723 * of hsync, ie. it completely misses the active portion
724 * of the line. Fix up the counter at both edges of vblank
725 * to get a more accurate picture whether we're in vblank
726 * or not.
727 */
728 in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
729 if ((in_vbl && position == vbl_start - 1) ||
730 (!in_vbl && position == vbl_end - 1))
731 position = (position + 1) % vtotal;
732 } else {
733 /*
734 * ISR vblank status bits don't work the way we'd want
735 * them to work on non-PCH platforms (for
736 * ilk_pipe_in_vblank_locked()), and there doesn't
737 * appear any other way to determine if we're currently
738 * in vblank.
739 *
740 * Instead let's assume that we're already in vblank if
741 * we got called from the vblank interrupt and the
742 * scanline counter value indicates that we're on the
743 * line just prior to vblank start. This should result
744 * in the correct answer, unless the vblank interrupt
745 * delivery really got delayed for almost exactly one
746 * full frame/field.
747 */
748 if (flags & DRM_CALLED_FROM_VBLIRQ &&
749 position == vbl_start - 1) {
750 position = (position + 1) % vtotal;
751
752 /* Signal this correction as "applied". */
753 ret |= 0x8;
754 }
755 }
0af7e4df
MK		 756 } else {
757 /* Have access to pixelcount since start of frame.
758 * We can split this into vertical and horizontal
759 * scanout position.
760 */
ad3543ed 761 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
0af7e4df 762
3aa18df8
VS		 763 /* convert to pixel counts */
764 vbl_start *= htotal;
765 vbl_end *= htotal;
766 vtotal *= htotal;
0af7e4df
MK		 767 }
768
ad3543ed
MK		 769 /* Get optional system timestamp after query. */
770 if (etime)
771 *etime = ktime_get();
772
773 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
774
775 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
776
3aa18df8
VS		 777 in_vbl = position >= vbl_start && position < vbl_end;
778
779 /*
780 * While in vblank, position will be negative
781 * counting up towards 0 at vbl_end. And outside
782 * vblank, position will be positive counting
783 * up since vbl_end.
784 */
785 if (position >= vbl_start)
786 position -= vbl_end;
787 else
788 position += vtotal - vbl_end;
0af7e4df 789
7c06b08a 790 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
3aa18df8
VS		 791 *vpos = position;
792 *hpos = 0;
793 } else {
794 *vpos = position / htotal;
795 *hpos = position - (*vpos * htotal);
796 }
0af7e4df 797
0af7e4df
MK		 798 /* In vblank? */
799 if (in_vbl)
800 ret |= DRM_SCANOUTPOS_INVBL;
801
802 return ret;
803}
804
f71d4af4 805static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 806 int *max_error,
807 struct timeval *vblank_time,
808 unsigned flags)
809{
4041b853 810 struct drm_crtc *crtc;
0af7e4df 811
7eb552ae 812 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
4041b853 813 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 814 return -EINVAL;
815 }
816
817 /* Get drm_crtc to timestamp: */
4041b853
CW		 818 crtc = intel_get_crtc_for_pipe(dev, pipe);
819 if (crtc == NULL) {
820 DRM_ERROR("Invalid crtc %d\n", pipe);
821 return -EINVAL;
822 }
823
824 if (!crtc->enabled) {
825 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
826 return -EBUSY;
827 }
0af7e4df
MK		 828
829 /* Helper routine in DRM core does all the work: */
4041b853
CW		 830 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
831 vblank_time, flags,
7da903ef
VS		 832 crtc,
833 &to_intel_crtc(crtc)->config.adjusted_mode);
0af7e4df
MK		 834}
835
67c347ff
JN		 836static bool intel_hpd_irq_event(struct drm_device *dev,
837 struct drm_connector *connector)
321a1b30
EE		 838{
839 enum drm_connector_status old_status;
840
841 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
842 old_status = connector->status;
843
844 connector->status = connector->funcs->detect(connector, false);
67c347ff
JN		 845 if (old_status == connector->status)
846 return false;
847
848 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
321a1b30
EE		 849 connector->base.id,
850 drm_get_connector_name(connector),
67c347ff
JN		 851 drm_get_connector_status_name(old_status),
852 drm_get_connector_status_name(connector->status));
853
854 return true;
321a1b30
EE		 855}
856
5ca58282
JB		 857/*
858 * Handle hotplug events outside the interrupt handler proper.
859 */
ac4c16c5
EE		 860#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
861
5ca58282
JB		 862static void i915_hotplug_work_func(struct work_struct *work)
863{
864 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
865 hotplug_work);
866 struct drm_device *dev = dev_priv->dev;
c31c4ba3 867 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed
EE		 868 struct intel_connector *intel_connector;
869 struct intel_encoder *intel_encoder;
870 struct drm_connector *connector;
871 unsigned long irqflags;
872 bool hpd_disabled = false;
321a1b30 873 bool changed = false;
142e2398 874 u32 hpd_event_bits;
4ef69c7a 875
52d7eced
DV		 876 /* HPD irq before everything is fully set up. */
877 if (!dev_priv->enable_hotplug_processing)
878 return;
879
a65e34c7 880 mutex_lock(&mode_config->mutex);
e67189ab
JB		 881 DRM_DEBUG_KMS("running encoder hotplug functions\n");
882
cd569aed 883 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
142e2398
EE		 884
885 hpd_event_bits = dev_priv->hpd_event_bits;
886 dev_priv->hpd_event_bits = 0;
cd569aed
EE		 887 list_for_each_entry(connector, &mode_config->connector_list, head) {
888 intel_connector = to_intel_connector(connector);
889 intel_encoder = intel_connector->encoder;
890 if (intel_encoder->hpd_pin > HPD_NONE &&
891 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
892 connector->polled == DRM_CONNECTOR_POLL_HPD) {
893 DRM_INFO("HPD interrupt storm detected on connector %s: "
894 "switching from hotplug detection to polling\n",
895 drm_get_connector_name(connector));
896 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
897 connector->polled = DRM_CONNECTOR_POLL_CONNECT
898 | DRM_CONNECTOR_POLL_DISCONNECT;
899 hpd_disabled = true;
900 }
142e2398
EE		 901 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
902 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
903 drm_get_connector_name(connector), intel_encoder->hpd_pin);
904 }
cd569aed
EE		 905 }
906 /* if there were no outputs to poll, poll was disabled,
907 * therefore make sure it's enabled when disabling HPD on
908 * some connectors */
ac4c16c5 909 if (hpd_disabled) {
cd569aed 910 drm_kms_helper_poll_enable(dev);
ac4c16c5
EE		 911 mod_timer(&dev_priv->hotplug_reenable_timer,
912 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
913 }
cd569aed
EE		 914
915 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
916
321a1b30
EE		 917 list_for_each_entry(connector, &mode_config->connector_list, head) {
918 intel_connector = to_intel_connector(connector);
919 intel_encoder = intel_connector->encoder;
920 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
921 if (intel_encoder->hot_plug)
922 intel_encoder->hot_plug(intel_encoder);
923 if (intel_hpd_irq_event(dev, connector))
924 changed = true;
925 }
926 }
40ee3381
KP		 927 mutex_unlock(&mode_config->mutex);
928
321a1b30
EE		 929 if (changed)
930 drm_kms_helper_hotplug_event(dev);
5ca58282
JB		 931}
932
3ca1cced
VS		 933static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv)
934{
935 del_timer_sync(&dev_priv->hotplug_reenable_timer);
936}
937
d0ecd7e2 938static void ironlake_rps_change_irq_handler(struct drm_device *dev)
f97108d1
JB		 939{
940 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 941 u32 busy_up, busy_down, max_avg, min_avg;
9270388e 942 u8 new_delay;
9270388e 943
d0ecd7e2 944 spin_lock(&mchdev_lock);
f97108d1 945
73edd18f
DV		 946 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
947
20e4d407 948 new_delay = dev_priv->ips.cur_delay;
9270388e 949
7648fa99 950 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 951 busy_up = I915_READ(RCPREVBSYTUPAVG);
952 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 953 max_avg = I915_READ(RCBMAXAVG);
954 min_avg = I915_READ(RCBMINAVG);
955
956 /* Handle RCS change request from hw */
b5b72e89 957 if (busy_up > max_avg) {
20e4d407
DV		 958 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
959 new_delay = dev_priv->ips.cur_delay - 1;
960 if (new_delay < dev_priv->ips.max_delay)
961 new_delay = dev_priv->ips.max_delay;
b5b72e89 962 } else if (busy_down < min_avg) {
20e4d407
DV		 963 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
964 new_delay = dev_priv->ips.cur_delay + 1;
965 if (new_delay > dev_priv->ips.min_delay)
966 new_delay = dev_priv->ips.min_delay;
f97108d1
JB		 967 }
968
7648fa99 969 if (ironlake_set_drps(dev, new_delay))
20e4d407 970 dev_priv->ips.cur_delay = new_delay;
f97108d1 971
d0ecd7e2 972 spin_unlock(&mchdev_lock);
9270388e 973
f97108d1
JB		 974 return;
975}
976
549f7365
CW		 977static void notify_ring(struct drm_device *dev,
978 struct intel_ring_buffer *ring)
979{
475553de
CW		 980 if (ring->obj == NULL)
981 return;
982
814e9b57 983 trace_i915_gem_request_complete(ring);
9862e600 984
549f7365 985 wake_up_all(&ring->irq_queue);
10cd45b6 986 i915_queue_hangcheck(dev);
549f7365
CW		 987}
988
76c3552f 989void gen6_set_pm_mask(struct drm_i915_private *dev_priv,
27544369
D		 990 u32 pm_iir, int new_delay)
991{
992 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
993 if (new_delay >= dev_priv->rps.max_delay) {
994 /* Mask UP THRESHOLD Interrupts */
995 I915_WRITE(GEN6_PMINTRMSK,
996 I915_READ(GEN6_PMINTRMSK) |
997 GEN6_PM_RP_UP_THRESHOLD);
998 dev_priv->rps.rp_up_masked = true;
999 }
1000 if (dev_priv->rps.rp_down_masked) {
1001 /* UnMask DOWN THRESHOLD Interrupts */
1002 I915_WRITE(GEN6_PMINTRMSK,
1003 I915_READ(GEN6_PMINTRMSK) &
1004 ~GEN6_PM_RP_DOWN_THRESHOLD);
1005 dev_priv->rps.rp_down_masked = false;
1006 }
1007 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1008 if (new_delay <= dev_priv->rps.min_delay) {
1009 /* Mask DOWN THRESHOLD Interrupts */
1010 I915_WRITE(GEN6_PMINTRMSK,
1011 I915_READ(GEN6_PMINTRMSK) |
1012 GEN6_PM_RP_DOWN_THRESHOLD);
1013 dev_priv->rps.rp_down_masked = true;
1014 }
1015
1016 if (dev_priv->rps.rp_up_masked) {
1017 /* UnMask UP THRESHOLD Interrupts */
1018 I915_WRITE(GEN6_PMINTRMSK,
1019 I915_READ(GEN6_PMINTRMSK) &
1020 ~GEN6_PM_RP_UP_THRESHOLD);
1021 dev_priv->rps.rp_up_masked = false;
1022 }
1023 }
1024}
1025
4912d041 1026static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 1027{
4912d041 1028 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
c6a828d3 1029 rps.work);
edbfdb45 1030 u32 pm_iir;
dd75fdc8 1031 int new_delay, adj;
4912d041 1032
59cdb63d 1033 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3
DV		 1034 pm_iir = dev_priv->rps.pm_iir;
1035 dev_priv->rps.pm_iir = 0;
4848405c 1036 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
edbfdb45 1037 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
59cdb63d 1038 spin_unlock_irq(&dev_priv->irq_lock);
3b8d8d91 1039
60611c13
PZ		 1040 /* Make sure we didn't queue anything we're not going to process. */
1041 WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS);
1042
4848405c 1043 if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
3b8d8d91
JB		 1044 return;
1045
4fc688ce 1046 mutex_lock(&dev_priv->rps.hw_lock);
7b9e0ae6 1047
dd75fdc8 1048 adj = dev_priv->rps.last_adj;
7425034a 1049 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
dd75fdc8
CW		 1050 if (adj > 0)
1051 adj *= 2;
1052 else
1053 adj = 1;
1054 new_delay = dev_priv->rps.cur_delay + adj;
7425034a
VS		 1055
1056 /*
1057 * For better performance, jump directly
1058 * to RPe if we're below it.
1059 */
dd75fdc8
CW		 1060 if (new_delay < dev_priv->rps.rpe_delay)
1061 new_delay = dev_priv->rps.rpe_delay;
1062 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1063 if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
7425034a 1064 new_delay = dev_priv->rps.rpe_delay;
dd75fdc8
CW		 1065 else
1066 new_delay = dev_priv->rps.min_delay;
1067 adj = 0;
1068 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1069 if (adj < 0)
1070 adj *= 2;
1071 else
1072 adj = -1;
1073 new_delay = dev_priv->rps.cur_delay + adj;
1074 } else { /* unknown event */
1075 new_delay = dev_priv->rps.cur_delay;
1076 }
3b8d8d91 1077
79249636
BW		 1078 /* sysfs frequency interfaces may have snuck in while servicing the
1079 * interrupt
1080 */
1272e7b8
VS		 1081 new_delay = clamp_t(int, new_delay,
1082 dev_priv->rps.min_delay, dev_priv->rps.max_delay);
27544369
D		 1083
1084 gen6_set_pm_mask(dev_priv, pm_iir, new_delay);
dd75fdc8
CW		 1085 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay;
1086
1087 if (IS_VALLEYVIEW(dev_priv->dev))
1088 valleyview_set_rps(dev_priv->dev, new_delay);
1089 else
1090 gen6_set_rps(dev_priv->dev, new_delay);
3b8d8d91 1091
4fc688ce 1092 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91
JB		 1093}
1094
e3689190
BW		 1095
1096/**
1097 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1098 * occurred.
1099 * @work: workqueue struct
1100 *
1101 * Doesn't actually do anything except notify userspace. As a consequence of
1102 * this event, userspace should try to remap the bad rows since statistically
1103 * it is likely the same row is more likely to go bad again.
1104 */
1105static void ivybridge_parity_work(struct work_struct *work)
1106{
1107 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
a4da4fa4 1108 l3_parity.error_work);
e3689190 1109 u32 error_status, row, bank, subbank;
35a85ac6 1110 char *parity_event[6];
e3689190
BW		 1111 uint32_t misccpctl;
1112 unsigned long flags;
35a85ac6 1113 uint8_t slice = 0;
e3689190
BW		 1114
1115 /* We must turn off DOP level clock gating to access the L3 registers.
1116 * In order to prevent a get/put style interface, acquire struct mutex
1117 * any time we access those registers.
1118 */
1119 mutex_lock(&dev_priv->dev->struct_mutex);
1120
35a85ac6
BW		 1121 /* If we've screwed up tracking, just let the interrupt fire again */
1122 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1123 goto out;
1124
e3689190
BW		 1125 misccpctl = I915_READ(GEN7_MISCCPCTL);
1126 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1127 POSTING_READ(GEN7_MISCCPCTL);
1128
35a85ac6
BW		 1129 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1130 u32 reg;
e3689190 1131
35a85ac6
BW		 1132 slice--;
1133 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1134 break;
e3689190 1135
35a85ac6 1136 dev_priv->l3_parity.which_slice &= ~(1<<slice);
e3689190 1137
35a85ac6 1138 reg = GEN7_L3CDERRST1 + (slice * 0x200);
e3689190 1139
35a85ac6
BW		 1140 error_status = I915_READ(reg);
1141 row = GEN7_PARITY_ERROR_ROW(error_status);
1142 bank = GEN7_PARITY_ERROR_BANK(error_status);
1143 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1144
1145 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1146 POSTING_READ(reg);
1147
1148 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1149 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1150 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1151 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1152 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1153 parity_event[5] = NULL;
1154
5bdebb18 1155 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
35a85ac6 1156 KOBJ_CHANGE, parity_event);
e3689190 1157
35a85ac6
BW		 1158 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1159 slice, row, bank, subbank);
e3689190 1160
35a85ac6
BW		 1161 kfree(parity_event[4]);
1162 kfree(parity_event[3]);
1163 kfree(parity_event[2]);
1164 kfree(parity_event[1]);
1165 }
e3689190 1166
35a85ac6 1167 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
e3689190 1168
35a85ac6
BW		 1169out:
1170 WARN_ON(dev_priv->l3_parity.which_slice);
1171 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1172 ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1173 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1174
1175 mutex_unlock(&dev_priv->dev->struct_mutex);
e3689190
BW		 1176}
1177
35a85ac6 1178static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
e3689190
BW		 1179{
1180 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e3689190 1181
040d2baa 1182 if (!HAS_L3_DPF(dev))
e3689190
BW		 1183 return;
1184
d0ecd7e2 1185 spin_lock(&dev_priv->irq_lock);
35a85ac6 1186 ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
d0ecd7e2 1187 spin_unlock(&dev_priv->irq_lock);
e3689190 1188
35a85ac6
BW		 1189 iir &= GT_PARITY_ERROR(dev);
1190 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1191 dev_priv->l3_parity.which_slice |= 1 << 1;
1192
1193 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1194 dev_priv->l3_parity.which_slice |= 1 << 0;
1195
a4da4fa4 1196 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
e3689190
BW		 1197}
1198
f1af8fc1
PZ		 1199static void ilk_gt_irq_handler(struct drm_device *dev,
1200 struct drm_i915_private *dev_priv,
1201 u32 gt_iir)
1202{
1203 if (gt_iir &
1204 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1205 notify_ring(dev, &dev_priv->ring[RCS]);
1206 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1207 notify_ring(dev, &dev_priv->ring[VCS]);
1208}
1209
e7b4c6b1
DV		 1210static void snb_gt_irq_handler(struct drm_device *dev,
1211 struct drm_i915_private *dev_priv,
1212 u32 gt_iir)
1213{
1214
cc609d5d
BW		 1215 if (gt_iir &
1216 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
e7b4c6b1 1217 notify_ring(dev, &dev_priv->ring[RCS]);
cc609d5d 1218 if (gt_iir & GT_BSD_USER_INTERRUPT)
e7b4c6b1 1219 notify_ring(dev, &dev_priv->ring[VCS]);
cc609d5d 1220 if (gt_iir & GT_BLT_USER_INTERRUPT)
e7b4c6b1
DV		 1221 notify_ring(dev, &dev_priv->ring[BCS]);
1222
cc609d5d
BW		 1223 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1224 GT_BSD_CS_ERROR_INTERRUPT |
1225 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
e7b4c6b1
DV		 1226 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
1227 i915_handle_error(dev, false);
1228 }
e3689190 1229
35a85ac6
BW		 1230 if (gt_iir & GT_PARITY_ERROR(dev))
1231 ivybridge_parity_error_irq_handler(dev, gt_iir);
e7b4c6b1
DV		 1232}
1233
abd58f01
BW		 1234static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1235 struct drm_i915_private *dev_priv,
1236 u32 master_ctl)
1237{
1238 u32 rcs, bcs, vcs;
1239 uint32_t tmp = 0;
1240 irqreturn_t ret = IRQ_NONE;
1241
1242 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1243 tmp = I915_READ(GEN8_GT_IIR(0));
1244 if (tmp) {
1245 ret = IRQ_HANDLED;
1246 rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1247 bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1248 if (rcs & GT_RENDER_USER_INTERRUPT)
1249 notify_ring(dev, &dev_priv->ring[RCS]);
1250 if (bcs & GT_RENDER_USER_INTERRUPT)
1251 notify_ring(dev, &dev_priv->ring[BCS]);
1252 I915_WRITE(GEN8_GT_IIR(0), tmp);
1253 } else
1254 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1255 }
1256
1257 if (master_ctl & GEN8_GT_VCS1_IRQ) {
1258 tmp = I915_READ(GEN8_GT_IIR(1));
1259 if (tmp) {
1260 ret = IRQ_HANDLED;
1261 vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1262 if (vcs & GT_RENDER_USER_INTERRUPT)
1263 notify_ring(dev, &dev_priv->ring[VCS]);
1264 I915_WRITE(GEN8_GT_IIR(1), tmp);
1265 } else
1266 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1267 }
1268
1269 if (master_ctl & GEN8_GT_VECS_IRQ) {
1270 tmp = I915_READ(GEN8_GT_IIR(3));
1271 if (tmp) {
1272 ret = IRQ_HANDLED;
1273 vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1274 if (vcs & GT_RENDER_USER_INTERRUPT)
1275 notify_ring(dev, &dev_priv->ring[VECS]);
1276 I915_WRITE(GEN8_GT_IIR(3), tmp);
1277 } else
1278 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1279 }
1280
1281 return ret;
1282}
1283
b543fb04
EE		 1284#define HPD_STORM_DETECT_PERIOD 1000
1285#define HPD_STORM_THRESHOLD 5
1286
10a504de 1287static inline void intel_hpd_irq_handler(struct drm_device *dev,
22062dba
DV		 1288 u32 hotplug_trigger,
1289 const u32 *hpd)
b543fb04
EE		 1290{
1291 drm_i915_private_t *dev_priv = dev->dev_private;
b543fb04 1292 int i;
10a504de 1293 bool storm_detected = false;
b543fb04 1294
91d131d2
DV		 1295 if (!hotplug_trigger)
1296 return;
1297
cc9bd499
ID		 1298 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1299 hotplug_trigger);
1300
b5ea2d56 1301 spin_lock(&dev_priv->irq_lock);
b543fb04 1302 for (i = 1; i < HPD_NUM_PINS; i++) {
821450c6 1303
3432087e 1304 WARN_ONCE(hpd[i] & hotplug_trigger &&
8b5565b8 1305 dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED,
cba1c073
CW		 1306 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1307 hotplug_trigger, i, hpd[i]);
b8f102e8 1308
b543fb04
EE		 1309 if (!(hpd[i] & hotplug_trigger) ||
1310 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1311 continue;
1312
bc5ead8c 1313 dev_priv->hpd_event_bits |= (1 << i);
b543fb04
EE		 1314 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1315 dev_priv->hpd_stats[i].hpd_last_jiffies
1316 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1317 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1318 dev_priv->hpd_stats[i].hpd_cnt = 0;
b8f102e8 1319 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
b543fb04
EE		 1320 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1321 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
142e2398 1322 dev_priv->hpd_event_bits &= ~(1 << i);
b543fb04 1323 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
10a504de 1324 storm_detected = true;
b543fb04
EE		 1325 } else {
1326 dev_priv->hpd_stats[i].hpd_cnt++;
b8f102e8
EE		 1327 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1328 dev_priv->hpd_stats[i].hpd_cnt);
b543fb04
EE		 1329 }
1330 }
1331
10a504de
DV		 1332 if (storm_detected)
1333 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 1334 spin_unlock(&dev_priv->irq_lock);
5876fa0d 1335
645416f5
DV		 1336 /*
1337 * Our hotplug handler can grab modeset locks (by calling down into the
1338 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1339 * queue for otherwise the flush_work in the pageflip code will
1340 * deadlock.
1341 */
1342 schedule_work(&dev_priv->hotplug_work);
b543fb04
EE		 1343}
1344
515ac2bb
DV		 1345static void gmbus_irq_handler(struct drm_device *dev)
1346{
28c70f16
DV		 1347 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1348
28c70f16 1349 wake_up_all(&dev_priv->gmbus_wait_queue);
515ac2bb
DV		 1350}
1351
ce99c256
DV		 1352static void dp_aux_irq_handler(struct drm_device *dev)
1353{
9ee32fea
DV		 1354 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1355
9ee32fea 1356 wake_up_all(&dev_priv->gmbus_wait_queue);
ce99c256
DV		 1357}
1358
8bf1e9f1 1359#if defined(CONFIG_DEBUG_FS)
277de95e
DV		 1360static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1361 uint32_t crc0, uint32_t crc1,
1362 uint32_t crc2, uint32_t crc3,
1363 uint32_t crc4)
8bf1e9f1
SH		 1364{
1365 struct drm_i915_private *dev_priv = dev->dev_private;
1366 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1367 struct intel_pipe_crc_entry *entry;
ac2300d4 1368 int head, tail;
b2c88f5b 1369
d538bbdf
DL		 1370 spin_lock(&pipe_crc->lock);
1371
0c912c79 1372 if (!pipe_crc->entries) {
d538bbdf 1373 spin_unlock(&pipe_crc->lock);
0c912c79
DL		 1374 DRM_ERROR("spurious interrupt\n");
1375 return;
1376 }
1377
d538bbdf
DL		 1378 head = pipe_crc->head;
1379 tail = pipe_crc->tail;
b2c88f5b
DL		 1380
1381 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
d538bbdf 1382 spin_unlock(&pipe_crc->lock);
b2c88f5b
DL		 1383 DRM_ERROR("CRC buffer overflowing\n");
1384 return;
1385 }
1386
1387 entry = &pipe_crc->entries[head];
8bf1e9f1 1388
8bc5e955 1389 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
eba94eb9
DV		 1390 entry->crc[0] = crc0;
1391 entry->crc[1] = crc1;
1392 entry->crc[2] = crc2;
1393 entry->crc[3] = crc3;
1394 entry->crc[4] = crc4;
b2c88f5b
DL		 1395
1396 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
d538bbdf
DL		 1397 pipe_crc->head = head;
1398
1399 spin_unlock(&pipe_crc->lock);
07144428
DL		 1400
1401 wake_up_interruptible(&pipe_crc->wq);
8bf1e9f1 1402}
277de95e
DV		 1403#else
1404static inline void
1405display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1406 uint32_t crc0, uint32_t crc1,
1407 uint32_t crc2, uint32_t crc3,
1408 uint32_t crc4) {}
1409#endif
1410
eba94eb9 1411
277de95e 1412static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
5a69b89f
DV		 1413{
1414 struct drm_i915_private *dev_priv = dev->dev_private;
1415
277de95e
DV		 1416 display_pipe_crc_irq_handler(dev, pipe,
1417 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1418 0, 0, 0, 0);
5a69b89f
DV		 1419}
1420
277de95e 1421static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
eba94eb9
DV		 1422{
1423 struct drm_i915_private *dev_priv = dev->dev_private;
1424
277de95e
DV		 1425 display_pipe_crc_irq_handler(dev, pipe,
1426 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1427 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1428 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1429 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1430 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
eba94eb9 1431}
5b3a856b 1432
277de95e 1433static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
5b3a856b
DV		 1434{
1435 struct drm_i915_private *dev_priv = dev->dev_private;
0b5c5ed0
DV		 1436 uint32_t res1, res2;
1437
1438 if (INTEL_INFO(dev)->gen >= 3)
1439 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1440 else
1441 res1 = 0;
1442
1443 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1444 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1445 else
1446 res2 = 0;
5b3a856b 1447
277de95e
DV		 1448 display_pipe_crc_irq_handler(dev, pipe,
1449 I915_READ(PIPE_CRC_RES_RED(pipe)),
1450 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1451 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1452 res1, res2);
5b3a856b 1453}
8bf1e9f1 1454
1403c0d4
PZ		 1455/* The RPS events need forcewake, so we add them to a work queue and mask their
1456 * IMR bits until the work is done. Other interrupts can be processed without
1457 * the work queue. */
1458static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
baf02a1f 1459{
41a05a3a 1460 if (pm_iir & GEN6_PM_RPS_EVENTS) {
59cdb63d 1461 spin_lock(&dev_priv->irq_lock);
41a05a3a 1462 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
4d3b3d5f 1463 snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS);
59cdb63d 1464 spin_unlock(&dev_priv->irq_lock);
2adbee62
DV		 1465
1466 queue_work(dev_priv->wq, &dev_priv->rps.work);
baf02a1f 1467 }
baf02a1f 1468
1403c0d4
PZ		 1469 if (HAS_VEBOX(dev_priv->dev)) {
1470 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1471 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
12638c57 1472
1403c0d4
PZ		 1473 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1474 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
1475 i915_handle_error(dev_priv->dev, false);
1476 }
12638c57 1477 }
baf02a1f
BW		 1478}
1479
c1874ed7
ID		 1480static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1481{
1482 struct drm_i915_private *dev_priv = dev->dev_private;
1483 u32 pipe_stats[I915_MAX_PIPES];
1484 unsigned long irqflags;
1485 int pipe;
1486
1487 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1488 for_each_pipe(pipe) {
1489 int reg = PIPESTAT(pipe);
1490 pipe_stats[pipe] = I915_READ(reg);
1491
1492 /*
1493 * Clear the PIPE*STAT regs before the IIR
1494 */
1495 if (pipe_stats[pipe] & 0x8000ffff)
1496 I915_WRITE(reg, pipe_stats[pipe]);
1497 }
1498 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1499
1500 for_each_pipe(pipe) {
1501 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1502 drm_handle_vblank(dev, pipe);
1503
1504 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
1505 intel_prepare_page_flip(dev, pipe);
1506 intel_finish_page_flip(dev, pipe);
1507 }
1508
1509 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1510 i9xx_pipe_crc_irq_handler(dev, pipe);
1511
1512 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
1513 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1514 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
1515 }
1516
1517 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1518 gmbus_irq_handler(dev);
1519}
1520
ff1f525e 1521static irqreturn_t valleyview_irq_handler(int irq, void *arg)
7e231dbe
JB		 1522{
1523 struct drm_device *dev = (struct drm_device *) arg;
1524 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1525 u32 iir, gt_iir, pm_iir;
1526 irqreturn_t ret = IRQ_NONE;
7e231dbe 1527
7e231dbe
JB		 1528 while (true) {
1529 iir = I915_READ(VLV_IIR);
1530 gt_iir = I915_READ(GTIIR);
1531 pm_iir = I915_READ(GEN6_PMIIR);
1532
1533 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1534 goto out;
1535
1536 ret = IRQ_HANDLED;
1537
e7b4c6b1 1538 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe 1539
c1874ed7 1540 valleyview_pipestat_irq_handler(dev, iir);
31acc7f5 1541
7e231dbe
JB		 1542 /* Consume port. Then clear IIR or we'll miss events */
1543 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1544 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04 1545 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
7e231dbe 1546
91d131d2
DV		 1547 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1548
4aeebd74
DV		 1549 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1550 dp_aux_irq_handler(dev);
1551
7e231dbe
JB		 1552 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1553 I915_READ(PORT_HOTPLUG_STAT);
1554 }
1555
7e231dbe 1556
60611c13 1557 if (pm_iir)
d0ecd7e2 1558 gen6_rps_irq_handler(dev_priv, pm_iir);
7e231dbe
JB		 1559
1560 I915_WRITE(GTIIR, gt_iir);
1561 I915_WRITE(GEN6_PMIIR, pm_iir);
1562 I915_WRITE(VLV_IIR, iir);
1563 }
1564
1565out:
1566 return ret;
1567}
1568
23e81d69 1569static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 1570{
1571 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 1572 int pipe;
b543fb04 1573 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
776ad806 1574
91d131d2
DV		 1575 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1576
cfc33bf7
VS		 1577 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1578 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1579 SDE_AUDIO_POWER_SHIFT);
776ad806 1580 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
cfc33bf7
VS		 1581 port_name(port));
1582 }
776ad806 1583
ce99c256
DV		 1584 if (pch_iir & SDE_AUX_MASK)
1585 dp_aux_irq_handler(dev);
1586
776ad806 1587 if (pch_iir & SDE_GMBUS)
515ac2bb 1588 gmbus_irq_handler(dev);
776ad806
JB		 1589
1590 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1591 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1592
1593 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1594 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1595
1596 if (pch_iir & SDE_POISON)
1597 DRM_ERROR("PCH poison interrupt\n");
1598
9db4a9c7
JB		 1599 if (pch_iir & SDE_FDI_MASK)
1600 for_each_pipe(pipe)
1601 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1602 pipe_name(pipe),
1603 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 1604
1605 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1606 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1607
1608 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1609 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1610
776ad806 1611 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
8664281b
PZ		 1612 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1613 false))
fc2c807b 1614 DRM_ERROR("PCH transcoder A FIFO underrun\n");
8664281b
PZ		 1615
1616 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1617 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1618 false))
fc2c807b 1619 DRM_ERROR("PCH transcoder B FIFO underrun\n");
8664281b
PZ		 1620}
1621
1622static void ivb_err_int_handler(struct drm_device *dev)
1623{
1624 struct drm_i915_private *dev_priv = dev->dev_private;
1625 u32 err_int = I915_READ(GEN7_ERR_INT);
5a69b89f 1626 enum pipe pipe;
8664281b 1627
de032bf4
PZ		 1628 if (err_int & ERR_INT_POISON)
1629 DRM_ERROR("Poison interrupt\n");
1630
5a69b89f
DV		 1631 for_each_pipe(pipe) {
1632 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
1633 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1634 false))
fc2c807b
VS		 1635 DRM_ERROR("Pipe %c FIFO underrun\n",
1636 pipe_name(pipe));
5a69b89f 1637 }
8bf1e9f1 1638
5a69b89f
DV		 1639 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1640 if (IS_IVYBRIDGE(dev))
277de95e 1641 ivb_pipe_crc_irq_handler(dev, pipe);
5a69b89f 1642 else
277de95e 1643 hsw_pipe_crc_irq_handler(dev, pipe);
5a69b89f
DV		 1644 }
1645 }
8bf1e9f1 1646
8664281b
PZ		 1647 I915_WRITE(GEN7_ERR_INT, err_int);
1648}
1649
1650static void cpt_serr_int_handler(struct drm_device *dev)
1651{
1652 struct drm_i915_private *dev_priv = dev->dev_private;
1653 u32 serr_int = I915_READ(SERR_INT);
1654
de032bf4
PZ		 1655 if (serr_int & SERR_INT_POISON)
1656 DRM_ERROR("PCH poison interrupt\n");
1657
8664281b
PZ		 1658 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1659 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1660 false))
fc2c807b 1661 DRM_ERROR("PCH transcoder A FIFO underrun\n");
8664281b
PZ		 1662
1663 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1664 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1665 false))
fc2c807b 1666 DRM_ERROR("PCH transcoder B FIFO underrun\n");
8664281b
PZ		 1667
1668 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1669 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1670 false))
fc2c807b 1671 DRM_ERROR("PCH transcoder C FIFO underrun\n");
8664281b
PZ		 1672
1673 I915_WRITE(SERR_INT, serr_int);
776ad806
JB		 1674}
1675
23e81d69
AJ		 1676static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1677{
1678 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1679 int pipe;
b543fb04 1680 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
23e81d69 1681
91d131d2
DV		 1682 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1683
cfc33bf7
VS		 1684 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1685 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1686 SDE_AUDIO_POWER_SHIFT_CPT);
1687 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1688 port_name(port));
1689 }
23e81d69
AJ		 1690
1691 if (pch_iir & SDE_AUX_MASK_CPT)
ce99c256 1692 dp_aux_irq_handler(dev);
23e81d69
AJ		 1693
1694 if (pch_iir & SDE_GMBUS_CPT)
515ac2bb 1695 gmbus_irq_handler(dev);
23e81d69
AJ		 1696
1697 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1698 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1699
1700 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1701 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1702
1703 if (pch_iir & SDE_FDI_MASK_CPT)
1704 for_each_pipe(pipe)
1705 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1706 pipe_name(pipe),
1707 I915_READ(FDI_RX_IIR(pipe)));
8664281b
PZ		 1708
1709 if (pch_iir & SDE_ERROR_CPT)
1710 cpt_serr_int_handler(dev);
23e81d69
AJ		 1711}
1712
c008bc6e
PZ		 1713static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1714{
1715 struct drm_i915_private *dev_priv = dev->dev_private;
40da17c2 1716 enum pipe pipe;
c008bc6e
PZ		 1717
1718 if (de_iir & DE_AUX_CHANNEL_A)
1719 dp_aux_irq_handler(dev);
1720
1721 if (de_iir & DE_GSE)
1722 intel_opregion_asle_intr(dev);
1723
c008bc6e
PZ		 1724 if (de_iir & DE_POISON)
1725 DRM_ERROR("Poison interrupt\n");
1726
40da17c2
DV		 1727 for_each_pipe(pipe) {
1728 if (de_iir & DE_PIPE_VBLANK(pipe))
1729 drm_handle_vblank(dev, pipe);
5b3a856b 1730
40da17c2
DV		 1731 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
1732 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
fc2c807b
VS		 1733 DRM_ERROR("Pipe %c FIFO underrun\n",
1734 pipe_name(pipe));
5b3a856b 1735
40da17c2
DV		 1736 if (de_iir & DE_PIPE_CRC_DONE(pipe))
1737 i9xx_pipe_crc_irq_handler(dev, pipe);
c008bc6e 1738
40da17c2
DV		 1739 /* plane/pipes map 1:1 on ilk+ */
1740 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
1741 intel_prepare_page_flip(dev, pipe);
1742 intel_finish_page_flip_plane(dev, pipe);
1743 }
c008bc6e
PZ		 1744 }
1745
1746 /* check event from PCH */
1747 if (de_iir & DE_PCH_EVENT) {
1748 u32 pch_iir = I915_READ(SDEIIR);
1749
1750 if (HAS_PCH_CPT(dev))
1751 cpt_irq_handler(dev, pch_iir);
1752 else
1753 ibx_irq_handler(dev, pch_iir);
1754
1755 /* should clear PCH hotplug event before clear CPU irq */
1756 I915_WRITE(SDEIIR, pch_iir);
1757 }
1758
1759 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1760 ironlake_rps_change_irq_handler(dev);
1761}
1762
9719fb98
PZ		 1763static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
1764{
1765 struct drm_i915_private *dev_priv = dev->dev_private;
3b6c42e8 1766 enum pipe i;
9719fb98
PZ		 1767
1768 if (de_iir & DE_ERR_INT_IVB)
1769 ivb_err_int_handler(dev);
1770
1771 if (de_iir & DE_AUX_CHANNEL_A_IVB)
1772 dp_aux_irq_handler(dev);
1773
1774 if (de_iir & DE_GSE_IVB)
1775 intel_opregion_asle_intr(dev);
1776
3b6c42e8 1777 for_each_pipe(i) {
40da17c2 1778 if (de_iir & (DE_PIPE_VBLANK_IVB(i)))
9719fb98 1779 drm_handle_vblank(dev, i);
40da17c2
DV		 1780
1781 /* plane/pipes map 1:1 on ilk+ */
1782 if (de_iir & DE_PLANE_FLIP_DONE_IVB(i)) {
9719fb98
PZ		 1783 intel_prepare_page_flip(dev, i);
1784 intel_finish_page_flip_plane(dev, i);
1785 }
1786 }
1787
1788 /* check event from PCH */
1789 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1790 u32 pch_iir = I915_READ(SDEIIR);
1791
1792 cpt_irq_handler(dev, pch_iir);
1793
1794 /* clear PCH hotplug event before clear CPU irq */
1795 I915_WRITE(SDEIIR, pch_iir);
1796 }
1797}
1798
f1af8fc1 1799static irqreturn_t ironlake_irq_handler(int irq, void *arg)
b1f14ad0
JB		 1800{
1801 struct drm_device *dev = (struct drm_device *) arg;
1802 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
f1af8fc1 1803 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
0e43406b 1804 irqreturn_t ret = IRQ_NONE;
b1f14ad0 1805
8664281b
PZ		 1806 /* We get interrupts on unclaimed registers, so check for this before we
1807 * do any I915_{READ,WRITE}. */
907b28c5 1808 intel_uncore_check_errors(dev);
8664281b 1809
b1f14ad0
JB		 1810 /* disable master interrupt before clearing iir */
1811 de_ier = I915_READ(DEIER);
1812 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
23a78516 1813 POSTING_READ(DEIER);
b1f14ad0 1814
44498aea
PZ		 1815 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1816 * interrupts will will be stored on its back queue, and then we'll be
1817 * able to process them after we restore SDEIER (as soon as we restore
1818 * it, we'll get an interrupt if SDEIIR still has something to process
1819 * due to its back queue). */
ab5c608b
BW		 1820 if (!HAS_PCH_NOP(dev)) {
1821 sde_ier = I915_READ(SDEIER);
1822 I915_WRITE(SDEIER, 0);
1823 POSTING_READ(SDEIER);
1824 }
44498aea 1825
b1f14ad0 1826 gt_iir = I915_READ(GTIIR);
0e43406b 1827 if (gt_iir) {
d8fc8a47 1828 if (INTEL_INFO(dev)->gen >= 6)
f1af8fc1 1829 snb_gt_irq_handler(dev, dev_priv, gt_iir);
d8fc8a47
PZ		 1830 else
1831 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
0e43406b
CW		 1832 I915_WRITE(GTIIR, gt_iir);
1833 ret = IRQ_HANDLED;
b1f14ad0
JB		 1834 }
1835
0e43406b
CW		 1836 de_iir = I915_READ(DEIIR);
1837 if (de_iir) {
f1af8fc1
PZ		 1838 if (INTEL_INFO(dev)->gen >= 7)
1839 ivb_display_irq_handler(dev, de_iir);
1840 else
1841 ilk_display_irq_handler(dev, de_iir);
0e43406b
CW		 1842 I915_WRITE(DEIIR, de_iir);
1843 ret = IRQ_HANDLED;
b1f14ad0
JB		 1844 }
1845
f1af8fc1
PZ		 1846 if (INTEL_INFO(dev)->gen >= 6) {
1847 u32 pm_iir = I915_READ(GEN6_PMIIR);
1848 if (pm_iir) {
1403c0d4 1849 gen6_rps_irq_handler(dev_priv, pm_iir);
f1af8fc1
PZ		 1850 I915_WRITE(GEN6_PMIIR, pm_iir);
1851 ret = IRQ_HANDLED;
1852 }
0e43406b 1853 }
b1f14ad0 1854
b1f14ad0
JB		 1855 I915_WRITE(DEIER, de_ier);
1856 POSTING_READ(DEIER);
ab5c608b
BW		 1857 if (!HAS_PCH_NOP(dev)) {
1858 I915_WRITE(SDEIER, sde_ier);
1859 POSTING_READ(SDEIER);
1860 }
b1f14ad0
JB		 1861
1862 return ret;
1863}
1864
abd58f01
BW		 1865static irqreturn_t gen8_irq_handler(int irq, void *arg)
1866{
1867 struct drm_device *dev = arg;
1868 struct drm_i915_private *dev_priv = dev->dev_private;
1869 u32 master_ctl;
1870 irqreturn_t ret = IRQ_NONE;
1871 uint32_t tmp = 0;
c42664cc 1872 enum pipe pipe;
abd58f01 1873
abd58f01
BW		 1874 master_ctl = I915_READ(GEN8_MASTER_IRQ);
1875 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
1876 if (!master_ctl)
1877 return IRQ_NONE;
1878
1879 I915_WRITE(GEN8_MASTER_IRQ, 0);
1880 POSTING_READ(GEN8_MASTER_IRQ);
1881
1882 ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
1883
1884 if (master_ctl & GEN8_DE_MISC_IRQ) {
1885 tmp = I915_READ(GEN8_DE_MISC_IIR);
1886 if (tmp & GEN8_DE_MISC_GSE)
1887 intel_opregion_asle_intr(dev);
1888 else if (tmp)
1889 DRM_ERROR("Unexpected DE Misc interrupt\n");
1890 else
1891 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
1892
1893 if (tmp) {
1894 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
1895 ret = IRQ_HANDLED;
1896 }
1897 }
1898
6d766f02
DV		 1899 if (master_ctl & GEN8_DE_PORT_IRQ) {
1900 tmp = I915_READ(GEN8_DE_PORT_IIR);
1901 if (tmp & GEN8_AUX_CHANNEL_A)
1902 dp_aux_irq_handler(dev);
1903 else if (tmp)
1904 DRM_ERROR("Unexpected DE Port interrupt\n");
1905 else
1906 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
1907
1908 if (tmp) {
1909 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
1910 ret = IRQ_HANDLED;
1911 }
1912 }
1913
c42664cc
DV		 1914 for_each_pipe(pipe) {
1915 uint32_t pipe_iir;
abd58f01 1916
c42664cc
DV		 1917 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
1918 continue;
abd58f01 1919
c42664cc
DV		 1920 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
1921 if (pipe_iir & GEN8_PIPE_VBLANK)
1922 drm_handle_vblank(dev, pipe);
abd58f01 1923
c42664cc
DV		 1924 if (pipe_iir & GEN8_PIPE_FLIP_DONE) {
1925 intel_prepare_page_flip(dev, pipe);
1926 intel_finish_page_flip_plane(dev, pipe);
abd58f01 1927 }
c42664cc 1928
0fbe7870
DV		 1929 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
1930 hsw_pipe_crc_irq_handler(dev, pipe);
1931
38d83c96
DV		 1932 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
1933 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1934 false))
fc2c807b
VS		 1935 DRM_ERROR("Pipe %c FIFO underrun\n",
1936 pipe_name(pipe));
38d83c96
DV		 1937 }
1938
30100f2b
DV		 1939 if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
1940 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
1941 pipe_name(pipe),
1942 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
1943 }
c42664cc
DV		 1944
1945 if (pipe_iir) {
1946 ret = IRQ_HANDLED;
1947 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
1948 } else
abd58f01
BW		 1949 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
1950 }
1951
92d03a80
DV		 1952 if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
1953 /*
1954 * FIXME(BDW): Assume for now that the new interrupt handling
1955 * scheme also closed the SDE interrupt handling race we've seen
1956 * on older pch-split platforms. But this needs testing.
1957 */
1958 u32 pch_iir = I915_READ(SDEIIR);
1959
1960 cpt_irq_handler(dev, pch_iir);
1961
1962 if (pch_iir) {
1963 I915_WRITE(SDEIIR, pch_iir);
1964 ret = IRQ_HANDLED;
1965 }
1966 }
1967
abd58f01
BW		 1968 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1969 POSTING_READ(GEN8_MASTER_IRQ);
1970
1971 return ret;
1972}
1973
17e1df07
DV		 1974static void i915_error_wake_up(struct drm_i915_private *dev_priv,
1975 bool reset_completed)
1976{
1977 struct intel_ring_buffer *ring;
1978 int i;
1979
1980 /*
1981 * Notify all waiters for GPU completion events that reset state has
1982 * been changed, and that they need to restart their wait after
1983 * checking for potential errors (and bail out to drop locks if there is
1984 * a gpu reset pending so that i915_error_work_func can acquire them).
1985 */
1986
1987 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
1988 for_each_ring(ring, dev_priv, i)
1989 wake_up_all(&ring->irq_queue);
1990
1991 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
1992 wake_up_all(&dev_priv->pending_flip_queue);
1993
1994 /*
1995 * Signal tasks blocked in i915_gem_wait_for_error that the pending
1996 * reset state is cleared.
1997 */
1998 if (reset_completed)
1999 wake_up_all(&dev_priv->gpu_error.reset_queue);
2000}
2001
8a905236
JB		 2002/**
2003 * i915_error_work_func - do process context error handling work
2004 * @work: work struct
2005 *
2006 * Fire an error uevent so userspace can see that a hang or error
2007 * was detected.
2008 */
2009static void i915_error_work_func(struct work_struct *work)
2010{
1f83fee0
DV		 2011 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
2012 work);
2013 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
2014 gpu_error);
8a905236 2015 struct drm_device *dev = dev_priv->dev;
cce723ed
BW		 2016 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2017 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2018 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
17e1df07 2019 int ret;
8a905236 2020
5bdebb18 2021 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
f316a42c 2022
7db0ba24
DV		 2023 /*
2024 * Note that there's only one work item which does gpu resets, so we
2025 * need not worry about concurrent gpu resets potentially incrementing
2026 * error->reset_counter twice. We only need to take care of another
2027 * racing irq/hangcheck declaring the gpu dead for a second time. A
2028 * quick check for that is good enough: schedule_work ensures the
2029 * correct ordering between hang detection and this work item, and since
2030 * the reset in-progress bit is only ever set by code outside of this
2031 * work we don't need to worry about any other races.
2032 */
2033 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
f803aa55 2034 DRM_DEBUG_DRIVER("resetting chip\n");
5bdebb18 2035 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
7db0ba24 2036 reset_event);
1f83fee0 2037
17e1df07
DV		 2038 /*
2039 * All state reset _must_ be completed before we update the
2040 * reset counter, for otherwise waiters might miss the reset
2041 * pending state and not properly drop locks, resulting in
2042 * deadlocks with the reset work.
2043 */
f69061be
DV		 2044 ret = i915_reset(dev);
2045
17e1df07
DV		 2046 intel_display_handle_reset(dev);
2047
f69061be
DV		 2048 if (ret == 0) {
2049 /*
2050 * After all the gem state is reset, increment the reset
2051 * counter and wake up everyone waiting for the reset to
2052 * complete.
2053 *
2054 * Since unlock operations are a one-sided barrier only,
2055 * we need to insert a barrier here to order any seqno
2056 * updates before
2057 * the counter increment.
2058 */
2059 smp_mb__before_atomic_inc();
2060 atomic_inc(&dev_priv->gpu_error.reset_counter);
2061
5bdebb18 2062 kobject_uevent_env(&dev->primary->kdev->kobj,
f69061be 2063 KOBJ_CHANGE, reset_done_event);
1f83fee0 2064 } else {
2ac0f450 2065 atomic_set_mask(I915_WEDGED, &error->reset_counter);
f316a42c 2066 }
1f83fee0 2067
17e1df07
DV		 2068 /*
2069 * Note: The wake_up also serves as a memory barrier so that
2070 * waiters see the update value of the reset counter atomic_t.
2071 */
2072 i915_error_wake_up(dev_priv, true);
f316a42c 2073 }
8a905236
JB		 2074}
2075
35aed2e6 2076static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 2077{
2078 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 2079 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 2080 u32 eir = I915_READ(EIR);
050ee91f 2081 int pipe, i;
8a905236 2082
35aed2e6
CW		 2083 if (!eir)
2084 return;
8a905236 2085
a70491cc 2086 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 2087
bd9854f9
BW		 2088 i915_get_extra_instdone(dev, instdone);
2089
8a905236
JB		 2090 if (IS_G4X(dev)) {
2091 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2092 u32 ipeir = I915_READ(IPEIR_I965);
2093
a70491cc
JP		 2094 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2095 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 2096 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2097 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 2098 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 2099 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 2100 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 2101 POSTING_READ(IPEIR_I965);
8a905236
JB		 2102 }
2103 if (eir & GM45_ERROR_PAGE_TABLE) {
2104 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 2105 pr_err("page table error\n");
2106 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 2107 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 2108 POSTING_READ(PGTBL_ER);
8a905236
JB		 2109 }
2110 }
2111
a6c45cf0 2112 if (!IS_GEN2(dev)) {
8a905236
JB		 2113 if (eir & I915_ERROR_PAGE_TABLE) {
2114 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 2115 pr_err("page table error\n");
2116 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 2117 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 2118 POSTING_READ(PGTBL_ER);
8a905236
JB		 2119 }
2120 }
2121
2122 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 2123 pr_err("memory refresh error:\n");
9db4a9c7 2124 for_each_pipe(pipe)
a70491cc 2125 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 2126 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 2127 /* pipestat has already been acked */
2128 }
2129 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 2130 pr_err("instruction error\n");
2131 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 2132 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2133 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 2134 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 2135 u32 ipeir = I915_READ(IPEIR);
2136
a70491cc
JP		 2137 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2138 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 2139 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 2140 I915_WRITE(IPEIR, ipeir);
3143a2bf 2141 POSTING_READ(IPEIR);
8a905236
JB		 2142 } else {
2143 u32 ipeir = I915_READ(IPEIR_I965);
2144
a70491cc
JP		 2145 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2146 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 2147 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 2148 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 2149 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 2150 POSTING_READ(IPEIR_I965);
8a905236
JB		 2151 }
2152 }
2153
2154 I915_WRITE(EIR, eir);
3143a2bf 2155 POSTING_READ(EIR);
8a905236
JB		 2156 eir = I915_READ(EIR);
2157 if (eir) {
2158 /*
2159 * some errors might have become stuck,
2160 * mask them.
2161 */
2162 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2163 I915_WRITE(EMR, I915_READ(EMR) | eir);
2164 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2165 }
35aed2e6
CW		 2166}
2167
2168/**
2169 * i915_handle_error - handle an error interrupt
2170 * @dev: drm device
2171 *
2172 * Do some basic checking of regsiter state at error interrupt time and
2173 * dump it to the syslog. Also call i915_capture_error_state() to make
2174 * sure we get a record and make it available in debugfs. Fire a uevent
2175 * so userspace knows something bad happened (should trigger collection
2176 * of a ring dump etc.).
2177 */
527f9e90 2178void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 2179{
2180 struct drm_i915_private *dev_priv = dev->dev_private;
2181
2182 i915_capture_error_state(dev);
2183 i915_report_and_clear_eir(dev);
8a905236 2184
ba1234d1 2185 if (wedged) {
f69061be
DV		 2186 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2187 &dev_priv->gpu_error.reset_counter);
ba1234d1 2188
11ed50ec 2189 /*
17e1df07
DV		 2190 * Wakeup waiting processes so that the reset work function
2191 * i915_error_work_func doesn't deadlock trying to grab various
2192 * locks. By bumping the reset counter first, the woken
2193 * processes will see a reset in progress and back off,
2194 * releasing their locks and then wait for the reset completion.
2195 * We must do this for _all_ gpu waiters that might hold locks
2196 * that the reset work needs to acquire.
2197 *
2198 * Note: The wake_up serves as the required memory barrier to
2199 * ensure that the waiters see the updated value of the reset
2200 * counter atomic_t.
11ed50ec 2201 */
17e1df07 2202 i915_error_wake_up(dev_priv, false);
11ed50ec
BG		 2203 }
2204
122f46ba
DV		 2205 /*
2206 * Our reset work can grab modeset locks (since it needs to reset the
2207 * state of outstanding pagelips). Hence it must not be run on our own
2208 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2209 * code will deadlock.
2210 */
2211 schedule_work(&dev_priv->gpu_error.work);
8a905236
JB		 2212}
2213
21ad8330 2214static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
4e5359cd
SF		 2215{
2216 drm_i915_private_t *dev_priv = dev->dev_private;
2217 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 2219 struct drm_i915_gem_object *obj;
4e5359cd
SF		 2220 struct intel_unpin_work *work;
2221 unsigned long flags;
2222 bool stall_detected;
2223
2224 /* Ignore early vblank irqs */
2225 if (intel_crtc == NULL)
2226 return;
2227
2228 spin_lock_irqsave(&dev->event_lock, flags);
2229 work = intel_crtc->unpin_work;
2230
e7d841ca
CW		 2231 if (work == NULL ||
2232 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2233 !work->enable_stall_check) {
4e5359cd
SF		 2234 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2235 spin_unlock_irqrestore(&dev->event_lock, flags);
2236 return;
2237 }
2238
2239 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 2240 obj = work->pending_flip_obj;
a6c45cf0 2241 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 2242 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545 2243 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
f343c5f6 2244 i915_gem_obj_ggtt_offset(obj);
4e5359cd 2245 } else {
9db4a9c7 2246 int dspaddr = DSPADDR(intel_crtc->plane);
f343c5f6 2247 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
01f2c773 2248 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 2249 crtc->x * crtc->fb->bits_per_pixel/8);
2250 }
2251
2252 spin_unlock_irqrestore(&dev->event_lock, flags);
2253
2254 if (stall_detected) {
2255 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2256 intel_prepare_page_flip(dev, intel_crtc->plane);
2257 }
2258}
2259
42f52ef8
KP		 2260/* Called from drm generic code, passed 'crtc' which
2261 * we use as a pipe index
2262 */
f71d4af4 2263static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 2264{
2265 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 2266 unsigned long irqflags;
71e0ffa5 2267
5eddb70b 2268 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 2269 return -EINVAL;
0a3e67a4 2270
1ec14ad3 2271 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 2272 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 2273 i915_enable_pipestat(dev_priv, pipe,
2274 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 2275 else
7c463586
KP		 2276 i915_enable_pipestat(dev_priv, pipe,
2277 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 2278
2279 /* maintain vblank delivery even in deep C-states */
2280 if (dev_priv->info->gen == 3)
6b26c86d 2281 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 2282 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 2283
0a3e67a4
JB		 2284 return 0;
2285}
2286
f71d4af4 2287static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 2288{
2289 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2290 unsigned long irqflags;
b518421f 2291 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
40da17c2 2292 DE_PIPE_VBLANK(pipe);
f796cf8f
JB		 2293
2294 if (!i915_pipe_enabled(dev, pipe))
2295 return -EINVAL;
2296
2297 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b518421f 2298 ironlake_enable_display_irq(dev_priv, bit);
b1f14ad0
JB		 2299 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2300
2301 return 0;
2302}
2303
7e231dbe
JB		 2304static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2305{
2306 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2307 unsigned long irqflags;
7e231dbe
JB		 2308
2309 if (!i915_pipe_enabled(dev, pipe))
2310 return -EINVAL;
2311
2312 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5
JB		 2313 i915_enable_pipestat(dev_priv, pipe,
2314 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe
JB		 2315 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2316
2317 return 0;
2318}
2319
abd58f01
BW		 2320static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2321{
2322 struct drm_i915_private *dev_priv = dev->dev_private;
2323 unsigned long irqflags;
abd58f01
BW		 2324
2325 if (!i915_pipe_enabled(dev, pipe))
2326 return -EINVAL;
2327
2328 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7167d7c6
DV		 2329 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2330 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2331 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
abd58f01
BW		 2332 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2333 return 0;
2334}
2335
42f52ef8
KP		 2336/* Called from drm generic code, passed 'crtc' which
2337 * we use as a pipe index
2338 */
f71d4af4 2339static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 2340{
2341 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 2342 unsigned long irqflags;
0a3e67a4 2343
1ec14ad3 2344 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 2345 if (dev_priv->info->gen == 3)
6b26c86d 2346 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 2347
f796cf8f
JB		 2348 i915_disable_pipestat(dev_priv, pipe,
2349 PIPE_VBLANK_INTERRUPT_ENABLE |
2350 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2351 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2352}
2353
f71d4af4 2354static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 2355{
2356 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2357 unsigned long irqflags;
b518421f 2358 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
40da17c2 2359 DE_PIPE_VBLANK(pipe);
f796cf8f
JB		 2360
2361 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b518421f 2362 ironlake_disable_display_irq(dev_priv, bit);
b1f14ad0
JB		 2363 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2364}
2365
7e231dbe
JB		 2366static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2367{
2368 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2369 unsigned long irqflags;
7e231dbe
JB		 2370
2371 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5
JB		 2372 i915_disable_pipestat(dev_priv, pipe,
2373 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe
JB		 2374 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2375}
2376
abd58f01
BW		 2377static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2378{
2379 struct drm_i915_private *dev_priv = dev->dev_private;
2380 unsigned long irqflags;
abd58f01
BW		 2381
2382 if (!i915_pipe_enabled(dev, pipe))
2383 return;
2384
2385 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7167d7c6
DV		 2386 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2387 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2388 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
abd58f01
BW		 2389 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2390}
2391
893eead0
CW		 2392static u32
2393ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 2394{
893eead0
CW		 2395 return list_entry(ring->request_list.prev,
2396 struct drm_i915_gem_request, list)->seqno;
2397}
2398
9107e9d2
CW		 2399static bool
2400ring_idle(struct intel_ring_buffer *ring, u32 seqno)
2401{
2402 return (list_empty(&ring->request_list) ||
2403 i915_seqno_passed(seqno, ring_last_seqno(ring)));
f65d9421
BG		 2404}
2405
6274f212
CW		 2406static struct intel_ring_buffer *
2407semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
a24a11e6
CW		 2408{
2409 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6274f212 2410 u32 cmd, ipehr, acthd, acthd_min;
a24a11e6
CW		 2411
2412 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2413 if ((ipehr & ~(0x3 << 16)) !=
2414 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
6274f212 2415 return NULL;
a24a11e6
CW		 2416
2417 /* ACTHD is likely pointing to the dword after the actual command,
2418 * so scan backwards until we find the MBOX.
2419 */
6274f212 2420 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
a24a11e6
CW		 2421 acthd_min = max((int)acthd - 3 * 4, 0);
2422 do {
2423 cmd = ioread32(ring->virtual_start + acthd);
2424 if (cmd == ipehr)
2425 break;
2426
2427 acthd -= 4;
2428 if (acthd < acthd_min)
6274f212 2429 return NULL;
a24a11e6
CW		 2430 } while (1);
2431
6274f212
CW		 2432 *seqno = ioread32(ring->virtual_start+acthd+4)+1;
2433 return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
a24a11e6
CW		 2434}
2435
6274f212
CW		 2436static int semaphore_passed(struct intel_ring_buffer *ring)
2437{
2438 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2439 struct intel_ring_buffer *signaller;
2440 u32 seqno, ctl;
2441
2442 ring->hangcheck.deadlock = true;
2443
2444 signaller = semaphore_waits_for(ring, &seqno);
2445 if (signaller == NULL || signaller->hangcheck.deadlock)
2446 return -1;
2447
2448 /* cursory check for an unkickable deadlock */
2449 ctl = I915_READ_CTL(signaller);
2450 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2451 return -1;
2452
2453 return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2454}
2455
2456static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2457{
2458 struct intel_ring_buffer *ring;
2459 int i;
2460
2461 for_each_ring(ring, dev_priv, i)
2462 ring->hangcheck.deadlock = false;
2463}
2464
ad8beaea
MK		 2465static enum intel_ring_hangcheck_action
2466ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
1ec14ad3
CW		 2467{
2468 struct drm_device *dev = ring->dev;
2469 struct drm_i915_private *dev_priv = dev->dev_private;
9107e9d2
CW		 2470 u32 tmp;
2471
6274f212 2472 if (ring->hangcheck.acthd != acthd)
f2f4d82f 2473 return HANGCHECK_ACTIVE;
6274f212 2474
9107e9d2 2475 if (IS_GEN2(dev))
f2f4d82f 2476 return HANGCHECK_HUNG;
9107e9d2
CW		 2477
2478 /* Is the chip hanging on a WAIT_FOR_EVENT?
2479 * If so we can simply poke the RB_WAIT bit
2480 * and break the hang. This should work on
2481 * all but the second generation chipsets.
2482 */
2483 tmp = I915_READ_CTL(ring);
1ec14ad3
CW		 2484 if (tmp & RING_WAIT) {
2485 DRM_ERROR("Kicking stuck wait on %s\n",
2486 ring->name);
09e14bf3 2487 i915_handle_error(dev, false);
1ec14ad3 2488 I915_WRITE_CTL(ring, tmp);
f2f4d82f 2489 return HANGCHECK_KICK;
6274f212
CW		 2490 }
2491
2492 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2493 switch (semaphore_passed(ring)) {
2494 default:
f2f4d82f 2495 return HANGCHECK_HUNG;
6274f212
CW		 2496 case 1:
2497 DRM_ERROR("Kicking stuck semaphore on %s\n",
2498 ring->name);
09e14bf3 2499 i915_handle_error(dev, false);
6274f212 2500 I915_WRITE_CTL(ring, tmp);
f2f4d82f 2501 return HANGCHECK_KICK;
6274f212 2502 case 0:
f2f4d82f 2503 return HANGCHECK_WAIT;
6274f212 2504 }
9107e9d2 2505 }
ed5cbb03 2506
f2f4d82f 2507 return HANGCHECK_HUNG;
ed5cbb03
MK		 2508}
2509
f65d9421
BG		 2510/**
2511 * This is called when the chip hasn't reported back with completed
05407ff8
MK		 2512 * batchbuffers in a long time. We keep track per ring seqno progress and
2513 * if there are no progress, hangcheck score for that ring is increased.
2514 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2515 * we kick the ring. If we see no progress on three subsequent calls
2516 * we assume chip is wedged and try to fix it by resetting the chip.
f65d9421 2517 */
a658b5d2 2518static void i915_hangcheck_elapsed(unsigned long data)
f65d9421
BG		 2519{
2520 struct drm_device *dev = (struct drm_device *)data;
2521 drm_i915_private_t *dev_priv = dev->dev_private;
b4519513 2522 struct intel_ring_buffer *ring;
b4519513 2523 int i;
05407ff8 2524 int busy_count = 0, rings_hung = 0;
9107e9d2
CW		 2525 bool stuck[I915_NUM_RINGS] = { 0 };
2526#define BUSY 1
2527#define KICK 5
2528#define HUNG 20
893eead0 2529
d330a953 2530 if (!i915.enable_hangcheck)
3e0dc6b0
BW		 2531 return;
2532
b4519513 2533 for_each_ring(ring, dev_priv, i) {
05407ff8 2534 u32 seqno, acthd;
9107e9d2 2535 bool busy = true;
05407ff8 2536
6274f212
CW		 2537 semaphore_clear_deadlocks(dev_priv);
2538
05407ff8
MK		 2539 seqno = ring->get_seqno(ring, false);
2540 acthd = intel_ring_get_active_head(ring);
b4519513 2541
9107e9d2
CW		 2542 if (ring->hangcheck.seqno == seqno) {
2543 if (ring_idle(ring, seqno)) {
da661464
MK		 2544 ring->hangcheck.action = HANGCHECK_IDLE;
2545
9107e9d2
CW		 2546 if (waitqueue_active(&ring->irq_queue)) {
2547 /* Issue a wake-up to catch stuck h/w. */
094f9a54 2548 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
f4adcd24
DV		 2549 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2550 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2551 ring->name);
2552 else
2553 DRM_INFO("Fake missed irq on %s\n",
2554 ring->name);
094f9a54
CW		 2555 wake_up_all(&ring->irq_queue);
2556 }
2557 /* Safeguard against driver failure */
2558 ring->hangcheck.score += BUSY;
9107e9d2
CW		 2559 } else
2560 busy = false;
05407ff8 2561 } else {
6274f212
CW		 2562 /* We always increment the hangcheck score
2563 * if the ring is busy and still processing
2564 * the same request, so that no single request
2565 * can run indefinitely (such as a chain of
2566 * batches). The only time we do not increment
2567 * the hangcheck score on this ring, if this
2568 * ring is in a legitimate wait for another
2569 * ring. In that case the waiting ring is a
2570 * victim and we want to be sure we catch the
2571 * right culprit. Then every time we do kick
2572 * the ring, add a small increment to the
2573 * score so that we can catch a batch that is
2574 * being repeatedly kicked and so responsible
2575 * for stalling the machine.
2576 */
ad8beaea
MK		 2577 ring->hangcheck.action = ring_stuck(ring,
2578 acthd);
2579
2580 switch (ring->hangcheck.action) {
da661464 2581 case HANGCHECK_IDLE:
f2f4d82f 2582 case HANGCHECK_WAIT:
6274f212 2583 break;
f2f4d82f 2584 case HANGCHECK_ACTIVE:
ea04cb31 2585 ring->hangcheck.score += BUSY;
6274f212 2586 break;
f2f4d82f 2587 case HANGCHECK_KICK:
ea04cb31 2588 ring->hangcheck.score += KICK;
6274f212 2589 break;
f2f4d82f 2590 case HANGCHECK_HUNG:
ea04cb31 2591 ring->hangcheck.score += HUNG;
6274f212
CW		 2592 stuck[i] = true;
2593 break;
2594 }
05407ff8 2595 }
9107e9d2 2596 } else {
da661464
MK		 2597 ring->hangcheck.action = HANGCHECK_ACTIVE;
2598
9107e9d2
CW		 2599 /* Gradually reduce the count so that we catch DoS
2600 * attempts across multiple batches.
2601 */
2602 if (ring->hangcheck.score > 0)
2603 ring->hangcheck.score--;
d1e61e7f
CW		 2604 }
2605
05407ff8
MK		 2606 ring->hangcheck.seqno = seqno;
2607 ring->hangcheck.acthd = acthd;
9107e9d2 2608 busy_count += busy;
893eead0 2609 }
b9201c14 2610
92cab734 2611 for_each_ring(ring, dev_priv, i) {
b6b0fac0 2612 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
b8d88d1d
DV		 2613 DRM_INFO("%s on %s\n",
2614 stuck[i] ? "stuck" : "no progress",
2615 ring->name);
a43adf07 2616 rings_hung++;
92cab734
MK		 2617 }
2618 }
2619
05407ff8
MK		 2620 if (rings_hung)
2621 return i915_handle_error(dev, true);
f65d9421 2622
05407ff8
MK		 2623 if (busy_count)
2624 /* Reset timer case chip hangs without another request
2625 * being added */
10cd45b6
MK		 2626 i915_queue_hangcheck(dev);
2627}
2628
2629void i915_queue_hangcheck(struct drm_device *dev)
2630{
2631 struct drm_i915_private *dev_priv = dev->dev_private;
d330a953 2632 if (!i915.enable_hangcheck)
10cd45b6
MK		 2633 return;
2634
2635 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2636 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
f65d9421
BG		 2637}
2638
91738a95
PZ		 2639static void ibx_irq_preinstall(struct drm_device *dev)
2640{
2641 struct drm_i915_private *dev_priv = dev->dev_private;
2642
2643 if (HAS_PCH_NOP(dev))
2644 return;
2645
2646 /* south display irq */
2647 I915_WRITE(SDEIMR, 0xffffffff);
2648 /*
2649 * SDEIER is also touched by the interrupt handler to work around missed
2650 * PCH interrupts. Hence we can't update it after the interrupt handler
2651 * is enabled - instead we unconditionally enable all PCH interrupt
2652 * sources here, but then only unmask them as needed with SDEIMR.
2653 */
2654 I915_WRITE(SDEIER, 0xffffffff);
2655 POSTING_READ(SDEIER);
2656}
2657
d18ea1b5
DV		 2658static void gen5_gt_irq_preinstall(struct drm_device *dev)
2659{
2660 struct drm_i915_private *dev_priv = dev->dev_private;
2661
2662 /* and GT */
2663 I915_WRITE(GTIMR, 0xffffffff);
2664 I915_WRITE(GTIER, 0x0);
2665 POSTING_READ(GTIER);
2666
2667 if (INTEL_INFO(dev)->gen >= 6) {
2668 /* and PM */
2669 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2670 I915_WRITE(GEN6_PMIER, 0x0);
2671 POSTING_READ(GEN6_PMIER);
2672 }
2673}
2674
1da177e4
LT		 2675/* drm_dma.h hooks
2676*/
f71d4af4 2677static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 2678{
2679 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2680
2681 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 2682
036a4a7d
ZW		 2683 I915_WRITE(DEIMR, 0xffffffff);
2684 I915_WRITE(DEIER, 0x0);
3143a2bf 2685 POSTING_READ(DEIER);
036a4a7d 2686
d18ea1b5 2687 gen5_gt_irq_preinstall(dev);
c650156a 2688
91738a95 2689 ibx_irq_preinstall(dev);
7d99163d
BW		 2690}
2691
7e231dbe
JB		 2692static void valleyview_irq_preinstall(struct drm_device *dev)
2693{
2694 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2695 int pipe;
2696
7e231dbe
JB		 2697 /* VLV magic */
2698 I915_WRITE(VLV_IMR, 0);
2699 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2700 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2701 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2702
7e231dbe
JB		 2703 /* and GT */
2704 I915_WRITE(GTIIR, I915_READ(GTIIR));
2705 I915_WRITE(GTIIR, I915_READ(GTIIR));
d18ea1b5
DV		 2706
2707 gen5_gt_irq_preinstall(dev);
7e231dbe
JB		 2708
2709 I915_WRITE(DPINVGTT, 0xff);
2710
2711 I915_WRITE(PORT_HOTPLUG_EN, 0);
2712 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2713 for_each_pipe(pipe)
2714 I915_WRITE(PIPESTAT(pipe), 0xffff);
2715 I915_WRITE(VLV_IIR, 0xffffffff);
2716 I915_WRITE(VLV_IMR, 0xffffffff);
2717 I915_WRITE(VLV_IER, 0x0);
2718 POSTING_READ(VLV_IER);
2719}
2720
abd58f01
BW		 2721static void gen8_irq_preinstall(struct drm_device *dev)
2722{
2723 struct drm_i915_private *dev_priv = dev->dev_private;
2724 int pipe;
2725
abd58f01
BW		 2726 I915_WRITE(GEN8_MASTER_IRQ, 0);
2727 POSTING_READ(GEN8_MASTER_IRQ);
2728
2729 /* IIR can theoretically queue up two events. Be paranoid */
2730#define GEN8_IRQ_INIT_NDX(type, which) do { \
2731 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
2732 POSTING_READ(GEN8_##type##_IMR(which)); \
2733 I915_WRITE(GEN8_##type##_IER(which), 0); \
2734 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2735 POSTING_READ(GEN8_##type##_IIR(which)); \
2736 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2737 } while (0)
2738
2739#define GEN8_IRQ_INIT(type) do { \
2740 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
2741 POSTING_READ(GEN8_##type##_IMR); \
2742 I915_WRITE(GEN8_##type##_IER, 0); \
2743 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2744 POSTING_READ(GEN8_##type##_IIR); \
2745 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2746 } while (0)
2747
2748 GEN8_IRQ_INIT_NDX(GT, 0);
2749 GEN8_IRQ_INIT_NDX(GT, 1);
2750 GEN8_IRQ_INIT_NDX(GT, 2);
2751 GEN8_IRQ_INIT_NDX(GT, 3);
2752
2753 for_each_pipe(pipe) {
2754 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe);
2755 }
2756
2757 GEN8_IRQ_INIT(DE_PORT);
2758 GEN8_IRQ_INIT(DE_MISC);
2759 GEN8_IRQ_INIT(PCU);
2760#undef GEN8_IRQ_INIT
2761#undef GEN8_IRQ_INIT_NDX
2762
2763 POSTING_READ(GEN8_PCU_IIR);
09f2344d
JB		 2764
2765 ibx_irq_preinstall(dev);
abd58f01
BW		 2766}
2767
82a28bcf 2768static void ibx_hpd_irq_setup(struct drm_device *dev)
7fe0b973
KP		 2769{
2770 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82a28bcf
DV		 2771 struct drm_mode_config *mode_config = &dev->mode_config;
2772 struct intel_encoder *intel_encoder;
fee884ed 2773 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
82a28bcf
DV		 2774
2775 if (HAS_PCH_IBX(dev)) {
fee884ed 2776 hotplug_irqs = SDE_HOTPLUG_MASK;
82a28bcf 2777 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed 2778 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
fee884ed 2779 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
82a28bcf 2780 } else {
fee884ed 2781 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
82a28bcf 2782 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed 2783 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
fee884ed 2784 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
82a28bcf 2785 }
7fe0b973 2786
fee884ed 2787 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
82a28bcf
DV		 2788
2789 /*
2790 * Enable digital hotplug on the PCH, and configure the DP short pulse
2791 * duration to 2ms (which is the minimum in the Display Port spec)
2792 *
2793 * This register is the same on all known PCH chips.
2794 */
7fe0b973
KP		 2795 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2796 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2797 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2798 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2799 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2800 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2801}
2802
d46da437
PZ		 2803static void ibx_irq_postinstall(struct drm_device *dev)
2804{
2805 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82a28bcf 2806 u32 mask;
e5868a31 2807
692a04cf
DV		 2808 if (HAS_PCH_NOP(dev))
2809 return;
2810
8664281b
PZ		 2811 if (HAS_PCH_IBX(dev)) {
2812 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
de032bf4 2813 SDE_TRANSA_FIFO_UNDER | SDE_POISON;
8664281b
PZ		 2814 } else {
2815 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2816
2817 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2818 }
ab5c608b 2819
d46da437
PZ		 2820 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2821 I915_WRITE(SDEIMR, ~mask);
d46da437
PZ		 2822}
2823
0a9a8c91
DV		 2824static void gen5_gt_irq_postinstall(struct drm_device *dev)
2825{
2826 struct drm_i915_private *dev_priv = dev->dev_private;
2827 u32 pm_irqs, gt_irqs;
2828
2829 pm_irqs = gt_irqs = 0;
2830
2831 dev_priv->gt_irq_mask = ~0;
040d2baa 2832 if (HAS_L3_DPF(dev)) {
0a9a8c91 2833 /* L3 parity interrupt is always unmasked. */
35a85ac6
BW		 2834 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
2835 gt_irqs |= GT_PARITY_ERROR(dev);
0a9a8c91
DV		 2836 }
2837
2838 gt_irqs |= GT_RENDER_USER_INTERRUPT;
2839 if (IS_GEN5(dev)) {
2840 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2841 ILK_BSD_USER_INTERRUPT;
2842 } else {
2843 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
2844 }
2845
2846 I915_WRITE(GTIIR, I915_READ(GTIIR));
2847 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2848 I915_WRITE(GTIER, gt_irqs);
2849 POSTING_READ(GTIER);
2850
2851 if (INTEL_INFO(dev)->gen >= 6) {
2852 pm_irqs |= GEN6_PM_RPS_EVENTS;
2853
2854 if (HAS_VEBOX(dev))
2855 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
2856
605cd25b 2857 dev_priv->pm_irq_mask = 0xffffffff;
0a9a8c91 2858 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
605cd25b 2859 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
0a9a8c91
DV		 2860 I915_WRITE(GEN6_PMIER, pm_irqs);
2861 POSTING_READ(GEN6_PMIER);
2862 }
2863}
2864
f71d4af4 2865static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d 2866{
4bc9d430 2867 unsigned long irqflags;
036a4a7d 2868 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8e76f8dc
PZ		 2869 u32 display_mask, extra_mask;
2870
2871 if (INTEL_INFO(dev)->gen >= 7) {
2872 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
2873 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
2874 DE_PLANEB_FLIP_DONE_IVB |
2875 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB |
2876 DE_ERR_INT_IVB);
2877 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
2878 DE_PIPEA_VBLANK_IVB);
2879
2880 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2881 } else {
2882 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2883 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
5b3a856b
DV		 2884 DE_AUX_CHANNEL_A |
2885 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
2886 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
2887 DE_POISON);
8e76f8dc
PZ		 2888 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT;
2889 }
036a4a7d 2890
1ec14ad3 2891 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 2892
2893 /* should always can generate irq */
2894 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3 2895 I915_WRITE(DEIMR, dev_priv->irq_mask);
8e76f8dc 2896 I915_WRITE(DEIER, display_mask | extra_mask);
3143a2bf 2897 POSTING_READ(DEIER);
036a4a7d 2898
0a9a8c91 2899 gen5_gt_irq_postinstall(dev);
036a4a7d 2900
d46da437 2901 ibx_irq_postinstall(dev);
7fe0b973 2902
f97108d1 2903 if (IS_IRONLAKE_M(dev)) {
6005ce42
DV		 2904 /* Enable PCU event interrupts
2905 *
2906 * spinlocking not required here for correctness since interrupt
4bc9d430
DV		 2907 * setup is guaranteed to run in single-threaded context. But we
2908 * need it to make the assert_spin_locked happy. */
2909 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f97108d1 2910 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
4bc9d430 2911 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
f97108d1
JB		 2912 }
2913
036a4a7d
ZW		 2914 return 0;
2915}
2916
7e231dbe
JB		 2917static int valleyview_irq_postinstall(struct drm_device *dev)
2918{
2919 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7e231dbe 2920 u32 enable_mask;
379ef82d
DV		 2921 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV |
2922 PIPE_CRC_DONE_ENABLE;
b79480ba 2923 unsigned long irqflags;
7e231dbe
JB		 2924
2925 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
31acc7f5
JB		 2926 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2927 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2928 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
7e231dbe
JB		 2929 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2930
31acc7f5
JB		 2931 /*
2932 *Leave vblank interrupts masked initially. enable/disable will
2933 * toggle them based on usage.
2934 */
2935 dev_priv->irq_mask = (~enable_mask) |
2936 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2937 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2938
20afbda2
DV		 2939 I915_WRITE(PORT_HOTPLUG_EN, 0);
2940 POSTING_READ(PORT_HOTPLUG_EN);
2941
7e231dbe
JB		 2942 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2943 I915_WRITE(VLV_IER, enable_mask);
2944 I915_WRITE(VLV_IIR, 0xffffffff);
2945 I915_WRITE(PIPESTAT(0), 0xffff);
2946 I915_WRITE(PIPESTAT(1), 0xffff);
2947 POSTING_READ(VLV_IER);
2948
b79480ba
DV		 2949 /* Interrupt setup is already guaranteed to be single-threaded, this is
2950 * just to make the assert_spin_locked check happy. */
2951 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3b6c42e8
DV		 2952 i915_enable_pipestat(dev_priv, PIPE_A, pipestat_enable);
2953 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE);
2954 i915_enable_pipestat(dev_priv, PIPE_B, pipestat_enable);
b79480ba 2955 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
31acc7f5 2956
7e231dbe
JB		 2957 I915_WRITE(VLV_IIR, 0xffffffff);
2958 I915_WRITE(VLV_IIR, 0xffffffff);
2959
0a9a8c91 2960 gen5_gt_irq_postinstall(dev);
7e231dbe
JB		 2961
2962 /* ack & enable invalid PTE error interrupts */
2963#if 0 /* FIXME: add support to irq handler for checking these bits */
2964 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2965 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2966#endif
2967
2968 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
20afbda2
DV		 2969
2970 return 0;
2971}
2972
abd58f01
BW		 2973static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
2974{
2975 int i;
2976
2977 /* These are interrupts we'll toggle with the ring mask register */
2978 uint32_t gt_interrupts[] = {
2979 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
2980 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
2981 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
2982 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
2983 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
2984 0,
2985 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT
2986 };
2987
2988 for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) {
2989 u32 tmp = I915_READ(GEN8_GT_IIR(i));
2990 if (tmp)
2991 DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
2992 i, tmp);
2993 I915_WRITE(GEN8_GT_IMR(i), ~gt_interrupts[i]);
2994 I915_WRITE(GEN8_GT_IER(i), gt_interrupts[i]);
2995 }
2996 POSTING_READ(GEN8_GT_IER(0));
2997}
2998
2999static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3000{
3001 struct drm_device *dev = dev_priv->dev;
13b3a0a7
DV		 3002 uint32_t de_pipe_masked = GEN8_PIPE_FLIP_DONE |
3003 GEN8_PIPE_CDCLK_CRC_DONE |
3004 GEN8_PIPE_FIFO_UNDERRUN |
3005 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3006 uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK;
abd58f01 3007 int pipe;
13b3a0a7
DV		 3008 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3009 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3010 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
abd58f01
BW		 3011
3012 for_each_pipe(pipe) {
3013 u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe));
3014 if (tmp)
3015 DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
3016 pipe, tmp);
3017 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
3018 I915_WRITE(GEN8_DE_PIPE_IER(pipe), de_pipe_enables);
3019 }
3020 POSTING_READ(GEN8_DE_PIPE_ISR(0));
3021
6d766f02
DV		 3022 I915_WRITE(GEN8_DE_PORT_IMR, ~GEN8_AUX_CHANNEL_A);
3023 I915_WRITE(GEN8_DE_PORT_IER, GEN8_AUX_CHANNEL_A);
abd58f01
BW		 3024 POSTING_READ(GEN8_DE_PORT_IER);
3025}
3026
3027static int gen8_irq_postinstall(struct drm_device *dev)
3028{
3029 struct drm_i915_private *dev_priv = dev->dev_private;
3030
3031 gen8_gt_irq_postinstall(dev_priv);
3032 gen8_de_irq_postinstall(dev_priv);
3033
3034 ibx_irq_postinstall(dev);
3035
3036 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3037 POSTING_READ(GEN8_MASTER_IRQ);
3038
3039 return 0;
3040}
3041
3042static void gen8_irq_uninstall(struct drm_device *dev)
3043{
3044 struct drm_i915_private *dev_priv = dev->dev_private;
3045 int pipe;
3046
3047 if (!dev_priv)
3048 return;
3049
abd58f01
BW		 3050 I915_WRITE(GEN8_MASTER_IRQ, 0);
3051
3052#define GEN8_IRQ_FINI_NDX(type, which) do { \
3053 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
3054 I915_WRITE(GEN8_##type##_IER(which), 0); \
3055 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3056 } while (0)
3057
3058#define GEN8_IRQ_FINI(type) do { \
3059 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
3060 I915_WRITE(GEN8_##type##_IER, 0); \
3061 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3062 } while (0)
3063
3064 GEN8_IRQ_FINI_NDX(GT, 0);
3065 GEN8_IRQ_FINI_NDX(GT, 1);
3066 GEN8_IRQ_FINI_NDX(GT, 2);
3067 GEN8_IRQ_FINI_NDX(GT, 3);
3068
3069 for_each_pipe(pipe) {
3070 GEN8_IRQ_FINI_NDX(DE_PIPE, pipe);
3071 }
3072
3073 GEN8_IRQ_FINI(DE_PORT);
3074 GEN8_IRQ_FINI(DE_MISC);
3075 GEN8_IRQ_FINI(PCU);
3076#undef GEN8_IRQ_FINI
3077#undef GEN8_IRQ_FINI_NDX
3078
3079 POSTING_READ(GEN8_PCU_IIR);
3080}
3081
7e231dbe
JB		 3082static void valleyview_irq_uninstall(struct drm_device *dev)
3083{
3084 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3085 int pipe;
3086
3087 if (!dev_priv)
3088 return;
3089
3ca1cced 3090 intel_hpd_irq_uninstall(dev_priv);
ac4c16c5 3091
7e231dbe
JB		 3092 for_each_pipe(pipe)
3093 I915_WRITE(PIPESTAT(pipe), 0xffff);
3094
3095 I915_WRITE(HWSTAM, 0xffffffff);
3096 I915_WRITE(PORT_HOTPLUG_EN, 0);
3097 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3098 for_each_pipe(pipe)
3099 I915_WRITE(PIPESTAT(pipe), 0xffff);
3100 I915_WRITE(VLV_IIR, 0xffffffff);
3101 I915_WRITE(VLV_IMR, 0xffffffff);
3102 I915_WRITE(VLV_IER, 0x0);
3103 POSTING_READ(VLV_IER);
3104}
3105
f71d4af4 3106static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 3107{
3108 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 3109
3110 if (!dev_priv)
3111 return;
3112
3ca1cced 3113 intel_hpd_irq_uninstall(dev_priv);
ac4c16c5 3114
036a4a7d
ZW		 3115 I915_WRITE(HWSTAM, 0xffffffff);
3116
3117 I915_WRITE(DEIMR, 0xffffffff);
3118 I915_WRITE(DEIER, 0x0);
3119 I915_WRITE(DEIIR, I915_READ(DEIIR));
8664281b
PZ		 3120 if (IS_GEN7(dev))
3121 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
036a4a7d
ZW		 3122
3123 I915_WRITE(GTIMR, 0xffffffff);
3124 I915_WRITE(GTIER, 0x0);
3125 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f 3126
ab5c608b
BW		 3127 if (HAS_PCH_NOP(dev))
3128 return;
3129
192aac1f
KP		 3130 I915_WRITE(SDEIMR, 0xffffffff);
3131 I915_WRITE(SDEIER, 0x0);
3132 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
8664281b
PZ		 3133 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3134 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
036a4a7d
ZW		 3135}
3136
a266c7d5 3137static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 3138{
3139 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 3140 int pipe;
91e3738e 3141
9db4a9c7
JB		 3142 for_each_pipe(pipe)
3143 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 3144 I915_WRITE16(IMR, 0xffff);
3145 I915_WRITE16(IER, 0x0);
3146 POSTING_READ16(IER);
c2798b19
CW		 3147}
3148
3149static int i8xx_irq_postinstall(struct drm_device *dev)
3150{
3151 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
379ef82d 3152 unsigned long irqflags;
c2798b19 3153
c2798b19
CW		 3154 I915_WRITE16(EMR,
3155 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3156
3157 /* Unmask the interrupts that we always want on. */
3158 dev_priv->irq_mask =
3159 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3160 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3161 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3162 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3163 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3164 I915_WRITE16(IMR, dev_priv->irq_mask);
3165
3166 I915_WRITE16(IER,
3167 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3168 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3169 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3170 I915_USER_INTERRUPT);
3171 POSTING_READ16(IER);
3172
379ef82d
DV		 3173 /* Interrupt setup is already guaranteed to be single-threaded, this is
3174 * just to make the assert_spin_locked check happy. */
3175 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3b6c42e8
DV		 3176 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3177 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
379ef82d
DV		 3178 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3179
c2798b19
CW		 3180 return 0;
3181}
3182
90a72f87
VS		 3183/*
3184 * Returns true when a page flip has completed.
3185 */
3186static bool i8xx_handle_vblank(struct drm_device *dev,
1f1c2e24 3187 int plane, int pipe, u32 iir)
90a72f87
VS		 3188{
3189 drm_i915_private_t *dev_priv = dev->dev_private;
1f1c2e24 3190 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
90a72f87
VS		 3191
3192 if (!drm_handle_vblank(dev, pipe))
3193 return false;
3194
3195 if ((iir & flip_pending) == 0)
3196 return false;
3197
1f1c2e24 3198 intel_prepare_page_flip(dev, plane);
90a72f87
VS		 3199
3200 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3201 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3202 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3203 * the flip is completed (no longer pending). Since this doesn't raise
3204 * an interrupt per se, we watch for the change at vblank.
3205 */
3206 if (I915_READ16(ISR) & flip_pending)
3207 return false;
3208
3209 intel_finish_page_flip(dev, pipe);
3210
3211 return true;
3212}
3213
ff1f525e 3214static irqreturn_t i8xx_irq_handler(int irq, void *arg)
c2798b19
CW		 3215{
3216 struct drm_device *dev = (struct drm_device *) arg;
3217 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 3218 u16 iir, new_iir;
3219 u32 pipe_stats[2];
3220 unsigned long irqflags;
c2798b19
CW		 3221 int pipe;
3222 u16 flip_mask =
3223 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3224 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3225
c2798b19
CW		 3226 iir = I915_READ16(IIR);
3227 if (iir == 0)
3228 return IRQ_NONE;
3229
3230 while (iir & ~flip_mask) {
3231 /* Can't rely on pipestat interrupt bit in iir as it might
3232 * have been cleared after the pipestat interrupt was received.
3233 * It doesn't set the bit in iir again, but it still produces
3234 * interrupts (for non-MSI).
3235 */
3236 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3237 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3238 i915_handle_error(dev, false);
3239
3240 for_each_pipe(pipe) {
3241 int reg = PIPESTAT(pipe);
3242 pipe_stats[pipe] = I915_READ(reg);
3243
3244 /*
3245 * Clear the PIPE*STAT regs before the IIR
3246 */
2d9d2b0b 3247 if (pipe_stats[pipe] & 0x8000ffff)
c2798b19 3248 I915_WRITE(reg, pipe_stats[pipe]);
c2798b19
CW		 3249 }
3250 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3251
3252 I915_WRITE16(IIR, iir & ~flip_mask);
3253 new_iir = I915_READ16(IIR); /* Flush posted writes */
3254
d05c617e 3255 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 3256
3257 if (iir & I915_USER_INTERRUPT)
3258 notify_ring(dev, &dev_priv->ring[RCS]);
3259
4356d586 3260 for_each_pipe(pipe) {
1f1c2e24 3261 int plane = pipe;
3a77c4c4 3262 if (HAS_FBC(dev))
1f1c2e24
VS		 3263 plane = !plane;
3264
4356d586 3265 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
1f1c2e24
VS		 3266 i8xx_handle_vblank(dev, plane, pipe, iir))
3267 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
c2798b19 3268
4356d586 3269 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
277de95e 3270 i9xx_pipe_crc_irq_handler(dev, pipe);
2d9d2b0b
VS		 3271
3272 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3273 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
fc2c807b 3274 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
4356d586 3275 }
c2798b19
CW		 3276
3277 iir = new_iir;
3278 }
3279
3280 return IRQ_HANDLED;
3281}
3282
3283static void i8xx_irq_uninstall(struct drm_device * dev)
3284{
3285 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3286 int pipe;
3287
c2798b19
CW		 3288 for_each_pipe(pipe) {
3289 /* Clear enable bits; then clear status bits */
3290 I915_WRITE(PIPESTAT(pipe), 0);
3291 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3292 }
3293 I915_WRITE16(IMR, 0xffff);
3294 I915_WRITE16(IER, 0x0);
3295 I915_WRITE16(IIR, I915_READ16(IIR));
3296}
3297
a266c7d5
CW		 3298static void i915_irq_preinstall(struct drm_device * dev)
3299{
3300 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3301 int pipe;
3302
a266c7d5
CW		 3303 if (I915_HAS_HOTPLUG(dev)) {
3304 I915_WRITE(PORT_HOTPLUG_EN, 0);
3305 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3306 }
3307
00d98ebd 3308 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 3309 for_each_pipe(pipe)
3310 I915_WRITE(PIPESTAT(pipe), 0);
3311 I915_WRITE(IMR, 0xffffffff);
3312 I915_WRITE(IER, 0x0);
3313 POSTING_READ(IER);
3314}
3315
3316static int i915_irq_postinstall(struct drm_device *dev)
3317{
3318 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 3319 u32 enable_mask;
379ef82d 3320 unsigned long irqflags;
a266c7d5 3321
38bde180
CW		 3322 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3323
3324 /* Unmask the interrupts that we always want on. */
3325 dev_priv->irq_mask =
3326 ~(I915_ASLE_INTERRUPT |
3327 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3328 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3329 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3330 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3331 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3332
3333 enable_mask =
3334 I915_ASLE_INTERRUPT |
3335 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3336 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3337 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3338 I915_USER_INTERRUPT;
3339
a266c7d5 3340 if (I915_HAS_HOTPLUG(dev)) {
20afbda2
DV		 3341 I915_WRITE(PORT_HOTPLUG_EN, 0);
3342 POSTING_READ(PORT_HOTPLUG_EN);
3343
a266c7d5
CW		 3344 /* Enable in IER... */
3345 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3346 /* and unmask in IMR */
3347 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3348 }
3349
a266c7d5
CW		 3350 I915_WRITE(IMR, dev_priv->irq_mask);
3351 I915_WRITE(IER, enable_mask);
3352 POSTING_READ(IER);
3353
f49e38dd 3354 i915_enable_asle_pipestat(dev);
20afbda2 3355
379ef82d
DV		 3356 /* Interrupt setup is already guaranteed to be single-threaded, this is
3357 * just to make the assert_spin_locked check happy. */
3358 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3b6c42e8
DV		 3359 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3360 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
379ef82d
DV		 3361 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3362
20afbda2
DV		 3363 return 0;
3364}
3365
90a72f87
VS		 3366/*
3367 * Returns true when a page flip has completed.
3368 */
3369static bool i915_handle_vblank(struct drm_device *dev,
3370 int plane, int pipe, u32 iir)
3371{
3372 drm_i915_private_t *dev_priv = dev->dev_private;
3373 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3374
3375 if (!drm_handle_vblank(dev, pipe))
3376 return false;
3377
3378 if ((iir & flip_pending) == 0)
3379 return false;
3380
3381 intel_prepare_page_flip(dev, plane);
3382
3383 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3384 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3385 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3386 * the flip is completed (no longer pending). Since this doesn't raise
3387 * an interrupt per se, we watch for the change at vblank.
3388 */
3389 if (I915_READ(ISR) & flip_pending)
3390 return false;
3391
3392 intel_finish_page_flip(dev, pipe);
3393
3394 return true;
3395}
3396
ff1f525e 3397static irqreturn_t i915_irq_handler(int irq, void *arg)
a266c7d5
CW		 3398{
3399 struct drm_device *dev = (struct drm_device *) arg;
3400 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 3401 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 3402 unsigned long irqflags;
38bde180
CW		 3403 u32 flip_mask =
3404 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3405 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
38bde180 3406 int pipe, ret = IRQ_NONE;
a266c7d5 3407
a266c7d5 3408 iir = I915_READ(IIR);
38bde180
CW		 3409 do {
3410 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 3411 bool blc_event = false;
a266c7d5
CW		 3412
3413 /* Can't rely on pipestat interrupt bit in iir as it might
3414 * have been cleared after the pipestat interrupt was received.
3415 * It doesn't set the bit in iir again, but it still produces
3416 * interrupts (for non-MSI).
3417 */
3418 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3419 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3420 i915_handle_error(dev, false);
3421
3422 for_each_pipe(pipe) {
3423 int reg = PIPESTAT(pipe);
3424 pipe_stats[pipe] = I915_READ(reg);
3425
38bde180 3426 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5 3427 if (pipe_stats[pipe] & 0x8000ffff) {
a266c7d5 3428 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 3429 irq_received = true;
a266c7d5
CW		 3430 }
3431 }
3432 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3433
3434 if (!irq_received)
3435 break;
3436
a266c7d5
CW		 3437 /* Consume port. Then clear IIR or we'll miss events */
3438 if ((I915_HAS_HOTPLUG(dev)) &&
3439 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
3440 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04 3441 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
a266c7d5 3442
91d131d2
DV		 3443 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
3444
a266c7d5 3445 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 3446 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 3447 }
3448
38bde180 3449 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 3450 new_iir = I915_READ(IIR); /* Flush posted writes */
3451
a266c7d5
CW		 3452 if (iir & I915_USER_INTERRUPT)
3453 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 3454
a266c7d5 3455 for_each_pipe(pipe) {
38bde180 3456 int plane = pipe;
3a77c4c4 3457 if (HAS_FBC(dev))
38bde180 3458 plane = !plane;
90a72f87 3459
8291ee90 3460 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3461 i915_handle_vblank(dev, plane, pipe, iir))
3462 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
a266c7d5
CW		 3463
3464 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3465 blc_event = true;
4356d586
DV		 3466
3467 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
277de95e 3468 i9xx_pipe_crc_irq_handler(dev, pipe);
2d9d2b0b
VS		 3469
3470 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3471 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
fc2c807b 3472 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
a266c7d5
CW		 3473 }
3474
a266c7d5
CW		 3475 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3476 intel_opregion_asle_intr(dev);
3477
3478 /* With MSI, interrupts are only generated when iir
3479 * transitions from zero to nonzero. If another bit got
3480 * set while we were handling the existing iir bits, then
3481 * we would never get another interrupt.
3482 *
3483 * This is fine on non-MSI as well, as if we hit this path
3484 * we avoid exiting the interrupt handler only to generate
3485 * another one.
3486 *
3487 * Note that for MSI this could cause a stray interrupt report
3488 * if an interrupt landed in the time between writing IIR and
3489 * the posting read. This should be rare enough to never
3490 * trigger the 99% of 100,000 interrupts test for disabling
3491 * stray interrupts.
3492 */
38bde180 3493 ret = IRQ_HANDLED;
a266c7d5 3494 iir = new_iir;
38bde180 3495 } while (iir & ~flip_mask);
a266c7d5 3496
d05c617e 3497 i915_update_dri1_breadcrumb(dev);
8291ee90 3498
a266c7d5
CW		 3499 return ret;
3500}
3501
3502static void i915_irq_uninstall(struct drm_device * dev)
3503{
3504 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3505 int pipe;
3506
3ca1cced 3507 intel_hpd_irq_uninstall(dev_priv);
ac4c16c5 3508
a266c7d5
CW		 3509 if (I915_HAS_HOTPLUG(dev)) {
3510 I915_WRITE(PORT_HOTPLUG_EN, 0);
3511 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3512 }
3513
00d98ebd 3514 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 3515 for_each_pipe(pipe) {
3516 /* Clear enable bits; then clear status bits */
a266c7d5 3517 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 3518 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3519 }
a266c7d5
CW		 3520 I915_WRITE(IMR, 0xffffffff);
3521 I915_WRITE(IER, 0x0);
3522
a266c7d5
CW		 3523 I915_WRITE(IIR, I915_READ(IIR));
3524}
3525
3526static void i965_irq_preinstall(struct drm_device * dev)
3527{
3528 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3529 int pipe;
3530
adca4730
CW		 3531 I915_WRITE(PORT_HOTPLUG_EN, 0);
3532 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 3533
3534 I915_WRITE(HWSTAM, 0xeffe);
3535 for_each_pipe(pipe)
3536 I915_WRITE(PIPESTAT(pipe), 0);
3537 I915_WRITE(IMR, 0xffffffff);
3538 I915_WRITE(IER, 0x0);
3539 POSTING_READ(IER);
3540}
3541
3542static int i965_irq_postinstall(struct drm_device *dev)
3543{
3544 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
bbba0a97 3545 u32 enable_mask;
a266c7d5 3546 u32 error_mask;
b79480ba 3547 unsigned long irqflags;
a266c7d5 3548
a266c7d5 3549 /* Unmask the interrupts that we always want on. */
bbba0a97 3550 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 3551 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 3552 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3553 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3554 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3555 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3556 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3557
3558 enable_mask = ~dev_priv->irq_mask;
21ad8330
VS		 3559 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3560 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
bbba0a97
CW		 3561 enable_mask |= I915_USER_INTERRUPT;
3562
3563 if (IS_G4X(dev))
3564 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5 3565
b79480ba
DV		 3566 /* Interrupt setup is already guaranteed to be single-threaded, this is
3567 * just to make the assert_spin_locked check happy. */
3568 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3b6c42e8
DV		 3569 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE);
3570 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3571 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
b79480ba 3572 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
a266c7d5 3573
a266c7d5
CW		 3574 /*
3575 * Enable some error detection, note the instruction error mask
3576 * bit is reserved, so we leave it masked.
3577 */
3578 if (IS_G4X(dev)) {
3579 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3580 GM45_ERROR_MEM_PRIV |
3581 GM45_ERROR_CP_PRIV |
3582 I915_ERROR_MEMORY_REFRESH);
3583 } else {
3584 error_mask = ~(I915_ERROR_PAGE_TABLE |
3585 I915_ERROR_MEMORY_REFRESH);
3586 }
3587 I915_WRITE(EMR, error_mask);
3588
3589 I915_WRITE(IMR, dev_priv->irq_mask);
3590 I915_WRITE(IER, enable_mask);
3591 POSTING_READ(IER);
3592
20afbda2
DV		 3593 I915_WRITE(PORT_HOTPLUG_EN, 0);
3594 POSTING_READ(PORT_HOTPLUG_EN);
3595
f49e38dd 3596 i915_enable_asle_pipestat(dev);
20afbda2
DV		 3597
3598 return 0;
3599}
3600
bac56d5b 3601static void i915_hpd_irq_setup(struct drm_device *dev)
20afbda2
DV		 3602{
3603 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e5868a31 3604 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed 3605 struct intel_encoder *intel_encoder;
20afbda2
DV		 3606 u32 hotplug_en;
3607
b5ea2d56
DV		 3608 assert_spin_locked(&dev_priv->irq_lock);
3609
bac56d5b
EE		 3610 if (I915_HAS_HOTPLUG(dev)) {
3611 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3612 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3613 /* Note HDMI and DP share hotplug bits */
e5868a31 3614 /* enable bits are the same for all generations */
cd569aed
EE		 3615 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3616 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3617 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
bac56d5b
EE		 3618 /* Programming the CRT detection parameters tends
3619 to generate a spurious hotplug event about three
3620 seconds later. So just do it once.
3621 */
3622 if (IS_G4X(dev))
3623 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
85fc95ba 3624 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
bac56d5b 3625 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
a266c7d5 3626
bac56d5b
EE		 3627 /* Ignore TV since it's buggy */
3628 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3629 }
a266c7d5
CW		 3630}
3631
ff1f525e 3632static irqreturn_t i965_irq_handler(int irq, void *arg)
a266c7d5
CW		 3633{
3634 struct drm_device *dev = (struct drm_device *) arg;
3635 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 3636 u32 iir, new_iir;
3637 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5 3638 unsigned long irqflags;
a266c7d5 3639 int ret = IRQ_NONE, pipe;
21ad8330
VS		 3640 u32 flip_mask =
3641 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3642 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
a266c7d5 3643
a266c7d5
CW		 3644 iir = I915_READ(IIR);
3645
a266c7d5 3646 for (;;) {
501e01d7 3647 bool irq_received = (iir & ~flip_mask) != 0;
2c8ba29f
CW		 3648 bool blc_event = false;
3649
a266c7d5
CW		 3650 /* Can't rely on pipestat interrupt bit in iir as it might
3651 * have been cleared after the pipestat interrupt was received.
3652 * It doesn't set the bit in iir again, but it still produces
3653 * interrupts (for non-MSI).
3654 */
3655 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3656 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3657 i915_handle_error(dev, false);
3658
3659 for_each_pipe(pipe) {
3660 int reg = PIPESTAT(pipe);
3661 pipe_stats[pipe] = I915_READ(reg);
3662
3663 /*
3664 * Clear the PIPE*STAT regs before the IIR
3665 */
3666 if (pipe_stats[pipe] & 0x8000ffff) {
a266c7d5 3667 I915_WRITE(reg, pipe_stats[pipe]);
501e01d7 3668 irq_received = true;
a266c7d5
CW		 3669 }
3670 }
3671 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3672
3673 if (!irq_received)
3674 break;
3675
3676 ret = IRQ_HANDLED;
3677
3678 /* Consume port. Then clear IIR or we'll miss events */
adca4730 3679 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
a266c7d5 3680 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04
EE		 3681 u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
3682 HOTPLUG_INT_STATUS_G4X :
4f7fd709 3683 HOTPLUG_INT_STATUS_I915);
a266c7d5 3684
91d131d2 3685 intel_hpd_irq_handler(dev, hotplug_trigger,
704cfb87 3686 IS_G4X(dev) ? hpd_status_g4x : hpd_status_i915);
91d131d2 3687
4aeebd74
DV		 3688 if (IS_G4X(dev) &&
3689 (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X))
3690 dp_aux_irq_handler(dev);
3691
a266c7d5
CW		 3692 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3693 I915_READ(PORT_HOTPLUG_STAT);
3694 }
3695
21ad8330 3696 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 3697 new_iir = I915_READ(IIR); /* Flush posted writes */
3698
a266c7d5
CW		 3699 if (iir & I915_USER_INTERRUPT)
3700 notify_ring(dev, &dev_priv->ring[RCS]);
3701 if (iir & I915_BSD_USER_INTERRUPT)
3702 notify_ring(dev, &dev_priv->ring[VCS]);
3703
a266c7d5 3704 for_each_pipe(pipe) {
2c8ba29f 3705 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3706 i915_handle_vblank(dev, pipe, pipe, iir))
3707 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
a266c7d5
CW		 3708
3709 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3710 blc_event = true;
4356d586
DV		 3711
3712 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
277de95e 3713 i9xx_pipe_crc_irq_handler(dev, pipe);
a266c7d5 3714
2d9d2b0b
VS		 3715 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3716 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
fc2c807b 3717 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
2d9d2b0b 3718 }
a266c7d5
CW		 3719
3720 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3721 intel_opregion_asle_intr(dev);
3722
515ac2bb
DV		 3723 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3724 gmbus_irq_handler(dev);
3725
a266c7d5
CW		 3726 /* With MSI, interrupts are only generated when iir
3727 * transitions from zero to nonzero. If another bit got
3728 * set while we were handling the existing iir bits, then
3729 * we would never get another interrupt.
3730 *
3731 * This is fine on non-MSI as well, as if we hit this path
3732 * we avoid exiting the interrupt handler only to generate
3733 * another one.
3734 *
3735 * Note that for MSI this could cause a stray interrupt report
3736 * if an interrupt landed in the time between writing IIR and
3737 * the posting read. This should be rare enough to never
3738 * trigger the 99% of 100,000 interrupts test for disabling
3739 * stray interrupts.
3740 */
3741 iir = new_iir;
3742 }
3743
d05c617e 3744 i915_update_dri1_breadcrumb(dev);
2c8ba29f 3745
a266c7d5
CW		 3746 return ret;
3747}
3748
3749static void i965_irq_uninstall(struct drm_device * dev)
3750{
3751 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3752 int pipe;
3753
3754 if (!dev_priv)
3755 return;
3756
3ca1cced 3757 intel_hpd_irq_uninstall(dev_priv);
ac4c16c5 3758
adca4730
CW		 3759 I915_WRITE(PORT_HOTPLUG_EN, 0);
3760 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 3761
3762 I915_WRITE(HWSTAM, 0xffffffff);
3763 for_each_pipe(pipe)
3764 I915_WRITE(PIPESTAT(pipe), 0);
3765 I915_WRITE(IMR, 0xffffffff);
3766 I915_WRITE(IER, 0x0);
3767
3768 for_each_pipe(pipe)
3769 I915_WRITE(PIPESTAT(pipe),
3770 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3771 I915_WRITE(IIR, I915_READ(IIR));
3772}
3773
3ca1cced 3774static void intel_hpd_irq_reenable(unsigned long data)
ac4c16c5
EE		 3775{
3776 drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3777 struct drm_device *dev = dev_priv->dev;
3778 struct drm_mode_config *mode_config = &dev->mode_config;
3779 unsigned long irqflags;
3780 int i;
3781
3782 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3783 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3784 struct drm_connector *connector;
3785
3786 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3787 continue;
3788
3789 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3790
3791 list_for_each_entry(connector, &mode_config->connector_list, head) {
3792 struct intel_connector *intel_connector = to_intel_connector(connector);
3793
3794 if (intel_connector->encoder->hpd_pin == i) {
3795 if (connector->polled != intel_connector->polled)
3796 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3797 drm_get_connector_name(connector));
3798 connector->polled = intel_connector->polled;
3799 if (!connector->polled)
3800 connector->polled = DRM_CONNECTOR_POLL_HPD;
3801 }
3802 }
3803 }
3804 if (dev_priv->display.hpd_irq_setup)
3805 dev_priv->display.hpd_irq_setup(dev);
3806 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3807}
3808
f71d4af4
JB		 3809void intel_irq_init(struct drm_device *dev)
3810{
8b2e326d
CW		 3811 struct drm_i915_private *dev_priv = dev->dev_private;
3812
3813 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
99584db3 3814 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
c6a828d3 3815 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
a4da4fa4 3816 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
8b2e326d 3817
99584db3
DV		 3818 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3819 i915_hangcheck_elapsed,
61bac78e 3820 (unsigned long) dev);
3ca1cced 3821 setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable,
ac4c16c5 3822 (unsigned long) dev_priv);
61bac78e 3823
97a19a24 3824 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
9ee32fea 3825
4cdb83ec
VS		 3826 if (IS_GEN2(dev)) {
3827 dev->max_vblank_count = 0;
3828 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
3829 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 3830 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3831 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
391f75e2
VS		 3832 } else {
3833 dev->driver->get_vblank_counter = i915_get_vblank_counter;
3834 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
f71d4af4
JB		 3835 }
3836
c2baf4b7 3837 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
c3613de9 3838 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
c2baf4b7
VS		 3839 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3840 }
f71d4af4 3841
7e231dbe
JB		 3842 if (IS_VALLEYVIEW(dev)) {
3843 dev->driver->irq_handler = valleyview_irq_handler;
3844 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3845 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3846 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3847 dev->driver->enable_vblank = valleyview_enable_vblank;
3848 dev->driver->disable_vblank = valleyview_disable_vblank;
fa00abe0 3849 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
abd58f01
BW		 3850 } else if (IS_GEN8(dev)) {
3851 dev->driver->irq_handler = gen8_irq_handler;
3852 dev->driver->irq_preinstall = gen8_irq_preinstall;
3853 dev->driver->irq_postinstall = gen8_irq_postinstall;
3854 dev->driver->irq_uninstall = gen8_irq_uninstall;
3855 dev->driver->enable_vblank = gen8_enable_vblank;
3856 dev->driver->disable_vblank = gen8_disable_vblank;
3857 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4
JB		 3858 } else if (HAS_PCH_SPLIT(dev)) {
3859 dev->driver->irq_handler = ironlake_irq_handler;
3860 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3861 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3862 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3863 dev->driver->enable_vblank = ironlake_enable_vblank;
3864 dev->driver->disable_vblank = ironlake_disable_vblank;
82a28bcf 3865 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4 3866 } else {
c2798b19
CW		 3867 if (INTEL_INFO(dev)->gen == 2) {
3868 dev->driver->irq_preinstall = i8xx_irq_preinstall;
3869 dev->driver->irq_postinstall = i8xx_irq_postinstall;
3870 dev->driver->irq_handler = i8xx_irq_handler;
3871 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5
CW		 3872 } else if (INTEL_INFO(dev)->gen == 3) {
3873 dev->driver->irq_preinstall = i915_irq_preinstall;
3874 dev->driver->irq_postinstall = i915_irq_postinstall;
3875 dev->driver->irq_uninstall = i915_irq_uninstall;
3876 dev->driver->irq_handler = i915_irq_handler;
20afbda2 3877 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 3878 } else {
a266c7d5
CW		 3879 dev->driver->irq_preinstall = i965_irq_preinstall;
3880 dev->driver->irq_postinstall = i965_irq_postinstall;
3881 dev->driver->irq_uninstall = i965_irq_uninstall;
3882 dev->driver->irq_handler = i965_irq_handler;
bac56d5b 3883 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 3884 }
f71d4af4
JB		 3885 dev->driver->enable_vblank = i915_enable_vblank;
3886 dev->driver->disable_vblank = i915_disable_vblank;
3887 }
3888}
20afbda2
DV		 3889
3890void intel_hpd_init(struct drm_device *dev)
3891{
3892 struct drm_i915_private *dev_priv = dev->dev_private;
821450c6
EE		 3893 struct drm_mode_config *mode_config = &dev->mode_config;
3894 struct drm_connector *connector;
b5ea2d56 3895 unsigned long irqflags;
821450c6 3896 int i;
20afbda2 3897
821450c6
EE		 3898 for (i = 1; i < HPD_NUM_PINS; i++) {
3899 dev_priv->hpd_stats[i].hpd_cnt = 0;
3900 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3901 }
3902 list_for_each_entry(connector, &mode_config->connector_list, head) {
3903 struct intel_connector *intel_connector = to_intel_connector(connector);
3904 connector->polled = intel_connector->polled;
3905 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3906 connector->polled = DRM_CONNECTOR_POLL_HPD;
3907 }
b5ea2d56
DV		 3908
3909 /* Interrupt setup is already guaranteed to be single-threaded, this is
3910 * just to make the assert_spin_locked checks happy. */
3911 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
20afbda2
DV		 3912 if (dev_priv->display.hpd_irq_setup)
3913 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 3914 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
20afbda2 3915}
c67a470b
PZ		 3916
3917/* Disable interrupts so we can allow Package C8+. */
3918void hsw_pc8_disable_interrupts(struct drm_device *dev)
3919{
3920 struct drm_i915_private *dev_priv = dev->dev_private;
3921 unsigned long irqflags;
3922
3923 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3924
3925 dev_priv->pc8.regsave.deimr = I915_READ(DEIMR);
3926 dev_priv->pc8.regsave.sdeimr = I915_READ(SDEIMR);
3927 dev_priv->pc8.regsave.gtimr = I915_READ(GTIMR);
3928 dev_priv->pc8.regsave.gtier = I915_READ(GTIER);
3929 dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR);
3930
1f2d4531
PZ		 3931 ironlake_disable_display_irq(dev_priv, 0xffffffff);
3932 ibx_disable_display_interrupt(dev_priv, 0xffffffff);
c67a470b
PZ		 3933 ilk_disable_gt_irq(dev_priv, 0xffffffff);
3934 snb_disable_pm_irq(dev_priv, 0xffffffff);
3935
3936 dev_priv->pc8.irqs_disabled = true;
3937
3938 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3939}
3940
3941/* Restore interrupts so we can recover from Package C8+. */
3942void hsw_pc8_restore_interrupts(struct drm_device *dev)
3943{
3944 struct drm_i915_private *dev_priv = dev->dev_private;
3945 unsigned long irqflags;
1f2d4531 3946 uint32_t val;
c67a470b
PZ		 3947
3948 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3949
3950 val = I915_READ(DEIMR);
1f2d4531 3951 WARN(val != 0xffffffff, "DEIMR is 0x%08x\n", val);
c67a470b 3952
1f2d4531
PZ		 3953 val = I915_READ(SDEIMR);
3954 WARN(val != 0xffffffff, "SDEIMR is 0x%08x\n", val);
c67a470b
PZ		 3955
3956 val = I915_READ(GTIMR);
1f2d4531 3957 WARN(val != 0xffffffff, "GTIMR is 0x%08x\n", val);
c67a470b
PZ		 3958
3959 val = I915_READ(GEN6_PMIMR);
1f2d4531 3960 WARN(val != 0xffffffff, "GEN6_PMIMR is 0x%08x\n", val);
c67a470b
PZ		 3961
3962 dev_priv->pc8.irqs_disabled = false;
3963
3964 ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr);
1f2d4531 3965 ibx_enable_display_interrupt(dev_priv, ~dev_priv->pc8.regsave.sdeimr);
c67a470b
PZ		 3966 ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr);
3967 snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr);
3968 I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier);
3969
3970 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3971}
Ubuntu Artful kernel mirror