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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
63eeaf38 | 31 | #include <linux/sysrq.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
b2c88f5b | 33 | #include <linux/circ_buf.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/i915_drm.h> | |
1da177e4 | 36 | #include "i915_drv.h" |
1c5d22f7 | 37 | #include "i915_trace.h" |
79e53945 | 38 | #include "intel_drv.h" |
1da177e4 | 39 | |
fca52a55 DV |
40 | /** |
41 | * DOC: interrupt handling | |
42 | * | |
43 | * These functions provide the basic support for enabling and disabling the | |
44 | * interrupt handling support. There's a lot more functionality in i915_irq.c | |
45 | * and related files, but that will be described in separate chapters. | |
46 | */ | |
47 | ||
e5868a31 EE |
48 | static const u32 hpd_ibx[] = { |
49 | [HPD_CRT] = SDE_CRT_HOTPLUG, | |
50 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, | |
51 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG, | |
52 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG, | |
53 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG | |
54 | }; | |
55 | ||
56 | static const u32 hpd_cpt[] = { | |
57 | [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, | |
73c352a2 | 58 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, |
e5868a31 EE |
59 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
60 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
61 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT | |
62 | }; | |
63 | ||
64 | static const u32 hpd_mask_i915[] = { | |
65 | [HPD_CRT] = CRT_HOTPLUG_INT_EN, | |
66 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, | |
67 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, | |
68 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, | |
69 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, | |
70 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN | |
71 | }; | |
72 | ||
704cfb87 | 73 | static const u32 hpd_status_g4x[] = { |
e5868a31 EE |
74 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
75 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, | |
76 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, | |
77 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
78 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
79 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
80 | }; | |
81 | ||
e5868a31 EE |
82 | static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ |
83 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, | |
84 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, | |
85 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, | |
86 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
87 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
88 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
89 | }; | |
90 | ||
5c502442 | 91 | /* IIR can theoretically queue up two events. Be paranoid. */ |
f86f3fb0 | 92 | #define GEN8_IRQ_RESET_NDX(type, which) do { \ |
5c502442 PZ |
93 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ |
94 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
95 | I915_WRITE(GEN8_##type##_IER(which), 0); \ | |
96 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
97 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
98 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
99 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
100 | } while (0) | |
101 | ||
f86f3fb0 | 102 | #define GEN5_IRQ_RESET(type) do { \ |
a9d356a6 | 103 | I915_WRITE(type##IMR, 0xffffffff); \ |
5c502442 | 104 | POSTING_READ(type##IMR); \ |
a9d356a6 | 105 | I915_WRITE(type##IER, 0); \ |
5c502442 PZ |
106 | I915_WRITE(type##IIR, 0xffffffff); \ |
107 | POSTING_READ(type##IIR); \ | |
108 | I915_WRITE(type##IIR, 0xffffffff); \ | |
109 | POSTING_READ(type##IIR); \ | |
a9d356a6 PZ |
110 | } while (0) |
111 | ||
337ba017 PZ |
112 | /* |
113 | * We should clear IMR at preinstall/uninstall, and just check at postinstall. | |
114 | */ | |
115 | #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \ | |
116 | u32 val = I915_READ(reg); \ | |
117 | if (val) { \ | |
118 | WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \ | |
119 | (reg), val); \ | |
120 | I915_WRITE((reg), 0xffffffff); \ | |
121 | POSTING_READ(reg); \ | |
122 | I915_WRITE((reg), 0xffffffff); \ | |
123 | POSTING_READ(reg); \ | |
124 | } \ | |
125 | } while (0) | |
126 | ||
35079899 | 127 | #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \ |
337ba017 | 128 | GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \ |
35079899 PZ |
129 | I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \ |
130 | I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \ | |
131 | POSTING_READ(GEN8_##type##_IER(which)); \ | |
132 | } while (0) | |
133 | ||
134 | #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \ | |
337ba017 | 135 | GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \ |
35079899 PZ |
136 | I915_WRITE(type##IMR, (imr_val)); \ |
137 | I915_WRITE(type##IER, (ier_val)); \ | |
138 | POSTING_READ(type##IER); \ | |
139 | } while (0) | |
140 | ||
036a4a7d | 141 | /* For display hotplug interrupt */ |
995b6762 | 142 | static void |
2d1013dd | 143 | ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask) |
036a4a7d | 144 | { |
4bc9d430 DV |
145 | assert_spin_locked(&dev_priv->irq_lock); |
146 | ||
9df7575f | 147 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 148 | return; |
c67a470b | 149 | |
1ec14ad3 CW |
150 | if ((dev_priv->irq_mask & mask) != 0) { |
151 | dev_priv->irq_mask &= ~mask; | |
152 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 153 | POSTING_READ(DEIMR); |
036a4a7d ZW |
154 | } |
155 | } | |
156 | ||
0ff9800a | 157 | static void |
2d1013dd | 158 | ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask) |
036a4a7d | 159 | { |
4bc9d430 DV |
160 | assert_spin_locked(&dev_priv->irq_lock); |
161 | ||
06ffc778 | 162 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 163 | return; |
c67a470b | 164 | |
1ec14ad3 CW |
165 | if ((dev_priv->irq_mask & mask) != mask) { |
166 | dev_priv->irq_mask |= mask; | |
167 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 168 | POSTING_READ(DEIMR); |
036a4a7d ZW |
169 | } |
170 | } | |
171 | ||
43eaea13 PZ |
172 | /** |
173 | * ilk_update_gt_irq - update GTIMR | |
174 | * @dev_priv: driver private | |
175 | * @interrupt_mask: mask of interrupt bits to update | |
176 | * @enabled_irq_mask: mask of interrupt bits to enable | |
177 | */ | |
178 | static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, | |
179 | uint32_t interrupt_mask, | |
180 | uint32_t enabled_irq_mask) | |
181 | { | |
182 | assert_spin_locked(&dev_priv->irq_lock); | |
183 | ||
9df7575f | 184 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 185 | return; |
c67a470b | 186 | |
43eaea13 PZ |
187 | dev_priv->gt_irq_mask &= ~interrupt_mask; |
188 | dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); | |
189 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
190 | POSTING_READ(GTIMR); | |
191 | } | |
192 | ||
480c8033 | 193 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
43eaea13 PZ |
194 | { |
195 | ilk_update_gt_irq(dev_priv, mask, mask); | |
196 | } | |
197 | ||
480c8033 | 198 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
43eaea13 PZ |
199 | { |
200 | ilk_update_gt_irq(dev_priv, mask, 0); | |
201 | } | |
202 | ||
edbfdb45 PZ |
203 | /** |
204 | * snb_update_pm_irq - update GEN6_PMIMR | |
205 | * @dev_priv: driver private | |
206 | * @interrupt_mask: mask of interrupt bits to update | |
207 | * @enabled_irq_mask: mask of interrupt bits to enable | |
208 | */ | |
209 | static void snb_update_pm_irq(struct drm_i915_private *dev_priv, | |
210 | uint32_t interrupt_mask, | |
211 | uint32_t enabled_irq_mask) | |
212 | { | |
605cd25b | 213 | uint32_t new_val; |
edbfdb45 PZ |
214 | |
215 | assert_spin_locked(&dev_priv->irq_lock); | |
216 | ||
9df7575f | 217 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 218 | return; |
c67a470b | 219 | |
605cd25b | 220 | new_val = dev_priv->pm_irq_mask; |
f52ecbcf PZ |
221 | new_val &= ~interrupt_mask; |
222 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
223 | ||
605cd25b PZ |
224 | if (new_val != dev_priv->pm_irq_mask) { |
225 | dev_priv->pm_irq_mask = new_val; | |
226 | I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask); | |
f52ecbcf PZ |
227 | POSTING_READ(GEN6_PMIMR); |
228 | } | |
edbfdb45 PZ |
229 | } |
230 | ||
480c8033 | 231 | void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
edbfdb45 PZ |
232 | { |
233 | snb_update_pm_irq(dev_priv, mask, mask); | |
234 | } | |
235 | ||
480c8033 | 236 | void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
edbfdb45 PZ |
237 | { |
238 | snb_update_pm_irq(dev_priv, mask, 0); | |
239 | } | |
240 | ||
8664281b PZ |
241 | static bool ivb_can_enable_err_int(struct drm_device *dev) |
242 | { | |
243 | struct drm_i915_private *dev_priv = dev->dev_private; | |
244 | struct intel_crtc *crtc; | |
245 | enum pipe pipe; | |
246 | ||
4bc9d430 DV |
247 | assert_spin_locked(&dev_priv->irq_lock); |
248 | ||
055e393f | 249 | for_each_pipe(dev_priv, pipe) { |
8664281b PZ |
250 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
251 | ||
252 | if (crtc->cpu_fifo_underrun_disabled) | |
253 | return false; | |
254 | } | |
255 | ||
256 | return true; | |
257 | } | |
258 | ||
0961021a BW |
259 | /** |
260 | * bdw_update_pm_irq - update GT interrupt 2 | |
261 | * @dev_priv: driver private | |
262 | * @interrupt_mask: mask of interrupt bits to update | |
263 | * @enabled_irq_mask: mask of interrupt bits to enable | |
264 | * | |
265 | * Copied from the snb function, updated with relevant register offsets | |
266 | */ | |
267 | static void bdw_update_pm_irq(struct drm_i915_private *dev_priv, | |
268 | uint32_t interrupt_mask, | |
269 | uint32_t enabled_irq_mask) | |
270 | { | |
271 | uint32_t new_val; | |
272 | ||
273 | assert_spin_locked(&dev_priv->irq_lock); | |
274 | ||
9df7575f | 275 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
0961021a BW |
276 | return; |
277 | ||
278 | new_val = dev_priv->pm_irq_mask; | |
279 | new_val &= ~interrupt_mask; | |
280 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
281 | ||
282 | if (new_val != dev_priv->pm_irq_mask) { | |
283 | dev_priv->pm_irq_mask = new_val; | |
284 | I915_WRITE(GEN8_GT_IMR(2), dev_priv->pm_irq_mask); | |
285 | POSTING_READ(GEN8_GT_IMR(2)); | |
286 | } | |
287 | } | |
288 | ||
480c8033 | 289 | void gen8_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
0961021a BW |
290 | { |
291 | bdw_update_pm_irq(dev_priv, mask, mask); | |
292 | } | |
293 | ||
480c8033 | 294 | void gen8_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
0961021a BW |
295 | { |
296 | bdw_update_pm_irq(dev_priv, mask, 0); | |
297 | } | |
298 | ||
8664281b PZ |
299 | static bool cpt_can_enable_serr_int(struct drm_device *dev) |
300 | { | |
301 | struct drm_i915_private *dev_priv = dev->dev_private; | |
302 | enum pipe pipe; | |
303 | struct intel_crtc *crtc; | |
304 | ||
fee884ed DV |
305 | assert_spin_locked(&dev_priv->irq_lock); |
306 | ||
055e393f | 307 | for_each_pipe(dev_priv, pipe) { |
8664281b PZ |
308 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
309 | ||
310 | if (crtc->pch_fifo_underrun_disabled) | |
311 | return false; | |
312 | } | |
313 | ||
314 | return true; | |
315 | } | |
316 | ||
56b80e1f VS |
317 | void i9xx_check_fifo_underruns(struct drm_device *dev) |
318 | { | |
319 | struct drm_i915_private *dev_priv = dev->dev_private; | |
320 | struct intel_crtc *crtc; | |
56b80e1f | 321 | |
13321786 | 322 | spin_lock_irq(&dev_priv->irq_lock); |
56b80e1f VS |
323 | |
324 | for_each_intel_crtc(dev, crtc) { | |
325 | u32 reg = PIPESTAT(crtc->pipe); | |
326 | u32 pipestat; | |
327 | ||
328 | if (crtc->cpu_fifo_underrun_disabled) | |
329 | continue; | |
330 | ||
331 | pipestat = I915_READ(reg) & 0xffff0000; | |
332 | if ((pipestat & PIPE_FIFO_UNDERRUN_STATUS) == 0) | |
333 | continue; | |
334 | ||
335 | I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS); | |
336 | POSTING_READ(reg); | |
337 | ||
338 | DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe)); | |
339 | } | |
340 | ||
13321786 | 341 | spin_unlock_irq(&dev_priv->irq_lock); |
56b80e1f VS |
342 | } |
343 | ||
e69abff0 | 344 | static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev, |
2ae2a50c DV |
345 | enum pipe pipe, |
346 | bool enable, bool old) | |
2d9d2b0b VS |
347 | { |
348 | struct drm_i915_private *dev_priv = dev->dev_private; | |
349 | u32 reg = PIPESTAT(pipe); | |
e69abff0 | 350 | u32 pipestat = I915_READ(reg) & 0xffff0000; |
2d9d2b0b VS |
351 | |
352 | assert_spin_locked(&dev_priv->irq_lock); | |
353 | ||
e69abff0 VS |
354 | if (enable) { |
355 | I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS); | |
356 | POSTING_READ(reg); | |
357 | } else { | |
2ae2a50c | 358 | if (old && pipestat & PIPE_FIFO_UNDERRUN_STATUS) |
e69abff0 VS |
359 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); |
360 | } | |
2d9d2b0b VS |
361 | } |
362 | ||
8664281b PZ |
363 | static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev, |
364 | enum pipe pipe, bool enable) | |
365 | { | |
366 | struct drm_i915_private *dev_priv = dev->dev_private; | |
367 | uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN : | |
368 | DE_PIPEB_FIFO_UNDERRUN; | |
369 | ||
370 | if (enable) | |
371 | ironlake_enable_display_irq(dev_priv, bit); | |
372 | else | |
373 | ironlake_disable_display_irq(dev_priv, bit); | |
374 | } | |
375 | ||
376 | static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev, | |
2ae2a50c DV |
377 | enum pipe pipe, |
378 | bool enable, bool old) | |
8664281b PZ |
379 | { |
380 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8664281b | 381 | if (enable) { |
7336df65 DV |
382 | I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); |
383 | ||
8664281b PZ |
384 | if (!ivb_can_enable_err_int(dev)) |
385 | return; | |
386 | ||
8664281b PZ |
387 | ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB); |
388 | } else { | |
389 | ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB); | |
7336df65 | 390 | |
2ae2a50c DV |
391 | if (old && |
392 | I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { | |
823c6909 VS |
393 | DRM_ERROR("uncleared fifo underrun on pipe %c\n", |
394 | pipe_name(pipe)); | |
7336df65 | 395 | } |
8664281b PZ |
396 | } |
397 | } | |
398 | ||
38d83c96 DV |
399 | static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev, |
400 | enum pipe pipe, bool enable) | |
401 | { | |
402 | struct drm_i915_private *dev_priv = dev->dev_private; | |
403 | ||
404 | assert_spin_locked(&dev_priv->irq_lock); | |
405 | ||
406 | if (enable) | |
407 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN; | |
408 | else | |
409 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN; | |
410 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
411 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
412 | } | |
413 | ||
fee884ed DV |
414 | /** |
415 | * ibx_display_interrupt_update - update SDEIMR | |
416 | * @dev_priv: driver private | |
417 | * @interrupt_mask: mask of interrupt bits to update | |
418 | * @enabled_irq_mask: mask of interrupt bits to enable | |
419 | */ | |
420 | static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, | |
421 | uint32_t interrupt_mask, | |
422 | uint32_t enabled_irq_mask) | |
423 | { | |
424 | uint32_t sdeimr = I915_READ(SDEIMR); | |
425 | sdeimr &= ~interrupt_mask; | |
426 | sdeimr |= (~enabled_irq_mask & interrupt_mask); | |
427 | ||
428 | assert_spin_locked(&dev_priv->irq_lock); | |
429 | ||
9df7575f | 430 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 431 | return; |
c67a470b | 432 | |
fee884ed DV |
433 | I915_WRITE(SDEIMR, sdeimr); |
434 | POSTING_READ(SDEIMR); | |
435 | } | |
436 | #define ibx_enable_display_interrupt(dev_priv, bits) \ | |
437 | ibx_display_interrupt_update((dev_priv), (bits), (bits)) | |
438 | #define ibx_disable_display_interrupt(dev_priv, bits) \ | |
439 | ibx_display_interrupt_update((dev_priv), (bits), 0) | |
440 | ||
de28075d DV |
441 | static void ibx_set_fifo_underrun_reporting(struct drm_device *dev, |
442 | enum transcoder pch_transcoder, | |
8664281b PZ |
443 | bool enable) |
444 | { | |
8664281b | 445 | struct drm_i915_private *dev_priv = dev->dev_private; |
de28075d DV |
446 | uint32_t bit = (pch_transcoder == TRANSCODER_A) ? |
447 | SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER; | |
8664281b PZ |
448 | |
449 | if (enable) | |
fee884ed | 450 | ibx_enable_display_interrupt(dev_priv, bit); |
8664281b | 451 | else |
fee884ed | 452 | ibx_disable_display_interrupt(dev_priv, bit); |
8664281b PZ |
453 | } |
454 | ||
455 | static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, | |
456 | enum transcoder pch_transcoder, | |
2ae2a50c | 457 | bool enable, bool old) |
8664281b PZ |
458 | { |
459 | struct drm_i915_private *dev_priv = dev->dev_private; | |
460 | ||
461 | if (enable) { | |
1dd246fb DV |
462 | I915_WRITE(SERR_INT, |
463 | SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); | |
464 | ||
8664281b PZ |
465 | if (!cpt_can_enable_serr_int(dev)) |
466 | return; | |
467 | ||
fee884ed | 468 | ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
8664281b | 469 | } else { |
fee884ed | 470 | ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
1dd246fb | 471 | |
2ae2a50c DV |
472 | if (old && I915_READ(SERR_INT) & |
473 | SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) { | |
823c6909 VS |
474 | DRM_ERROR("uncleared pch fifo underrun on pch transcoder %c\n", |
475 | transcoder_name(pch_transcoder)); | |
1dd246fb | 476 | } |
8664281b | 477 | } |
8664281b PZ |
478 | } |
479 | ||
480 | /** | |
481 | * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages | |
482 | * @dev: drm device | |
483 | * @pipe: pipe | |
484 | * @enable: true if we want to report FIFO underrun errors, false otherwise | |
485 | * | |
486 | * This function makes us disable or enable CPU fifo underruns for a specific | |
487 | * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun | |
488 | * reporting for one pipe may also disable all the other CPU error interruts for | |
489 | * the other pipes, due to the fact that there's just one interrupt mask/enable | |
490 | * bit for all the pipes. | |
491 | * | |
492 | * Returns the previous state of underrun reporting. | |
493 | */ | |
c5ab3bc0 DV |
494 | static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, |
495 | enum pipe pipe, bool enable) | |
8664281b PZ |
496 | { |
497 | struct drm_i915_private *dev_priv = dev->dev_private; | |
498 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
499 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2ae2a50c | 500 | bool old; |
8664281b | 501 | |
77961eb9 ID |
502 | assert_spin_locked(&dev_priv->irq_lock); |
503 | ||
2ae2a50c | 504 | old = !intel_crtc->cpu_fifo_underrun_disabled; |
8664281b PZ |
505 | intel_crtc->cpu_fifo_underrun_disabled = !enable; |
506 | ||
a3ed6aad | 507 | if (HAS_GMCH_DISPLAY(dev)) |
2ae2a50c | 508 | i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old); |
2d9d2b0b | 509 | else if (IS_GEN5(dev) || IS_GEN6(dev)) |
8664281b PZ |
510 | ironlake_set_fifo_underrun_reporting(dev, pipe, enable); |
511 | else if (IS_GEN7(dev)) | |
2ae2a50c | 512 | ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old); |
a440ca6f | 513 | else if (IS_GEN8(dev) || IS_GEN9(dev)) |
38d83c96 | 514 | broadwell_set_fifo_underrun_reporting(dev, pipe, enable); |
8664281b | 515 | |
2ae2a50c | 516 | return old; |
f88d42f1 ID |
517 | } |
518 | ||
519 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, | |
520 | enum pipe pipe, bool enable) | |
521 | { | |
522 | struct drm_i915_private *dev_priv = dev->dev_private; | |
523 | unsigned long flags; | |
524 | bool ret; | |
525 | ||
526 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
527 | ret = __intel_set_cpu_fifo_underrun_reporting(dev, pipe, enable); | |
8664281b | 528 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
f88d42f1 | 529 | |
8664281b PZ |
530 | return ret; |
531 | } | |
532 | ||
91d181dd ID |
533 | static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev, |
534 | enum pipe pipe) | |
535 | { | |
536 | struct drm_i915_private *dev_priv = dev->dev_private; | |
537 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
538 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
539 | ||
540 | return !intel_crtc->cpu_fifo_underrun_disabled; | |
541 | } | |
542 | ||
8664281b PZ |
543 | /** |
544 | * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages | |
545 | * @dev: drm device | |
546 | * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) | |
547 | * @enable: true if we want to report FIFO underrun errors, false otherwise | |
548 | * | |
549 | * This function makes us disable or enable PCH fifo underruns for a specific | |
550 | * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO | |
551 | * underrun reporting for one transcoder may also disable all the other PCH | |
552 | * error interruts for the other transcoders, due to the fact that there's just | |
553 | * one interrupt mask/enable bit for all the transcoders. | |
554 | * | |
555 | * Returns the previous state of underrun reporting. | |
556 | */ | |
557 | bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, | |
558 | enum transcoder pch_transcoder, | |
559 | bool enable) | |
560 | { | |
561 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de28075d DV |
562 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder]; |
563 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8664281b | 564 | unsigned long flags; |
2ae2a50c | 565 | bool old; |
8664281b | 566 | |
de28075d DV |
567 | /* |
568 | * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT | |
569 | * has only one pch transcoder A that all pipes can use. To avoid racy | |
570 | * pch transcoder -> pipe lookups from interrupt code simply store the | |
571 | * underrun statistics in crtc A. Since we never expose this anywhere | |
572 | * nor use it outside of the fifo underrun code here using the "wrong" | |
573 | * crtc on LPT won't cause issues. | |
574 | */ | |
8664281b PZ |
575 | |
576 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
577 | ||
2ae2a50c | 578 | old = !intel_crtc->pch_fifo_underrun_disabled; |
8664281b PZ |
579 | intel_crtc->pch_fifo_underrun_disabled = !enable; |
580 | ||
581 | if (HAS_PCH_IBX(dev)) | |
de28075d | 582 | ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable); |
8664281b | 583 | else |
2ae2a50c | 584 | cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable, old); |
8664281b | 585 | |
8664281b | 586 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
2ae2a50c | 587 | return old; |
8664281b PZ |
588 | } |
589 | ||
590 | ||
b5ea642a | 591 | static void |
755e9019 ID |
592 | __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
593 | u32 enable_mask, u32 status_mask) | |
7c463586 | 594 | { |
46c06a30 | 595 | u32 reg = PIPESTAT(pipe); |
755e9019 | 596 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 597 | |
b79480ba | 598 | assert_spin_locked(&dev_priv->irq_lock); |
d518ce50 | 599 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
b79480ba | 600 | |
04feced9 VS |
601 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
602 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
603 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
604 | pipe_name(pipe), enable_mask, status_mask)) | |
755e9019 ID |
605 | return; |
606 | ||
607 | if ((pipestat & enable_mask) == enable_mask) | |
46c06a30 VS |
608 | return; |
609 | ||
91d181dd ID |
610 | dev_priv->pipestat_irq_mask[pipe] |= status_mask; |
611 | ||
46c06a30 | 612 | /* Enable the interrupt, clear any pending status */ |
755e9019 | 613 | pipestat |= enable_mask | status_mask; |
46c06a30 VS |
614 | I915_WRITE(reg, pipestat); |
615 | POSTING_READ(reg); | |
7c463586 KP |
616 | } |
617 | ||
b5ea642a | 618 | static void |
755e9019 ID |
619 | __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
620 | u32 enable_mask, u32 status_mask) | |
7c463586 | 621 | { |
46c06a30 | 622 | u32 reg = PIPESTAT(pipe); |
755e9019 | 623 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 624 | |
b79480ba | 625 | assert_spin_locked(&dev_priv->irq_lock); |
d518ce50 | 626 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
b79480ba | 627 | |
04feced9 VS |
628 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
629 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
630 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
631 | pipe_name(pipe), enable_mask, status_mask)) | |
46c06a30 VS |
632 | return; |
633 | ||
755e9019 ID |
634 | if ((pipestat & enable_mask) == 0) |
635 | return; | |
636 | ||
91d181dd ID |
637 | dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; |
638 | ||
755e9019 | 639 | pipestat &= ~enable_mask; |
46c06a30 VS |
640 | I915_WRITE(reg, pipestat); |
641 | POSTING_READ(reg); | |
7c463586 KP |
642 | } |
643 | ||
10c59c51 ID |
644 | static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask) |
645 | { | |
646 | u32 enable_mask = status_mask << 16; | |
647 | ||
648 | /* | |
724a6905 VS |
649 | * On pipe A we don't support the PSR interrupt yet, |
650 | * on pipe B and C the same bit MBZ. | |
10c59c51 ID |
651 | */ |
652 | if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV)) | |
653 | return 0; | |
724a6905 VS |
654 | /* |
655 | * On pipe B and C we don't support the PSR interrupt yet, on pipe | |
656 | * A the same bit is for perf counters which we don't use either. | |
657 | */ | |
658 | if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV)) | |
659 | return 0; | |
10c59c51 ID |
660 | |
661 | enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | | |
662 | SPRITE0_FLIP_DONE_INT_EN_VLV | | |
663 | SPRITE1_FLIP_DONE_INT_EN_VLV); | |
664 | if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV) | |
665 | enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV; | |
666 | if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV) | |
667 | enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; | |
668 | ||
669 | return enable_mask; | |
670 | } | |
671 | ||
755e9019 ID |
672 | void |
673 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
674 | u32 status_mask) | |
675 | { | |
676 | u32 enable_mask; | |
677 | ||
10c59c51 ID |
678 | if (IS_VALLEYVIEW(dev_priv->dev)) |
679 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, | |
680 | status_mask); | |
681 | else | |
682 | enable_mask = status_mask << 16; | |
755e9019 ID |
683 | __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
684 | } | |
685 | ||
686 | void | |
687 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
688 | u32 status_mask) | |
689 | { | |
690 | u32 enable_mask; | |
691 | ||
10c59c51 ID |
692 | if (IS_VALLEYVIEW(dev_priv->dev)) |
693 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, | |
694 | status_mask); | |
695 | else | |
696 | enable_mask = status_mask << 16; | |
755e9019 ID |
697 | __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
698 | } | |
699 | ||
01c66889 | 700 | /** |
f49e38dd | 701 | * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion |
01c66889 | 702 | */ |
f49e38dd | 703 | static void i915_enable_asle_pipestat(struct drm_device *dev) |
01c66889 | 704 | { |
2d1013dd | 705 | struct drm_i915_private *dev_priv = dev->dev_private; |
1ec14ad3 | 706 | |
f49e38dd JN |
707 | if (!dev_priv->opregion.asle || !IS_MOBILE(dev)) |
708 | return; | |
709 | ||
13321786 | 710 | spin_lock_irq(&dev_priv->irq_lock); |
01c66889 | 711 | |
755e9019 | 712 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); |
f898780b | 713 | if (INTEL_INFO(dev)->gen >= 4) |
3b6c42e8 | 714 | i915_enable_pipestat(dev_priv, PIPE_A, |
755e9019 | 715 | PIPE_LEGACY_BLC_EVENT_STATUS); |
1ec14ad3 | 716 | |
13321786 | 717 | spin_unlock_irq(&dev_priv->irq_lock); |
01c66889 ZY |
718 | } |
719 | ||
0a3e67a4 JB |
720 | /** |
721 | * i915_pipe_enabled - check if a pipe is enabled | |
722 | * @dev: DRM device | |
723 | * @pipe: pipe to check | |
724 | * | |
725 | * Reading certain registers when the pipe is disabled can hang the chip. | |
726 | * Use this routine to make sure the PLL is running and the pipe is active | |
727 | * before reading such registers if unsure. | |
728 | */ | |
729 | static int | |
730 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
731 | { | |
2d1013dd | 732 | struct drm_i915_private *dev_priv = dev->dev_private; |
702e7a56 | 733 | |
a01025af DV |
734 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
735 | /* Locking is horribly broken here, but whatever. */ | |
736 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
737 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
71f8ba6b | 738 | |
a01025af DV |
739 | return intel_crtc->active; |
740 | } else { | |
741 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; | |
742 | } | |
0a3e67a4 JB |
743 | } |
744 | ||
f75f3746 VS |
745 | /* |
746 | * This timing diagram depicts the video signal in and | |
747 | * around the vertical blanking period. | |
748 | * | |
749 | * Assumptions about the fictitious mode used in this example: | |
750 | * vblank_start >= 3 | |
751 | * vsync_start = vblank_start + 1 | |
752 | * vsync_end = vblank_start + 2 | |
753 | * vtotal = vblank_start + 3 | |
754 | * | |
755 | * start of vblank: | |
756 | * latch double buffered registers | |
757 | * increment frame counter (ctg+) | |
758 | * generate start of vblank interrupt (gen4+) | |
759 | * | | |
760 | * | frame start: | |
761 | * | generate frame start interrupt (aka. vblank interrupt) (gmch) | |
762 | * | may be shifted forward 1-3 extra lines via PIPECONF | |
763 | * | | | |
764 | * | | start of vsync: | |
765 | * | | generate vsync interrupt | |
766 | * | | | | |
767 | * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx | |
768 | * . \hs/ . \hs/ \hs/ \hs/ . \hs/ | |
769 | * ----va---> <-----------------vb--------------------> <--------va------------- | |
770 | * | | <----vs-----> | | |
771 | * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2) | |
772 | * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+) | |
773 | * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi) | |
774 | * | | | | |
775 | * last visible pixel first visible pixel | |
776 | * | increment frame counter (gen3/4) | |
777 | * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4) | |
778 | * | |
779 | * x = horizontal active | |
780 | * _ = horizontal blanking | |
781 | * hs = horizontal sync | |
782 | * va = vertical active | |
783 | * vb = vertical blanking | |
784 | * vs = vertical sync | |
785 | * vbs = vblank_start (number) | |
786 | * | |
787 | * Summary: | |
788 | * - most events happen at the start of horizontal sync | |
789 | * - frame start happens at the start of horizontal blank, 1-4 lines | |
790 | * (depending on PIPECONF settings) after the start of vblank | |
791 | * - gen3/4 pixel and frame counter are synchronized with the start | |
792 | * of horizontal active on the first line of vertical active | |
793 | */ | |
794 | ||
4cdb83ec VS |
795 | static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe) |
796 | { | |
797 | /* Gen2 doesn't have a hardware frame counter */ | |
798 | return 0; | |
799 | } | |
800 | ||
42f52ef8 KP |
801 | /* Called from drm generic code, passed a 'crtc', which |
802 | * we use as a pipe index | |
803 | */ | |
f71d4af4 | 804 | static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
0a3e67a4 | 805 | { |
2d1013dd | 806 | struct drm_i915_private *dev_priv = dev->dev_private; |
0a3e67a4 JB |
807 | unsigned long high_frame; |
808 | unsigned long low_frame; | |
0b2a8e09 | 809 | u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal; |
0a3e67a4 JB |
810 | |
811 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 812 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 813 | "pipe %c\n", pipe_name(pipe)); |
0a3e67a4 JB |
814 | return 0; |
815 | } | |
816 | ||
391f75e2 VS |
817 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
818 | struct intel_crtc *intel_crtc = | |
819 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
820 | const struct drm_display_mode *mode = | |
821 | &intel_crtc->config.adjusted_mode; | |
822 | ||
0b2a8e09 VS |
823 | htotal = mode->crtc_htotal; |
824 | hsync_start = mode->crtc_hsync_start; | |
825 | vbl_start = mode->crtc_vblank_start; | |
826 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
827 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
391f75e2 | 828 | } else { |
a2d213dd | 829 | enum transcoder cpu_transcoder = (enum transcoder) pipe; |
391f75e2 VS |
830 | |
831 | htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1; | |
0b2a8e09 | 832 | hsync_start = (I915_READ(HSYNC(cpu_transcoder)) & 0x1fff) + 1; |
391f75e2 | 833 | vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1; |
0b2a8e09 VS |
834 | if ((I915_READ(PIPECONF(cpu_transcoder)) & |
835 | PIPECONF_INTERLACE_MASK) != PIPECONF_PROGRESSIVE) | |
836 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
391f75e2 VS |
837 | } |
838 | ||
0b2a8e09 VS |
839 | /* Convert to pixel count */ |
840 | vbl_start *= htotal; | |
841 | ||
842 | /* Start of vblank event occurs at start of hsync */ | |
843 | vbl_start -= htotal - hsync_start; | |
844 | ||
9db4a9c7 JB |
845 | high_frame = PIPEFRAME(pipe); |
846 | low_frame = PIPEFRAMEPIXEL(pipe); | |
5eddb70b | 847 | |
0a3e67a4 JB |
848 | /* |
849 | * High & low register fields aren't synchronized, so make sure | |
850 | * we get a low value that's stable across two reads of the high | |
851 | * register. | |
852 | */ | |
853 | do { | |
5eddb70b | 854 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
391f75e2 | 855 | low = I915_READ(low_frame); |
5eddb70b | 856 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
0a3e67a4 JB |
857 | } while (high1 != high2); |
858 | ||
5eddb70b | 859 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
391f75e2 | 860 | pixel = low & PIPE_PIXEL_MASK; |
5eddb70b | 861 | low >>= PIPE_FRAME_LOW_SHIFT; |
391f75e2 VS |
862 | |
863 | /* | |
864 | * The frame counter increments at beginning of active. | |
865 | * Cook up a vblank counter by also checking the pixel | |
866 | * counter against vblank start. | |
867 | */ | |
edc08d0a | 868 | return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; |
0a3e67a4 JB |
869 | } |
870 | ||
f71d4af4 | 871 | static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
9880b7a5 | 872 | { |
2d1013dd | 873 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 874 | int reg = PIPE_FRMCOUNT_GM45(pipe); |
9880b7a5 JB |
875 | |
876 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 877 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 878 | "pipe %c\n", pipe_name(pipe)); |
9880b7a5 JB |
879 | return 0; |
880 | } | |
881 | ||
882 | return I915_READ(reg); | |
883 | } | |
884 | ||
ad3543ed MK |
885 | /* raw reads, only for fast reads of display block, no need for forcewake etc. */ |
886 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) | |
ad3543ed | 887 | |
a225f079 VS |
888 | static int __intel_get_crtc_scanline(struct intel_crtc *crtc) |
889 | { | |
890 | struct drm_device *dev = crtc->base.dev; | |
891 | struct drm_i915_private *dev_priv = dev->dev_private; | |
892 | const struct drm_display_mode *mode = &crtc->config.adjusted_mode; | |
893 | enum pipe pipe = crtc->pipe; | |
80715b2f | 894 | int position, vtotal; |
a225f079 | 895 | |
80715b2f | 896 | vtotal = mode->crtc_vtotal; |
a225f079 VS |
897 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
898 | vtotal /= 2; | |
899 | ||
900 | if (IS_GEN2(dev)) | |
901 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; | |
902 | else | |
903 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; | |
904 | ||
905 | /* | |
80715b2f VS |
906 | * See update_scanline_offset() for the details on the |
907 | * scanline_offset adjustment. | |
a225f079 | 908 | */ |
80715b2f | 909 | return (position + crtc->scanline_offset) % vtotal; |
a225f079 VS |
910 | } |
911 | ||
f71d4af4 | 912 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
abca9e45 VS |
913 | unsigned int flags, int *vpos, int *hpos, |
914 | ktime_t *stime, ktime_t *etime) | |
0af7e4df | 915 | { |
c2baf4b7 VS |
916 | struct drm_i915_private *dev_priv = dev->dev_private; |
917 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
918 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
919 | const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; | |
3aa18df8 | 920 | int position; |
78e8fc6b | 921 | int vbl_start, vbl_end, hsync_start, htotal, vtotal; |
0af7e4df MK |
922 | bool in_vbl = true; |
923 | int ret = 0; | |
ad3543ed | 924 | unsigned long irqflags; |
0af7e4df | 925 | |
c2baf4b7 | 926 | if (!intel_crtc->active) { |
0af7e4df | 927 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
9db4a9c7 | 928 | "pipe %c\n", pipe_name(pipe)); |
0af7e4df MK |
929 | return 0; |
930 | } | |
931 | ||
c2baf4b7 | 932 | htotal = mode->crtc_htotal; |
78e8fc6b | 933 | hsync_start = mode->crtc_hsync_start; |
c2baf4b7 VS |
934 | vtotal = mode->crtc_vtotal; |
935 | vbl_start = mode->crtc_vblank_start; | |
936 | vbl_end = mode->crtc_vblank_end; | |
0af7e4df | 937 | |
d31faf65 VS |
938 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
939 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
940 | vbl_end /= 2; | |
941 | vtotal /= 2; | |
942 | } | |
943 | ||
c2baf4b7 VS |
944 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; |
945 | ||
ad3543ed MK |
946 | /* |
947 | * Lock uncore.lock, as we will do multiple timing critical raw | |
948 | * register reads, potentially with preemption disabled, so the | |
949 | * following code must not block on uncore.lock. | |
950 | */ | |
951 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
78e8fc6b | 952 | |
ad3543ed MK |
953 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ |
954 | ||
955 | /* Get optional system timestamp before query. */ | |
956 | if (stime) | |
957 | *stime = ktime_get(); | |
958 | ||
7c06b08a | 959 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
0af7e4df MK |
960 | /* No obvious pixelcount register. Only query vertical |
961 | * scanout position from Display scan line register. | |
962 | */ | |
a225f079 | 963 | position = __intel_get_crtc_scanline(intel_crtc); |
0af7e4df MK |
964 | } else { |
965 | /* Have access to pixelcount since start of frame. | |
966 | * We can split this into vertical and horizontal | |
967 | * scanout position. | |
968 | */ | |
ad3543ed | 969 | position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; |
0af7e4df | 970 | |
3aa18df8 VS |
971 | /* convert to pixel counts */ |
972 | vbl_start *= htotal; | |
973 | vbl_end *= htotal; | |
974 | vtotal *= htotal; | |
78e8fc6b | 975 | |
7e78f1cb VS |
976 | /* |
977 | * In interlaced modes, the pixel counter counts all pixels, | |
978 | * so one field will have htotal more pixels. In order to avoid | |
979 | * the reported position from jumping backwards when the pixel | |
980 | * counter is beyond the length of the shorter field, just | |
981 | * clamp the position the length of the shorter field. This | |
982 | * matches how the scanline counter based position works since | |
983 | * the scanline counter doesn't count the two half lines. | |
984 | */ | |
985 | if (position >= vtotal) | |
986 | position = vtotal - 1; | |
987 | ||
78e8fc6b VS |
988 | /* |
989 | * Start of vblank interrupt is triggered at start of hsync, | |
990 | * just prior to the first active line of vblank. However we | |
991 | * consider lines to start at the leading edge of horizontal | |
992 | * active. So, should we get here before we've crossed into | |
993 | * the horizontal active of the first line in vblank, we would | |
994 | * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that, | |
995 | * always add htotal-hsync_start to the current pixel position. | |
996 | */ | |
997 | position = (position + htotal - hsync_start) % vtotal; | |
0af7e4df MK |
998 | } |
999 | ||
ad3543ed MK |
1000 | /* Get optional system timestamp after query. */ |
1001 | if (etime) | |
1002 | *etime = ktime_get(); | |
1003 | ||
1004 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ | |
1005 | ||
1006 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
1007 | ||
3aa18df8 VS |
1008 | in_vbl = position >= vbl_start && position < vbl_end; |
1009 | ||
1010 | /* | |
1011 | * While in vblank, position will be negative | |
1012 | * counting up towards 0 at vbl_end. And outside | |
1013 | * vblank, position will be positive counting | |
1014 | * up since vbl_end. | |
1015 | */ | |
1016 | if (position >= vbl_start) | |
1017 | position -= vbl_end; | |
1018 | else | |
1019 | position += vtotal - vbl_end; | |
0af7e4df | 1020 | |
7c06b08a | 1021 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
3aa18df8 VS |
1022 | *vpos = position; |
1023 | *hpos = 0; | |
1024 | } else { | |
1025 | *vpos = position / htotal; | |
1026 | *hpos = position - (*vpos * htotal); | |
1027 | } | |
0af7e4df | 1028 | |
0af7e4df MK |
1029 | /* In vblank? */ |
1030 | if (in_vbl) | |
3d3cbd84 | 1031 | ret |= DRM_SCANOUTPOS_IN_VBLANK; |
0af7e4df MK |
1032 | |
1033 | return ret; | |
1034 | } | |
1035 | ||
a225f079 VS |
1036 | int intel_get_crtc_scanline(struct intel_crtc *crtc) |
1037 | { | |
1038 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1039 | unsigned long irqflags; | |
1040 | int position; | |
1041 | ||
1042 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
1043 | position = __intel_get_crtc_scanline(crtc); | |
1044 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
1045 | ||
1046 | return position; | |
1047 | } | |
1048 | ||
f71d4af4 | 1049 | static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
0af7e4df MK |
1050 | int *max_error, |
1051 | struct timeval *vblank_time, | |
1052 | unsigned flags) | |
1053 | { | |
4041b853 | 1054 | struct drm_crtc *crtc; |
0af7e4df | 1055 | |
7eb552ae | 1056 | if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { |
4041b853 | 1057 | DRM_ERROR("Invalid crtc %d\n", pipe); |
0af7e4df MK |
1058 | return -EINVAL; |
1059 | } | |
1060 | ||
1061 | /* Get drm_crtc to timestamp: */ | |
4041b853 CW |
1062 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
1063 | if (crtc == NULL) { | |
1064 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
1065 | return -EINVAL; | |
1066 | } | |
1067 | ||
1068 | if (!crtc->enabled) { | |
1069 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); | |
1070 | return -EBUSY; | |
1071 | } | |
0af7e4df MK |
1072 | |
1073 | /* Helper routine in DRM core does all the work: */ | |
4041b853 CW |
1074 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
1075 | vblank_time, flags, | |
7da903ef VS |
1076 | crtc, |
1077 | &to_intel_crtc(crtc)->config.adjusted_mode); | |
0af7e4df MK |
1078 | } |
1079 | ||
67c347ff JN |
1080 | static bool intel_hpd_irq_event(struct drm_device *dev, |
1081 | struct drm_connector *connector) | |
321a1b30 EE |
1082 | { |
1083 | enum drm_connector_status old_status; | |
1084 | ||
1085 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); | |
1086 | old_status = connector->status; | |
1087 | ||
1088 | connector->status = connector->funcs->detect(connector, false); | |
67c347ff JN |
1089 | if (old_status == connector->status) |
1090 | return false; | |
1091 | ||
1092 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n", | |
321a1b30 | 1093 | connector->base.id, |
c23cc417 | 1094 | connector->name, |
67c347ff JN |
1095 | drm_get_connector_status_name(old_status), |
1096 | drm_get_connector_status_name(connector->status)); | |
1097 | ||
1098 | return true; | |
321a1b30 EE |
1099 | } |
1100 | ||
13cf5504 DA |
1101 | static void i915_digport_work_func(struct work_struct *work) |
1102 | { | |
1103 | struct drm_i915_private *dev_priv = | |
1104 | container_of(work, struct drm_i915_private, dig_port_work); | |
13cf5504 DA |
1105 | u32 long_port_mask, short_port_mask; |
1106 | struct intel_digital_port *intel_dig_port; | |
1107 | int i, ret; | |
1108 | u32 old_bits = 0; | |
1109 | ||
4cb21832 | 1110 | spin_lock_irq(&dev_priv->irq_lock); |
13cf5504 DA |
1111 | long_port_mask = dev_priv->long_hpd_port_mask; |
1112 | dev_priv->long_hpd_port_mask = 0; | |
1113 | short_port_mask = dev_priv->short_hpd_port_mask; | |
1114 | dev_priv->short_hpd_port_mask = 0; | |
4cb21832 | 1115 | spin_unlock_irq(&dev_priv->irq_lock); |
13cf5504 DA |
1116 | |
1117 | for (i = 0; i < I915_MAX_PORTS; i++) { | |
1118 | bool valid = false; | |
1119 | bool long_hpd = false; | |
1120 | intel_dig_port = dev_priv->hpd_irq_port[i]; | |
1121 | if (!intel_dig_port || !intel_dig_port->hpd_pulse) | |
1122 | continue; | |
1123 | ||
1124 | if (long_port_mask & (1 << i)) { | |
1125 | valid = true; | |
1126 | long_hpd = true; | |
1127 | } else if (short_port_mask & (1 << i)) | |
1128 | valid = true; | |
1129 | ||
1130 | if (valid) { | |
1131 | ret = intel_dig_port->hpd_pulse(intel_dig_port, long_hpd); | |
1132 | if (ret == true) { | |
1133 | /* if we get true fallback to old school hpd */ | |
1134 | old_bits |= (1 << intel_dig_port->base.hpd_pin); | |
1135 | } | |
1136 | } | |
1137 | } | |
1138 | ||
1139 | if (old_bits) { | |
4cb21832 | 1140 | spin_lock_irq(&dev_priv->irq_lock); |
13cf5504 | 1141 | dev_priv->hpd_event_bits |= old_bits; |
4cb21832 | 1142 | spin_unlock_irq(&dev_priv->irq_lock); |
13cf5504 DA |
1143 | schedule_work(&dev_priv->hotplug_work); |
1144 | } | |
1145 | } | |
1146 | ||
5ca58282 JB |
1147 | /* |
1148 | * Handle hotplug events outside the interrupt handler proper. | |
1149 | */ | |
ac4c16c5 EE |
1150 | #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000) |
1151 | ||
5ca58282 JB |
1152 | static void i915_hotplug_work_func(struct work_struct *work) |
1153 | { | |
2d1013dd JN |
1154 | struct drm_i915_private *dev_priv = |
1155 | container_of(work, struct drm_i915_private, hotplug_work); | |
5ca58282 | 1156 | struct drm_device *dev = dev_priv->dev; |
c31c4ba3 | 1157 | struct drm_mode_config *mode_config = &dev->mode_config; |
cd569aed EE |
1158 | struct intel_connector *intel_connector; |
1159 | struct intel_encoder *intel_encoder; | |
1160 | struct drm_connector *connector; | |
cd569aed | 1161 | bool hpd_disabled = false; |
321a1b30 | 1162 | bool changed = false; |
142e2398 | 1163 | u32 hpd_event_bits; |
4ef69c7a | 1164 | |
a65e34c7 | 1165 | mutex_lock(&mode_config->mutex); |
e67189ab JB |
1166 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); |
1167 | ||
4cb21832 | 1168 | spin_lock_irq(&dev_priv->irq_lock); |
142e2398 EE |
1169 | |
1170 | hpd_event_bits = dev_priv->hpd_event_bits; | |
1171 | dev_priv->hpd_event_bits = 0; | |
cd569aed EE |
1172 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
1173 | intel_connector = to_intel_connector(connector); | |
36cd7444 DA |
1174 | if (!intel_connector->encoder) |
1175 | continue; | |
cd569aed EE |
1176 | intel_encoder = intel_connector->encoder; |
1177 | if (intel_encoder->hpd_pin > HPD_NONE && | |
1178 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED && | |
1179 | connector->polled == DRM_CONNECTOR_POLL_HPD) { | |
1180 | DRM_INFO("HPD interrupt storm detected on connector %s: " | |
1181 | "switching from hotplug detection to polling\n", | |
c23cc417 | 1182 | connector->name); |
cd569aed EE |
1183 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED; |
1184 | connector->polled = DRM_CONNECTOR_POLL_CONNECT | |
1185 | | DRM_CONNECTOR_POLL_DISCONNECT; | |
1186 | hpd_disabled = true; | |
1187 | } | |
142e2398 EE |
1188 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { |
1189 | DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n", | |
c23cc417 | 1190 | connector->name, intel_encoder->hpd_pin); |
142e2398 | 1191 | } |
cd569aed EE |
1192 | } |
1193 | /* if there were no outputs to poll, poll was disabled, | |
1194 | * therefore make sure it's enabled when disabling HPD on | |
1195 | * some connectors */ | |
ac4c16c5 | 1196 | if (hpd_disabled) { |
cd569aed | 1197 | drm_kms_helper_poll_enable(dev); |
6323751d ID |
1198 | mod_delayed_work(system_wq, &dev_priv->hotplug_reenable_work, |
1199 | msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY)); | |
ac4c16c5 | 1200 | } |
cd569aed | 1201 | |
4cb21832 | 1202 | spin_unlock_irq(&dev_priv->irq_lock); |
cd569aed | 1203 | |
321a1b30 EE |
1204 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
1205 | intel_connector = to_intel_connector(connector); | |
36cd7444 DA |
1206 | if (!intel_connector->encoder) |
1207 | continue; | |
321a1b30 EE |
1208 | intel_encoder = intel_connector->encoder; |
1209 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { | |
1210 | if (intel_encoder->hot_plug) | |
1211 | intel_encoder->hot_plug(intel_encoder); | |
1212 | if (intel_hpd_irq_event(dev, connector)) | |
1213 | changed = true; | |
1214 | } | |
1215 | } | |
40ee3381 KP |
1216 | mutex_unlock(&mode_config->mutex); |
1217 | ||
321a1b30 EE |
1218 | if (changed) |
1219 | drm_kms_helper_hotplug_event(dev); | |
5ca58282 JB |
1220 | } |
1221 | ||
d0ecd7e2 | 1222 | static void ironlake_rps_change_irq_handler(struct drm_device *dev) |
f97108d1 | 1223 | { |
2d1013dd | 1224 | struct drm_i915_private *dev_priv = dev->dev_private; |
b5b72e89 | 1225 | u32 busy_up, busy_down, max_avg, min_avg; |
9270388e | 1226 | u8 new_delay; |
9270388e | 1227 | |
d0ecd7e2 | 1228 | spin_lock(&mchdev_lock); |
f97108d1 | 1229 | |
73edd18f DV |
1230 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
1231 | ||
20e4d407 | 1232 | new_delay = dev_priv->ips.cur_delay; |
9270388e | 1233 | |
7648fa99 | 1234 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
1235 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
1236 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
1237 | max_avg = I915_READ(RCBMAXAVG); |
1238 | min_avg = I915_READ(RCBMINAVG); | |
1239 | ||
1240 | /* Handle RCS change request from hw */ | |
b5b72e89 | 1241 | if (busy_up > max_avg) { |
20e4d407 DV |
1242 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
1243 | new_delay = dev_priv->ips.cur_delay - 1; | |
1244 | if (new_delay < dev_priv->ips.max_delay) | |
1245 | new_delay = dev_priv->ips.max_delay; | |
b5b72e89 | 1246 | } else if (busy_down < min_avg) { |
20e4d407 DV |
1247 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
1248 | new_delay = dev_priv->ips.cur_delay + 1; | |
1249 | if (new_delay > dev_priv->ips.min_delay) | |
1250 | new_delay = dev_priv->ips.min_delay; | |
f97108d1 JB |
1251 | } |
1252 | ||
7648fa99 | 1253 | if (ironlake_set_drps(dev, new_delay)) |
20e4d407 | 1254 | dev_priv->ips.cur_delay = new_delay; |
f97108d1 | 1255 | |
d0ecd7e2 | 1256 | spin_unlock(&mchdev_lock); |
9270388e | 1257 | |
f97108d1 JB |
1258 | return; |
1259 | } | |
1260 | ||
549f7365 | 1261 | static void notify_ring(struct drm_device *dev, |
a4872ba6 | 1262 | struct intel_engine_cs *ring) |
549f7365 | 1263 | { |
93b0a4e0 | 1264 | if (!intel_ring_initialized(ring)) |
475553de CW |
1265 | return; |
1266 | ||
814e9b57 | 1267 | trace_i915_gem_request_complete(ring); |
9862e600 | 1268 | |
84c33a64 SG |
1269 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
1270 | intel_notify_mmio_flip(ring); | |
1271 | ||
549f7365 | 1272 | wake_up_all(&ring->irq_queue); |
10cd45b6 | 1273 | i915_queue_hangcheck(dev); |
549f7365 CW |
1274 | } |
1275 | ||
31685c25 | 1276 | static u32 vlv_c0_residency(struct drm_i915_private *dev_priv, |
bf225f20 | 1277 | struct intel_rps_ei *rps_ei) |
31685c25 D |
1278 | { |
1279 | u32 cz_ts, cz_freq_khz; | |
1280 | u32 render_count, media_count; | |
1281 | u32 elapsed_render, elapsed_media, elapsed_time; | |
1282 | u32 residency = 0; | |
1283 | ||
1284 | cz_ts = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP); | |
1285 | cz_freq_khz = DIV_ROUND_CLOSEST(dev_priv->mem_freq * 1000, 4); | |
1286 | ||
1287 | render_count = I915_READ(VLV_RENDER_C0_COUNT_REG); | |
1288 | media_count = I915_READ(VLV_MEDIA_C0_COUNT_REG); | |
1289 | ||
bf225f20 CW |
1290 | if (rps_ei->cz_clock == 0) { |
1291 | rps_ei->cz_clock = cz_ts; | |
1292 | rps_ei->render_c0 = render_count; | |
1293 | rps_ei->media_c0 = media_count; | |
31685c25 D |
1294 | |
1295 | return dev_priv->rps.cur_freq; | |
1296 | } | |
1297 | ||
bf225f20 CW |
1298 | elapsed_time = cz_ts - rps_ei->cz_clock; |
1299 | rps_ei->cz_clock = cz_ts; | |
31685c25 | 1300 | |
bf225f20 CW |
1301 | elapsed_render = render_count - rps_ei->render_c0; |
1302 | rps_ei->render_c0 = render_count; | |
31685c25 | 1303 | |
bf225f20 CW |
1304 | elapsed_media = media_count - rps_ei->media_c0; |
1305 | rps_ei->media_c0 = media_count; | |
31685c25 D |
1306 | |
1307 | /* Convert all the counters into common unit of milli sec */ | |
1308 | elapsed_time /= VLV_CZ_CLOCK_TO_MILLI_SEC; | |
1309 | elapsed_render /= cz_freq_khz; | |
1310 | elapsed_media /= cz_freq_khz; | |
1311 | ||
1312 | /* | |
1313 | * Calculate overall C0 residency percentage | |
1314 | * only if elapsed time is non zero | |
1315 | */ | |
1316 | if (elapsed_time) { | |
1317 | residency = | |
1318 | ((max(elapsed_render, elapsed_media) * 100) | |
1319 | / elapsed_time); | |
1320 | } | |
1321 | ||
1322 | return residency; | |
1323 | } | |
1324 | ||
1325 | /** | |
1326 | * vlv_calc_delay_from_C0_counters - Increase/Decrease freq based on GPU | |
1327 | * busy-ness calculated from C0 counters of render & media power wells | |
1328 | * @dev_priv: DRM device private | |
1329 | * | |
1330 | */ | |
4fa79042 | 1331 | static int vlv_calc_delay_from_C0_counters(struct drm_i915_private *dev_priv) |
31685c25 D |
1332 | { |
1333 | u32 residency_C0_up = 0, residency_C0_down = 0; | |
4fa79042 | 1334 | int new_delay, adj; |
31685c25 D |
1335 | |
1336 | dev_priv->rps.ei_interrupt_count++; | |
1337 | ||
1338 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
1339 | ||
1340 | ||
bf225f20 CW |
1341 | if (dev_priv->rps.up_ei.cz_clock == 0) { |
1342 | vlv_c0_residency(dev_priv, &dev_priv->rps.up_ei); | |
1343 | vlv_c0_residency(dev_priv, &dev_priv->rps.down_ei); | |
31685c25 D |
1344 | return dev_priv->rps.cur_freq; |
1345 | } | |
1346 | ||
1347 | ||
1348 | /* | |
1349 | * To down throttle, C0 residency should be less than down threshold | |
1350 | * for continous EI intervals. So calculate down EI counters | |
1351 | * once in VLV_INT_COUNT_FOR_DOWN_EI | |
1352 | */ | |
1353 | if (dev_priv->rps.ei_interrupt_count == VLV_INT_COUNT_FOR_DOWN_EI) { | |
1354 | ||
1355 | dev_priv->rps.ei_interrupt_count = 0; | |
1356 | ||
1357 | residency_C0_down = vlv_c0_residency(dev_priv, | |
bf225f20 | 1358 | &dev_priv->rps.down_ei); |
31685c25 D |
1359 | } else { |
1360 | residency_C0_up = vlv_c0_residency(dev_priv, | |
bf225f20 | 1361 | &dev_priv->rps.up_ei); |
31685c25 D |
1362 | } |
1363 | ||
1364 | new_delay = dev_priv->rps.cur_freq; | |
1365 | ||
1366 | adj = dev_priv->rps.last_adj; | |
1367 | /* C0 residency is greater than UP threshold. Increase Frequency */ | |
1368 | if (residency_C0_up >= VLV_RP_UP_EI_THRESHOLD) { | |
1369 | if (adj > 0) | |
1370 | adj *= 2; | |
1371 | else | |
1372 | adj = 1; | |
1373 | ||
1374 | if (dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit) | |
1375 | new_delay = dev_priv->rps.cur_freq + adj; | |
1376 | ||
1377 | /* | |
1378 | * For better performance, jump directly | |
1379 | * to RPe if we're below it. | |
1380 | */ | |
1381 | if (new_delay < dev_priv->rps.efficient_freq) | |
1382 | new_delay = dev_priv->rps.efficient_freq; | |
1383 | ||
1384 | } else if (!dev_priv->rps.ei_interrupt_count && | |
1385 | (residency_C0_down < VLV_RP_DOWN_EI_THRESHOLD)) { | |
1386 | if (adj < 0) | |
1387 | adj *= 2; | |
1388 | else | |
1389 | adj = -1; | |
1390 | /* | |
1391 | * This means, C0 residency is less than down threshold over | |
1392 | * a period of VLV_INT_COUNT_FOR_DOWN_EI. So, reduce the freq | |
1393 | */ | |
1394 | if (dev_priv->rps.cur_freq > dev_priv->rps.min_freq_softlimit) | |
1395 | new_delay = dev_priv->rps.cur_freq + adj; | |
1396 | } | |
1397 | ||
1398 | return new_delay; | |
1399 | } | |
1400 | ||
4912d041 | 1401 | static void gen6_pm_rps_work(struct work_struct *work) |
3b8d8d91 | 1402 | { |
2d1013dd JN |
1403 | struct drm_i915_private *dev_priv = |
1404 | container_of(work, struct drm_i915_private, rps.work); | |
edbfdb45 | 1405 | u32 pm_iir; |
dd75fdc8 | 1406 | int new_delay, adj; |
4912d041 | 1407 | |
59cdb63d | 1408 | spin_lock_irq(&dev_priv->irq_lock); |
c6a828d3 DV |
1409 | pm_iir = dev_priv->rps.pm_iir; |
1410 | dev_priv->rps.pm_iir = 0; | |
6af257cd | 1411 | if (INTEL_INFO(dev_priv->dev)->gen >= 8) |
480c8033 | 1412 | gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
0961021a BW |
1413 | else { |
1414 | /* Make sure not to corrupt PMIMR state used by ringbuffer */ | |
480c8033 | 1415 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
0961021a | 1416 | } |
59cdb63d | 1417 | spin_unlock_irq(&dev_priv->irq_lock); |
3b8d8d91 | 1418 | |
60611c13 | 1419 | /* Make sure we didn't queue anything we're not going to process. */ |
a6706b45 | 1420 | WARN_ON(pm_iir & ~dev_priv->pm_rps_events); |
60611c13 | 1421 | |
a6706b45 | 1422 | if ((pm_iir & dev_priv->pm_rps_events) == 0) |
3b8d8d91 JB |
1423 | return; |
1424 | ||
4fc688ce | 1425 | mutex_lock(&dev_priv->rps.hw_lock); |
7b9e0ae6 | 1426 | |
dd75fdc8 | 1427 | adj = dev_priv->rps.last_adj; |
7425034a | 1428 | if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { |
dd75fdc8 CW |
1429 | if (adj > 0) |
1430 | adj *= 2; | |
13a5660c D |
1431 | else { |
1432 | /* CHV needs even encode values */ | |
1433 | adj = IS_CHERRYVIEW(dev_priv->dev) ? 2 : 1; | |
1434 | } | |
b39fb297 | 1435 | new_delay = dev_priv->rps.cur_freq + adj; |
7425034a VS |
1436 | |
1437 | /* | |
1438 | * For better performance, jump directly | |
1439 | * to RPe if we're below it. | |
1440 | */ | |
b39fb297 BW |
1441 | if (new_delay < dev_priv->rps.efficient_freq) |
1442 | new_delay = dev_priv->rps.efficient_freq; | |
dd75fdc8 | 1443 | } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { |
b39fb297 BW |
1444 | if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq) |
1445 | new_delay = dev_priv->rps.efficient_freq; | |
dd75fdc8 | 1446 | else |
b39fb297 | 1447 | new_delay = dev_priv->rps.min_freq_softlimit; |
dd75fdc8 | 1448 | adj = 0; |
31685c25 D |
1449 | } else if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) { |
1450 | new_delay = vlv_calc_delay_from_C0_counters(dev_priv); | |
dd75fdc8 CW |
1451 | } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { |
1452 | if (adj < 0) | |
1453 | adj *= 2; | |
13a5660c D |
1454 | else { |
1455 | /* CHV needs even encode values */ | |
1456 | adj = IS_CHERRYVIEW(dev_priv->dev) ? -2 : -1; | |
1457 | } | |
b39fb297 | 1458 | new_delay = dev_priv->rps.cur_freq + adj; |
dd75fdc8 | 1459 | } else { /* unknown event */ |
b39fb297 | 1460 | new_delay = dev_priv->rps.cur_freq; |
dd75fdc8 | 1461 | } |
3b8d8d91 | 1462 | |
79249636 BW |
1463 | /* sysfs frequency interfaces may have snuck in while servicing the |
1464 | * interrupt | |
1465 | */ | |
1272e7b8 | 1466 | new_delay = clamp_t(int, new_delay, |
b39fb297 BW |
1467 | dev_priv->rps.min_freq_softlimit, |
1468 | dev_priv->rps.max_freq_softlimit); | |
27544369 | 1469 | |
b39fb297 | 1470 | dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq; |
dd75fdc8 CW |
1471 | |
1472 | if (IS_VALLEYVIEW(dev_priv->dev)) | |
1473 | valleyview_set_rps(dev_priv->dev, new_delay); | |
1474 | else | |
1475 | gen6_set_rps(dev_priv->dev, new_delay); | |
3b8d8d91 | 1476 | |
4fc688ce | 1477 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 JB |
1478 | } |
1479 | ||
e3689190 BW |
1480 | |
1481 | /** | |
1482 | * ivybridge_parity_work - Workqueue called when a parity error interrupt | |
1483 | * occurred. | |
1484 | * @work: workqueue struct | |
1485 | * | |
1486 | * Doesn't actually do anything except notify userspace. As a consequence of | |
1487 | * this event, userspace should try to remap the bad rows since statistically | |
1488 | * it is likely the same row is more likely to go bad again. | |
1489 | */ | |
1490 | static void ivybridge_parity_work(struct work_struct *work) | |
1491 | { | |
2d1013dd JN |
1492 | struct drm_i915_private *dev_priv = |
1493 | container_of(work, struct drm_i915_private, l3_parity.error_work); | |
e3689190 | 1494 | u32 error_status, row, bank, subbank; |
35a85ac6 | 1495 | char *parity_event[6]; |
e3689190 | 1496 | uint32_t misccpctl; |
35a85ac6 | 1497 | uint8_t slice = 0; |
e3689190 BW |
1498 | |
1499 | /* We must turn off DOP level clock gating to access the L3 registers. | |
1500 | * In order to prevent a get/put style interface, acquire struct mutex | |
1501 | * any time we access those registers. | |
1502 | */ | |
1503 | mutex_lock(&dev_priv->dev->struct_mutex); | |
1504 | ||
35a85ac6 BW |
1505 | /* If we've screwed up tracking, just let the interrupt fire again */ |
1506 | if (WARN_ON(!dev_priv->l3_parity.which_slice)) | |
1507 | goto out; | |
1508 | ||
e3689190 BW |
1509 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
1510 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
1511 | POSTING_READ(GEN7_MISCCPCTL); | |
1512 | ||
35a85ac6 BW |
1513 | while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { |
1514 | u32 reg; | |
e3689190 | 1515 | |
35a85ac6 BW |
1516 | slice--; |
1517 | if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev))) | |
1518 | break; | |
e3689190 | 1519 | |
35a85ac6 | 1520 | dev_priv->l3_parity.which_slice &= ~(1<<slice); |
e3689190 | 1521 | |
35a85ac6 | 1522 | reg = GEN7_L3CDERRST1 + (slice * 0x200); |
e3689190 | 1523 | |
35a85ac6 BW |
1524 | error_status = I915_READ(reg); |
1525 | row = GEN7_PARITY_ERROR_ROW(error_status); | |
1526 | bank = GEN7_PARITY_ERROR_BANK(error_status); | |
1527 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); | |
1528 | ||
1529 | I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); | |
1530 | POSTING_READ(reg); | |
1531 | ||
1532 | parity_event[0] = I915_L3_PARITY_UEVENT "=1"; | |
1533 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); | |
1534 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); | |
1535 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); | |
1536 | parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); | |
1537 | parity_event[5] = NULL; | |
1538 | ||
5bdebb18 | 1539 | kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj, |
35a85ac6 | 1540 | KOBJ_CHANGE, parity_event); |
e3689190 | 1541 | |
35a85ac6 BW |
1542 | DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", |
1543 | slice, row, bank, subbank); | |
e3689190 | 1544 | |
35a85ac6 BW |
1545 | kfree(parity_event[4]); |
1546 | kfree(parity_event[3]); | |
1547 | kfree(parity_event[2]); | |
1548 | kfree(parity_event[1]); | |
1549 | } | |
e3689190 | 1550 | |
35a85ac6 | 1551 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
e3689190 | 1552 | |
35a85ac6 BW |
1553 | out: |
1554 | WARN_ON(dev_priv->l3_parity.which_slice); | |
4cb21832 | 1555 | spin_lock_irq(&dev_priv->irq_lock); |
480c8033 | 1556 | gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev)); |
4cb21832 | 1557 | spin_unlock_irq(&dev_priv->irq_lock); |
35a85ac6 BW |
1558 | |
1559 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
e3689190 BW |
1560 | } |
1561 | ||
35a85ac6 | 1562 | static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir) |
e3689190 | 1563 | { |
2d1013dd | 1564 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3689190 | 1565 | |
040d2baa | 1566 | if (!HAS_L3_DPF(dev)) |
e3689190 BW |
1567 | return; |
1568 | ||
d0ecd7e2 | 1569 | spin_lock(&dev_priv->irq_lock); |
480c8033 | 1570 | gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev)); |
d0ecd7e2 | 1571 | spin_unlock(&dev_priv->irq_lock); |
e3689190 | 1572 | |
35a85ac6 BW |
1573 | iir &= GT_PARITY_ERROR(dev); |
1574 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) | |
1575 | dev_priv->l3_parity.which_slice |= 1 << 1; | |
1576 | ||
1577 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) | |
1578 | dev_priv->l3_parity.which_slice |= 1 << 0; | |
1579 | ||
a4da4fa4 | 1580 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
e3689190 BW |
1581 | } |
1582 | ||
f1af8fc1 PZ |
1583 | static void ilk_gt_irq_handler(struct drm_device *dev, |
1584 | struct drm_i915_private *dev_priv, | |
1585 | u32 gt_iir) | |
1586 | { | |
1587 | if (gt_iir & | |
1588 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
1589 | notify_ring(dev, &dev_priv->ring[RCS]); | |
1590 | if (gt_iir & ILK_BSD_USER_INTERRUPT) | |
1591 | notify_ring(dev, &dev_priv->ring[VCS]); | |
1592 | } | |
1593 | ||
e7b4c6b1 DV |
1594 | static void snb_gt_irq_handler(struct drm_device *dev, |
1595 | struct drm_i915_private *dev_priv, | |
1596 | u32 gt_iir) | |
1597 | { | |
1598 | ||
cc609d5d BW |
1599 | if (gt_iir & |
1600 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
e7b4c6b1 | 1601 | notify_ring(dev, &dev_priv->ring[RCS]); |
cc609d5d | 1602 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
e7b4c6b1 | 1603 | notify_ring(dev, &dev_priv->ring[VCS]); |
cc609d5d | 1604 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
e7b4c6b1 DV |
1605 | notify_ring(dev, &dev_priv->ring[BCS]); |
1606 | ||
cc609d5d BW |
1607 | if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | |
1608 | GT_BSD_CS_ERROR_INTERRUPT | | |
1609 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) { | |
58174462 MK |
1610 | i915_handle_error(dev, false, "GT error interrupt 0x%08x", |
1611 | gt_iir); | |
e7b4c6b1 | 1612 | } |
e3689190 | 1613 | |
35a85ac6 BW |
1614 | if (gt_iir & GT_PARITY_ERROR(dev)) |
1615 | ivybridge_parity_error_irq_handler(dev, gt_iir); | |
e7b4c6b1 DV |
1616 | } |
1617 | ||
0961021a BW |
1618 | static void gen8_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) |
1619 | { | |
1620 | if ((pm_iir & dev_priv->pm_rps_events) == 0) | |
1621 | return; | |
1622 | ||
1623 | spin_lock(&dev_priv->irq_lock); | |
1624 | dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; | |
480c8033 | 1625 | gen8_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); |
0961021a BW |
1626 | spin_unlock(&dev_priv->irq_lock); |
1627 | ||
1628 | queue_work(dev_priv->wq, &dev_priv->rps.work); | |
1629 | } | |
1630 | ||
abd58f01 BW |
1631 | static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev, |
1632 | struct drm_i915_private *dev_priv, | |
1633 | u32 master_ctl) | |
1634 | { | |
e981e7b1 | 1635 | struct intel_engine_cs *ring; |
abd58f01 BW |
1636 | u32 rcs, bcs, vcs; |
1637 | uint32_t tmp = 0; | |
1638 | irqreturn_t ret = IRQ_NONE; | |
1639 | ||
1640 | if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { | |
1641 | tmp = I915_READ(GEN8_GT_IIR(0)); | |
1642 | if (tmp) { | |
38cc46d7 | 1643 | I915_WRITE(GEN8_GT_IIR(0), tmp); |
abd58f01 | 1644 | ret = IRQ_HANDLED; |
e981e7b1 | 1645 | |
abd58f01 | 1646 | rcs = tmp >> GEN8_RCS_IRQ_SHIFT; |
e981e7b1 | 1647 | ring = &dev_priv->ring[RCS]; |
abd58f01 | 1648 | if (rcs & GT_RENDER_USER_INTERRUPT) |
e981e7b1 TD |
1649 | notify_ring(dev, ring); |
1650 | if (rcs & GT_CONTEXT_SWITCH_INTERRUPT) | |
1651 | intel_execlists_handle_ctx_events(ring); | |
1652 | ||
1653 | bcs = tmp >> GEN8_BCS_IRQ_SHIFT; | |
1654 | ring = &dev_priv->ring[BCS]; | |
abd58f01 | 1655 | if (bcs & GT_RENDER_USER_INTERRUPT) |
e981e7b1 TD |
1656 | notify_ring(dev, ring); |
1657 | if (bcs & GT_CONTEXT_SWITCH_INTERRUPT) | |
1658 | intel_execlists_handle_ctx_events(ring); | |
abd58f01 BW |
1659 | } else |
1660 | DRM_ERROR("The master control interrupt lied (GT0)!\n"); | |
1661 | } | |
1662 | ||
85f9b5f9 | 1663 | if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) { |
abd58f01 BW |
1664 | tmp = I915_READ(GEN8_GT_IIR(1)); |
1665 | if (tmp) { | |
38cc46d7 | 1666 | I915_WRITE(GEN8_GT_IIR(1), tmp); |
abd58f01 | 1667 | ret = IRQ_HANDLED; |
e981e7b1 | 1668 | |
abd58f01 | 1669 | vcs = tmp >> GEN8_VCS1_IRQ_SHIFT; |
e981e7b1 | 1670 | ring = &dev_priv->ring[VCS]; |
abd58f01 | 1671 | if (vcs & GT_RENDER_USER_INTERRUPT) |
e981e7b1 | 1672 | notify_ring(dev, ring); |
73d477f6 | 1673 | if (vcs & GT_CONTEXT_SWITCH_INTERRUPT) |
e981e7b1 TD |
1674 | intel_execlists_handle_ctx_events(ring); |
1675 | ||
85f9b5f9 | 1676 | vcs = tmp >> GEN8_VCS2_IRQ_SHIFT; |
e981e7b1 | 1677 | ring = &dev_priv->ring[VCS2]; |
85f9b5f9 | 1678 | if (vcs & GT_RENDER_USER_INTERRUPT) |
e981e7b1 | 1679 | notify_ring(dev, ring); |
73d477f6 | 1680 | if (vcs & GT_CONTEXT_SWITCH_INTERRUPT) |
e981e7b1 | 1681 | intel_execlists_handle_ctx_events(ring); |
abd58f01 BW |
1682 | } else |
1683 | DRM_ERROR("The master control interrupt lied (GT1)!\n"); | |
1684 | } | |
1685 | ||
0961021a BW |
1686 | if (master_ctl & GEN8_GT_PM_IRQ) { |
1687 | tmp = I915_READ(GEN8_GT_IIR(2)); | |
1688 | if (tmp & dev_priv->pm_rps_events) { | |
0961021a BW |
1689 | I915_WRITE(GEN8_GT_IIR(2), |
1690 | tmp & dev_priv->pm_rps_events); | |
38cc46d7 OM |
1691 | ret = IRQ_HANDLED; |
1692 | gen8_rps_irq_handler(dev_priv, tmp); | |
0961021a BW |
1693 | } else |
1694 | DRM_ERROR("The master control interrupt lied (PM)!\n"); | |
1695 | } | |
1696 | ||
abd58f01 BW |
1697 | if (master_ctl & GEN8_GT_VECS_IRQ) { |
1698 | tmp = I915_READ(GEN8_GT_IIR(3)); | |
1699 | if (tmp) { | |
38cc46d7 | 1700 | I915_WRITE(GEN8_GT_IIR(3), tmp); |
abd58f01 | 1701 | ret = IRQ_HANDLED; |
e981e7b1 | 1702 | |
abd58f01 | 1703 | vcs = tmp >> GEN8_VECS_IRQ_SHIFT; |
e981e7b1 | 1704 | ring = &dev_priv->ring[VECS]; |
abd58f01 | 1705 | if (vcs & GT_RENDER_USER_INTERRUPT) |
e981e7b1 | 1706 | notify_ring(dev, ring); |
73d477f6 | 1707 | if (vcs & GT_CONTEXT_SWITCH_INTERRUPT) |
e981e7b1 | 1708 | intel_execlists_handle_ctx_events(ring); |
abd58f01 BW |
1709 | } else |
1710 | DRM_ERROR("The master control interrupt lied (GT3)!\n"); | |
1711 | } | |
1712 | ||
1713 | return ret; | |
1714 | } | |
1715 | ||
b543fb04 EE |
1716 | #define HPD_STORM_DETECT_PERIOD 1000 |
1717 | #define HPD_STORM_THRESHOLD 5 | |
1718 | ||
07c338ce | 1719 | static int pch_port_to_hotplug_shift(enum port port) |
13cf5504 DA |
1720 | { |
1721 | switch (port) { | |
1722 | case PORT_A: | |
1723 | case PORT_E: | |
1724 | default: | |
1725 | return -1; | |
1726 | case PORT_B: | |
1727 | return 0; | |
1728 | case PORT_C: | |
1729 | return 8; | |
1730 | case PORT_D: | |
1731 | return 16; | |
1732 | } | |
1733 | } | |
1734 | ||
07c338ce | 1735 | static int i915_port_to_hotplug_shift(enum port port) |
13cf5504 DA |
1736 | { |
1737 | switch (port) { | |
1738 | case PORT_A: | |
1739 | case PORT_E: | |
1740 | default: | |
1741 | return -1; | |
1742 | case PORT_B: | |
1743 | return 17; | |
1744 | case PORT_C: | |
1745 | return 19; | |
1746 | case PORT_D: | |
1747 | return 21; | |
1748 | } | |
1749 | } | |
1750 | ||
1751 | static inline enum port get_port_from_pin(enum hpd_pin pin) | |
1752 | { | |
1753 | switch (pin) { | |
1754 | case HPD_PORT_B: | |
1755 | return PORT_B; | |
1756 | case HPD_PORT_C: | |
1757 | return PORT_C; | |
1758 | case HPD_PORT_D: | |
1759 | return PORT_D; | |
1760 | default: | |
1761 | return PORT_A; /* no hpd */ | |
1762 | } | |
1763 | } | |
1764 | ||
10a504de | 1765 | static inline void intel_hpd_irq_handler(struct drm_device *dev, |
22062dba | 1766 | u32 hotplug_trigger, |
13cf5504 | 1767 | u32 dig_hotplug_reg, |
22062dba | 1768 | const u32 *hpd) |
b543fb04 | 1769 | { |
2d1013dd | 1770 | struct drm_i915_private *dev_priv = dev->dev_private; |
b543fb04 | 1771 | int i; |
13cf5504 | 1772 | enum port port; |
10a504de | 1773 | bool storm_detected = false; |
13cf5504 DA |
1774 | bool queue_dig = false, queue_hp = false; |
1775 | u32 dig_shift; | |
1776 | u32 dig_port_mask = 0; | |
b543fb04 | 1777 | |
91d131d2 DV |
1778 | if (!hotplug_trigger) |
1779 | return; | |
1780 | ||
13cf5504 DA |
1781 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x\n", |
1782 | hotplug_trigger, dig_hotplug_reg); | |
cc9bd499 | 1783 | |
b5ea2d56 | 1784 | spin_lock(&dev_priv->irq_lock); |
b543fb04 | 1785 | for (i = 1; i < HPD_NUM_PINS; i++) { |
13cf5504 DA |
1786 | if (!(hpd[i] & hotplug_trigger)) |
1787 | continue; | |
1788 | ||
1789 | port = get_port_from_pin(i); | |
1790 | if (port && dev_priv->hpd_irq_port[port]) { | |
1791 | bool long_hpd; | |
1792 | ||
07c338ce JN |
1793 | if (HAS_PCH_SPLIT(dev)) { |
1794 | dig_shift = pch_port_to_hotplug_shift(port); | |
13cf5504 | 1795 | long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT; |
07c338ce JN |
1796 | } else { |
1797 | dig_shift = i915_port_to_hotplug_shift(port); | |
1798 | long_hpd = (hotplug_trigger >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT; | |
13cf5504 DA |
1799 | } |
1800 | ||
26fbb774 VS |
1801 | DRM_DEBUG_DRIVER("digital hpd port %c - %s\n", |
1802 | port_name(port), | |
1803 | long_hpd ? "long" : "short"); | |
13cf5504 DA |
1804 | /* for long HPD pulses we want to have the digital queue happen, |
1805 | but we still want HPD storm detection to function. */ | |
1806 | if (long_hpd) { | |
1807 | dev_priv->long_hpd_port_mask |= (1 << port); | |
1808 | dig_port_mask |= hpd[i]; | |
1809 | } else { | |
1810 | /* for short HPD just trigger the digital queue */ | |
1811 | dev_priv->short_hpd_port_mask |= (1 << port); | |
1812 | hotplug_trigger &= ~hpd[i]; | |
1813 | } | |
1814 | queue_dig = true; | |
1815 | } | |
1816 | } | |
821450c6 | 1817 | |
13cf5504 | 1818 | for (i = 1; i < HPD_NUM_PINS; i++) { |
3ff04a16 DV |
1819 | if (hpd[i] & hotplug_trigger && |
1820 | dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) { | |
1821 | /* | |
1822 | * On GMCH platforms the interrupt mask bits only | |
1823 | * prevent irq generation, not the setting of the | |
1824 | * hotplug bits itself. So only WARN about unexpected | |
1825 | * interrupts on saner platforms. | |
1826 | */ | |
1827 | WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev), | |
1828 | "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n", | |
1829 | hotplug_trigger, i, hpd[i]); | |
1830 | ||
1831 | continue; | |
1832 | } | |
b8f102e8 | 1833 | |
b543fb04 EE |
1834 | if (!(hpd[i] & hotplug_trigger) || |
1835 | dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED) | |
1836 | continue; | |
1837 | ||
13cf5504 DA |
1838 | if (!(dig_port_mask & hpd[i])) { |
1839 | dev_priv->hpd_event_bits |= (1 << i); | |
1840 | queue_hp = true; | |
1841 | } | |
1842 | ||
b543fb04 EE |
1843 | if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies, |
1844 | dev_priv->hpd_stats[i].hpd_last_jiffies | |
1845 | + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) { | |
1846 | dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies; | |
1847 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
b8f102e8 | 1848 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i); |
b543fb04 EE |
1849 | } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) { |
1850 | dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED; | |
142e2398 | 1851 | dev_priv->hpd_event_bits &= ~(1 << i); |
b543fb04 | 1852 | DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i); |
10a504de | 1853 | storm_detected = true; |
b543fb04 EE |
1854 | } else { |
1855 | dev_priv->hpd_stats[i].hpd_cnt++; | |
b8f102e8 EE |
1856 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i, |
1857 | dev_priv->hpd_stats[i].hpd_cnt); | |
b543fb04 EE |
1858 | } |
1859 | } | |
1860 | ||
10a504de DV |
1861 | if (storm_detected) |
1862 | dev_priv->display.hpd_irq_setup(dev); | |
b5ea2d56 | 1863 | spin_unlock(&dev_priv->irq_lock); |
5876fa0d | 1864 | |
645416f5 DV |
1865 | /* |
1866 | * Our hotplug handler can grab modeset locks (by calling down into the | |
1867 | * fb helpers). Hence it must not be run on our own dev-priv->wq work | |
1868 | * queue for otherwise the flush_work in the pageflip code will | |
1869 | * deadlock. | |
1870 | */ | |
13cf5504 | 1871 | if (queue_dig) |
0e32b39c | 1872 | queue_work(dev_priv->dp_wq, &dev_priv->dig_port_work); |
13cf5504 DA |
1873 | if (queue_hp) |
1874 | schedule_work(&dev_priv->hotplug_work); | |
b543fb04 EE |
1875 | } |
1876 | ||
515ac2bb DV |
1877 | static void gmbus_irq_handler(struct drm_device *dev) |
1878 | { | |
2d1013dd | 1879 | struct drm_i915_private *dev_priv = dev->dev_private; |
28c70f16 | 1880 | |
28c70f16 | 1881 | wake_up_all(&dev_priv->gmbus_wait_queue); |
515ac2bb DV |
1882 | } |
1883 | ||
ce99c256 DV |
1884 | static void dp_aux_irq_handler(struct drm_device *dev) |
1885 | { | |
2d1013dd | 1886 | struct drm_i915_private *dev_priv = dev->dev_private; |
9ee32fea | 1887 | |
9ee32fea | 1888 | wake_up_all(&dev_priv->gmbus_wait_queue); |
ce99c256 DV |
1889 | } |
1890 | ||
8bf1e9f1 | 1891 | #if defined(CONFIG_DEBUG_FS) |
277de95e DV |
1892 | static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, |
1893 | uint32_t crc0, uint32_t crc1, | |
1894 | uint32_t crc2, uint32_t crc3, | |
1895 | uint32_t crc4) | |
8bf1e9f1 SH |
1896 | { |
1897 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1898 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; | |
1899 | struct intel_pipe_crc_entry *entry; | |
ac2300d4 | 1900 | int head, tail; |
b2c88f5b | 1901 | |
d538bbdf DL |
1902 | spin_lock(&pipe_crc->lock); |
1903 | ||
0c912c79 | 1904 | if (!pipe_crc->entries) { |
d538bbdf | 1905 | spin_unlock(&pipe_crc->lock); |
0c912c79 DL |
1906 | DRM_ERROR("spurious interrupt\n"); |
1907 | return; | |
1908 | } | |
1909 | ||
d538bbdf DL |
1910 | head = pipe_crc->head; |
1911 | tail = pipe_crc->tail; | |
b2c88f5b DL |
1912 | |
1913 | if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { | |
d538bbdf | 1914 | spin_unlock(&pipe_crc->lock); |
b2c88f5b DL |
1915 | DRM_ERROR("CRC buffer overflowing\n"); |
1916 | return; | |
1917 | } | |
1918 | ||
1919 | entry = &pipe_crc->entries[head]; | |
8bf1e9f1 | 1920 | |
8bc5e955 | 1921 | entry->frame = dev->driver->get_vblank_counter(dev, pipe); |
eba94eb9 DV |
1922 | entry->crc[0] = crc0; |
1923 | entry->crc[1] = crc1; | |
1924 | entry->crc[2] = crc2; | |
1925 | entry->crc[3] = crc3; | |
1926 | entry->crc[4] = crc4; | |
b2c88f5b DL |
1927 | |
1928 | head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
d538bbdf DL |
1929 | pipe_crc->head = head; |
1930 | ||
1931 | spin_unlock(&pipe_crc->lock); | |
07144428 DL |
1932 | |
1933 | wake_up_interruptible(&pipe_crc->wq); | |
8bf1e9f1 | 1934 | } |
277de95e DV |
1935 | #else |
1936 | static inline void | |
1937 | display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, | |
1938 | uint32_t crc0, uint32_t crc1, | |
1939 | uint32_t crc2, uint32_t crc3, | |
1940 | uint32_t crc4) {} | |
1941 | #endif | |
1942 | ||
eba94eb9 | 1943 | |
277de95e | 1944 | static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5a69b89f DV |
1945 | { |
1946 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1947 | ||
277de95e DV |
1948 | display_pipe_crc_irq_handler(dev, pipe, |
1949 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1950 | 0, 0, 0, 0); | |
5a69b89f DV |
1951 | } |
1952 | ||
277de95e | 1953 | static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
eba94eb9 DV |
1954 | { |
1955 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1956 | ||
277de95e DV |
1957 | display_pipe_crc_irq_handler(dev, pipe, |
1958 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1959 | I915_READ(PIPE_CRC_RES_2_IVB(pipe)), | |
1960 | I915_READ(PIPE_CRC_RES_3_IVB(pipe)), | |
1961 | I915_READ(PIPE_CRC_RES_4_IVB(pipe)), | |
1962 | I915_READ(PIPE_CRC_RES_5_IVB(pipe))); | |
eba94eb9 | 1963 | } |
5b3a856b | 1964 | |
277de95e | 1965 | static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5b3a856b DV |
1966 | { |
1967 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0b5c5ed0 DV |
1968 | uint32_t res1, res2; |
1969 | ||
1970 | if (INTEL_INFO(dev)->gen >= 3) | |
1971 | res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); | |
1972 | else | |
1973 | res1 = 0; | |
1974 | ||
1975 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
1976 | res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); | |
1977 | else | |
1978 | res2 = 0; | |
5b3a856b | 1979 | |
277de95e DV |
1980 | display_pipe_crc_irq_handler(dev, pipe, |
1981 | I915_READ(PIPE_CRC_RES_RED(pipe)), | |
1982 | I915_READ(PIPE_CRC_RES_GREEN(pipe)), | |
1983 | I915_READ(PIPE_CRC_RES_BLUE(pipe)), | |
1984 | res1, res2); | |
5b3a856b | 1985 | } |
8bf1e9f1 | 1986 | |
1403c0d4 PZ |
1987 | /* The RPS events need forcewake, so we add them to a work queue and mask their |
1988 | * IMR bits until the work is done. Other interrupts can be processed without | |
1989 | * the work queue. */ | |
1990 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) | |
baf02a1f | 1991 | { |
a6706b45 | 1992 | if (pm_iir & dev_priv->pm_rps_events) { |
59cdb63d | 1993 | spin_lock(&dev_priv->irq_lock); |
a6706b45 | 1994 | dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; |
480c8033 | 1995 | gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); |
59cdb63d | 1996 | spin_unlock(&dev_priv->irq_lock); |
2adbee62 DV |
1997 | |
1998 | queue_work(dev_priv->wq, &dev_priv->rps.work); | |
baf02a1f | 1999 | } |
baf02a1f | 2000 | |
1403c0d4 PZ |
2001 | if (HAS_VEBOX(dev_priv->dev)) { |
2002 | if (pm_iir & PM_VEBOX_USER_INTERRUPT) | |
2003 | notify_ring(dev_priv->dev, &dev_priv->ring[VECS]); | |
12638c57 | 2004 | |
1403c0d4 | 2005 | if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) { |
58174462 MK |
2006 | i915_handle_error(dev_priv->dev, false, |
2007 | "VEBOX CS error interrupt 0x%08x", | |
2008 | pm_iir); | |
1403c0d4 | 2009 | } |
12638c57 | 2010 | } |
baf02a1f BW |
2011 | } |
2012 | ||
8d7849db VS |
2013 | static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe) |
2014 | { | |
8d7849db VS |
2015 | if (!drm_handle_vblank(dev, pipe)) |
2016 | return false; | |
2017 | ||
8d7849db VS |
2018 | return true; |
2019 | } | |
2020 | ||
c1874ed7 ID |
2021 | static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir) |
2022 | { | |
2023 | struct drm_i915_private *dev_priv = dev->dev_private; | |
91d181dd | 2024 | u32 pipe_stats[I915_MAX_PIPES] = { }; |
c1874ed7 ID |
2025 | int pipe; |
2026 | ||
58ead0d7 | 2027 | spin_lock(&dev_priv->irq_lock); |
055e393f | 2028 | for_each_pipe(dev_priv, pipe) { |
91d181dd | 2029 | int reg; |
bbb5eebf | 2030 | u32 mask, iir_bit = 0; |
91d181dd | 2031 | |
bbb5eebf DV |
2032 | /* |
2033 | * PIPESTAT bits get signalled even when the interrupt is | |
2034 | * disabled with the mask bits, and some of the status bits do | |
2035 | * not generate interrupts at all (like the underrun bit). Hence | |
2036 | * we need to be careful that we only handle what we want to | |
2037 | * handle. | |
2038 | */ | |
2039 | mask = 0; | |
2040 | if (__cpu_fifo_underrun_reporting_enabled(dev, pipe)) | |
2041 | mask |= PIPE_FIFO_UNDERRUN_STATUS; | |
2042 | ||
2043 | switch (pipe) { | |
2044 | case PIPE_A: | |
2045 | iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; | |
2046 | break; | |
2047 | case PIPE_B: | |
2048 | iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
2049 | break; | |
3278f67f VS |
2050 | case PIPE_C: |
2051 | iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
2052 | break; | |
bbb5eebf DV |
2053 | } |
2054 | if (iir & iir_bit) | |
2055 | mask |= dev_priv->pipestat_irq_mask[pipe]; | |
2056 | ||
2057 | if (!mask) | |
91d181dd ID |
2058 | continue; |
2059 | ||
2060 | reg = PIPESTAT(pipe); | |
bbb5eebf DV |
2061 | mask |= PIPESTAT_INT_ENABLE_MASK; |
2062 | pipe_stats[pipe] = I915_READ(reg) & mask; | |
c1874ed7 ID |
2063 | |
2064 | /* | |
2065 | * Clear the PIPE*STAT regs before the IIR | |
2066 | */ | |
91d181dd ID |
2067 | if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS | |
2068 | PIPESTAT_INT_STATUS_MASK)) | |
c1874ed7 ID |
2069 | I915_WRITE(reg, pipe_stats[pipe]); |
2070 | } | |
58ead0d7 | 2071 | spin_unlock(&dev_priv->irq_lock); |
c1874ed7 | 2072 | |
055e393f | 2073 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
2074 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
2075 | intel_pipe_handle_vblank(dev, pipe)) | |
2076 | intel_check_page_flip(dev, pipe); | |
c1874ed7 | 2077 | |
579a9b0e | 2078 | if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) { |
c1874ed7 ID |
2079 | intel_prepare_page_flip(dev, pipe); |
2080 | intel_finish_page_flip(dev, pipe); | |
2081 | } | |
2082 | ||
2083 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
2084 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
2085 | ||
2086 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && | |
2087 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
2088 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); | |
2089 | } | |
2090 | ||
2091 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) | |
2092 | gmbus_irq_handler(dev); | |
2093 | } | |
2094 | ||
16c6c56b VS |
2095 | static void i9xx_hpd_irq_handler(struct drm_device *dev) |
2096 | { | |
2097 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2098 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
2099 | ||
3ff60f89 OM |
2100 | if (hotplug_status) { |
2101 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
2102 | /* | |
2103 | * Make sure hotplug status is cleared before we clear IIR, or else we | |
2104 | * may miss hotplug events. | |
2105 | */ | |
2106 | POSTING_READ(PORT_HOTPLUG_STAT); | |
16c6c56b | 2107 | |
3ff60f89 OM |
2108 | if (IS_G4X(dev)) { |
2109 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; | |
16c6c56b | 2110 | |
13cf5504 | 2111 | intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_g4x); |
3ff60f89 OM |
2112 | } else { |
2113 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; | |
16c6c56b | 2114 | |
13cf5504 | 2115 | intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_i915); |
3ff60f89 | 2116 | } |
16c6c56b | 2117 | |
3ff60f89 OM |
2118 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && |
2119 | hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) | |
2120 | dp_aux_irq_handler(dev); | |
2121 | } | |
16c6c56b VS |
2122 | } |
2123 | ||
ff1f525e | 2124 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
7e231dbe | 2125 | { |
45a83f84 | 2126 | struct drm_device *dev = arg; |
2d1013dd | 2127 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
2128 | u32 iir, gt_iir, pm_iir; |
2129 | irqreturn_t ret = IRQ_NONE; | |
7e231dbe | 2130 | |
7e231dbe | 2131 | while (true) { |
3ff60f89 OM |
2132 | /* Find, clear, then process each source of interrupt */ |
2133 | ||
7e231dbe | 2134 | gt_iir = I915_READ(GTIIR); |
3ff60f89 OM |
2135 | if (gt_iir) |
2136 | I915_WRITE(GTIIR, gt_iir); | |
2137 | ||
7e231dbe | 2138 | pm_iir = I915_READ(GEN6_PMIIR); |
3ff60f89 OM |
2139 | if (pm_iir) |
2140 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
2141 | ||
2142 | iir = I915_READ(VLV_IIR); | |
2143 | if (iir) { | |
2144 | /* Consume port before clearing IIR or we'll miss events */ | |
2145 | if (iir & I915_DISPLAY_PORT_INTERRUPT) | |
2146 | i9xx_hpd_irq_handler(dev); | |
2147 | I915_WRITE(VLV_IIR, iir); | |
2148 | } | |
7e231dbe JB |
2149 | |
2150 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) | |
2151 | goto out; | |
2152 | ||
2153 | ret = IRQ_HANDLED; | |
2154 | ||
3ff60f89 OM |
2155 | if (gt_iir) |
2156 | snb_gt_irq_handler(dev, dev_priv, gt_iir); | |
60611c13 | 2157 | if (pm_iir) |
d0ecd7e2 | 2158 | gen6_rps_irq_handler(dev_priv, pm_iir); |
3ff60f89 OM |
2159 | /* Call regardless, as some status bits might not be |
2160 | * signalled in iir */ | |
2161 | valleyview_pipestat_irq_handler(dev, iir); | |
7e231dbe JB |
2162 | } |
2163 | ||
2164 | out: | |
2165 | return ret; | |
2166 | } | |
2167 | ||
43f328d7 VS |
2168 | static irqreturn_t cherryview_irq_handler(int irq, void *arg) |
2169 | { | |
45a83f84 | 2170 | struct drm_device *dev = arg; |
43f328d7 VS |
2171 | struct drm_i915_private *dev_priv = dev->dev_private; |
2172 | u32 master_ctl, iir; | |
2173 | irqreturn_t ret = IRQ_NONE; | |
43f328d7 | 2174 | |
8e5fd599 VS |
2175 | for (;;) { |
2176 | master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; | |
2177 | iir = I915_READ(VLV_IIR); | |
43f328d7 | 2178 | |
8e5fd599 VS |
2179 | if (master_ctl == 0 && iir == 0) |
2180 | break; | |
43f328d7 | 2181 | |
27b6c122 OM |
2182 | ret = IRQ_HANDLED; |
2183 | ||
8e5fd599 | 2184 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
43f328d7 | 2185 | |
27b6c122 | 2186 | /* Find, clear, then process each source of interrupt */ |
43f328d7 | 2187 | |
27b6c122 OM |
2188 | if (iir) { |
2189 | /* Consume port before clearing IIR or we'll miss events */ | |
2190 | if (iir & I915_DISPLAY_PORT_INTERRUPT) | |
2191 | i9xx_hpd_irq_handler(dev); | |
2192 | I915_WRITE(VLV_IIR, iir); | |
2193 | } | |
43f328d7 | 2194 | |
27b6c122 | 2195 | gen8_gt_irq_handler(dev, dev_priv, master_ctl); |
43f328d7 | 2196 | |
27b6c122 OM |
2197 | /* Call regardless, as some status bits might not be |
2198 | * signalled in iir */ | |
2199 | valleyview_pipestat_irq_handler(dev, iir); | |
43f328d7 | 2200 | |
8e5fd599 VS |
2201 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); |
2202 | POSTING_READ(GEN8_MASTER_IRQ); | |
8e5fd599 | 2203 | } |
3278f67f | 2204 | |
43f328d7 VS |
2205 | return ret; |
2206 | } | |
2207 | ||
23e81d69 | 2208 | static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) |
776ad806 | 2209 | { |
2d1013dd | 2210 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 2211 | int pipe; |
b543fb04 | 2212 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; |
13cf5504 DA |
2213 | u32 dig_hotplug_reg; |
2214 | ||
2215 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); | |
2216 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
776ad806 | 2217 | |
13cf5504 | 2218 | intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_ibx); |
91d131d2 | 2219 | |
cfc33bf7 VS |
2220 | if (pch_iir & SDE_AUDIO_POWER_MASK) { |
2221 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> | |
2222 | SDE_AUDIO_POWER_SHIFT); | |
776ad806 | 2223 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
cfc33bf7 VS |
2224 | port_name(port)); |
2225 | } | |
776ad806 | 2226 | |
ce99c256 DV |
2227 | if (pch_iir & SDE_AUX_MASK) |
2228 | dp_aux_irq_handler(dev); | |
2229 | ||
776ad806 | 2230 | if (pch_iir & SDE_GMBUS) |
515ac2bb | 2231 | gmbus_irq_handler(dev); |
776ad806 JB |
2232 | |
2233 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
2234 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
2235 | ||
2236 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
2237 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
2238 | ||
2239 | if (pch_iir & SDE_POISON) | |
2240 | DRM_ERROR("PCH poison interrupt\n"); | |
2241 | ||
9db4a9c7 | 2242 | if (pch_iir & SDE_FDI_MASK) |
055e393f | 2243 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
2244 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
2245 | pipe_name(pipe), | |
2246 | I915_READ(FDI_RX_IIR(pipe))); | |
776ad806 JB |
2247 | |
2248 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
2249 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
2250 | ||
2251 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
2252 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
2253 | ||
776ad806 | 2254 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
8664281b PZ |
2255 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, |
2256 | false)) | |
fc2c807b | 2257 | DRM_ERROR("PCH transcoder A FIFO underrun\n"); |
8664281b PZ |
2258 | |
2259 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
2260 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, | |
2261 | false)) | |
fc2c807b | 2262 | DRM_ERROR("PCH transcoder B FIFO underrun\n"); |
8664281b PZ |
2263 | } |
2264 | ||
2265 | static void ivb_err_int_handler(struct drm_device *dev) | |
2266 | { | |
2267 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2268 | u32 err_int = I915_READ(GEN7_ERR_INT); | |
5a69b89f | 2269 | enum pipe pipe; |
8664281b | 2270 | |
de032bf4 PZ |
2271 | if (err_int & ERR_INT_POISON) |
2272 | DRM_ERROR("Poison interrupt\n"); | |
2273 | ||
055e393f | 2274 | for_each_pipe(dev_priv, pipe) { |
5a69b89f DV |
2275 | if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) { |
2276 | if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, | |
2277 | false)) | |
fc2c807b VS |
2278 | DRM_ERROR("Pipe %c FIFO underrun\n", |
2279 | pipe_name(pipe)); | |
5a69b89f | 2280 | } |
8bf1e9f1 | 2281 | |
5a69b89f DV |
2282 | if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { |
2283 | if (IS_IVYBRIDGE(dev)) | |
277de95e | 2284 | ivb_pipe_crc_irq_handler(dev, pipe); |
5a69b89f | 2285 | else |
277de95e | 2286 | hsw_pipe_crc_irq_handler(dev, pipe); |
5a69b89f DV |
2287 | } |
2288 | } | |
8bf1e9f1 | 2289 | |
8664281b PZ |
2290 | I915_WRITE(GEN7_ERR_INT, err_int); |
2291 | } | |
2292 | ||
2293 | static void cpt_serr_int_handler(struct drm_device *dev) | |
2294 | { | |
2295 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2296 | u32 serr_int = I915_READ(SERR_INT); | |
2297 | ||
de032bf4 PZ |
2298 | if (serr_int & SERR_INT_POISON) |
2299 | DRM_ERROR("PCH poison interrupt\n"); | |
2300 | ||
8664281b PZ |
2301 | if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) |
2302 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, | |
2303 | false)) | |
fc2c807b | 2304 | DRM_ERROR("PCH transcoder A FIFO underrun\n"); |
8664281b PZ |
2305 | |
2306 | if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) | |
2307 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, | |
2308 | false)) | |
fc2c807b | 2309 | DRM_ERROR("PCH transcoder B FIFO underrun\n"); |
8664281b PZ |
2310 | |
2311 | if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) | |
2312 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C, | |
2313 | false)) | |
fc2c807b | 2314 | DRM_ERROR("PCH transcoder C FIFO underrun\n"); |
8664281b PZ |
2315 | |
2316 | I915_WRITE(SERR_INT, serr_int); | |
776ad806 JB |
2317 | } |
2318 | ||
23e81d69 AJ |
2319 | static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) |
2320 | { | |
2d1013dd | 2321 | struct drm_i915_private *dev_priv = dev->dev_private; |
23e81d69 | 2322 | int pipe; |
b543fb04 | 2323 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; |
13cf5504 DA |
2324 | u32 dig_hotplug_reg; |
2325 | ||
2326 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); | |
2327 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
23e81d69 | 2328 | |
13cf5504 | 2329 | intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_cpt); |
91d131d2 | 2330 | |
cfc33bf7 VS |
2331 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { |
2332 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> | |
2333 | SDE_AUDIO_POWER_SHIFT_CPT); | |
2334 | DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", | |
2335 | port_name(port)); | |
2336 | } | |
23e81d69 AJ |
2337 | |
2338 | if (pch_iir & SDE_AUX_MASK_CPT) | |
ce99c256 | 2339 | dp_aux_irq_handler(dev); |
23e81d69 AJ |
2340 | |
2341 | if (pch_iir & SDE_GMBUS_CPT) | |
515ac2bb | 2342 | gmbus_irq_handler(dev); |
23e81d69 AJ |
2343 | |
2344 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) | |
2345 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); | |
2346 | ||
2347 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) | |
2348 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); | |
2349 | ||
2350 | if (pch_iir & SDE_FDI_MASK_CPT) | |
055e393f | 2351 | for_each_pipe(dev_priv, pipe) |
23e81d69 AJ |
2352 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
2353 | pipe_name(pipe), | |
2354 | I915_READ(FDI_RX_IIR(pipe))); | |
8664281b PZ |
2355 | |
2356 | if (pch_iir & SDE_ERROR_CPT) | |
2357 | cpt_serr_int_handler(dev); | |
23e81d69 AJ |
2358 | } |
2359 | ||
c008bc6e PZ |
2360 | static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) |
2361 | { | |
2362 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40da17c2 | 2363 | enum pipe pipe; |
c008bc6e PZ |
2364 | |
2365 | if (de_iir & DE_AUX_CHANNEL_A) | |
2366 | dp_aux_irq_handler(dev); | |
2367 | ||
2368 | if (de_iir & DE_GSE) | |
2369 | intel_opregion_asle_intr(dev); | |
2370 | ||
c008bc6e PZ |
2371 | if (de_iir & DE_POISON) |
2372 | DRM_ERROR("Poison interrupt\n"); | |
2373 | ||
055e393f | 2374 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
2375 | if (de_iir & DE_PIPE_VBLANK(pipe) && |
2376 | intel_pipe_handle_vblank(dev, pipe)) | |
2377 | intel_check_page_flip(dev, pipe); | |
5b3a856b | 2378 | |
40da17c2 DV |
2379 | if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) |
2380 | if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
fc2c807b VS |
2381 | DRM_ERROR("Pipe %c FIFO underrun\n", |
2382 | pipe_name(pipe)); | |
5b3a856b | 2383 | |
40da17c2 DV |
2384 | if (de_iir & DE_PIPE_CRC_DONE(pipe)) |
2385 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
c008bc6e | 2386 | |
40da17c2 DV |
2387 | /* plane/pipes map 1:1 on ilk+ */ |
2388 | if (de_iir & DE_PLANE_FLIP_DONE(pipe)) { | |
2389 | intel_prepare_page_flip(dev, pipe); | |
2390 | intel_finish_page_flip_plane(dev, pipe); | |
2391 | } | |
c008bc6e PZ |
2392 | } |
2393 | ||
2394 | /* check event from PCH */ | |
2395 | if (de_iir & DE_PCH_EVENT) { | |
2396 | u32 pch_iir = I915_READ(SDEIIR); | |
2397 | ||
2398 | if (HAS_PCH_CPT(dev)) | |
2399 | cpt_irq_handler(dev, pch_iir); | |
2400 | else | |
2401 | ibx_irq_handler(dev, pch_iir); | |
2402 | ||
2403 | /* should clear PCH hotplug event before clear CPU irq */ | |
2404 | I915_WRITE(SDEIIR, pch_iir); | |
2405 | } | |
2406 | ||
2407 | if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) | |
2408 | ironlake_rps_change_irq_handler(dev); | |
2409 | } | |
2410 | ||
9719fb98 PZ |
2411 | static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir) |
2412 | { | |
2413 | struct drm_i915_private *dev_priv = dev->dev_private; | |
07d27e20 | 2414 | enum pipe pipe; |
9719fb98 PZ |
2415 | |
2416 | if (de_iir & DE_ERR_INT_IVB) | |
2417 | ivb_err_int_handler(dev); | |
2418 | ||
2419 | if (de_iir & DE_AUX_CHANNEL_A_IVB) | |
2420 | dp_aux_irq_handler(dev); | |
2421 | ||
2422 | if (de_iir & DE_GSE_IVB) | |
2423 | intel_opregion_asle_intr(dev); | |
2424 | ||
055e393f | 2425 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
2426 | if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) && |
2427 | intel_pipe_handle_vblank(dev, pipe)) | |
2428 | intel_check_page_flip(dev, pipe); | |
40da17c2 DV |
2429 | |
2430 | /* plane/pipes map 1:1 on ilk+ */ | |
07d27e20 DL |
2431 | if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) { |
2432 | intel_prepare_page_flip(dev, pipe); | |
2433 | intel_finish_page_flip_plane(dev, pipe); | |
9719fb98 PZ |
2434 | } |
2435 | } | |
2436 | ||
2437 | /* check event from PCH */ | |
2438 | if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) { | |
2439 | u32 pch_iir = I915_READ(SDEIIR); | |
2440 | ||
2441 | cpt_irq_handler(dev, pch_iir); | |
2442 | ||
2443 | /* clear PCH hotplug event before clear CPU irq */ | |
2444 | I915_WRITE(SDEIIR, pch_iir); | |
2445 | } | |
2446 | } | |
2447 | ||
72c90f62 OM |
2448 | /* |
2449 | * To handle irqs with the minimum potential races with fresh interrupts, we: | |
2450 | * 1 - Disable Master Interrupt Control. | |
2451 | * 2 - Find the source(s) of the interrupt. | |
2452 | * 3 - Clear the Interrupt Identity bits (IIR). | |
2453 | * 4 - Process the interrupt(s) that had bits set in the IIRs. | |
2454 | * 5 - Re-enable Master Interrupt Control. | |
2455 | */ | |
f1af8fc1 | 2456 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
b1f14ad0 | 2457 | { |
45a83f84 | 2458 | struct drm_device *dev = arg; |
2d1013dd | 2459 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1af8fc1 | 2460 | u32 de_iir, gt_iir, de_ier, sde_ier = 0; |
0e43406b | 2461 | irqreturn_t ret = IRQ_NONE; |
b1f14ad0 | 2462 | |
8664281b PZ |
2463 | /* We get interrupts on unclaimed registers, so check for this before we |
2464 | * do any I915_{READ,WRITE}. */ | |
907b28c5 | 2465 | intel_uncore_check_errors(dev); |
8664281b | 2466 | |
b1f14ad0 JB |
2467 | /* disable master interrupt before clearing iir */ |
2468 | de_ier = I915_READ(DEIER); | |
2469 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
23a78516 | 2470 | POSTING_READ(DEIER); |
b1f14ad0 | 2471 | |
44498aea PZ |
2472 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
2473 | * interrupts will will be stored on its back queue, and then we'll be | |
2474 | * able to process them after we restore SDEIER (as soon as we restore | |
2475 | * it, we'll get an interrupt if SDEIIR still has something to process | |
2476 | * due to its back queue). */ | |
ab5c608b BW |
2477 | if (!HAS_PCH_NOP(dev)) { |
2478 | sde_ier = I915_READ(SDEIER); | |
2479 | I915_WRITE(SDEIER, 0); | |
2480 | POSTING_READ(SDEIER); | |
2481 | } | |
44498aea | 2482 | |
72c90f62 OM |
2483 | /* Find, clear, then process each source of interrupt */ |
2484 | ||
b1f14ad0 | 2485 | gt_iir = I915_READ(GTIIR); |
0e43406b | 2486 | if (gt_iir) { |
72c90f62 OM |
2487 | I915_WRITE(GTIIR, gt_iir); |
2488 | ret = IRQ_HANDLED; | |
d8fc8a47 | 2489 | if (INTEL_INFO(dev)->gen >= 6) |
f1af8fc1 | 2490 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
d8fc8a47 PZ |
2491 | else |
2492 | ilk_gt_irq_handler(dev, dev_priv, gt_iir); | |
b1f14ad0 JB |
2493 | } |
2494 | ||
0e43406b CW |
2495 | de_iir = I915_READ(DEIIR); |
2496 | if (de_iir) { | |
72c90f62 OM |
2497 | I915_WRITE(DEIIR, de_iir); |
2498 | ret = IRQ_HANDLED; | |
f1af8fc1 PZ |
2499 | if (INTEL_INFO(dev)->gen >= 7) |
2500 | ivb_display_irq_handler(dev, de_iir); | |
2501 | else | |
2502 | ilk_display_irq_handler(dev, de_iir); | |
b1f14ad0 JB |
2503 | } |
2504 | ||
f1af8fc1 PZ |
2505 | if (INTEL_INFO(dev)->gen >= 6) { |
2506 | u32 pm_iir = I915_READ(GEN6_PMIIR); | |
2507 | if (pm_iir) { | |
f1af8fc1 PZ |
2508 | I915_WRITE(GEN6_PMIIR, pm_iir); |
2509 | ret = IRQ_HANDLED; | |
72c90f62 | 2510 | gen6_rps_irq_handler(dev_priv, pm_iir); |
f1af8fc1 | 2511 | } |
0e43406b | 2512 | } |
b1f14ad0 | 2513 | |
b1f14ad0 JB |
2514 | I915_WRITE(DEIER, de_ier); |
2515 | POSTING_READ(DEIER); | |
ab5c608b BW |
2516 | if (!HAS_PCH_NOP(dev)) { |
2517 | I915_WRITE(SDEIER, sde_ier); | |
2518 | POSTING_READ(SDEIER); | |
2519 | } | |
b1f14ad0 JB |
2520 | |
2521 | return ret; | |
2522 | } | |
2523 | ||
abd58f01 BW |
2524 | static irqreturn_t gen8_irq_handler(int irq, void *arg) |
2525 | { | |
2526 | struct drm_device *dev = arg; | |
2527 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2528 | u32 master_ctl; | |
2529 | irqreturn_t ret = IRQ_NONE; | |
2530 | uint32_t tmp = 0; | |
c42664cc | 2531 | enum pipe pipe; |
abd58f01 | 2532 | |
abd58f01 BW |
2533 | master_ctl = I915_READ(GEN8_MASTER_IRQ); |
2534 | master_ctl &= ~GEN8_MASTER_IRQ_CONTROL; | |
2535 | if (!master_ctl) | |
2536 | return IRQ_NONE; | |
2537 | ||
2538 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
2539 | POSTING_READ(GEN8_MASTER_IRQ); | |
2540 | ||
38cc46d7 OM |
2541 | /* Find, clear, then process each source of interrupt */ |
2542 | ||
abd58f01 BW |
2543 | ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl); |
2544 | ||
2545 | if (master_ctl & GEN8_DE_MISC_IRQ) { | |
2546 | tmp = I915_READ(GEN8_DE_MISC_IIR); | |
abd58f01 BW |
2547 | if (tmp) { |
2548 | I915_WRITE(GEN8_DE_MISC_IIR, tmp); | |
2549 | ret = IRQ_HANDLED; | |
38cc46d7 OM |
2550 | if (tmp & GEN8_DE_MISC_GSE) |
2551 | intel_opregion_asle_intr(dev); | |
2552 | else | |
2553 | DRM_ERROR("Unexpected DE Misc interrupt\n"); | |
abd58f01 | 2554 | } |
38cc46d7 OM |
2555 | else |
2556 | DRM_ERROR("The master control interrupt lied (DE MISC)!\n"); | |
abd58f01 BW |
2557 | } |
2558 | ||
6d766f02 DV |
2559 | if (master_ctl & GEN8_DE_PORT_IRQ) { |
2560 | tmp = I915_READ(GEN8_DE_PORT_IIR); | |
6d766f02 DV |
2561 | if (tmp) { |
2562 | I915_WRITE(GEN8_DE_PORT_IIR, tmp); | |
2563 | ret = IRQ_HANDLED; | |
38cc46d7 OM |
2564 | if (tmp & GEN8_AUX_CHANNEL_A) |
2565 | dp_aux_irq_handler(dev); | |
2566 | else | |
2567 | DRM_ERROR("Unexpected DE Port interrupt\n"); | |
6d766f02 | 2568 | } |
38cc46d7 OM |
2569 | else |
2570 | DRM_ERROR("The master control interrupt lied (DE PORT)!\n"); | |
6d766f02 DV |
2571 | } |
2572 | ||
055e393f | 2573 | for_each_pipe(dev_priv, pipe) { |
770de83d | 2574 | uint32_t pipe_iir, flip_done = 0, fault_errors = 0; |
abd58f01 | 2575 | |
c42664cc DV |
2576 | if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) |
2577 | continue; | |
abd58f01 | 2578 | |
c42664cc | 2579 | pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); |
c42664cc DV |
2580 | if (pipe_iir) { |
2581 | ret = IRQ_HANDLED; | |
2582 | I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir); | |
770de83d | 2583 | |
d6bbafa1 CW |
2584 | if (pipe_iir & GEN8_PIPE_VBLANK && |
2585 | intel_pipe_handle_vblank(dev, pipe)) | |
2586 | intel_check_page_flip(dev, pipe); | |
38cc46d7 | 2587 | |
770de83d DL |
2588 | if (IS_GEN9(dev)) |
2589 | flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE; | |
2590 | else | |
2591 | flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE; | |
2592 | ||
2593 | if (flip_done) { | |
38cc46d7 OM |
2594 | intel_prepare_page_flip(dev, pipe); |
2595 | intel_finish_page_flip_plane(dev, pipe); | |
2596 | } | |
2597 | ||
2598 | if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE) | |
2599 | hsw_pipe_crc_irq_handler(dev, pipe); | |
2600 | ||
2601 | if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) { | |
2602 | if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, | |
2603 | false)) | |
2604 | DRM_ERROR("Pipe %c FIFO underrun\n", | |
2605 | pipe_name(pipe)); | |
2606 | } | |
2607 | ||
770de83d DL |
2608 | |
2609 | if (IS_GEN9(dev)) | |
2610 | fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS; | |
2611 | else | |
2612 | fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
2613 | ||
2614 | if (fault_errors) | |
38cc46d7 OM |
2615 | DRM_ERROR("Fault errors on pipe %c\n: 0x%08x", |
2616 | pipe_name(pipe), | |
2617 | pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS); | |
c42664cc | 2618 | } else |
abd58f01 BW |
2619 | DRM_ERROR("The master control interrupt lied (DE PIPE)!\n"); |
2620 | } | |
2621 | ||
92d03a80 DV |
2622 | if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) { |
2623 | /* | |
2624 | * FIXME(BDW): Assume for now that the new interrupt handling | |
2625 | * scheme also closed the SDE interrupt handling race we've seen | |
2626 | * on older pch-split platforms. But this needs testing. | |
2627 | */ | |
2628 | u32 pch_iir = I915_READ(SDEIIR); | |
92d03a80 DV |
2629 | if (pch_iir) { |
2630 | I915_WRITE(SDEIIR, pch_iir); | |
2631 | ret = IRQ_HANDLED; | |
38cc46d7 OM |
2632 | cpt_irq_handler(dev, pch_iir); |
2633 | } else | |
2634 | DRM_ERROR("The master control interrupt lied (SDE)!\n"); | |
2635 | ||
92d03a80 DV |
2636 | } |
2637 | ||
abd58f01 BW |
2638 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
2639 | POSTING_READ(GEN8_MASTER_IRQ); | |
2640 | ||
2641 | return ret; | |
2642 | } | |
2643 | ||
17e1df07 DV |
2644 | static void i915_error_wake_up(struct drm_i915_private *dev_priv, |
2645 | bool reset_completed) | |
2646 | { | |
a4872ba6 | 2647 | struct intel_engine_cs *ring; |
17e1df07 DV |
2648 | int i; |
2649 | ||
2650 | /* | |
2651 | * Notify all waiters for GPU completion events that reset state has | |
2652 | * been changed, and that they need to restart their wait after | |
2653 | * checking for potential errors (and bail out to drop locks if there is | |
2654 | * a gpu reset pending so that i915_error_work_func can acquire them). | |
2655 | */ | |
2656 | ||
2657 | /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */ | |
2658 | for_each_ring(ring, dev_priv, i) | |
2659 | wake_up_all(&ring->irq_queue); | |
2660 | ||
2661 | /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */ | |
2662 | wake_up_all(&dev_priv->pending_flip_queue); | |
2663 | ||
2664 | /* | |
2665 | * Signal tasks blocked in i915_gem_wait_for_error that the pending | |
2666 | * reset state is cleared. | |
2667 | */ | |
2668 | if (reset_completed) | |
2669 | wake_up_all(&dev_priv->gpu_error.reset_queue); | |
2670 | } | |
2671 | ||
8a905236 JB |
2672 | /** |
2673 | * i915_error_work_func - do process context error handling work | |
2674 | * @work: work struct | |
2675 | * | |
2676 | * Fire an error uevent so userspace can see that a hang or error | |
2677 | * was detected. | |
2678 | */ | |
2679 | static void i915_error_work_func(struct work_struct *work) | |
2680 | { | |
1f83fee0 DV |
2681 | struct i915_gpu_error *error = container_of(work, struct i915_gpu_error, |
2682 | work); | |
2d1013dd JN |
2683 | struct drm_i915_private *dev_priv = |
2684 | container_of(error, struct drm_i915_private, gpu_error); | |
8a905236 | 2685 | struct drm_device *dev = dev_priv->dev; |
cce723ed BW |
2686 | char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; |
2687 | char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; | |
2688 | char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; | |
17e1df07 | 2689 | int ret; |
8a905236 | 2690 | |
5bdebb18 | 2691 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event); |
f316a42c | 2692 | |
7db0ba24 DV |
2693 | /* |
2694 | * Note that there's only one work item which does gpu resets, so we | |
2695 | * need not worry about concurrent gpu resets potentially incrementing | |
2696 | * error->reset_counter twice. We only need to take care of another | |
2697 | * racing irq/hangcheck declaring the gpu dead for a second time. A | |
2698 | * quick check for that is good enough: schedule_work ensures the | |
2699 | * correct ordering between hang detection and this work item, and since | |
2700 | * the reset in-progress bit is only ever set by code outside of this | |
2701 | * work we don't need to worry about any other races. | |
2702 | */ | |
2703 | if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) { | |
f803aa55 | 2704 | DRM_DEBUG_DRIVER("resetting chip\n"); |
5bdebb18 | 2705 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, |
7db0ba24 | 2706 | reset_event); |
1f83fee0 | 2707 | |
f454c694 ID |
2708 | /* |
2709 | * In most cases it's guaranteed that we get here with an RPM | |
2710 | * reference held, for example because there is a pending GPU | |
2711 | * request that won't finish until the reset is done. This | |
2712 | * isn't the case at least when we get here by doing a | |
2713 | * simulated reset via debugs, so get an RPM reference. | |
2714 | */ | |
2715 | intel_runtime_pm_get(dev_priv); | |
17e1df07 DV |
2716 | /* |
2717 | * All state reset _must_ be completed before we update the | |
2718 | * reset counter, for otherwise waiters might miss the reset | |
2719 | * pending state and not properly drop locks, resulting in | |
2720 | * deadlocks with the reset work. | |
2721 | */ | |
f69061be DV |
2722 | ret = i915_reset(dev); |
2723 | ||
17e1df07 DV |
2724 | intel_display_handle_reset(dev); |
2725 | ||
f454c694 ID |
2726 | intel_runtime_pm_put(dev_priv); |
2727 | ||
f69061be DV |
2728 | if (ret == 0) { |
2729 | /* | |
2730 | * After all the gem state is reset, increment the reset | |
2731 | * counter and wake up everyone waiting for the reset to | |
2732 | * complete. | |
2733 | * | |
2734 | * Since unlock operations are a one-sided barrier only, | |
2735 | * we need to insert a barrier here to order any seqno | |
2736 | * updates before | |
2737 | * the counter increment. | |
2738 | */ | |
4e857c58 | 2739 | smp_mb__before_atomic(); |
f69061be DV |
2740 | atomic_inc(&dev_priv->gpu_error.reset_counter); |
2741 | ||
5bdebb18 | 2742 | kobject_uevent_env(&dev->primary->kdev->kobj, |
f69061be | 2743 | KOBJ_CHANGE, reset_done_event); |
1f83fee0 | 2744 | } else { |
2ac0f450 | 2745 | atomic_set_mask(I915_WEDGED, &error->reset_counter); |
f316a42c | 2746 | } |
1f83fee0 | 2747 | |
17e1df07 DV |
2748 | /* |
2749 | * Note: The wake_up also serves as a memory barrier so that | |
2750 | * waiters see the update value of the reset counter atomic_t. | |
2751 | */ | |
2752 | i915_error_wake_up(dev_priv, true); | |
f316a42c | 2753 | } |
8a905236 JB |
2754 | } |
2755 | ||
35aed2e6 | 2756 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
2757 | { |
2758 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bd9854f9 | 2759 | uint32_t instdone[I915_NUM_INSTDONE_REG]; |
8a905236 | 2760 | u32 eir = I915_READ(EIR); |
050ee91f | 2761 | int pipe, i; |
8a905236 | 2762 | |
35aed2e6 CW |
2763 | if (!eir) |
2764 | return; | |
8a905236 | 2765 | |
a70491cc | 2766 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
8a905236 | 2767 | |
bd9854f9 BW |
2768 | i915_get_extra_instdone(dev, instdone); |
2769 | ||
8a905236 JB |
2770 | if (IS_G4X(dev)) { |
2771 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
2772 | u32 ipeir = I915_READ(IPEIR_I965); | |
2773 | ||
a70491cc JP |
2774 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2775 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
050ee91f BW |
2776 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2777 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a70491cc | 2778 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2779 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2780 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2781 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2782 | } |
2783 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
2784 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2785 | pr_err("page table error\n"); |
2786 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2787 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2788 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2789 | } |
2790 | } | |
2791 | ||
a6c45cf0 | 2792 | if (!IS_GEN2(dev)) { |
8a905236 JB |
2793 | if (eir & I915_ERROR_PAGE_TABLE) { |
2794 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2795 | pr_err("page table error\n"); |
2796 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2797 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2798 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2799 | } |
2800 | } | |
2801 | ||
2802 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
a70491cc | 2803 | pr_err("memory refresh error:\n"); |
055e393f | 2804 | for_each_pipe(dev_priv, pipe) |
a70491cc | 2805 | pr_err("pipe %c stat: 0x%08x\n", |
9db4a9c7 | 2806 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
8a905236 JB |
2807 | /* pipestat has already been acked */ |
2808 | } | |
2809 | if (eir & I915_ERROR_INSTRUCTION) { | |
a70491cc JP |
2810 | pr_err("instruction error\n"); |
2811 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); | |
050ee91f BW |
2812 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2813 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a6c45cf0 | 2814 | if (INTEL_INFO(dev)->gen < 4) { |
8a905236 JB |
2815 | u32 ipeir = I915_READ(IPEIR); |
2816 | ||
a70491cc JP |
2817 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
2818 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); | |
a70491cc | 2819 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); |
8a905236 | 2820 | I915_WRITE(IPEIR, ipeir); |
3143a2bf | 2821 | POSTING_READ(IPEIR); |
8a905236 JB |
2822 | } else { |
2823 | u32 ipeir = I915_READ(IPEIR_I965); | |
2824 | ||
a70491cc JP |
2825 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2826 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
a70491cc | 2827 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2828 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2829 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2830 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2831 | } |
2832 | } | |
2833 | ||
2834 | I915_WRITE(EIR, eir); | |
3143a2bf | 2835 | POSTING_READ(EIR); |
8a905236 JB |
2836 | eir = I915_READ(EIR); |
2837 | if (eir) { | |
2838 | /* | |
2839 | * some errors might have become stuck, | |
2840 | * mask them. | |
2841 | */ | |
2842 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
2843 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
2844 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2845 | } | |
35aed2e6 CW |
2846 | } |
2847 | ||
2848 | /** | |
2849 | * i915_handle_error - handle an error interrupt | |
2850 | * @dev: drm device | |
2851 | * | |
2852 | * Do some basic checking of regsiter state at error interrupt time and | |
2853 | * dump it to the syslog. Also call i915_capture_error_state() to make | |
2854 | * sure we get a record and make it available in debugfs. Fire a uevent | |
2855 | * so userspace knows something bad happened (should trigger collection | |
2856 | * of a ring dump etc.). | |
2857 | */ | |
58174462 MK |
2858 | void i915_handle_error(struct drm_device *dev, bool wedged, |
2859 | const char *fmt, ...) | |
35aed2e6 CW |
2860 | { |
2861 | struct drm_i915_private *dev_priv = dev->dev_private; | |
58174462 MK |
2862 | va_list args; |
2863 | char error_msg[80]; | |
35aed2e6 | 2864 | |
58174462 MK |
2865 | va_start(args, fmt); |
2866 | vscnprintf(error_msg, sizeof(error_msg), fmt, args); | |
2867 | va_end(args); | |
2868 | ||
2869 | i915_capture_error_state(dev, wedged, error_msg); | |
35aed2e6 | 2870 | i915_report_and_clear_eir(dev); |
8a905236 | 2871 | |
ba1234d1 | 2872 | if (wedged) { |
f69061be DV |
2873 | atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG, |
2874 | &dev_priv->gpu_error.reset_counter); | |
ba1234d1 | 2875 | |
11ed50ec | 2876 | /* |
17e1df07 DV |
2877 | * Wakeup waiting processes so that the reset work function |
2878 | * i915_error_work_func doesn't deadlock trying to grab various | |
2879 | * locks. By bumping the reset counter first, the woken | |
2880 | * processes will see a reset in progress and back off, | |
2881 | * releasing their locks and then wait for the reset completion. | |
2882 | * We must do this for _all_ gpu waiters that might hold locks | |
2883 | * that the reset work needs to acquire. | |
2884 | * | |
2885 | * Note: The wake_up serves as the required memory barrier to | |
2886 | * ensure that the waiters see the updated value of the reset | |
2887 | * counter atomic_t. | |
11ed50ec | 2888 | */ |
17e1df07 | 2889 | i915_error_wake_up(dev_priv, false); |
11ed50ec BG |
2890 | } |
2891 | ||
122f46ba DV |
2892 | /* |
2893 | * Our reset work can grab modeset locks (since it needs to reset the | |
2894 | * state of outstanding pagelips). Hence it must not be run on our own | |
2895 | * dev-priv->wq work queue for otherwise the flush_work in the pageflip | |
2896 | * code will deadlock. | |
2897 | */ | |
2898 | schedule_work(&dev_priv->gpu_error.work); | |
8a905236 JB |
2899 | } |
2900 | ||
42f52ef8 KP |
2901 | /* Called from drm generic code, passed 'crtc' which |
2902 | * we use as a pipe index | |
2903 | */ | |
f71d4af4 | 2904 | static int i915_enable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 | 2905 | { |
2d1013dd | 2906 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2907 | unsigned long irqflags; |
71e0ffa5 | 2908 | |
5eddb70b | 2909 | if (!i915_pipe_enabled(dev, pipe)) |
71e0ffa5 | 2910 | return -EINVAL; |
0a3e67a4 | 2911 | |
1ec14ad3 | 2912 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2913 | if (INTEL_INFO(dev)->gen >= 4) |
7c463586 | 2914 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2915 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
e9d21d7f | 2916 | else |
7c463586 | 2917 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2918 | PIPE_VBLANK_INTERRUPT_STATUS); |
1ec14ad3 | 2919 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
8692d00e | 2920 | |
0a3e67a4 JB |
2921 | return 0; |
2922 | } | |
2923 | ||
f71d4af4 | 2924 | static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
f796cf8f | 2925 | { |
2d1013dd | 2926 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2927 | unsigned long irqflags; |
b518421f | 2928 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2929 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2930 | |
2931 | if (!i915_pipe_enabled(dev, pipe)) | |
2932 | return -EINVAL; | |
2933 | ||
2934 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 2935 | ironlake_enable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2936 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2937 | ||
2938 | return 0; | |
2939 | } | |
2940 | ||
7e231dbe JB |
2941 | static int valleyview_enable_vblank(struct drm_device *dev, int pipe) |
2942 | { | |
2d1013dd | 2943 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2944 | unsigned long irqflags; |
7e231dbe JB |
2945 | |
2946 | if (!i915_pipe_enabled(dev, pipe)) | |
2947 | return -EINVAL; | |
2948 | ||
2949 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 | 2950 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2951 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2952 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2953 | ||
2954 | return 0; | |
2955 | } | |
2956 | ||
abd58f01 BW |
2957 | static int gen8_enable_vblank(struct drm_device *dev, int pipe) |
2958 | { | |
2959 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2960 | unsigned long irqflags; | |
abd58f01 BW |
2961 | |
2962 | if (!i915_pipe_enabled(dev, pipe)) | |
2963 | return -EINVAL; | |
2964 | ||
2965 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
7167d7c6 DV |
2966 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK; |
2967 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2968 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2969 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2970 | return 0; | |
2971 | } | |
2972 | ||
42f52ef8 KP |
2973 | /* Called from drm generic code, passed 'crtc' which |
2974 | * we use as a pipe index | |
2975 | */ | |
f71d4af4 | 2976 | static void i915_disable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 | 2977 | { |
2d1013dd | 2978 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2979 | unsigned long irqflags; |
0a3e67a4 | 2980 | |
1ec14ad3 | 2981 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2982 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 ID |
2983 | PIPE_VBLANK_INTERRUPT_STATUS | |
2984 | PIPE_START_VBLANK_INTERRUPT_STATUS); | |
f796cf8f JB |
2985 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2986 | } | |
2987 | ||
f71d4af4 | 2988 | static void ironlake_disable_vblank(struct drm_device *dev, int pipe) |
f796cf8f | 2989 | { |
2d1013dd | 2990 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2991 | unsigned long irqflags; |
b518421f | 2992 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2993 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2994 | |
2995 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 2996 | ironlake_disable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2997 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2998 | } | |
2999 | ||
7e231dbe JB |
3000 | static void valleyview_disable_vblank(struct drm_device *dev, int pipe) |
3001 | { | |
2d1013dd | 3002 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 3003 | unsigned long irqflags; |
7e231dbe JB |
3004 | |
3005 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 | 3006 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 | 3007 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
3008 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
3009 | } | |
3010 | ||
abd58f01 BW |
3011 | static void gen8_disable_vblank(struct drm_device *dev, int pipe) |
3012 | { | |
3013 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3014 | unsigned long irqflags; | |
abd58f01 BW |
3015 | |
3016 | if (!i915_pipe_enabled(dev, pipe)) | |
3017 | return; | |
3018 | ||
3019 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
7167d7c6 DV |
3020 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK; |
3021 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
3022 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
3023 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
3024 | } | |
3025 | ||
893eead0 | 3026 | static u32 |
a4872ba6 | 3027 | ring_last_seqno(struct intel_engine_cs *ring) |
852835f3 | 3028 | { |
893eead0 CW |
3029 | return list_entry(ring->request_list.prev, |
3030 | struct drm_i915_gem_request, list)->seqno; | |
3031 | } | |
3032 | ||
9107e9d2 | 3033 | static bool |
a4872ba6 | 3034 | ring_idle(struct intel_engine_cs *ring, u32 seqno) |
9107e9d2 CW |
3035 | { |
3036 | return (list_empty(&ring->request_list) || | |
3037 | i915_seqno_passed(seqno, ring_last_seqno(ring))); | |
f65d9421 BG |
3038 | } |
3039 | ||
a028c4b0 DV |
3040 | static bool |
3041 | ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr) | |
3042 | { | |
3043 | if (INTEL_INFO(dev)->gen >= 8) { | |
a6cdb93a | 3044 | return (ipehr >> 23) == 0x1c; |
a028c4b0 DV |
3045 | } else { |
3046 | ipehr &= ~MI_SEMAPHORE_SYNC_MASK; | |
3047 | return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | | |
3048 | MI_SEMAPHORE_REGISTER); | |
3049 | } | |
3050 | } | |
3051 | ||
a4872ba6 | 3052 | static struct intel_engine_cs * |
a6cdb93a | 3053 | semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset) |
921d42ea DV |
3054 | { |
3055 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
a4872ba6 | 3056 | struct intel_engine_cs *signaller; |
921d42ea DV |
3057 | int i; |
3058 | ||
3059 | if (INTEL_INFO(dev_priv->dev)->gen >= 8) { | |
a6cdb93a RV |
3060 | for_each_ring(signaller, dev_priv, i) { |
3061 | if (ring == signaller) | |
3062 | continue; | |
3063 | ||
3064 | if (offset == signaller->semaphore.signal_ggtt[ring->id]) | |
3065 | return signaller; | |
3066 | } | |
921d42ea DV |
3067 | } else { |
3068 | u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK; | |
3069 | ||
3070 | for_each_ring(signaller, dev_priv, i) { | |
3071 | if(ring == signaller) | |
3072 | continue; | |
3073 | ||
ebc348b2 | 3074 | if (sync_bits == signaller->semaphore.mbox.wait[ring->id]) |
921d42ea DV |
3075 | return signaller; |
3076 | } | |
3077 | } | |
3078 | ||
a6cdb93a RV |
3079 | DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n", |
3080 | ring->id, ipehr, offset); | |
921d42ea DV |
3081 | |
3082 | return NULL; | |
3083 | } | |
3084 | ||
a4872ba6 OM |
3085 | static struct intel_engine_cs * |
3086 | semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno) | |
a24a11e6 CW |
3087 | { |
3088 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
88fe429d | 3089 | u32 cmd, ipehr, head; |
a6cdb93a RV |
3090 | u64 offset = 0; |
3091 | int i, backwards; | |
a24a11e6 CW |
3092 | |
3093 | ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); | |
a028c4b0 | 3094 | if (!ipehr_is_semaphore_wait(ring->dev, ipehr)) |
6274f212 | 3095 | return NULL; |
a24a11e6 | 3096 | |
88fe429d DV |
3097 | /* |
3098 | * HEAD is likely pointing to the dword after the actual command, | |
3099 | * so scan backwards until we find the MBOX. But limit it to just 3 | |
a6cdb93a RV |
3100 | * or 4 dwords depending on the semaphore wait command size. |
3101 | * Note that we don't care about ACTHD here since that might | |
88fe429d DV |
3102 | * point at at batch, and semaphores are always emitted into the |
3103 | * ringbuffer itself. | |
a24a11e6 | 3104 | */ |
88fe429d | 3105 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
a6cdb93a | 3106 | backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4; |
88fe429d | 3107 | |
a6cdb93a | 3108 | for (i = backwards; i; --i) { |
88fe429d DV |
3109 | /* |
3110 | * Be paranoid and presume the hw has gone off into the wild - | |
3111 | * our ring is smaller than what the hardware (and hence | |
3112 | * HEAD_ADDR) allows. Also handles wrap-around. | |
3113 | */ | |
ee1b1e5e | 3114 | head &= ring->buffer->size - 1; |
88fe429d DV |
3115 | |
3116 | /* This here seems to blow up */ | |
ee1b1e5e | 3117 | cmd = ioread32(ring->buffer->virtual_start + head); |
a24a11e6 CW |
3118 | if (cmd == ipehr) |
3119 | break; | |
3120 | ||
88fe429d DV |
3121 | head -= 4; |
3122 | } | |
a24a11e6 | 3123 | |
88fe429d DV |
3124 | if (!i) |
3125 | return NULL; | |
a24a11e6 | 3126 | |
ee1b1e5e | 3127 | *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1; |
a6cdb93a RV |
3128 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
3129 | offset = ioread32(ring->buffer->virtual_start + head + 12); | |
3130 | offset <<= 32; | |
3131 | offset = ioread32(ring->buffer->virtual_start + head + 8); | |
3132 | } | |
3133 | return semaphore_wait_to_signaller_ring(ring, ipehr, offset); | |
a24a11e6 CW |
3134 | } |
3135 | ||
a4872ba6 | 3136 | static int semaphore_passed(struct intel_engine_cs *ring) |
6274f212 CW |
3137 | { |
3138 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
a4872ba6 | 3139 | struct intel_engine_cs *signaller; |
a0d036b0 | 3140 | u32 seqno; |
6274f212 | 3141 | |
4be17381 | 3142 | ring->hangcheck.deadlock++; |
6274f212 CW |
3143 | |
3144 | signaller = semaphore_waits_for(ring, &seqno); | |
4be17381 CW |
3145 | if (signaller == NULL) |
3146 | return -1; | |
3147 | ||
3148 | /* Prevent pathological recursion due to driver bugs */ | |
3149 | if (signaller->hangcheck.deadlock >= I915_NUM_RINGS) | |
6274f212 CW |
3150 | return -1; |
3151 | ||
4be17381 CW |
3152 | if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno)) |
3153 | return 1; | |
3154 | ||
a0d036b0 CW |
3155 | /* cursory check for an unkickable deadlock */ |
3156 | if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE && | |
3157 | semaphore_passed(signaller) < 0) | |
4be17381 CW |
3158 | return -1; |
3159 | ||
3160 | return 0; | |
6274f212 CW |
3161 | } |
3162 | ||
3163 | static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) | |
3164 | { | |
a4872ba6 | 3165 | struct intel_engine_cs *ring; |
6274f212 CW |
3166 | int i; |
3167 | ||
3168 | for_each_ring(ring, dev_priv, i) | |
4be17381 | 3169 | ring->hangcheck.deadlock = 0; |
6274f212 CW |
3170 | } |
3171 | ||
ad8beaea | 3172 | static enum intel_ring_hangcheck_action |
a4872ba6 | 3173 | ring_stuck(struct intel_engine_cs *ring, u64 acthd) |
1ec14ad3 CW |
3174 | { |
3175 | struct drm_device *dev = ring->dev; | |
3176 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9107e9d2 CW |
3177 | u32 tmp; |
3178 | ||
f260fe7b MK |
3179 | if (acthd != ring->hangcheck.acthd) { |
3180 | if (acthd > ring->hangcheck.max_acthd) { | |
3181 | ring->hangcheck.max_acthd = acthd; | |
3182 | return HANGCHECK_ACTIVE; | |
3183 | } | |
3184 | ||
3185 | return HANGCHECK_ACTIVE_LOOP; | |
3186 | } | |
6274f212 | 3187 | |
9107e9d2 | 3188 | if (IS_GEN2(dev)) |
f2f4d82f | 3189 | return HANGCHECK_HUNG; |
9107e9d2 CW |
3190 | |
3191 | /* Is the chip hanging on a WAIT_FOR_EVENT? | |
3192 | * If so we can simply poke the RB_WAIT bit | |
3193 | * and break the hang. This should work on | |
3194 | * all but the second generation chipsets. | |
3195 | */ | |
3196 | tmp = I915_READ_CTL(ring); | |
1ec14ad3 | 3197 | if (tmp & RING_WAIT) { |
58174462 MK |
3198 | i915_handle_error(dev, false, |
3199 | "Kicking stuck wait on %s", | |
3200 | ring->name); | |
1ec14ad3 | 3201 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 3202 | return HANGCHECK_KICK; |
6274f212 CW |
3203 | } |
3204 | ||
3205 | if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { | |
3206 | switch (semaphore_passed(ring)) { | |
3207 | default: | |
f2f4d82f | 3208 | return HANGCHECK_HUNG; |
6274f212 | 3209 | case 1: |
58174462 MK |
3210 | i915_handle_error(dev, false, |
3211 | "Kicking stuck semaphore on %s", | |
3212 | ring->name); | |
6274f212 | 3213 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 3214 | return HANGCHECK_KICK; |
6274f212 | 3215 | case 0: |
f2f4d82f | 3216 | return HANGCHECK_WAIT; |
6274f212 | 3217 | } |
9107e9d2 | 3218 | } |
ed5cbb03 | 3219 | |
f2f4d82f | 3220 | return HANGCHECK_HUNG; |
ed5cbb03 MK |
3221 | } |
3222 | ||
f65d9421 BG |
3223 | /** |
3224 | * This is called when the chip hasn't reported back with completed | |
05407ff8 MK |
3225 | * batchbuffers in a long time. We keep track per ring seqno progress and |
3226 | * if there are no progress, hangcheck score for that ring is increased. | |
3227 | * Further, acthd is inspected to see if the ring is stuck. On stuck case | |
3228 | * we kick the ring. If we see no progress on three subsequent calls | |
3229 | * we assume chip is wedged and try to fix it by resetting the chip. | |
f65d9421 | 3230 | */ |
a658b5d2 | 3231 | static void i915_hangcheck_elapsed(unsigned long data) |
f65d9421 BG |
3232 | { |
3233 | struct drm_device *dev = (struct drm_device *)data; | |
2d1013dd | 3234 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 3235 | struct intel_engine_cs *ring; |
b4519513 | 3236 | int i; |
05407ff8 | 3237 | int busy_count = 0, rings_hung = 0; |
9107e9d2 CW |
3238 | bool stuck[I915_NUM_RINGS] = { 0 }; |
3239 | #define BUSY 1 | |
3240 | #define KICK 5 | |
3241 | #define HUNG 20 | |
893eead0 | 3242 | |
d330a953 | 3243 | if (!i915.enable_hangcheck) |
3e0dc6b0 BW |
3244 | return; |
3245 | ||
b4519513 | 3246 | for_each_ring(ring, dev_priv, i) { |
50877445 CW |
3247 | u64 acthd; |
3248 | u32 seqno; | |
9107e9d2 | 3249 | bool busy = true; |
05407ff8 | 3250 | |
6274f212 CW |
3251 | semaphore_clear_deadlocks(dev_priv); |
3252 | ||
05407ff8 MK |
3253 | seqno = ring->get_seqno(ring, false); |
3254 | acthd = intel_ring_get_active_head(ring); | |
b4519513 | 3255 | |
9107e9d2 CW |
3256 | if (ring->hangcheck.seqno == seqno) { |
3257 | if (ring_idle(ring, seqno)) { | |
da661464 MK |
3258 | ring->hangcheck.action = HANGCHECK_IDLE; |
3259 | ||
9107e9d2 CW |
3260 | if (waitqueue_active(&ring->irq_queue)) { |
3261 | /* Issue a wake-up to catch stuck h/w. */ | |
094f9a54 | 3262 | if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) { |
f4adcd24 DV |
3263 | if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring))) |
3264 | DRM_ERROR("Hangcheck timer elapsed... %s idle\n", | |
3265 | ring->name); | |
3266 | else | |
3267 | DRM_INFO("Fake missed irq on %s\n", | |
3268 | ring->name); | |
094f9a54 CW |
3269 | wake_up_all(&ring->irq_queue); |
3270 | } | |
3271 | /* Safeguard against driver failure */ | |
3272 | ring->hangcheck.score += BUSY; | |
9107e9d2 CW |
3273 | } else |
3274 | busy = false; | |
05407ff8 | 3275 | } else { |
6274f212 CW |
3276 | /* We always increment the hangcheck score |
3277 | * if the ring is busy and still processing | |
3278 | * the same request, so that no single request | |
3279 | * can run indefinitely (such as a chain of | |
3280 | * batches). The only time we do not increment | |
3281 | * the hangcheck score on this ring, if this | |
3282 | * ring is in a legitimate wait for another | |
3283 | * ring. In that case the waiting ring is a | |
3284 | * victim and we want to be sure we catch the | |
3285 | * right culprit. Then every time we do kick | |
3286 | * the ring, add a small increment to the | |
3287 | * score so that we can catch a batch that is | |
3288 | * being repeatedly kicked and so responsible | |
3289 | * for stalling the machine. | |
3290 | */ | |
ad8beaea MK |
3291 | ring->hangcheck.action = ring_stuck(ring, |
3292 | acthd); | |
3293 | ||
3294 | switch (ring->hangcheck.action) { | |
da661464 | 3295 | case HANGCHECK_IDLE: |
f2f4d82f | 3296 | case HANGCHECK_WAIT: |
f2f4d82f | 3297 | case HANGCHECK_ACTIVE: |
f260fe7b MK |
3298 | break; |
3299 | case HANGCHECK_ACTIVE_LOOP: | |
ea04cb31 | 3300 | ring->hangcheck.score += BUSY; |
6274f212 | 3301 | break; |
f2f4d82f | 3302 | case HANGCHECK_KICK: |
ea04cb31 | 3303 | ring->hangcheck.score += KICK; |
6274f212 | 3304 | break; |
f2f4d82f | 3305 | case HANGCHECK_HUNG: |
ea04cb31 | 3306 | ring->hangcheck.score += HUNG; |
6274f212 CW |
3307 | stuck[i] = true; |
3308 | break; | |
3309 | } | |
05407ff8 | 3310 | } |
9107e9d2 | 3311 | } else { |
da661464 MK |
3312 | ring->hangcheck.action = HANGCHECK_ACTIVE; |
3313 | ||
9107e9d2 CW |
3314 | /* Gradually reduce the count so that we catch DoS |
3315 | * attempts across multiple batches. | |
3316 | */ | |
3317 | if (ring->hangcheck.score > 0) | |
3318 | ring->hangcheck.score--; | |
f260fe7b MK |
3319 | |
3320 | ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0; | |
d1e61e7f CW |
3321 | } |
3322 | ||
05407ff8 MK |
3323 | ring->hangcheck.seqno = seqno; |
3324 | ring->hangcheck.acthd = acthd; | |
9107e9d2 | 3325 | busy_count += busy; |
893eead0 | 3326 | } |
b9201c14 | 3327 | |
92cab734 | 3328 | for_each_ring(ring, dev_priv, i) { |
b6b0fac0 | 3329 | if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) { |
b8d88d1d DV |
3330 | DRM_INFO("%s on %s\n", |
3331 | stuck[i] ? "stuck" : "no progress", | |
3332 | ring->name); | |
a43adf07 | 3333 | rings_hung++; |
92cab734 MK |
3334 | } |
3335 | } | |
3336 | ||
05407ff8 | 3337 | if (rings_hung) |
58174462 | 3338 | return i915_handle_error(dev, true, "Ring hung"); |
f65d9421 | 3339 | |
05407ff8 MK |
3340 | if (busy_count) |
3341 | /* Reset timer case chip hangs without another request | |
3342 | * being added */ | |
10cd45b6 MK |
3343 | i915_queue_hangcheck(dev); |
3344 | } | |
3345 | ||
3346 | void i915_queue_hangcheck(struct drm_device *dev) | |
3347 | { | |
3348 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d330a953 | 3349 | if (!i915.enable_hangcheck) |
10cd45b6 MK |
3350 | return; |
3351 | ||
3352 | mod_timer(&dev_priv->gpu_error.hangcheck_timer, | |
3353 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); | |
f65d9421 BG |
3354 | } |
3355 | ||
1c69eb42 | 3356 | static void ibx_irq_reset(struct drm_device *dev) |
91738a95 PZ |
3357 | { |
3358 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3359 | ||
3360 | if (HAS_PCH_NOP(dev)) | |
3361 | return; | |
3362 | ||
f86f3fb0 | 3363 | GEN5_IRQ_RESET(SDE); |
105b122e PZ |
3364 | |
3365 | if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) | |
3366 | I915_WRITE(SERR_INT, 0xffffffff); | |
622364b6 | 3367 | } |
105b122e | 3368 | |
622364b6 PZ |
3369 | /* |
3370 | * SDEIER is also touched by the interrupt handler to work around missed PCH | |
3371 | * interrupts. Hence we can't update it after the interrupt handler is enabled - | |
3372 | * instead we unconditionally enable all PCH interrupt sources here, but then | |
3373 | * only unmask them as needed with SDEIMR. | |
3374 | * | |
3375 | * This function needs to be called before interrupts are enabled. | |
3376 | */ | |
3377 | static void ibx_irq_pre_postinstall(struct drm_device *dev) | |
3378 | { | |
3379 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3380 | ||
3381 | if (HAS_PCH_NOP(dev)) | |
3382 | return; | |
3383 | ||
3384 | WARN_ON(I915_READ(SDEIER) != 0); | |
91738a95 PZ |
3385 | I915_WRITE(SDEIER, 0xffffffff); |
3386 | POSTING_READ(SDEIER); | |
3387 | } | |
3388 | ||
7c4d664e | 3389 | static void gen5_gt_irq_reset(struct drm_device *dev) |
d18ea1b5 DV |
3390 | { |
3391 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3392 | ||
f86f3fb0 | 3393 | GEN5_IRQ_RESET(GT); |
a9d356a6 | 3394 | if (INTEL_INFO(dev)->gen >= 6) |
f86f3fb0 | 3395 | GEN5_IRQ_RESET(GEN6_PM); |
d18ea1b5 DV |
3396 | } |
3397 | ||
1da177e4 LT |
3398 | /* drm_dma.h hooks |
3399 | */ | |
be30b29f | 3400 | static void ironlake_irq_reset(struct drm_device *dev) |
036a4a7d | 3401 | { |
2d1013dd | 3402 | struct drm_i915_private *dev_priv = dev->dev_private; |
036a4a7d | 3403 | |
0c841212 | 3404 | I915_WRITE(HWSTAM, 0xffffffff); |
bdfcdb63 | 3405 | |
f86f3fb0 | 3406 | GEN5_IRQ_RESET(DE); |
c6d954c1 PZ |
3407 | if (IS_GEN7(dev)) |
3408 | I915_WRITE(GEN7_ERR_INT, 0xffffffff); | |
036a4a7d | 3409 | |
7c4d664e | 3410 | gen5_gt_irq_reset(dev); |
c650156a | 3411 | |
1c69eb42 | 3412 | ibx_irq_reset(dev); |
7d99163d | 3413 | } |
c650156a | 3414 | |
7e231dbe JB |
3415 | static void valleyview_irq_preinstall(struct drm_device *dev) |
3416 | { | |
2d1013dd | 3417 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
3418 | int pipe; |
3419 | ||
7e231dbe JB |
3420 | /* VLV magic */ |
3421 | I915_WRITE(VLV_IMR, 0); | |
3422 | I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); | |
3423 | I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); | |
3424 | I915_WRITE(RING_IMR(BLT_RING_BASE), 0); | |
3425 | ||
7e231dbe JB |
3426 | /* and GT */ |
3427 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
3428 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
d18ea1b5 | 3429 | |
7c4d664e | 3430 | gen5_gt_irq_reset(dev); |
7e231dbe JB |
3431 | |
3432 | I915_WRITE(DPINVGTT, 0xff); | |
3433 | ||
3434 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3435 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
055e393f | 3436 | for_each_pipe(dev_priv, pipe) |
7e231dbe JB |
3437 | I915_WRITE(PIPESTAT(pipe), 0xffff); |
3438 | I915_WRITE(VLV_IIR, 0xffffffff); | |
3439 | I915_WRITE(VLV_IMR, 0xffffffff); | |
3440 | I915_WRITE(VLV_IER, 0x0); | |
3441 | POSTING_READ(VLV_IER); | |
3442 | } | |
3443 | ||
d6e3cca3 DV |
3444 | static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv) |
3445 | { | |
3446 | GEN8_IRQ_RESET_NDX(GT, 0); | |
3447 | GEN8_IRQ_RESET_NDX(GT, 1); | |
3448 | GEN8_IRQ_RESET_NDX(GT, 2); | |
3449 | GEN8_IRQ_RESET_NDX(GT, 3); | |
3450 | } | |
3451 | ||
823f6b38 | 3452 | static void gen8_irq_reset(struct drm_device *dev) |
abd58f01 BW |
3453 | { |
3454 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3455 | int pipe; | |
3456 | ||
abd58f01 BW |
3457 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
3458 | POSTING_READ(GEN8_MASTER_IRQ); | |
3459 | ||
d6e3cca3 | 3460 | gen8_gt_irq_reset(dev_priv); |
abd58f01 | 3461 | |
055e393f | 3462 | for_each_pipe(dev_priv, pipe) |
f458ebbc DV |
3463 | if (intel_display_power_is_enabled(dev_priv, |
3464 | POWER_DOMAIN_PIPE(pipe))) | |
813bde43 | 3465 | GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); |
abd58f01 | 3466 | |
f86f3fb0 PZ |
3467 | GEN5_IRQ_RESET(GEN8_DE_PORT_); |
3468 | GEN5_IRQ_RESET(GEN8_DE_MISC_); | |
3469 | GEN5_IRQ_RESET(GEN8_PCU_); | |
abd58f01 | 3470 | |
1c69eb42 | 3471 | ibx_irq_reset(dev); |
abd58f01 | 3472 | } |
09f2344d | 3473 | |
d49bdb0e PZ |
3474 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv) |
3475 | { | |
1180e206 | 3476 | uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; |
d49bdb0e | 3477 | |
13321786 | 3478 | spin_lock_irq(&dev_priv->irq_lock); |
d49bdb0e | 3479 | GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B], |
1180e206 | 3480 | ~dev_priv->de_irq_mask[PIPE_B] | extra_ier); |
d49bdb0e | 3481 | GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C], |
1180e206 | 3482 | ~dev_priv->de_irq_mask[PIPE_C] | extra_ier); |
13321786 | 3483 | spin_unlock_irq(&dev_priv->irq_lock); |
d49bdb0e PZ |
3484 | } |
3485 | ||
43f328d7 VS |
3486 | static void cherryview_irq_preinstall(struct drm_device *dev) |
3487 | { | |
3488 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3489 | int pipe; | |
3490 | ||
3491 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3492 | POSTING_READ(GEN8_MASTER_IRQ); | |
3493 | ||
d6e3cca3 | 3494 | gen8_gt_irq_reset(dev_priv); |
43f328d7 VS |
3495 | |
3496 | GEN5_IRQ_RESET(GEN8_PCU_); | |
3497 | ||
3498 | POSTING_READ(GEN8_PCU_IIR); | |
3499 | ||
3500 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV); | |
3501 | ||
3502 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3503 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3504 | ||
055e393f | 3505 | for_each_pipe(dev_priv, pipe) |
43f328d7 VS |
3506 | I915_WRITE(PIPESTAT(pipe), 0xffff); |
3507 | ||
3508 | I915_WRITE(VLV_IMR, 0xffffffff); | |
3509 | I915_WRITE(VLV_IER, 0x0); | |
3510 | I915_WRITE(VLV_IIR, 0xffffffff); | |
3511 | POSTING_READ(VLV_IIR); | |
3512 | } | |
3513 | ||
82a28bcf | 3514 | static void ibx_hpd_irq_setup(struct drm_device *dev) |
7fe0b973 | 3515 | { |
2d1013dd | 3516 | struct drm_i915_private *dev_priv = dev->dev_private; |
82a28bcf | 3517 | struct intel_encoder *intel_encoder; |
fee884ed | 3518 | u32 hotplug_irqs, hotplug, enabled_irqs = 0; |
82a28bcf DV |
3519 | |
3520 | if (HAS_PCH_IBX(dev)) { | |
fee884ed | 3521 | hotplug_irqs = SDE_HOTPLUG_MASK; |
b2784e15 | 3522 | for_each_intel_encoder(dev, intel_encoder) |
cd569aed | 3523 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
fee884ed | 3524 | enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin]; |
82a28bcf | 3525 | } else { |
fee884ed | 3526 | hotplug_irqs = SDE_HOTPLUG_MASK_CPT; |
b2784e15 | 3527 | for_each_intel_encoder(dev, intel_encoder) |
cd569aed | 3528 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
fee884ed | 3529 | enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin]; |
82a28bcf | 3530 | } |
7fe0b973 | 3531 | |
fee884ed | 3532 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); |
82a28bcf DV |
3533 | |
3534 | /* | |
3535 | * Enable digital hotplug on the PCH, and configure the DP short pulse | |
3536 | * duration to 2ms (which is the minimum in the Display Port spec) | |
3537 | * | |
3538 | * This register is the same on all known PCH chips. | |
3539 | */ | |
7fe0b973 KP |
3540 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
3541 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); | |
3542 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; | |
3543 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; | |
3544 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; | |
3545 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); | |
3546 | } | |
3547 | ||
d46da437 PZ |
3548 | static void ibx_irq_postinstall(struct drm_device *dev) |
3549 | { | |
2d1013dd | 3550 | struct drm_i915_private *dev_priv = dev->dev_private; |
82a28bcf | 3551 | u32 mask; |
e5868a31 | 3552 | |
692a04cf DV |
3553 | if (HAS_PCH_NOP(dev)) |
3554 | return; | |
3555 | ||
105b122e | 3556 | if (HAS_PCH_IBX(dev)) |
5c673b60 | 3557 | mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; |
105b122e | 3558 | else |
5c673b60 | 3559 | mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; |
8664281b | 3560 | |
337ba017 | 3561 | GEN5_ASSERT_IIR_IS_ZERO(SDEIIR); |
d46da437 | 3562 | I915_WRITE(SDEIMR, ~mask); |
d46da437 PZ |
3563 | } |
3564 | ||
0a9a8c91 DV |
3565 | static void gen5_gt_irq_postinstall(struct drm_device *dev) |
3566 | { | |
3567 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3568 | u32 pm_irqs, gt_irqs; | |
3569 | ||
3570 | pm_irqs = gt_irqs = 0; | |
3571 | ||
3572 | dev_priv->gt_irq_mask = ~0; | |
040d2baa | 3573 | if (HAS_L3_DPF(dev)) { |
0a9a8c91 | 3574 | /* L3 parity interrupt is always unmasked. */ |
35a85ac6 BW |
3575 | dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev); |
3576 | gt_irqs |= GT_PARITY_ERROR(dev); | |
0a9a8c91 DV |
3577 | } |
3578 | ||
3579 | gt_irqs |= GT_RENDER_USER_INTERRUPT; | |
3580 | if (IS_GEN5(dev)) { | |
3581 | gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | | |
3582 | ILK_BSD_USER_INTERRUPT; | |
3583 | } else { | |
3584 | gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; | |
3585 | } | |
3586 | ||
35079899 | 3587 | GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); |
0a9a8c91 DV |
3588 | |
3589 | if (INTEL_INFO(dev)->gen >= 6) { | |
a6706b45 | 3590 | pm_irqs |= dev_priv->pm_rps_events; |
0a9a8c91 DV |
3591 | |
3592 | if (HAS_VEBOX(dev)) | |
3593 | pm_irqs |= PM_VEBOX_USER_INTERRUPT; | |
3594 | ||
605cd25b | 3595 | dev_priv->pm_irq_mask = 0xffffffff; |
35079899 | 3596 | GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs); |
0a9a8c91 DV |
3597 | } |
3598 | } | |
3599 | ||
f71d4af4 | 3600 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d | 3601 | { |
2d1013dd | 3602 | struct drm_i915_private *dev_priv = dev->dev_private; |
8e76f8dc PZ |
3603 | u32 display_mask, extra_mask; |
3604 | ||
3605 | if (INTEL_INFO(dev)->gen >= 7) { | |
3606 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | | |
3607 | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | | |
3608 | DE_PLANEB_FLIP_DONE_IVB | | |
5c673b60 | 3609 | DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB); |
8e76f8dc | 3610 | extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | |
5c673b60 | 3611 | DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB); |
8e76f8dc PZ |
3612 | } else { |
3613 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | | |
3614 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | | |
5b3a856b | 3615 | DE_AUX_CHANNEL_A | |
5b3a856b DV |
3616 | DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE | |
3617 | DE_POISON); | |
5c673b60 DV |
3618 | extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT | |
3619 | DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN; | |
8e76f8dc | 3620 | } |
036a4a7d | 3621 | |
1ec14ad3 | 3622 | dev_priv->irq_mask = ~display_mask; |
036a4a7d | 3623 | |
0c841212 PZ |
3624 | I915_WRITE(HWSTAM, 0xeffe); |
3625 | ||
622364b6 PZ |
3626 | ibx_irq_pre_postinstall(dev); |
3627 | ||
35079899 | 3628 | GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); |
036a4a7d | 3629 | |
0a9a8c91 | 3630 | gen5_gt_irq_postinstall(dev); |
036a4a7d | 3631 | |
d46da437 | 3632 | ibx_irq_postinstall(dev); |
7fe0b973 | 3633 | |
f97108d1 | 3634 | if (IS_IRONLAKE_M(dev)) { |
6005ce42 DV |
3635 | /* Enable PCU event interrupts |
3636 | * | |
3637 | * spinlocking not required here for correctness since interrupt | |
4bc9d430 DV |
3638 | * setup is guaranteed to run in single-threaded context. But we |
3639 | * need it to make the assert_spin_locked happy. */ | |
d6207435 | 3640 | spin_lock_irq(&dev_priv->irq_lock); |
f97108d1 | 3641 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); |
d6207435 | 3642 | spin_unlock_irq(&dev_priv->irq_lock); |
f97108d1 JB |
3643 | } |
3644 | ||
036a4a7d ZW |
3645 | return 0; |
3646 | } | |
3647 | ||
f8b79e58 ID |
3648 | static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv) |
3649 | { | |
3650 | u32 pipestat_mask; | |
3651 | u32 iir_mask; | |
3652 | ||
3653 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | | |
3654 | PIPE_FIFO_UNDERRUN_STATUS; | |
3655 | ||
3656 | I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask); | |
3657 | I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask); | |
3658 | POSTING_READ(PIPESTAT(PIPE_A)); | |
3659 | ||
3660 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3661 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3662 | ||
3663 | i915_enable_pipestat(dev_priv, PIPE_A, pipestat_mask | | |
3664 | PIPE_GMBUS_INTERRUPT_STATUS); | |
3665 | i915_enable_pipestat(dev_priv, PIPE_B, pipestat_mask); | |
3666 | ||
3667 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3668 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3669 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
3670 | dev_priv->irq_mask &= ~iir_mask; | |
3671 | ||
3672 | I915_WRITE(VLV_IIR, iir_mask); | |
3673 | I915_WRITE(VLV_IIR, iir_mask); | |
3674 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); | |
3675 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); | |
3676 | POSTING_READ(VLV_IER); | |
3677 | } | |
3678 | ||
3679 | static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv) | |
3680 | { | |
3681 | u32 pipestat_mask; | |
3682 | u32 iir_mask; | |
3683 | ||
3684 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3685 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
6c7fba04 | 3686 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; |
f8b79e58 ID |
3687 | |
3688 | dev_priv->irq_mask |= iir_mask; | |
3689 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); | |
3690 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); | |
3691 | I915_WRITE(VLV_IIR, iir_mask); | |
3692 | I915_WRITE(VLV_IIR, iir_mask); | |
3693 | POSTING_READ(VLV_IIR); | |
3694 | ||
3695 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3696 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3697 | ||
3698 | i915_disable_pipestat(dev_priv, PIPE_A, pipestat_mask | | |
3699 | PIPE_GMBUS_INTERRUPT_STATUS); | |
3700 | i915_disable_pipestat(dev_priv, PIPE_B, pipestat_mask); | |
3701 | ||
3702 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | | |
3703 | PIPE_FIFO_UNDERRUN_STATUS; | |
3704 | I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask); | |
3705 | I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask); | |
3706 | POSTING_READ(PIPESTAT(PIPE_A)); | |
3707 | } | |
3708 | ||
3709 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) | |
3710 | { | |
3711 | assert_spin_locked(&dev_priv->irq_lock); | |
3712 | ||
3713 | if (dev_priv->display_irqs_enabled) | |
3714 | return; | |
3715 | ||
3716 | dev_priv->display_irqs_enabled = true; | |
3717 | ||
950eabaf | 3718 | if (intel_irqs_enabled(dev_priv)) |
f8b79e58 ID |
3719 | valleyview_display_irqs_install(dev_priv); |
3720 | } | |
3721 | ||
3722 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) | |
3723 | { | |
3724 | assert_spin_locked(&dev_priv->irq_lock); | |
3725 | ||
3726 | if (!dev_priv->display_irqs_enabled) | |
3727 | return; | |
3728 | ||
3729 | dev_priv->display_irqs_enabled = false; | |
3730 | ||
950eabaf | 3731 | if (intel_irqs_enabled(dev_priv)) |
f8b79e58 ID |
3732 | valleyview_display_irqs_uninstall(dev_priv); |
3733 | } | |
3734 | ||
7e231dbe JB |
3735 | static int valleyview_irq_postinstall(struct drm_device *dev) |
3736 | { | |
2d1013dd | 3737 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 3738 | |
f8b79e58 | 3739 | dev_priv->irq_mask = ~0; |
7e231dbe | 3740 | |
20afbda2 DV |
3741 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3742 | POSTING_READ(PORT_HOTPLUG_EN); | |
3743 | ||
7e231dbe | 3744 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
f8b79e58 | 3745 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); |
7e231dbe | 3746 | I915_WRITE(VLV_IIR, 0xffffffff); |
7e231dbe JB |
3747 | POSTING_READ(VLV_IER); |
3748 | ||
b79480ba DV |
3749 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3750 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3751 | spin_lock_irq(&dev_priv->irq_lock); |
f8b79e58 ID |
3752 | if (dev_priv->display_irqs_enabled) |
3753 | valleyview_display_irqs_install(dev_priv); | |
d6207435 | 3754 | spin_unlock_irq(&dev_priv->irq_lock); |
31acc7f5 | 3755 | |
7e231dbe JB |
3756 | I915_WRITE(VLV_IIR, 0xffffffff); |
3757 | I915_WRITE(VLV_IIR, 0xffffffff); | |
3758 | ||
0a9a8c91 | 3759 | gen5_gt_irq_postinstall(dev); |
7e231dbe JB |
3760 | |
3761 | /* ack & enable invalid PTE error interrupts */ | |
3762 | #if 0 /* FIXME: add support to irq handler for checking these bits */ | |
3763 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); | |
3764 | I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); | |
3765 | #endif | |
3766 | ||
3767 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); | |
20afbda2 DV |
3768 | |
3769 | return 0; | |
3770 | } | |
3771 | ||
abd58f01 BW |
3772 | static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) |
3773 | { | |
abd58f01 BW |
3774 | /* These are interrupts we'll toggle with the ring mask register */ |
3775 | uint32_t gt_interrupts[] = { | |
3776 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | | |
73d477f6 | 3777 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT | |
abd58f01 | 3778 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT | |
73d477f6 OM |
3779 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT | |
3780 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT, | |
abd58f01 | 3781 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
73d477f6 OM |
3782 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
3783 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT | | |
3784 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT, | |
abd58f01 | 3785 | 0, |
73d477f6 OM |
3786 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
3787 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
abd58f01 BW |
3788 | }; |
3789 | ||
0961021a | 3790 | dev_priv->pm_irq_mask = 0xffffffff; |
9a2d2d87 D |
3791 | GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]); |
3792 | GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]); | |
3793 | GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, dev_priv->pm_rps_events); | |
3794 | GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]); | |
abd58f01 BW |
3795 | } |
3796 | ||
3797 | static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) | |
3798 | { | |
770de83d DL |
3799 | uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE; |
3800 | uint32_t de_pipe_enables; | |
abd58f01 | 3801 | int pipe; |
770de83d DL |
3802 | |
3803 | if (IS_GEN9(dev_priv)) | |
3804 | de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE | | |
3805 | GEN9_DE_PIPE_IRQ_FAULT_ERRORS; | |
3806 | else | |
3807 | de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE | | |
3808 | GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
3809 | ||
3810 | de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | | |
3811 | GEN8_PIPE_FIFO_UNDERRUN; | |
3812 | ||
13b3a0a7 DV |
3813 | dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; |
3814 | dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; | |
3815 | dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; | |
abd58f01 | 3816 | |
055e393f | 3817 | for_each_pipe(dev_priv, pipe) |
f458ebbc | 3818 | if (intel_display_power_is_enabled(dev_priv, |
813bde43 PZ |
3819 | POWER_DOMAIN_PIPE(pipe))) |
3820 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, | |
3821 | dev_priv->de_irq_mask[pipe], | |
3822 | de_pipe_enables); | |
abd58f01 | 3823 | |
35079899 | 3824 | GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A); |
abd58f01 BW |
3825 | } |
3826 | ||
3827 | static int gen8_irq_postinstall(struct drm_device *dev) | |
3828 | { | |
3829 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3830 | ||
622364b6 PZ |
3831 | ibx_irq_pre_postinstall(dev); |
3832 | ||
abd58f01 BW |
3833 | gen8_gt_irq_postinstall(dev_priv); |
3834 | gen8_de_irq_postinstall(dev_priv); | |
3835 | ||
3836 | ibx_irq_postinstall(dev); | |
3837 | ||
3838 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); | |
3839 | POSTING_READ(GEN8_MASTER_IRQ); | |
3840 | ||
3841 | return 0; | |
3842 | } | |
3843 | ||
43f328d7 VS |
3844 | static int cherryview_irq_postinstall(struct drm_device *dev) |
3845 | { | |
3846 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3847 | u32 enable_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3848 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
43f328d7 | 3849 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
3278f67f VS |
3850 | I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; |
3851 | u32 pipestat_enable = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3852 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
43f328d7 VS |
3853 | int pipe; |
3854 | ||
3855 | /* | |
3856 | * Leave vblank interrupts masked initially. enable/disable will | |
3857 | * toggle them based on usage. | |
3858 | */ | |
3278f67f | 3859 | dev_priv->irq_mask = ~enable_mask; |
43f328d7 | 3860 | |
055e393f | 3861 | for_each_pipe(dev_priv, pipe) |
43f328d7 VS |
3862 | I915_WRITE(PIPESTAT(pipe), 0xffff); |
3863 | ||
d6207435 | 3864 | spin_lock_irq(&dev_priv->irq_lock); |
3278f67f | 3865 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
055e393f | 3866 | for_each_pipe(dev_priv, pipe) |
43f328d7 | 3867 | i915_enable_pipestat(dev_priv, pipe, pipestat_enable); |
d6207435 | 3868 | spin_unlock_irq(&dev_priv->irq_lock); |
43f328d7 VS |
3869 | |
3870 | I915_WRITE(VLV_IIR, 0xffffffff); | |
3871 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); | |
3872 | I915_WRITE(VLV_IER, enable_mask); | |
3873 | ||
3874 | gen8_gt_irq_postinstall(dev_priv); | |
3875 | ||
3876 | I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE); | |
3877 | POSTING_READ(GEN8_MASTER_IRQ); | |
3878 | ||
3879 | return 0; | |
3880 | } | |
3881 | ||
abd58f01 BW |
3882 | static void gen8_irq_uninstall(struct drm_device *dev) |
3883 | { | |
3884 | struct drm_i915_private *dev_priv = dev->dev_private; | |
abd58f01 BW |
3885 | |
3886 | if (!dev_priv) | |
3887 | return; | |
3888 | ||
823f6b38 | 3889 | gen8_irq_reset(dev); |
abd58f01 BW |
3890 | } |
3891 | ||
7e231dbe JB |
3892 | static void valleyview_irq_uninstall(struct drm_device *dev) |
3893 | { | |
2d1013dd | 3894 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
3895 | int pipe; |
3896 | ||
3897 | if (!dev_priv) | |
3898 | return; | |
3899 | ||
843d0e7d ID |
3900 | I915_WRITE(VLV_MASTER_IER, 0); |
3901 | ||
055e393f | 3902 | for_each_pipe(dev_priv, pipe) |
7e231dbe JB |
3903 | I915_WRITE(PIPESTAT(pipe), 0xffff); |
3904 | ||
3905 | I915_WRITE(HWSTAM, 0xffffffff); | |
3906 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3907 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
f8b79e58 | 3908 | |
d6207435 DV |
3909 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3910 | * just to make the assert_spin_locked check happy. */ | |
3911 | spin_lock_irq(&dev_priv->irq_lock); | |
f8b79e58 ID |
3912 | if (dev_priv->display_irqs_enabled) |
3913 | valleyview_display_irqs_uninstall(dev_priv); | |
d6207435 | 3914 | spin_unlock_irq(&dev_priv->irq_lock); |
f8b79e58 ID |
3915 | |
3916 | dev_priv->irq_mask = 0; | |
3917 | ||
7e231dbe JB |
3918 | I915_WRITE(VLV_IIR, 0xffffffff); |
3919 | I915_WRITE(VLV_IMR, 0xffffffff); | |
3920 | I915_WRITE(VLV_IER, 0x0); | |
3921 | POSTING_READ(VLV_IER); | |
3922 | } | |
3923 | ||
43f328d7 VS |
3924 | static void cherryview_irq_uninstall(struct drm_device *dev) |
3925 | { | |
3926 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3927 | int pipe; | |
3928 | ||
3929 | if (!dev_priv) | |
3930 | return; | |
3931 | ||
3932 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3933 | POSTING_READ(GEN8_MASTER_IRQ); | |
3934 | ||
3935 | #define GEN8_IRQ_FINI_NDX(type, which) \ | |
3936 | do { \ | |
3937 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ | |
3938 | I915_WRITE(GEN8_##type##_IER(which), 0); \ | |
3939 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
3940 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
3941 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
3942 | } while (0) | |
3943 | ||
3944 | #define GEN8_IRQ_FINI(type) \ | |
3945 | do { \ | |
3946 | I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \ | |
3947 | I915_WRITE(GEN8_##type##_IER, 0); \ | |
3948 | I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ | |
3949 | POSTING_READ(GEN8_##type##_IIR); \ | |
3950 | I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ | |
3951 | } while (0) | |
3952 | ||
3953 | GEN8_IRQ_FINI_NDX(GT, 0); | |
3954 | GEN8_IRQ_FINI_NDX(GT, 1); | |
3955 | GEN8_IRQ_FINI_NDX(GT, 2); | |
3956 | GEN8_IRQ_FINI_NDX(GT, 3); | |
3957 | ||
3958 | GEN8_IRQ_FINI(PCU); | |
3959 | ||
3960 | #undef GEN8_IRQ_FINI | |
3961 | #undef GEN8_IRQ_FINI_NDX | |
3962 | ||
3963 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3964 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3965 | ||
055e393f | 3966 | for_each_pipe(dev_priv, pipe) |
43f328d7 VS |
3967 | I915_WRITE(PIPESTAT(pipe), 0xffff); |
3968 | ||
3969 | I915_WRITE(VLV_IMR, 0xffffffff); | |
3970 | I915_WRITE(VLV_IER, 0x0); | |
3971 | I915_WRITE(VLV_IIR, 0xffffffff); | |
3972 | POSTING_READ(VLV_IIR); | |
3973 | } | |
3974 | ||
f71d4af4 | 3975 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d | 3976 | { |
2d1013dd | 3977 | struct drm_i915_private *dev_priv = dev->dev_private; |
4697995b JB |
3978 | |
3979 | if (!dev_priv) | |
3980 | return; | |
3981 | ||
be30b29f | 3982 | ironlake_irq_reset(dev); |
036a4a7d ZW |
3983 | } |
3984 | ||
a266c7d5 | 3985 | static void i8xx_irq_preinstall(struct drm_device * dev) |
1da177e4 | 3986 | { |
2d1013dd | 3987 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 3988 | int pipe; |
91e3738e | 3989 | |
055e393f | 3990 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 | 3991 | I915_WRITE(PIPESTAT(pipe), 0); |
a266c7d5 CW |
3992 | I915_WRITE16(IMR, 0xffff); |
3993 | I915_WRITE16(IER, 0x0); | |
3994 | POSTING_READ16(IER); | |
c2798b19 CW |
3995 | } |
3996 | ||
3997 | static int i8xx_irq_postinstall(struct drm_device *dev) | |
3998 | { | |
2d1013dd | 3999 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 | 4000 | |
c2798b19 CW |
4001 | I915_WRITE16(EMR, |
4002 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); | |
4003 | ||
4004 | /* Unmask the interrupts that we always want on. */ | |
4005 | dev_priv->irq_mask = | |
4006 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
4007 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
4008 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4009 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
4010 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
4011 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
4012 | ||
4013 | I915_WRITE16(IER, | |
4014 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
4015 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
4016 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
4017 | I915_USER_INTERRUPT); | |
4018 | POSTING_READ16(IER); | |
4019 | ||
379ef82d DV |
4020 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
4021 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 4022 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
4023 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
4024 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 4025 | spin_unlock_irq(&dev_priv->irq_lock); |
379ef82d | 4026 | |
c2798b19 CW |
4027 | return 0; |
4028 | } | |
4029 | ||
90a72f87 VS |
4030 | /* |
4031 | * Returns true when a page flip has completed. | |
4032 | */ | |
4033 | static bool i8xx_handle_vblank(struct drm_device *dev, | |
1f1c2e24 | 4034 | int plane, int pipe, u32 iir) |
90a72f87 | 4035 | { |
2d1013dd | 4036 | struct drm_i915_private *dev_priv = dev->dev_private; |
1f1c2e24 | 4037 | u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
90a72f87 | 4038 | |
8d7849db | 4039 | if (!intel_pipe_handle_vblank(dev, pipe)) |
90a72f87 VS |
4040 | return false; |
4041 | ||
4042 | if ((iir & flip_pending) == 0) | |
d6bbafa1 | 4043 | goto check_page_flip; |
90a72f87 | 4044 | |
1f1c2e24 | 4045 | intel_prepare_page_flip(dev, plane); |
90a72f87 VS |
4046 | |
4047 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
4048 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
4049 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
4050 | * the flip is completed (no longer pending). Since this doesn't raise | |
4051 | * an interrupt per se, we watch for the change at vblank. | |
4052 | */ | |
4053 | if (I915_READ16(ISR) & flip_pending) | |
d6bbafa1 | 4054 | goto check_page_flip; |
90a72f87 VS |
4055 | |
4056 | intel_finish_page_flip(dev, pipe); | |
90a72f87 | 4057 | return true; |
d6bbafa1 CW |
4058 | |
4059 | check_page_flip: | |
4060 | intel_check_page_flip(dev, pipe); | |
4061 | return false; | |
90a72f87 VS |
4062 | } |
4063 | ||
ff1f525e | 4064 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
c2798b19 | 4065 | { |
45a83f84 | 4066 | struct drm_device *dev = arg; |
2d1013dd | 4067 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
4068 | u16 iir, new_iir; |
4069 | u32 pipe_stats[2]; | |
c2798b19 CW |
4070 | int pipe; |
4071 | u16 flip_mask = | |
4072 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4073 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
4074 | ||
c2798b19 CW |
4075 | iir = I915_READ16(IIR); |
4076 | if (iir == 0) | |
4077 | return IRQ_NONE; | |
4078 | ||
4079 | while (iir & ~flip_mask) { | |
4080 | /* Can't rely on pipestat interrupt bit in iir as it might | |
4081 | * have been cleared after the pipestat interrupt was received. | |
4082 | * It doesn't set the bit in iir again, but it still produces | |
4083 | * interrupts (for non-MSI). | |
4084 | */ | |
222c7f51 | 4085 | spin_lock(&dev_priv->irq_lock); |
c2798b19 | 4086 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
58174462 MK |
4087 | i915_handle_error(dev, false, |
4088 | "Command parser error, iir 0x%08x", | |
4089 | iir); | |
c2798b19 | 4090 | |
055e393f | 4091 | for_each_pipe(dev_priv, pipe) { |
c2798b19 CW |
4092 | int reg = PIPESTAT(pipe); |
4093 | pipe_stats[pipe] = I915_READ(reg); | |
4094 | ||
4095 | /* | |
4096 | * Clear the PIPE*STAT regs before the IIR | |
4097 | */ | |
2d9d2b0b | 4098 | if (pipe_stats[pipe] & 0x8000ffff) |
c2798b19 | 4099 | I915_WRITE(reg, pipe_stats[pipe]); |
c2798b19 | 4100 | } |
222c7f51 | 4101 | spin_unlock(&dev_priv->irq_lock); |
c2798b19 CW |
4102 | |
4103 | I915_WRITE16(IIR, iir & ~flip_mask); | |
4104 | new_iir = I915_READ16(IIR); /* Flush posted writes */ | |
4105 | ||
d05c617e | 4106 | i915_update_dri1_breadcrumb(dev); |
c2798b19 CW |
4107 | |
4108 | if (iir & I915_USER_INTERRUPT) | |
4109 | notify_ring(dev, &dev_priv->ring[RCS]); | |
4110 | ||
055e393f | 4111 | for_each_pipe(dev_priv, pipe) { |
1f1c2e24 | 4112 | int plane = pipe; |
3a77c4c4 | 4113 | if (HAS_FBC(dev)) |
1f1c2e24 VS |
4114 | plane = !plane; |
4115 | ||
4356d586 | 4116 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
1f1c2e24 VS |
4117 | i8xx_handle_vblank(dev, plane, pipe, iir)) |
4118 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
c2798b19 | 4119 | |
4356d586 | 4120 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
277de95e | 4121 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b VS |
4122 | |
4123 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && | |
4124 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
fc2c807b | 4125 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); |
4356d586 | 4126 | } |
c2798b19 CW |
4127 | |
4128 | iir = new_iir; | |
4129 | } | |
4130 | ||
4131 | return IRQ_HANDLED; | |
4132 | } | |
4133 | ||
4134 | static void i8xx_irq_uninstall(struct drm_device * dev) | |
4135 | { | |
2d1013dd | 4136 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
4137 | int pipe; |
4138 | ||
055e393f | 4139 | for_each_pipe(dev_priv, pipe) { |
c2798b19 CW |
4140 | /* Clear enable bits; then clear status bits */ |
4141 | I915_WRITE(PIPESTAT(pipe), 0); | |
4142 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); | |
4143 | } | |
4144 | I915_WRITE16(IMR, 0xffff); | |
4145 | I915_WRITE16(IER, 0x0); | |
4146 | I915_WRITE16(IIR, I915_READ16(IIR)); | |
4147 | } | |
4148 | ||
a266c7d5 CW |
4149 | static void i915_irq_preinstall(struct drm_device * dev) |
4150 | { | |
2d1013dd | 4151 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4152 | int pipe; |
4153 | ||
a266c7d5 CW |
4154 | if (I915_HAS_HOTPLUG(dev)) { |
4155 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
4156 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
4157 | } | |
4158 | ||
00d98ebd | 4159 | I915_WRITE16(HWSTAM, 0xeffe); |
055e393f | 4160 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4161 | I915_WRITE(PIPESTAT(pipe), 0); |
4162 | I915_WRITE(IMR, 0xffffffff); | |
4163 | I915_WRITE(IER, 0x0); | |
4164 | POSTING_READ(IER); | |
4165 | } | |
4166 | ||
4167 | static int i915_irq_postinstall(struct drm_device *dev) | |
4168 | { | |
2d1013dd | 4169 | struct drm_i915_private *dev_priv = dev->dev_private; |
38bde180 | 4170 | u32 enable_mask; |
a266c7d5 | 4171 | |
38bde180 CW |
4172 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
4173 | ||
4174 | /* Unmask the interrupts that we always want on. */ | |
4175 | dev_priv->irq_mask = | |
4176 | ~(I915_ASLE_INTERRUPT | | |
4177 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
4178 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
4179 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4180 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
4181 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
4182 | ||
4183 | enable_mask = | |
4184 | I915_ASLE_INTERRUPT | | |
4185 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
4186 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
4187 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
4188 | I915_USER_INTERRUPT; | |
4189 | ||
a266c7d5 | 4190 | if (I915_HAS_HOTPLUG(dev)) { |
20afbda2 DV |
4191 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
4192 | POSTING_READ(PORT_HOTPLUG_EN); | |
4193 | ||
a266c7d5 CW |
4194 | /* Enable in IER... */ |
4195 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
4196 | /* and unmask in IMR */ | |
4197 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; | |
4198 | } | |
4199 | ||
a266c7d5 CW |
4200 | I915_WRITE(IMR, dev_priv->irq_mask); |
4201 | I915_WRITE(IER, enable_mask); | |
4202 | POSTING_READ(IER); | |
4203 | ||
f49e38dd | 4204 | i915_enable_asle_pipestat(dev); |
20afbda2 | 4205 | |
379ef82d DV |
4206 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
4207 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 4208 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
4209 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
4210 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 4211 | spin_unlock_irq(&dev_priv->irq_lock); |
379ef82d | 4212 | |
20afbda2 DV |
4213 | return 0; |
4214 | } | |
4215 | ||
90a72f87 VS |
4216 | /* |
4217 | * Returns true when a page flip has completed. | |
4218 | */ | |
4219 | static bool i915_handle_vblank(struct drm_device *dev, | |
4220 | int plane, int pipe, u32 iir) | |
4221 | { | |
2d1013dd | 4222 | struct drm_i915_private *dev_priv = dev->dev_private; |
90a72f87 VS |
4223 | u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
4224 | ||
8d7849db | 4225 | if (!intel_pipe_handle_vblank(dev, pipe)) |
90a72f87 VS |
4226 | return false; |
4227 | ||
4228 | if ((iir & flip_pending) == 0) | |
d6bbafa1 | 4229 | goto check_page_flip; |
90a72f87 VS |
4230 | |
4231 | intel_prepare_page_flip(dev, plane); | |
4232 | ||
4233 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
4234 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
4235 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
4236 | * the flip is completed (no longer pending). Since this doesn't raise | |
4237 | * an interrupt per se, we watch for the change at vblank. | |
4238 | */ | |
4239 | if (I915_READ(ISR) & flip_pending) | |
d6bbafa1 | 4240 | goto check_page_flip; |
90a72f87 VS |
4241 | |
4242 | intel_finish_page_flip(dev, pipe); | |
90a72f87 | 4243 | return true; |
d6bbafa1 CW |
4244 | |
4245 | check_page_flip: | |
4246 | intel_check_page_flip(dev, pipe); | |
4247 | return false; | |
90a72f87 VS |
4248 | } |
4249 | ||
ff1f525e | 4250 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
a266c7d5 | 4251 | { |
45a83f84 | 4252 | struct drm_device *dev = arg; |
2d1013dd | 4253 | struct drm_i915_private *dev_priv = dev->dev_private; |
8291ee90 | 4254 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
38bde180 CW |
4255 | u32 flip_mask = |
4256 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4257 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
38bde180 | 4258 | int pipe, ret = IRQ_NONE; |
a266c7d5 | 4259 | |
a266c7d5 | 4260 | iir = I915_READ(IIR); |
38bde180 CW |
4261 | do { |
4262 | bool irq_received = (iir & ~flip_mask) != 0; | |
8291ee90 | 4263 | bool blc_event = false; |
a266c7d5 CW |
4264 | |
4265 | /* Can't rely on pipestat interrupt bit in iir as it might | |
4266 | * have been cleared after the pipestat interrupt was received. | |
4267 | * It doesn't set the bit in iir again, but it still produces | |
4268 | * interrupts (for non-MSI). | |
4269 | */ | |
222c7f51 | 4270 | spin_lock(&dev_priv->irq_lock); |
a266c7d5 | 4271 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
58174462 MK |
4272 | i915_handle_error(dev, false, |
4273 | "Command parser error, iir 0x%08x", | |
4274 | iir); | |
a266c7d5 | 4275 | |
055e393f | 4276 | for_each_pipe(dev_priv, pipe) { |
a266c7d5 CW |
4277 | int reg = PIPESTAT(pipe); |
4278 | pipe_stats[pipe] = I915_READ(reg); | |
4279 | ||
38bde180 | 4280 | /* Clear the PIPE*STAT regs before the IIR */ |
a266c7d5 | 4281 | if (pipe_stats[pipe] & 0x8000ffff) { |
a266c7d5 | 4282 | I915_WRITE(reg, pipe_stats[pipe]); |
38bde180 | 4283 | irq_received = true; |
a266c7d5 CW |
4284 | } |
4285 | } | |
222c7f51 | 4286 | spin_unlock(&dev_priv->irq_lock); |
a266c7d5 CW |
4287 | |
4288 | if (!irq_received) | |
4289 | break; | |
4290 | ||
a266c7d5 | 4291 | /* Consume port. Then clear IIR or we'll miss events */ |
16c6c56b VS |
4292 | if (I915_HAS_HOTPLUG(dev) && |
4293 | iir & I915_DISPLAY_PORT_INTERRUPT) | |
4294 | i9xx_hpd_irq_handler(dev); | |
a266c7d5 | 4295 | |
38bde180 | 4296 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
4297 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
4298 | ||
a266c7d5 CW |
4299 | if (iir & I915_USER_INTERRUPT) |
4300 | notify_ring(dev, &dev_priv->ring[RCS]); | |
a266c7d5 | 4301 | |
055e393f | 4302 | for_each_pipe(dev_priv, pipe) { |
38bde180 | 4303 | int plane = pipe; |
3a77c4c4 | 4304 | if (HAS_FBC(dev)) |
38bde180 | 4305 | plane = !plane; |
90a72f87 | 4306 | |
8291ee90 | 4307 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
4308 | i915_handle_vblank(dev, plane, pipe, iir)) |
4309 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
a266c7d5 CW |
4310 | |
4311 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
4312 | blc_event = true; | |
4356d586 DV |
4313 | |
4314 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 4315 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b VS |
4316 | |
4317 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && | |
4318 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
fc2c807b | 4319 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); |
a266c7d5 CW |
4320 | } |
4321 | ||
a266c7d5 CW |
4322 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
4323 | intel_opregion_asle_intr(dev); | |
4324 | ||
4325 | /* With MSI, interrupts are only generated when iir | |
4326 | * transitions from zero to nonzero. If another bit got | |
4327 | * set while we were handling the existing iir bits, then | |
4328 | * we would never get another interrupt. | |
4329 | * | |
4330 | * This is fine on non-MSI as well, as if we hit this path | |
4331 | * we avoid exiting the interrupt handler only to generate | |
4332 | * another one. | |
4333 | * | |
4334 | * Note that for MSI this could cause a stray interrupt report | |
4335 | * if an interrupt landed in the time between writing IIR and | |
4336 | * the posting read. This should be rare enough to never | |
4337 | * trigger the 99% of 100,000 interrupts test for disabling | |
4338 | * stray interrupts. | |
4339 | */ | |
38bde180 | 4340 | ret = IRQ_HANDLED; |
a266c7d5 | 4341 | iir = new_iir; |
38bde180 | 4342 | } while (iir & ~flip_mask); |
a266c7d5 | 4343 | |
d05c617e | 4344 | i915_update_dri1_breadcrumb(dev); |
8291ee90 | 4345 | |
a266c7d5 CW |
4346 | return ret; |
4347 | } | |
4348 | ||
4349 | static void i915_irq_uninstall(struct drm_device * dev) | |
4350 | { | |
2d1013dd | 4351 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4352 | int pipe; |
4353 | ||
a266c7d5 CW |
4354 | if (I915_HAS_HOTPLUG(dev)) { |
4355 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
4356 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
4357 | } | |
4358 | ||
00d98ebd | 4359 | I915_WRITE16(HWSTAM, 0xffff); |
055e393f | 4360 | for_each_pipe(dev_priv, pipe) { |
55b39755 | 4361 | /* Clear enable bits; then clear status bits */ |
a266c7d5 | 4362 | I915_WRITE(PIPESTAT(pipe), 0); |
55b39755 CW |
4363 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
4364 | } | |
a266c7d5 CW |
4365 | I915_WRITE(IMR, 0xffffffff); |
4366 | I915_WRITE(IER, 0x0); | |
4367 | ||
a266c7d5 CW |
4368 | I915_WRITE(IIR, I915_READ(IIR)); |
4369 | } | |
4370 | ||
4371 | static void i965_irq_preinstall(struct drm_device * dev) | |
4372 | { | |
2d1013dd | 4373 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4374 | int pipe; |
4375 | ||
adca4730 CW |
4376 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
4377 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
4378 | |
4379 | I915_WRITE(HWSTAM, 0xeffe); | |
055e393f | 4380 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4381 | I915_WRITE(PIPESTAT(pipe), 0); |
4382 | I915_WRITE(IMR, 0xffffffff); | |
4383 | I915_WRITE(IER, 0x0); | |
4384 | POSTING_READ(IER); | |
4385 | } | |
4386 | ||
4387 | static int i965_irq_postinstall(struct drm_device *dev) | |
4388 | { | |
2d1013dd | 4389 | struct drm_i915_private *dev_priv = dev->dev_private; |
bbba0a97 | 4390 | u32 enable_mask; |
a266c7d5 CW |
4391 | u32 error_mask; |
4392 | ||
a266c7d5 | 4393 | /* Unmask the interrupts that we always want on. */ |
bbba0a97 | 4394 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
adca4730 | 4395 | I915_DISPLAY_PORT_INTERRUPT | |
bbba0a97 CW |
4396 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
4397 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
4398 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4399 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
4400 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
4401 | ||
4402 | enable_mask = ~dev_priv->irq_mask; | |
21ad8330 VS |
4403 | enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
4404 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); | |
bbba0a97 CW |
4405 | enable_mask |= I915_USER_INTERRUPT; |
4406 | ||
4407 | if (IS_G4X(dev)) | |
4408 | enable_mask |= I915_BSD_USER_INTERRUPT; | |
a266c7d5 | 4409 | |
b79480ba DV |
4410 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
4411 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 4412 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
4413 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
4414 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
4415 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 4416 | spin_unlock_irq(&dev_priv->irq_lock); |
a266c7d5 | 4417 | |
a266c7d5 CW |
4418 | /* |
4419 | * Enable some error detection, note the instruction error mask | |
4420 | * bit is reserved, so we leave it masked. | |
4421 | */ | |
4422 | if (IS_G4X(dev)) { | |
4423 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
4424 | GM45_ERROR_MEM_PRIV | | |
4425 | GM45_ERROR_CP_PRIV | | |
4426 | I915_ERROR_MEMORY_REFRESH); | |
4427 | } else { | |
4428 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
4429 | I915_ERROR_MEMORY_REFRESH); | |
4430 | } | |
4431 | I915_WRITE(EMR, error_mask); | |
4432 | ||
4433 | I915_WRITE(IMR, dev_priv->irq_mask); | |
4434 | I915_WRITE(IER, enable_mask); | |
4435 | POSTING_READ(IER); | |
4436 | ||
20afbda2 DV |
4437 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
4438 | POSTING_READ(PORT_HOTPLUG_EN); | |
4439 | ||
f49e38dd | 4440 | i915_enable_asle_pipestat(dev); |
20afbda2 DV |
4441 | |
4442 | return 0; | |
4443 | } | |
4444 | ||
bac56d5b | 4445 | static void i915_hpd_irq_setup(struct drm_device *dev) |
20afbda2 | 4446 | { |
2d1013dd | 4447 | struct drm_i915_private *dev_priv = dev->dev_private; |
cd569aed | 4448 | struct intel_encoder *intel_encoder; |
20afbda2 DV |
4449 | u32 hotplug_en; |
4450 | ||
b5ea2d56 DV |
4451 | assert_spin_locked(&dev_priv->irq_lock); |
4452 | ||
bac56d5b EE |
4453 | if (I915_HAS_HOTPLUG(dev)) { |
4454 | hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
4455 | hotplug_en &= ~HOTPLUG_INT_EN_MASK; | |
4456 | /* Note HDMI and DP share hotplug bits */ | |
e5868a31 | 4457 | /* enable bits are the same for all generations */ |
b2784e15 | 4458 | for_each_intel_encoder(dev, intel_encoder) |
cd569aed EE |
4459 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
4460 | hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin]; | |
bac56d5b EE |
4461 | /* Programming the CRT detection parameters tends |
4462 | to generate a spurious hotplug event about three | |
4463 | seconds later. So just do it once. | |
4464 | */ | |
4465 | if (IS_G4X(dev)) | |
4466 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
85fc95ba | 4467 | hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK; |
bac56d5b | 4468 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
a266c7d5 | 4469 | |
bac56d5b EE |
4470 | /* Ignore TV since it's buggy */ |
4471 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
4472 | } | |
a266c7d5 CW |
4473 | } |
4474 | ||
ff1f525e | 4475 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
a266c7d5 | 4476 | { |
45a83f84 | 4477 | struct drm_device *dev = arg; |
2d1013dd | 4478 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4479 | u32 iir, new_iir; |
4480 | u32 pipe_stats[I915_MAX_PIPES]; | |
a266c7d5 | 4481 | int ret = IRQ_NONE, pipe; |
21ad8330 VS |
4482 | u32 flip_mask = |
4483 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4484 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
a266c7d5 | 4485 | |
a266c7d5 CW |
4486 | iir = I915_READ(IIR); |
4487 | ||
a266c7d5 | 4488 | for (;;) { |
501e01d7 | 4489 | bool irq_received = (iir & ~flip_mask) != 0; |
2c8ba29f CW |
4490 | bool blc_event = false; |
4491 | ||
a266c7d5 CW |
4492 | /* Can't rely on pipestat interrupt bit in iir as it might |
4493 | * have been cleared after the pipestat interrupt was received. | |
4494 | * It doesn't set the bit in iir again, but it still produces | |
4495 | * interrupts (for non-MSI). | |
4496 | */ | |
222c7f51 | 4497 | spin_lock(&dev_priv->irq_lock); |
a266c7d5 | 4498 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
58174462 MK |
4499 | i915_handle_error(dev, false, |
4500 | "Command parser error, iir 0x%08x", | |
4501 | iir); | |
a266c7d5 | 4502 | |
055e393f | 4503 | for_each_pipe(dev_priv, pipe) { |
a266c7d5 CW |
4504 | int reg = PIPESTAT(pipe); |
4505 | pipe_stats[pipe] = I915_READ(reg); | |
4506 | ||
4507 | /* | |
4508 | * Clear the PIPE*STAT regs before the IIR | |
4509 | */ | |
4510 | if (pipe_stats[pipe] & 0x8000ffff) { | |
a266c7d5 | 4511 | I915_WRITE(reg, pipe_stats[pipe]); |
501e01d7 | 4512 | irq_received = true; |
a266c7d5 CW |
4513 | } |
4514 | } | |
222c7f51 | 4515 | spin_unlock(&dev_priv->irq_lock); |
a266c7d5 CW |
4516 | |
4517 | if (!irq_received) | |
4518 | break; | |
4519 | ||
4520 | ret = IRQ_HANDLED; | |
4521 | ||
4522 | /* Consume port. Then clear IIR or we'll miss events */ | |
16c6c56b VS |
4523 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
4524 | i9xx_hpd_irq_handler(dev); | |
a266c7d5 | 4525 | |
21ad8330 | 4526 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
4527 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
4528 | ||
a266c7d5 CW |
4529 | if (iir & I915_USER_INTERRUPT) |
4530 | notify_ring(dev, &dev_priv->ring[RCS]); | |
4531 | if (iir & I915_BSD_USER_INTERRUPT) | |
4532 | notify_ring(dev, &dev_priv->ring[VCS]); | |
4533 | ||
055e393f | 4534 | for_each_pipe(dev_priv, pipe) { |
2c8ba29f | 4535 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
4536 | i915_handle_vblank(dev, pipe, pipe, iir)) |
4537 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); | |
a266c7d5 CW |
4538 | |
4539 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
4540 | blc_event = true; | |
4356d586 DV |
4541 | |
4542 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 4543 | i9xx_pipe_crc_irq_handler(dev, pipe); |
a266c7d5 | 4544 | |
2d9d2b0b VS |
4545 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && |
4546 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
fc2c807b | 4547 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); |
2d9d2b0b | 4548 | } |
a266c7d5 CW |
4549 | |
4550 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | |
4551 | intel_opregion_asle_intr(dev); | |
4552 | ||
515ac2bb DV |
4553 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
4554 | gmbus_irq_handler(dev); | |
4555 | ||
a266c7d5 CW |
4556 | /* With MSI, interrupts are only generated when iir |
4557 | * transitions from zero to nonzero. If another bit got | |
4558 | * set while we were handling the existing iir bits, then | |
4559 | * we would never get another interrupt. | |
4560 | * | |
4561 | * This is fine on non-MSI as well, as if we hit this path | |
4562 | * we avoid exiting the interrupt handler only to generate | |
4563 | * another one. | |
4564 | * | |
4565 | * Note that for MSI this could cause a stray interrupt report | |
4566 | * if an interrupt landed in the time between writing IIR and | |
4567 | * the posting read. This should be rare enough to never | |
4568 | * trigger the 99% of 100,000 interrupts test for disabling | |
4569 | * stray interrupts. | |
4570 | */ | |
4571 | iir = new_iir; | |
4572 | } | |
4573 | ||
d05c617e | 4574 | i915_update_dri1_breadcrumb(dev); |
2c8ba29f | 4575 | |
a266c7d5 CW |
4576 | return ret; |
4577 | } | |
4578 | ||
4579 | static void i965_irq_uninstall(struct drm_device * dev) | |
4580 | { | |
2d1013dd | 4581 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4582 | int pipe; |
4583 | ||
4584 | if (!dev_priv) | |
4585 | return; | |
4586 | ||
adca4730 CW |
4587 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
4588 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
4589 | |
4590 | I915_WRITE(HWSTAM, 0xffffffff); | |
055e393f | 4591 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4592 | I915_WRITE(PIPESTAT(pipe), 0); |
4593 | I915_WRITE(IMR, 0xffffffff); | |
4594 | I915_WRITE(IER, 0x0); | |
4595 | ||
055e393f | 4596 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4597 | I915_WRITE(PIPESTAT(pipe), |
4598 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); | |
4599 | I915_WRITE(IIR, I915_READ(IIR)); | |
4600 | } | |
4601 | ||
4cb21832 | 4602 | static void intel_hpd_irq_reenable_work(struct work_struct *work) |
ac4c16c5 | 4603 | { |
6323751d ID |
4604 | struct drm_i915_private *dev_priv = |
4605 | container_of(work, typeof(*dev_priv), | |
4606 | hotplug_reenable_work.work); | |
ac4c16c5 EE |
4607 | struct drm_device *dev = dev_priv->dev; |
4608 | struct drm_mode_config *mode_config = &dev->mode_config; | |
ac4c16c5 EE |
4609 | int i; |
4610 | ||
6323751d ID |
4611 | intel_runtime_pm_get(dev_priv); |
4612 | ||
4cb21832 | 4613 | spin_lock_irq(&dev_priv->irq_lock); |
ac4c16c5 EE |
4614 | for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) { |
4615 | struct drm_connector *connector; | |
4616 | ||
4617 | if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED) | |
4618 | continue; | |
4619 | ||
4620 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
4621 | ||
4622 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
4623 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4624 | ||
4625 | if (intel_connector->encoder->hpd_pin == i) { | |
4626 | if (connector->polled != intel_connector->polled) | |
4627 | DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n", | |
c23cc417 | 4628 | connector->name); |
ac4c16c5 EE |
4629 | connector->polled = intel_connector->polled; |
4630 | if (!connector->polled) | |
4631 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
4632 | } | |
4633 | } | |
4634 | } | |
4635 | if (dev_priv->display.hpd_irq_setup) | |
4636 | dev_priv->display.hpd_irq_setup(dev); | |
4cb21832 | 4637 | spin_unlock_irq(&dev_priv->irq_lock); |
6323751d ID |
4638 | |
4639 | intel_runtime_pm_put(dev_priv); | |
ac4c16c5 EE |
4640 | } |
4641 | ||
fca52a55 DV |
4642 | /** |
4643 | * intel_irq_init - initializes irq support | |
4644 | * @dev_priv: i915 device instance | |
4645 | * | |
4646 | * This function initializes all the irq support including work items, timers | |
4647 | * and all the vtables. It does not setup the interrupt itself though. | |
4648 | */ | |
b963291c | 4649 | void intel_irq_init(struct drm_i915_private *dev_priv) |
f71d4af4 | 4650 | { |
b963291c | 4651 | struct drm_device *dev = dev_priv->dev; |
8b2e326d CW |
4652 | |
4653 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); | |
13cf5504 | 4654 | INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func); |
99584db3 | 4655 | INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func); |
c6a828d3 | 4656 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
a4da4fa4 | 4657 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
8b2e326d | 4658 | |
a6706b45 | 4659 | /* Let's track the enabled rps events */ |
b963291c | 4660 | if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) |
6c65a587 | 4661 | /* WaGsvRC0ResidencyMethod:vlv */ |
31685c25 D |
4662 | dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED; |
4663 | else | |
4664 | dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; | |
a6706b45 | 4665 | |
99584db3 DV |
4666 | setup_timer(&dev_priv->gpu_error.hangcheck_timer, |
4667 | i915_hangcheck_elapsed, | |
61bac78e | 4668 | (unsigned long) dev); |
6323751d | 4669 | INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work, |
4cb21832 | 4670 | intel_hpd_irq_reenable_work); |
61bac78e | 4671 | |
97a19a24 | 4672 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); |
9ee32fea | 4673 | |
b963291c | 4674 | if (IS_GEN2(dev_priv)) { |
4cdb83ec VS |
4675 | dev->max_vblank_count = 0; |
4676 | dev->driver->get_vblank_counter = i8xx_get_vblank_counter; | |
b963291c | 4677 | } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { |
f71d4af4 JB |
4678 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
4679 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; | |
391f75e2 VS |
4680 | } else { |
4681 | dev->driver->get_vblank_counter = i915_get_vblank_counter; | |
4682 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
f71d4af4 JB |
4683 | } |
4684 | ||
21da2700 VS |
4685 | /* |
4686 | * Opt out of the vblank disable timer on everything except gen2. | |
4687 | * Gen2 doesn't have a hardware frame counter and so depends on | |
4688 | * vblank interrupts to produce sane vblank seuquence numbers. | |
4689 | */ | |
b963291c | 4690 | if (!IS_GEN2(dev_priv)) |
21da2700 VS |
4691 | dev->vblank_disable_immediate = true; |
4692 | ||
c2baf4b7 | 4693 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
c3613de9 | 4694 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; |
c2baf4b7 VS |
4695 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; |
4696 | } | |
f71d4af4 | 4697 | |
b963291c | 4698 | if (IS_CHERRYVIEW(dev_priv)) { |
43f328d7 VS |
4699 | dev->driver->irq_handler = cherryview_irq_handler; |
4700 | dev->driver->irq_preinstall = cherryview_irq_preinstall; | |
4701 | dev->driver->irq_postinstall = cherryview_irq_postinstall; | |
4702 | dev->driver->irq_uninstall = cherryview_irq_uninstall; | |
4703 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4704 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
4705 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; | |
b963291c | 4706 | } else if (IS_VALLEYVIEW(dev_priv)) { |
7e231dbe JB |
4707 | dev->driver->irq_handler = valleyview_irq_handler; |
4708 | dev->driver->irq_preinstall = valleyview_irq_preinstall; | |
4709 | dev->driver->irq_postinstall = valleyview_irq_postinstall; | |
4710 | dev->driver->irq_uninstall = valleyview_irq_uninstall; | |
4711 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4712 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
fa00abe0 | 4713 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
b963291c | 4714 | } else if (INTEL_INFO(dev_priv)->gen >= 8) { |
abd58f01 | 4715 | dev->driver->irq_handler = gen8_irq_handler; |
723761b8 | 4716 | dev->driver->irq_preinstall = gen8_irq_reset; |
abd58f01 BW |
4717 | dev->driver->irq_postinstall = gen8_irq_postinstall; |
4718 | dev->driver->irq_uninstall = gen8_irq_uninstall; | |
4719 | dev->driver->enable_vblank = gen8_enable_vblank; | |
4720 | dev->driver->disable_vblank = gen8_disable_vblank; | |
4721 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; | |
f71d4af4 JB |
4722 | } else if (HAS_PCH_SPLIT(dev)) { |
4723 | dev->driver->irq_handler = ironlake_irq_handler; | |
723761b8 | 4724 | dev->driver->irq_preinstall = ironlake_irq_reset; |
f71d4af4 JB |
4725 | dev->driver->irq_postinstall = ironlake_irq_postinstall; |
4726 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
4727 | dev->driver->enable_vblank = ironlake_enable_vblank; | |
4728 | dev->driver->disable_vblank = ironlake_disable_vblank; | |
82a28bcf | 4729 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; |
f71d4af4 | 4730 | } else { |
b963291c | 4731 | if (INTEL_INFO(dev_priv)->gen == 2) { |
c2798b19 CW |
4732 | dev->driver->irq_preinstall = i8xx_irq_preinstall; |
4733 | dev->driver->irq_postinstall = i8xx_irq_postinstall; | |
4734 | dev->driver->irq_handler = i8xx_irq_handler; | |
4735 | dev->driver->irq_uninstall = i8xx_irq_uninstall; | |
b963291c | 4736 | } else if (INTEL_INFO(dev_priv)->gen == 3) { |
a266c7d5 CW |
4737 | dev->driver->irq_preinstall = i915_irq_preinstall; |
4738 | dev->driver->irq_postinstall = i915_irq_postinstall; | |
4739 | dev->driver->irq_uninstall = i915_irq_uninstall; | |
4740 | dev->driver->irq_handler = i915_irq_handler; | |
20afbda2 | 4741 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
c2798b19 | 4742 | } else { |
a266c7d5 CW |
4743 | dev->driver->irq_preinstall = i965_irq_preinstall; |
4744 | dev->driver->irq_postinstall = i965_irq_postinstall; | |
4745 | dev->driver->irq_uninstall = i965_irq_uninstall; | |
4746 | dev->driver->irq_handler = i965_irq_handler; | |
bac56d5b | 4747 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
c2798b19 | 4748 | } |
f71d4af4 JB |
4749 | dev->driver->enable_vblank = i915_enable_vblank; |
4750 | dev->driver->disable_vblank = i915_disable_vblank; | |
4751 | } | |
4752 | } | |
20afbda2 | 4753 | |
fca52a55 DV |
4754 | /** |
4755 | * intel_hpd_init - initializes and enables hpd support | |
4756 | * @dev_priv: i915 device instance | |
4757 | * | |
4758 | * This function enables the hotplug support. It requires that interrupts have | |
4759 | * already been enabled with intel_irq_init_hw(). From this point on hotplug and | |
4760 | * poll request can run concurrently to other code, so locking rules must be | |
4761 | * obeyed. | |
4762 | * | |
4763 | * This is a separate step from interrupt enabling to simplify the locking rules | |
4764 | * in the driver load and resume code. | |
4765 | */ | |
b963291c | 4766 | void intel_hpd_init(struct drm_i915_private *dev_priv) |
20afbda2 | 4767 | { |
b963291c | 4768 | struct drm_device *dev = dev_priv->dev; |
821450c6 EE |
4769 | struct drm_mode_config *mode_config = &dev->mode_config; |
4770 | struct drm_connector *connector; | |
4771 | int i; | |
20afbda2 | 4772 | |
821450c6 EE |
4773 | for (i = 1; i < HPD_NUM_PINS; i++) { |
4774 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
4775 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
4776 | } | |
4777 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
4778 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4779 | connector->polled = intel_connector->polled; | |
0e32b39c DA |
4780 | if (connector->encoder && !connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE) |
4781 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
4782 | if (intel_connector->mst_port) | |
821450c6 EE |
4783 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
4784 | } | |
b5ea2d56 DV |
4785 | |
4786 | /* Interrupt setup is already guaranteed to be single-threaded, this is | |
4787 | * just to make the assert_spin_locked checks happy. */ | |
d6207435 | 4788 | spin_lock_irq(&dev_priv->irq_lock); |
20afbda2 DV |
4789 | if (dev_priv->display.hpd_irq_setup) |
4790 | dev_priv->display.hpd_irq_setup(dev); | |
d6207435 | 4791 | spin_unlock_irq(&dev_priv->irq_lock); |
20afbda2 | 4792 | } |
c67a470b | 4793 | |
fca52a55 DV |
4794 | /** |
4795 | * intel_irq_install - enables the hardware interrupt | |
4796 | * @dev_priv: i915 device instance | |
4797 | * | |
4798 | * This function enables the hardware interrupt handling, but leaves the hotplug | |
4799 | * handling still disabled. It is called after intel_irq_init(). | |
4800 | * | |
4801 | * In the driver load and resume code we need working interrupts in a few places | |
4802 | * but don't want to deal with the hassle of concurrent probe and hotplug | |
4803 | * workers. Hence the split into this two-stage approach. | |
4804 | */ | |
2aeb7d3a DV |
4805 | int intel_irq_install(struct drm_i915_private *dev_priv) |
4806 | { | |
4807 | /* | |
4808 | * We enable some interrupt sources in our postinstall hooks, so mark | |
4809 | * interrupts as enabled _before_ actually enabling them to avoid | |
4810 | * special cases in our ordering checks. | |
4811 | */ | |
4812 | dev_priv->pm.irqs_enabled = true; | |
4813 | ||
4814 | return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq); | |
4815 | } | |
4816 | ||
fca52a55 DV |
4817 | /** |
4818 | * intel_irq_uninstall - finilizes all irq handling | |
4819 | * @dev_priv: i915 device instance | |
4820 | * | |
4821 | * This stops interrupt and hotplug handling and unregisters and frees all | |
4822 | * resources acquired in the init functions. | |
4823 | */ | |
2aeb7d3a DV |
4824 | void intel_irq_uninstall(struct drm_i915_private *dev_priv) |
4825 | { | |
4826 | drm_irq_uninstall(dev_priv->dev); | |
4827 | intel_hpd_cancel_work(dev_priv); | |
4828 | dev_priv->pm.irqs_enabled = false; | |
4829 | } | |
4830 | ||
fca52a55 DV |
4831 | /** |
4832 | * intel_runtime_pm_disable_interrupts - runtime interrupt disabling | |
4833 | * @dev_priv: i915 device instance | |
4834 | * | |
4835 | * This function is used to disable interrupts at runtime, both in the runtime | |
4836 | * pm and the system suspend/resume code. | |
4837 | */ | |
b963291c | 4838 | void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv) |
c67a470b | 4839 | { |
b963291c | 4840 | dev_priv->dev->driver->irq_uninstall(dev_priv->dev); |
2aeb7d3a | 4841 | dev_priv->pm.irqs_enabled = false; |
c67a470b PZ |
4842 | } |
4843 | ||
fca52a55 DV |
4844 | /** |
4845 | * intel_runtime_pm_enable_interrupts - runtime interrupt enabling | |
4846 | * @dev_priv: i915 device instance | |
4847 | * | |
4848 | * This function is used to enable interrupts at runtime, both in the runtime | |
4849 | * pm and the system suspend/resume code. | |
4850 | */ | |
b963291c | 4851 | void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv) |
c67a470b | 4852 | { |
2aeb7d3a | 4853 | dev_priv->pm.irqs_enabled = true; |
b963291c DV |
4854 | dev_priv->dev->driver->irq_preinstall(dev_priv->dev); |
4855 | dev_priv->dev->driver->irq_postinstall(dev_priv->dev); | |
c67a470b | 4856 | } |