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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
63eeaf38 | 31 | #include <linux/sysrq.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
b2c88f5b | 33 | #include <linux/circ_buf.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/i915_drm.h> | |
1da177e4 | 36 | #include "i915_drv.h" |
1c5d22f7 | 37 | #include "i915_trace.h" |
79e53945 | 38 | #include "intel_drv.h" |
1da177e4 | 39 | |
fca52a55 DV |
40 | /** |
41 | * DOC: interrupt handling | |
42 | * | |
43 | * These functions provide the basic support for enabling and disabling the | |
44 | * interrupt handling support. There's a lot more functionality in i915_irq.c | |
45 | * and related files, but that will be described in separate chapters. | |
46 | */ | |
47 | ||
7c7e10db | 48 | static const u32 hpd_ibx[HPD_NUM_PINS] = { |
e5868a31 EE |
49 | [HPD_CRT] = SDE_CRT_HOTPLUG, |
50 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, | |
51 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG, | |
52 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG, | |
53 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG | |
54 | }; | |
55 | ||
7c7e10db | 56 | static const u32 hpd_cpt[HPD_NUM_PINS] = { |
e5868a31 | 57 | [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, |
73c352a2 | 58 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, |
e5868a31 EE |
59 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
60 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
61 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT | |
62 | }; | |
63 | ||
7c7e10db | 64 | static const u32 hpd_mask_i915[HPD_NUM_PINS] = { |
e5868a31 EE |
65 | [HPD_CRT] = CRT_HOTPLUG_INT_EN, |
66 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, | |
67 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, | |
68 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, | |
69 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, | |
70 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN | |
71 | }; | |
72 | ||
7c7e10db | 73 | static const u32 hpd_status_g4x[HPD_NUM_PINS] = { |
e5868a31 EE |
74 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
75 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, | |
76 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, | |
77 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
78 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
79 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
80 | }; | |
81 | ||
7c7e10db | 82 | static const u32 hpd_status_i915[HPD_NUM_PINS] = { /* i915 and valleyview are the same */ |
e5868a31 EE |
83 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
84 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, | |
85 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, | |
86 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
87 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
88 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
89 | }; | |
90 | ||
5c502442 | 91 | /* IIR can theoretically queue up two events. Be paranoid. */ |
f86f3fb0 | 92 | #define GEN8_IRQ_RESET_NDX(type, which) do { \ |
5c502442 PZ |
93 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ |
94 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
95 | I915_WRITE(GEN8_##type##_IER(which), 0); \ | |
96 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
97 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
98 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
99 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
100 | } while (0) | |
101 | ||
f86f3fb0 | 102 | #define GEN5_IRQ_RESET(type) do { \ |
a9d356a6 | 103 | I915_WRITE(type##IMR, 0xffffffff); \ |
5c502442 | 104 | POSTING_READ(type##IMR); \ |
a9d356a6 | 105 | I915_WRITE(type##IER, 0); \ |
5c502442 PZ |
106 | I915_WRITE(type##IIR, 0xffffffff); \ |
107 | POSTING_READ(type##IIR); \ | |
108 | I915_WRITE(type##IIR, 0xffffffff); \ | |
109 | POSTING_READ(type##IIR); \ | |
a9d356a6 PZ |
110 | } while (0) |
111 | ||
337ba017 PZ |
112 | /* |
113 | * We should clear IMR at preinstall/uninstall, and just check at postinstall. | |
114 | */ | |
115 | #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \ | |
116 | u32 val = I915_READ(reg); \ | |
117 | if (val) { \ | |
118 | WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \ | |
119 | (reg), val); \ | |
120 | I915_WRITE((reg), 0xffffffff); \ | |
121 | POSTING_READ(reg); \ | |
122 | I915_WRITE((reg), 0xffffffff); \ | |
123 | POSTING_READ(reg); \ | |
124 | } \ | |
125 | } while (0) | |
126 | ||
35079899 | 127 | #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \ |
337ba017 | 128 | GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \ |
35079899 | 129 | I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \ |
7d1bd539 VS |
130 | I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \ |
131 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
35079899 PZ |
132 | } while (0) |
133 | ||
134 | #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \ | |
337ba017 | 135 | GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \ |
35079899 | 136 | I915_WRITE(type##IER, (ier_val)); \ |
7d1bd539 VS |
137 | I915_WRITE(type##IMR, (imr_val)); \ |
138 | POSTING_READ(type##IMR); \ | |
35079899 PZ |
139 | } while (0) |
140 | ||
c9a9a268 ID |
141 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir); |
142 | ||
036a4a7d | 143 | /* For display hotplug interrupt */ |
47339cd9 | 144 | void |
2d1013dd | 145 | ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask) |
036a4a7d | 146 | { |
4bc9d430 DV |
147 | assert_spin_locked(&dev_priv->irq_lock); |
148 | ||
9df7575f | 149 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 150 | return; |
c67a470b | 151 | |
1ec14ad3 CW |
152 | if ((dev_priv->irq_mask & mask) != 0) { |
153 | dev_priv->irq_mask &= ~mask; | |
154 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 155 | POSTING_READ(DEIMR); |
036a4a7d ZW |
156 | } |
157 | } | |
158 | ||
47339cd9 | 159 | void |
2d1013dd | 160 | ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask) |
036a4a7d | 161 | { |
4bc9d430 DV |
162 | assert_spin_locked(&dev_priv->irq_lock); |
163 | ||
06ffc778 | 164 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 165 | return; |
c67a470b | 166 | |
1ec14ad3 CW |
167 | if ((dev_priv->irq_mask & mask) != mask) { |
168 | dev_priv->irq_mask |= mask; | |
169 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 170 | POSTING_READ(DEIMR); |
036a4a7d ZW |
171 | } |
172 | } | |
173 | ||
43eaea13 PZ |
174 | /** |
175 | * ilk_update_gt_irq - update GTIMR | |
176 | * @dev_priv: driver private | |
177 | * @interrupt_mask: mask of interrupt bits to update | |
178 | * @enabled_irq_mask: mask of interrupt bits to enable | |
179 | */ | |
180 | static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, | |
181 | uint32_t interrupt_mask, | |
182 | uint32_t enabled_irq_mask) | |
183 | { | |
184 | assert_spin_locked(&dev_priv->irq_lock); | |
185 | ||
15a17aae DV |
186 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
187 | ||
9df7575f | 188 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 189 | return; |
c67a470b | 190 | |
43eaea13 PZ |
191 | dev_priv->gt_irq_mask &= ~interrupt_mask; |
192 | dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); | |
193 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
194 | POSTING_READ(GTIMR); | |
195 | } | |
196 | ||
480c8033 | 197 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
43eaea13 PZ |
198 | { |
199 | ilk_update_gt_irq(dev_priv, mask, mask); | |
200 | } | |
201 | ||
480c8033 | 202 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
43eaea13 PZ |
203 | { |
204 | ilk_update_gt_irq(dev_priv, mask, 0); | |
205 | } | |
206 | ||
b900b949 ID |
207 | static u32 gen6_pm_iir(struct drm_i915_private *dev_priv) |
208 | { | |
209 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; | |
210 | } | |
211 | ||
a72fbc3a ID |
212 | static u32 gen6_pm_imr(struct drm_i915_private *dev_priv) |
213 | { | |
214 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR; | |
215 | } | |
216 | ||
b900b949 ID |
217 | static u32 gen6_pm_ier(struct drm_i915_private *dev_priv) |
218 | { | |
219 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER; | |
220 | } | |
221 | ||
edbfdb45 PZ |
222 | /** |
223 | * snb_update_pm_irq - update GEN6_PMIMR | |
224 | * @dev_priv: driver private | |
225 | * @interrupt_mask: mask of interrupt bits to update | |
226 | * @enabled_irq_mask: mask of interrupt bits to enable | |
227 | */ | |
228 | static void snb_update_pm_irq(struct drm_i915_private *dev_priv, | |
229 | uint32_t interrupt_mask, | |
230 | uint32_t enabled_irq_mask) | |
231 | { | |
605cd25b | 232 | uint32_t new_val; |
edbfdb45 | 233 | |
15a17aae DV |
234 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
235 | ||
edbfdb45 PZ |
236 | assert_spin_locked(&dev_priv->irq_lock); |
237 | ||
605cd25b | 238 | new_val = dev_priv->pm_irq_mask; |
f52ecbcf PZ |
239 | new_val &= ~interrupt_mask; |
240 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
241 | ||
605cd25b PZ |
242 | if (new_val != dev_priv->pm_irq_mask) { |
243 | dev_priv->pm_irq_mask = new_val; | |
a72fbc3a ID |
244 | I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask); |
245 | POSTING_READ(gen6_pm_imr(dev_priv)); | |
f52ecbcf | 246 | } |
edbfdb45 PZ |
247 | } |
248 | ||
480c8033 | 249 | void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
edbfdb45 | 250 | { |
9939fba2 ID |
251 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
252 | return; | |
253 | ||
edbfdb45 PZ |
254 | snb_update_pm_irq(dev_priv, mask, mask); |
255 | } | |
256 | ||
9939fba2 ID |
257 | static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv, |
258 | uint32_t mask) | |
edbfdb45 PZ |
259 | { |
260 | snb_update_pm_irq(dev_priv, mask, 0); | |
261 | } | |
262 | ||
9939fba2 ID |
263 | void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
264 | { | |
265 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) | |
266 | return; | |
267 | ||
268 | __gen6_disable_pm_irq(dev_priv, mask); | |
269 | } | |
270 | ||
3cc134e3 ID |
271 | void gen6_reset_rps_interrupts(struct drm_device *dev) |
272 | { | |
273 | struct drm_i915_private *dev_priv = dev->dev_private; | |
274 | uint32_t reg = gen6_pm_iir(dev_priv); | |
275 | ||
276 | spin_lock_irq(&dev_priv->irq_lock); | |
277 | I915_WRITE(reg, dev_priv->pm_rps_events); | |
278 | I915_WRITE(reg, dev_priv->pm_rps_events); | |
279 | POSTING_READ(reg); | |
096fad9e | 280 | dev_priv->rps.pm_iir = 0; |
3cc134e3 ID |
281 | spin_unlock_irq(&dev_priv->irq_lock); |
282 | } | |
283 | ||
b900b949 ID |
284 | void gen6_enable_rps_interrupts(struct drm_device *dev) |
285 | { | |
286 | struct drm_i915_private *dev_priv = dev->dev_private; | |
287 | ||
288 | spin_lock_irq(&dev_priv->irq_lock); | |
78e68d36 | 289 | |
b900b949 | 290 | WARN_ON(dev_priv->rps.pm_iir); |
3cc134e3 | 291 | WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events); |
d4d70aa5 | 292 | dev_priv->rps.interrupts_enabled = true; |
78e68d36 ID |
293 | I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) | |
294 | dev_priv->pm_rps_events); | |
b900b949 | 295 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
78e68d36 | 296 | |
b900b949 ID |
297 | spin_unlock_irq(&dev_priv->irq_lock); |
298 | } | |
299 | ||
59d02a1f ID |
300 | u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask) |
301 | { | |
302 | /* | |
f24eeb19 | 303 | * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer |
59d02a1f | 304 | * if GEN6_PM_UP_EI_EXPIRED is masked. |
f24eeb19 ID |
305 | * |
306 | * TODO: verify if this can be reproduced on VLV,CHV. | |
59d02a1f ID |
307 | */ |
308 | if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv)) | |
309 | mask &= ~GEN6_PM_RP_UP_EI_EXPIRED; | |
310 | ||
311 | if (INTEL_INFO(dev_priv)->gen >= 8) | |
312 | mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP; | |
313 | ||
314 | return mask; | |
315 | } | |
316 | ||
b900b949 ID |
317 | void gen6_disable_rps_interrupts(struct drm_device *dev) |
318 | { | |
319 | struct drm_i915_private *dev_priv = dev->dev_private; | |
320 | ||
d4d70aa5 ID |
321 | spin_lock_irq(&dev_priv->irq_lock); |
322 | dev_priv->rps.interrupts_enabled = false; | |
323 | spin_unlock_irq(&dev_priv->irq_lock); | |
324 | ||
325 | cancel_work_sync(&dev_priv->rps.work); | |
326 | ||
9939fba2 ID |
327 | spin_lock_irq(&dev_priv->irq_lock); |
328 | ||
59d02a1f | 329 | I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0)); |
9939fba2 ID |
330 | |
331 | __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events); | |
b900b949 ID |
332 | I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) & |
333 | ~dev_priv->pm_rps_events); | |
58072ccb ID |
334 | |
335 | spin_unlock_irq(&dev_priv->irq_lock); | |
336 | ||
337 | synchronize_irq(dev->irq); | |
b900b949 ID |
338 | } |
339 | ||
fee884ed DV |
340 | /** |
341 | * ibx_display_interrupt_update - update SDEIMR | |
342 | * @dev_priv: driver private | |
343 | * @interrupt_mask: mask of interrupt bits to update | |
344 | * @enabled_irq_mask: mask of interrupt bits to enable | |
345 | */ | |
47339cd9 DV |
346 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
347 | uint32_t interrupt_mask, | |
348 | uint32_t enabled_irq_mask) | |
fee884ed DV |
349 | { |
350 | uint32_t sdeimr = I915_READ(SDEIMR); | |
351 | sdeimr &= ~interrupt_mask; | |
352 | sdeimr |= (~enabled_irq_mask & interrupt_mask); | |
353 | ||
15a17aae DV |
354 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
355 | ||
fee884ed DV |
356 | assert_spin_locked(&dev_priv->irq_lock); |
357 | ||
9df7575f | 358 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 359 | return; |
c67a470b | 360 | |
fee884ed DV |
361 | I915_WRITE(SDEIMR, sdeimr); |
362 | POSTING_READ(SDEIMR); | |
363 | } | |
8664281b | 364 | |
b5ea642a | 365 | static void |
755e9019 ID |
366 | __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
367 | u32 enable_mask, u32 status_mask) | |
7c463586 | 368 | { |
46c06a30 | 369 | u32 reg = PIPESTAT(pipe); |
755e9019 | 370 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 371 | |
b79480ba | 372 | assert_spin_locked(&dev_priv->irq_lock); |
d518ce50 | 373 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
b79480ba | 374 | |
04feced9 VS |
375 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
376 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
377 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
378 | pipe_name(pipe), enable_mask, status_mask)) | |
755e9019 ID |
379 | return; |
380 | ||
381 | if ((pipestat & enable_mask) == enable_mask) | |
46c06a30 VS |
382 | return; |
383 | ||
91d181dd ID |
384 | dev_priv->pipestat_irq_mask[pipe] |= status_mask; |
385 | ||
46c06a30 | 386 | /* Enable the interrupt, clear any pending status */ |
755e9019 | 387 | pipestat |= enable_mask | status_mask; |
46c06a30 VS |
388 | I915_WRITE(reg, pipestat); |
389 | POSTING_READ(reg); | |
7c463586 KP |
390 | } |
391 | ||
b5ea642a | 392 | static void |
755e9019 ID |
393 | __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
394 | u32 enable_mask, u32 status_mask) | |
7c463586 | 395 | { |
46c06a30 | 396 | u32 reg = PIPESTAT(pipe); |
755e9019 | 397 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 398 | |
b79480ba | 399 | assert_spin_locked(&dev_priv->irq_lock); |
d518ce50 | 400 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
b79480ba | 401 | |
04feced9 VS |
402 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
403 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
404 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
405 | pipe_name(pipe), enable_mask, status_mask)) | |
46c06a30 VS |
406 | return; |
407 | ||
755e9019 ID |
408 | if ((pipestat & enable_mask) == 0) |
409 | return; | |
410 | ||
91d181dd ID |
411 | dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; |
412 | ||
755e9019 | 413 | pipestat &= ~enable_mask; |
46c06a30 VS |
414 | I915_WRITE(reg, pipestat); |
415 | POSTING_READ(reg); | |
7c463586 KP |
416 | } |
417 | ||
10c59c51 ID |
418 | static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask) |
419 | { | |
420 | u32 enable_mask = status_mask << 16; | |
421 | ||
422 | /* | |
724a6905 VS |
423 | * On pipe A we don't support the PSR interrupt yet, |
424 | * on pipe B and C the same bit MBZ. | |
10c59c51 ID |
425 | */ |
426 | if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV)) | |
427 | return 0; | |
724a6905 VS |
428 | /* |
429 | * On pipe B and C we don't support the PSR interrupt yet, on pipe | |
430 | * A the same bit is for perf counters which we don't use either. | |
431 | */ | |
432 | if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV)) | |
433 | return 0; | |
10c59c51 ID |
434 | |
435 | enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | | |
436 | SPRITE0_FLIP_DONE_INT_EN_VLV | | |
437 | SPRITE1_FLIP_DONE_INT_EN_VLV); | |
438 | if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV) | |
439 | enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV; | |
440 | if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV) | |
441 | enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; | |
442 | ||
443 | return enable_mask; | |
444 | } | |
445 | ||
755e9019 ID |
446 | void |
447 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
448 | u32 status_mask) | |
449 | { | |
450 | u32 enable_mask; | |
451 | ||
10c59c51 ID |
452 | if (IS_VALLEYVIEW(dev_priv->dev)) |
453 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, | |
454 | status_mask); | |
455 | else | |
456 | enable_mask = status_mask << 16; | |
755e9019 ID |
457 | __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
458 | } | |
459 | ||
460 | void | |
461 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
462 | u32 status_mask) | |
463 | { | |
464 | u32 enable_mask; | |
465 | ||
10c59c51 ID |
466 | if (IS_VALLEYVIEW(dev_priv->dev)) |
467 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, | |
468 | status_mask); | |
469 | else | |
470 | enable_mask = status_mask << 16; | |
755e9019 ID |
471 | __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
472 | } | |
473 | ||
01c66889 | 474 | /** |
f49e38dd | 475 | * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion |
01c66889 | 476 | */ |
f49e38dd | 477 | static void i915_enable_asle_pipestat(struct drm_device *dev) |
01c66889 | 478 | { |
2d1013dd | 479 | struct drm_i915_private *dev_priv = dev->dev_private; |
1ec14ad3 | 480 | |
f49e38dd JN |
481 | if (!dev_priv->opregion.asle || !IS_MOBILE(dev)) |
482 | return; | |
483 | ||
13321786 | 484 | spin_lock_irq(&dev_priv->irq_lock); |
01c66889 | 485 | |
755e9019 | 486 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); |
f898780b | 487 | if (INTEL_INFO(dev)->gen >= 4) |
3b6c42e8 | 488 | i915_enable_pipestat(dev_priv, PIPE_A, |
755e9019 | 489 | PIPE_LEGACY_BLC_EVENT_STATUS); |
1ec14ad3 | 490 | |
13321786 | 491 | spin_unlock_irq(&dev_priv->irq_lock); |
01c66889 ZY |
492 | } |
493 | ||
f75f3746 VS |
494 | /* |
495 | * This timing diagram depicts the video signal in and | |
496 | * around the vertical blanking period. | |
497 | * | |
498 | * Assumptions about the fictitious mode used in this example: | |
499 | * vblank_start >= 3 | |
500 | * vsync_start = vblank_start + 1 | |
501 | * vsync_end = vblank_start + 2 | |
502 | * vtotal = vblank_start + 3 | |
503 | * | |
504 | * start of vblank: | |
505 | * latch double buffered registers | |
506 | * increment frame counter (ctg+) | |
507 | * generate start of vblank interrupt (gen4+) | |
508 | * | | |
509 | * | frame start: | |
510 | * | generate frame start interrupt (aka. vblank interrupt) (gmch) | |
511 | * | may be shifted forward 1-3 extra lines via PIPECONF | |
512 | * | | | |
513 | * | | start of vsync: | |
514 | * | | generate vsync interrupt | |
515 | * | | | | |
516 | * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx | |
517 | * . \hs/ . \hs/ \hs/ \hs/ . \hs/ | |
518 | * ----va---> <-----------------vb--------------------> <--------va------------- | |
519 | * | | <----vs-----> | | |
520 | * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2) | |
521 | * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+) | |
522 | * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi) | |
523 | * | | | | |
524 | * last visible pixel first visible pixel | |
525 | * | increment frame counter (gen3/4) | |
526 | * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4) | |
527 | * | |
528 | * x = horizontal active | |
529 | * _ = horizontal blanking | |
530 | * hs = horizontal sync | |
531 | * va = vertical active | |
532 | * vb = vertical blanking | |
533 | * vs = vertical sync | |
534 | * vbs = vblank_start (number) | |
535 | * | |
536 | * Summary: | |
537 | * - most events happen at the start of horizontal sync | |
538 | * - frame start happens at the start of horizontal blank, 1-4 lines | |
539 | * (depending on PIPECONF settings) after the start of vblank | |
540 | * - gen3/4 pixel and frame counter are synchronized with the start | |
541 | * of horizontal active on the first line of vertical active | |
542 | */ | |
543 | ||
4cdb83ec VS |
544 | static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe) |
545 | { | |
546 | /* Gen2 doesn't have a hardware frame counter */ | |
547 | return 0; | |
548 | } | |
549 | ||
42f52ef8 KP |
550 | /* Called from drm generic code, passed a 'crtc', which |
551 | * we use as a pipe index | |
552 | */ | |
f71d4af4 | 553 | static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
0a3e67a4 | 554 | { |
2d1013dd | 555 | struct drm_i915_private *dev_priv = dev->dev_private; |
0a3e67a4 JB |
556 | unsigned long high_frame; |
557 | unsigned long low_frame; | |
0b2a8e09 | 558 | u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal; |
f3a5c3f6 DV |
559 | struct intel_crtc *intel_crtc = |
560 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
561 | const struct drm_display_mode *mode = | |
562 | &intel_crtc->config->base.adjusted_mode; | |
0a3e67a4 | 563 | |
f3a5c3f6 DV |
564 | htotal = mode->crtc_htotal; |
565 | hsync_start = mode->crtc_hsync_start; | |
566 | vbl_start = mode->crtc_vblank_start; | |
567 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
568 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
391f75e2 | 569 | |
0b2a8e09 VS |
570 | /* Convert to pixel count */ |
571 | vbl_start *= htotal; | |
572 | ||
573 | /* Start of vblank event occurs at start of hsync */ | |
574 | vbl_start -= htotal - hsync_start; | |
575 | ||
9db4a9c7 JB |
576 | high_frame = PIPEFRAME(pipe); |
577 | low_frame = PIPEFRAMEPIXEL(pipe); | |
5eddb70b | 578 | |
0a3e67a4 JB |
579 | /* |
580 | * High & low register fields aren't synchronized, so make sure | |
581 | * we get a low value that's stable across two reads of the high | |
582 | * register. | |
583 | */ | |
584 | do { | |
5eddb70b | 585 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
391f75e2 | 586 | low = I915_READ(low_frame); |
5eddb70b | 587 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
0a3e67a4 JB |
588 | } while (high1 != high2); |
589 | ||
5eddb70b | 590 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
391f75e2 | 591 | pixel = low & PIPE_PIXEL_MASK; |
5eddb70b | 592 | low >>= PIPE_FRAME_LOW_SHIFT; |
391f75e2 VS |
593 | |
594 | /* | |
595 | * The frame counter increments at beginning of active. | |
596 | * Cook up a vblank counter by also checking the pixel | |
597 | * counter against vblank start. | |
598 | */ | |
edc08d0a | 599 | return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; |
0a3e67a4 JB |
600 | } |
601 | ||
f71d4af4 | 602 | static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
9880b7a5 | 603 | { |
2d1013dd | 604 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 605 | int reg = PIPE_FRMCOUNT_GM45(pipe); |
9880b7a5 | 606 | |
9880b7a5 JB |
607 | return I915_READ(reg); |
608 | } | |
609 | ||
ad3543ed MK |
610 | /* raw reads, only for fast reads of display block, no need for forcewake etc. */ |
611 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) | |
ad3543ed | 612 | |
a225f079 VS |
613 | static int __intel_get_crtc_scanline(struct intel_crtc *crtc) |
614 | { | |
615 | struct drm_device *dev = crtc->base.dev; | |
616 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 617 | const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; |
a225f079 | 618 | enum pipe pipe = crtc->pipe; |
80715b2f | 619 | int position, vtotal; |
a225f079 | 620 | |
80715b2f | 621 | vtotal = mode->crtc_vtotal; |
a225f079 VS |
622 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
623 | vtotal /= 2; | |
624 | ||
625 | if (IS_GEN2(dev)) | |
626 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; | |
627 | else | |
628 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; | |
629 | ||
630 | /* | |
80715b2f VS |
631 | * See update_scanline_offset() for the details on the |
632 | * scanline_offset adjustment. | |
a225f079 | 633 | */ |
80715b2f | 634 | return (position + crtc->scanline_offset) % vtotal; |
a225f079 VS |
635 | } |
636 | ||
f71d4af4 | 637 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
abca9e45 VS |
638 | unsigned int flags, int *vpos, int *hpos, |
639 | ktime_t *stime, ktime_t *etime) | |
0af7e4df | 640 | { |
c2baf4b7 VS |
641 | struct drm_i915_private *dev_priv = dev->dev_private; |
642 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
643 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 644 | const struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode; |
3aa18df8 | 645 | int position; |
78e8fc6b | 646 | int vbl_start, vbl_end, hsync_start, htotal, vtotal; |
0af7e4df MK |
647 | bool in_vbl = true; |
648 | int ret = 0; | |
ad3543ed | 649 | unsigned long irqflags; |
0af7e4df | 650 | |
c2baf4b7 | 651 | if (!intel_crtc->active) { |
0af7e4df | 652 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
9db4a9c7 | 653 | "pipe %c\n", pipe_name(pipe)); |
0af7e4df MK |
654 | return 0; |
655 | } | |
656 | ||
c2baf4b7 | 657 | htotal = mode->crtc_htotal; |
78e8fc6b | 658 | hsync_start = mode->crtc_hsync_start; |
c2baf4b7 VS |
659 | vtotal = mode->crtc_vtotal; |
660 | vbl_start = mode->crtc_vblank_start; | |
661 | vbl_end = mode->crtc_vblank_end; | |
0af7e4df | 662 | |
d31faf65 VS |
663 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
664 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
665 | vbl_end /= 2; | |
666 | vtotal /= 2; | |
667 | } | |
668 | ||
c2baf4b7 VS |
669 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; |
670 | ||
ad3543ed MK |
671 | /* |
672 | * Lock uncore.lock, as we will do multiple timing critical raw | |
673 | * register reads, potentially with preemption disabled, so the | |
674 | * following code must not block on uncore.lock. | |
675 | */ | |
676 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
78e8fc6b | 677 | |
ad3543ed MK |
678 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ |
679 | ||
680 | /* Get optional system timestamp before query. */ | |
681 | if (stime) | |
682 | *stime = ktime_get(); | |
683 | ||
7c06b08a | 684 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
0af7e4df MK |
685 | /* No obvious pixelcount register. Only query vertical |
686 | * scanout position from Display scan line register. | |
687 | */ | |
a225f079 | 688 | position = __intel_get_crtc_scanline(intel_crtc); |
0af7e4df MK |
689 | } else { |
690 | /* Have access to pixelcount since start of frame. | |
691 | * We can split this into vertical and horizontal | |
692 | * scanout position. | |
693 | */ | |
ad3543ed | 694 | position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; |
0af7e4df | 695 | |
3aa18df8 VS |
696 | /* convert to pixel counts */ |
697 | vbl_start *= htotal; | |
698 | vbl_end *= htotal; | |
699 | vtotal *= htotal; | |
78e8fc6b | 700 | |
7e78f1cb VS |
701 | /* |
702 | * In interlaced modes, the pixel counter counts all pixels, | |
703 | * so one field will have htotal more pixels. In order to avoid | |
704 | * the reported position from jumping backwards when the pixel | |
705 | * counter is beyond the length of the shorter field, just | |
706 | * clamp the position the length of the shorter field. This | |
707 | * matches how the scanline counter based position works since | |
708 | * the scanline counter doesn't count the two half lines. | |
709 | */ | |
710 | if (position >= vtotal) | |
711 | position = vtotal - 1; | |
712 | ||
78e8fc6b VS |
713 | /* |
714 | * Start of vblank interrupt is triggered at start of hsync, | |
715 | * just prior to the first active line of vblank. However we | |
716 | * consider lines to start at the leading edge of horizontal | |
717 | * active. So, should we get here before we've crossed into | |
718 | * the horizontal active of the first line in vblank, we would | |
719 | * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that, | |
720 | * always add htotal-hsync_start to the current pixel position. | |
721 | */ | |
722 | position = (position + htotal - hsync_start) % vtotal; | |
0af7e4df MK |
723 | } |
724 | ||
ad3543ed MK |
725 | /* Get optional system timestamp after query. */ |
726 | if (etime) | |
727 | *etime = ktime_get(); | |
728 | ||
729 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ | |
730 | ||
731 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
732 | ||
3aa18df8 VS |
733 | in_vbl = position >= vbl_start && position < vbl_end; |
734 | ||
735 | /* | |
736 | * While in vblank, position will be negative | |
737 | * counting up towards 0 at vbl_end. And outside | |
738 | * vblank, position will be positive counting | |
739 | * up since vbl_end. | |
740 | */ | |
741 | if (position >= vbl_start) | |
742 | position -= vbl_end; | |
743 | else | |
744 | position += vtotal - vbl_end; | |
0af7e4df | 745 | |
7c06b08a | 746 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
3aa18df8 VS |
747 | *vpos = position; |
748 | *hpos = 0; | |
749 | } else { | |
750 | *vpos = position / htotal; | |
751 | *hpos = position - (*vpos * htotal); | |
752 | } | |
0af7e4df | 753 | |
0af7e4df MK |
754 | /* In vblank? */ |
755 | if (in_vbl) | |
3d3cbd84 | 756 | ret |= DRM_SCANOUTPOS_IN_VBLANK; |
0af7e4df MK |
757 | |
758 | return ret; | |
759 | } | |
760 | ||
a225f079 VS |
761 | int intel_get_crtc_scanline(struct intel_crtc *crtc) |
762 | { | |
763 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
764 | unsigned long irqflags; | |
765 | int position; | |
766 | ||
767 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
768 | position = __intel_get_crtc_scanline(crtc); | |
769 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
770 | ||
771 | return position; | |
772 | } | |
773 | ||
f71d4af4 | 774 | static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
0af7e4df MK |
775 | int *max_error, |
776 | struct timeval *vblank_time, | |
777 | unsigned flags) | |
778 | { | |
4041b853 | 779 | struct drm_crtc *crtc; |
0af7e4df | 780 | |
7eb552ae | 781 | if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { |
4041b853 | 782 | DRM_ERROR("Invalid crtc %d\n", pipe); |
0af7e4df MK |
783 | return -EINVAL; |
784 | } | |
785 | ||
786 | /* Get drm_crtc to timestamp: */ | |
4041b853 CW |
787 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
788 | if (crtc == NULL) { | |
789 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
790 | return -EINVAL; | |
791 | } | |
792 | ||
83d65738 | 793 | if (!crtc->state->enable) { |
4041b853 CW |
794 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); |
795 | return -EBUSY; | |
796 | } | |
0af7e4df MK |
797 | |
798 | /* Helper routine in DRM core does all the work: */ | |
4041b853 CW |
799 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
800 | vblank_time, flags, | |
7da903ef | 801 | crtc, |
6e3c9717 | 802 | &to_intel_crtc(crtc)->config->base.adjusted_mode); |
0af7e4df MK |
803 | } |
804 | ||
67c347ff JN |
805 | static bool intel_hpd_irq_event(struct drm_device *dev, |
806 | struct drm_connector *connector) | |
321a1b30 EE |
807 | { |
808 | enum drm_connector_status old_status; | |
809 | ||
810 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); | |
811 | old_status = connector->status; | |
812 | ||
813 | connector->status = connector->funcs->detect(connector, false); | |
67c347ff JN |
814 | if (old_status == connector->status) |
815 | return false; | |
816 | ||
817 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n", | |
321a1b30 | 818 | connector->base.id, |
c23cc417 | 819 | connector->name, |
67c347ff JN |
820 | drm_get_connector_status_name(old_status), |
821 | drm_get_connector_status_name(connector->status)); | |
822 | ||
823 | return true; | |
321a1b30 EE |
824 | } |
825 | ||
13cf5504 DA |
826 | static void i915_digport_work_func(struct work_struct *work) |
827 | { | |
828 | struct drm_i915_private *dev_priv = | |
829 | container_of(work, struct drm_i915_private, dig_port_work); | |
13cf5504 DA |
830 | u32 long_port_mask, short_port_mask; |
831 | struct intel_digital_port *intel_dig_port; | |
b2c5c181 | 832 | int i; |
13cf5504 DA |
833 | u32 old_bits = 0; |
834 | ||
4cb21832 | 835 | spin_lock_irq(&dev_priv->irq_lock); |
13cf5504 DA |
836 | long_port_mask = dev_priv->long_hpd_port_mask; |
837 | dev_priv->long_hpd_port_mask = 0; | |
838 | short_port_mask = dev_priv->short_hpd_port_mask; | |
839 | dev_priv->short_hpd_port_mask = 0; | |
4cb21832 | 840 | spin_unlock_irq(&dev_priv->irq_lock); |
13cf5504 DA |
841 | |
842 | for (i = 0; i < I915_MAX_PORTS; i++) { | |
843 | bool valid = false; | |
844 | bool long_hpd = false; | |
845 | intel_dig_port = dev_priv->hpd_irq_port[i]; | |
846 | if (!intel_dig_port || !intel_dig_port->hpd_pulse) | |
847 | continue; | |
848 | ||
849 | if (long_port_mask & (1 << i)) { | |
850 | valid = true; | |
851 | long_hpd = true; | |
852 | } else if (short_port_mask & (1 << i)) | |
853 | valid = true; | |
854 | ||
855 | if (valid) { | |
b2c5c181 DV |
856 | enum irqreturn ret; |
857 | ||
13cf5504 | 858 | ret = intel_dig_port->hpd_pulse(intel_dig_port, long_hpd); |
b2c5c181 DV |
859 | if (ret == IRQ_NONE) { |
860 | /* fall back to old school hpd */ | |
13cf5504 DA |
861 | old_bits |= (1 << intel_dig_port->base.hpd_pin); |
862 | } | |
863 | } | |
864 | } | |
865 | ||
866 | if (old_bits) { | |
4cb21832 | 867 | spin_lock_irq(&dev_priv->irq_lock); |
13cf5504 | 868 | dev_priv->hpd_event_bits |= old_bits; |
4cb21832 | 869 | spin_unlock_irq(&dev_priv->irq_lock); |
13cf5504 DA |
870 | schedule_work(&dev_priv->hotplug_work); |
871 | } | |
872 | } | |
873 | ||
5ca58282 JB |
874 | /* |
875 | * Handle hotplug events outside the interrupt handler proper. | |
876 | */ | |
ac4c16c5 EE |
877 | #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000) |
878 | ||
5ca58282 JB |
879 | static void i915_hotplug_work_func(struct work_struct *work) |
880 | { | |
2d1013dd JN |
881 | struct drm_i915_private *dev_priv = |
882 | container_of(work, struct drm_i915_private, hotplug_work); | |
5ca58282 | 883 | struct drm_device *dev = dev_priv->dev; |
c31c4ba3 | 884 | struct drm_mode_config *mode_config = &dev->mode_config; |
cd569aed EE |
885 | struct intel_connector *intel_connector; |
886 | struct intel_encoder *intel_encoder; | |
887 | struct drm_connector *connector; | |
cd569aed | 888 | bool hpd_disabled = false; |
321a1b30 | 889 | bool changed = false; |
142e2398 | 890 | u32 hpd_event_bits; |
4ef69c7a | 891 | |
a65e34c7 | 892 | mutex_lock(&mode_config->mutex); |
e67189ab JB |
893 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); |
894 | ||
4cb21832 | 895 | spin_lock_irq(&dev_priv->irq_lock); |
142e2398 EE |
896 | |
897 | hpd_event_bits = dev_priv->hpd_event_bits; | |
898 | dev_priv->hpd_event_bits = 0; | |
cd569aed EE |
899 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
900 | intel_connector = to_intel_connector(connector); | |
36cd7444 DA |
901 | if (!intel_connector->encoder) |
902 | continue; | |
cd569aed EE |
903 | intel_encoder = intel_connector->encoder; |
904 | if (intel_encoder->hpd_pin > HPD_NONE && | |
905 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED && | |
906 | connector->polled == DRM_CONNECTOR_POLL_HPD) { | |
907 | DRM_INFO("HPD interrupt storm detected on connector %s: " | |
908 | "switching from hotplug detection to polling\n", | |
c23cc417 | 909 | connector->name); |
cd569aed EE |
910 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED; |
911 | connector->polled = DRM_CONNECTOR_POLL_CONNECT | |
912 | | DRM_CONNECTOR_POLL_DISCONNECT; | |
913 | hpd_disabled = true; | |
914 | } | |
142e2398 EE |
915 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { |
916 | DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n", | |
c23cc417 | 917 | connector->name, intel_encoder->hpd_pin); |
142e2398 | 918 | } |
cd569aed EE |
919 | } |
920 | /* if there were no outputs to poll, poll was disabled, | |
921 | * therefore make sure it's enabled when disabling HPD on | |
922 | * some connectors */ | |
ac4c16c5 | 923 | if (hpd_disabled) { |
cd569aed | 924 | drm_kms_helper_poll_enable(dev); |
6323751d ID |
925 | mod_delayed_work(system_wq, &dev_priv->hotplug_reenable_work, |
926 | msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY)); | |
ac4c16c5 | 927 | } |
cd569aed | 928 | |
4cb21832 | 929 | spin_unlock_irq(&dev_priv->irq_lock); |
cd569aed | 930 | |
321a1b30 EE |
931 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
932 | intel_connector = to_intel_connector(connector); | |
36cd7444 DA |
933 | if (!intel_connector->encoder) |
934 | continue; | |
321a1b30 EE |
935 | intel_encoder = intel_connector->encoder; |
936 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { | |
937 | if (intel_encoder->hot_plug) | |
938 | intel_encoder->hot_plug(intel_encoder); | |
939 | if (intel_hpd_irq_event(dev, connector)) | |
940 | changed = true; | |
941 | } | |
942 | } | |
40ee3381 KP |
943 | mutex_unlock(&mode_config->mutex); |
944 | ||
321a1b30 EE |
945 | if (changed) |
946 | drm_kms_helper_hotplug_event(dev); | |
5ca58282 JB |
947 | } |
948 | ||
d0ecd7e2 | 949 | static void ironlake_rps_change_irq_handler(struct drm_device *dev) |
f97108d1 | 950 | { |
2d1013dd | 951 | struct drm_i915_private *dev_priv = dev->dev_private; |
b5b72e89 | 952 | u32 busy_up, busy_down, max_avg, min_avg; |
9270388e | 953 | u8 new_delay; |
9270388e | 954 | |
d0ecd7e2 | 955 | spin_lock(&mchdev_lock); |
f97108d1 | 956 | |
73edd18f DV |
957 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
958 | ||
20e4d407 | 959 | new_delay = dev_priv->ips.cur_delay; |
9270388e | 960 | |
7648fa99 | 961 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
962 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
963 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
964 | max_avg = I915_READ(RCBMAXAVG); |
965 | min_avg = I915_READ(RCBMINAVG); | |
966 | ||
967 | /* Handle RCS change request from hw */ | |
b5b72e89 | 968 | if (busy_up > max_avg) { |
20e4d407 DV |
969 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
970 | new_delay = dev_priv->ips.cur_delay - 1; | |
971 | if (new_delay < dev_priv->ips.max_delay) | |
972 | new_delay = dev_priv->ips.max_delay; | |
b5b72e89 | 973 | } else if (busy_down < min_avg) { |
20e4d407 DV |
974 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
975 | new_delay = dev_priv->ips.cur_delay + 1; | |
976 | if (new_delay > dev_priv->ips.min_delay) | |
977 | new_delay = dev_priv->ips.min_delay; | |
f97108d1 JB |
978 | } |
979 | ||
7648fa99 | 980 | if (ironlake_set_drps(dev, new_delay)) |
20e4d407 | 981 | dev_priv->ips.cur_delay = new_delay; |
f97108d1 | 982 | |
d0ecd7e2 | 983 | spin_unlock(&mchdev_lock); |
9270388e | 984 | |
f97108d1 JB |
985 | return; |
986 | } | |
987 | ||
549f7365 | 988 | static void notify_ring(struct drm_device *dev, |
a4872ba6 | 989 | struct intel_engine_cs *ring) |
549f7365 | 990 | { |
93b0a4e0 | 991 | if (!intel_ring_initialized(ring)) |
475553de CW |
992 | return; |
993 | ||
bcfcc8ba | 994 | trace_i915_gem_request_notify(ring); |
9862e600 | 995 | |
549f7365 | 996 | wake_up_all(&ring->irq_queue); |
549f7365 CW |
997 | } |
998 | ||
43cf3bf0 CW |
999 | static void vlv_c0_read(struct drm_i915_private *dev_priv, |
1000 | struct intel_rps_ei *ei) | |
31685c25 | 1001 | { |
43cf3bf0 CW |
1002 | ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP); |
1003 | ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT); | |
1004 | ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT); | |
1005 | } | |
31685c25 | 1006 | |
43cf3bf0 CW |
1007 | static bool vlv_c0_above(struct drm_i915_private *dev_priv, |
1008 | const struct intel_rps_ei *old, | |
1009 | const struct intel_rps_ei *now, | |
1010 | int threshold) | |
1011 | { | |
1012 | u64 time, c0; | |
31685c25 | 1013 | |
43cf3bf0 CW |
1014 | if (old->cz_clock == 0) |
1015 | return false; | |
31685c25 | 1016 | |
43cf3bf0 CW |
1017 | time = now->cz_clock - old->cz_clock; |
1018 | time *= threshold * dev_priv->mem_freq; | |
31685c25 | 1019 | |
43cf3bf0 CW |
1020 | /* Workload can be split between render + media, e.g. SwapBuffers |
1021 | * being blitted in X after being rendered in mesa. To account for | |
1022 | * this we need to combine both engines into our activity counter. | |
31685c25 | 1023 | */ |
43cf3bf0 CW |
1024 | c0 = now->render_c0 - old->render_c0; |
1025 | c0 += now->media_c0 - old->media_c0; | |
1026 | c0 *= 100 * VLV_CZ_CLOCK_TO_MILLI_SEC * 4 / 1000; | |
31685c25 | 1027 | |
43cf3bf0 | 1028 | return c0 >= time; |
31685c25 D |
1029 | } |
1030 | ||
43cf3bf0 | 1031 | void gen6_rps_reset_ei(struct drm_i915_private *dev_priv) |
31685c25 | 1032 | { |
43cf3bf0 CW |
1033 | vlv_c0_read(dev_priv, &dev_priv->rps.down_ei); |
1034 | dev_priv->rps.up_ei = dev_priv->rps.down_ei; | |
43cf3bf0 | 1035 | } |
31685c25 | 1036 | |
43cf3bf0 CW |
1037 | static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir) |
1038 | { | |
1039 | struct intel_rps_ei now; | |
1040 | u32 events = 0; | |
31685c25 | 1041 | |
6f4b12f8 | 1042 | if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0) |
43cf3bf0 | 1043 | return 0; |
31685c25 | 1044 | |
43cf3bf0 CW |
1045 | vlv_c0_read(dev_priv, &now); |
1046 | if (now.cz_clock == 0) | |
1047 | return 0; | |
31685c25 | 1048 | |
43cf3bf0 CW |
1049 | if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) { |
1050 | if (!vlv_c0_above(dev_priv, | |
1051 | &dev_priv->rps.down_ei, &now, | |
8fb55197 | 1052 | dev_priv->rps.down_threshold)) |
43cf3bf0 CW |
1053 | events |= GEN6_PM_RP_DOWN_THRESHOLD; |
1054 | dev_priv->rps.down_ei = now; | |
1055 | } | |
31685c25 | 1056 | |
43cf3bf0 CW |
1057 | if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) { |
1058 | if (vlv_c0_above(dev_priv, | |
1059 | &dev_priv->rps.up_ei, &now, | |
8fb55197 | 1060 | dev_priv->rps.up_threshold)) |
43cf3bf0 CW |
1061 | events |= GEN6_PM_RP_UP_THRESHOLD; |
1062 | dev_priv->rps.up_ei = now; | |
31685c25 D |
1063 | } |
1064 | ||
43cf3bf0 | 1065 | return events; |
31685c25 D |
1066 | } |
1067 | ||
4912d041 | 1068 | static void gen6_pm_rps_work(struct work_struct *work) |
3b8d8d91 | 1069 | { |
2d1013dd JN |
1070 | struct drm_i915_private *dev_priv = |
1071 | container_of(work, struct drm_i915_private, rps.work); | |
edbfdb45 | 1072 | u32 pm_iir; |
dd75fdc8 | 1073 | int new_delay, adj; |
4912d041 | 1074 | |
59cdb63d | 1075 | spin_lock_irq(&dev_priv->irq_lock); |
d4d70aa5 ID |
1076 | /* Speed up work cancelation during disabling rps interrupts. */ |
1077 | if (!dev_priv->rps.interrupts_enabled) { | |
1078 | spin_unlock_irq(&dev_priv->irq_lock); | |
1079 | return; | |
1080 | } | |
c6a828d3 DV |
1081 | pm_iir = dev_priv->rps.pm_iir; |
1082 | dev_priv->rps.pm_iir = 0; | |
a72fbc3a ID |
1083 | /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */ |
1084 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); | |
59cdb63d | 1085 | spin_unlock_irq(&dev_priv->irq_lock); |
3b8d8d91 | 1086 | |
60611c13 | 1087 | /* Make sure we didn't queue anything we're not going to process. */ |
a6706b45 | 1088 | WARN_ON(pm_iir & ~dev_priv->pm_rps_events); |
60611c13 | 1089 | |
a6706b45 | 1090 | if ((pm_iir & dev_priv->pm_rps_events) == 0) |
3b8d8d91 JB |
1091 | return; |
1092 | ||
4fc688ce | 1093 | mutex_lock(&dev_priv->rps.hw_lock); |
7b9e0ae6 | 1094 | |
43cf3bf0 CW |
1095 | pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir); |
1096 | ||
dd75fdc8 | 1097 | adj = dev_priv->rps.last_adj; |
edcf284b | 1098 | new_delay = dev_priv->rps.cur_freq; |
7425034a | 1099 | if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { |
dd75fdc8 CW |
1100 | if (adj > 0) |
1101 | adj *= 2; | |
edcf284b CW |
1102 | else /* CHV needs even encode values */ |
1103 | adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1; | |
7425034a VS |
1104 | /* |
1105 | * For better performance, jump directly | |
1106 | * to RPe if we're below it. | |
1107 | */ | |
edcf284b | 1108 | if (new_delay < dev_priv->rps.efficient_freq - adj) { |
b39fb297 | 1109 | new_delay = dev_priv->rps.efficient_freq; |
edcf284b CW |
1110 | adj = 0; |
1111 | } | |
dd75fdc8 | 1112 | } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { |
b39fb297 BW |
1113 | if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq) |
1114 | new_delay = dev_priv->rps.efficient_freq; | |
dd75fdc8 | 1115 | else |
b39fb297 | 1116 | new_delay = dev_priv->rps.min_freq_softlimit; |
dd75fdc8 CW |
1117 | adj = 0; |
1118 | } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { | |
1119 | if (adj < 0) | |
1120 | adj *= 2; | |
edcf284b CW |
1121 | else /* CHV needs even encode values */ |
1122 | adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1; | |
dd75fdc8 | 1123 | } else { /* unknown event */ |
edcf284b | 1124 | adj = 0; |
dd75fdc8 | 1125 | } |
3b8d8d91 | 1126 | |
edcf284b CW |
1127 | dev_priv->rps.last_adj = adj; |
1128 | ||
79249636 BW |
1129 | /* sysfs frequency interfaces may have snuck in while servicing the |
1130 | * interrupt | |
1131 | */ | |
edcf284b | 1132 | new_delay += adj; |
1272e7b8 | 1133 | new_delay = clamp_t(int, new_delay, |
b39fb297 BW |
1134 | dev_priv->rps.min_freq_softlimit, |
1135 | dev_priv->rps.max_freq_softlimit); | |
27544369 | 1136 | |
ffe02b40 | 1137 | intel_set_rps(dev_priv->dev, new_delay); |
3b8d8d91 | 1138 | |
4fc688ce | 1139 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 JB |
1140 | } |
1141 | ||
e3689190 BW |
1142 | |
1143 | /** | |
1144 | * ivybridge_parity_work - Workqueue called when a parity error interrupt | |
1145 | * occurred. | |
1146 | * @work: workqueue struct | |
1147 | * | |
1148 | * Doesn't actually do anything except notify userspace. As a consequence of | |
1149 | * this event, userspace should try to remap the bad rows since statistically | |
1150 | * it is likely the same row is more likely to go bad again. | |
1151 | */ | |
1152 | static void ivybridge_parity_work(struct work_struct *work) | |
1153 | { | |
2d1013dd JN |
1154 | struct drm_i915_private *dev_priv = |
1155 | container_of(work, struct drm_i915_private, l3_parity.error_work); | |
e3689190 | 1156 | u32 error_status, row, bank, subbank; |
35a85ac6 | 1157 | char *parity_event[6]; |
e3689190 | 1158 | uint32_t misccpctl; |
35a85ac6 | 1159 | uint8_t slice = 0; |
e3689190 BW |
1160 | |
1161 | /* We must turn off DOP level clock gating to access the L3 registers. | |
1162 | * In order to prevent a get/put style interface, acquire struct mutex | |
1163 | * any time we access those registers. | |
1164 | */ | |
1165 | mutex_lock(&dev_priv->dev->struct_mutex); | |
1166 | ||
35a85ac6 BW |
1167 | /* If we've screwed up tracking, just let the interrupt fire again */ |
1168 | if (WARN_ON(!dev_priv->l3_parity.which_slice)) | |
1169 | goto out; | |
1170 | ||
e3689190 BW |
1171 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
1172 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
1173 | POSTING_READ(GEN7_MISCCPCTL); | |
1174 | ||
35a85ac6 BW |
1175 | while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { |
1176 | u32 reg; | |
e3689190 | 1177 | |
35a85ac6 BW |
1178 | slice--; |
1179 | if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev))) | |
1180 | break; | |
e3689190 | 1181 | |
35a85ac6 | 1182 | dev_priv->l3_parity.which_slice &= ~(1<<slice); |
e3689190 | 1183 | |
35a85ac6 | 1184 | reg = GEN7_L3CDERRST1 + (slice * 0x200); |
e3689190 | 1185 | |
35a85ac6 BW |
1186 | error_status = I915_READ(reg); |
1187 | row = GEN7_PARITY_ERROR_ROW(error_status); | |
1188 | bank = GEN7_PARITY_ERROR_BANK(error_status); | |
1189 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); | |
1190 | ||
1191 | I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); | |
1192 | POSTING_READ(reg); | |
1193 | ||
1194 | parity_event[0] = I915_L3_PARITY_UEVENT "=1"; | |
1195 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); | |
1196 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); | |
1197 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); | |
1198 | parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); | |
1199 | parity_event[5] = NULL; | |
1200 | ||
5bdebb18 | 1201 | kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj, |
35a85ac6 | 1202 | KOBJ_CHANGE, parity_event); |
e3689190 | 1203 | |
35a85ac6 BW |
1204 | DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", |
1205 | slice, row, bank, subbank); | |
e3689190 | 1206 | |
35a85ac6 BW |
1207 | kfree(parity_event[4]); |
1208 | kfree(parity_event[3]); | |
1209 | kfree(parity_event[2]); | |
1210 | kfree(parity_event[1]); | |
1211 | } | |
e3689190 | 1212 | |
35a85ac6 | 1213 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
e3689190 | 1214 | |
35a85ac6 BW |
1215 | out: |
1216 | WARN_ON(dev_priv->l3_parity.which_slice); | |
4cb21832 | 1217 | spin_lock_irq(&dev_priv->irq_lock); |
480c8033 | 1218 | gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev)); |
4cb21832 | 1219 | spin_unlock_irq(&dev_priv->irq_lock); |
35a85ac6 BW |
1220 | |
1221 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
e3689190 BW |
1222 | } |
1223 | ||
35a85ac6 | 1224 | static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir) |
e3689190 | 1225 | { |
2d1013dd | 1226 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3689190 | 1227 | |
040d2baa | 1228 | if (!HAS_L3_DPF(dev)) |
e3689190 BW |
1229 | return; |
1230 | ||
d0ecd7e2 | 1231 | spin_lock(&dev_priv->irq_lock); |
480c8033 | 1232 | gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev)); |
d0ecd7e2 | 1233 | spin_unlock(&dev_priv->irq_lock); |
e3689190 | 1234 | |
35a85ac6 BW |
1235 | iir &= GT_PARITY_ERROR(dev); |
1236 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) | |
1237 | dev_priv->l3_parity.which_slice |= 1 << 1; | |
1238 | ||
1239 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) | |
1240 | dev_priv->l3_parity.which_slice |= 1 << 0; | |
1241 | ||
a4da4fa4 | 1242 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
e3689190 BW |
1243 | } |
1244 | ||
f1af8fc1 PZ |
1245 | static void ilk_gt_irq_handler(struct drm_device *dev, |
1246 | struct drm_i915_private *dev_priv, | |
1247 | u32 gt_iir) | |
1248 | { | |
1249 | if (gt_iir & | |
1250 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
1251 | notify_ring(dev, &dev_priv->ring[RCS]); | |
1252 | if (gt_iir & ILK_BSD_USER_INTERRUPT) | |
1253 | notify_ring(dev, &dev_priv->ring[VCS]); | |
1254 | } | |
1255 | ||
e7b4c6b1 DV |
1256 | static void snb_gt_irq_handler(struct drm_device *dev, |
1257 | struct drm_i915_private *dev_priv, | |
1258 | u32 gt_iir) | |
1259 | { | |
1260 | ||
cc609d5d BW |
1261 | if (gt_iir & |
1262 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
e7b4c6b1 | 1263 | notify_ring(dev, &dev_priv->ring[RCS]); |
cc609d5d | 1264 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
e7b4c6b1 | 1265 | notify_ring(dev, &dev_priv->ring[VCS]); |
cc609d5d | 1266 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
e7b4c6b1 DV |
1267 | notify_ring(dev, &dev_priv->ring[BCS]); |
1268 | ||
cc609d5d BW |
1269 | if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | |
1270 | GT_BSD_CS_ERROR_INTERRUPT | | |
aaecdf61 DV |
1271 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) |
1272 | DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir); | |
e3689190 | 1273 | |
35a85ac6 BW |
1274 | if (gt_iir & GT_PARITY_ERROR(dev)) |
1275 | ivybridge_parity_error_irq_handler(dev, gt_iir); | |
e7b4c6b1 DV |
1276 | } |
1277 | ||
abd58f01 BW |
1278 | static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev, |
1279 | struct drm_i915_private *dev_priv, | |
1280 | u32 master_ctl) | |
1281 | { | |
e981e7b1 | 1282 | struct intel_engine_cs *ring; |
abd58f01 BW |
1283 | u32 rcs, bcs, vcs; |
1284 | uint32_t tmp = 0; | |
1285 | irqreturn_t ret = IRQ_NONE; | |
1286 | ||
1287 | if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { | |
cb0d205e | 1288 | tmp = I915_READ_FW(GEN8_GT_IIR(0)); |
abd58f01 | 1289 | if (tmp) { |
cb0d205e | 1290 | I915_WRITE_FW(GEN8_GT_IIR(0), tmp); |
abd58f01 | 1291 | ret = IRQ_HANDLED; |
e981e7b1 | 1292 | |
abd58f01 | 1293 | rcs = tmp >> GEN8_RCS_IRQ_SHIFT; |
e981e7b1 | 1294 | ring = &dev_priv->ring[RCS]; |
e981e7b1 | 1295 | if (rcs & GT_CONTEXT_SWITCH_INTERRUPT) |
3f7531c3 | 1296 | intel_lrc_irq_handler(ring); |
cb0d205e CW |
1297 | if (rcs & GT_RENDER_USER_INTERRUPT) |
1298 | notify_ring(dev, ring); | |
e981e7b1 TD |
1299 | |
1300 | bcs = tmp >> GEN8_BCS_IRQ_SHIFT; | |
1301 | ring = &dev_priv->ring[BCS]; | |
e981e7b1 | 1302 | if (bcs & GT_CONTEXT_SWITCH_INTERRUPT) |
3f7531c3 | 1303 | intel_lrc_irq_handler(ring); |
cb0d205e CW |
1304 | if (bcs & GT_RENDER_USER_INTERRUPT) |
1305 | notify_ring(dev, ring); | |
abd58f01 BW |
1306 | } else |
1307 | DRM_ERROR("The master control interrupt lied (GT0)!\n"); | |
1308 | } | |
1309 | ||
85f9b5f9 | 1310 | if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) { |
cb0d205e | 1311 | tmp = I915_READ_FW(GEN8_GT_IIR(1)); |
abd58f01 | 1312 | if (tmp) { |
cb0d205e | 1313 | I915_WRITE_FW(GEN8_GT_IIR(1), tmp); |
abd58f01 | 1314 | ret = IRQ_HANDLED; |
e981e7b1 | 1315 | |
abd58f01 | 1316 | vcs = tmp >> GEN8_VCS1_IRQ_SHIFT; |
e981e7b1 | 1317 | ring = &dev_priv->ring[VCS]; |
73d477f6 | 1318 | if (vcs & GT_CONTEXT_SWITCH_INTERRUPT) |
3f7531c3 | 1319 | intel_lrc_irq_handler(ring); |
cb0d205e CW |
1320 | if (vcs & GT_RENDER_USER_INTERRUPT) |
1321 | notify_ring(dev, ring); | |
e981e7b1 | 1322 | |
85f9b5f9 | 1323 | vcs = tmp >> GEN8_VCS2_IRQ_SHIFT; |
e981e7b1 | 1324 | ring = &dev_priv->ring[VCS2]; |
73d477f6 | 1325 | if (vcs & GT_CONTEXT_SWITCH_INTERRUPT) |
3f7531c3 | 1326 | intel_lrc_irq_handler(ring); |
cb0d205e CW |
1327 | if (vcs & GT_RENDER_USER_INTERRUPT) |
1328 | notify_ring(dev, ring); | |
abd58f01 BW |
1329 | } else |
1330 | DRM_ERROR("The master control interrupt lied (GT1)!\n"); | |
1331 | } | |
1332 | ||
0961021a | 1333 | if (master_ctl & GEN8_GT_PM_IRQ) { |
cb0d205e | 1334 | tmp = I915_READ_FW(GEN8_GT_IIR(2)); |
0961021a | 1335 | if (tmp & dev_priv->pm_rps_events) { |
cb0d205e CW |
1336 | I915_WRITE_FW(GEN8_GT_IIR(2), |
1337 | tmp & dev_priv->pm_rps_events); | |
38cc46d7 | 1338 | ret = IRQ_HANDLED; |
c9a9a268 | 1339 | gen6_rps_irq_handler(dev_priv, tmp); |
0961021a BW |
1340 | } else |
1341 | DRM_ERROR("The master control interrupt lied (PM)!\n"); | |
1342 | } | |
1343 | ||
abd58f01 | 1344 | if (master_ctl & GEN8_GT_VECS_IRQ) { |
cb0d205e | 1345 | tmp = I915_READ_FW(GEN8_GT_IIR(3)); |
abd58f01 | 1346 | if (tmp) { |
cb0d205e | 1347 | I915_WRITE_FW(GEN8_GT_IIR(3), tmp); |
abd58f01 | 1348 | ret = IRQ_HANDLED; |
e981e7b1 | 1349 | |
abd58f01 | 1350 | vcs = tmp >> GEN8_VECS_IRQ_SHIFT; |
e981e7b1 | 1351 | ring = &dev_priv->ring[VECS]; |
73d477f6 | 1352 | if (vcs & GT_CONTEXT_SWITCH_INTERRUPT) |
3f7531c3 | 1353 | intel_lrc_irq_handler(ring); |
cb0d205e CW |
1354 | if (vcs & GT_RENDER_USER_INTERRUPT) |
1355 | notify_ring(dev, ring); | |
abd58f01 BW |
1356 | } else |
1357 | DRM_ERROR("The master control interrupt lied (GT3)!\n"); | |
1358 | } | |
1359 | ||
1360 | return ret; | |
1361 | } | |
1362 | ||
b543fb04 EE |
1363 | #define HPD_STORM_DETECT_PERIOD 1000 |
1364 | #define HPD_STORM_THRESHOLD 5 | |
1365 | ||
07c338ce | 1366 | static int pch_port_to_hotplug_shift(enum port port) |
13cf5504 DA |
1367 | { |
1368 | switch (port) { | |
1369 | case PORT_A: | |
1370 | case PORT_E: | |
1371 | default: | |
1372 | return -1; | |
1373 | case PORT_B: | |
1374 | return 0; | |
1375 | case PORT_C: | |
1376 | return 8; | |
1377 | case PORT_D: | |
1378 | return 16; | |
1379 | } | |
1380 | } | |
1381 | ||
07c338ce | 1382 | static int i915_port_to_hotplug_shift(enum port port) |
13cf5504 DA |
1383 | { |
1384 | switch (port) { | |
1385 | case PORT_A: | |
1386 | case PORT_E: | |
1387 | default: | |
1388 | return -1; | |
1389 | case PORT_B: | |
1390 | return 17; | |
1391 | case PORT_C: | |
1392 | return 19; | |
1393 | case PORT_D: | |
1394 | return 21; | |
1395 | } | |
1396 | } | |
1397 | ||
1398 | static inline enum port get_port_from_pin(enum hpd_pin pin) | |
1399 | { | |
1400 | switch (pin) { | |
1401 | case HPD_PORT_B: | |
1402 | return PORT_B; | |
1403 | case HPD_PORT_C: | |
1404 | return PORT_C; | |
1405 | case HPD_PORT_D: | |
1406 | return PORT_D; | |
1407 | default: | |
1408 | return PORT_A; /* no hpd */ | |
1409 | } | |
1410 | } | |
1411 | ||
10a504de | 1412 | static inline void intel_hpd_irq_handler(struct drm_device *dev, |
22062dba | 1413 | u32 hotplug_trigger, |
13cf5504 | 1414 | u32 dig_hotplug_reg, |
7c7e10db | 1415 | const u32 hpd[HPD_NUM_PINS]) |
b543fb04 | 1416 | { |
2d1013dd | 1417 | struct drm_i915_private *dev_priv = dev->dev_private; |
b543fb04 | 1418 | int i; |
13cf5504 | 1419 | enum port port; |
10a504de | 1420 | bool storm_detected = false; |
13cf5504 DA |
1421 | bool queue_dig = false, queue_hp = false; |
1422 | u32 dig_shift; | |
1423 | u32 dig_port_mask = 0; | |
b543fb04 | 1424 | |
91d131d2 DV |
1425 | if (!hotplug_trigger) |
1426 | return; | |
1427 | ||
13cf5504 DA |
1428 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x\n", |
1429 | hotplug_trigger, dig_hotplug_reg); | |
cc9bd499 | 1430 | |
b5ea2d56 | 1431 | spin_lock(&dev_priv->irq_lock); |
b543fb04 | 1432 | for (i = 1; i < HPD_NUM_PINS; i++) { |
13cf5504 DA |
1433 | if (!(hpd[i] & hotplug_trigger)) |
1434 | continue; | |
1435 | ||
1436 | port = get_port_from_pin(i); | |
1437 | if (port && dev_priv->hpd_irq_port[port]) { | |
1438 | bool long_hpd; | |
1439 | ||
07c338ce JN |
1440 | if (HAS_PCH_SPLIT(dev)) { |
1441 | dig_shift = pch_port_to_hotplug_shift(port); | |
13cf5504 | 1442 | long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT; |
07c338ce JN |
1443 | } else { |
1444 | dig_shift = i915_port_to_hotplug_shift(port); | |
1445 | long_hpd = (hotplug_trigger >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT; | |
13cf5504 DA |
1446 | } |
1447 | ||
26fbb774 VS |
1448 | DRM_DEBUG_DRIVER("digital hpd port %c - %s\n", |
1449 | port_name(port), | |
1450 | long_hpd ? "long" : "short"); | |
13cf5504 DA |
1451 | /* for long HPD pulses we want to have the digital queue happen, |
1452 | but we still want HPD storm detection to function. */ | |
1453 | if (long_hpd) { | |
1454 | dev_priv->long_hpd_port_mask |= (1 << port); | |
1455 | dig_port_mask |= hpd[i]; | |
1456 | } else { | |
1457 | /* for short HPD just trigger the digital queue */ | |
1458 | dev_priv->short_hpd_port_mask |= (1 << port); | |
1459 | hotplug_trigger &= ~hpd[i]; | |
1460 | } | |
1461 | queue_dig = true; | |
1462 | } | |
1463 | } | |
821450c6 | 1464 | |
13cf5504 | 1465 | for (i = 1; i < HPD_NUM_PINS; i++) { |
3ff04a16 DV |
1466 | if (hpd[i] & hotplug_trigger && |
1467 | dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) { | |
1468 | /* | |
1469 | * On GMCH platforms the interrupt mask bits only | |
1470 | * prevent irq generation, not the setting of the | |
1471 | * hotplug bits itself. So only WARN about unexpected | |
1472 | * interrupts on saner platforms. | |
1473 | */ | |
1474 | WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev), | |
1475 | "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n", | |
1476 | hotplug_trigger, i, hpd[i]); | |
1477 | ||
1478 | continue; | |
1479 | } | |
b8f102e8 | 1480 | |
b543fb04 EE |
1481 | if (!(hpd[i] & hotplug_trigger) || |
1482 | dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED) | |
1483 | continue; | |
1484 | ||
13cf5504 DA |
1485 | if (!(dig_port_mask & hpd[i])) { |
1486 | dev_priv->hpd_event_bits |= (1 << i); | |
1487 | queue_hp = true; | |
1488 | } | |
1489 | ||
b543fb04 EE |
1490 | if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies, |
1491 | dev_priv->hpd_stats[i].hpd_last_jiffies | |
1492 | + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) { | |
1493 | dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies; | |
1494 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
b8f102e8 | 1495 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i); |
b543fb04 EE |
1496 | } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) { |
1497 | dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED; | |
142e2398 | 1498 | dev_priv->hpd_event_bits &= ~(1 << i); |
b543fb04 | 1499 | DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i); |
10a504de | 1500 | storm_detected = true; |
b543fb04 EE |
1501 | } else { |
1502 | dev_priv->hpd_stats[i].hpd_cnt++; | |
b8f102e8 EE |
1503 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i, |
1504 | dev_priv->hpd_stats[i].hpd_cnt); | |
b543fb04 EE |
1505 | } |
1506 | } | |
1507 | ||
10a504de DV |
1508 | if (storm_detected) |
1509 | dev_priv->display.hpd_irq_setup(dev); | |
b5ea2d56 | 1510 | spin_unlock(&dev_priv->irq_lock); |
5876fa0d | 1511 | |
645416f5 DV |
1512 | /* |
1513 | * Our hotplug handler can grab modeset locks (by calling down into the | |
1514 | * fb helpers). Hence it must not be run on our own dev-priv->wq work | |
1515 | * queue for otherwise the flush_work in the pageflip code will | |
1516 | * deadlock. | |
1517 | */ | |
13cf5504 | 1518 | if (queue_dig) |
0e32b39c | 1519 | queue_work(dev_priv->dp_wq, &dev_priv->dig_port_work); |
13cf5504 DA |
1520 | if (queue_hp) |
1521 | schedule_work(&dev_priv->hotplug_work); | |
b543fb04 EE |
1522 | } |
1523 | ||
515ac2bb DV |
1524 | static void gmbus_irq_handler(struct drm_device *dev) |
1525 | { | |
2d1013dd | 1526 | struct drm_i915_private *dev_priv = dev->dev_private; |
28c70f16 | 1527 | |
28c70f16 | 1528 | wake_up_all(&dev_priv->gmbus_wait_queue); |
515ac2bb DV |
1529 | } |
1530 | ||
ce99c256 DV |
1531 | static void dp_aux_irq_handler(struct drm_device *dev) |
1532 | { | |
2d1013dd | 1533 | struct drm_i915_private *dev_priv = dev->dev_private; |
9ee32fea | 1534 | |
9ee32fea | 1535 | wake_up_all(&dev_priv->gmbus_wait_queue); |
ce99c256 DV |
1536 | } |
1537 | ||
8bf1e9f1 | 1538 | #if defined(CONFIG_DEBUG_FS) |
277de95e DV |
1539 | static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, |
1540 | uint32_t crc0, uint32_t crc1, | |
1541 | uint32_t crc2, uint32_t crc3, | |
1542 | uint32_t crc4) | |
8bf1e9f1 SH |
1543 | { |
1544 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1545 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; | |
1546 | struct intel_pipe_crc_entry *entry; | |
ac2300d4 | 1547 | int head, tail; |
b2c88f5b | 1548 | |
d538bbdf DL |
1549 | spin_lock(&pipe_crc->lock); |
1550 | ||
0c912c79 | 1551 | if (!pipe_crc->entries) { |
d538bbdf | 1552 | spin_unlock(&pipe_crc->lock); |
34273620 | 1553 | DRM_DEBUG_KMS("spurious interrupt\n"); |
0c912c79 DL |
1554 | return; |
1555 | } | |
1556 | ||
d538bbdf DL |
1557 | head = pipe_crc->head; |
1558 | tail = pipe_crc->tail; | |
b2c88f5b DL |
1559 | |
1560 | if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { | |
d538bbdf | 1561 | spin_unlock(&pipe_crc->lock); |
b2c88f5b DL |
1562 | DRM_ERROR("CRC buffer overflowing\n"); |
1563 | return; | |
1564 | } | |
1565 | ||
1566 | entry = &pipe_crc->entries[head]; | |
8bf1e9f1 | 1567 | |
8bc5e955 | 1568 | entry->frame = dev->driver->get_vblank_counter(dev, pipe); |
eba94eb9 DV |
1569 | entry->crc[0] = crc0; |
1570 | entry->crc[1] = crc1; | |
1571 | entry->crc[2] = crc2; | |
1572 | entry->crc[3] = crc3; | |
1573 | entry->crc[4] = crc4; | |
b2c88f5b DL |
1574 | |
1575 | head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
d538bbdf DL |
1576 | pipe_crc->head = head; |
1577 | ||
1578 | spin_unlock(&pipe_crc->lock); | |
07144428 DL |
1579 | |
1580 | wake_up_interruptible(&pipe_crc->wq); | |
8bf1e9f1 | 1581 | } |
277de95e DV |
1582 | #else |
1583 | static inline void | |
1584 | display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, | |
1585 | uint32_t crc0, uint32_t crc1, | |
1586 | uint32_t crc2, uint32_t crc3, | |
1587 | uint32_t crc4) {} | |
1588 | #endif | |
1589 | ||
eba94eb9 | 1590 | |
277de95e | 1591 | static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5a69b89f DV |
1592 | { |
1593 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1594 | ||
277de95e DV |
1595 | display_pipe_crc_irq_handler(dev, pipe, |
1596 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1597 | 0, 0, 0, 0); | |
5a69b89f DV |
1598 | } |
1599 | ||
277de95e | 1600 | static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
eba94eb9 DV |
1601 | { |
1602 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1603 | ||
277de95e DV |
1604 | display_pipe_crc_irq_handler(dev, pipe, |
1605 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1606 | I915_READ(PIPE_CRC_RES_2_IVB(pipe)), | |
1607 | I915_READ(PIPE_CRC_RES_3_IVB(pipe)), | |
1608 | I915_READ(PIPE_CRC_RES_4_IVB(pipe)), | |
1609 | I915_READ(PIPE_CRC_RES_5_IVB(pipe))); | |
eba94eb9 | 1610 | } |
5b3a856b | 1611 | |
277de95e | 1612 | static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5b3a856b DV |
1613 | { |
1614 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0b5c5ed0 DV |
1615 | uint32_t res1, res2; |
1616 | ||
1617 | if (INTEL_INFO(dev)->gen >= 3) | |
1618 | res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); | |
1619 | else | |
1620 | res1 = 0; | |
1621 | ||
1622 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
1623 | res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); | |
1624 | else | |
1625 | res2 = 0; | |
5b3a856b | 1626 | |
277de95e DV |
1627 | display_pipe_crc_irq_handler(dev, pipe, |
1628 | I915_READ(PIPE_CRC_RES_RED(pipe)), | |
1629 | I915_READ(PIPE_CRC_RES_GREEN(pipe)), | |
1630 | I915_READ(PIPE_CRC_RES_BLUE(pipe)), | |
1631 | res1, res2); | |
5b3a856b | 1632 | } |
8bf1e9f1 | 1633 | |
1403c0d4 PZ |
1634 | /* The RPS events need forcewake, so we add them to a work queue and mask their |
1635 | * IMR bits until the work is done. Other interrupts can be processed without | |
1636 | * the work queue. */ | |
1637 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) | |
baf02a1f | 1638 | { |
a6706b45 | 1639 | if (pm_iir & dev_priv->pm_rps_events) { |
59cdb63d | 1640 | spin_lock(&dev_priv->irq_lock); |
480c8033 | 1641 | gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); |
d4d70aa5 ID |
1642 | if (dev_priv->rps.interrupts_enabled) { |
1643 | dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; | |
1644 | queue_work(dev_priv->wq, &dev_priv->rps.work); | |
1645 | } | |
59cdb63d | 1646 | spin_unlock(&dev_priv->irq_lock); |
baf02a1f | 1647 | } |
baf02a1f | 1648 | |
c9a9a268 ID |
1649 | if (INTEL_INFO(dev_priv)->gen >= 8) |
1650 | return; | |
1651 | ||
1403c0d4 PZ |
1652 | if (HAS_VEBOX(dev_priv->dev)) { |
1653 | if (pm_iir & PM_VEBOX_USER_INTERRUPT) | |
1654 | notify_ring(dev_priv->dev, &dev_priv->ring[VECS]); | |
12638c57 | 1655 | |
aaecdf61 DV |
1656 | if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) |
1657 | DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir); | |
12638c57 | 1658 | } |
baf02a1f BW |
1659 | } |
1660 | ||
8d7849db VS |
1661 | static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe) |
1662 | { | |
8d7849db VS |
1663 | if (!drm_handle_vblank(dev, pipe)) |
1664 | return false; | |
1665 | ||
8d7849db VS |
1666 | return true; |
1667 | } | |
1668 | ||
c1874ed7 ID |
1669 | static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir) |
1670 | { | |
1671 | struct drm_i915_private *dev_priv = dev->dev_private; | |
91d181dd | 1672 | u32 pipe_stats[I915_MAX_PIPES] = { }; |
c1874ed7 ID |
1673 | int pipe; |
1674 | ||
58ead0d7 | 1675 | spin_lock(&dev_priv->irq_lock); |
055e393f | 1676 | for_each_pipe(dev_priv, pipe) { |
91d181dd | 1677 | int reg; |
bbb5eebf | 1678 | u32 mask, iir_bit = 0; |
91d181dd | 1679 | |
bbb5eebf DV |
1680 | /* |
1681 | * PIPESTAT bits get signalled even when the interrupt is | |
1682 | * disabled with the mask bits, and some of the status bits do | |
1683 | * not generate interrupts at all (like the underrun bit). Hence | |
1684 | * we need to be careful that we only handle what we want to | |
1685 | * handle. | |
1686 | */ | |
0f239f4c DV |
1687 | |
1688 | /* fifo underruns are filterered in the underrun handler. */ | |
1689 | mask = PIPE_FIFO_UNDERRUN_STATUS; | |
bbb5eebf DV |
1690 | |
1691 | switch (pipe) { | |
1692 | case PIPE_A: | |
1693 | iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; | |
1694 | break; | |
1695 | case PIPE_B: | |
1696 | iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
1697 | break; | |
3278f67f VS |
1698 | case PIPE_C: |
1699 | iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
1700 | break; | |
bbb5eebf DV |
1701 | } |
1702 | if (iir & iir_bit) | |
1703 | mask |= dev_priv->pipestat_irq_mask[pipe]; | |
1704 | ||
1705 | if (!mask) | |
91d181dd ID |
1706 | continue; |
1707 | ||
1708 | reg = PIPESTAT(pipe); | |
bbb5eebf DV |
1709 | mask |= PIPESTAT_INT_ENABLE_MASK; |
1710 | pipe_stats[pipe] = I915_READ(reg) & mask; | |
c1874ed7 ID |
1711 | |
1712 | /* | |
1713 | * Clear the PIPE*STAT regs before the IIR | |
1714 | */ | |
91d181dd ID |
1715 | if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS | |
1716 | PIPESTAT_INT_STATUS_MASK)) | |
c1874ed7 ID |
1717 | I915_WRITE(reg, pipe_stats[pipe]); |
1718 | } | |
58ead0d7 | 1719 | spin_unlock(&dev_priv->irq_lock); |
c1874ed7 | 1720 | |
055e393f | 1721 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
1722 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
1723 | intel_pipe_handle_vblank(dev, pipe)) | |
1724 | intel_check_page_flip(dev, pipe); | |
c1874ed7 | 1725 | |
579a9b0e | 1726 | if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) { |
c1874ed7 ID |
1727 | intel_prepare_page_flip(dev, pipe); |
1728 | intel_finish_page_flip(dev, pipe); | |
1729 | } | |
1730 | ||
1731 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
1732 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
1733 | ||
1f7247c0 DV |
1734 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
1735 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
c1874ed7 ID |
1736 | } |
1737 | ||
1738 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) | |
1739 | gmbus_irq_handler(dev); | |
1740 | } | |
1741 | ||
16c6c56b VS |
1742 | static void i9xx_hpd_irq_handler(struct drm_device *dev) |
1743 | { | |
1744 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1745 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
1746 | ||
3ff60f89 OM |
1747 | if (hotplug_status) { |
1748 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
1749 | /* | |
1750 | * Make sure hotplug status is cleared before we clear IIR, or else we | |
1751 | * may miss hotplug events. | |
1752 | */ | |
1753 | POSTING_READ(PORT_HOTPLUG_STAT); | |
16c6c56b | 1754 | |
3ff60f89 OM |
1755 | if (IS_G4X(dev)) { |
1756 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; | |
16c6c56b | 1757 | |
13cf5504 | 1758 | intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_g4x); |
3ff60f89 OM |
1759 | } else { |
1760 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; | |
16c6c56b | 1761 | |
13cf5504 | 1762 | intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_i915); |
3ff60f89 | 1763 | } |
16c6c56b | 1764 | |
3ff60f89 OM |
1765 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && |
1766 | hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) | |
1767 | dp_aux_irq_handler(dev); | |
1768 | } | |
16c6c56b VS |
1769 | } |
1770 | ||
ff1f525e | 1771 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
7e231dbe | 1772 | { |
45a83f84 | 1773 | struct drm_device *dev = arg; |
2d1013dd | 1774 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
1775 | u32 iir, gt_iir, pm_iir; |
1776 | irqreturn_t ret = IRQ_NONE; | |
7e231dbe | 1777 | |
2dd2a883 ID |
1778 | if (!intel_irqs_enabled(dev_priv)) |
1779 | return IRQ_NONE; | |
1780 | ||
7e231dbe | 1781 | while (true) { |
3ff60f89 OM |
1782 | /* Find, clear, then process each source of interrupt */ |
1783 | ||
7e231dbe | 1784 | gt_iir = I915_READ(GTIIR); |
3ff60f89 OM |
1785 | if (gt_iir) |
1786 | I915_WRITE(GTIIR, gt_iir); | |
1787 | ||
7e231dbe | 1788 | pm_iir = I915_READ(GEN6_PMIIR); |
3ff60f89 OM |
1789 | if (pm_iir) |
1790 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
1791 | ||
1792 | iir = I915_READ(VLV_IIR); | |
1793 | if (iir) { | |
1794 | /* Consume port before clearing IIR or we'll miss events */ | |
1795 | if (iir & I915_DISPLAY_PORT_INTERRUPT) | |
1796 | i9xx_hpd_irq_handler(dev); | |
1797 | I915_WRITE(VLV_IIR, iir); | |
1798 | } | |
7e231dbe JB |
1799 | |
1800 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) | |
1801 | goto out; | |
1802 | ||
1803 | ret = IRQ_HANDLED; | |
1804 | ||
3ff60f89 OM |
1805 | if (gt_iir) |
1806 | snb_gt_irq_handler(dev, dev_priv, gt_iir); | |
60611c13 | 1807 | if (pm_iir) |
d0ecd7e2 | 1808 | gen6_rps_irq_handler(dev_priv, pm_iir); |
3ff60f89 OM |
1809 | /* Call regardless, as some status bits might not be |
1810 | * signalled in iir */ | |
1811 | valleyview_pipestat_irq_handler(dev, iir); | |
7e231dbe JB |
1812 | } |
1813 | ||
1814 | out: | |
1815 | return ret; | |
1816 | } | |
1817 | ||
43f328d7 VS |
1818 | static irqreturn_t cherryview_irq_handler(int irq, void *arg) |
1819 | { | |
45a83f84 | 1820 | struct drm_device *dev = arg; |
43f328d7 VS |
1821 | struct drm_i915_private *dev_priv = dev->dev_private; |
1822 | u32 master_ctl, iir; | |
1823 | irqreturn_t ret = IRQ_NONE; | |
43f328d7 | 1824 | |
2dd2a883 ID |
1825 | if (!intel_irqs_enabled(dev_priv)) |
1826 | return IRQ_NONE; | |
1827 | ||
8e5fd599 VS |
1828 | for (;;) { |
1829 | master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; | |
1830 | iir = I915_READ(VLV_IIR); | |
43f328d7 | 1831 | |
8e5fd599 VS |
1832 | if (master_ctl == 0 && iir == 0) |
1833 | break; | |
43f328d7 | 1834 | |
27b6c122 OM |
1835 | ret = IRQ_HANDLED; |
1836 | ||
8e5fd599 | 1837 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
43f328d7 | 1838 | |
27b6c122 | 1839 | /* Find, clear, then process each source of interrupt */ |
43f328d7 | 1840 | |
27b6c122 OM |
1841 | if (iir) { |
1842 | /* Consume port before clearing IIR or we'll miss events */ | |
1843 | if (iir & I915_DISPLAY_PORT_INTERRUPT) | |
1844 | i9xx_hpd_irq_handler(dev); | |
1845 | I915_WRITE(VLV_IIR, iir); | |
1846 | } | |
43f328d7 | 1847 | |
27b6c122 | 1848 | gen8_gt_irq_handler(dev, dev_priv, master_ctl); |
43f328d7 | 1849 | |
27b6c122 OM |
1850 | /* Call regardless, as some status bits might not be |
1851 | * signalled in iir */ | |
1852 | valleyview_pipestat_irq_handler(dev, iir); | |
43f328d7 | 1853 | |
8e5fd599 VS |
1854 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); |
1855 | POSTING_READ(GEN8_MASTER_IRQ); | |
8e5fd599 | 1856 | } |
3278f67f | 1857 | |
43f328d7 VS |
1858 | return ret; |
1859 | } | |
1860 | ||
23e81d69 | 1861 | static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) |
776ad806 | 1862 | { |
2d1013dd | 1863 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 1864 | int pipe; |
b543fb04 | 1865 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; |
13cf5504 DA |
1866 | u32 dig_hotplug_reg; |
1867 | ||
1868 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); | |
1869 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
776ad806 | 1870 | |
13cf5504 | 1871 | intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_ibx); |
91d131d2 | 1872 | |
cfc33bf7 VS |
1873 | if (pch_iir & SDE_AUDIO_POWER_MASK) { |
1874 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> | |
1875 | SDE_AUDIO_POWER_SHIFT); | |
776ad806 | 1876 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
cfc33bf7 VS |
1877 | port_name(port)); |
1878 | } | |
776ad806 | 1879 | |
ce99c256 DV |
1880 | if (pch_iir & SDE_AUX_MASK) |
1881 | dp_aux_irq_handler(dev); | |
1882 | ||
776ad806 | 1883 | if (pch_iir & SDE_GMBUS) |
515ac2bb | 1884 | gmbus_irq_handler(dev); |
776ad806 JB |
1885 | |
1886 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
1887 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
1888 | ||
1889 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
1890 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
1891 | ||
1892 | if (pch_iir & SDE_POISON) | |
1893 | DRM_ERROR("PCH poison interrupt\n"); | |
1894 | ||
9db4a9c7 | 1895 | if (pch_iir & SDE_FDI_MASK) |
055e393f | 1896 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
1897 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
1898 | pipe_name(pipe), | |
1899 | I915_READ(FDI_RX_IIR(pipe))); | |
776ad806 JB |
1900 | |
1901 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
1902 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
1903 | ||
1904 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
1905 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
1906 | ||
776ad806 | 1907 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
1f7247c0 | 1908 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); |
8664281b PZ |
1909 | |
1910 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
1f7247c0 | 1911 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); |
8664281b PZ |
1912 | } |
1913 | ||
1914 | static void ivb_err_int_handler(struct drm_device *dev) | |
1915 | { | |
1916 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1917 | u32 err_int = I915_READ(GEN7_ERR_INT); | |
5a69b89f | 1918 | enum pipe pipe; |
8664281b | 1919 | |
de032bf4 PZ |
1920 | if (err_int & ERR_INT_POISON) |
1921 | DRM_ERROR("Poison interrupt\n"); | |
1922 | ||
055e393f | 1923 | for_each_pipe(dev_priv, pipe) { |
1f7247c0 DV |
1924 | if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) |
1925 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
8bf1e9f1 | 1926 | |
5a69b89f DV |
1927 | if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { |
1928 | if (IS_IVYBRIDGE(dev)) | |
277de95e | 1929 | ivb_pipe_crc_irq_handler(dev, pipe); |
5a69b89f | 1930 | else |
277de95e | 1931 | hsw_pipe_crc_irq_handler(dev, pipe); |
5a69b89f DV |
1932 | } |
1933 | } | |
8bf1e9f1 | 1934 | |
8664281b PZ |
1935 | I915_WRITE(GEN7_ERR_INT, err_int); |
1936 | } | |
1937 | ||
1938 | static void cpt_serr_int_handler(struct drm_device *dev) | |
1939 | { | |
1940 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1941 | u32 serr_int = I915_READ(SERR_INT); | |
1942 | ||
de032bf4 PZ |
1943 | if (serr_int & SERR_INT_POISON) |
1944 | DRM_ERROR("PCH poison interrupt\n"); | |
1945 | ||
8664281b | 1946 | if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) |
1f7247c0 | 1947 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); |
8664281b PZ |
1948 | |
1949 | if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) | |
1f7247c0 | 1950 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); |
8664281b PZ |
1951 | |
1952 | if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) | |
1f7247c0 | 1953 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C); |
8664281b PZ |
1954 | |
1955 | I915_WRITE(SERR_INT, serr_int); | |
776ad806 JB |
1956 | } |
1957 | ||
23e81d69 AJ |
1958 | static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) |
1959 | { | |
2d1013dd | 1960 | struct drm_i915_private *dev_priv = dev->dev_private; |
23e81d69 | 1961 | int pipe; |
b543fb04 | 1962 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; |
13cf5504 DA |
1963 | u32 dig_hotplug_reg; |
1964 | ||
1965 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); | |
1966 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
23e81d69 | 1967 | |
13cf5504 | 1968 | intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_cpt); |
91d131d2 | 1969 | |
cfc33bf7 VS |
1970 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { |
1971 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> | |
1972 | SDE_AUDIO_POWER_SHIFT_CPT); | |
1973 | DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", | |
1974 | port_name(port)); | |
1975 | } | |
23e81d69 AJ |
1976 | |
1977 | if (pch_iir & SDE_AUX_MASK_CPT) | |
ce99c256 | 1978 | dp_aux_irq_handler(dev); |
23e81d69 AJ |
1979 | |
1980 | if (pch_iir & SDE_GMBUS_CPT) | |
515ac2bb | 1981 | gmbus_irq_handler(dev); |
23e81d69 AJ |
1982 | |
1983 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) | |
1984 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); | |
1985 | ||
1986 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) | |
1987 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); | |
1988 | ||
1989 | if (pch_iir & SDE_FDI_MASK_CPT) | |
055e393f | 1990 | for_each_pipe(dev_priv, pipe) |
23e81d69 AJ |
1991 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
1992 | pipe_name(pipe), | |
1993 | I915_READ(FDI_RX_IIR(pipe))); | |
8664281b PZ |
1994 | |
1995 | if (pch_iir & SDE_ERROR_CPT) | |
1996 | cpt_serr_int_handler(dev); | |
23e81d69 AJ |
1997 | } |
1998 | ||
c008bc6e PZ |
1999 | static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) |
2000 | { | |
2001 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40da17c2 | 2002 | enum pipe pipe; |
c008bc6e PZ |
2003 | |
2004 | if (de_iir & DE_AUX_CHANNEL_A) | |
2005 | dp_aux_irq_handler(dev); | |
2006 | ||
2007 | if (de_iir & DE_GSE) | |
2008 | intel_opregion_asle_intr(dev); | |
2009 | ||
c008bc6e PZ |
2010 | if (de_iir & DE_POISON) |
2011 | DRM_ERROR("Poison interrupt\n"); | |
2012 | ||
055e393f | 2013 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
2014 | if (de_iir & DE_PIPE_VBLANK(pipe) && |
2015 | intel_pipe_handle_vblank(dev, pipe)) | |
2016 | intel_check_page_flip(dev, pipe); | |
5b3a856b | 2017 | |
40da17c2 | 2018 | if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) |
1f7247c0 | 2019 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); |
5b3a856b | 2020 | |
40da17c2 DV |
2021 | if (de_iir & DE_PIPE_CRC_DONE(pipe)) |
2022 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
c008bc6e | 2023 | |
40da17c2 DV |
2024 | /* plane/pipes map 1:1 on ilk+ */ |
2025 | if (de_iir & DE_PLANE_FLIP_DONE(pipe)) { | |
2026 | intel_prepare_page_flip(dev, pipe); | |
2027 | intel_finish_page_flip_plane(dev, pipe); | |
2028 | } | |
c008bc6e PZ |
2029 | } |
2030 | ||
2031 | /* check event from PCH */ | |
2032 | if (de_iir & DE_PCH_EVENT) { | |
2033 | u32 pch_iir = I915_READ(SDEIIR); | |
2034 | ||
2035 | if (HAS_PCH_CPT(dev)) | |
2036 | cpt_irq_handler(dev, pch_iir); | |
2037 | else | |
2038 | ibx_irq_handler(dev, pch_iir); | |
2039 | ||
2040 | /* should clear PCH hotplug event before clear CPU irq */ | |
2041 | I915_WRITE(SDEIIR, pch_iir); | |
2042 | } | |
2043 | ||
2044 | if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) | |
2045 | ironlake_rps_change_irq_handler(dev); | |
2046 | } | |
2047 | ||
9719fb98 PZ |
2048 | static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir) |
2049 | { | |
2050 | struct drm_i915_private *dev_priv = dev->dev_private; | |
07d27e20 | 2051 | enum pipe pipe; |
9719fb98 PZ |
2052 | |
2053 | if (de_iir & DE_ERR_INT_IVB) | |
2054 | ivb_err_int_handler(dev); | |
2055 | ||
2056 | if (de_iir & DE_AUX_CHANNEL_A_IVB) | |
2057 | dp_aux_irq_handler(dev); | |
2058 | ||
2059 | if (de_iir & DE_GSE_IVB) | |
2060 | intel_opregion_asle_intr(dev); | |
2061 | ||
055e393f | 2062 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
2063 | if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) && |
2064 | intel_pipe_handle_vblank(dev, pipe)) | |
2065 | intel_check_page_flip(dev, pipe); | |
40da17c2 DV |
2066 | |
2067 | /* plane/pipes map 1:1 on ilk+ */ | |
07d27e20 DL |
2068 | if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) { |
2069 | intel_prepare_page_flip(dev, pipe); | |
2070 | intel_finish_page_flip_plane(dev, pipe); | |
9719fb98 PZ |
2071 | } |
2072 | } | |
2073 | ||
2074 | /* check event from PCH */ | |
2075 | if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) { | |
2076 | u32 pch_iir = I915_READ(SDEIIR); | |
2077 | ||
2078 | cpt_irq_handler(dev, pch_iir); | |
2079 | ||
2080 | /* clear PCH hotplug event before clear CPU irq */ | |
2081 | I915_WRITE(SDEIIR, pch_iir); | |
2082 | } | |
2083 | } | |
2084 | ||
72c90f62 OM |
2085 | /* |
2086 | * To handle irqs with the minimum potential races with fresh interrupts, we: | |
2087 | * 1 - Disable Master Interrupt Control. | |
2088 | * 2 - Find the source(s) of the interrupt. | |
2089 | * 3 - Clear the Interrupt Identity bits (IIR). | |
2090 | * 4 - Process the interrupt(s) that had bits set in the IIRs. | |
2091 | * 5 - Re-enable Master Interrupt Control. | |
2092 | */ | |
f1af8fc1 | 2093 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
b1f14ad0 | 2094 | { |
45a83f84 | 2095 | struct drm_device *dev = arg; |
2d1013dd | 2096 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1af8fc1 | 2097 | u32 de_iir, gt_iir, de_ier, sde_ier = 0; |
0e43406b | 2098 | irqreturn_t ret = IRQ_NONE; |
b1f14ad0 | 2099 | |
2dd2a883 ID |
2100 | if (!intel_irqs_enabled(dev_priv)) |
2101 | return IRQ_NONE; | |
2102 | ||
8664281b PZ |
2103 | /* We get interrupts on unclaimed registers, so check for this before we |
2104 | * do any I915_{READ,WRITE}. */ | |
907b28c5 | 2105 | intel_uncore_check_errors(dev); |
8664281b | 2106 | |
b1f14ad0 JB |
2107 | /* disable master interrupt before clearing iir */ |
2108 | de_ier = I915_READ(DEIER); | |
2109 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
23a78516 | 2110 | POSTING_READ(DEIER); |
b1f14ad0 | 2111 | |
44498aea PZ |
2112 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
2113 | * interrupts will will be stored on its back queue, and then we'll be | |
2114 | * able to process them after we restore SDEIER (as soon as we restore | |
2115 | * it, we'll get an interrupt if SDEIIR still has something to process | |
2116 | * due to its back queue). */ | |
ab5c608b BW |
2117 | if (!HAS_PCH_NOP(dev)) { |
2118 | sde_ier = I915_READ(SDEIER); | |
2119 | I915_WRITE(SDEIER, 0); | |
2120 | POSTING_READ(SDEIER); | |
2121 | } | |
44498aea | 2122 | |
72c90f62 OM |
2123 | /* Find, clear, then process each source of interrupt */ |
2124 | ||
b1f14ad0 | 2125 | gt_iir = I915_READ(GTIIR); |
0e43406b | 2126 | if (gt_iir) { |
72c90f62 OM |
2127 | I915_WRITE(GTIIR, gt_iir); |
2128 | ret = IRQ_HANDLED; | |
d8fc8a47 | 2129 | if (INTEL_INFO(dev)->gen >= 6) |
f1af8fc1 | 2130 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
d8fc8a47 PZ |
2131 | else |
2132 | ilk_gt_irq_handler(dev, dev_priv, gt_iir); | |
b1f14ad0 JB |
2133 | } |
2134 | ||
0e43406b CW |
2135 | de_iir = I915_READ(DEIIR); |
2136 | if (de_iir) { | |
72c90f62 OM |
2137 | I915_WRITE(DEIIR, de_iir); |
2138 | ret = IRQ_HANDLED; | |
f1af8fc1 PZ |
2139 | if (INTEL_INFO(dev)->gen >= 7) |
2140 | ivb_display_irq_handler(dev, de_iir); | |
2141 | else | |
2142 | ilk_display_irq_handler(dev, de_iir); | |
b1f14ad0 JB |
2143 | } |
2144 | ||
f1af8fc1 PZ |
2145 | if (INTEL_INFO(dev)->gen >= 6) { |
2146 | u32 pm_iir = I915_READ(GEN6_PMIIR); | |
2147 | if (pm_iir) { | |
f1af8fc1 PZ |
2148 | I915_WRITE(GEN6_PMIIR, pm_iir); |
2149 | ret = IRQ_HANDLED; | |
72c90f62 | 2150 | gen6_rps_irq_handler(dev_priv, pm_iir); |
f1af8fc1 | 2151 | } |
0e43406b | 2152 | } |
b1f14ad0 | 2153 | |
b1f14ad0 JB |
2154 | I915_WRITE(DEIER, de_ier); |
2155 | POSTING_READ(DEIER); | |
ab5c608b BW |
2156 | if (!HAS_PCH_NOP(dev)) { |
2157 | I915_WRITE(SDEIER, sde_ier); | |
2158 | POSTING_READ(SDEIER); | |
2159 | } | |
b1f14ad0 JB |
2160 | |
2161 | return ret; | |
2162 | } | |
2163 | ||
abd58f01 BW |
2164 | static irqreturn_t gen8_irq_handler(int irq, void *arg) |
2165 | { | |
2166 | struct drm_device *dev = arg; | |
2167 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2168 | u32 master_ctl; | |
2169 | irqreturn_t ret = IRQ_NONE; | |
2170 | uint32_t tmp = 0; | |
c42664cc | 2171 | enum pipe pipe; |
88e04703 JB |
2172 | u32 aux_mask = GEN8_AUX_CHANNEL_A; |
2173 | ||
2dd2a883 ID |
2174 | if (!intel_irqs_enabled(dev_priv)) |
2175 | return IRQ_NONE; | |
2176 | ||
88e04703 JB |
2177 | if (IS_GEN9(dev)) |
2178 | aux_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | | |
2179 | GEN9_AUX_CHANNEL_D; | |
abd58f01 | 2180 | |
cb0d205e | 2181 | master_ctl = I915_READ_FW(GEN8_MASTER_IRQ); |
abd58f01 BW |
2182 | master_ctl &= ~GEN8_MASTER_IRQ_CONTROL; |
2183 | if (!master_ctl) | |
2184 | return IRQ_NONE; | |
2185 | ||
cb0d205e | 2186 | I915_WRITE_FW(GEN8_MASTER_IRQ, 0); |
abd58f01 | 2187 | |
38cc46d7 OM |
2188 | /* Find, clear, then process each source of interrupt */ |
2189 | ||
abd58f01 BW |
2190 | ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl); |
2191 | ||
2192 | if (master_ctl & GEN8_DE_MISC_IRQ) { | |
2193 | tmp = I915_READ(GEN8_DE_MISC_IIR); | |
abd58f01 BW |
2194 | if (tmp) { |
2195 | I915_WRITE(GEN8_DE_MISC_IIR, tmp); | |
2196 | ret = IRQ_HANDLED; | |
38cc46d7 OM |
2197 | if (tmp & GEN8_DE_MISC_GSE) |
2198 | intel_opregion_asle_intr(dev); | |
2199 | else | |
2200 | DRM_ERROR("Unexpected DE Misc interrupt\n"); | |
abd58f01 | 2201 | } |
38cc46d7 OM |
2202 | else |
2203 | DRM_ERROR("The master control interrupt lied (DE MISC)!\n"); | |
abd58f01 BW |
2204 | } |
2205 | ||
6d766f02 DV |
2206 | if (master_ctl & GEN8_DE_PORT_IRQ) { |
2207 | tmp = I915_READ(GEN8_DE_PORT_IIR); | |
6d766f02 DV |
2208 | if (tmp) { |
2209 | I915_WRITE(GEN8_DE_PORT_IIR, tmp); | |
2210 | ret = IRQ_HANDLED; | |
88e04703 JB |
2211 | |
2212 | if (tmp & aux_mask) | |
38cc46d7 OM |
2213 | dp_aux_irq_handler(dev); |
2214 | else | |
2215 | DRM_ERROR("Unexpected DE Port interrupt\n"); | |
6d766f02 | 2216 | } |
38cc46d7 OM |
2217 | else |
2218 | DRM_ERROR("The master control interrupt lied (DE PORT)!\n"); | |
6d766f02 DV |
2219 | } |
2220 | ||
055e393f | 2221 | for_each_pipe(dev_priv, pipe) { |
770de83d | 2222 | uint32_t pipe_iir, flip_done = 0, fault_errors = 0; |
abd58f01 | 2223 | |
c42664cc DV |
2224 | if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) |
2225 | continue; | |
abd58f01 | 2226 | |
c42664cc | 2227 | pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); |
c42664cc DV |
2228 | if (pipe_iir) { |
2229 | ret = IRQ_HANDLED; | |
2230 | I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir); | |
770de83d | 2231 | |
d6bbafa1 CW |
2232 | if (pipe_iir & GEN8_PIPE_VBLANK && |
2233 | intel_pipe_handle_vblank(dev, pipe)) | |
2234 | intel_check_page_flip(dev, pipe); | |
38cc46d7 | 2235 | |
770de83d DL |
2236 | if (IS_GEN9(dev)) |
2237 | flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE; | |
2238 | else | |
2239 | flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE; | |
2240 | ||
2241 | if (flip_done) { | |
38cc46d7 OM |
2242 | intel_prepare_page_flip(dev, pipe); |
2243 | intel_finish_page_flip_plane(dev, pipe); | |
2244 | } | |
2245 | ||
2246 | if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE) | |
2247 | hsw_pipe_crc_irq_handler(dev, pipe); | |
2248 | ||
1f7247c0 DV |
2249 | if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) |
2250 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
2251 | pipe); | |
38cc46d7 | 2252 | |
770de83d DL |
2253 | |
2254 | if (IS_GEN9(dev)) | |
2255 | fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS; | |
2256 | else | |
2257 | fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
2258 | ||
2259 | if (fault_errors) | |
38cc46d7 OM |
2260 | DRM_ERROR("Fault errors on pipe %c\n: 0x%08x", |
2261 | pipe_name(pipe), | |
2262 | pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS); | |
c42664cc | 2263 | } else |
abd58f01 BW |
2264 | DRM_ERROR("The master control interrupt lied (DE PIPE)!\n"); |
2265 | } | |
2266 | ||
92d03a80 DV |
2267 | if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) { |
2268 | /* | |
2269 | * FIXME(BDW): Assume for now that the new interrupt handling | |
2270 | * scheme also closed the SDE interrupt handling race we've seen | |
2271 | * on older pch-split platforms. But this needs testing. | |
2272 | */ | |
2273 | u32 pch_iir = I915_READ(SDEIIR); | |
92d03a80 DV |
2274 | if (pch_iir) { |
2275 | I915_WRITE(SDEIIR, pch_iir); | |
2276 | ret = IRQ_HANDLED; | |
38cc46d7 OM |
2277 | cpt_irq_handler(dev, pch_iir); |
2278 | } else | |
2279 | DRM_ERROR("The master control interrupt lied (SDE)!\n"); | |
2280 | ||
92d03a80 DV |
2281 | } |
2282 | ||
cb0d205e CW |
2283 | I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
2284 | POSTING_READ_FW(GEN8_MASTER_IRQ); | |
abd58f01 BW |
2285 | |
2286 | return ret; | |
2287 | } | |
2288 | ||
17e1df07 DV |
2289 | static void i915_error_wake_up(struct drm_i915_private *dev_priv, |
2290 | bool reset_completed) | |
2291 | { | |
a4872ba6 | 2292 | struct intel_engine_cs *ring; |
17e1df07 DV |
2293 | int i; |
2294 | ||
2295 | /* | |
2296 | * Notify all waiters for GPU completion events that reset state has | |
2297 | * been changed, and that they need to restart their wait after | |
2298 | * checking for potential errors (and bail out to drop locks if there is | |
2299 | * a gpu reset pending so that i915_error_work_func can acquire them). | |
2300 | */ | |
2301 | ||
2302 | /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */ | |
2303 | for_each_ring(ring, dev_priv, i) | |
2304 | wake_up_all(&ring->irq_queue); | |
2305 | ||
2306 | /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */ | |
2307 | wake_up_all(&dev_priv->pending_flip_queue); | |
2308 | ||
2309 | /* | |
2310 | * Signal tasks blocked in i915_gem_wait_for_error that the pending | |
2311 | * reset state is cleared. | |
2312 | */ | |
2313 | if (reset_completed) | |
2314 | wake_up_all(&dev_priv->gpu_error.reset_queue); | |
2315 | } | |
2316 | ||
8a905236 | 2317 | /** |
b8d24a06 | 2318 | * i915_reset_and_wakeup - do process context error handling work |
8a905236 JB |
2319 | * |
2320 | * Fire an error uevent so userspace can see that a hang or error | |
2321 | * was detected. | |
2322 | */ | |
b8d24a06 | 2323 | static void i915_reset_and_wakeup(struct drm_device *dev) |
8a905236 | 2324 | { |
b8d24a06 MK |
2325 | struct drm_i915_private *dev_priv = to_i915(dev); |
2326 | struct i915_gpu_error *error = &dev_priv->gpu_error; | |
cce723ed BW |
2327 | char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; |
2328 | char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; | |
2329 | char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; | |
17e1df07 | 2330 | int ret; |
8a905236 | 2331 | |
5bdebb18 | 2332 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event); |
f316a42c | 2333 | |
7db0ba24 DV |
2334 | /* |
2335 | * Note that there's only one work item which does gpu resets, so we | |
2336 | * need not worry about concurrent gpu resets potentially incrementing | |
2337 | * error->reset_counter twice. We only need to take care of another | |
2338 | * racing irq/hangcheck declaring the gpu dead for a second time. A | |
2339 | * quick check for that is good enough: schedule_work ensures the | |
2340 | * correct ordering between hang detection and this work item, and since | |
2341 | * the reset in-progress bit is only ever set by code outside of this | |
2342 | * work we don't need to worry about any other races. | |
2343 | */ | |
2344 | if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) { | |
f803aa55 | 2345 | DRM_DEBUG_DRIVER("resetting chip\n"); |
5bdebb18 | 2346 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, |
7db0ba24 | 2347 | reset_event); |
1f83fee0 | 2348 | |
f454c694 ID |
2349 | /* |
2350 | * In most cases it's guaranteed that we get here with an RPM | |
2351 | * reference held, for example because there is a pending GPU | |
2352 | * request that won't finish until the reset is done. This | |
2353 | * isn't the case at least when we get here by doing a | |
2354 | * simulated reset via debugs, so get an RPM reference. | |
2355 | */ | |
2356 | intel_runtime_pm_get(dev_priv); | |
7514747d VS |
2357 | |
2358 | intel_prepare_reset(dev); | |
2359 | ||
17e1df07 DV |
2360 | /* |
2361 | * All state reset _must_ be completed before we update the | |
2362 | * reset counter, for otherwise waiters might miss the reset | |
2363 | * pending state and not properly drop locks, resulting in | |
2364 | * deadlocks with the reset work. | |
2365 | */ | |
f69061be DV |
2366 | ret = i915_reset(dev); |
2367 | ||
7514747d | 2368 | intel_finish_reset(dev); |
17e1df07 | 2369 | |
f454c694 ID |
2370 | intel_runtime_pm_put(dev_priv); |
2371 | ||
f69061be DV |
2372 | if (ret == 0) { |
2373 | /* | |
2374 | * After all the gem state is reset, increment the reset | |
2375 | * counter and wake up everyone waiting for the reset to | |
2376 | * complete. | |
2377 | * | |
2378 | * Since unlock operations are a one-sided barrier only, | |
2379 | * we need to insert a barrier here to order any seqno | |
2380 | * updates before | |
2381 | * the counter increment. | |
2382 | */ | |
4e857c58 | 2383 | smp_mb__before_atomic(); |
f69061be DV |
2384 | atomic_inc(&dev_priv->gpu_error.reset_counter); |
2385 | ||
5bdebb18 | 2386 | kobject_uevent_env(&dev->primary->kdev->kobj, |
f69061be | 2387 | KOBJ_CHANGE, reset_done_event); |
1f83fee0 | 2388 | } else { |
2ac0f450 | 2389 | atomic_set_mask(I915_WEDGED, &error->reset_counter); |
f316a42c | 2390 | } |
1f83fee0 | 2391 | |
17e1df07 DV |
2392 | /* |
2393 | * Note: The wake_up also serves as a memory barrier so that | |
2394 | * waiters see the update value of the reset counter atomic_t. | |
2395 | */ | |
2396 | i915_error_wake_up(dev_priv, true); | |
f316a42c | 2397 | } |
8a905236 JB |
2398 | } |
2399 | ||
35aed2e6 | 2400 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
2401 | { |
2402 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bd9854f9 | 2403 | uint32_t instdone[I915_NUM_INSTDONE_REG]; |
8a905236 | 2404 | u32 eir = I915_READ(EIR); |
050ee91f | 2405 | int pipe, i; |
8a905236 | 2406 | |
35aed2e6 CW |
2407 | if (!eir) |
2408 | return; | |
8a905236 | 2409 | |
a70491cc | 2410 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
8a905236 | 2411 | |
bd9854f9 BW |
2412 | i915_get_extra_instdone(dev, instdone); |
2413 | ||
8a905236 JB |
2414 | if (IS_G4X(dev)) { |
2415 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
2416 | u32 ipeir = I915_READ(IPEIR_I965); | |
2417 | ||
a70491cc JP |
2418 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2419 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
050ee91f BW |
2420 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2421 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a70491cc | 2422 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2423 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2424 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2425 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2426 | } |
2427 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
2428 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2429 | pr_err("page table error\n"); |
2430 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2431 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2432 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2433 | } |
2434 | } | |
2435 | ||
a6c45cf0 | 2436 | if (!IS_GEN2(dev)) { |
8a905236 JB |
2437 | if (eir & I915_ERROR_PAGE_TABLE) { |
2438 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2439 | pr_err("page table error\n"); |
2440 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2441 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2442 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2443 | } |
2444 | } | |
2445 | ||
2446 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
a70491cc | 2447 | pr_err("memory refresh error:\n"); |
055e393f | 2448 | for_each_pipe(dev_priv, pipe) |
a70491cc | 2449 | pr_err("pipe %c stat: 0x%08x\n", |
9db4a9c7 | 2450 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
8a905236 JB |
2451 | /* pipestat has already been acked */ |
2452 | } | |
2453 | if (eir & I915_ERROR_INSTRUCTION) { | |
a70491cc JP |
2454 | pr_err("instruction error\n"); |
2455 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); | |
050ee91f BW |
2456 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2457 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a6c45cf0 | 2458 | if (INTEL_INFO(dev)->gen < 4) { |
8a905236 JB |
2459 | u32 ipeir = I915_READ(IPEIR); |
2460 | ||
a70491cc JP |
2461 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
2462 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); | |
a70491cc | 2463 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); |
8a905236 | 2464 | I915_WRITE(IPEIR, ipeir); |
3143a2bf | 2465 | POSTING_READ(IPEIR); |
8a905236 JB |
2466 | } else { |
2467 | u32 ipeir = I915_READ(IPEIR_I965); | |
2468 | ||
a70491cc JP |
2469 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2470 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
a70491cc | 2471 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2472 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2473 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2474 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2475 | } |
2476 | } | |
2477 | ||
2478 | I915_WRITE(EIR, eir); | |
3143a2bf | 2479 | POSTING_READ(EIR); |
8a905236 JB |
2480 | eir = I915_READ(EIR); |
2481 | if (eir) { | |
2482 | /* | |
2483 | * some errors might have become stuck, | |
2484 | * mask them. | |
2485 | */ | |
2486 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
2487 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
2488 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2489 | } | |
35aed2e6 CW |
2490 | } |
2491 | ||
2492 | /** | |
b8d24a06 | 2493 | * i915_handle_error - handle a gpu error |
35aed2e6 CW |
2494 | * @dev: drm device |
2495 | * | |
b8d24a06 | 2496 | * Do some basic checking of regsiter state at error time and |
35aed2e6 CW |
2497 | * dump it to the syslog. Also call i915_capture_error_state() to make |
2498 | * sure we get a record and make it available in debugfs. Fire a uevent | |
2499 | * so userspace knows something bad happened (should trigger collection | |
2500 | * of a ring dump etc.). | |
2501 | */ | |
58174462 MK |
2502 | void i915_handle_error(struct drm_device *dev, bool wedged, |
2503 | const char *fmt, ...) | |
35aed2e6 CW |
2504 | { |
2505 | struct drm_i915_private *dev_priv = dev->dev_private; | |
58174462 MK |
2506 | va_list args; |
2507 | char error_msg[80]; | |
35aed2e6 | 2508 | |
58174462 MK |
2509 | va_start(args, fmt); |
2510 | vscnprintf(error_msg, sizeof(error_msg), fmt, args); | |
2511 | va_end(args); | |
2512 | ||
2513 | i915_capture_error_state(dev, wedged, error_msg); | |
35aed2e6 | 2514 | i915_report_and_clear_eir(dev); |
8a905236 | 2515 | |
ba1234d1 | 2516 | if (wedged) { |
f69061be DV |
2517 | atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG, |
2518 | &dev_priv->gpu_error.reset_counter); | |
ba1234d1 | 2519 | |
11ed50ec | 2520 | /* |
b8d24a06 MK |
2521 | * Wakeup waiting processes so that the reset function |
2522 | * i915_reset_and_wakeup doesn't deadlock trying to grab | |
2523 | * various locks. By bumping the reset counter first, the woken | |
17e1df07 DV |
2524 | * processes will see a reset in progress and back off, |
2525 | * releasing their locks and then wait for the reset completion. | |
2526 | * We must do this for _all_ gpu waiters that might hold locks | |
2527 | * that the reset work needs to acquire. | |
2528 | * | |
2529 | * Note: The wake_up serves as the required memory barrier to | |
2530 | * ensure that the waiters see the updated value of the reset | |
2531 | * counter atomic_t. | |
11ed50ec | 2532 | */ |
17e1df07 | 2533 | i915_error_wake_up(dev_priv, false); |
11ed50ec BG |
2534 | } |
2535 | ||
b8d24a06 | 2536 | i915_reset_and_wakeup(dev); |
8a905236 JB |
2537 | } |
2538 | ||
42f52ef8 KP |
2539 | /* Called from drm generic code, passed 'crtc' which |
2540 | * we use as a pipe index | |
2541 | */ | |
f71d4af4 | 2542 | static int i915_enable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 | 2543 | { |
2d1013dd | 2544 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2545 | unsigned long irqflags; |
71e0ffa5 | 2546 | |
1ec14ad3 | 2547 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2548 | if (INTEL_INFO(dev)->gen >= 4) |
7c463586 | 2549 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2550 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
e9d21d7f | 2551 | else |
7c463586 | 2552 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2553 | PIPE_VBLANK_INTERRUPT_STATUS); |
1ec14ad3 | 2554 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
8692d00e | 2555 | |
0a3e67a4 JB |
2556 | return 0; |
2557 | } | |
2558 | ||
f71d4af4 | 2559 | static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
f796cf8f | 2560 | { |
2d1013dd | 2561 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2562 | unsigned long irqflags; |
b518421f | 2563 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2564 | DE_PIPE_VBLANK(pipe); |
f796cf8f | 2565 | |
f796cf8f | 2566 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
b518421f | 2567 | ironlake_enable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2568 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2569 | ||
2570 | return 0; | |
2571 | } | |
2572 | ||
7e231dbe JB |
2573 | static int valleyview_enable_vblank(struct drm_device *dev, int pipe) |
2574 | { | |
2d1013dd | 2575 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2576 | unsigned long irqflags; |
7e231dbe | 2577 | |
7e231dbe | 2578 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
31acc7f5 | 2579 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2580 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2581 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2582 | ||
2583 | return 0; | |
2584 | } | |
2585 | ||
abd58f01 BW |
2586 | static int gen8_enable_vblank(struct drm_device *dev, int pipe) |
2587 | { | |
2588 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2589 | unsigned long irqflags; | |
abd58f01 | 2590 | |
abd58f01 | 2591 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
7167d7c6 DV |
2592 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK; |
2593 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2594 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2595 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2596 | return 0; | |
2597 | } | |
2598 | ||
42f52ef8 KP |
2599 | /* Called from drm generic code, passed 'crtc' which |
2600 | * we use as a pipe index | |
2601 | */ | |
f71d4af4 | 2602 | static void i915_disable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 | 2603 | { |
2d1013dd | 2604 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2605 | unsigned long irqflags; |
0a3e67a4 | 2606 | |
1ec14ad3 | 2607 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2608 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 ID |
2609 | PIPE_VBLANK_INTERRUPT_STATUS | |
2610 | PIPE_START_VBLANK_INTERRUPT_STATUS); | |
f796cf8f JB |
2611 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2612 | } | |
2613 | ||
f71d4af4 | 2614 | static void ironlake_disable_vblank(struct drm_device *dev, int pipe) |
f796cf8f | 2615 | { |
2d1013dd | 2616 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2617 | unsigned long irqflags; |
b518421f | 2618 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2619 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2620 | |
2621 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 2622 | ironlake_disable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2623 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2624 | } | |
2625 | ||
7e231dbe JB |
2626 | static void valleyview_disable_vblank(struct drm_device *dev, int pipe) |
2627 | { | |
2d1013dd | 2628 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2629 | unsigned long irqflags; |
7e231dbe JB |
2630 | |
2631 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 | 2632 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 | 2633 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2634 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2635 | } | |
2636 | ||
abd58f01 BW |
2637 | static void gen8_disable_vblank(struct drm_device *dev, int pipe) |
2638 | { | |
2639 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2640 | unsigned long irqflags; | |
abd58f01 | 2641 | |
abd58f01 | 2642 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
7167d7c6 DV |
2643 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK; |
2644 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2645 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2646 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2647 | } | |
2648 | ||
44cdd6d2 JH |
2649 | static struct drm_i915_gem_request * |
2650 | ring_last_request(struct intel_engine_cs *ring) | |
852835f3 | 2651 | { |
893eead0 | 2652 | return list_entry(ring->request_list.prev, |
44cdd6d2 | 2653 | struct drm_i915_gem_request, list); |
893eead0 CW |
2654 | } |
2655 | ||
9107e9d2 | 2656 | static bool |
44cdd6d2 | 2657 | ring_idle(struct intel_engine_cs *ring) |
9107e9d2 CW |
2658 | { |
2659 | return (list_empty(&ring->request_list) || | |
1b5a433a | 2660 | i915_gem_request_completed(ring_last_request(ring), false)); |
f65d9421 BG |
2661 | } |
2662 | ||
a028c4b0 DV |
2663 | static bool |
2664 | ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr) | |
2665 | { | |
2666 | if (INTEL_INFO(dev)->gen >= 8) { | |
a6cdb93a | 2667 | return (ipehr >> 23) == 0x1c; |
a028c4b0 DV |
2668 | } else { |
2669 | ipehr &= ~MI_SEMAPHORE_SYNC_MASK; | |
2670 | return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | | |
2671 | MI_SEMAPHORE_REGISTER); | |
2672 | } | |
2673 | } | |
2674 | ||
a4872ba6 | 2675 | static struct intel_engine_cs * |
a6cdb93a | 2676 | semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset) |
921d42ea DV |
2677 | { |
2678 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
a4872ba6 | 2679 | struct intel_engine_cs *signaller; |
921d42ea DV |
2680 | int i; |
2681 | ||
2682 | if (INTEL_INFO(dev_priv->dev)->gen >= 8) { | |
a6cdb93a RV |
2683 | for_each_ring(signaller, dev_priv, i) { |
2684 | if (ring == signaller) | |
2685 | continue; | |
2686 | ||
2687 | if (offset == signaller->semaphore.signal_ggtt[ring->id]) | |
2688 | return signaller; | |
2689 | } | |
921d42ea DV |
2690 | } else { |
2691 | u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK; | |
2692 | ||
2693 | for_each_ring(signaller, dev_priv, i) { | |
2694 | if(ring == signaller) | |
2695 | continue; | |
2696 | ||
ebc348b2 | 2697 | if (sync_bits == signaller->semaphore.mbox.wait[ring->id]) |
921d42ea DV |
2698 | return signaller; |
2699 | } | |
2700 | } | |
2701 | ||
a6cdb93a RV |
2702 | DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n", |
2703 | ring->id, ipehr, offset); | |
921d42ea DV |
2704 | |
2705 | return NULL; | |
2706 | } | |
2707 | ||
a4872ba6 OM |
2708 | static struct intel_engine_cs * |
2709 | semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno) | |
a24a11e6 CW |
2710 | { |
2711 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
88fe429d | 2712 | u32 cmd, ipehr, head; |
a6cdb93a RV |
2713 | u64 offset = 0; |
2714 | int i, backwards; | |
a24a11e6 CW |
2715 | |
2716 | ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); | |
a028c4b0 | 2717 | if (!ipehr_is_semaphore_wait(ring->dev, ipehr)) |
6274f212 | 2718 | return NULL; |
a24a11e6 | 2719 | |
88fe429d DV |
2720 | /* |
2721 | * HEAD is likely pointing to the dword after the actual command, | |
2722 | * so scan backwards until we find the MBOX. But limit it to just 3 | |
a6cdb93a RV |
2723 | * or 4 dwords depending on the semaphore wait command size. |
2724 | * Note that we don't care about ACTHD here since that might | |
88fe429d DV |
2725 | * point at at batch, and semaphores are always emitted into the |
2726 | * ringbuffer itself. | |
a24a11e6 | 2727 | */ |
88fe429d | 2728 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
a6cdb93a | 2729 | backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4; |
88fe429d | 2730 | |
a6cdb93a | 2731 | for (i = backwards; i; --i) { |
88fe429d DV |
2732 | /* |
2733 | * Be paranoid and presume the hw has gone off into the wild - | |
2734 | * our ring is smaller than what the hardware (and hence | |
2735 | * HEAD_ADDR) allows. Also handles wrap-around. | |
2736 | */ | |
ee1b1e5e | 2737 | head &= ring->buffer->size - 1; |
88fe429d DV |
2738 | |
2739 | /* This here seems to blow up */ | |
ee1b1e5e | 2740 | cmd = ioread32(ring->buffer->virtual_start + head); |
a24a11e6 CW |
2741 | if (cmd == ipehr) |
2742 | break; | |
2743 | ||
88fe429d DV |
2744 | head -= 4; |
2745 | } | |
a24a11e6 | 2746 | |
88fe429d DV |
2747 | if (!i) |
2748 | return NULL; | |
a24a11e6 | 2749 | |
ee1b1e5e | 2750 | *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1; |
a6cdb93a RV |
2751 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
2752 | offset = ioread32(ring->buffer->virtual_start + head + 12); | |
2753 | offset <<= 32; | |
2754 | offset = ioread32(ring->buffer->virtual_start + head + 8); | |
2755 | } | |
2756 | return semaphore_wait_to_signaller_ring(ring, ipehr, offset); | |
a24a11e6 CW |
2757 | } |
2758 | ||
a4872ba6 | 2759 | static int semaphore_passed(struct intel_engine_cs *ring) |
6274f212 CW |
2760 | { |
2761 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
a4872ba6 | 2762 | struct intel_engine_cs *signaller; |
a0d036b0 | 2763 | u32 seqno; |
6274f212 | 2764 | |
4be17381 | 2765 | ring->hangcheck.deadlock++; |
6274f212 CW |
2766 | |
2767 | signaller = semaphore_waits_for(ring, &seqno); | |
4be17381 CW |
2768 | if (signaller == NULL) |
2769 | return -1; | |
2770 | ||
2771 | /* Prevent pathological recursion due to driver bugs */ | |
2772 | if (signaller->hangcheck.deadlock >= I915_NUM_RINGS) | |
6274f212 CW |
2773 | return -1; |
2774 | ||
4be17381 CW |
2775 | if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno)) |
2776 | return 1; | |
2777 | ||
a0d036b0 CW |
2778 | /* cursory check for an unkickable deadlock */ |
2779 | if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE && | |
2780 | semaphore_passed(signaller) < 0) | |
4be17381 CW |
2781 | return -1; |
2782 | ||
2783 | return 0; | |
6274f212 CW |
2784 | } |
2785 | ||
2786 | static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) | |
2787 | { | |
a4872ba6 | 2788 | struct intel_engine_cs *ring; |
6274f212 CW |
2789 | int i; |
2790 | ||
2791 | for_each_ring(ring, dev_priv, i) | |
4be17381 | 2792 | ring->hangcheck.deadlock = 0; |
6274f212 CW |
2793 | } |
2794 | ||
ad8beaea | 2795 | static enum intel_ring_hangcheck_action |
a4872ba6 | 2796 | ring_stuck(struct intel_engine_cs *ring, u64 acthd) |
1ec14ad3 CW |
2797 | { |
2798 | struct drm_device *dev = ring->dev; | |
2799 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9107e9d2 CW |
2800 | u32 tmp; |
2801 | ||
f260fe7b MK |
2802 | if (acthd != ring->hangcheck.acthd) { |
2803 | if (acthd > ring->hangcheck.max_acthd) { | |
2804 | ring->hangcheck.max_acthd = acthd; | |
2805 | return HANGCHECK_ACTIVE; | |
2806 | } | |
2807 | ||
2808 | return HANGCHECK_ACTIVE_LOOP; | |
2809 | } | |
6274f212 | 2810 | |
9107e9d2 | 2811 | if (IS_GEN2(dev)) |
f2f4d82f | 2812 | return HANGCHECK_HUNG; |
9107e9d2 CW |
2813 | |
2814 | /* Is the chip hanging on a WAIT_FOR_EVENT? | |
2815 | * If so we can simply poke the RB_WAIT bit | |
2816 | * and break the hang. This should work on | |
2817 | * all but the second generation chipsets. | |
2818 | */ | |
2819 | tmp = I915_READ_CTL(ring); | |
1ec14ad3 | 2820 | if (tmp & RING_WAIT) { |
58174462 MK |
2821 | i915_handle_error(dev, false, |
2822 | "Kicking stuck wait on %s", | |
2823 | ring->name); | |
1ec14ad3 | 2824 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2825 | return HANGCHECK_KICK; |
6274f212 CW |
2826 | } |
2827 | ||
2828 | if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { | |
2829 | switch (semaphore_passed(ring)) { | |
2830 | default: | |
f2f4d82f | 2831 | return HANGCHECK_HUNG; |
6274f212 | 2832 | case 1: |
58174462 MK |
2833 | i915_handle_error(dev, false, |
2834 | "Kicking stuck semaphore on %s", | |
2835 | ring->name); | |
6274f212 | 2836 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2837 | return HANGCHECK_KICK; |
6274f212 | 2838 | case 0: |
f2f4d82f | 2839 | return HANGCHECK_WAIT; |
6274f212 | 2840 | } |
9107e9d2 | 2841 | } |
ed5cbb03 | 2842 | |
f2f4d82f | 2843 | return HANGCHECK_HUNG; |
ed5cbb03 MK |
2844 | } |
2845 | ||
737b1506 | 2846 | /* |
f65d9421 | 2847 | * This is called when the chip hasn't reported back with completed |
05407ff8 MK |
2848 | * batchbuffers in a long time. We keep track per ring seqno progress and |
2849 | * if there are no progress, hangcheck score for that ring is increased. | |
2850 | * Further, acthd is inspected to see if the ring is stuck. On stuck case | |
2851 | * we kick the ring. If we see no progress on three subsequent calls | |
2852 | * we assume chip is wedged and try to fix it by resetting the chip. | |
f65d9421 | 2853 | */ |
737b1506 | 2854 | static void i915_hangcheck_elapsed(struct work_struct *work) |
f65d9421 | 2855 | { |
737b1506 CW |
2856 | struct drm_i915_private *dev_priv = |
2857 | container_of(work, typeof(*dev_priv), | |
2858 | gpu_error.hangcheck_work.work); | |
2859 | struct drm_device *dev = dev_priv->dev; | |
a4872ba6 | 2860 | struct intel_engine_cs *ring; |
b4519513 | 2861 | int i; |
05407ff8 | 2862 | int busy_count = 0, rings_hung = 0; |
9107e9d2 CW |
2863 | bool stuck[I915_NUM_RINGS] = { 0 }; |
2864 | #define BUSY 1 | |
2865 | #define KICK 5 | |
2866 | #define HUNG 20 | |
893eead0 | 2867 | |
d330a953 | 2868 | if (!i915.enable_hangcheck) |
3e0dc6b0 BW |
2869 | return; |
2870 | ||
b4519513 | 2871 | for_each_ring(ring, dev_priv, i) { |
50877445 CW |
2872 | u64 acthd; |
2873 | u32 seqno; | |
9107e9d2 | 2874 | bool busy = true; |
05407ff8 | 2875 | |
6274f212 CW |
2876 | semaphore_clear_deadlocks(dev_priv); |
2877 | ||
05407ff8 MK |
2878 | seqno = ring->get_seqno(ring, false); |
2879 | acthd = intel_ring_get_active_head(ring); | |
b4519513 | 2880 | |
9107e9d2 | 2881 | if (ring->hangcheck.seqno == seqno) { |
44cdd6d2 | 2882 | if (ring_idle(ring)) { |
da661464 MK |
2883 | ring->hangcheck.action = HANGCHECK_IDLE; |
2884 | ||
9107e9d2 CW |
2885 | if (waitqueue_active(&ring->irq_queue)) { |
2886 | /* Issue a wake-up to catch stuck h/w. */ | |
094f9a54 | 2887 | if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) { |
f4adcd24 DV |
2888 | if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring))) |
2889 | DRM_ERROR("Hangcheck timer elapsed... %s idle\n", | |
2890 | ring->name); | |
2891 | else | |
2892 | DRM_INFO("Fake missed irq on %s\n", | |
2893 | ring->name); | |
094f9a54 CW |
2894 | wake_up_all(&ring->irq_queue); |
2895 | } | |
2896 | /* Safeguard against driver failure */ | |
2897 | ring->hangcheck.score += BUSY; | |
9107e9d2 CW |
2898 | } else |
2899 | busy = false; | |
05407ff8 | 2900 | } else { |
6274f212 CW |
2901 | /* We always increment the hangcheck score |
2902 | * if the ring is busy and still processing | |
2903 | * the same request, so that no single request | |
2904 | * can run indefinitely (such as a chain of | |
2905 | * batches). The only time we do not increment | |
2906 | * the hangcheck score on this ring, if this | |
2907 | * ring is in a legitimate wait for another | |
2908 | * ring. In that case the waiting ring is a | |
2909 | * victim and we want to be sure we catch the | |
2910 | * right culprit. Then every time we do kick | |
2911 | * the ring, add a small increment to the | |
2912 | * score so that we can catch a batch that is | |
2913 | * being repeatedly kicked and so responsible | |
2914 | * for stalling the machine. | |
2915 | */ | |
ad8beaea MK |
2916 | ring->hangcheck.action = ring_stuck(ring, |
2917 | acthd); | |
2918 | ||
2919 | switch (ring->hangcheck.action) { | |
da661464 | 2920 | case HANGCHECK_IDLE: |
f2f4d82f | 2921 | case HANGCHECK_WAIT: |
f2f4d82f | 2922 | case HANGCHECK_ACTIVE: |
f260fe7b MK |
2923 | break; |
2924 | case HANGCHECK_ACTIVE_LOOP: | |
ea04cb31 | 2925 | ring->hangcheck.score += BUSY; |
6274f212 | 2926 | break; |
f2f4d82f | 2927 | case HANGCHECK_KICK: |
ea04cb31 | 2928 | ring->hangcheck.score += KICK; |
6274f212 | 2929 | break; |
f2f4d82f | 2930 | case HANGCHECK_HUNG: |
ea04cb31 | 2931 | ring->hangcheck.score += HUNG; |
6274f212 CW |
2932 | stuck[i] = true; |
2933 | break; | |
2934 | } | |
05407ff8 | 2935 | } |
9107e9d2 | 2936 | } else { |
da661464 MK |
2937 | ring->hangcheck.action = HANGCHECK_ACTIVE; |
2938 | ||
9107e9d2 CW |
2939 | /* Gradually reduce the count so that we catch DoS |
2940 | * attempts across multiple batches. | |
2941 | */ | |
2942 | if (ring->hangcheck.score > 0) | |
2943 | ring->hangcheck.score--; | |
f260fe7b MK |
2944 | |
2945 | ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0; | |
d1e61e7f CW |
2946 | } |
2947 | ||
05407ff8 MK |
2948 | ring->hangcheck.seqno = seqno; |
2949 | ring->hangcheck.acthd = acthd; | |
9107e9d2 | 2950 | busy_count += busy; |
893eead0 | 2951 | } |
b9201c14 | 2952 | |
92cab734 | 2953 | for_each_ring(ring, dev_priv, i) { |
b6b0fac0 | 2954 | if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) { |
b8d88d1d DV |
2955 | DRM_INFO("%s on %s\n", |
2956 | stuck[i] ? "stuck" : "no progress", | |
2957 | ring->name); | |
a43adf07 | 2958 | rings_hung++; |
92cab734 MK |
2959 | } |
2960 | } | |
2961 | ||
05407ff8 | 2962 | if (rings_hung) |
58174462 | 2963 | return i915_handle_error(dev, true, "Ring hung"); |
f65d9421 | 2964 | |
05407ff8 MK |
2965 | if (busy_count) |
2966 | /* Reset timer case chip hangs without another request | |
2967 | * being added */ | |
10cd45b6 MK |
2968 | i915_queue_hangcheck(dev); |
2969 | } | |
2970 | ||
2971 | void i915_queue_hangcheck(struct drm_device *dev) | |
2972 | { | |
737b1506 | 2973 | struct i915_gpu_error *e = &to_i915(dev)->gpu_error; |
672e7b7c | 2974 | |
d330a953 | 2975 | if (!i915.enable_hangcheck) |
10cd45b6 MK |
2976 | return; |
2977 | ||
737b1506 CW |
2978 | /* Don't continually defer the hangcheck so that it is always run at |
2979 | * least once after work has been scheduled on any ring. Otherwise, | |
2980 | * we will ignore a hung ring if a second ring is kept busy. | |
2981 | */ | |
2982 | ||
2983 | queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work, | |
2984 | round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES)); | |
f65d9421 BG |
2985 | } |
2986 | ||
1c69eb42 | 2987 | static void ibx_irq_reset(struct drm_device *dev) |
91738a95 PZ |
2988 | { |
2989 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2990 | ||
2991 | if (HAS_PCH_NOP(dev)) | |
2992 | return; | |
2993 | ||
f86f3fb0 | 2994 | GEN5_IRQ_RESET(SDE); |
105b122e PZ |
2995 | |
2996 | if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) | |
2997 | I915_WRITE(SERR_INT, 0xffffffff); | |
622364b6 | 2998 | } |
105b122e | 2999 | |
622364b6 PZ |
3000 | /* |
3001 | * SDEIER is also touched by the interrupt handler to work around missed PCH | |
3002 | * interrupts. Hence we can't update it after the interrupt handler is enabled - | |
3003 | * instead we unconditionally enable all PCH interrupt sources here, but then | |
3004 | * only unmask them as needed with SDEIMR. | |
3005 | * | |
3006 | * This function needs to be called before interrupts are enabled. | |
3007 | */ | |
3008 | static void ibx_irq_pre_postinstall(struct drm_device *dev) | |
3009 | { | |
3010 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3011 | ||
3012 | if (HAS_PCH_NOP(dev)) | |
3013 | return; | |
3014 | ||
3015 | WARN_ON(I915_READ(SDEIER) != 0); | |
91738a95 PZ |
3016 | I915_WRITE(SDEIER, 0xffffffff); |
3017 | POSTING_READ(SDEIER); | |
3018 | } | |
3019 | ||
7c4d664e | 3020 | static void gen5_gt_irq_reset(struct drm_device *dev) |
d18ea1b5 DV |
3021 | { |
3022 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3023 | ||
f86f3fb0 | 3024 | GEN5_IRQ_RESET(GT); |
a9d356a6 | 3025 | if (INTEL_INFO(dev)->gen >= 6) |
f86f3fb0 | 3026 | GEN5_IRQ_RESET(GEN6_PM); |
d18ea1b5 DV |
3027 | } |
3028 | ||
1da177e4 LT |
3029 | /* drm_dma.h hooks |
3030 | */ | |
be30b29f | 3031 | static void ironlake_irq_reset(struct drm_device *dev) |
036a4a7d | 3032 | { |
2d1013dd | 3033 | struct drm_i915_private *dev_priv = dev->dev_private; |
036a4a7d | 3034 | |
0c841212 | 3035 | I915_WRITE(HWSTAM, 0xffffffff); |
bdfcdb63 | 3036 | |
f86f3fb0 | 3037 | GEN5_IRQ_RESET(DE); |
c6d954c1 PZ |
3038 | if (IS_GEN7(dev)) |
3039 | I915_WRITE(GEN7_ERR_INT, 0xffffffff); | |
036a4a7d | 3040 | |
7c4d664e | 3041 | gen5_gt_irq_reset(dev); |
c650156a | 3042 | |
1c69eb42 | 3043 | ibx_irq_reset(dev); |
7d99163d | 3044 | } |
c650156a | 3045 | |
70591a41 VS |
3046 | static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) |
3047 | { | |
3048 | enum pipe pipe; | |
3049 | ||
3050 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3051 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3052 | ||
3053 | for_each_pipe(dev_priv, pipe) | |
3054 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
3055 | ||
3056 | GEN5_IRQ_RESET(VLV_); | |
3057 | } | |
3058 | ||
7e231dbe JB |
3059 | static void valleyview_irq_preinstall(struct drm_device *dev) |
3060 | { | |
2d1013dd | 3061 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 3062 | |
7e231dbe JB |
3063 | /* VLV magic */ |
3064 | I915_WRITE(VLV_IMR, 0); | |
3065 | I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); | |
3066 | I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); | |
3067 | I915_WRITE(RING_IMR(BLT_RING_BASE), 0); | |
3068 | ||
7c4d664e | 3069 | gen5_gt_irq_reset(dev); |
7e231dbe | 3070 | |
7c4cde39 | 3071 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); |
7e231dbe | 3072 | |
70591a41 | 3073 | vlv_display_irq_reset(dev_priv); |
7e231dbe JB |
3074 | } |
3075 | ||
d6e3cca3 DV |
3076 | static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv) |
3077 | { | |
3078 | GEN8_IRQ_RESET_NDX(GT, 0); | |
3079 | GEN8_IRQ_RESET_NDX(GT, 1); | |
3080 | GEN8_IRQ_RESET_NDX(GT, 2); | |
3081 | GEN8_IRQ_RESET_NDX(GT, 3); | |
3082 | } | |
3083 | ||
823f6b38 | 3084 | static void gen8_irq_reset(struct drm_device *dev) |
abd58f01 BW |
3085 | { |
3086 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3087 | int pipe; | |
3088 | ||
abd58f01 BW |
3089 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
3090 | POSTING_READ(GEN8_MASTER_IRQ); | |
3091 | ||
d6e3cca3 | 3092 | gen8_gt_irq_reset(dev_priv); |
abd58f01 | 3093 | |
055e393f | 3094 | for_each_pipe(dev_priv, pipe) |
f458ebbc DV |
3095 | if (intel_display_power_is_enabled(dev_priv, |
3096 | POWER_DOMAIN_PIPE(pipe))) | |
813bde43 | 3097 | GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); |
abd58f01 | 3098 | |
f86f3fb0 PZ |
3099 | GEN5_IRQ_RESET(GEN8_DE_PORT_); |
3100 | GEN5_IRQ_RESET(GEN8_DE_MISC_); | |
3101 | GEN5_IRQ_RESET(GEN8_PCU_); | |
abd58f01 | 3102 | |
1c69eb42 | 3103 | ibx_irq_reset(dev); |
abd58f01 | 3104 | } |
09f2344d | 3105 | |
4c6c03be DL |
3106 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, |
3107 | unsigned int pipe_mask) | |
d49bdb0e | 3108 | { |
1180e206 | 3109 | uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; |
d49bdb0e | 3110 | |
13321786 | 3111 | spin_lock_irq(&dev_priv->irq_lock); |
d14c0343 DL |
3112 | if (pipe_mask & 1 << PIPE_A) |
3113 | GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_A, | |
3114 | dev_priv->de_irq_mask[PIPE_A], | |
3115 | ~dev_priv->de_irq_mask[PIPE_A] | extra_ier); | |
4c6c03be DL |
3116 | if (pipe_mask & 1 << PIPE_B) |
3117 | GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, | |
3118 | dev_priv->de_irq_mask[PIPE_B], | |
3119 | ~dev_priv->de_irq_mask[PIPE_B] | extra_ier); | |
3120 | if (pipe_mask & 1 << PIPE_C) | |
3121 | GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, | |
3122 | dev_priv->de_irq_mask[PIPE_C], | |
3123 | ~dev_priv->de_irq_mask[PIPE_C] | extra_ier); | |
13321786 | 3124 | spin_unlock_irq(&dev_priv->irq_lock); |
d49bdb0e PZ |
3125 | } |
3126 | ||
43f328d7 VS |
3127 | static void cherryview_irq_preinstall(struct drm_device *dev) |
3128 | { | |
3129 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43f328d7 VS |
3130 | |
3131 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3132 | POSTING_READ(GEN8_MASTER_IRQ); | |
3133 | ||
d6e3cca3 | 3134 | gen8_gt_irq_reset(dev_priv); |
43f328d7 VS |
3135 | |
3136 | GEN5_IRQ_RESET(GEN8_PCU_); | |
3137 | ||
43f328d7 VS |
3138 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV); |
3139 | ||
70591a41 | 3140 | vlv_display_irq_reset(dev_priv); |
43f328d7 VS |
3141 | } |
3142 | ||
82a28bcf | 3143 | static void ibx_hpd_irq_setup(struct drm_device *dev) |
7fe0b973 | 3144 | { |
2d1013dd | 3145 | struct drm_i915_private *dev_priv = dev->dev_private; |
82a28bcf | 3146 | struct intel_encoder *intel_encoder; |
fee884ed | 3147 | u32 hotplug_irqs, hotplug, enabled_irqs = 0; |
82a28bcf DV |
3148 | |
3149 | if (HAS_PCH_IBX(dev)) { | |
fee884ed | 3150 | hotplug_irqs = SDE_HOTPLUG_MASK; |
b2784e15 | 3151 | for_each_intel_encoder(dev, intel_encoder) |
cd569aed | 3152 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
fee884ed | 3153 | enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin]; |
82a28bcf | 3154 | } else { |
fee884ed | 3155 | hotplug_irqs = SDE_HOTPLUG_MASK_CPT; |
b2784e15 | 3156 | for_each_intel_encoder(dev, intel_encoder) |
cd569aed | 3157 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
fee884ed | 3158 | enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin]; |
82a28bcf | 3159 | } |
7fe0b973 | 3160 | |
fee884ed | 3161 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); |
82a28bcf DV |
3162 | |
3163 | /* | |
3164 | * Enable digital hotplug on the PCH, and configure the DP short pulse | |
3165 | * duration to 2ms (which is the minimum in the Display Port spec) | |
3166 | * | |
3167 | * This register is the same on all known PCH chips. | |
3168 | */ | |
7fe0b973 KP |
3169 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
3170 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); | |
3171 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; | |
3172 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; | |
3173 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; | |
3174 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); | |
3175 | } | |
3176 | ||
d46da437 PZ |
3177 | static void ibx_irq_postinstall(struct drm_device *dev) |
3178 | { | |
2d1013dd | 3179 | struct drm_i915_private *dev_priv = dev->dev_private; |
82a28bcf | 3180 | u32 mask; |
e5868a31 | 3181 | |
692a04cf DV |
3182 | if (HAS_PCH_NOP(dev)) |
3183 | return; | |
3184 | ||
105b122e | 3185 | if (HAS_PCH_IBX(dev)) |
5c673b60 | 3186 | mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; |
105b122e | 3187 | else |
5c673b60 | 3188 | mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; |
8664281b | 3189 | |
337ba017 | 3190 | GEN5_ASSERT_IIR_IS_ZERO(SDEIIR); |
d46da437 | 3191 | I915_WRITE(SDEIMR, ~mask); |
d46da437 PZ |
3192 | } |
3193 | ||
0a9a8c91 DV |
3194 | static void gen5_gt_irq_postinstall(struct drm_device *dev) |
3195 | { | |
3196 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3197 | u32 pm_irqs, gt_irqs; | |
3198 | ||
3199 | pm_irqs = gt_irqs = 0; | |
3200 | ||
3201 | dev_priv->gt_irq_mask = ~0; | |
040d2baa | 3202 | if (HAS_L3_DPF(dev)) { |
0a9a8c91 | 3203 | /* L3 parity interrupt is always unmasked. */ |
35a85ac6 BW |
3204 | dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev); |
3205 | gt_irqs |= GT_PARITY_ERROR(dev); | |
0a9a8c91 DV |
3206 | } |
3207 | ||
3208 | gt_irqs |= GT_RENDER_USER_INTERRUPT; | |
3209 | if (IS_GEN5(dev)) { | |
3210 | gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | | |
3211 | ILK_BSD_USER_INTERRUPT; | |
3212 | } else { | |
3213 | gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; | |
3214 | } | |
3215 | ||
35079899 | 3216 | GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); |
0a9a8c91 DV |
3217 | |
3218 | if (INTEL_INFO(dev)->gen >= 6) { | |
78e68d36 ID |
3219 | /* |
3220 | * RPS interrupts will get enabled/disabled on demand when RPS | |
3221 | * itself is enabled/disabled. | |
3222 | */ | |
0a9a8c91 DV |
3223 | if (HAS_VEBOX(dev)) |
3224 | pm_irqs |= PM_VEBOX_USER_INTERRUPT; | |
3225 | ||
605cd25b | 3226 | dev_priv->pm_irq_mask = 0xffffffff; |
35079899 | 3227 | GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs); |
0a9a8c91 DV |
3228 | } |
3229 | } | |
3230 | ||
f71d4af4 | 3231 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d | 3232 | { |
2d1013dd | 3233 | struct drm_i915_private *dev_priv = dev->dev_private; |
8e76f8dc PZ |
3234 | u32 display_mask, extra_mask; |
3235 | ||
3236 | if (INTEL_INFO(dev)->gen >= 7) { | |
3237 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | | |
3238 | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | | |
3239 | DE_PLANEB_FLIP_DONE_IVB | | |
5c673b60 | 3240 | DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB); |
8e76f8dc | 3241 | extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | |
5c673b60 | 3242 | DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB); |
8e76f8dc PZ |
3243 | } else { |
3244 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | | |
3245 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | | |
5b3a856b | 3246 | DE_AUX_CHANNEL_A | |
5b3a856b DV |
3247 | DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE | |
3248 | DE_POISON); | |
5c673b60 DV |
3249 | extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT | |
3250 | DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN; | |
8e76f8dc | 3251 | } |
036a4a7d | 3252 | |
1ec14ad3 | 3253 | dev_priv->irq_mask = ~display_mask; |
036a4a7d | 3254 | |
0c841212 PZ |
3255 | I915_WRITE(HWSTAM, 0xeffe); |
3256 | ||
622364b6 PZ |
3257 | ibx_irq_pre_postinstall(dev); |
3258 | ||
35079899 | 3259 | GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); |
036a4a7d | 3260 | |
0a9a8c91 | 3261 | gen5_gt_irq_postinstall(dev); |
036a4a7d | 3262 | |
d46da437 | 3263 | ibx_irq_postinstall(dev); |
7fe0b973 | 3264 | |
f97108d1 | 3265 | if (IS_IRONLAKE_M(dev)) { |
6005ce42 DV |
3266 | /* Enable PCU event interrupts |
3267 | * | |
3268 | * spinlocking not required here for correctness since interrupt | |
4bc9d430 DV |
3269 | * setup is guaranteed to run in single-threaded context. But we |
3270 | * need it to make the assert_spin_locked happy. */ | |
d6207435 | 3271 | spin_lock_irq(&dev_priv->irq_lock); |
f97108d1 | 3272 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); |
d6207435 | 3273 | spin_unlock_irq(&dev_priv->irq_lock); |
f97108d1 JB |
3274 | } |
3275 | ||
036a4a7d ZW |
3276 | return 0; |
3277 | } | |
3278 | ||
f8b79e58 ID |
3279 | static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv) |
3280 | { | |
3281 | u32 pipestat_mask; | |
3282 | u32 iir_mask; | |
120dda4f | 3283 | enum pipe pipe; |
f8b79e58 ID |
3284 | |
3285 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | | |
3286 | PIPE_FIFO_UNDERRUN_STATUS; | |
3287 | ||
120dda4f VS |
3288 | for_each_pipe(dev_priv, pipe) |
3289 | I915_WRITE(PIPESTAT(pipe), pipestat_mask); | |
f8b79e58 ID |
3290 | POSTING_READ(PIPESTAT(PIPE_A)); |
3291 | ||
3292 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3293 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3294 | ||
120dda4f VS |
3295 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
3296 | for_each_pipe(dev_priv, pipe) | |
3297 | i915_enable_pipestat(dev_priv, pipe, pipestat_mask); | |
f8b79e58 ID |
3298 | |
3299 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3300 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3301 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
120dda4f VS |
3302 | if (IS_CHERRYVIEW(dev_priv)) |
3303 | iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
f8b79e58 ID |
3304 | dev_priv->irq_mask &= ~iir_mask; |
3305 | ||
3306 | I915_WRITE(VLV_IIR, iir_mask); | |
3307 | I915_WRITE(VLV_IIR, iir_mask); | |
f8b79e58 | 3308 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); |
76e41860 VS |
3309 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
3310 | POSTING_READ(VLV_IMR); | |
f8b79e58 ID |
3311 | } |
3312 | ||
3313 | static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv) | |
3314 | { | |
3315 | u32 pipestat_mask; | |
3316 | u32 iir_mask; | |
120dda4f | 3317 | enum pipe pipe; |
f8b79e58 ID |
3318 | |
3319 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3320 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
6c7fba04 | 3321 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; |
120dda4f VS |
3322 | if (IS_CHERRYVIEW(dev_priv)) |
3323 | iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
f8b79e58 ID |
3324 | |
3325 | dev_priv->irq_mask |= iir_mask; | |
f8b79e58 | 3326 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
76e41860 | 3327 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); |
f8b79e58 ID |
3328 | I915_WRITE(VLV_IIR, iir_mask); |
3329 | I915_WRITE(VLV_IIR, iir_mask); | |
3330 | POSTING_READ(VLV_IIR); | |
3331 | ||
3332 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3333 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3334 | ||
120dda4f VS |
3335 | i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
3336 | for_each_pipe(dev_priv, pipe) | |
3337 | i915_disable_pipestat(dev_priv, pipe, pipestat_mask); | |
f8b79e58 ID |
3338 | |
3339 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | | |
3340 | PIPE_FIFO_UNDERRUN_STATUS; | |
120dda4f VS |
3341 | |
3342 | for_each_pipe(dev_priv, pipe) | |
3343 | I915_WRITE(PIPESTAT(pipe), pipestat_mask); | |
f8b79e58 ID |
3344 | POSTING_READ(PIPESTAT(PIPE_A)); |
3345 | } | |
3346 | ||
3347 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) | |
3348 | { | |
3349 | assert_spin_locked(&dev_priv->irq_lock); | |
3350 | ||
3351 | if (dev_priv->display_irqs_enabled) | |
3352 | return; | |
3353 | ||
3354 | dev_priv->display_irqs_enabled = true; | |
3355 | ||
950eabaf | 3356 | if (intel_irqs_enabled(dev_priv)) |
f8b79e58 ID |
3357 | valleyview_display_irqs_install(dev_priv); |
3358 | } | |
3359 | ||
3360 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) | |
3361 | { | |
3362 | assert_spin_locked(&dev_priv->irq_lock); | |
3363 | ||
3364 | if (!dev_priv->display_irqs_enabled) | |
3365 | return; | |
3366 | ||
3367 | dev_priv->display_irqs_enabled = false; | |
3368 | ||
950eabaf | 3369 | if (intel_irqs_enabled(dev_priv)) |
f8b79e58 ID |
3370 | valleyview_display_irqs_uninstall(dev_priv); |
3371 | } | |
3372 | ||
0e6c9a9e | 3373 | static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) |
7e231dbe | 3374 | { |
f8b79e58 | 3375 | dev_priv->irq_mask = ~0; |
7e231dbe | 3376 | |
20afbda2 DV |
3377 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3378 | POSTING_READ(PORT_HOTPLUG_EN); | |
3379 | ||
7e231dbe | 3380 | I915_WRITE(VLV_IIR, 0xffffffff); |
76e41860 VS |
3381 | I915_WRITE(VLV_IIR, 0xffffffff); |
3382 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); | |
3383 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); | |
3384 | POSTING_READ(VLV_IMR); | |
7e231dbe | 3385 | |
b79480ba DV |
3386 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3387 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3388 | spin_lock_irq(&dev_priv->irq_lock); |
f8b79e58 ID |
3389 | if (dev_priv->display_irqs_enabled) |
3390 | valleyview_display_irqs_install(dev_priv); | |
d6207435 | 3391 | spin_unlock_irq(&dev_priv->irq_lock); |
0e6c9a9e VS |
3392 | } |
3393 | ||
3394 | static int valleyview_irq_postinstall(struct drm_device *dev) | |
3395 | { | |
3396 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3397 | ||
3398 | vlv_display_irq_postinstall(dev_priv); | |
7e231dbe | 3399 | |
0a9a8c91 | 3400 | gen5_gt_irq_postinstall(dev); |
7e231dbe JB |
3401 | |
3402 | /* ack & enable invalid PTE error interrupts */ | |
3403 | #if 0 /* FIXME: add support to irq handler for checking these bits */ | |
3404 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); | |
3405 | I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); | |
3406 | #endif | |
3407 | ||
3408 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); | |
20afbda2 DV |
3409 | |
3410 | return 0; | |
3411 | } | |
3412 | ||
abd58f01 BW |
3413 | static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) |
3414 | { | |
abd58f01 BW |
3415 | /* These are interrupts we'll toggle with the ring mask register */ |
3416 | uint32_t gt_interrupts[] = { | |
3417 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | | |
73d477f6 | 3418 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT | |
abd58f01 | 3419 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT | |
73d477f6 OM |
3420 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT | |
3421 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT, | |
abd58f01 | 3422 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
73d477f6 OM |
3423 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
3424 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT | | |
3425 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT, | |
abd58f01 | 3426 | 0, |
73d477f6 OM |
3427 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
3428 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
abd58f01 BW |
3429 | }; |
3430 | ||
0961021a | 3431 | dev_priv->pm_irq_mask = 0xffffffff; |
9a2d2d87 D |
3432 | GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]); |
3433 | GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]); | |
78e68d36 ID |
3434 | /* |
3435 | * RPS interrupts will get enabled/disabled on demand when RPS itself | |
3436 | * is enabled/disabled. | |
3437 | */ | |
3438 | GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0); | |
9a2d2d87 | 3439 | GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]); |
abd58f01 BW |
3440 | } |
3441 | ||
3442 | static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) | |
3443 | { | |
770de83d DL |
3444 | uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE; |
3445 | uint32_t de_pipe_enables; | |
abd58f01 | 3446 | int pipe; |
88e04703 | 3447 | u32 aux_en = GEN8_AUX_CHANNEL_A; |
770de83d | 3448 | |
88e04703 | 3449 | if (IS_GEN9(dev_priv)) { |
770de83d DL |
3450 | de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE | |
3451 | GEN9_DE_PIPE_IRQ_FAULT_ERRORS; | |
88e04703 JB |
3452 | aux_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | |
3453 | GEN9_AUX_CHANNEL_D; | |
3454 | } else | |
770de83d DL |
3455 | de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE | |
3456 | GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
3457 | ||
3458 | de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | | |
3459 | GEN8_PIPE_FIFO_UNDERRUN; | |
3460 | ||
13b3a0a7 DV |
3461 | dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; |
3462 | dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; | |
3463 | dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; | |
abd58f01 | 3464 | |
055e393f | 3465 | for_each_pipe(dev_priv, pipe) |
f458ebbc | 3466 | if (intel_display_power_is_enabled(dev_priv, |
813bde43 PZ |
3467 | POWER_DOMAIN_PIPE(pipe))) |
3468 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, | |
3469 | dev_priv->de_irq_mask[pipe], | |
3470 | de_pipe_enables); | |
abd58f01 | 3471 | |
88e04703 | 3472 | GEN5_IRQ_INIT(GEN8_DE_PORT_, ~aux_en, aux_en); |
abd58f01 BW |
3473 | } |
3474 | ||
3475 | static int gen8_irq_postinstall(struct drm_device *dev) | |
3476 | { | |
3477 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3478 | ||
622364b6 PZ |
3479 | ibx_irq_pre_postinstall(dev); |
3480 | ||
abd58f01 BW |
3481 | gen8_gt_irq_postinstall(dev_priv); |
3482 | gen8_de_irq_postinstall(dev_priv); | |
3483 | ||
3484 | ibx_irq_postinstall(dev); | |
3485 | ||
3486 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); | |
3487 | POSTING_READ(GEN8_MASTER_IRQ); | |
3488 | ||
3489 | return 0; | |
3490 | } | |
3491 | ||
43f328d7 VS |
3492 | static int cherryview_irq_postinstall(struct drm_device *dev) |
3493 | { | |
3494 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43f328d7 | 3495 | |
c2b66797 | 3496 | vlv_display_irq_postinstall(dev_priv); |
43f328d7 VS |
3497 | |
3498 | gen8_gt_irq_postinstall(dev_priv); | |
3499 | ||
3500 | I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE); | |
3501 | POSTING_READ(GEN8_MASTER_IRQ); | |
3502 | ||
3503 | return 0; | |
3504 | } | |
3505 | ||
abd58f01 BW |
3506 | static void gen8_irq_uninstall(struct drm_device *dev) |
3507 | { | |
3508 | struct drm_i915_private *dev_priv = dev->dev_private; | |
abd58f01 BW |
3509 | |
3510 | if (!dev_priv) | |
3511 | return; | |
3512 | ||
823f6b38 | 3513 | gen8_irq_reset(dev); |
abd58f01 BW |
3514 | } |
3515 | ||
8ea0be4f VS |
3516 | static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv) |
3517 | { | |
3518 | /* Interrupt setup is already guaranteed to be single-threaded, this is | |
3519 | * just to make the assert_spin_locked check happy. */ | |
3520 | spin_lock_irq(&dev_priv->irq_lock); | |
3521 | if (dev_priv->display_irqs_enabled) | |
3522 | valleyview_display_irqs_uninstall(dev_priv); | |
3523 | spin_unlock_irq(&dev_priv->irq_lock); | |
3524 | ||
3525 | vlv_display_irq_reset(dev_priv); | |
3526 | ||
c352d1ba | 3527 | dev_priv->irq_mask = ~0; |
8ea0be4f VS |
3528 | } |
3529 | ||
7e231dbe JB |
3530 | static void valleyview_irq_uninstall(struct drm_device *dev) |
3531 | { | |
2d1013dd | 3532 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
3533 | |
3534 | if (!dev_priv) | |
3535 | return; | |
3536 | ||
843d0e7d ID |
3537 | I915_WRITE(VLV_MASTER_IER, 0); |
3538 | ||
893fce8e VS |
3539 | gen5_gt_irq_reset(dev); |
3540 | ||
7e231dbe | 3541 | I915_WRITE(HWSTAM, 0xffffffff); |
f8b79e58 | 3542 | |
8ea0be4f | 3543 | vlv_display_irq_uninstall(dev_priv); |
7e231dbe JB |
3544 | } |
3545 | ||
43f328d7 VS |
3546 | static void cherryview_irq_uninstall(struct drm_device *dev) |
3547 | { | |
3548 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43f328d7 VS |
3549 | |
3550 | if (!dev_priv) | |
3551 | return; | |
3552 | ||
3553 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3554 | POSTING_READ(GEN8_MASTER_IRQ); | |
3555 | ||
a2c30fba | 3556 | gen8_gt_irq_reset(dev_priv); |
43f328d7 | 3557 | |
a2c30fba | 3558 | GEN5_IRQ_RESET(GEN8_PCU_); |
43f328d7 | 3559 | |
c2b66797 | 3560 | vlv_display_irq_uninstall(dev_priv); |
43f328d7 VS |
3561 | } |
3562 | ||
f71d4af4 | 3563 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d | 3564 | { |
2d1013dd | 3565 | struct drm_i915_private *dev_priv = dev->dev_private; |
4697995b JB |
3566 | |
3567 | if (!dev_priv) | |
3568 | return; | |
3569 | ||
be30b29f | 3570 | ironlake_irq_reset(dev); |
036a4a7d ZW |
3571 | } |
3572 | ||
a266c7d5 | 3573 | static void i8xx_irq_preinstall(struct drm_device * dev) |
1da177e4 | 3574 | { |
2d1013dd | 3575 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 3576 | int pipe; |
91e3738e | 3577 | |
055e393f | 3578 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 | 3579 | I915_WRITE(PIPESTAT(pipe), 0); |
a266c7d5 CW |
3580 | I915_WRITE16(IMR, 0xffff); |
3581 | I915_WRITE16(IER, 0x0); | |
3582 | POSTING_READ16(IER); | |
c2798b19 CW |
3583 | } |
3584 | ||
3585 | static int i8xx_irq_postinstall(struct drm_device *dev) | |
3586 | { | |
2d1013dd | 3587 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 | 3588 | |
c2798b19 CW |
3589 | I915_WRITE16(EMR, |
3590 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); | |
3591 | ||
3592 | /* Unmask the interrupts that we always want on. */ | |
3593 | dev_priv->irq_mask = | |
3594 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3595 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3596 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3597 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3598 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3599 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
3600 | ||
3601 | I915_WRITE16(IER, | |
3602 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3603 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3604 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
3605 | I915_USER_INTERRUPT); | |
3606 | POSTING_READ16(IER); | |
3607 | ||
379ef82d DV |
3608 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3609 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3610 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
3611 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3612 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 3613 | spin_unlock_irq(&dev_priv->irq_lock); |
379ef82d | 3614 | |
c2798b19 CW |
3615 | return 0; |
3616 | } | |
3617 | ||
90a72f87 VS |
3618 | /* |
3619 | * Returns true when a page flip has completed. | |
3620 | */ | |
3621 | static bool i8xx_handle_vblank(struct drm_device *dev, | |
1f1c2e24 | 3622 | int plane, int pipe, u32 iir) |
90a72f87 | 3623 | { |
2d1013dd | 3624 | struct drm_i915_private *dev_priv = dev->dev_private; |
1f1c2e24 | 3625 | u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
90a72f87 | 3626 | |
8d7849db | 3627 | if (!intel_pipe_handle_vblank(dev, pipe)) |
90a72f87 VS |
3628 | return false; |
3629 | ||
3630 | if ((iir & flip_pending) == 0) | |
d6bbafa1 | 3631 | goto check_page_flip; |
90a72f87 | 3632 | |
90a72f87 VS |
3633 | /* We detect FlipDone by looking for the change in PendingFlip from '1' |
3634 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3635 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3636 | * the flip is completed (no longer pending). Since this doesn't raise | |
3637 | * an interrupt per se, we watch for the change at vblank. | |
3638 | */ | |
3639 | if (I915_READ16(ISR) & flip_pending) | |
d6bbafa1 | 3640 | goto check_page_flip; |
90a72f87 | 3641 | |
7d47559e | 3642 | intel_prepare_page_flip(dev, plane); |
90a72f87 | 3643 | intel_finish_page_flip(dev, pipe); |
90a72f87 | 3644 | return true; |
d6bbafa1 CW |
3645 | |
3646 | check_page_flip: | |
3647 | intel_check_page_flip(dev, pipe); | |
3648 | return false; | |
90a72f87 VS |
3649 | } |
3650 | ||
ff1f525e | 3651 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
c2798b19 | 3652 | { |
45a83f84 | 3653 | struct drm_device *dev = arg; |
2d1013dd | 3654 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
3655 | u16 iir, new_iir; |
3656 | u32 pipe_stats[2]; | |
c2798b19 CW |
3657 | int pipe; |
3658 | u16 flip_mask = | |
3659 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3660 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
3661 | ||
2dd2a883 ID |
3662 | if (!intel_irqs_enabled(dev_priv)) |
3663 | return IRQ_NONE; | |
3664 | ||
c2798b19 CW |
3665 | iir = I915_READ16(IIR); |
3666 | if (iir == 0) | |
3667 | return IRQ_NONE; | |
3668 | ||
3669 | while (iir & ~flip_mask) { | |
3670 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3671 | * have been cleared after the pipestat interrupt was received. | |
3672 | * It doesn't set the bit in iir again, but it still produces | |
3673 | * interrupts (for non-MSI). | |
3674 | */ | |
222c7f51 | 3675 | spin_lock(&dev_priv->irq_lock); |
c2798b19 | 3676 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 3677 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
c2798b19 | 3678 | |
055e393f | 3679 | for_each_pipe(dev_priv, pipe) { |
c2798b19 CW |
3680 | int reg = PIPESTAT(pipe); |
3681 | pipe_stats[pipe] = I915_READ(reg); | |
3682 | ||
3683 | /* | |
3684 | * Clear the PIPE*STAT regs before the IIR | |
3685 | */ | |
2d9d2b0b | 3686 | if (pipe_stats[pipe] & 0x8000ffff) |
c2798b19 | 3687 | I915_WRITE(reg, pipe_stats[pipe]); |
c2798b19 | 3688 | } |
222c7f51 | 3689 | spin_unlock(&dev_priv->irq_lock); |
c2798b19 CW |
3690 | |
3691 | I915_WRITE16(IIR, iir & ~flip_mask); | |
3692 | new_iir = I915_READ16(IIR); /* Flush posted writes */ | |
3693 | ||
c2798b19 CW |
3694 | if (iir & I915_USER_INTERRUPT) |
3695 | notify_ring(dev, &dev_priv->ring[RCS]); | |
3696 | ||
055e393f | 3697 | for_each_pipe(dev_priv, pipe) { |
1f1c2e24 | 3698 | int plane = pipe; |
3a77c4c4 | 3699 | if (HAS_FBC(dev)) |
1f1c2e24 VS |
3700 | plane = !plane; |
3701 | ||
4356d586 | 3702 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
1f1c2e24 VS |
3703 | i8xx_handle_vblank(dev, plane, pipe, iir)) |
3704 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
c2798b19 | 3705 | |
4356d586 | 3706 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
277de95e | 3707 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b | 3708 | |
1f7247c0 DV |
3709 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
3710 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
3711 | pipe); | |
4356d586 | 3712 | } |
c2798b19 CW |
3713 | |
3714 | iir = new_iir; | |
3715 | } | |
3716 | ||
3717 | return IRQ_HANDLED; | |
3718 | } | |
3719 | ||
3720 | static void i8xx_irq_uninstall(struct drm_device * dev) | |
3721 | { | |
2d1013dd | 3722 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
3723 | int pipe; |
3724 | ||
055e393f | 3725 | for_each_pipe(dev_priv, pipe) { |
c2798b19 CW |
3726 | /* Clear enable bits; then clear status bits */ |
3727 | I915_WRITE(PIPESTAT(pipe), 0); | |
3728 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); | |
3729 | } | |
3730 | I915_WRITE16(IMR, 0xffff); | |
3731 | I915_WRITE16(IER, 0x0); | |
3732 | I915_WRITE16(IIR, I915_READ16(IIR)); | |
3733 | } | |
3734 | ||
a266c7d5 CW |
3735 | static void i915_irq_preinstall(struct drm_device * dev) |
3736 | { | |
2d1013dd | 3737 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3738 | int pipe; |
3739 | ||
a266c7d5 CW |
3740 | if (I915_HAS_HOTPLUG(dev)) { |
3741 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3742 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3743 | } | |
3744 | ||
00d98ebd | 3745 | I915_WRITE16(HWSTAM, 0xeffe); |
055e393f | 3746 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
3747 | I915_WRITE(PIPESTAT(pipe), 0); |
3748 | I915_WRITE(IMR, 0xffffffff); | |
3749 | I915_WRITE(IER, 0x0); | |
3750 | POSTING_READ(IER); | |
3751 | } | |
3752 | ||
3753 | static int i915_irq_postinstall(struct drm_device *dev) | |
3754 | { | |
2d1013dd | 3755 | struct drm_i915_private *dev_priv = dev->dev_private; |
38bde180 | 3756 | u32 enable_mask; |
a266c7d5 | 3757 | |
38bde180 CW |
3758 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
3759 | ||
3760 | /* Unmask the interrupts that we always want on. */ | |
3761 | dev_priv->irq_mask = | |
3762 | ~(I915_ASLE_INTERRUPT | | |
3763 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3764 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3765 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3766 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3767 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3768 | ||
3769 | enable_mask = | |
3770 | I915_ASLE_INTERRUPT | | |
3771 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3772 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3773 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
3774 | I915_USER_INTERRUPT; | |
3775 | ||
a266c7d5 | 3776 | if (I915_HAS_HOTPLUG(dev)) { |
20afbda2 DV |
3777 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3778 | POSTING_READ(PORT_HOTPLUG_EN); | |
3779 | ||
a266c7d5 CW |
3780 | /* Enable in IER... */ |
3781 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
3782 | /* and unmask in IMR */ | |
3783 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; | |
3784 | } | |
3785 | ||
a266c7d5 CW |
3786 | I915_WRITE(IMR, dev_priv->irq_mask); |
3787 | I915_WRITE(IER, enable_mask); | |
3788 | POSTING_READ(IER); | |
3789 | ||
f49e38dd | 3790 | i915_enable_asle_pipestat(dev); |
20afbda2 | 3791 | |
379ef82d DV |
3792 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3793 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3794 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
3795 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3796 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 3797 | spin_unlock_irq(&dev_priv->irq_lock); |
379ef82d | 3798 | |
20afbda2 DV |
3799 | return 0; |
3800 | } | |
3801 | ||
90a72f87 VS |
3802 | /* |
3803 | * Returns true when a page flip has completed. | |
3804 | */ | |
3805 | static bool i915_handle_vblank(struct drm_device *dev, | |
3806 | int plane, int pipe, u32 iir) | |
3807 | { | |
2d1013dd | 3808 | struct drm_i915_private *dev_priv = dev->dev_private; |
90a72f87 VS |
3809 | u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
3810 | ||
8d7849db | 3811 | if (!intel_pipe_handle_vblank(dev, pipe)) |
90a72f87 VS |
3812 | return false; |
3813 | ||
3814 | if ((iir & flip_pending) == 0) | |
d6bbafa1 | 3815 | goto check_page_flip; |
90a72f87 | 3816 | |
90a72f87 VS |
3817 | /* We detect FlipDone by looking for the change in PendingFlip from '1' |
3818 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3819 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3820 | * the flip is completed (no longer pending). Since this doesn't raise | |
3821 | * an interrupt per se, we watch for the change at vblank. | |
3822 | */ | |
3823 | if (I915_READ(ISR) & flip_pending) | |
d6bbafa1 | 3824 | goto check_page_flip; |
90a72f87 | 3825 | |
7d47559e | 3826 | intel_prepare_page_flip(dev, plane); |
90a72f87 | 3827 | intel_finish_page_flip(dev, pipe); |
90a72f87 | 3828 | return true; |
d6bbafa1 CW |
3829 | |
3830 | check_page_flip: | |
3831 | intel_check_page_flip(dev, pipe); | |
3832 | return false; | |
90a72f87 VS |
3833 | } |
3834 | ||
ff1f525e | 3835 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
a266c7d5 | 3836 | { |
45a83f84 | 3837 | struct drm_device *dev = arg; |
2d1013dd | 3838 | struct drm_i915_private *dev_priv = dev->dev_private; |
8291ee90 | 3839 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
38bde180 CW |
3840 | u32 flip_mask = |
3841 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3842 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
38bde180 | 3843 | int pipe, ret = IRQ_NONE; |
a266c7d5 | 3844 | |
2dd2a883 ID |
3845 | if (!intel_irqs_enabled(dev_priv)) |
3846 | return IRQ_NONE; | |
3847 | ||
a266c7d5 | 3848 | iir = I915_READ(IIR); |
38bde180 CW |
3849 | do { |
3850 | bool irq_received = (iir & ~flip_mask) != 0; | |
8291ee90 | 3851 | bool blc_event = false; |
a266c7d5 CW |
3852 | |
3853 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3854 | * have been cleared after the pipestat interrupt was received. | |
3855 | * It doesn't set the bit in iir again, but it still produces | |
3856 | * interrupts (for non-MSI). | |
3857 | */ | |
222c7f51 | 3858 | spin_lock(&dev_priv->irq_lock); |
a266c7d5 | 3859 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 3860 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
a266c7d5 | 3861 | |
055e393f | 3862 | for_each_pipe(dev_priv, pipe) { |
a266c7d5 CW |
3863 | int reg = PIPESTAT(pipe); |
3864 | pipe_stats[pipe] = I915_READ(reg); | |
3865 | ||
38bde180 | 3866 | /* Clear the PIPE*STAT regs before the IIR */ |
a266c7d5 | 3867 | if (pipe_stats[pipe] & 0x8000ffff) { |
a266c7d5 | 3868 | I915_WRITE(reg, pipe_stats[pipe]); |
38bde180 | 3869 | irq_received = true; |
a266c7d5 CW |
3870 | } |
3871 | } | |
222c7f51 | 3872 | spin_unlock(&dev_priv->irq_lock); |
a266c7d5 CW |
3873 | |
3874 | if (!irq_received) | |
3875 | break; | |
3876 | ||
a266c7d5 | 3877 | /* Consume port. Then clear IIR or we'll miss events */ |
16c6c56b VS |
3878 | if (I915_HAS_HOTPLUG(dev) && |
3879 | iir & I915_DISPLAY_PORT_INTERRUPT) | |
3880 | i9xx_hpd_irq_handler(dev); | |
a266c7d5 | 3881 | |
38bde180 | 3882 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
3883 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
3884 | ||
a266c7d5 CW |
3885 | if (iir & I915_USER_INTERRUPT) |
3886 | notify_ring(dev, &dev_priv->ring[RCS]); | |
a266c7d5 | 3887 | |
055e393f | 3888 | for_each_pipe(dev_priv, pipe) { |
38bde180 | 3889 | int plane = pipe; |
3a77c4c4 | 3890 | if (HAS_FBC(dev)) |
38bde180 | 3891 | plane = !plane; |
90a72f87 | 3892 | |
8291ee90 | 3893 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
3894 | i915_handle_vblank(dev, plane, pipe, iir)) |
3895 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
a266c7d5 CW |
3896 | |
3897 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
3898 | blc_event = true; | |
4356d586 DV |
3899 | |
3900 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 3901 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b | 3902 | |
1f7247c0 DV |
3903 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
3904 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
3905 | pipe); | |
a266c7d5 CW |
3906 | } |
3907 | ||
a266c7d5 CW |
3908 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
3909 | intel_opregion_asle_intr(dev); | |
3910 | ||
3911 | /* With MSI, interrupts are only generated when iir | |
3912 | * transitions from zero to nonzero. If another bit got | |
3913 | * set while we were handling the existing iir bits, then | |
3914 | * we would never get another interrupt. | |
3915 | * | |
3916 | * This is fine on non-MSI as well, as if we hit this path | |
3917 | * we avoid exiting the interrupt handler only to generate | |
3918 | * another one. | |
3919 | * | |
3920 | * Note that for MSI this could cause a stray interrupt report | |
3921 | * if an interrupt landed in the time between writing IIR and | |
3922 | * the posting read. This should be rare enough to never | |
3923 | * trigger the 99% of 100,000 interrupts test for disabling | |
3924 | * stray interrupts. | |
3925 | */ | |
38bde180 | 3926 | ret = IRQ_HANDLED; |
a266c7d5 | 3927 | iir = new_iir; |
38bde180 | 3928 | } while (iir & ~flip_mask); |
a266c7d5 CW |
3929 | |
3930 | return ret; | |
3931 | } | |
3932 | ||
3933 | static void i915_irq_uninstall(struct drm_device * dev) | |
3934 | { | |
2d1013dd | 3935 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3936 | int pipe; |
3937 | ||
a266c7d5 CW |
3938 | if (I915_HAS_HOTPLUG(dev)) { |
3939 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3940 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3941 | } | |
3942 | ||
00d98ebd | 3943 | I915_WRITE16(HWSTAM, 0xffff); |
055e393f | 3944 | for_each_pipe(dev_priv, pipe) { |
55b39755 | 3945 | /* Clear enable bits; then clear status bits */ |
a266c7d5 | 3946 | I915_WRITE(PIPESTAT(pipe), 0); |
55b39755 CW |
3947 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
3948 | } | |
a266c7d5 CW |
3949 | I915_WRITE(IMR, 0xffffffff); |
3950 | I915_WRITE(IER, 0x0); | |
3951 | ||
a266c7d5 CW |
3952 | I915_WRITE(IIR, I915_READ(IIR)); |
3953 | } | |
3954 | ||
3955 | static void i965_irq_preinstall(struct drm_device * dev) | |
3956 | { | |
2d1013dd | 3957 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3958 | int pipe; |
3959 | ||
adca4730 CW |
3960 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3961 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
3962 | |
3963 | I915_WRITE(HWSTAM, 0xeffe); | |
055e393f | 3964 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
3965 | I915_WRITE(PIPESTAT(pipe), 0); |
3966 | I915_WRITE(IMR, 0xffffffff); | |
3967 | I915_WRITE(IER, 0x0); | |
3968 | POSTING_READ(IER); | |
3969 | } | |
3970 | ||
3971 | static int i965_irq_postinstall(struct drm_device *dev) | |
3972 | { | |
2d1013dd | 3973 | struct drm_i915_private *dev_priv = dev->dev_private; |
bbba0a97 | 3974 | u32 enable_mask; |
a266c7d5 CW |
3975 | u32 error_mask; |
3976 | ||
a266c7d5 | 3977 | /* Unmask the interrupts that we always want on. */ |
bbba0a97 | 3978 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
adca4730 | 3979 | I915_DISPLAY_PORT_INTERRUPT | |
bbba0a97 CW |
3980 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
3981 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3982 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3983 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3984 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3985 | ||
3986 | enable_mask = ~dev_priv->irq_mask; | |
21ad8330 VS |
3987 | enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
3988 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); | |
bbba0a97 CW |
3989 | enable_mask |= I915_USER_INTERRUPT; |
3990 | ||
3991 | if (IS_G4X(dev)) | |
3992 | enable_mask |= I915_BSD_USER_INTERRUPT; | |
a266c7d5 | 3993 | |
b79480ba DV |
3994 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3995 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3996 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
3997 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
3998 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
3999 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 4000 | spin_unlock_irq(&dev_priv->irq_lock); |
a266c7d5 | 4001 | |
a266c7d5 CW |
4002 | /* |
4003 | * Enable some error detection, note the instruction error mask | |
4004 | * bit is reserved, so we leave it masked. | |
4005 | */ | |
4006 | if (IS_G4X(dev)) { | |
4007 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
4008 | GM45_ERROR_MEM_PRIV | | |
4009 | GM45_ERROR_CP_PRIV | | |
4010 | I915_ERROR_MEMORY_REFRESH); | |
4011 | } else { | |
4012 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
4013 | I915_ERROR_MEMORY_REFRESH); | |
4014 | } | |
4015 | I915_WRITE(EMR, error_mask); | |
4016 | ||
4017 | I915_WRITE(IMR, dev_priv->irq_mask); | |
4018 | I915_WRITE(IER, enable_mask); | |
4019 | POSTING_READ(IER); | |
4020 | ||
20afbda2 DV |
4021 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
4022 | POSTING_READ(PORT_HOTPLUG_EN); | |
4023 | ||
f49e38dd | 4024 | i915_enable_asle_pipestat(dev); |
20afbda2 DV |
4025 | |
4026 | return 0; | |
4027 | } | |
4028 | ||
bac56d5b | 4029 | static void i915_hpd_irq_setup(struct drm_device *dev) |
20afbda2 | 4030 | { |
2d1013dd | 4031 | struct drm_i915_private *dev_priv = dev->dev_private; |
cd569aed | 4032 | struct intel_encoder *intel_encoder; |
20afbda2 DV |
4033 | u32 hotplug_en; |
4034 | ||
b5ea2d56 DV |
4035 | assert_spin_locked(&dev_priv->irq_lock); |
4036 | ||
778eb334 VS |
4037 | hotplug_en = I915_READ(PORT_HOTPLUG_EN); |
4038 | hotplug_en &= ~HOTPLUG_INT_EN_MASK; | |
4039 | /* Note HDMI and DP share hotplug bits */ | |
4040 | /* enable bits are the same for all generations */ | |
4041 | for_each_intel_encoder(dev, intel_encoder) | |
4042 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) | |
4043 | hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin]; | |
4044 | /* Programming the CRT detection parameters tends | |
4045 | to generate a spurious hotplug event about three | |
4046 | seconds later. So just do it once. | |
4047 | */ | |
4048 | if (IS_G4X(dev)) | |
4049 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
4050 | hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK; | |
4051 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; | |
4052 | ||
4053 | /* Ignore TV since it's buggy */ | |
4054 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
a266c7d5 CW |
4055 | } |
4056 | ||
ff1f525e | 4057 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
a266c7d5 | 4058 | { |
45a83f84 | 4059 | struct drm_device *dev = arg; |
2d1013dd | 4060 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4061 | u32 iir, new_iir; |
4062 | u32 pipe_stats[I915_MAX_PIPES]; | |
a266c7d5 | 4063 | int ret = IRQ_NONE, pipe; |
21ad8330 VS |
4064 | u32 flip_mask = |
4065 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4066 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
a266c7d5 | 4067 | |
2dd2a883 ID |
4068 | if (!intel_irqs_enabled(dev_priv)) |
4069 | return IRQ_NONE; | |
4070 | ||
a266c7d5 CW |
4071 | iir = I915_READ(IIR); |
4072 | ||
a266c7d5 | 4073 | for (;;) { |
501e01d7 | 4074 | bool irq_received = (iir & ~flip_mask) != 0; |
2c8ba29f CW |
4075 | bool blc_event = false; |
4076 | ||
a266c7d5 CW |
4077 | /* Can't rely on pipestat interrupt bit in iir as it might |
4078 | * have been cleared after the pipestat interrupt was received. | |
4079 | * It doesn't set the bit in iir again, but it still produces | |
4080 | * interrupts (for non-MSI). | |
4081 | */ | |
222c7f51 | 4082 | spin_lock(&dev_priv->irq_lock); |
a266c7d5 | 4083 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 4084 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
a266c7d5 | 4085 | |
055e393f | 4086 | for_each_pipe(dev_priv, pipe) { |
a266c7d5 CW |
4087 | int reg = PIPESTAT(pipe); |
4088 | pipe_stats[pipe] = I915_READ(reg); | |
4089 | ||
4090 | /* | |
4091 | * Clear the PIPE*STAT regs before the IIR | |
4092 | */ | |
4093 | if (pipe_stats[pipe] & 0x8000ffff) { | |
a266c7d5 | 4094 | I915_WRITE(reg, pipe_stats[pipe]); |
501e01d7 | 4095 | irq_received = true; |
a266c7d5 CW |
4096 | } |
4097 | } | |
222c7f51 | 4098 | spin_unlock(&dev_priv->irq_lock); |
a266c7d5 CW |
4099 | |
4100 | if (!irq_received) | |
4101 | break; | |
4102 | ||
4103 | ret = IRQ_HANDLED; | |
4104 | ||
4105 | /* Consume port. Then clear IIR or we'll miss events */ | |
16c6c56b VS |
4106 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
4107 | i9xx_hpd_irq_handler(dev); | |
a266c7d5 | 4108 | |
21ad8330 | 4109 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
4110 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
4111 | ||
a266c7d5 CW |
4112 | if (iir & I915_USER_INTERRUPT) |
4113 | notify_ring(dev, &dev_priv->ring[RCS]); | |
4114 | if (iir & I915_BSD_USER_INTERRUPT) | |
4115 | notify_ring(dev, &dev_priv->ring[VCS]); | |
4116 | ||
055e393f | 4117 | for_each_pipe(dev_priv, pipe) { |
2c8ba29f | 4118 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
4119 | i915_handle_vblank(dev, pipe, pipe, iir)) |
4120 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); | |
a266c7d5 CW |
4121 | |
4122 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
4123 | blc_event = true; | |
4356d586 DV |
4124 | |
4125 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 4126 | i9xx_pipe_crc_irq_handler(dev, pipe); |
a266c7d5 | 4127 | |
1f7247c0 DV |
4128 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
4129 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
2d9d2b0b | 4130 | } |
a266c7d5 CW |
4131 | |
4132 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | |
4133 | intel_opregion_asle_intr(dev); | |
4134 | ||
515ac2bb DV |
4135 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
4136 | gmbus_irq_handler(dev); | |
4137 | ||
a266c7d5 CW |
4138 | /* With MSI, interrupts are only generated when iir |
4139 | * transitions from zero to nonzero. If another bit got | |
4140 | * set while we were handling the existing iir bits, then | |
4141 | * we would never get another interrupt. | |
4142 | * | |
4143 | * This is fine on non-MSI as well, as if we hit this path | |
4144 | * we avoid exiting the interrupt handler only to generate | |
4145 | * another one. | |
4146 | * | |
4147 | * Note that for MSI this could cause a stray interrupt report | |
4148 | * if an interrupt landed in the time between writing IIR and | |
4149 | * the posting read. This should be rare enough to never | |
4150 | * trigger the 99% of 100,000 interrupts test for disabling | |
4151 | * stray interrupts. | |
4152 | */ | |
4153 | iir = new_iir; | |
4154 | } | |
4155 | ||
4156 | return ret; | |
4157 | } | |
4158 | ||
4159 | static void i965_irq_uninstall(struct drm_device * dev) | |
4160 | { | |
2d1013dd | 4161 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4162 | int pipe; |
4163 | ||
4164 | if (!dev_priv) | |
4165 | return; | |
4166 | ||
adca4730 CW |
4167 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
4168 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
4169 | |
4170 | I915_WRITE(HWSTAM, 0xffffffff); | |
055e393f | 4171 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4172 | I915_WRITE(PIPESTAT(pipe), 0); |
4173 | I915_WRITE(IMR, 0xffffffff); | |
4174 | I915_WRITE(IER, 0x0); | |
4175 | ||
055e393f | 4176 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4177 | I915_WRITE(PIPESTAT(pipe), |
4178 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); | |
4179 | I915_WRITE(IIR, I915_READ(IIR)); | |
4180 | } | |
4181 | ||
4cb21832 | 4182 | static void intel_hpd_irq_reenable_work(struct work_struct *work) |
ac4c16c5 | 4183 | { |
6323751d ID |
4184 | struct drm_i915_private *dev_priv = |
4185 | container_of(work, typeof(*dev_priv), | |
4186 | hotplug_reenable_work.work); | |
ac4c16c5 EE |
4187 | struct drm_device *dev = dev_priv->dev; |
4188 | struct drm_mode_config *mode_config = &dev->mode_config; | |
ac4c16c5 EE |
4189 | int i; |
4190 | ||
6323751d ID |
4191 | intel_runtime_pm_get(dev_priv); |
4192 | ||
4cb21832 | 4193 | spin_lock_irq(&dev_priv->irq_lock); |
ac4c16c5 EE |
4194 | for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) { |
4195 | struct drm_connector *connector; | |
4196 | ||
4197 | if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED) | |
4198 | continue; | |
4199 | ||
4200 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
4201 | ||
4202 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
4203 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4204 | ||
4205 | if (intel_connector->encoder->hpd_pin == i) { | |
4206 | if (connector->polled != intel_connector->polled) | |
4207 | DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n", | |
c23cc417 | 4208 | connector->name); |
ac4c16c5 EE |
4209 | connector->polled = intel_connector->polled; |
4210 | if (!connector->polled) | |
4211 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
4212 | } | |
4213 | } | |
4214 | } | |
4215 | if (dev_priv->display.hpd_irq_setup) | |
4216 | dev_priv->display.hpd_irq_setup(dev); | |
4cb21832 | 4217 | spin_unlock_irq(&dev_priv->irq_lock); |
6323751d ID |
4218 | |
4219 | intel_runtime_pm_put(dev_priv); | |
ac4c16c5 EE |
4220 | } |
4221 | ||
fca52a55 DV |
4222 | /** |
4223 | * intel_irq_init - initializes irq support | |
4224 | * @dev_priv: i915 device instance | |
4225 | * | |
4226 | * This function initializes all the irq support including work items, timers | |
4227 | * and all the vtables. It does not setup the interrupt itself though. | |
4228 | */ | |
b963291c | 4229 | void intel_irq_init(struct drm_i915_private *dev_priv) |
f71d4af4 | 4230 | { |
b963291c | 4231 | struct drm_device *dev = dev_priv->dev; |
8b2e326d CW |
4232 | |
4233 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); | |
13cf5504 | 4234 | INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func); |
c6a828d3 | 4235 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
a4da4fa4 | 4236 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
8b2e326d | 4237 | |
a6706b45 | 4238 | /* Let's track the enabled rps events */ |
b963291c | 4239 | if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) |
6c65a587 | 4240 | /* WaGsvRC0ResidencyMethod:vlv */ |
6f4b12f8 | 4241 | dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED; |
31685c25 D |
4242 | else |
4243 | dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; | |
a6706b45 | 4244 | |
737b1506 CW |
4245 | INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work, |
4246 | i915_hangcheck_elapsed); | |
6323751d | 4247 | INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work, |
4cb21832 | 4248 | intel_hpd_irq_reenable_work); |
61bac78e | 4249 | |
97a19a24 | 4250 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); |
9ee32fea | 4251 | |
b963291c | 4252 | if (IS_GEN2(dev_priv)) { |
4cdb83ec VS |
4253 | dev->max_vblank_count = 0; |
4254 | dev->driver->get_vblank_counter = i8xx_get_vblank_counter; | |
b963291c | 4255 | } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { |
f71d4af4 JB |
4256 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
4257 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; | |
391f75e2 VS |
4258 | } else { |
4259 | dev->driver->get_vblank_counter = i915_get_vblank_counter; | |
4260 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
f71d4af4 JB |
4261 | } |
4262 | ||
21da2700 VS |
4263 | /* |
4264 | * Opt out of the vblank disable timer on everything except gen2. | |
4265 | * Gen2 doesn't have a hardware frame counter and so depends on | |
4266 | * vblank interrupts to produce sane vblank seuquence numbers. | |
4267 | */ | |
b963291c | 4268 | if (!IS_GEN2(dev_priv)) |
21da2700 VS |
4269 | dev->vblank_disable_immediate = true; |
4270 | ||
f3a5c3f6 DV |
4271 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; |
4272 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; | |
f71d4af4 | 4273 | |
b963291c | 4274 | if (IS_CHERRYVIEW(dev_priv)) { |
43f328d7 VS |
4275 | dev->driver->irq_handler = cherryview_irq_handler; |
4276 | dev->driver->irq_preinstall = cherryview_irq_preinstall; | |
4277 | dev->driver->irq_postinstall = cherryview_irq_postinstall; | |
4278 | dev->driver->irq_uninstall = cherryview_irq_uninstall; | |
4279 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4280 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
4281 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; | |
b963291c | 4282 | } else if (IS_VALLEYVIEW(dev_priv)) { |
7e231dbe JB |
4283 | dev->driver->irq_handler = valleyview_irq_handler; |
4284 | dev->driver->irq_preinstall = valleyview_irq_preinstall; | |
4285 | dev->driver->irq_postinstall = valleyview_irq_postinstall; | |
4286 | dev->driver->irq_uninstall = valleyview_irq_uninstall; | |
4287 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4288 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
fa00abe0 | 4289 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
b963291c | 4290 | } else if (INTEL_INFO(dev_priv)->gen >= 8) { |
abd58f01 | 4291 | dev->driver->irq_handler = gen8_irq_handler; |
723761b8 | 4292 | dev->driver->irq_preinstall = gen8_irq_reset; |
abd58f01 BW |
4293 | dev->driver->irq_postinstall = gen8_irq_postinstall; |
4294 | dev->driver->irq_uninstall = gen8_irq_uninstall; | |
4295 | dev->driver->enable_vblank = gen8_enable_vblank; | |
4296 | dev->driver->disable_vblank = gen8_disable_vblank; | |
4297 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; | |
f71d4af4 JB |
4298 | } else if (HAS_PCH_SPLIT(dev)) { |
4299 | dev->driver->irq_handler = ironlake_irq_handler; | |
723761b8 | 4300 | dev->driver->irq_preinstall = ironlake_irq_reset; |
f71d4af4 JB |
4301 | dev->driver->irq_postinstall = ironlake_irq_postinstall; |
4302 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
4303 | dev->driver->enable_vblank = ironlake_enable_vblank; | |
4304 | dev->driver->disable_vblank = ironlake_disable_vblank; | |
82a28bcf | 4305 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; |
f71d4af4 | 4306 | } else { |
b963291c | 4307 | if (INTEL_INFO(dev_priv)->gen == 2) { |
c2798b19 CW |
4308 | dev->driver->irq_preinstall = i8xx_irq_preinstall; |
4309 | dev->driver->irq_postinstall = i8xx_irq_postinstall; | |
4310 | dev->driver->irq_handler = i8xx_irq_handler; | |
4311 | dev->driver->irq_uninstall = i8xx_irq_uninstall; | |
b963291c | 4312 | } else if (INTEL_INFO(dev_priv)->gen == 3) { |
a266c7d5 CW |
4313 | dev->driver->irq_preinstall = i915_irq_preinstall; |
4314 | dev->driver->irq_postinstall = i915_irq_postinstall; | |
4315 | dev->driver->irq_uninstall = i915_irq_uninstall; | |
4316 | dev->driver->irq_handler = i915_irq_handler; | |
c2798b19 | 4317 | } else { |
a266c7d5 CW |
4318 | dev->driver->irq_preinstall = i965_irq_preinstall; |
4319 | dev->driver->irq_postinstall = i965_irq_postinstall; | |
4320 | dev->driver->irq_uninstall = i965_irq_uninstall; | |
4321 | dev->driver->irq_handler = i965_irq_handler; | |
c2798b19 | 4322 | } |
778eb334 VS |
4323 | if (I915_HAS_HOTPLUG(dev_priv)) |
4324 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; | |
f71d4af4 JB |
4325 | dev->driver->enable_vblank = i915_enable_vblank; |
4326 | dev->driver->disable_vblank = i915_disable_vblank; | |
4327 | } | |
4328 | } | |
20afbda2 | 4329 | |
fca52a55 DV |
4330 | /** |
4331 | * intel_hpd_init - initializes and enables hpd support | |
4332 | * @dev_priv: i915 device instance | |
4333 | * | |
4334 | * This function enables the hotplug support. It requires that interrupts have | |
4335 | * already been enabled with intel_irq_init_hw(). From this point on hotplug and | |
4336 | * poll request can run concurrently to other code, so locking rules must be | |
4337 | * obeyed. | |
4338 | * | |
4339 | * This is a separate step from interrupt enabling to simplify the locking rules | |
4340 | * in the driver load and resume code. | |
4341 | */ | |
b963291c | 4342 | void intel_hpd_init(struct drm_i915_private *dev_priv) |
20afbda2 | 4343 | { |
b963291c | 4344 | struct drm_device *dev = dev_priv->dev; |
821450c6 EE |
4345 | struct drm_mode_config *mode_config = &dev->mode_config; |
4346 | struct drm_connector *connector; | |
4347 | int i; | |
20afbda2 | 4348 | |
821450c6 EE |
4349 | for (i = 1; i < HPD_NUM_PINS; i++) { |
4350 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
4351 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
4352 | } | |
4353 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
4354 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4355 | connector->polled = intel_connector->polled; | |
0e32b39c DA |
4356 | if (connector->encoder && !connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE) |
4357 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
4358 | if (intel_connector->mst_port) | |
821450c6 EE |
4359 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
4360 | } | |
b5ea2d56 DV |
4361 | |
4362 | /* Interrupt setup is already guaranteed to be single-threaded, this is | |
4363 | * just to make the assert_spin_locked checks happy. */ | |
d6207435 | 4364 | spin_lock_irq(&dev_priv->irq_lock); |
20afbda2 DV |
4365 | if (dev_priv->display.hpd_irq_setup) |
4366 | dev_priv->display.hpd_irq_setup(dev); | |
d6207435 | 4367 | spin_unlock_irq(&dev_priv->irq_lock); |
20afbda2 | 4368 | } |
c67a470b | 4369 | |
fca52a55 DV |
4370 | /** |
4371 | * intel_irq_install - enables the hardware interrupt | |
4372 | * @dev_priv: i915 device instance | |
4373 | * | |
4374 | * This function enables the hardware interrupt handling, but leaves the hotplug | |
4375 | * handling still disabled. It is called after intel_irq_init(). | |
4376 | * | |
4377 | * In the driver load and resume code we need working interrupts in a few places | |
4378 | * but don't want to deal with the hassle of concurrent probe and hotplug | |
4379 | * workers. Hence the split into this two-stage approach. | |
4380 | */ | |
2aeb7d3a DV |
4381 | int intel_irq_install(struct drm_i915_private *dev_priv) |
4382 | { | |
4383 | /* | |
4384 | * We enable some interrupt sources in our postinstall hooks, so mark | |
4385 | * interrupts as enabled _before_ actually enabling them to avoid | |
4386 | * special cases in our ordering checks. | |
4387 | */ | |
4388 | dev_priv->pm.irqs_enabled = true; | |
4389 | ||
4390 | return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq); | |
4391 | } | |
4392 | ||
fca52a55 DV |
4393 | /** |
4394 | * intel_irq_uninstall - finilizes all irq handling | |
4395 | * @dev_priv: i915 device instance | |
4396 | * | |
4397 | * This stops interrupt and hotplug handling and unregisters and frees all | |
4398 | * resources acquired in the init functions. | |
4399 | */ | |
2aeb7d3a DV |
4400 | void intel_irq_uninstall(struct drm_i915_private *dev_priv) |
4401 | { | |
4402 | drm_irq_uninstall(dev_priv->dev); | |
4403 | intel_hpd_cancel_work(dev_priv); | |
4404 | dev_priv->pm.irqs_enabled = false; | |
4405 | } | |
4406 | ||
fca52a55 DV |
4407 | /** |
4408 | * intel_runtime_pm_disable_interrupts - runtime interrupt disabling | |
4409 | * @dev_priv: i915 device instance | |
4410 | * | |
4411 | * This function is used to disable interrupts at runtime, both in the runtime | |
4412 | * pm and the system suspend/resume code. | |
4413 | */ | |
b963291c | 4414 | void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv) |
c67a470b | 4415 | { |
b963291c | 4416 | dev_priv->dev->driver->irq_uninstall(dev_priv->dev); |
2aeb7d3a | 4417 | dev_priv->pm.irqs_enabled = false; |
2dd2a883 | 4418 | synchronize_irq(dev_priv->dev->irq); |
c67a470b PZ |
4419 | } |
4420 | ||
fca52a55 DV |
4421 | /** |
4422 | * intel_runtime_pm_enable_interrupts - runtime interrupt enabling | |
4423 | * @dev_priv: i915 device instance | |
4424 | * | |
4425 | * This function is used to enable interrupts at runtime, both in the runtime | |
4426 | * pm and the system suspend/resume code. | |
4427 | */ | |
b963291c | 4428 | void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv) |
c67a470b | 4429 | { |
2aeb7d3a | 4430 | dev_priv->pm.irqs_enabled = true; |
b963291c DV |
4431 | dev_priv->dev->driver->irq_preinstall(dev_priv->dev); |
4432 | dev_priv->dev->driver->irq_postinstall(dev_priv->dev); | |
c67a470b | 4433 | } |