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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
63eeaf38 | 31 | #include <linux/sysrq.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
1da177e4 LT |
33 | #include "drmP.h" |
34 | #include "drm.h" | |
35 | #include "i915_drm.h" | |
36 | #include "i915_drv.h" | |
1c5d22f7 | 37 | #include "i915_trace.h" |
79e53945 | 38 | #include "intel_drv.h" |
1da177e4 | 39 | |
036a4a7d | 40 | /* For display hotplug interrupt */ |
995b6762 | 41 | static void |
f2b115e6 | 42 | ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d | 43 | { |
1ec14ad3 CW |
44 | if ((dev_priv->irq_mask & mask) != 0) { |
45 | dev_priv->irq_mask &= ~mask; | |
46 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 47 | POSTING_READ(DEIMR); |
036a4a7d ZW |
48 | } |
49 | } | |
50 | ||
51 | static inline void | |
f2b115e6 | 52 | ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d | 53 | { |
1ec14ad3 CW |
54 | if ((dev_priv->irq_mask & mask) != mask) { |
55 | dev_priv->irq_mask |= mask; | |
56 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 57 | POSTING_READ(DEIMR); |
036a4a7d ZW |
58 | } |
59 | } | |
60 | ||
7c463586 KP |
61 | void |
62 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
63 | { | |
64 | if ((dev_priv->pipestat[pipe] & mask) != mask) { | |
9db4a9c7 | 65 | u32 reg = PIPESTAT(pipe); |
7c463586 KP |
66 | |
67 | dev_priv->pipestat[pipe] |= mask; | |
68 | /* Enable the interrupt, clear any pending status */ | |
69 | I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); | |
3143a2bf | 70 | POSTING_READ(reg); |
7c463586 KP |
71 | } |
72 | } | |
73 | ||
74 | void | |
75 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
76 | { | |
77 | if ((dev_priv->pipestat[pipe] & mask) != 0) { | |
9db4a9c7 | 78 | u32 reg = PIPESTAT(pipe); |
7c463586 KP |
79 | |
80 | dev_priv->pipestat[pipe] &= ~mask; | |
81 | I915_WRITE(reg, dev_priv->pipestat[pipe]); | |
3143a2bf | 82 | POSTING_READ(reg); |
7c463586 KP |
83 | } |
84 | } | |
85 | ||
01c66889 ZY |
86 | /** |
87 | * intel_enable_asle - enable ASLE interrupt for OpRegion | |
88 | */ | |
1ec14ad3 | 89 | void intel_enable_asle(struct drm_device *dev) |
01c66889 | 90 | { |
1ec14ad3 CW |
91 | drm_i915_private_t *dev_priv = dev->dev_private; |
92 | unsigned long irqflags; | |
93 | ||
7e231dbe JB |
94 | /* FIXME: opregion/asle for VLV */ |
95 | if (IS_VALLEYVIEW(dev)) | |
96 | return; | |
97 | ||
1ec14ad3 | 98 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
01c66889 | 99 | |
c619eed4 | 100 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 101 | ironlake_enable_display_irq(dev_priv, DE_GSE); |
edcb49ca | 102 | else { |
01c66889 | 103 | i915_enable_pipestat(dev_priv, 1, |
d874bcff | 104 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
a6c45cf0 | 105 | if (INTEL_INFO(dev)->gen >= 4) |
edcb49ca | 106 | i915_enable_pipestat(dev_priv, 0, |
d874bcff | 107 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
edcb49ca | 108 | } |
1ec14ad3 CW |
109 | |
110 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
01c66889 ZY |
111 | } |
112 | ||
0a3e67a4 JB |
113 | /** |
114 | * i915_pipe_enabled - check if a pipe is enabled | |
115 | * @dev: DRM device | |
116 | * @pipe: pipe to check | |
117 | * | |
118 | * Reading certain registers when the pipe is disabled can hang the chip. | |
119 | * Use this routine to make sure the PLL is running and the pipe is active | |
120 | * before reading such registers if unsure. | |
121 | */ | |
122 | static int | |
123 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
124 | { | |
125 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
5eddb70b | 126 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; |
0a3e67a4 JB |
127 | } |
128 | ||
42f52ef8 KP |
129 | /* Called from drm generic code, passed a 'crtc', which |
130 | * we use as a pipe index | |
131 | */ | |
f71d4af4 | 132 | static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
0a3e67a4 JB |
133 | { |
134 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
135 | unsigned long high_frame; | |
136 | unsigned long low_frame; | |
5eddb70b | 137 | u32 high1, high2, low; |
0a3e67a4 JB |
138 | |
139 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 140 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 141 | "pipe %c\n", pipe_name(pipe)); |
0a3e67a4 JB |
142 | return 0; |
143 | } | |
144 | ||
9db4a9c7 JB |
145 | high_frame = PIPEFRAME(pipe); |
146 | low_frame = PIPEFRAMEPIXEL(pipe); | |
5eddb70b | 147 | |
0a3e67a4 JB |
148 | /* |
149 | * High & low register fields aren't synchronized, so make sure | |
150 | * we get a low value that's stable across two reads of the high | |
151 | * register. | |
152 | */ | |
153 | do { | |
5eddb70b CW |
154 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
155 | low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK; | |
156 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; | |
0a3e67a4 JB |
157 | } while (high1 != high2); |
158 | ||
5eddb70b CW |
159 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
160 | low >>= PIPE_FRAME_LOW_SHIFT; | |
161 | return (high1 << 8) | low; | |
0a3e67a4 JB |
162 | } |
163 | ||
f71d4af4 | 164 | static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
9880b7a5 JB |
165 | { |
166 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 167 | int reg = PIPE_FRMCOUNT_GM45(pipe); |
9880b7a5 JB |
168 | |
169 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 170 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 171 | "pipe %c\n", pipe_name(pipe)); |
9880b7a5 JB |
172 | return 0; |
173 | } | |
174 | ||
175 | return I915_READ(reg); | |
176 | } | |
177 | ||
f71d4af4 | 178 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
0af7e4df MK |
179 | int *vpos, int *hpos) |
180 | { | |
181 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
182 | u32 vbl = 0, position = 0; | |
183 | int vbl_start, vbl_end, htotal, vtotal; | |
184 | bool in_vbl = true; | |
185 | int ret = 0; | |
186 | ||
187 | if (!i915_pipe_enabled(dev, pipe)) { | |
188 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " | |
9db4a9c7 | 189 | "pipe %c\n", pipe_name(pipe)); |
0af7e4df MK |
190 | return 0; |
191 | } | |
192 | ||
193 | /* Get vtotal. */ | |
194 | vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff); | |
195 | ||
196 | if (INTEL_INFO(dev)->gen >= 4) { | |
197 | /* No obvious pixelcount register. Only query vertical | |
198 | * scanout position from Display scan line register. | |
199 | */ | |
200 | position = I915_READ(PIPEDSL(pipe)); | |
201 | ||
202 | /* Decode into vertical scanout position. Don't have | |
203 | * horizontal scanout position. | |
204 | */ | |
205 | *vpos = position & 0x1fff; | |
206 | *hpos = 0; | |
207 | } else { | |
208 | /* Have access to pixelcount since start of frame. | |
209 | * We can split this into vertical and horizontal | |
210 | * scanout position. | |
211 | */ | |
212 | position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; | |
213 | ||
214 | htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff); | |
215 | *vpos = position / htotal; | |
216 | *hpos = position - (*vpos * htotal); | |
217 | } | |
218 | ||
219 | /* Query vblank area. */ | |
220 | vbl = I915_READ(VBLANK(pipe)); | |
221 | ||
222 | /* Test position against vblank region. */ | |
223 | vbl_start = vbl & 0x1fff; | |
224 | vbl_end = (vbl >> 16) & 0x1fff; | |
225 | ||
226 | if ((*vpos < vbl_start) || (*vpos > vbl_end)) | |
227 | in_vbl = false; | |
228 | ||
229 | /* Inside "upper part" of vblank area? Apply corrective offset: */ | |
230 | if (in_vbl && (*vpos >= vbl_start)) | |
231 | *vpos = *vpos - vtotal; | |
232 | ||
233 | /* Readouts valid? */ | |
234 | if (vbl > 0) | |
235 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; | |
236 | ||
237 | /* In vblank? */ | |
238 | if (in_vbl) | |
239 | ret |= DRM_SCANOUTPOS_INVBL; | |
240 | ||
241 | return ret; | |
242 | } | |
243 | ||
f71d4af4 | 244 | static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
0af7e4df MK |
245 | int *max_error, |
246 | struct timeval *vblank_time, | |
247 | unsigned flags) | |
248 | { | |
4041b853 CW |
249 | struct drm_i915_private *dev_priv = dev->dev_private; |
250 | struct drm_crtc *crtc; | |
0af7e4df | 251 | |
4041b853 CW |
252 | if (pipe < 0 || pipe >= dev_priv->num_pipe) { |
253 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
0af7e4df MK |
254 | return -EINVAL; |
255 | } | |
256 | ||
257 | /* Get drm_crtc to timestamp: */ | |
4041b853 CW |
258 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
259 | if (crtc == NULL) { | |
260 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
261 | return -EINVAL; | |
262 | } | |
263 | ||
264 | if (!crtc->enabled) { | |
265 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); | |
266 | return -EBUSY; | |
267 | } | |
0af7e4df MK |
268 | |
269 | /* Helper routine in DRM core does all the work: */ | |
4041b853 CW |
270 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
271 | vblank_time, flags, | |
272 | crtc); | |
0af7e4df MK |
273 | } |
274 | ||
5ca58282 JB |
275 | /* |
276 | * Handle hotplug events outside the interrupt handler proper. | |
277 | */ | |
278 | static void i915_hotplug_work_func(struct work_struct *work) | |
279 | { | |
280 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
281 | hotplug_work); | |
282 | struct drm_device *dev = dev_priv->dev; | |
c31c4ba3 | 283 | struct drm_mode_config *mode_config = &dev->mode_config; |
4ef69c7a CW |
284 | struct intel_encoder *encoder; |
285 | ||
a65e34c7 | 286 | mutex_lock(&mode_config->mutex); |
e67189ab JB |
287 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); |
288 | ||
4ef69c7a CW |
289 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) |
290 | if (encoder->hot_plug) | |
291 | encoder->hot_plug(encoder); | |
292 | ||
40ee3381 KP |
293 | mutex_unlock(&mode_config->mutex); |
294 | ||
5ca58282 | 295 | /* Just fire off a uevent and let userspace tell us what to do */ |
eb1f8e4f | 296 | drm_helper_hpd_irq_event(dev); |
5ca58282 JB |
297 | } |
298 | ||
9270388e DV |
299 | /* defined intel_pm.c */ |
300 | extern spinlock_t mchdev_lock; | |
301 | ||
73edd18f | 302 | static void ironlake_handle_rps_change(struct drm_device *dev) |
f97108d1 JB |
303 | { |
304 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b5b72e89 | 305 | u32 busy_up, busy_down, max_avg, min_avg; |
9270388e DV |
306 | u8 new_delay; |
307 | unsigned long flags; | |
308 | ||
309 | spin_lock_irqsave(&mchdev_lock, flags); | |
f97108d1 | 310 | |
73edd18f DV |
311 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
312 | ||
20e4d407 | 313 | new_delay = dev_priv->ips.cur_delay; |
9270388e | 314 | |
7648fa99 | 315 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
316 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
317 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
318 | max_avg = I915_READ(RCBMAXAVG); |
319 | min_avg = I915_READ(RCBMINAVG); | |
320 | ||
321 | /* Handle RCS change request from hw */ | |
b5b72e89 | 322 | if (busy_up > max_avg) { |
20e4d407 DV |
323 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
324 | new_delay = dev_priv->ips.cur_delay - 1; | |
325 | if (new_delay < dev_priv->ips.max_delay) | |
326 | new_delay = dev_priv->ips.max_delay; | |
b5b72e89 | 327 | } else if (busy_down < min_avg) { |
20e4d407 DV |
328 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
329 | new_delay = dev_priv->ips.cur_delay + 1; | |
330 | if (new_delay > dev_priv->ips.min_delay) | |
331 | new_delay = dev_priv->ips.min_delay; | |
f97108d1 JB |
332 | } |
333 | ||
7648fa99 | 334 | if (ironlake_set_drps(dev, new_delay)) |
20e4d407 | 335 | dev_priv->ips.cur_delay = new_delay; |
f97108d1 | 336 | |
9270388e DV |
337 | spin_unlock_irqrestore(&mchdev_lock, flags); |
338 | ||
f97108d1 JB |
339 | return; |
340 | } | |
341 | ||
549f7365 CW |
342 | static void notify_ring(struct drm_device *dev, |
343 | struct intel_ring_buffer *ring) | |
344 | { | |
345 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9862e600 | 346 | |
475553de CW |
347 | if (ring->obj == NULL) |
348 | return; | |
349 | ||
b2eadbc8 | 350 | trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false)); |
9862e600 | 351 | |
549f7365 | 352 | wake_up_all(&ring->irq_queue); |
3e0dc6b0 BW |
353 | if (i915_enable_hangcheck) { |
354 | dev_priv->hangcheck_count = 0; | |
355 | mod_timer(&dev_priv->hangcheck_timer, | |
356 | jiffies + | |
357 | msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
358 | } | |
549f7365 CW |
359 | } |
360 | ||
4912d041 | 361 | static void gen6_pm_rps_work(struct work_struct *work) |
3b8d8d91 | 362 | { |
4912d041 | 363 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
c6a828d3 | 364 | rps.work); |
4912d041 | 365 | u32 pm_iir, pm_imr; |
7b9e0ae6 | 366 | u8 new_delay; |
4912d041 | 367 | |
c6a828d3 DV |
368 | spin_lock_irq(&dev_priv->rps.lock); |
369 | pm_iir = dev_priv->rps.pm_iir; | |
370 | dev_priv->rps.pm_iir = 0; | |
4912d041 | 371 | pm_imr = I915_READ(GEN6_PMIMR); |
a9e2641d | 372 | I915_WRITE(GEN6_PMIMR, 0); |
c6a828d3 | 373 | spin_unlock_irq(&dev_priv->rps.lock); |
3b8d8d91 | 374 | |
7b9e0ae6 | 375 | if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0) |
3b8d8d91 JB |
376 | return; |
377 | ||
4912d041 | 378 | mutex_lock(&dev_priv->dev->struct_mutex); |
7b9e0ae6 CW |
379 | |
380 | if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) | |
c6a828d3 | 381 | new_delay = dev_priv->rps.cur_delay + 1; |
7b9e0ae6 | 382 | else |
c6a828d3 | 383 | new_delay = dev_priv->rps.cur_delay - 1; |
3b8d8d91 | 384 | |
4912d041 | 385 | gen6_set_rps(dev_priv->dev, new_delay); |
3b8d8d91 | 386 | |
4912d041 | 387 | mutex_unlock(&dev_priv->dev->struct_mutex); |
3b8d8d91 JB |
388 | } |
389 | ||
e3689190 BW |
390 | |
391 | /** | |
392 | * ivybridge_parity_work - Workqueue called when a parity error interrupt | |
393 | * occurred. | |
394 | * @work: workqueue struct | |
395 | * | |
396 | * Doesn't actually do anything except notify userspace. As a consequence of | |
397 | * this event, userspace should try to remap the bad rows since statistically | |
398 | * it is likely the same row is more likely to go bad again. | |
399 | */ | |
400 | static void ivybridge_parity_work(struct work_struct *work) | |
401 | { | |
402 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
403 | parity_error_work); | |
404 | u32 error_status, row, bank, subbank; | |
405 | char *parity_event[5]; | |
406 | uint32_t misccpctl; | |
407 | unsigned long flags; | |
408 | ||
409 | /* We must turn off DOP level clock gating to access the L3 registers. | |
410 | * In order to prevent a get/put style interface, acquire struct mutex | |
411 | * any time we access those registers. | |
412 | */ | |
413 | mutex_lock(&dev_priv->dev->struct_mutex); | |
414 | ||
415 | misccpctl = I915_READ(GEN7_MISCCPCTL); | |
416 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
417 | POSTING_READ(GEN7_MISCCPCTL); | |
418 | ||
419 | error_status = I915_READ(GEN7_L3CDERRST1); | |
420 | row = GEN7_PARITY_ERROR_ROW(error_status); | |
421 | bank = GEN7_PARITY_ERROR_BANK(error_status); | |
422 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); | |
423 | ||
424 | I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID | | |
425 | GEN7_L3CDERRST1_ENABLE); | |
426 | POSTING_READ(GEN7_L3CDERRST1); | |
427 | ||
428 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); | |
429 | ||
430 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
431 | dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT; | |
432 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
433 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
434 | ||
435 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
436 | ||
437 | parity_event[0] = "L3_PARITY_ERROR=1"; | |
438 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); | |
439 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); | |
440 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); | |
441 | parity_event[4] = NULL; | |
442 | ||
443 | kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj, | |
444 | KOBJ_CHANGE, parity_event); | |
445 | ||
446 | DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n", | |
447 | row, bank, subbank); | |
448 | ||
449 | kfree(parity_event[3]); | |
450 | kfree(parity_event[2]); | |
451 | kfree(parity_event[1]); | |
452 | } | |
453 | ||
d2ba8470 | 454 | static void ivybridge_handle_parity_error(struct drm_device *dev) |
e3689190 BW |
455 | { |
456 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
457 | unsigned long flags; | |
458 | ||
e1ef7cc2 | 459 | if (!HAS_L3_GPU_CACHE(dev)) |
e3689190 BW |
460 | return; |
461 | ||
462 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
463 | dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT; | |
464 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
465 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
466 | ||
467 | queue_work(dev_priv->wq, &dev_priv->parity_error_work); | |
468 | } | |
469 | ||
e7b4c6b1 DV |
470 | static void snb_gt_irq_handler(struct drm_device *dev, |
471 | struct drm_i915_private *dev_priv, | |
472 | u32 gt_iir) | |
473 | { | |
474 | ||
475 | if (gt_iir & (GEN6_RENDER_USER_INTERRUPT | | |
476 | GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT)) | |
477 | notify_ring(dev, &dev_priv->ring[RCS]); | |
478 | if (gt_iir & GEN6_BSD_USER_INTERRUPT) | |
479 | notify_ring(dev, &dev_priv->ring[VCS]); | |
480 | if (gt_iir & GEN6_BLITTER_USER_INTERRUPT) | |
481 | notify_ring(dev, &dev_priv->ring[BCS]); | |
482 | ||
483 | if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT | | |
484 | GT_GEN6_BSD_CS_ERROR_INTERRUPT | | |
485 | GT_RENDER_CS_ERROR_INTERRUPT)) { | |
486 | DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir); | |
487 | i915_handle_error(dev, false); | |
488 | } | |
e3689190 BW |
489 | |
490 | if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT) | |
491 | ivybridge_handle_parity_error(dev); | |
e7b4c6b1 DV |
492 | } |
493 | ||
fc6826d1 CW |
494 | static void gen6_queue_rps_work(struct drm_i915_private *dev_priv, |
495 | u32 pm_iir) | |
496 | { | |
497 | unsigned long flags; | |
498 | ||
499 | /* | |
500 | * IIR bits should never already be set because IMR should | |
501 | * prevent an interrupt from being shown in IIR. The warning | |
502 | * displays a case where we've unsafely cleared | |
c6a828d3 | 503 | * dev_priv->rps.pm_iir. Although missing an interrupt of the same |
fc6826d1 CW |
504 | * type is not a problem, it displays a problem in the logic. |
505 | * | |
c6a828d3 | 506 | * The mask bit in IMR is cleared by dev_priv->rps.work. |
fc6826d1 CW |
507 | */ |
508 | ||
c6a828d3 | 509 | spin_lock_irqsave(&dev_priv->rps.lock, flags); |
c6a828d3 DV |
510 | dev_priv->rps.pm_iir |= pm_iir; |
511 | I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir); | |
fc6826d1 | 512 | POSTING_READ(GEN6_PMIMR); |
c6a828d3 | 513 | spin_unlock_irqrestore(&dev_priv->rps.lock, flags); |
fc6826d1 | 514 | |
c6a828d3 | 515 | queue_work(dev_priv->wq, &dev_priv->rps.work); |
fc6826d1 CW |
516 | } |
517 | ||
7e231dbe JB |
518 | static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS) |
519 | { | |
520 | struct drm_device *dev = (struct drm_device *) arg; | |
521 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
522 | u32 iir, gt_iir, pm_iir; | |
523 | irqreturn_t ret = IRQ_NONE; | |
524 | unsigned long irqflags; | |
525 | int pipe; | |
526 | u32 pipe_stats[I915_MAX_PIPES]; | |
7e231dbe JB |
527 | bool blc_event; |
528 | ||
529 | atomic_inc(&dev_priv->irq_received); | |
530 | ||
7e231dbe JB |
531 | while (true) { |
532 | iir = I915_READ(VLV_IIR); | |
533 | gt_iir = I915_READ(GTIIR); | |
534 | pm_iir = I915_READ(GEN6_PMIIR); | |
535 | ||
536 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) | |
537 | goto out; | |
538 | ||
539 | ret = IRQ_HANDLED; | |
540 | ||
e7b4c6b1 | 541 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
7e231dbe JB |
542 | |
543 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
544 | for_each_pipe(pipe) { | |
545 | int reg = PIPESTAT(pipe); | |
546 | pipe_stats[pipe] = I915_READ(reg); | |
547 | ||
548 | /* | |
549 | * Clear the PIPE*STAT regs before the IIR | |
550 | */ | |
551 | if (pipe_stats[pipe] & 0x8000ffff) { | |
552 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | |
553 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | |
554 | pipe_name(pipe)); | |
555 | I915_WRITE(reg, pipe_stats[pipe]); | |
556 | } | |
557 | } | |
558 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
559 | ||
31acc7f5 JB |
560 | for_each_pipe(pipe) { |
561 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) | |
562 | drm_handle_vblank(dev, pipe); | |
563 | ||
564 | if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) { | |
565 | intel_prepare_page_flip(dev, pipe); | |
566 | intel_finish_page_flip(dev, pipe); | |
567 | } | |
568 | } | |
569 | ||
7e231dbe JB |
570 | /* Consume port. Then clear IIR or we'll miss events */ |
571 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { | |
572 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
573 | ||
574 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", | |
575 | hotplug_status); | |
576 | if (hotplug_status & dev_priv->hotplug_supported_mask) | |
577 | queue_work(dev_priv->wq, | |
578 | &dev_priv->hotplug_work); | |
579 | ||
580 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
581 | I915_READ(PORT_HOTPLUG_STAT); | |
582 | } | |
583 | ||
7e231dbe JB |
584 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) |
585 | blc_event = true; | |
586 | ||
fc6826d1 CW |
587 | if (pm_iir & GEN6_PM_DEFERRED_EVENTS) |
588 | gen6_queue_rps_work(dev_priv, pm_iir); | |
7e231dbe JB |
589 | |
590 | I915_WRITE(GTIIR, gt_iir); | |
591 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
592 | I915_WRITE(VLV_IIR, iir); | |
593 | } | |
594 | ||
595 | out: | |
596 | return ret; | |
597 | } | |
598 | ||
23e81d69 | 599 | static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) |
776ad806 JB |
600 | { |
601 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 602 | int pipe; |
776ad806 | 603 | |
776ad806 JB |
604 | if (pch_iir & SDE_AUDIO_POWER_MASK) |
605 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", | |
606 | (pch_iir & SDE_AUDIO_POWER_MASK) >> | |
607 | SDE_AUDIO_POWER_SHIFT); | |
608 | ||
609 | if (pch_iir & SDE_GMBUS) | |
610 | DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n"); | |
611 | ||
612 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
613 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
614 | ||
615 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
616 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
617 | ||
618 | if (pch_iir & SDE_POISON) | |
619 | DRM_ERROR("PCH poison interrupt\n"); | |
620 | ||
9db4a9c7 JB |
621 | if (pch_iir & SDE_FDI_MASK) |
622 | for_each_pipe(pipe) | |
623 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", | |
624 | pipe_name(pipe), | |
625 | I915_READ(FDI_RX_IIR(pipe))); | |
776ad806 JB |
626 | |
627 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
628 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
629 | ||
630 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
631 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
632 | ||
633 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
634 | DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n"); | |
635 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) | |
636 | DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n"); | |
637 | } | |
638 | ||
23e81d69 AJ |
639 | static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) |
640 | { | |
641 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
642 | int pipe; | |
643 | ||
644 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) | |
645 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", | |
646 | (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> | |
647 | SDE_AUDIO_POWER_SHIFT_CPT); | |
648 | ||
649 | if (pch_iir & SDE_AUX_MASK_CPT) | |
650 | DRM_DEBUG_DRIVER("AUX channel interrupt\n"); | |
651 | ||
652 | if (pch_iir & SDE_GMBUS_CPT) | |
653 | DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n"); | |
654 | ||
655 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) | |
656 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); | |
657 | ||
658 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) | |
659 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); | |
660 | ||
661 | if (pch_iir & SDE_FDI_MASK_CPT) | |
662 | for_each_pipe(pipe) | |
663 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", | |
664 | pipe_name(pipe), | |
665 | I915_READ(FDI_RX_IIR(pipe))); | |
666 | } | |
667 | ||
f71d4af4 | 668 | static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS) |
b1f14ad0 JB |
669 | { |
670 | struct drm_device *dev = (struct drm_device *) arg; | |
671 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
0e43406b CW |
672 | u32 de_iir, gt_iir, de_ier, pm_iir; |
673 | irqreturn_t ret = IRQ_NONE; | |
674 | int i; | |
b1f14ad0 JB |
675 | |
676 | atomic_inc(&dev_priv->irq_received); | |
677 | ||
678 | /* disable master interrupt before clearing iir */ | |
679 | de_ier = I915_READ(DEIER); | |
680 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
b1f14ad0 | 681 | |
b1f14ad0 | 682 | gt_iir = I915_READ(GTIIR); |
0e43406b CW |
683 | if (gt_iir) { |
684 | snb_gt_irq_handler(dev, dev_priv, gt_iir); | |
685 | I915_WRITE(GTIIR, gt_iir); | |
686 | ret = IRQ_HANDLED; | |
b1f14ad0 JB |
687 | } |
688 | ||
0e43406b CW |
689 | de_iir = I915_READ(DEIIR); |
690 | if (de_iir) { | |
691 | if (de_iir & DE_GSE_IVB) | |
692 | intel_opregion_gse_intr(dev); | |
693 | ||
694 | for (i = 0; i < 3; i++) { | |
695 | if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) { | |
696 | intel_prepare_page_flip(dev, i); | |
697 | intel_finish_page_flip_plane(dev, i); | |
698 | } | |
699 | if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i))) | |
700 | drm_handle_vblank(dev, i); | |
701 | } | |
b615b57a | 702 | |
0e43406b CW |
703 | /* check event from PCH */ |
704 | if (de_iir & DE_PCH_EVENT_IVB) { | |
705 | u32 pch_iir = I915_READ(SDEIIR); | |
b1f14ad0 | 706 | |
0e43406b CW |
707 | if (pch_iir & SDE_HOTPLUG_MASK_CPT) |
708 | queue_work(dev_priv->wq, &dev_priv->hotplug_work); | |
23e81d69 | 709 | cpt_irq_handler(dev, pch_iir); |
b1f14ad0 | 710 | |
0e43406b CW |
711 | /* clear PCH hotplug event before clear CPU irq */ |
712 | I915_WRITE(SDEIIR, pch_iir); | |
713 | } | |
b615b57a | 714 | |
0e43406b CW |
715 | I915_WRITE(DEIIR, de_iir); |
716 | ret = IRQ_HANDLED; | |
b1f14ad0 JB |
717 | } |
718 | ||
0e43406b CW |
719 | pm_iir = I915_READ(GEN6_PMIIR); |
720 | if (pm_iir) { | |
721 | if (pm_iir & GEN6_PM_DEFERRED_EVENTS) | |
722 | gen6_queue_rps_work(dev_priv, pm_iir); | |
723 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
724 | ret = IRQ_HANDLED; | |
725 | } | |
b1f14ad0 | 726 | |
b1f14ad0 JB |
727 | I915_WRITE(DEIER, de_ier); |
728 | POSTING_READ(DEIER); | |
729 | ||
730 | return ret; | |
731 | } | |
732 | ||
e7b4c6b1 DV |
733 | static void ilk_gt_irq_handler(struct drm_device *dev, |
734 | struct drm_i915_private *dev_priv, | |
735 | u32 gt_iir) | |
736 | { | |
737 | if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY)) | |
738 | notify_ring(dev, &dev_priv->ring[RCS]); | |
739 | if (gt_iir & GT_BSD_USER_INTERRUPT) | |
740 | notify_ring(dev, &dev_priv->ring[VCS]); | |
741 | } | |
742 | ||
f71d4af4 | 743 | static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS) |
036a4a7d | 744 | { |
4697995b | 745 | struct drm_device *dev = (struct drm_device *) arg; |
036a4a7d ZW |
746 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
747 | int ret = IRQ_NONE; | |
3b8d8d91 | 748 | u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir; |
2d7b8366 | 749 | u32 hotplug_mask; |
881f47b6 | 750 | |
4697995b JB |
751 | atomic_inc(&dev_priv->irq_received); |
752 | ||
2d109a84 ZN |
753 | /* disable master interrupt before clearing iir */ |
754 | de_ier = I915_READ(DEIER); | |
755 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
3143a2bf | 756 | POSTING_READ(DEIER); |
2d109a84 | 757 | |
036a4a7d ZW |
758 | de_iir = I915_READ(DEIIR); |
759 | gt_iir = I915_READ(GTIIR); | |
c650156a | 760 | pch_iir = I915_READ(SDEIIR); |
3b8d8d91 | 761 | pm_iir = I915_READ(GEN6_PMIIR); |
036a4a7d | 762 | |
3b8d8d91 JB |
763 | if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && |
764 | (!IS_GEN6(dev) || pm_iir == 0)) | |
c7c85101 | 765 | goto done; |
036a4a7d | 766 | |
2d7b8366 YL |
767 | if (HAS_PCH_CPT(dev)) |
768 | hotplug_mask = SDE_HOTPLUG_MASK_CPT; | |
769 | else | |
770 | hotplug_mask = SDE_HOTPLUG_MASK; | |
771 | ||
c7c85101 | 772 | ret = IRQ_HANDLED; |
036a4a7d | 773 | |
e7b4c6b1 DV |
774 | if (IS_GEN5(dev)) |
775 | ilk_gt_irq_handler(dev, dev_priv, gt_iir); | |
776 | else | |
777 | snb_gt_irq_handler(dev, dev_priv, gt_iir); | |
01c66889 | 778 | |
c7c85101 | 779 | if (de_iir & DE_GSE) |
3b617967 | 780 | intel_opregion_gse_intr(dev); |
c650156a | 781 | |
f072d2e7 | 782 | if (de_iir & DE_PLANEA_FLIP_DONE) { |
013d5aa2 | 783 | intel_prepare_page_flip(dev, 0); |
2bbda389 | 784 | intel_finish_page_flip_plane(dev, 0); |
f072d2e7 | 785 | } |
013d5aa2 | 786 | |
f072d2e7 | 787 | if (de_iir & DE_PLANEB_FLIP_DONE) { |
013d5aa2 | 788 | intel_prepare_page_flip(dev, 1); |
2bbda389 | 789 | intel_finish_page_flip_plane(dev, 1); |
f072d2e7 | 790 | } |
013d5aa2 | 791 | |
f072d2e7 | 792 | if (de_iir & DE_PIPEA_VBLANK) |
c062df61 LP |
793 | drm_handle_vblank(dev, 0); |
794 | ||
f072d2e7 | 795 | if (de_iir & DE_PIPEB_VBLANK) |
c062df61 LP |
796 | drm_handle_vblank(dev, 1); |
797 | ||
c7c85101 | 798 | /* check event from PCH */ |
776ad806 JB |
799 | if (de_iir & DE_PCH_EVENT) { |
800 | if (pch_iir & hotplug_mask) | |
801 | queue_work(dev_priv->wq, &dev_priv->hotplug_work); | |
23e81d69 AJ |
802 | if (HAS_PCH_CPT(dev)) |
803 | cpt_irq_handler(dev, pch_iir); | |
804 | else | |
805 | ibx_irq_handler(dev, pch_iir); | |
776ad806 | 806 | } |
036a4a7d | 807 | |
73edd18f DV |
808 | if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) |
809 | ironlake_handle_rps_change(dev); | |
f97108d1 | 810 | |
fc6826d1 CW |
811 | if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS) |
812 | gen6_queue_rps_work(dev_priv, pm_iir); | |
3b8d8d91 | 813 | |
c7c85101 ZN |
814 | /* should clear PCH hotplug event before clear CPU irq */ |
815 | I915_WRITE(SDEIIR, pch_iir); | |
816 | I915_WRITE(GTIIR, gt_iir); | |
817 | I915_WRITE(DEIIR, de_iir); | |
4912d041 | 818 | I915_WRITE(GEN6_PMIIR, pm_iir); |
c7c85101 ZN |
819 | |
820 | done: | |
2d109a84 | 821 | I915_WRITE(DEIER, de_ier); |
3143a2bf | 822 | POSTING_READ(DEIER); |
2d109a84 | 823 | |
036a4a7d ZW |
824 | return ret; |
825 | } | |
826 | ||
8a905236 JB |
827 | /** |
828 | * i915_error_work_func - do process context error handling work | |
829 | * @work: work struct | |
830 | * | |
831 | * Fire an error uevent so userspace can see that a hang or error | |
832 | * was detected. | |
833 | */ | |
834 | static void i915_error_work_func(struct work_struct *work) | |
835 | { | |
836 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
837 | error_work); | |
838 | struct drm_device *dev = dev_priv->dev; | |
f316a42c BG |
839 | char *error_event[] = { "ERROR=1", NULL }; |
840 | char *reset_event[] = { "RESET=1", NULL }; | |
841 | char *reset_done_event[] = { "ERROR=0", NULL }; | |
8a905236 | 842 | |
f316a42c BG |
843 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); |
844 | ||
ba1234d1 | 845 | if (atomic_read(&dev_priv->mm.wedged)) { |
f803aa55 CW |
846 | DRM_DEBUG_DRIVER("resetting chip\n"); |
847 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); | |
d4b8bb2a | 848 | if (!i915_reset(dev)) { |
f803aa55 CW |
849 | atomic_set(&dev_priv->mm.wedged, 0); |
850 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); | |
f316a42c | 851 | } |
30dbf0c0 | 852 | complete_all(&dev_priv->error_completion); |
f316a42c | 853 | } |
8a905236 JB |
854 | } |
855 | ||
85f9e50d DV |
856 | /* NB: please notice the memset */ |
857 | static void i915_get_extra_instdone(struct drm_device *dev, | |
858 | uint32_t *instdone) | |
859 | { | |
860 | struct drm_i915_private *dev_priv = dev->dev_private; | |
861 | memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG); | |
862 | ||
863 | switch(INTEL_INFO(dev)->gen) { | |
864 | case 2: | |
865 | case 3: | |
866 | instdone[0] = I915_READ(INSTDONE); | |
867 | break; | |
868 | case 4: | |
869 | case 5: | |
870 | case 6: | |
871 | instdone[0] = I915_READ(INSTDONE_I965); | |
872 | instdone[1] = I915_READ(INSTDONE1); | |
873 | break; | |
874 | default: | |
875 | WARN_ONCE(1, "Unsupported platform\n"); | |
876 | case 7: | |
877 | instdone[0] = I915_READ(GEN7_INSTDONE_1); | |
878 | instdone[1] = I915_READ(GEN7_SC_INSTDONE); | |
879 | instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE); | |
880 | instdone[3] = I915_READ(GEN7_ROW_INSTDONE); | |
881 | break; | |
882 | } | |
883 | } | |
884 | ||
3bd3c932 | 885 | #ifdef CONFIG_DEBUG_FS |
9df30794 | 886 | static struct drm_i915_error_object * |
bcfb2e28 | 887 | i915_error_object_create(struct drm_i915_private *dev_priv, |
05394f39 | 888 | struct drm_i915_gem_object *src) |
9df30794 CW |
889 | { |
890 | struct drm_i915_error_object *dst; | |
9da3da66 | 891 | int i, count; |
e56660dd | 892 | u32 reloc_offset; |
9df30794 | 893 | |
05394f39 | 894 | if (src == NULL || src->pages == NULL) |
9df30794 CW |
895 | return NULL; |
896 | ||
9da3da66 | 897 | count = src->base.size / PAGE_SIZE; |
9df30794 | 898 | |
9da3da66 | 899 | dst = kmalloc(sizeof(*dst) + count * sizeof(u32 *), GFP_ATOMIC); |
9df30794 CW |
900 | if (dst == NULL) |
901 | return NULL; | |
902 | ||
05394f39 | 903 | reloc_offset = src->gtt_offset; |
9da3da66 | 904 | for (i = 0; i < count; i++) { |
788885ae | 905 | unsigned long flags; |
e56660dd | 906 | void *d; |
788885ae | 907 | |
e56660dd | 908 | d = kmalloc(PAGE_SIZE, GFP_ATOMIC); |
9df30794 CW |
909 | if (d == NULL) |
910 | goto unwind; | |
e56660dd | 911 | |
788885ae | 912 | local_irq_save(flags); |
74898d7e DV |
913 | if (reloc_offset < dev_priv->mm.gtt_mappable_end && |
914 | src->has_global_gtt_mapping) { | |
172975aa CW |
915 | void __iomem *s; |
916 | ||
917 | /* Simply ignore tiling or any overlapping fence. | |
918 | * It's part of the error state, and this hopefully | |
919 | * captures what the GPU read. | |
920 | */ | |
921 | ||
922 | s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, | |
923 | reloc_offset); | |
924 | memcpy_fromio(d, s, PAGE_SIZE); | |
925 | io_mapping_unmap_atomic(s); | |
926 | } else { | |
9da3da66 | 927 | struct page *page; |
172975aa CW |
928 | void *s; |
929 | ||
9da3da66 | 930 | page = i915_gem_object_get_page(src, i); |
172975aa | 931 | |
9da3da66 CW |
932 | drm_clflush_pages(&page, 1); |
933 | ||
934 | s = kmap_atomic(page); | |
172975aa CW |
935 | memcpy(d, s, PAGE_SIZE); |
936 | kunmap_atomic(s); | |
937 | ||
9da3da66 | 938 | drm_clflush_pages(&page, 1); |
172975aa | 939 | } |
788885ae | 940 | local_irq_restore(flags); |
e56660dd | 941 | |
9da3da66 | 942 | dst->pages[i] = d; |
e56660dd CW |
943 | |
944 | reloc_offset += PAGE_SIZE; | |
9df30794 | 945 | } |
9da3da66 | 946 | dst->page_count = count; |
05394f39 | 947 | dst->gtt_offset = src->gtt_offset; |
9df30794 CW |
948 | |
949 | return dst; | |
950 | ||
951 | unwind: | |
9da3da66 CW |
952 | while (i--) |
953 | kfree(dst->pages[i]); | |
9df30794 CW |
954 | kfree(dst); |
955 | return NULL; | |
956 | } | |
957 | ||
958 | static void | |
959 | i915_error_object_free(struct drm_i915_error_object *obj) | |
960 | { | |
961 | int page; | |
962 | ||
963 | if (obj == NULL) | |
964 | return; | |
965 | ||
966 | for (page = 0; page < obj->page_count; page++) | |
967 | kfree(obj->pages[page]); | |
968 | ||
969 | kfree(obj); | |
970 | } | |
971 | ||
742cbee8 DV |
972 | void |
973 | i915_error_state_free(struct kref *error_ref) | |
9df30794 | 974 | { |
742cbee8 DV |
975 | struct drm_i915_error_state *error = container_of(error_ref, |
976 | typeof(*error), ref); | |
e2f973d5 CW |
977 | int i; |
978 | ||
52d39a21 CW |
979 | for (i = 0; i < ARRAY_SIZE(error->ring); i++) { |
980 | i915_error_object_free(error->ring[i].batchbuffer); | |
981 | i915_error_object_free(error->ring[i].ringbuffer); | |
982 | kfree(error->ring[i].requests); | |
983 | } | |
e2f973d5 | 984 | |
9df30794 | 985 | kfree(error->active_bo); |
6ef3d427 | 986 | kfree(error->overlay); |
9df30794 CW |
987 | kfree(error); |
988 | } | |
1b50247a CW |
989 | static void capture_bo(struct drm_i915_error_buffer *err, |
990 | struct drm_i915_gem_object *obj) | |
991 | { | |
992 | err->size = obj->base.size; | |
993 | err->name = obj->base.name; | |
0201f1ec CW |
994 | err->rseqno = obj->last_read_seqno; |
995 | err->wseqno = obj->last_write_seqno; | |
1b50247a CW |
996 | err->gtt_offset = obj->gtt_offset; |
997 | err->read_domains = obj->base.read_domains; | |
998 | err->write_domain = obj->base.write_domain; | |
999 | err->fence_reg = obj->fence_reg; | |
1000 | err->pinned = 0; | |
1001 | if (obj->pin_count > 0) | |
1002 | err->pinned = 1; | |
1003 | if (obj->user_pin_count > 0) | |
1004 | err->pinned = -1; | |
1005 | err->tiling = obj->tiling_mode; | |
1006 | err->dirty = obj->dirty; | |
1007 | err->purgeable = obj->madv != I915_MADV_WILLNEED; | |
1008 | err->ring = obj->ring ? obj->ring->id : -1; | |
1009 | err->cache_level = obj->cache_level; | |
1010 | } | |
9df30794 | 1011 | |
1b50247a CW |
1012 | static u32 capture_active_bo(struct drm_i915_error_buffer *err, |
1013 | int count, struct list_head *head) | |
c724e8a9 CW |
1014 | { |
1015 | struct drm_i915_gem_object *obj; | |
1016 | int i = 0; | |
1017 | ||
1018 | list_for_each_entry(obj, head, mm_list) { | |
1b50247a | 1019 | capture_bo(err++, obj); |
c724e8a9 CW |
1020 | if (++i == count) |
1021 | break; | |
1b50247a CW |
1022 | } |
1023 | ||
1024 | return i; | |
1025 | } | |
1026 | ||
1027 | static u32 capture_pinned_bo(struct drm_i915_error_buffer *err, | |
1028 | int count, struct list_head *head) | |
1029 | { | |
1030 | struct drm_i915_gem_object *obj; | |
1031 | int i = 0; | |
1032 | ||
1033 | list_for_each_entry(obj, head, gtt_list) { | |
1034 | if (obj->pin_count == 0) | |
1035 | continue; | |
c724e8a9 | 1036 | |
1b50247a CW |
1037 | capture_bo(err++, obj); |
1038 | if (++i == count) | |
1039 | break; | |
c724e8a9 CW |
1040 | } |
1041 | ||
1042 | return i; | |
1043 | } | |
1044 | ||
748ebc60 CW |
1045 | static void i915_gem_record_fences(struct drm_device *dev, |
1046 | struct drm_i915_error_state *error) | |
1047 | { | |
1048 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1049 | int i; | |
1050 | ||
1051 | /* Fences */ | |
1052 | switch (INTEL_INFO(dev)->gen) { | |
775d17b6 | 1053 | case 7: |
748ebc60 CW |
1054 | case 6: |
1055 | for (i = 0; i < 16; i++) | |
1056 | error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); | |
1057 | break; | |
1058 | case 5: | |
1059 | case 4: | |
1060 | for (i = 0; i < 16; i++) | |
1061 | error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); | |
1062 | break; | |
1063 | case 3: | |
1064 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
1065 | for (i = 0; i < 8; i++) | |
1066 | error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); | |
1067 | case 2: | |
1068 | for (i = 0; i < 8; i++) | |
1069 | error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); | |
1070 | break; | |
1071 | ||
1072 | } | |
1073 | } | |
1074 | ||
bcfb2e28 CW |
1075 | static struct drm_i915_error_object * |
1076 | i915_error_first_batchbuffer(struct drm_i915_private *dev_priv, | |
1077 | struct intel_ring_buffer *ring) | |
1078 | { | |
1079 | struct drm_i915_gem_object *obj; | |
1080 | u32 seqno; | |
1081 | ||
1082 | if (!ring->get_seqno) | |
1083 | return NULL; | |
1084 | ||
b2eadbc8 | 1085 | seqno = ring->get_seqno(ring, false); |
bcfb2e28 CW |
1086 | list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) { |
1087 | if (obj->ring != ring) | |
1088 | continue; | |
1089 | ||
0201f1ec | 1090 | if (i915_seqno_passed(seqno, obj->last_read_seqno)) |
bcfb2e28 CW |
1091 | continue; |
1092 | ||
1093 | if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0) | |
1094 | continue; | |
1095 | ||
1096 | /* We need to copy these to an anonymous buffer as the simplest | |
1097 | * method to avoid being overwritten by userspace. | |
1098 | */ | |
1099 | return i915_error_object_create(dev_priv, obj); | |
1100 | } | |
1101 | ||
1102 | return NULL; | |
1103 | } | |
1104 | ||
d27b1e0e DV |
1105 | static void i915_record_ring_state(struct drm_device *dev, |
1106 | struct drm_i915_error_state *error, | |
1107 | struct intel_ring_buffer *ring) | |
1108 | { | |
1109 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1110 | ||
33f3f518 | 1111 | if (INTEL_INFO(dev)->gen >= 6) { |
12f55818 | 1112 | error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50); |
33f3f518 | 1113 | error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring)); |
7e3b8737 DV |
1114 | error->semaphore_mboxes[ring->id][0] |
1115 | = I915_READ(RING_SYNC_0(ring->mmio_base)); | |
1116 | error->semaphore_mboxes[ring->id][1] | |
1117 | = I915_READ(RING_SYNC_1(ring->mmio_base)); | |
33f3f518 | 1118 | } |
c1cd90ed | 1119 | |
d27b1e0e | 1120 | if (INTEL_INFO(dev)->gen >= 4) { |
9d2f41fa | 1121 | error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base)); |
d27b1e0e DV |
1122 | error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base)); |
1123 | error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base)); | |
1124 | error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base)); | |
c1cd90ed | 1125 | error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base)); |
050ee91f | 1126 | if (ring->id == RCS) |
d27b1e0e | 1127 | error->bbaddr = I915_READ64(BB_ADDR); |
d27b1e0e | 1128 | } else { |
9d2f41fa | 1129 | error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX); |
d27b1e0e DV |
1130 | error->ipeir[ring->id] = I915_READ(IPEIR); |
1131 | error->ipehr[ring->id] = I915_READ(IPEHR); | |
1132 | error->instdone[ring->id] = I915_READ(INSTDONE); | |
d27b1e0e DV |
1133 | } |
1134 | ||
9574b3fe | 1135 | error->waiting[ring->id] = waitqueue_active(&ring->irq_queue); |
c1cd90ed | 1136 | error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base)); |
b2eadbc8 | 1137 | error->seqno[ring->id] = ring->get_seqno(ring, false); |
d27b1e0e | 1138 | error->acthd[ring->id] = intel_ring_get_active_head(ring); |
c1cd90ed DV |
1139 | error->head[ring->id] = I915_READ_HEAD(ring); |
1140 | error->tail[ring->id] = I915_READ_TAIL(ring); | |
7e3b8737 DV |
1141 | |
1142 | error->cpu_ring_head[ring->id] = ring->head; | |
1143 | error->cpu_ring_tail[ring->id] = ring->tail; | |
d27b1e0e DV |
1144 | } |
1145 | ||
52d39a21 CW |
1146 | static void i915_gem_record_rings(struct drm_device *dev, |
1147 | struct drm_i915_error_state *error) | |
1148 | { | |
1149 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b4519513 | 1150 | struct intel_ring_buffer *ring; |
52d39a21 CW |
1151 | struct drm_i915_gem_request *request; |
1152 | int i, count; | |
1153 | ||
b4519513 | 1154 | for_each_ring(ring, dev_priv, i) { |
52d39a21 CW |
1155 | i915_record_ring_state(dev, error, ring); |
1156 | ||
1157 | error->ring[i].batchbuffer = | |
1158 | i915_error_first_batchbuffer(dev_priv, ring); | |
1159 | ||
1160 | error->ring[i].ringbuffer = | |
1161 | i915_error_object_create(dev_priv, ring->obj); | |
1162 | ||
1163 | count = 0; | |
1164 | list_for_each_entry(request, &ring->request_list, list) | |
1165 | count++; | |
1166 | ||
1167 | error->ring[i].num_requests = count; | |
1168 | error->ring[i].requests = | |
1169 | kmalloc(count*sizeof(struct drm_i915_error_request), | |
1170 | GFP_ATOMIC); | |
1171 | if (error->ring[i].requests == NULL) { | |
1172 | error->ring[i].num_requests = 0; | |
1173 | continue; | |
1174 | } | |
1175 | ||
1176 | count = 0; | |
1177 | list_for_each_entry(request, &ring->request_list, list) { | |
1178 | struct drm_i915_error_request *erq; | |
1179 | ||
1180 | erq = &error->ring[i].requests[count++]; | |
1181 | erq->seqno = request->seqno; | |
1182 | erq->jiffies = request->emitted_jiffies; | |
ee4f42b1 | 1183 | erq->tail = request->tail; |
52d39a21 CW |
1184 | } |
1185 | } | |
1186 | } | |
1187 | ||
8a905236 JB |
1188 | /** |
1189 | * i915_capture_error_state - capture an error record for later analysis | |
1190 | * @dev: drm device | |
1191 | * | |
1192 | * Should be called when an error is detected (either a hang or an error | |
1193 | * interrupt) to capture error state from the time of the error. Fills | |
1194 | * out a structure which becomes available in debugfs for user level tools | |
1195 | * to pick up. | |
1196 | */ | |
63eeaf38 JB |
1197 | static void i915_capture_error_state(struct drm_device *dev) |
1198 | { | |
1199 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 1200 | struct drm_i915_gem_object *obj; |
63eeaf38 JB |
1201 | struct drm_i915_error_state *error; |
1202 | unsigned long flags; | |
9db4a9c7 | 1203 | int i, pipe; |
63eeaf38 JB |
1204 | |
1205 | spin_lock_irqsave(&dev_priv->error_lock, flags); | |
9df30794 CW |
1206 | error = dev_priv->first_error; |
1207 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); | |
1208 | if (error) | |
1209 | return; | |
63eeaf38 | 1210 | |
9db4a9c7 | 1211 | /* Account for pipe specific data like PIPE*STAT */ |
33f3f518 | 1212 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
63eeaf38 | 1213 | if (!error) { |
9df30794 CW |
1214 | DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); |
1215 | return; | |
63eeaf38 JB |
1216 | } |
1217 | ||
b6f7833b CW |
1218 | DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n", |
1219 | dev->primary->index); | |
2fa772f3 | 1220 | |
742cbee8 | 1221 | kref_init(&error->ref); |
63eeaf38 JB |
1222 | error->eir = I915_READ(EIR); |
1223 | error->pgtbl_er = I915_READ(PGTBL_ER); | |
b9a3906b | 1224 | error->ccid = I915_READ(CCID); |
be998e2e BW |
1225 | |
1226 | if (HAS_PCH_SPLIT(dev)) | |
1227 | error->ier = I915_READ(DEIER) | I915_READ(GTIER); | |
1228 | else if (IS_VALLEYVIEW(dev)) | |
1229 | error->ier = I915_READ(GTIER) | I915_READ(VLV_IER); | |
1230 | else if (IS_GEN2(dev)) | |
1231 | error->ier = I915_READ16(IER); | |
1232 | else | |
1233 | error->ier = I915_READ(IER); | |
1234 | ||
9db4a9c7 JB |
1235 | for_each_pipe(pipe) |
1236 | error->pipestat[pipe] = I915_READ(PIPESTAT(pipe)); | |
d27b1e0e | 1237 | |
33f3f518 | 1238 | if (INTEL_INFO(dev)->gen >= 6) { |
f406839f | 1239 | error->error = I915_READ(ERROR_GEN6); |
33f3f518 DV |
1240 | error->done_reg = I915_READ(DONE_REG); |
1241 | } | |
d27b1e0e | 1242 | |
71e172e8 BW |
1243 | if (INTEL_INFO(dev)->gen == 7) |
1244 | error->err_int = I915_READ(GEN7_ERR_INT); | |
1245 | ||
050ee91f BW |
1246 | i915_get_extra_instdone(dev, error->extra_instdone); |
1247 | ||
748ebc60 | 1248 | i915_gem_record_fences(dev, error); |
52d39a21 | 1249 | i915_gem_record_rings(dev, error); |
9df30794 | 1250 | |
c724e8a9 | 1251 | /* Record buffers on the active and pinned lists. */ |
9df30794 | 1252 | error->active_bo = NULL; |
c724e8a9 | 1253 | error->pinned_bo = NULL; |
9df30794 | 1254 | |
bcfb2e28 CW |
1255 | i = 0; |
1256 | list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) | |
1257 | i++; | |
1258 | error->active_bo_count = i; | |
6c085a72 | 1259 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) |
1b50247a CW |
1260 | if (obj->pin_count) |
1261 | i++; | |
bcfb2e28 | 1262 | error->pinned_bo_count = i - error->active_bo_count; |
c724e8a9 | 1263 | |
8e934dbf CW |
1264 | error->active_bo = NULL; |
1265 | error->pinned_bo = NULL; | |
bcfb2e28 CW |
1266 | if (i) { |
1267 | error->active_bo = kmalloc(sizeof(*error->active_bo)*i, | |
9df30794 | 1268 | GFP_ATOMIC); |
c724e8a9 CW |
1269 | if (error->active_bo) |
1270 | error->pinned_bo = | |
1271 | error->active_bo + error->active_bo_count; | |
9df30794 CW |
1272 | } |
1273 | ||
c724e8a9 CW |
1274 | if (error->active_bo) |
1275 | error->active_bo_count = | |
1b50247a CW |
1276 | capture_active_bo(error->active_bo, |
1277 | error->active_bo_count, | |
1278 | &dev_priv->mm.active_list); | |
c724e8a9 CW |
1279 | |
1280 | if (error->pinned_bo) | |
1281 | error->pinned_bo_count = | |
1b50247a CW |
1282 | capture_pinned_bo(error->pinned_bo, |
1283 | error->pinned_bo_count, | |
6c085a72 | 1284 | &dev_priv->mm.bound_list); |
c724e8a9 | 1285 | |
9df30794 CW |
1286 | do_gettimeofday(&error->time); |
1287 | ||
6ef3d427 | 1288 | error->overlay = intel_overlay_capture_error_state(dev); |
c4a1d9e4 | 1289 | error->display = intel_display_capture_error_state(dev); |
6ef3d427 | 1290 | |
9df30794 CW |
1291 | spin_lock_irqsave(&dev_priv->error_lock, flags); |
1292 | if (dev_priv->first_error == NULL) { | |
1293 | dev_priv->first_error = error; | |
1294 | error = NULL; | |
1295 | } | |
63eeaf38 | 1296 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); |
9df30794 CW |
1297 | |
1298 | if (error) | |
742cbee8 | 1299 | i915_error_state_free(&error->ref); |
9df30794 CW |
1300 | } |
1301 | ||
1302 | void i915_destroy_error_state(struct drm_device *dev) | |
1303 | { | |
1304 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1305 | struct drm_i915_error_state *error; | |
6dc0e816 | 1306 | unsigned long flags; |
9df30794 | 1307 | |
6dc0e816 | 1308 | spin_lock_irqsave(&dev_priv->error_lock, flags); |
9df30794 CW |
1309 | error = dev_priv->first_error; |
1310 | dev_priv->first_error = NULL; | |
6dc0e816 | 1311 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); |
9df30794 CW |
1312 | |
1313 | if (error) | |
742cbee8 | 1314 | kref_put(&error->ref, i915_error_state_free); |
63eeaf38 | 1315 | } |
3bd3c932 CW |
1316 | #else |
1317 | #define i915_capture_error_state(x) | |
1318 | #endif | |
63eeaf38 | 1319 | |
35aed2e6 | 1320 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
1321 | { |
1322 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bd9854f9 | 1323 | uint32_t instdone[I915_NUM_INSTDONE_REG]; |
8a905236 | 1324 | u32 eir = I915_READ(EIR); |
050ee91f | 1325 | int pipe, i; |
8a905236 | 1326 | |
35aed2e6 CW |
1327 | if (!eir) |
1328 | return; | |
8a905236 | 1329 | |
a70491cc | 1330 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
8a905236 | 1331 | |
bd9854f9 BW |
1332 | i915_get_extra_instdone(dev, instdone); |
1333 | ||
8a905236 JB |
1334 | if (IS_G4X(dev)) { |
1335 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
1336 | u32 ipeir = I915_READ(IPEIR_I965); | |
1337 | ||
a70491cc JP |
1338 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
1339 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
050ee91f BW |
1340 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
1341 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a70491cc | 1342 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 1343 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 1344 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 1345 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
1346 | } |
1347 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
1348 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
1349 | pr_err("page table error\n"); |
1350 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 1351 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 1352 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
1353 | } |
1354 | } | |
1355 | ||
a6c45cf0 | 1356 | if (!IS_GEN2(dev)) { |
8a905236 JB |
1357 | if (eir & I915_ERROR_PAGE_TABLE) { |
1358 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
1359 | pr_err("page table error\n"); |
1360 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 1361 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 1362 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
1363 | } |
1364 | } | |
1365 | ||
1366 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
a70491cc | 1367 | pr_err("memory refresh error:\n"); |
9db4a9c7 | 1368 | for_each_pipe(pipe) |
a70491cc | 1369 | pr_err("pipe %c stat: 0x%08x\n", |
9db4a9c7 | 1370 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
8a905236 JB |
1371 | /* pipestat has already been acked */ |
1372 | } | |
1373 | if (eir & I915_ERROR_INSTRUCTION) { | |
a70491cc JP |
1374 | pr_err("instruction error\n"); |
1375 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); | |
050ee91f BW |
1376 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
1377 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a6c45cf0 | 1378 | if (INTEL_INFO(dev)->gen < 4) { |
8a905236 JB |
1379 | u32 ipeir = I915_READ(IPEIR); |
1380 | ||
a70491cc JP |
1381 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
1382 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); | |
a70491cc | 1383 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); |
8a905236 | 1384 | I915_WRITE(IPEIR, ipeir); |
3143a2bf | 1385 | POSTING_READ(IPEIR); |
8a905236 JB |
1386 | } else { |
1387 | u32 ipeir = I915_READ(IPEIR_I965); | |
1388 | ||
a70491cc JP |
1389 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
1390 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
a70491cc | 1391 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 1392 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 1393 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 1394 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
1395 | } |
1396 | } | |
1397 | ||
1398 | I915_WRITE(EIR, eir); | |
3143a2bf | 1399 | POSTING_READ(EIR); |
8a905236 JB |
1400 | eir = I915_READ(EIR); |
1401 | if (eir) { | |
1402 | /* | |
1403 | * some errors might have become stuck, | |
1404 | * mask them. | |
1405 | */ | |
1406 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
1407 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
1408 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
1409 | } | |
35aed2e6 CW |
1410 | } |
1411 | ||
1412 | /** | |
1413 | * i915_handle_error - handle an error interrupt | |
1414 | * @dev: drm device | |
1415 | * | |
1416 | * Do some basic checking of regsiter state at error interrupt time and | |
1417 | * dump it to the syslog. Also call i915_capture_error_state() to make | |
1418 | * sure we get a record and make it available in debugfs. Fire a uevent | |
1419 | * so userspace knows something bad happened (should trigger collection | |
1420 | * of a ring dump etc.). | |
1421 | */ | |
527f9e90 | 1422 | void i915_handle_error(struct drm_device *dev, bool wedged) |
35aed2e6 CW |
1423 | { |
1424 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b4519513 CW |
1425 | struct intel_ring_buffer *ring; |
1426 | int i; | |
35aed2e6 CW |
1427 | |
1428 | i915_capture_error_state(dev); | |
1429 | i915_report_and_clear_eir(dev); | |
8a905236 | 1430 | |
ba1234d1 | 1431 | if (wedged) { |
30dbf0c0 | 1432 | INIT_COMPLETION(dev_priv->error_completion); |
ba1234d1 BG |
1433 | atomic_set(&dev_priv->mm.wedged, 1); |
1434 | ||
11ed50ec BG |
1435 | /* |
1436 | * Wakeup waiting processes so they don't hang | |
1437 | */ | |
b4519513 CW |
1438 | for_each_ring(ring, dev_priv, i) |
1439 | wake_up_all(&ring->irq_queue); | |
11ed50ec BG |
1440 | } |
1441 | ||
9c9fe1f8 | 1442 | queue_work(dev_priv->wq, &dev_priv->error_work); |
8a905236 JB |
1443 | } |
1444 | ||
4e5359cd SF |
1445 | static void i915_pageflip_stall_check(struct drm_device *dev, int pipe) |
1446 | { | |
1447 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1448 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1449 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 1450 | struct drm_i915_gem_object *obj; |
4e5359cd SF |
1451 | struct intel_unpin_work *work; |
1452 | unsigned long flags; | |
1453 | bool stall_detected; | |
1454 | ||
1455 | /* Ignore early vblank irqs */ | |
1456 | if (intel_crtc == NULL) | |
1457 | return; | |
1458 | ||
1459 | spin_lock_irqsave(&dev->event_lock, flags); | |
1460 | work = intel_crtc->unpin_work; | |
1461 | ||
1462 | if (work == NULL || work->pending || !work->enable_stall_check) { | |
1463 | /* Either the pending flip IRQ arrived, or we're too early. Don't check */ | |
1464 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
1465 | return; | |
1466 | } | |
1467 | ||
1468 | /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ | |
05394f39 | 1469 | obj = work->pending_flip_obj; |
a6c45cf0 | 1470 | if (INTEL_INFO(dev)->gen >= 4) { |
9db4a9c7 | 1471 | int dspsurf = DSPSURF(intel_crtc->plane); |
446f2545 AR |
1472 | stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) == |
1473 | obj->gtt_offset; | |
4e5359cd | 1474 | } else { |
9db4a9c7 | 1475 | int dspaddr = DSPADDR(intel_crtc->plane); |
05394f39 | 1476 | stall_detected = I915_READ(dspaddr) == (obj->gtt_offset + |
01f2c773 | 1477 | crtc->y * crtc->fb->pitches[0] + |
4e5359cd SF |
1478 | crtc->x * crtc->fb->bits_per_pixel/8); |
1479 | } | |
1480 | ||
1481 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
1482 | ||
1483 | if (stall_detected) { | |
1484 | DRM_DEBUG_DRIVER("Pageflip stall detected\n"); | |
1485 | intel_prepare_page_flip(dev, intel_crtc->plane); | |
1486 | } | |
1487 | } | |
1488 | ||
42f52ef8 KP |
1489 | /* Called from drm generic code, passed 'crtc' which |
1490 | * we use as a pipe index | |
1491 | */ | |
f71d4af4 | 1492 | static int i915_enable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 JB |
1493 | { |
1494 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 1495 | unsigned long irqflags; |
71e0ffa5 | 1496 | |
5eddb70b | 1497 | if (!i915_pipe_enabled(dev, pipe)) |
71e0ffa5 | 1498 | return -EINVAL; |
0a3e67a4 | 1499 | |
1ec14ad3 | 1500 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 1501 | if (INTEL_INFO(dev)->gen >= 4) |
7c463586 KP |
1502 | i915_enable_pipestat(dev_priv, pipe, |
1503 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 1504 | else |
7c463586 KP |
1505 | i915_enable_pipestat(dev_priv, pipe, |
1506 | PIPE_VBLANK_INTERRUPT_ENABLE); | |
8692d00e CW |
1507 | |
1508 | /* maintain vblank delivery even in deep C-states */ | |
1509 | if (dev_priv->info->gen == 3) | |
6b26c86d | 1510 | I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS)); |
1ec14ad3 | 1511 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
8692d00e | 1512 | |
0a3e67a4 JB |
1513 | return 0; |
1514 | } | |
1515 | ||
f71d4af4 | 1516 | static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
f796cf8f JB |
1517 | { |
1518 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1519 | unsigned long irqflags; | |
1520 | ||
1521 | if (!i915_pipe_enabled(dev, pipe)) | |
1522 | return -EINVAL; | |
1523 | ||
1524 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
1525 | ironlake_enable_display_irq(dev_priv, (pipe == 0) ? | |
0206e353 | 1526 | DE_PIPEA_VBLANK : DE_PIPEB_VBLANK); |
f796cf8f JB |
1527 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
1528 | ||
1529 | return 0; | |
1530 | } | |
1531 | ||
f71d4af4 | 1532 | static int ivybridge_enable_vblank(struct drm_device *dev, int pipe) |
b1f14ad0 JB |
1533 | { |
1534 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1535 | unsigned long irqflags; | |
1536 | ||
1537 | if (!i915_pipe_enabled(dev, pipe)) | |
1538 | return -EINVAL; | |
1539 | ||
1540 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b615b57a CW |
1541 | ironlake_enable_display_irq(dev_priv, |
1542 | DE_PIPEA_VBLANK_IVB << (5 * pipe)); | |
b1f14ad0 JB |
1543 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
1544 | ||
1545 | return 0; | |
1546 | } | |
1547 | ||
7e231dbe JB |
1548 | static int valleyview_enable_vblank(struct drm_device *dev, int pipe) |
1549 | { | |
1550 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1551 | unsigned long irqflags; | |
31acc7f5 | 1552 | u32 imr; |
7e231dbe JB |
1553 | |
1554 | if (!i915_pipe_enabled(dev, pipe)) | |
1555 | return -EINVAL; | |
1556 | ||
1557 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
7e231dbe | 1558 | imr = I915_READ(VLV_IMR); |
31acc7f5 | 1559 | if (pipe == 0) |
7e231dbe | 1560 | imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; |
31acc7f5 | 1561 | else |
7e231dbe | 1562 | imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
7e231dbe | 1563 | I915_WRITE(VLV_IMR, imr); |
31acc7f5 JB |
1564 | i915_enable_pipestat(dev_priv, pipe, |
1565 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
7e231dbe JB |
1566 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
1567 | ||
1568 | return 0; | |
1569 | } | |
1570 | ||
42f52ef8 KP |
1571 | /* Called from drm generic code, passed 'crtc' which |
1572 | * we use as a pipe index | |
1573 | */ | |
f71d4af4 | 1574 | static void i915_disable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 JB |
1575 | { |
1576 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 1577 | unsigned long irqflags; |
0a3e67a4 | 1578 | |
1ec14ad3 | 1579 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
8692d00e | 1580 | if (dev_priv->info->gen == 3) |
6b26c86d | 1581 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS)); |
8692d00e | 1582 | |
f796cf8f JB |
1583 | i915_disable_pipestat(dev_priv, pipe, |
1584 | PIPE_VBLANK_INTERRUPT_ENABLE | | |
1585 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
1586 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
1587 | } | |
1588 | ||
f71d4af4 | 1589 | static void ironlake_disable_vblank(struct drm_device *dev, int pipe) |
f796cf8f JB |
1590 | { |
1591 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1592 | unsigned long irqflags; | |
1593 | ||
1594 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
1595 | ironlake_disable_display_irq(dev_priv, (pipe == 0) ? | |
0206e353 | 1596 | DE_PIPEA_VBLANK : DE_PIPEB_VBLANK); |
1ec14ad3 | 1597 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
0a3e67a4 JB |
1598 | } |
1599 | ||
f71d4af4 | 1600 | static void ivybridge_disable_vblank(struct drm_device *dev, int pipe) |
b1f14ad0 JB |
1601 | { |
1602 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1603 | unsigned long irqflags; | |
1604 | ||
1605 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b615b57a CW |
1606 | ironlake_disable_display_irq(dev_priv, |
1607 | DE_PIPEA_VBLANK_IVB << (pipe * 5)); | |
b1f14ad0 JB |
1608 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
1609 | } | |
1610 | ||
7e231dbe JB |
1611 | static void valleyview_disable_vblank(struct drm_device *dev, int pipe) |
1612 | { | |
1613 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1614 | unsigned long irqflags; | |
31acc7f5 | 1615 | u32 imr; |
7e231dbe JB |
1616 | |
1617 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 JB |
1618 | i915_disable_pipestat(dev_priv, pipe, |
1619 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
7e231dbe | 1620 | imr = I915_READ(VLV_IMR); |
31acc7f5 | 1621 | if (pipe == 0) |
7e231dbe | 1622 | imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; |
31acc7f5 | 1623 | else |
7e231dbe | 1624 | imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
7e231dbe | 1625 | I915_WRITE(VLV_IMR, imr); |
7e231dbe JB |
1626 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
1627 | } | |
1628 | ||
893eead0 CW |
1629 | static u32 |
1630 | ring_last_seqno(struct intel_ring_buffer *ring) | |
852835f3 | 1631 | { |
893eead0 CW |
1632 | return list_entry(ring->request_list.prev, |
1633 | struct drm_i915_gem_request, list)->seqno; | |
1634 | } | |
1635 | ||
1636 | static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err) | |
1637 | { | |
1638 | if (list_empty(&ring->request_list) || | |
b2eadbc8 CW |
1639 | i915_seqno_passed(ring->get_seqno(ring, false), |
1640 | ring_last_seqno(ring))) { | |
893eead0 | 1641 | /* Issue a wake-up to catch stuck h/w. */ |
9574b3fe BW |
1642 | if (waitqueue_active(&ring->irq_queue)) { |
1643 | DRM_ERROR("Hangcheck timer elapsed... %s idle\n", | |
1644 | ring->name); | |
893eead0 CW |
1645 | wake_up_all(&ring->irq_queue); |
1646 | *err = true; | |
1647 | } | |
1648 | return true; | |
1649 | } | |
1650 | return false; | |
f65d9421 BG |
1651 | } |
1652 | ||
1ec14ad3 CW |
1653 | static bool kick_ring(struct intel_ring_buffer *ring) |
1654 | { | |
1655 | struct drm_device *dev = ring->dev; | |
1656 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1657 | u32 tmp = I915_READ_CTL(ring); | |
1658 | if (tmp & RING_WAIT) { | |
1659 | DRM_ERROR("Kicking stuck wait on %s\n", | |
1660 | ring->name); | |
1661 | I915_WRITE_CTL(ring, tmp); | |
1662 | return true; | |
1663 | } | |
1ec14ad3 CW |
1664 | return false; |
1665 | } | |
1666 | ||
d1e61e7f CW |
1667 | static bool i915_hangcheck_hung(struct drm_device *dev) |
1668 | { | |
1669 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1670 | ||
1671 | if (dev_priv->hangcheck_count++ > 1) { | |
b4519513 CW |
1672 | bool hung = true; |
1673 | ||
d1e61e7f CW |
1674 | DRM_ERROR("Hangcheck timer elapsed... GPU hung\n"); |
1675 | i915_handle_error(dev, true); | |
1676 | ||
1677 | if (!IS_GEN2(dev)) { | |
b4519513 CW |
1678 | struct intel_ring_buffer *ring; |
1679 | int i; | |
1680 | ||
d1e61e7f CW |
1681 | /* Is the chip hanging on a WAIT_FOR_EVENT? |
1682 | * If so we can simply poke the RB_WAIT bit | |
1683 | * and break the hang. This should work on | |
1684 | * all but the second generation chipsets. | |
1685 | */ | |
b4519513 CW |
1686 | for_each_ring(ring, dev_priv, i) |
1687 | hung &= !kick_ring(ring); | |
d1e61e7f CW |
1688 | } |
1689 | ||
b4519513 | 1690 | return hung; |
d1e61e7f CW |
1691 | } |
1692 | ||
1693 | return false; | |
1694 | } | |
1695 | ||
f65d9421 BG |
1696 | /** |
1697 | * This is called when the chip hasn't reported back with completed | |
1698 | * batchbuffers in a long time. The first time this is called we simply record | |
1699 | * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses | |
1700 | * again, we assume the chip is wedged and try to fix it. | |
1701 | */ | |
1702 | void i915_hangcheck_elapsed(unsigned long data) | |
1703 | { | |
1704 | struct drm_device *dev = (struct drm_device *)data; | |
1705 | drm_i915_private_t *dev_priv = dev->dev_private; | |
bd9854f9 | 1706 | uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG]; |
b4519513 CW |
1707 | struct intel_ring_buffer *ring; |
1708 | bool err = false, idle; | |
1709 | int i; | |
893eead0 | 1710 | |
3e0dc6b0 BW |
1711 | if (!i915_enable_hangcheck) |
1712 | return; | |
1713 | ||
b4519513 CW |
1714 | memset(acthd, 0, sizeof(acthd)); |
1715 | idle = true; | |
1716 | for_each_ring(ring, dev_priv, i) { | |
1717 | idle &= i915_hangcheck_ring_idle(ring, &err); | |
1718 | acthd[i] = intel_ring_get_active_head(ring); | |
1719 | } | |
1720 | ||
893eead0 | 1721 | /* If all work is done then ACTHD clearly hasn't advanced. */ |
b4519513 | 1722 | if (idle) { |
d1e61e7f CW |
1723 | if (err) { |
1724 | if (i915_hangcheck_hung(dev)) | |
1725 | return; | |
1726 | ||
893eead0 | 1727 | goto repeat; |
d1e61e7f CW |
1728 | } |
1729 | ||
1730 | dev_priv->hangcheck_count = 0; | |
893eead0 CW |
1731 | return; |
1732 | } | |
b9201c14 | 1733 | |
bd9854f9 | 1734 | i915_get_extra_instdone(dev, instdone); |
b4519513 | 1735 | if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 && |
050ee91f | 1736 | memcmp(dev_priv->prev_instdone, instdone, sizeof(instdone)) == 0) { |
d1e61e7f | 1737 | if (i915_hangcheck_hung(dev)) |
cbb465e7 | 1738 | return; |
cbb465e7 CW |
1739 | } else { |
1740 | dev_priv->hangcheck_count = 0; | |
1741 | ||
b4519513 | 1742 | memcpy(dev_priv->last_acthd, acthd, sizeof(acthd)); |
050ee91f | 1743 | memcpy(dev_priv->prev_instdone, instdone, sizeof(instdone)); |
cbb465e7 | 1744 | } |
f65d9421 | 1745 | |
893eead0 | 1746 | repeat: |
f65d9421 | 1747 | /* Reset timer case chip hangs without another request being added */ |
b3b079db CW |
1748 | mod_timer(&dev_priv->hangcheck_timer, |
1749 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
f65d9421 BG |
1750 | } |
1751 | ||
1da177e4 LT |
1752 | /* drm_dma.h hooks |
1753 | */ | |
f71d4af4 | 1754 | static void ironlake_irq_preinstall(struct drm_device *dev) |
036a4a7d ZW |
1755 | { |
1756 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1757 | ||
4697995b JB |
1758 | atomic_set(&dev_priv->irq_received, 0); |
1759 | ||
036a4a7d | 1760 | I915_WRITE(HWSTAM, 0xeffe); |
bdfcdb63 | 1761 | |
036a4a7d ZW |
1762 | /* XXX hotplug from PCH */ |
1763 | ||
1764 | I915_WRITE(DEIMR, 0xffffffff); | |
1765 | I915_WRITE(DEIER, 0x0); | |
3143a2bf | 1766 | POSTING_READ(DEIER); |
036a4a7d ZW |
1767 | |
1768 | /* and GT */ | |
1769 | I915_WRITE(GTIMR, 0xffffffff); | |
1770 | I915_WRITE(GTIER, 0x0); | |
3143a2bf | 1771 | POSTING_READ(GTIER); |
c650156a ZW |
1772 | |
1773 | /* south display irq */ | |
1774 | I915_WRITE(SDEIMR, 0xffffffff); | |
1775 | I915_WRITE(SDEIER, 0x0); | |
3143a2bf | 1776 | POSTING_READ(SDEIER); |
036a4a7d ZW |
1777 | } |
1778 | ||
7e231dbe JB |
1779 | static void valleyview_irq_preinstall(struct drm_device *dev) |
1780 | { | |
1781 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1782 | int pipe; | |
1783 | ||
1784 | atomic_set(&dev_priv->irq_received, 0); | |
1785 | ||
7e231dbe JB |
1786 | /* VLV magic */ |
1787 | I915_WRITE(VLV_IMR, 0); | |
1788 | I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); | |
1789 | I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); | |
1790 | I915_WRITE(RING_IMR(BLT_RING_BASE), 0); | |
1791 | ||
7e231dbe JB |
1792 | /* and GT */ |
1793 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1794 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1795 | I915_WRITE(GTIMR, 0xffffffff); | |
1796 | I915_WRITE(GTIER, 0x0); | |
1797 | POSTING_READ(GTIER); | |
1798 | ||
1799 | I915_WRITE(DPINVGTT, 0xff); | |
1800 | ||
1801 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
1802 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
1803 | for_each_pipe(pipe) | |
1804 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
1805 | I915_WRITE(VLV_IIR, 0xffffffff); | |
1806 | I915_WRITE(VLV_IMR, 0xffffffff); | |
1807 | I915_WRITE(VLV_IER, 0x0); | |
1808 | POSTING_READ(VLV_IER); | |
1809 | } | |
1810 | ||
7fe0b973 KP |
1811 | /* |
1812 | * Enable digital hotplug on the PCH, and configure the DP short pulse | |
1813 | * duration to 2ms (which is the minimum in the Display Port spec) | |
1814 | * | |
1815 | * This register is the same on all known PCH chips. | |
1816 | */ | |
1817 | ||
1818 | static void ironlake_enable_pch_hotplug(struct drm_device *dev) | |
1819 | { | |
1820 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1821 | u32 hotplug; | |
1822 | ||
1823 | hotplug = I915_READ(PCH_PORT_HOTPLUG); | |
1824 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); | |
1825 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; | |
1826 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; | |
1827 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; | |
1828 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); | |
1829 | } | |
1830 | ||
f71d4af4 | 1831 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d ZW |
1832 | { |
1833 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1834 | /* enable kind of interrupts always enabled */ | |
013d5aa2 JB |
1835 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | |
1836 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; | |
1ec14ad3 | 1837 | u32 render_irqs; |
2d7b8366 | 1838 | u32 hotplug_mask; |
036a4a7d | 1839 | |
1ec14ad3 | 1840 | dev_priv->irq_mask = ~display_mask; |
036a4a7d ZW |
1841 | |
1842 | /* should always can generate irq */ | |
1843 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1ec14ad3 CW |
1844 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
1845 | I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK); | |
3143a2bf | 1846 | POSTING_READ(DEIER); |
036a4a7d | 1847 | |
1ec14ad3 | 1848 | dev_priv->gt_irq_mask = ~0; |
036a4a7d ZW |
1849 | |
1850 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1ec14ad3 | 1851 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
881f47b6 | 1852 | |
1ec14ad3 CW |
1853 | if (IS_GEN6(dev)) |
1854 | render_irqs = | |
1855 | GT_USER_INTERRUPT | | |
e2a1e2f0 BW |
1856 | GEN6_BSD_USER_INTERRUPT | |
1857 | GEN6_BLITTER_USER_INTERRUPT; | |
1ec14ad3 CW |
1858 | else |
1859 | render_irqs = | |
88f23b8f | 1860 | GT_USER_INTERRUPT | |
c6df541c | 1861 | GT_PIPE_NOTIFY | |
1ec14ad3 CW |
1862 | GT_BSD_USER_INTERRUPT; |
1863 | I915_WRITE(GTIER, render_irqs); | |
3143a2bf | 1864 | POSTING_READ(GTIER); |
036a4a7d | 1865 | |
2d7b8366 | 1866 | if (HAS_PCH_CPT(dev)) { |
9035a97a CW |
1867 | hotplug_mask = (SDE_CRT_HOTPLUG_CPT | |
1868 | SDE_PORTB_HOTPLUG_CPT | | |
1869 | SDE_PORTC_HOTPLUG_CPT | | |
1870 | SDE_PORTD_HOTPLUG_CPT); | |
2d7b8366 | 1871 | } else { |
9035a97a CW |
1872 | hotplug_mask = (SDE_CRT_HOTPLUG | |
1873 | SDE_PORTB_HOTPLUG | | |
1874 | SDE_PORTC_HOTPLUG | | |
1875 | SDE_PORTD_HOTPLUG | | |
1876 | SDE_AUX_MASK); | |
2d7b8366 YL |
1877 | } |
1878 | ||
1ec14ad3 | 1879 | dev_priv->pch_irq_mask = ~hotplug_mask; |
c650156a ZW |
1880 | |
1881 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | |
1ec14ad3 CW |
1882 | I915_WRITE(SDEIMR, dev_priv->pch_irq_mask); |
1883 | I915_WRITE(SDEIER, hotplug_mask); | |
3143a2bf | 1884 | POSTING_READ(SDEIER); |
c650156a | 1885 | |
7fe0b973 KP |
1886 | ironlake_enable_pch_hotplug(dev); |
1887 | ||
f97108d1 JB |
1888 | if (IS_IRONLAKE_M(dev)) { |
1889 | /* Clear & enable PCU event interrupts */ | |
1890 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
1891 | I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT); | |
1892 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); | |
1893 | } | |
1894 | ||
036a4a7d ZW |
1895 | return 0; |
1896 | } | |
1897 | ||
f71d4af4 | 1898 | static int ivybridge_irq_postinstall(struct drm_device *dev) |
b1f14ad0 JB |
1899 | { |
1900 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1901 | /* enable kind of interrupts always enabled */ | |
b615b57a CW |
1902 | u32 display_mask = |
1903 | DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB | | |
1904 | DE_PLANEC_FLIP_DONE_IVB | | |
1905 | DE_PLANEB_FLIP_DONE_IVB | | |
1906 | DE_PLANEA_FLIP_DONE_IVB; | |
b1f14ad0 JB |
1907 | u32 render_irqs; |
1908 | u32 hotplug_mask; | |
1909 | ||
b1f14ad0 JB |
1910 | dev_priv->irq_mask = ~display_mask; |
1911 | ||
1912 | /* should always can generate irq */ | |
1913 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1914 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
b615b57a CW |
1915 | I915_WRITE(DEIER, |
1916 | display_mask | | |
1917 | DE_PIPEC_VBLANK_IVB | | |
1918 | DE_PIPEB_VBLANK_IVB | | |
1919 | DE_PIPEA_VBLANK_IVB); | |
b1f14ad0 JB |
1920 | POSTING_READ(DEIER); |
1921 | ||
15b9f80e | 1922 | dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT; |
b1f14ad0 JB |
1923 | |
1924 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1925 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
1926 | ||
e2a1e2f0 | 1927 | render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT | |
15b9f80e | 1928 | GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT; |
b1f14ad0 JB |
1929 | I915_WRITE(GTIER, render_irqs); |
1930 | POSTING_READ(GTIER); | |
1931 | ||
1932 | hotplug_mask = (SDE_CRT_HOTPLUG_CPT | | |
1933 | SDE_PORTB_HOTPLUG_CPT | | |
1934 | SDE_PORTC_HOTPLUG_CPT | | |
1935 | SDE_PORTD_HOTPLUG_CPT); | |
1936 | dev_priv->pch_irq_mask = ~hotplug_mask; | |
1937 | ||
1938 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | |
1939 | I915_WRITE(SDEIMR, dev_priv->pch_irq_mask); | |
1940 | I915_WRITE(SDEIER, hotplug_mask); | |
1941 | POSTING_READ(SDEIER); | |
1942 | ||
7fe0b973 KP |
1943 | ironlake_enable_pch_hotplug(dev); |
1944 | ||
b1f14ad0 JB |
1945 | return 0; |
1946 | } | |
1947 | ||
7e231dbe JB |
1948 | static int valleyview_irq_postinstall(struct drm_device *dev) |
1949 | { | |
1950 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
7e231dbe JB |
1951 | u32 enable_mask; |
1952 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
31acc7f5 | 1953 | u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV; |
7e231dbe JB |
1954 | u16 msid; |
1955 | ||
1956 | enable_mask = I915_DISPLAY_PORT_INTERRUPT; | |
31acc7f5 JB |
1957 | enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
1958 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | | |
1959 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
7e231dbe JB |
1960 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
1961 | ||
31acc7f5 JB |
1962 | /* |
1963 | *Leave vblank interrupts masked initially. enable/disable will | |
1964 | * toggle them based on usage. | |
1965 | */ | |
1966 | dev_priv->irq_mask = (~enable_mask) | | |
1967 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | | |
1968 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; | |
7e231dbe | 1969 | |
7e231dbe JB |
1970 | dev_priv->pipestat[0] = 0; |
1971 | dev_priv->pipestat[1] = 0; | |
1972 | ||
7e231dbe JB |
1973 | /* Hack for broken MSIs on VLV */ |
1974 | pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000); | |
1975 | pci_read_config_word(dev->pdev, 0x98, &msid); | |
1976 | msid &= 0xff; /* mask out delivery bits */ | |
1977 | msid |= (1<<14); | |
1978 | pci_write_config_word(dev_priv->dev->pdev, 0x98, msid); | |
1979 | ||
1980 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); | |
1981 | I915_WRITE(VLV_IER, enable_mask); | |
1982 | I915_WRITE(VLV_IIR, 0xffffffff); | |
1983 | I915_WRITE(PIPESTAT(0), 0xffff); | |
1984 | I915_WRITE(PIPESTAT(1), 0xffff); | |
1985 | POSTING_READ(VLV_IER); | |
1986 | ||
31acc7f5 JB |
1987 | i915_enable_pipestat(dev_priv, 0, pipestat_enable); |
1988 | i915_enable_pipestat(dev_priv, 1, pipestat_enable); | |
1989 | ||
7e231dbe JB |
1990 | I915_WRITE(VLV_IIR, 0xffffffff); |
1991 | I915_WRITE(VLV_IIR, 0xffffffff); | |
1992 | ||
31acc7f5 | 1993 | dev_priv->gt_irq_mask = ~0; |
7e231dbe JB |
1994 | |
1995 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1996 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
31acc7f5 JB |
1997 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
1998 | I915_WRITE(GTIER, GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT | | |
1999 | GT_GEN6_BLT_CS_ERROR_INTERRUPT | | |
2000 | GT_GEN6_BLT_USER_INTERRUPT | | |
2001 | GT_GEN6_BSD_USER_INTERRUPT | | |
2002 | GT_GEN6_BSD_CS_ERROR_INTERRUPT | | |
2003 | GT_GEN7_L3_PARITY_ERROR_INTERRUPT | | |
2004 | GT_PIPE_NOTIFY | | |
2005 | GT_RENDER_CS_ERROR_INTERRUPT | | |
2006 | GT_SYNC_STATUS | | |
2007 | GT_USER_INTERRUPT); | |
7e231dbe JB |
2008 | POSTING_READ(GTIER); |
2009 | ||
2010 | /* ack & enable invalid PTE error interrupts */ | |
2011 | #if 0 /* FIXME: add support to irq handler for checking these bits */ | |
2012 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); | |
2013 | I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); | |
2014 | #endif | |
2015 | ||
2016 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); | |
2017 | #if 0 /* FIXME: check register definitions; some have moved */ | |
2018 | /* Note HDMI and DP share bits */ | |
2019 | if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) | |
2020 | hotplug_en |= HDMIB_HOTPLUG_INT_EN; | |
2021 | if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) | |
2022 | hotplug_en |= HDMIC_HOTPLUG_INT_EN; | |
2023 | if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) | |
2024 | hotplug_en |= HDMID_HOTPLUG_INT_EN; | |
2025 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS) | |
2026 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; | |
2027 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS) | |
2028 | hotplug_en |= SDVOB_HOTPLUG_INT_EN; | |
2029 | if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { | |
2030 | hotplug_en |= CRT_HOTPLUG_INT_EN; | |
2031 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; | |
2032 | } | |
2033 | #endif | |
2034 | ||
2035 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
2036 | ||
2037 | return 0; | |
2038 | } | |
2039 | ||
7e231dbe JB |
2040 | static void valleyview_irq_uninstall(struct drm_device *dev) |
2041 | { | |
2042 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2043 | int pipe; | |
2044 | ||
2045 | if (!dev_priv) | |
2046 | return; | |
2047 | ||
7e231dbe JB |
2048 | for_each_pipe(pipe) |
2049 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
2050 | ||
2051 | I915_WRITE(HWSTAM, 0xffffffff); | |
2052 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
2053 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
2054 | for_each_pipe(pipe) | |
2055 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
2056 | I915_WRITE(VLV_IIR, 0xffffffff); | |
2057 | I915_WRITE(VLV_IMR, 0xffffffff); | |
2058 | I915_WRITE(VLV_IER, 0x0); | |
2059 | POSTING_READ(VLV_IER); | |
2060 | } | |
2061 | ||
f71d4af4 | 2062 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d ZW |
2063 | { |
2064 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
4697995b JB |
2065 | |
2066 | if (!dev_priv) | |
2067 | return; | |
2068 | ||
036a4a7d ZW |
2069 | I915_WRITE(HWSTAM, 0xffffffff); |
2070 | ||
2071 | I915_WRITE(DEIMR, 0xffffffff); | |
2072 | I915_WRITE(DEIER, 0x0); | |
2073 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
2074 | ||
2075 | I915_WRITE(GTIMR, 0xffffffff); | |
2076 | I915_WRITE(GTIER, 0x0); | |
2077 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
192aac1f KP |
2078 | |
2079 | I915_WRITE(SDEIMR, 0xffffffff); | |
2080 | I915_WRITE(SDEIER, 0x0); | |
2081 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | |
036a4a7d ZW |
2082 | } |
2083 | ||
a266c7d5 | 2084 | static void i8xx_irq_preinstall(struct drm_device * dev) |
1da177e4 LT |
2085 | { |
2086 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 2087 | int pipe; |
91e3738e | 2088 | |
a266c7d5 | 2089 | atomic_set(&dev_priv->irq_received, 0); |
5ca58282 | 2090 | |
9db4a9c7 JB |
2091 | for_each_pipe(pipe) |
2092 | I915_WRITE(PIPESTAT(pipe), 0); | |
a266c7d5 CW |
2093 | I915_WRITE16(IMR, 0xffff); |
2094 | I915_WRITE16(IER, 0x0); | |
2095 | POSTING_READ16(IER); | |
c2798b19 CW |
2096 | } |
2097 | ||
2098 | static int i8xx_irq_postinstall(struct drm_device *dev) | |
2099 | { | |
2100 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2101 | ||
c2798b19 CW |
2102 | dev_priv->pipestat[0] = 0; |
2103 | dev_priv->pipestat[1] = 0; | |
2104 | ||
2105 | I915_WRITE16(EMR, | |
2106 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); | |
2107 | ||
2108 | /* Unmask the interrupts that we always want on. */ | |
2109 | dev_priv->irq_mask = | |
2110 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
2111 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
2112 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
2113 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
2114 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2115 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
2116 | ||
2117 | I915_WRITE16(IER, | |
2118 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
2119 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
2120 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
2121 | I915_USER_INTERRUPT); | |
2122 | POSTING_READ16(IER); | |
2123 | ||
2124 | return 0; | |
2125 | } | |
2126 | ||
2127 | static irqreturn_t i8xx_irq_handler(DRM_IRQ_ARGS) | |
2128 | { | |
2129 | struct drm_device *dev = (struct drm_device *) arg; | |
2130 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
c2798b19 CW |
2131 | u16 iir, new_iir; |
2132 | u32 pipe_stats[2]; | |
2133 | unsigned long irqflags; | |
2134 | int irq_received; | |
2135 | int pipe; | |
2136 | u16 flip_mask = | |
2137 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
2138 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
2139 | ||
2140 | atomic_inc(&dev_priv->irq_received); | |
2141 | ||
2142 | iir = I915_READ16(IIR); | |
2143 | if (iir == 0) | |
2144 | return IRQ_NONE; | |
2145 | ||
2146 | while (iir & ~flip_mask) { | |
2147 | /* Can't rely on pipestat interrupt bit in iir as it might | |
2148 | * have been cleared after the pipestat interrupt was received. | |
2149 | * It doesn't set the bit in iir again, but it still produces | |
2150 | * interrupts (for non-MSI). | |
2151 | */ | |
2152 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
2153 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
2154 | i915_handle_error(dev, false); | |
2155 | ||
2156 | for_each_pipe(pipe) { | |
2157 | int reg = PIPESTAT(pipe); | |
2158 | pipe_stats[pipe] = I915_READ(reg); | |
2159 | ||
2160 | /* | |
2161 | * Clear the PIPE*STAT regs before the IIR | |
2162 | */ | |
2163 | if (pipe_stats[pipe] & 0x8000ffff) { | |
2164 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | |
2165 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | |
2166 | pipe_name(pipe)); | |
2167 | I915_WRITE(reg, pipe_stats[pipe]); | |
2168 | irq_received = 1; | |
2169 | } | |
2170 | } | |
2171 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
2172 | ||
2173 | I915_WRITE16(IIR, iir & ~flip_mask); | |
2174 | new_iir = I915_READ16(IIR); /* Flush posted writes */ | |
2175 | ||
d05c617e | 2176 | i915_update_dri1_breadcrumb(dev); |
c2798b19 CW |
2177 | |
2178 | if (iir & I915_USER_INTERRUPT) | |
2179 | notify_ring(dev, &dev_priv->ring[RCS]); | |
2180 | ||
2181 | if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS && | |
2182 | drm_handle_vblank(dev, 0)) { | |
2183 | if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) { | |
2184 | intel_prepare_page_flip(dev, 0); | |
2185 | intel_finish_page_flip(dev, 0); | |
2186 | flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT; | |
2187 | } | |
2188 | } | |
2189 | ||
2190 | if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS && | |
2191 | drm_handle_vblank(dev, 1)) { | |
2192 | if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) { | |
2193 | intel_prepare_page_flip(dev, 1); | |
2194 | intel_finish_page_flip(dev, 1); | |
2195 | flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
2196 | } | |
2197 | } | |
2198 | ||
2199 | iir = new_iir; | |
2200 | } | |
2201 | ||
2202 | return IRQ_HANDLED; | |
2203 | } | |
2204 | ||
2205 | static void i8xx_irq_uninstall(struct drm_device * dev) | |
2206 | { | |
2207 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2208 | int pipe; | |
2209 | ||
c2798b19 CW |
2210 | for_each_pipe(pipe) { |
2211 | /* Clear enable bits; then clear status bits */ | |
2212 | I915_WRITE(PIPESTAT(pipe), 0); | |
2213 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); | |
2214 | } | |
2215 | I915_WRITE16(IMR, 0xffff); | |
2216 | I915_WRITE16(IER, 0x0); | |
2217 | I915_WRITE16(IIR, I915_READ16(IIR)); | |
2218 | } | |
2219 | ||
a266c7d5 CW |
2220 | static void i915_irq_preinstall(struct drm_device * dev) |
2221 | { | |
2222 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2223 | int pipe; | |
2224 | ||
2225 | atomic_set(&dev_priv->irq_received, 0); | |
2226 | ||
2227 | if (I915_HAS_HOTPLUG(dev)) { | |
2228 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
2229 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
2230 | } | |
2231 | ||
00d98ebd | 2232 | I915_WRITE16(HWSTAM, 0xeffe); |
a266c7d5 CW |
2233 | for_each_pipe(pipe) |
2234 | I915_WRITE(PIPESTAT(pipe), 0); | |
2235 | I915_WRITE(IMR, 0xffffffff); | |
2236 | I915_WRITE(IER, 0x0); | |
2237 | POSTING_READ(IER); | |
2238 | } | |
2239 | ||
2240 | static int i915_irq_postinstall(struct drm_device *dev) | |
2241 | { | |
2242 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
38bde180 | 2243 | u32 enable_mask; |
a266c7d5 | 2244 | |
a266c7d5 CW |
2245 | dev_priv->pipestat[0] = 0; |
2246 | dev_priv->pipestat[1] = 0; | |
2247 | ||
38bde180 CW |
2248 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
2249 | ||
2250 | /* Unmask the interrupts that we always want on. */ | |
2251 | dev_priv->irq_mask = | |
2252 | ~(I915_ASLE_INTERRUPT | | |
2253 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
2254 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
2255 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
2256 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
2257 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2258 | ||
2259 | enable_mask = | |
2260 | I915_ASLE_INTERRUPT | | |
2261 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
2262 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
2263 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
2264 | I915_USER_INTERRUPT; | |
2265 | ||
a266c7d5 CW |
2266 | if (I915_HAS_HOTPLUG(dev)) { |
2267 | /* Enable in IER... */ | |
2268 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
2269 | /* and unmask in IMR */ | |
2270 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; | |
2271 | } | |
2272 | ||
a266c7d5 CW |
2273 | I915_WRITE(IMR, dev_priv->irq_mask); |
2274 | I915_WRITE(IER, enable_mask); | |
2275 | POSTING_READ(IER); | |
2276 | ||
2277 | if (I915_HAS_HOTPLUG(dev)) { | |
2278 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
2279 | ||
a266c7d5 CW |
2280 | if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) |
2281 | hotplug_en |= HDMIB_HOTPLUG_INT_EN; | |
2282 | if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) | |
2283 | hotplug_en |= HDMIC_HOTPLUG_INT_EN; | |
2284 | if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) | |
2285 | hotplug_en |= HDMID_HOTPLUG_INT_EN; | |
084b612e | 2286 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915) |
a266c7d5 | 2287 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; |
084b612e | 2288 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915) |
a266c7d5 CW |
2289 | hotplug_en |= SDVOB_HOTPLUG_INT_EN; |
2290 | if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { | |
2291 | hotplug_en |= CRT_HOTPLUG_INT_EN; | |
a266c7d5 CW |
2292 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
2293 | } | |
2294 | ||
2295 | /* Ignore TV since it's buggy */ | |
2296 | ||
2297 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
2298 | } | |
2299 | ||
2300 | intel_opregion_enable_asle(dev); | |
2301 | ||
2302 | return 0; | |
2303 | } | |
2304 | ||
2305 | static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS) | |
2306 | { | |
2307 | struct drm_device *dev = (struct drm_device *) arg; | |
2308 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
8291ee90 | 2309 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
a266c7d5 | 2310 | unsigned long irqflags; |
38bde180 CW |
2311 | u32 flip_mask = |
2312 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
2313 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
2314 | u32 flip[2] = { | |
2315 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT, | |
2316 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | |
2317 | }; | |
2318 | int pipe, ret = IRQ_NONE; | |
a266c7d5 CW |
2319 | |
2320 | atomic_inc(&dev_priv->irq_received); | |
2321 | ||
2322 | iir = I915_READ(IIR); | |
38bde180 CW |
2323 | do { |
2324 | bool irq_received = (iir & ~flip_mask) != 0; | |
8291ee90 | 2325 | bool blc_event = false; |
a266c7d5 CW |
2326 | |
2327 | /* Can't rely on pipestat interrupt bit in iir as it might | |
2328 | * have been cleared after the pipestat interrupt was received. | |
2329 | * It doesn't set the bit in iir again, but it still produces | |
2330 | * interrupts (for non-MSI). | |
2331 | */ | |
2332 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
2333 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
2334 | i915_handle_error(dev, false); | |
2335 | ||
2336 | for_each_pipe(pipe) { | |
2337 | int reg = PIPESTAT(pipe); | |
2338 | pipe_stats[pipe] = I915_READ(reg); | |
2339 | ||
38bde180 | 2340 | /* Clear the PIPE*STAT regs before the IIR */ |
a266c7d5 CW |
2341 | if (pipe_stats[pipe] & 0x8000ffff) { |
2342 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | |
2343 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | |
2344 | pipe_name(pipe)); | |
2345 | I915_WRITE(reg, pipe_stats[pipe]); | |
38bde180 | 2346 | irq_received = true; |
a266c7d5 CW |
2347 | } |
2348 | } | |
2349 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
2350 | ||
2351 | if (!irq_received) | |
2352 | break; | |
2353 | ||
a266c7d5 CW |
2354 | /* Consume port. Then clear IIR or we'll miss events */ |
2355 | if ((I915_HAS_HOTPLUG(dev)) && | |
2356 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { | |
2357 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
2358 | ||
2359 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", | |
2360 | hotplug_status); | |
2361 | if (hotplug_status & dev_priv->hotplug_supported_mask) | |
2362 | queue_work(dev_priv->wq, | |
2363 | &dev_priv->hotplug_work); | |
2364 | ||
2365 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
38bde180 | 2366 | POSTING_READ(PORT_HOTPLUG_STAT); |
a266c7d5 CW |
2367 | } |
2368 | ||
38bde180 | 2369 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
2370 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
2371 | ||
a266c7d5 CW |
2372 | if (iir & I915_USER_INTERRUPT) |
2373 | notify_ring(dev, &dev_priv->ring[RCS]); | |
a266c7d5 | 2374 | |
a266c7d5 | 2375 | for_each_pipe(pipe) { |
38bde180 CW |
2376 | int plane = pipe; |
2377 | if (IS_MOBILE(dev)) | |
2378 | plane = !plane; | |
8291ee90 | 2379 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
a266c7d5 | 2380 | drm_handle_vblank(dev, pipe)) { |
38bde180 CW |
2381 | if (iir & flip[plane]) { |
2382 | intel_prepare_page_flip(dev, plane); | |
2383 | intel_finish_page_flip(dev, pipe); | |
2384 | flip_mask &= ~flip[plane]; | |
2385 | } | |
a266c7d5 CW |
2386 | } |
2387 | ||
2388 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
2389 | blc_event = true; | |
2390 | } | |
2391 | ||
a266c7d5 CW |
2392 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
2393 | intel_opregion_asle_intr(dev); | |
2394 | ||
2395 | /* With MSI, interrupts are only generated when iir | |
2396 | * transitions from zero to nonzero. If another bit got | |
2397 | * set while we were handling the existing iir bits, then | |
2398 | * we would never get another interrupt. | |
2399 | * | |
2400 | * This is fine on non-MSI as well, as if we hit this path | |
2401 | * we avoid exiting the interrupt handler only to generate | |
2402 | * another one. | |
2403 | * | |
2404 | * Note that for MSI this could cause a stray interrupt report | |
2405 | * if an interrupt landed in the time between writing IIR and | |
2406 | * the posting read. This should be rare enough to never | |
2407 | * trigger the 99% of 100,000 interrupts test for disabling | |
2408 | * stray interrupts. | |
2409 | */ | |
38bde180 | 2410 | ret = IRQ_HANDLED; |
a266c7d5 | 2411 | iir = new_iir; |
38bde180 | 2412 | } while (iir & ~flip_mask); |
a266c7d5 | 2413 | |
d05c617e | 2414 | i915_update_dri1_breadcrumb(dev); |
8291ee90 | 2415 | |
a266c7d5 CW |
2416 | return ret; |
2417 | } | |
2418 | ||
2419 | static void i915_irq_uninstall(struct drm_device * dev) | |
2420 | { | |
2421 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2422 | int pipe; | |
2423 | ||
a266c7d5 CW |
2424 | if (I915_HAS_HOTPLUG(dev)) { |
2425 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
2426 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
2427 | } | |
2428 | ||
00d98ebd | 2429 | I915_WRITE16(HWSTAM, 0xffff); |
55b39755 CW |
2430 | for_each_pipe(pipe) { |
2431 | /* Clear enable bits; then clear status bits */ | |
a266c7d5 | 2432 | I915_WRITE(PIPESTAT(pipe), 0); |
55b39755 CW |
2433 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
2434 | } | |
a266c7d5 CW |
2435 | I915_WRITE(IMR, 0xffffffff); |
2436 | I915_WRITE(IER, 0x0); | |
2437 | ||
a266c7d5 CW |
2438 | I915_WRITE(IIR, I915_READ(IIR)); |
2439 | } | |
2440 | ||
2441 | static void i965_irq_preinstall(struct drm_device * dev) | |
2442 | { | |
2443 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2444 | int pipe; | |
2445 | ||
2446 | atomic_set(&dev_priv->irq_received, 0); | |
2447 | ||
adca4730 CW |
2448 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
2449 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
2450 | |
2451 | I915_WRITE(HWSTAM, 0xeffe); | |
2452 | for_each_pipe(pipe) | |
2453 | I915_WRITE(PIPESTAT(pipe), 0); | |
2454 | I915_WRITE(IMR, 0xffffffff); | |
2455 | I915_WRITE(IER, 0x0); | |
2456 | POSTING_READ(IER); | |
2457 | } | |
2458 | ||
2459 | static int i965_irq_postinstall(struct drm_device *dev) | |
2460 | { | |
2461 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
adca4730 | 2462 | u32 hotplug_en; |
bbba0a97 | 2463 | u32 enable_mask; |
a266c7d5 CW |
2464 | u32 error_mask; |
2465 | ||
a266c7d5 | 2466 | /* Unmask the interrupts that we always want on. */ |
bbba0a97 | 2467 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
adca4730 | 2468 | I915_DISPLAY_PORT_INTERRUPT | |
bbba0a97 CW |
2469 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
2470 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
2471 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
2472 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
2473 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2474 | ||
2475 | enable_mask = ~dev_priv->irq_mask; | |
2476 | enable_mask |= I915_USER_INTERRUPT; | |
2477 | ||
2478 | if (IS_G4X(dev)) | |
2479 | enable_mask |= I915_BSD_USER_INTERRUPT; | |
a266c7d5 CW |
2480 | |
2481 | dev_priv->pipestat[0] = 0; | |
2482 | dev_priv->pipestat[1] = 0; | |
2483 | ||
a266c7d5 CW |
2484 | /* |
2485 | * Enable some error detection, note the instruction error mask | |
2486 | * bit is reserved, so we leave it masked. | |
2487 | */ | |
2488 | if (IS_G4X(dev)) { | |
2489 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
2490 | GM45_ERROR_MEM_PRIV | | |
2491 | GM45_ERROR_CP_PRIV | | |
2492 | I915_ERROR_MEMORY_REFRESH); | |
2493 | } else { | |
2494 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
2495 | I915_ERROR_MEMORY_REFRESH); | |
2496 | } | |
2497 | I915_WRITE(EMR, error_mask); | |
2498 | ||
2499 | I915_WRITE(IMR, dev_priv->irq_mask); | |
2500 | I915_WRITE(IER, enable_mask); | |
2501 | POSTING_READ(IER); | |
2502 | ||
adca4730 CW |
2503 | /* Note HDMI and DP share hotplug bits */ |
2504 | hotplug_en = 0; | |
2505 | if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) | |
2506 | hotplug_en |= HDMIB_HOTPLUG_INT_EN; | |
2507 | if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) | |
2508 | hotplug_en |= HDMIC_HOTPLUG_INT_EN; | |
2509 | if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) | |
2510 | hotplug_en |= HDMID_HOTPLUG_INT_EN; | |
084b612e CW |
2511 | if (IS_G4X(dev)) { |
2512 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X) | |
2513 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; | |
2514 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X) | |
2515 | hotplug_en |= SDVOB_HOTPLUG_INT_EN; | |
2516 | } else { | |
2517 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965) | |
2518 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; | |
2519 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965) | |
2520 | hotplug_en |= SDVOB_HOTPLUG_INT_EN; | |
2521 | } | |
adca4730 CW |
2522 | if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { |
2523 | hotplug_en |= CRT_HOTPLUG_INT_EN; | |
a266c7d5 | 2524 | |
adca4730 CW |
2525 | /* Programming the CRT detection parameters tends |
2526 | to generate a spurious hotplug event about three | |
2527 | seconds later. So just do it once. | |
2528 | */ | |
2529 | if (IS_G4X(dev)) | |
2530 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
2531 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; | |
2532 | } | |
a266c7d5 | 2533 | |
adca4730 | 2534 | /* Ignore TV since it's buggy */ |
a266c7d5 | 2535 | |
adca4730 | 2536 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); |
a266c7d5 CW |
2537 | |
2538 | intel_opregion_enable_asle(dev); | |
2539 | ||
2540 | return 0; | |
2541 | } | |
2542 | ||
2543 | static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS) | |
2544 | { | |
2545 | struct drm_device *dev = (struct drm_device *) arg; | |
2546 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
a266c7d5 CW |
2547 | u32 iir, new_iir; |
2548 | u32 pipe_stats[I915_MAX_PIPES]; | |
a266c7d5 CW |
2549 | unsigned long irqflags; |
2550 | int irq_received; | |
2551 | int ret = IRQ_NONE, pipe; | |
a266c7d5 CW |
2552 | |
2553 | atomic_inc(&dev_priv->irq_received); | |
2554 | ||
2555 | iir = I915_READ(IIR); | |
2556 | ||
a266c7d5 | 2557 | for (;;) { |
2c8ba29f CW |
2558 | bool blc_event = false; |
2559 | ||
a266c7d5 CW |
2560 | irq_received = iir != 0; |
2561 | ||
2562 | /* Can't rely on pipestat interrupt bit in iir as it might | |
2563 | * have been cleared after the pipestat interrupt was received. | |
2564 | * It doesn't set the bit in iir again, but it still produces | |
2565 | * interrupts (for non-MSI). | |
2566 | */ | |
2567 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
2568 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
2569 | i915_handle_error(dev, false); | |
2570 | ||
2571 | for_each_pipe(pipe) { | |
2572 | int reg = PIPESTAT(pipe); | |
2573 | pipe_stats[pipe] = I915_READ(reg); | |
2574 | ||
2575 | /* | |
2576 | * Clear the PIPE*STAT regs before the IIR | |
2577 | */ | |
2578 | if (pipe_stats[pipe] & 0x8000ffff) { | |
2579 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | |
2580 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | |
2581 | pipe_name(pipe)); | |
2582 | I915_WRITE(reg, pipe_stats[pipe]); | |
2583 | irq_received = 1; | |
2584 | } | |
2585 | } | |
2586 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
2587 | ||
2588 | if (!irq_received) | |
2589 | break; | |
2590 | ||
2591 | ret = IRQ_HANDLED; | |
2592 | ||
2593 | /* Consume port. Then clear IIR or we'll miss events */ | |
adca4730 | 2594 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { |
a266c7d5 CW |
2595 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
2596 | ||
2597 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", | |
2598 | hotplug_status); | |
2599 | if (hotplug_status & dev_priv->hotplug_supported_mask) | |
2600 | queue_work(dev_priv->wq, | |
2601 | &dev_priv->hotplug_work); | |
2602 | ||
2603 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
2604 | I915_READ(PORT_HOTPLUG_STAT); | |
2605 | } | |
2606 | ||
2607 | I915_WRITE(IIR, iir); | |
2608 | new_iir = I915_READ(IIR); /* Flush posted writes */ | |
2609 | ||
a266c7d5 CW |
2610 | if (iir & I915_USER_INTERRUPT) |
2611 | notify_ring(dev, &dev_priv->ring[RCS]); | |
2612 | if (iir & I915_BSD_USER_INTERRUPT) | |
2613 | notify_ring(dev, &dev_priv->ring[VCS]); | |
2614 | ||
4f7d1e79 | 2615 | if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) |
a266c7d5 | 2616 | intel_prepare_page_flip(dev, 0); |
a266c7d5 | 2617 | |
4f7d1e79 | 2618 | if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) |
a266c7d5 | 2619 | intel_prepare_page_flip(dev, 1); |
a266c7d5 CW |
2620 | |
2621 | for_each_pipe(pipe) { | |
2c8ba29f | 2622 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
a266c7d5 | 2623 | drm_handle_vblank(dev, pipe)) { |
4f7d1e79 CW |
2624 | i915_pageflip_stall_check(dev, pipe); |
2625 | intel_finish_page_flip(dev, pipe); | |
a266c7d5 CW |
2626 | } |
2627 | ||
2628 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
2629 | blc_event = true; | |
2630 | } | |
2631 | ||
2632 | ||
2633 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | |
2634 | intel_opregion_asle_intr(dev); | |
2635 | ||
2636 | /* With MSI, interrupts are only generated when iir | |
2637 | * transitions from zero to nonzero. If another bit got | |
2638 | * set while we were handling the existing iir bits, then | |
2639 | * we would never get another interrupt. | |
2640 | * | |
2641 | * This is fine on non-MSI as well, as if we hit this path | |
2642 | * we avoid exiting the interrupt handler only to generate | |
2643 | * another one. | |
2644 | * | |
2645 | * Note that for MSI this could cause a stray interrupt report | |
2646 | * if an interrupt landed in the time between writing IIR and | |
2647 | * the posting read. This should be rare enough to never | |
2648 | * trigger the 99% of 100,000 interrupts test for disabling | |
2649 | * stray interrupts. | |
2650 | */ | |
2651 | iir = new_iir; | |
2652 | } | |
2653 | ||
d05c617e | 2654 | i915_update_dri1_breadcrumb(dev); |
2c8ba29f | 2655 | |
a266c7d5 CW |
2656 | return ret; |
2657 | } | |
2658 | ||
2659 | static void i965_irq_uninstall(struct drm_device * dev) | |
2660 | { | |
2661 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2662 | int pipe; | |
2663 | ||
2664 | if (!dev_priv) | |
2665 | return; | |
2666 | ||
adca4730 CW |
2667 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
2668 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
2669 | |
2670 | I915_WRITE(HWSTAM, 0xffffffff); | |
2671 | for_each_pipe(pipe) | |
2672 | I915_WRITE(PIPESTAT(pipe), 0); | |
2673 | I915_WRITE(IMR, 0xffffffff); | |
2674 | I915_WRITE(IER, 0x0); | |
2675 | ||
2676 | for_each_pipe(pipe) | |
2677 | I915_WRITE(PIPESTAT(pipe), | |
2678 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); | |
2679 | I915_WRITE(IIR, I915_READ(IIR)); | |
2680 | } | |
2681 | ||
f71d4af4 JB |
2682 | void intel_irq_init(struct drm_device *dev) |
2683 | { | |
8b2e326d CW |
2684 | struct drm_i915_private *dev_priv = dev->dev_private; |
2685 | ||
2686 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); | |
2687 | INIT_WORK(&dev_priv->error_work, i915_error_work_func); | |
c6a828d3 | 2688 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
98fd81cd | 2689 | INIT_WORK(&dev_priv->parity_error_work, ivybridge_parity_work); |
8b2e326d | 2690 | |
f71d4af4 JB |
2691 | dev->driver->get_vblank_counter = i915_get_vblank_counter; |
2692 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
7d4e146f | 2693 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
f71d4af4 JB |
2694 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
2695 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; | |
2696 | } | |
2697 | ||
c3613de9 KP |
2698 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
2699 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; | |
2700 | else | |
2701 | dev->driver->get_vblank_timestamp = NULL; | |
f71d4af4 JB |
2702 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; |
2703 | ||
7e231dbe JB |
2704 | if (IS_VALLEYVIEW(dev)) { |
2705 | dev->driver->irq_handler = valleyview_irq_handler; | |
2706 | dev->driver->irq_preinstall = valleyview_irq_preinstall; | |
2707 | dev->driver->irq_postinstall = valleyview_irq_postinstall; | |
2708 | dev->driver->irq_uninstall = valleyview_irq_uninstall; | |
2709 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
2710 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
2711 | } else if (IS_IVYBRIDGE(dev)) { | |
f71d4af4 JB |
2712 | /* Share pre & uninstall handlers with ILK/SNB */ |
2713 | dev->driver->irq_handler = ivybridge_irq_handler; | |
2714 | dev->driver->irq_preinstall = ironlake_irq_preinstall; | |
2715 | dev->driver->irq_postinstall = ivybridge_irq_postinstall; | |
2716 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
2717 | dev->driver->enable_vblank = ivybridge_enable_vblank; | |
2718 | dev->driver->disable_vblank = ivybridge_disable_vblank; | |
7d4e146f ED |
2719 | } else if (IS_HASWELL(dev)) { |
2720 | /* Share interrupts handling with IVB */ | |
2721 | dev->driver->irq_handler = ivybridge_irq_handler; | |
2722 | dev->driver->irq_preinstall = ironlake_irq_preinstall; | |
2723 | dev->driver->irq_postinstall = ivybridge_irq_postinstall; | |
2724 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
2725 | dev->driver->enable_vblank = ivybridge_enable_vblank; | |
2726 | dev->driver->disable_vblank = ivybridge_disable_vblank; | |
f71d4af4 JB |
2727 | } else if (HAS_PCH_SPLIT(dev)) { |
2728 | dev->driver->irq_handler = ironlake_irq_handler; | |
2729 | dev->driver->irq_preinstall = ironlake_irq_preinstall; | |
2730 | dev->driver->irq_postinstall = ironlake_irq_postinstall; | |
2731 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
2732 | dev->driver->enable_vblank = ironlake_enable_vblank; | |
2733 | dev->driver->disable_vblank = ironlake_disable_vblank; | |
2734 | } else { | |
c2798b19 CW |
2735 | if (INTEL_INFO(dev)->gen == 2) { |
2736 | dev->driver->irq_preinstall = i8xx_irq_preinstall; | |
2737 | dev->driver->irq_postinstall = i8xx_irq_postinstall; | |
2738 | dev->driver->irq_handler = i8xx_irq_handler; | |
2739 | dev->driver->irq_uninstall = i8xx_irq_uninstall; | |
a266c7d5 | 2740 | } else if (INTEL_INFO(dev)->gen == 3) { |
4f7d1e79 CW |
2741 | /* IIR "flip pending" means done if this bit is set */ |
2742 | I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); | |
2743 | ||
a266c7d5 CW |
2744 | dev->driver->irq_preinstall = i915_irq_preinstall; |
2745 | dev->driver->irq_postinstall = i915_irq_postinstall; | |
2746 | dev->driver->irq_uninstall = i915_irq_uninstall; | |
2747 | dev->driver->irq_handler = i915_irq_handler; | |
c2798b19 | 2748 | } else { |
a266c7d5 CW |
2749 | dev->driver->irq_preinstall = i965_irq_preinstall; |
2750 | dev->driver->irq_postinstall = i965_irq_postinstall; | |
2751 | dev->driver->irq_uninstall = i965_irq_uninstall; | |
2752 | dev->driver->irq_handler = i965_irq_handler; | |
c2798b19 | 2753 | } |
f71d4af4 JB |
2754 | dev->driver->enable_vblank = i915_enable_vblank; |
2755 | dev->driver->disable_vblank = i915_disable_vblank; | |
2756 | } | |
2757 | } |