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drm/i915: fix CRC debugfs setup
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / i915 / i915_irq.c
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0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
b2c88f5b 33#include <linux/circ_buf.h>
760285e7
DH		 34#include <drm/drmP.h>
35#include <drm/i915_drm.h>
1da177e4 36#include "i915_drv.h"
1c5d22f7 37#include "i915_trace.h"
79e53945 38#include "intel_drv.h"
1da177e4 39
e5868a31
EE		 40static const u32 hpd_ibx[] = {
41 [HPD_CRT] = SDE_CRT_HOTPLUG,
42 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
43 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
44 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
45 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
46};
47
48static const u32 hpd_cpt[] = {
49 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
73c352a2 50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
e5868a31
EE		 51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
54};
55
56static const u32 hpd_mask_i915[] = {
57 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
58 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
59 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
60 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
61 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
62 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
63};
64
65static const u32 hpd_status_gen4[] = {
66 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
67 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
68 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
69 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
70 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
71 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
72};
73
e5868a31
EE		 74static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
75 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
76 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
77 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
78 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
79 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
80 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
81};
82
036a4a7d 83/* For display hotplug interrupt */
995b6762 84static void
f2b115e6 85ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 86{
4bc9d430
DV		 87 assert_spin_locked(&dev_priv->irq_lock);
88
c67a470b
PZ		 89 if (dev_priv->pc8.irqs_disabled) {
90 WARN(1, "IRQs disabled\n");
91 dev_priv->pc8.regsave.deimr &= ~mask;
92 return;
93 }
94
1ec14ad3
CW		 95 if ((dev_priv->irq_mask & mask) != 0) {
96 dev_priv->irq_mask &= ~mask;
97 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 98 POSTING_READ(DEIMR);
036a4a7d
ZW		 99 }
100}
101
0ff9800a 102static void
f2b115e6 103ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 104{
4bc9d430
DV		 105 assert_spin_locked(&dev_priv->irq_lock);
106
c67a470b
PZ		 107 if (dev_priv->pc8.irqs_disabled) {
108 WARN(1, "IRQs disabled\n");
109 dev_priv->pc8.regsave.deimr |= mask;
110 return;
111 }
112
1ec14ad3
CW		 113 if ((dev_priv->irq_mask & mask) != mask) {
114 dev_priv->irq_mask |= mask;
115 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 116 POSTING_READ(DEIMR);
036a4a7d
ZW		 117 }
118}
119
43eaea13
PZ		 120/**
121 * ilk_update_gt_irq - update GTIMR
122 * @dev_priv: driver private
123 * @interrupt_mask: mask of interrupt bits to update
124 * @enabled_irq_mask: mask of interrupt bits to enable
125 */
126static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
127 uint32_t interrupt_mask,
128 uint32_t enabled_irq_mask)
129{
130 assert_spin_locked(&dev_priv->irq_lock);
131
c67a470b
PZ		 132 if (dev_priv->pc8.irqs_disabled) {
133 WARN(1, "IRQs disabled\n");
134 dev_priv->pc8.regsave.gtimr &= ~interrupt_mask;
135 dev_priv->pc8.regsave.gtimr |= (~enabled_irq_mask &
136 interrupt_mask);
137 return;
138 }
139
43eaea13
PZ		 140 dev_priv->gt_irq_mask &= ~interrupt_mask;
141 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
142 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
143 POSTING_READ(GTIMR);
144}
145
146void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
147{
148 ilk_update_gt_irq(dev_priv, mask, mask);
149}
150
151void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
152{
153 ilk_update_gt_irq(dev_priv, mask, 0);
154}
155
edbfdb45
PZ		 156/**
157 * snb_update_pm_irq - update GEN6_PMIMR
158 * @dev_priv: driver private
159 * @interrupt_mask: mask of interrupt bits to update
160 * @enabled_irq_mask: mask of interrupt bits to enable
161 */
162static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
163 uint32_t interrupt_mask,
164 uint32_t enabled_irq_mask)
165{
605cd25b 166 uint32_t new_val;
edbfdb45
PZ		 167
168 assert_spin_locked(&dev_priv->irq_lock);
169
c67a470b
PZ		 170 if (dev_priv->pc8.irqs_disabled) {
171 WARN(1, "IRQs disabled\n");
172 dev_priv->pc8.regsave.gen6_pmimr &= ~interrupt_mask;
173 dev_priv->pc8.regsave.gen6_pmimr |= (~enabled_irq_mask &
174 interrupt_mask);
175 return;
176 }
177
605cd25b 178 new_val = dev_priv->pm_irq_mask;
f52ecbcf
PZ		 179 new_val &= ~interrupt_mask;
180 new_val |= (~enabled_irq_mask & interrupt_mask);
181
605cd25b
PZ		 182 if (new_val != dev_priv->pm_irq_mask) {
183 dev_priv->pm_irq_mask = new_val;
184 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
f52ecbcf
PZ		 185 POSTING_READ(GEN6_PMIMR);
186 }
edbfdb45
PZ		 187}
188
189void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
190{
191 snb_update_pm_irq(dev_priv, mask, mask);
192}
193
194void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
195{
196 snb_update_pm_irq(dev_priv, mask, 0);
197}
198
8664281b
PZ		 199static bool ivb_can_enable_err_int(struct drm_device *dev)
200{
201 struct drm_i915_private *dev_priv = dev->dev_private;
202 struct intel_crtc *crtc;
203 enum pipe pipe;
204
4bc9d430
DV		 205 assert_spin_locked(&dev_priv->irq_lock);
206
8664281b
PZ		 207 for_each_pipe(pipe) {
208 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
209
210 if (crtc->cpu_fifo_underrun_disabled)
211 return false;
212 }
213
214 return true;
215}
216
217static bool cpt_can_enable_serr_int(struct drm_device *dev)
218{
219 struct drm_i915_private *dev_priv = dev->dev_private;
220 enum pipe pipe;
221 struct intel_crtc *crtc;
222
fee884ed
DV		 223 assert_spin_locked(&dev_priv->irq_lock);
224
8664281b
PZ		 225 for_each_pipe(pipe) {
226 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
227
228 if (crtc->pch_fifo_underrun_disabled)
229 return false;
230 }
231
232 return true;
233}
234
235static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
236 enum pipe pipe, bool enable)
237{
238 struct drm_i915_private *dev_priv = dev->dev_private;
239 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
240 DE_PIPEB_FIFO_UNDERRUN;
241
242 if (enable)
243 ironlake_enable_display_irq(dev_priv, bit);
244 else
245 ironlake_disable_display_irq(dev_priv, bit);
246}
247
248static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
7336df65 249 enum pipe pipe, bool enable)
8664281b
PZ		 250{
251 struct drm_i915_private *dev_priv = dev->dev_private;
8664281b 252 if (enable) {
7336df65
DV		 253 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
254
8664281b
PZ		 255 if (!ivb_can_enable_err_int(dev))
256 return;
257
8664281b
PZ		 258 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
259 } else {
7336df65
DV		 260 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
261
262 /* Change the state _after_ we've read out the current one. */
8664281b 263 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
7336df65
DV		 264
265 if (!was_enabled &&
266 (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
267 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
268 pipe_name(pipe));
269 }
8664281b
PZ		 270 }
271}
272
fee884ed
DV		 273/**
274 * ibx_display_interrupt_update - update SDEIMR
275 * @dev_priv: driver private
276 * @interrupt_mask: mask of interrupt bits to update
277 * @enabled_irq_mask: mask of interrupt bits to enable
278 */
279static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
280 uint32_t interrupt_mask,
281 uint32_t enabled_irq_mask)
282{
283 uint32_t sdeimr = I915_READ(SDEIMR);
284 sdeimr &= ~interrupt_mask;
285 sdeimr |= (~enabled_irq_mask & interrupt_mask);
286
287 assert_spin_locked(&dev_priv->irq_lock);
288
c67a470b
PZ		 289 if (dev_priv->pc8.irqs_disabled &&
290 (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) {
291 WARN(1, "IRQs disabled\n");
292 dev_priv->pc8.regsave.sdeimr &= ~interrupt_mask;
293 dev_priv->pc8.regsave.sdeimr |= (~enabled_irq_mask &
294 interrupt_mask);
295 return;
296 }
297
fee884ed
DV		 298 I915_WRITE(SDEIMR, sdeimr);
299 POSTING_READ(SDEIMR);
300}
301#define ibx_enable_display_interrupt(dev_priv, bits) \
302 ibx_display_interrupt_update((dev_priv), (bits), (bits))
303#define ibx_disable_display_interrupt(dev_priv, bits) \
304 ibx_display_interrupt_update((dev_priv), (bits), 0)
305
de28075d
DV		 306static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
307 enum transcoder pch_transcoder,
8664281b
PZ		 308 bool enable)
309{
8664281b 310 struct drm_i915_private *dev_priv = dev->dev_private;
de28075d
DV		 311 uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
312 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
8664281b
PZ		 313
314 if (enable)
fee884ed 315 ibx_enable_display_interrupt(dev_priv, bit);
8664281b 316 else
fee884ed 317 ibx_disable_display_interrupt(dev_priv, bit);
8664281b
PZ		 318}
319
320static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
321 enum transcoder pch_transcoder,
322 bool enable)
323{
324 struct drm_i915_private *dev_priv = dev->dev_private;
325
326 if (enable) {
1dd246fb
DV		 327 I915_WRITE(SERR_INT,
328 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
329
8664281b
PZ		 330 if (!cpt_can_enable_serr_int(dev))
331 return;
332
fee884ed 333 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
8664281b 334 } else {
1dd246fb
DV		 335 uint32_t tmp = I915_READ(SERR_INT);
336 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
337
338 /* Change the state _after_ we've read out the current one. */
fee884ed 339 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
1dd246fb
DV		 340
341 if (!was_enabled &&
342 (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
343 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
344 transcoder_name(pch_transcoder));
345 }
8664281b 346 }
8664281b
PZ		 347}
348
349/**
350 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
351 * @dev: drm device
352 * @pipe: pipe
353 * @enable: true if we want to report FIFO underrun errors, false otherwise
354 *
355 * This function makes us disable or enable CPU fifo underruns for a specific
356 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
357 * reporting for one pipe may also disable all the other CPU error interruts for
358 * the other pipes, due to the fact that there's just one interrupt mask/enable
359 * bit for all the pipes.
360 *
361 * Returns the previous state of underrun reporting.
362 */
363bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
364 enum pipe pipe, bool enable)
365{
366 struct drm_i915_private *dev_priv = dev->dev_private;
367 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
369 unsigned long flags;
370 bool ret;
371
372 spin_lock_irqsave(&dev_priv->irq_lock, flags);
373
374 ret = !intel_crtc->cpu_fifo_underrun_disabled;
375
376 if (enable == ret)
377 goto done;
378
379 intel_crtc->cpu_fifo_underrun_disabled = !enable;
380
381 if (IS_GEN5(dev) || IS_GEN6(dev))
382 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
383 else if (IS_GEN7(dev))
7336df65 384 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
8664281b
PZ		 385
386done:
387 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
388 return ret;
389}
390
391/**
392 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
393 * @dev: drm device
394 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
395 * @enable: true if we want to report FIFO underrun errors, false otherwise
396 *
397 * This function makes us disable or enable PCH fifo underruns for a specific
398 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
399 * underrun reporting for one transcoder may also disable all the other PCH
400 * error interruts for the other transcoders, due to the fact that there's just
401 * one interrupt mask/enable bit for all the transcoders.
402 *
403 * Returns the previous state of underrun reporting.
404 */
405bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
406 enum transcoder pch_transcoder,
407 bool enable)
408{
409 struct drm_i915_private *dev_priv = dev->dev_private;
de28075d
DV		 410 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
411 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8664281b
PZ		 412 unsigned long flags;
413 bool ret;
414
de28075d
DV		 415 /*
416 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
417 * has only one pch transcoder A that all pipes can use. To avoid racy
418 * pch transcoder -> pipe lookups from interrupt code simply store the
419 * underrun statistics in crtc A. Since we never expose this anywhere
420 * nor use it outside of the fifo underrun code here using the "wrong"
421 * crtc on LPT won't cause issues.
422 */
8664281b
PZ		 423
424 spin_lock_irqsave(&dev_priv->irq_lock, flags);
425
426 ret = !intel_crtc->pch_fifo_underrun_disabled;
427
428 if (enable == ret)
429 goto done;
430
431 intel_crtc->pch_fifo_underrun_disabled = !enable;
432
433 if (HAS_PCH_IBX(dev))
de28075d 434 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
8664281b
PZ		 435 else
436 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
437
438done:
439 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
440 return ret;
441}
442
443
7c463586
KP		 444void
445i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
446{
46c06a30
VS		 447 u32 reg = PIPESTAT(pipe);
448 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 449
b79480ba
DV		 450 assert_spin_locked(&dev_priv->irq_lock);
451
46c06a30
VS		 452 if ((pipestat & mask) == mask)
453 return;
454
455 /* Enable the interrupt, clear any pending status */
456 pipestat |= mask | (mask >> 16);
457 I915_WRITE(reg, pipestat);
458 POSTING_READ(reg);
7c463586
KP		 459}
460
461void
462i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
463{
46c06a30
VS		 464 u32 reg = PIPESTAT(pipe);
465 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 466
b79480ba
DV		 467 assert_spin_locked(&dev_priv->irq_lock);
468
46c06a30
VS		 469 if ((pipestat & mask) == 0)
470 return;
471
472 pipestat &= ~mask;
473 I915_WRITE(reg, pipestat);
474 POSTING_READ(reg);
7c463586
KP		 475}
476
01c66889 477/**
f49e38dd 478 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
01c66889 479 */
f49e38dd 480static void i915_enable_asle_pipestat(struct drm_device *dev)
01c66889 481{
1ec14ad3
CW		 482 drm_i915_private_t *dev_priv = dev->dev_private;
483 unsigned long irqflags;
484
f49e38dd
JN		 485 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
486 return;
487
1ec14ad3 488 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 489
f898780b
JN		 490 i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE);
491 if (INTEL_INFO(dev)->gen >= 4)
492 i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE);
1ec14ad3
CW		 493
494 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 495}
496
0a3e67a4
JB		 497/**
498 * i915_pipe_enabled - check if a pipe is enabled
499 * @dev: DRM device
500 * @pipe: pipe to check
501 *
502 * Reading certain registers when the pipe is disabled can hang the chip.
503 * Use this routine to make sure the PLL is running and the pipe is active
504 * before reading such registers if unsure.
505 */
506static int
507i915_pipe_enabled(struct drm_device *dev, int pipe)
508{
509 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
702e7a56 510
a01025af
DV		 511 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
512 /* Locking is horribly broken here, but whatever. */
513 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
514 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
71f8ba6b 515
a01025af
DV		 516 return intel_crtc->active;
517 } else {
518 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
519 }
0a3e67a4
JB		 520}
521
4cdb83ec
VS		 522static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
523{
524 /* Gen2 doesn't have a hardware frame counter */
525 return 0;
526}
527
42f52ef8
KP		 528/* Called from drm generic code, passed a 'crtc', which
529 * we use as a pipe index
530 */
f71d4af4 531static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 532{
533 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
534 unsigned long high_frame;
535 unsigned long low_frame;
391f75e2 536 u32 high1, high2, low, pixel, vbl_start;
0a3e67a4
JB		 537
538 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 539 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 540 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 541 return 0;
542 }
543
391f75e2
VS		 544 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
545 struct intel_crtc *intel_crtc =
546 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
547 const struct drm_display_mode *mode =
548 &intel_crtc->config.adjusted_mode;
549
550 vbl_start = mode->crtc_vblank_start * mode->crtc_htotal;
551 } else {
552 enum transcoder cpu_transcoder =
553 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
554 u32 htotal;
555
556 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
557 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
558
559 vbl_start *= htotal;
560 }
561
9db4a9c7
JB		 562 high_frame = PIPEFRAME(pipe);
563 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 564
0a3e67a4
JB		 565 /*
566 * High & low register fields aren't synchronized, so make sure
567 * we get a low value that's stable across two reads of the high
568 * register.
569 */
570 do {
5eddb70b 571 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
391f75e2 572 low = I915_READ(low_frame);
5eddb70b 573 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 574 } while (high1 != high2);
575
5eddb70b 576 high1 >>= PIPE_FRAME_HIGH_SHIFT;
391f75e2 577 pixel = low & PIPE_PIXEL_MASK;
5eddb70b 578 low >>= PIPE_FRAME_LOW_SHIFT;
391f75e2
VS		 579
580 /*
581 * The frame counter increments at beginning of active.
582 * Cook up a vblank counter by also checking the pixel
583 * counter against vblank start.
584 */
585 return ((high1 << 8) | low) + (pixel >= vbl_start);
0a3e67a4
JB		 586}
587
f71d4af4 588static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 589{
590 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 591 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 592
593 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 594 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 595 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 596 return 0;
597 }
598
599 return I915_READ(reg);
600}
601
7c06b08a 602static bool intel_pipe_in_vblank(struct drm_device *dev, enum pipe pipe)
54ddcbd2
VS		 603{
604 struct drm_i915_private *dev_priv = dev->dev_private;
605 uint32_t status;
606
607 if (IS_VALLEYVIEW(dev)) {
608 status = pipe == PIPE_A ?
609 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT :
610 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
611
612 return I915_READ(VLV_ISR) & status;
7c06b08a
VS		 613 } else if (IS_GEN2(dev)) {
614 status = pipe == PIPE_A ?
615 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT :
616 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
617
618 return I915_READ16(ISR) & status;
619 } else if (INTEL_INFO(dev)->gen < 5) {
54ddcbd2
VS		 620 status = pipe == PIPE_A ?
621 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT :
622 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
623
624 return I915_READ(ISR) & status;
625 } else if (INTEL_INFO(dev)->gen < 7) {
626 status = pipe == PIPE_A ?
627 DE_PIPEA_VBLANK :
628 DE_PIPEB_VBLANK;
629
630 return I915_READ(DEISR) & status;
631 } else {
632 switch (pipe) {
633 default:
634 case PIPE_A:
635 status = DE_PIPEA_VBLANK_IVB;
636 break;
637 case PIPE_B:
638 status = DE_PIPEB_VBLANK_IVB;
639 break;
640 case PIPE_C:
641 status = DE_PIPEC_VBLANK_IVB;
642 break;
643 }
644
645 return I915_READ(DEISR) & status;
646 }
647}
648
f71d4af4 649static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 650 int *vpos, int *hpos)
651{
c2baf4b7
VS		 652 struct drm_i915_private *dev_priv = dev->dev_private;
653 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
655 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
3aa18df8 656 int position;
0af7e4df
MK		 657 int vbl_start, vbl_end, htotal, vtotal;
658 bool in_vbl = true;
659 int ret = 0;
660
c2baf4b7 661 if (!intel_crtc->active) {
0af7e4df 662 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 663 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 664 return 0;
665 }
666
c2baf4b7
VS		 667 htotal = mode->crtc_htotal;
668 vtotal = mode->crtc_vtotal;
669 vbl_start = mode->crtc_vblank_start;
670 vbl_end = mode->crtc_vblank_end;
0af7e4df 671
c2baf4b7
VS		 672 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
673
7c06b08a 674 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
0af7e4df
MK		 675 /* No obvious pixelcount register. Only query vertical
676 * scanout position from Display scan line register.
677 */
7c06b08a
VS		 678 if (IS_GEN2(dev))
679 position = I915_READ(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
680 else
681 position = I915_READ(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
54ddcbd2
VS		 682
683 /*
684 * The scanline counter increments at the leading edge
685 * of hsync, ie. it completely misses the active portion
686 * of the line. Fix up the counter at both edges of vblank
687 * to get a more accurate picture whether we're in vblank
688 * or not.
689 */
7c06b08a 690 in_vbl = intel_pipe_in_vblank(dev, pipe);
54ddcbd2
VS		 691 if ((in_vbl && position == vbl_start - 1) ||
692 (!in_vbl && position == vbl_end - 1))
693 position = (position + 1) % vtotal;
0af7e4df
MK		 694 } else {
695 /* Have access to pixelcount since start of frame.
696 * We can split this into vertical and horizontal
697 * scanout position.
698 */
699 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
700
3aa18df8
VS		 701 /* convert to pixel counts */
702 vbl_start *= htotal;
703 vbl_end *= htotal;
704 vtotal *= htotal;
0af7e4df
MK		 705 }
706
3aa18df8
VS		 707 in_vbl = position >= vbl_start && position < vbl_end;
708
709 /*
710 * While in vblank, position will be negative
711 * counting up towards 0 at vbl_end. And outside
712 * vblank, position will be positive counting
713 * up since vbl_end.
714 */
715 if (position >= vbl_start)
716 position -= vbl_end;
717 else
718 position += vtotal - vbl_end;
0af7e4df 719
7c06b08a 720 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
3aa18df8
VS		 721 *vpos = position;
722 *hpos = 0;
723 } else {
724 *vpos = position / htotal;
725 *hpos = position - (*vpos * htotal);
726 }
0af7e4df 727
0af7e4df
MK		 728 /* In vblank? */
729 if (in_vbl)
730 ret |= DRM_SCANOUTPOS_INVBL;
731
732 return ret;
733}
734
f71d4af4 735static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 736 int *max_error,
737 struct timeval *vblank_time,
738 unsigned flags)
739{
4041b853 740 struct drm_crtc *crtc;
0af7e4df 741
7eb552ae 742 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
4041b853 743 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 744 return -EINVAL;
745 }
746
747 /* Get drm_crtc to timestamp: */
4041b853
CW		 748 crtc = intel_get_crtc_for_pipe(dev, pipe);
749 if (crtc == NULL) {
750 DRM_ERROR("Invalid crtc %d\n", pipe);
751 return -EINVAL;
752 }
753
754 if (!crtc->enabled) {
755 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
756 return -EBUSY;
757 }
0af7e4df
MK		 758
759 /* Helper routine in DRM core does all the work: */
4041b853
CW		 760 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
761 vblank_time, flags,
762 crtc);
0af7e4df
MK		 763}
764
67c347ff
JN		 765static bool intel_hpd_irq_event(struct drm_device *dev,
766 struct drm_connector *connector)
321a1b30
EE		 767{
768 enum drm_connector_status old_status;
769
770 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
771 old_status = connector->status;
772
773 connector->status = connector->funcs->detect(connector, false);
67c347ff
JN		 774 if (old_status == connector->status)
775 return false;
776
777 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
321a1b30
EE		 778 connector->base.id,
779 drm_get_connector_name(connector),
67c347ff
JN		 780 drm_get_connector_status_name(old_status),
781 drm_get_connector_status_name(connector->status));
782
783 return true;
321a1b30
EE		 784}
785
5ca58282
JB		 786/*
787 * Handle hotplug events outside the interrupt handler proper.
788 */
ac4c16c5
EE		 789#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
790
5ca58282
JB		 791static void i915_hotplug_work_func(struct work_struct *work)
792{
793 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
794 hotplug_work);
795 struct drm_device *dev = dev_priv->dev;
c31c4ba3 796 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed
EE		 797 struct intel_connector *intel_connector;
798 struct intel_encoder *intel_encoder;
799 struct drm_connector *connector;
800 unsigned long irqflags;
801 bool hpd_disabled = false;
321a1b30 802 bool changed = false;
142e2398 803 u32 hpd_event_bits;
4ef69c7a 804
52d7eced
DV		 805 /* HPD irq before everything is fully set up. */
806 if (!dev_priv->enable_hotplug_processing)
807 return;
808
a65e34c7 809 mutex_lock(&mode_config->mutex);
e67189ab
JB		 810 DRM_DEBUG_KMS("running encoder hotplug functions\n");
811
cd569aed 812 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
142e2398
EE		 813
814 hpd_event_bits = dev_priv->hpd_event_bits;
815 dev_priv->hpd_event_bits = 0;
cd569aed
EE		 816 list_for_each_entry(connector, &mode_config->connector_list, head) {
817 intel_connector = to_intel_connector(connector);
818 intel_encoder = intel_connector->encoder;
819 if (intel_encoder->hpd_pin > HPD_NONE &&
820 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
821 connector->polled == DRM_CONNECTOR_POLL_HPD) {
822 DRM_INFO("HPD interrupt storm detected on connector %s: "
823 "switching from hotplug detection to polling\n",
824 drm_get_connector_name(connector));
825 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
826 connector->polled = DRM_CONNECTOR_POLL_CONNECT
827 | DRM_CONNECTOR_POLL_DISCONNECT;
828 hpd_disabled = true;
829 }
142e2398
EE		 830 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
831 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
832 drm_get_connector_name(connector), intel_encoder->hpd_pin);
833 }
cd569aed
EE		 834 }
835 /* if there were no outputs to poll, poll was disabled,
836 * therefore make sure it's enabled when disabling HPD on
837 * some connectors */
ac4c16c5 838 if (hpd_disabled) {
cd569aed 839 drm_kms_helper_poll_enable(dev);
ac4c16c5
EE		 840 mod_timer(&dev_priv->hotplug_reenable_timer,
841 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
842 }
cd569aed
EE		 843
844 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
845
321a1b30
EE		 846 list_for_each_entry(connector, &mode_config->connector_list, head) {
847 intel_connector = to_intel_connector(connector);
848 intel_encoder = intel_connector->encoder;
849 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
850 if (intel_encoder->hot_plug)
851 intel_encoder->hot_plug(intel_encoder);
852 if (intel_hpd_irq_event(dev, connector))
853 changed = true;
854 }
855 }
40ee3381
KP		 856 mutex_unlock(&mode_config->mutex);
857
321a1b30
EE		 858 if (changed)
859 drm_kms_helper_hotplug_event(dev);
5ca58282
JB		 860}
861
d0ecd7e2 862static void ironlake_rps_change_irq_handler(struct drm_device *dev)
f97108d1
JB		 863{
864 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 865 u32 busy_up, busy_down, max_avg, min_avg;
9270388e 866 u8 new_delay;
9270388e 867
d0ecd7e2 868 spin_lock(&mchdev_lock);
f97108d1 869
73edd18f
DV		 870 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
871
20e4d407 872 new_delay = dev_priv->ips.cur_delay;
9270388e 873
7648fa99 874 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 875 busy_up = I915_READ(RCPREVBSYTUPAVG);
876 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 877 max_avg = I915_READ(RCBMAXAVG);
878 min_avg = I915_READ(RCBMINAVG);
879
880 /* Handle RCS change request from hw */
b5b72e89 881 if (busy_up > max_avg) {
20e4d407
DV		 882 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
883 new_delay = dev_priv->ips.cur_delay - 1;
884 if (new_delay < dev_priv->ips.max_delay)
885 new_delay = dev_priv->ips.max_delay;
b5b72e89 886 } else if (busy_down < min_avg) {
20e4d407
DV		 887 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
888 new_delay = dev_priv->ips.cur_delay + 1;
889 if (new_delay > dev_priv->ips.min_delay)
890 new_delay = dev_priv->ips.min_delay;
f97108d1
JB		 891 }
892
7648fa99 893 if (ironlake_set_drps(dev, new_delay))
20e4d407 894 dev_priv->ips.cur_delay = new_delay;
f97108d1 895
d0ecd7e2 896 spin_unlock(&mchdev_lock);
9270388e 897
f97108d1
JB		 898 return;
899}
900
549f7365
CW		 901static void notify_ring(struct drm_device *dev,
902 struct intel_ring_buffer *ring)
903{
475553de
CW		 904 if (ring->obj == NULL)
905 return;
906
814e9b57 907 trace_i915_gem_request_complete(ring);
9862e600 908
549f7365 909 wake_up_all(&ring->irq_queue);
10cd45b6 910 i915_queue_hangcheck(dev);
549f7365
CW		 911}
912
4912d041 913static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 914{
4912d041 915 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
c6a828d3 916 rps.work);
edbfdb45 917 u32 pm_iir;
dd75fdc8 918 int new_delay, adj;
4912d041 919
59cdb63d 920 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3
DV		 921 pm_iir = dev_priv->rps.pm_iir;
922 dev_priv->rps.pm_iir = 0;
4848405c 923 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
edbfdb45 924 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
59cdb63d 925 spin_unlock_irq(&dev_priv->irq_lock);
3b8d8d91 926
60611c13
PZ		 927 /* Make sure we didn't queue anything we're not going to process. */
928 WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS);
929
4848405c 930 if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
3b8d8d91
JB		 931 return;
932
4fc688ce 933 mutex_lock(&dev_priv->rps.hw_lock);
7b9e0ae6 934
dd75fdc8 935 adj = dev_priv->rps.last_adj;
7425034a 936 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
dd75fdc8
CW		 937 if (adj > 0)
938 adj *= 2;
939 else
940 adj = 1;
941 new_delay = dev_priv->rps.cur_delay + adj;
7425034a
VS		 942
943 /*
944 * For better performance, jump directly
945 * to RPe if we're below it.
946 */
dd75fdc8
CW		 947 if (new_delay < dev_priv->rps.rpe_delay)
948 new_delay = dev_priv->rps.rpe_delay;
949 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
950 if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
7425034a 951 new_delay = dev_priv->rps.rpe_delay;
dd75fdc8
CW		 952 else
953 new_delay = dev_priv->rps.min_delay;
954 adj = 0;
955 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
956 if (adj < 0)
957 adj *= 2;
958 else
959 adj = -1;
960 new_delay = dev_priv->rps.cur_delay + adj;
961 } else { /* unknown event */
962 new_delay = dev_priv->rps.cur_delay;
963 }
3b8d8d91 964
79249636
BW		 965 /* sysfs frequency interfaces may have snuck in while servicing the
966 * interrupt
967 */
dd75fdc8
CW		 968 if (new_delay < (int)dev_priv->rps.min_delay)
969 new_delay = dev_priv->rps.min_delay;
970 if (new_delay > (int)dev_priv->rps.max_delay)
971 new_delay = dev_priv->rps.max_delay;
972 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay;
973
974 if (IS_VALLEYVIEW(dev_priv->dev))
975 valleyview_set_rps(dev_priv->dev, new_delay);
976 else
977 gen6_set_rps(dev_priv->dev, new_delay);
3b8d8d91 978
4fc688ce 979 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91
JB		 980}
981
e3689190
BW		 982
983/**
984 * ivybridge_parity_work - Workqueue called when a parity error interrupt
985 * occurred.
986 * @work: workqueue struct
987 *
988 * Doesn't actually do anything except notify userspace. As a consequence of
989 * this event, userspace should try to remap the bad rows since statistically
990 * it is likely the same row is more likely to go bad again.
991 */
992static void ivybridge_parity_work(struct work_struct *work)
993{
994 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
a4da4fa4 995 l3_parity.error_work);
e3689190 996 u32 error_status, row, bank, subbank;
35a85ac6 997 char *parity_event[6];
e3689190
BW		 998 uint32_t misccpctl;
999 unsigned long flags;
35a85ac6 1000 uint8_t slice = 0;
e3689190
BW		 1001
1002 /* We must turn off DOP level clock gating to access the L3 registers.
1003 * In order to prevent a get/put style interface, acquire struct mutex
1004 * any time we access those registers.
1005 */
1006 mutex_lock(&dev_priv->dev->struct_mutex);
1007
35a85ac6
BW		 1008 /* If we've screwed up tracking, just let the interrupt fire again */
1009 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1010 goto out;
1011
e3689190
BW		 1012 misccpctl = I915_READ(GEN7_MISCCPCTL);
1013 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1014 POSTING_READ(GEN7_MISCCPCTL);
1015
35a85ac6
BW		 1016 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1017 u32 reg;
e3689190 1018
35a85ac6
BW		 1019 slice--;
1020 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1021 break;
e3689190 1022
35a85ac6 1023 dev_priv->l3_parity.which_slice &= ~(1<<slice);
e3689190 1024
35a85ac6 1025 reg = GEN7_L3CDERRST1 + (slice * 0x200);
e3689190 1026
35a85ac6
BW		 1027 error_status = I915_READ(reg);
1028 row = GEN7_PARITY_ERROR_ROW(error_status);
1029 bank = GEN7_PARITY_ERROR_BANK(error_status);
1030 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1031
1032 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1033 POSTING_READ(reg);
1034
1035 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1036 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1037 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1038 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1039 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1040 parity_event[5] = NULL;
1041
1042 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
1043 KOBJ_CHANGE, parity_event);
e3689190 1044
35a85ac6
BW		 1045 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1046 slice, row, bank, subbank);
e3689190 1047
35a85ac6
BW		 1048 kfree(parity_event[4]);
1049 kfree(parity_event[3]);
1050 kfree(parity_event[2]);
1051 kfree(parity_event[1]);
1052 }
e3689190 1053
35a85ac6 1054 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
e3689190 1055
35a85ac6
BW		 1056out:
1057 WARN_ON(dev_priv->l3_parity.which_slice);
1058 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1059 ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1060 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1061
1062 mutex_unlock(&dev_priv->dev->struct_mutex);
e3689190
BW		 1063}
1064
35a85ac6 1065static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
e3689190
BW		 1066{
1067 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e3689190 1068
040d2baa 1069 if (!HAS_L3_DPF(dev))
e3689190
BW		 1070 return;
1071
d0ecd7e2 1072 spin_lock(&dev_priv->irq_lock);
35a85ac6 1073 ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
d0ecd7e2 1074 spin_unlock(&dev_priv->irq_lock);
e3689190 1075
35a85ac6
BW		 1076 iir &= GT_PARITY_ERROR(dev);
1077 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1078 dev_priv->l3_parity.which_slice |= 1 << 1;
1079
1080 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1081 dev_priv->l3_parity.which_slice |= 1 << 0;
1082
a4da4fa4 1083 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
e3689190
BW		 1084}
1085
f1af8fc1
PZ		 1086static void ilk_gt_irq_handler(struct drm_device *dev,
1087 struct drm_i915_private *dev_priv,
1088 u32 gt_iir)
1089{
1090 if (gt_iir &
1091 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1092 notify_ring(dev, &dev_priv->ring[RCS]);
1093 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1094 notify_ring(dev, &dev_priv->ring[VCS]);
1095}
1096
e7b4c6b1
DV		 1097static void snb_gt_irq_handler(struct drm_device *dev,
1098 struct drm_i915_private *dev_priv,
1099 u32 gt_iir)
1100{
1101
cc609d5d
BW		 1102 if (gt_iir &
1103 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
e7b4c6b1 1104 notify_ring(dev, &dev_priv->ring[RCS]);
cc609d5d 1105 if (gt_iir & GT_BSD_USER_INTERRUPT)
e7b4c6b1 1106 notify_ring(dev, &dev_priv->ring[VCS]);
cc609d5d 1107 if (gt_iir & GT_BLT_USER_INTERRUPT)
e7b4c6b1
DV		 1108 notify_ring(dev, &dev_priv->ring[BCS]);
1109
cc609d5d
BW		 1110 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1111 GT_BSD_CS_ERROR_INTERRUPT |
1112 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
e7b4c6b1
DV		 1113 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
1114 i915_handle_error(dev, false);
1115 }
e3689190 1116
35a85ac6
BW		 1117 if (gt_iir & GT_PARITY_ERROR(dev))
1118 ivybridge_parity_error_irq_handler(dev, gt_iir);
e7b4c6b1
DV		 1119}
1120
b543fb04
EE		 1121#define HPD_STORM_DETECT_PERIOD 1000
1122#define HPD_STORM_THRESHOLD 5
1123
10a504de 1124static inline void intel_hpd_irq_handler(struct drm_device *dev,
22062dba
DV		 1125 u32 hotplug_trigger,
1126 const u32 *hpd)
b543fb04
EE		 1127{
1128 drm_i915_private_t *dev_priv = dev->dev_private;
b543fb04 1129 int i;
10a504de 1130 bool storm_detected = false;
b543fb04 1131
91d131d2
DV		 1132 if (!hotplug_trigger)
1133 return;
1134
b5ea2d56 1135 spin_lock(&dev_priv->irq_lock);
b543fb04 1136 for (i = 1; i < HPD_NUM_PINS; i++) {
821450c6 1137
b8f102e8
EE		 1138 WARN(((hpd[i] & hotplug_trigger) &&
1139 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED),
1140 "Received HPD interrupt although disabled\n");
1141
b543fb04
EE		 1142 if (!(hpd[i] & hotplug_trigger) ||
1143 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1144 continue;
1145
bc5ead8c 1146 dev_priv->hpd_event_bits |= (1 << i);
b543fb04
EE		 1147 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1148 dev_priv->hpd_stats[i].hpd_last_jiffies
1149 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1150 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1151 dev_priv->hpd_stats[i].hpd_cnt = 0;
b8f102e8 1152 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
b543fb04
EE		 1153 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1154 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
142e2398 1155 dev_priv->hpd_event_bits &= ~(1 << i);
b543fb04 1156 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
10a504de 1157 storm_detected = true;
b543fb04
EE		 1158 } else {
1159 dev_priv->hpd_stats[i].hpd_cnt++;
b8f102e8
EE		 1160 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1161 dev_priv->hpd_stats[i].hpd_cnt);
b543fb04
EE		 1162 }
1163 }
1164
10a504de
DV		 1165 if (storm_detected)
1166 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 1167 spin_unlock(&dev_priv->irq_lock);
5876fa0d 1168
645416f5
DV		 1169 /*
1170 * Our hotplug handler can grab modeset locks (by calling down into the
1171 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1172 * queue for otherwise the flush_work in the pageflip code will
1173 * deadlock.
1174 */
1175 schedule_work(&dev_priv->hotplug_work);
b543fb04
EE		 1176}
1177
515ac2bb
DV		 1178static void gmbus_irq_handler(struct drm_device *dev)
1179{
28c70f16
DV		 1180 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1181
28c70f16 1182 wake_up_all(&dev_priv->gmbus_wait_queue);
515ac2bb
DV		 1183}
1184
ce99c256
DV		 1185static void dp_aux_irq_handler(struct drm_device *dev)
1186{
9ee32fea
DV		 1187 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1188
9ee32fea 1189 wake_up_all(&dev_priv->gmbus_wait_queue);
ce99c256
DV		 1190}
1191
8bf1e9f1 1192#if defined(CONFIG_DEBUG_FS)
eba94eb9
DV		 1193static void display_pipe_crc_update(struct drm_device *dev, enum pipe pipe,
1194 uint32_t crc0, uint32_t crc1,
1195 uint32_t crc2, uint32_t crc3,
8bc5e955 1196 uint32_t crc4)
8bf1e9f1
SH		 1197{
1198 struct drm_i915_private *dev_priv = dev->dev_private;
1199 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1200 struct intel_pipe_crc_entry *entry;
ac2300d4 1201 int head, tail;
b2c88f5b 1202
0c912c79
DL		 1203 if (!pipe_crc->entries) {
1204 DRM_ERROR("spurious interrupt\n");
1205 return;
1206 }
1207
b2c88f5b
DL		 1208 head = atomic_read(&pipe_crc->head);
1209 tail = atomic_read(&pipe_crc->tail);
1210
1211 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1212 DRM_ERROR("CRC buffer overflowing\n");
1213 return;
1214 }
1215
1216 entry = &pipe_crc->entries[head];
8bf1e9f1 1217
8bc5e955 1218 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
eba94eb9
DV		 1219 entry->crc[0] = crc0;
1220 entry->crc[1] = crc1;
1221 entry->crc[2] = crc2;
1222 entry->crc[3] = crc3;
1223 entry->crc[4] = crc4;
b2c88f5b
DL		 1224
1225 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1226 atomic_set(&pipe_crc->head, head);
07144428
DL		 1227
1228 wake_up_interruptible(&pipe_crc->wq);
8bf1e9f1 1229}
eba94eb9
DV		 1230
1231static void ivb_pipe_crc_update(struct drm_device *dev, enum pipe pipe)
1232{
1233 struct drm_i915_private *dev_priv = dev->dev_private;
1234
1235 display_pipe_crc_update(dev, pipe,
1236 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1237 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1238 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1239 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
8bc5e955 1240 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
eba94eb9 1241}
5b3a856b
DV		 1242
1243static void ilk_pipe_crc_update(struct drm_device *dev, enum pipe pipe)
1244{
1245 struct drm_i915_private *dev_priv = dev->dev_private;
1246
1247 display_pipe_crc_update(dev, pipe,
1248 I915_READ(PIPE_CRC_RES_RED_ILK(pipe)),
1249 I915_READ(PIPE_CRC_RES_GREEN_ILK(pipe)),
1250 I915_READ(PIPE_CRC_RES_BLUE_ILK(pipe)),
1251 I915_READ(PIPE_CRC_RES_RES1_ILK(pipe)),
8bc5e955 1252 I915_READ(PIPE_CRC_RES_RES2_ILK(pipe)));
5b3a856b 1253}
8bf1e9f1 1254#else
f8c168fa 1255static inline void ivb_pipe_crc_update(struct drm_device *dev, int pipe) {}
5b3a856b 1256static inline void ilk_pipe_crc_update(struct drm_device *dev, int pipe) {}
8bf1e9f1
SH		 1257#endif
1258
1403c0d4
PZ		 1259/* The RPS events need forcewake, so we add them to a work queue and mask their
1260 * IMR bits until the work is done. Other interrupts can be processed without
1261 * the work queue. */
1262static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
baf02a1f 1263{
41a05a3a 1264 if (pm_iir & GEN6_PM_RPS_EVENTS) {
59cdb63d 1265 spin_lock(&dev_priv->irq_lock);
41a05a3a 1266 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
4d3b3d5f 1267 snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS);
59cdb63d 1268 spin_unlock(&dev_priv->irq_lock);
2adbee62
DV		 1269
1270 queue_work(dev_priv->wq, &dev_priv->rps.work);
baf02a1f 1271 }
baf02a1f 1272
1403c0d4
PZ		 1273 if (HAS_VEBOX(dev_priv->dev)) {
1274 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1275 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
12638c57 1276
1403c0d4
PZ		 1277 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1278 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
1279 i915_handle_error(dev_priv->dev, false);
1280 }
12638c57 1281 }
baf02a1f
BW		 1282}
1283
ff1f525e 1284static irqreturn_t valleyview_irq_handler(int irq, void *arg)
7e231dbe
JB		 1285{
1286 struct drm_device *dev = (struct drm_device *) arg;
1287 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1288 u32 iir, gt_iir, pm_iir;
1289 irqreturn_t ret = IRQ_NONE;
1290 unsigned long irqflags;
1291 int pipe;
1292 u32 pipe_stats[I915_MAX_PIPES];
7e231dbe
JB		 1293
1294 atomic_inc(&dev_priv->irq_received);
1295
7e231dbe
JB		 1296 while (true) {
1297 iir = I915_READ(VLV_IIR);
1298 gt_iir = I915_READ(GTIIR);
1299 pm_iir = I915_READ(GEN6_PMIIR);
1300
1301 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1302 goto out;
1303
1304 ret = IRQ_HANDLED;
1305
e7b4c6b1 1306 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 1307
1308 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1309 for_each_pipe(pipe) {
1310 int reg = PIPESTAT(pipe);
1311 pipe_stats[pipe] = I915_READ(reg);
1312
1313 /*
1314 * Clear the PIPE*STAT regs before the IIR
1315 */
1316 if (pipe_stats[pipe] & 0x8000ffff) {
1317 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1318 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1319 pipe_name(pipe));
1320 I915_WRITE(reg, pipe_stats[pipe]);
1321 }
1322 }
1323 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1324
31acc7f5
JB		 1325 for_each_pipe(pipe) {
1326 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1327 drm_handle_vblank(dev, pipe);
1328
1329 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
1330 intel_prepare_page_flip(dev, pipe);
1331 intel_finish_page_flip(dev, pipe);
1332 }
1333 }
1334
7e231dbe
JB		 1335 /* Consume port. Then clear IIR or we'll miss events */
1336 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1337 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04 1338 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
7e231dbe
JB		 1339
1340 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1341 hotplug_status);
91d131d2
DV		 1342
1343 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1344
7e231dbe
JB		 1345 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1346 I915_READ(PORT_HOTPLUG_STAT);
1347 }
1348
515ac2bb
DV		 1349 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1350 gmbus_irq_handler(dev);
7e231dbe 1351
60611c13 1352 if (pm_iir)
d0ecd7e2 1353 gen6_rps_irq_handler(dev_priv, pm_iir);
7e231dbe
JB		 1354
1355 I915_WRITE(GTIIR, gt_iir);
1356 I915_WRITE(GEN6_PMIIR, pm_iir);
1357 I915_WRITE(VLV_IIR, iir);
1358 }
1359
1360out:
1361 return ret;
1362}
1363
23e81d69 1364static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 1365{
1366 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 1367 int pipe;
b543fb04 1368 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
776ad806 1369
91d131d2
DV		 1370 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1371
cfc33bf7
VS		 1372 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1373 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1374 SDE_AUDIO_POWER_SHIFT);
776ad806 1375 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
cfc33bf7
VS		 1376 port_name(port));
1377 }
776ad806 1378
ce99c256
DV		 1379 if (pch_iir & SDE_AUX_MASK)
1380 dp_aux_irq_handler(dev);
1381
776ad806 1382 if (pch_iir & SDE_GMBUS)
515ac2bb 1383 gmbus_irq_handler(dev);
776ad806
JB		 1384
1385 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1386 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1387
1388 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1389 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1390
1391 if (pch_iir & SDE_POISON)
1392 DRM_ERROR("PCH poison interrupt\n");
1393
9db4a9c7
JB		 1394 if (pch_iir & SDE_FDI_MASK)
1395 for_each_pipe(pipe)
1396 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1397 pipe_name(pipe),
1398 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 1399
1400 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1401 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1402
1403 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1404 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1405
776ad806 1406 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
8664281b
PZ		 1407 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1408 false))
1409 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1410
1411 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1412 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1413 false))
1414 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1415}
1416
1417static void ivb_err_int_handler(struct drm_device *dev)
1418{
1419 struct drm_i915_private *dev_priv = dev->dev_private;
1420 u32 err_int = I915_READ(GEN7_ERR_INT);
1421
de032bf4
PZ		 1422 if (err_int & ERR_INT_POISON)
1423 DRM_ERROR("Poison interrupt\n");
1424
8664281b
PZ		 1425 if (err_int & ERR_INT_FIFO_UNDERRUN_A)
1426 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1427 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1428
1429 if (err_int & ERR_INT_FIFO_UNDERRUN_B)
1430 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1431 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1432
1433 if (err_int & ERR_INT_FIFO_UNDERRUN_C)
1434 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false))
1435 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1436
8bf1e9f1
SH		 1437 if (err_int & ERR_INT_PIPE_CRC_DONE_A)
1438 ivb_pipe_crc_update(dev, PIPE_A);
1439
1440 if (err_int & ERR_INT_PIPE_CRC_DONE_B)
1441 ivb_pipe_crc_update(dev, PIPE_B);
1442
1443 if (err_int & ERR_INT_PIPE_CRC_DONE_C)
1444 ivb_pipe_crc_update(dev, PIPE_C);
1445
8664281b
PZ		 1446 I915_WRITE(GEN7_ERR_INT, err_int);
1447}
1448
1449static void cpt_serr_int_handler(struct drm_device *dev)
1450{
1451 struct drm_i915_private *dev_priv = dev->dev_private;
1452 u32 serr_int = I915_READ(SERR_INT);
1453
de032bf4
PZ		 1454 if (serr_int & SERR_INT_POISON)
1455 DRM_ERROR("PCH poison interrupt\n");
1456
8664281b
PZ		 1457 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1458 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1459 false))
1460 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1461
1462 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1463 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1464 false))
1465 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1466
1467 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1468 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1469 false))
1470 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1471
1472 I915_WRITE(SERR_INT, serr_int);
776ad806
JB		 1473}
1474
23e81d69
AJ		 1475static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1476{
1477 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1478 int pipe;
b543fb04 1479 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
23e81d69 1480
91d131d2
DV		 1481 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1482
cfc33bf7
VS		 1483 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1484 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1485 SDE_AUDIO_POWER_SHIFT_CPT);
1486 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1487 port_name(port));
1488 }
23e81d69
AJ		 1489
1490 if (pch_iir & SDE_AUX_MASK_CPT)
ce99c256 1491 dp_aux_irq_handler(dev);
23e81d69
AJ		 1492
1493 if (pch_iir & SDE_GMBUS_CPT)
515ac2bb 1494 gmbus_irq_handler(dev);
23e81d69
AJ		 1495
1496 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1497 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1498
1499 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1500 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1501
1502 if (pch_iir & SDE_FDI_MASK_CPT)
1503 for_each_pipe(pipe)
1504 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1505 pipe_name(pipe),
1506 I915_READ(FDI_RX_IIR(pipe)));
8664281b
PZ		 1507
1508 if (pch_iir & SDE_ERROR_CPT)
1509 cpt_serr_int_handler(dev);
23e81d69
AJ		 1510}
1511
c008bc6e
PZ		 1512static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1513{
1514 struct drm_i915_private *dev_priv = dev->dev_private;
1515
1516 if (de_iir & DE_AUX_CHANNEL_A)
1517 dp_aux_irq_handler(dev);
1518
1519 if (de_iir & DE_GSE)
1520 intel_opregion_asle_intr(dev);
1521
1522 if (de_iir & DE_PIPEA_VBLANK)
1523 drm_handle_vblank(dev, 0);
1524
1525 if (de_iir & DE_PIPEB_VBLANK)
1526 drm_handle_vblank(dev, 1);
1527
1528 if (de_iir & DE_POISON)
1529 DRM_ERROR("Poison interrupt\n");
1530
1531 if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
1532 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1533 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1534
1535 if (de_iir & DE_PIPEB_FIFO_UNDERRUN)
1536 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1537 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1538
5b3a856b
DV		 1539 if (de_iir & DE_PIPEA_CRC_DONE)
1540 ilk_pipe_crc_update(dev, PIPE_A);
1541
1542 if (de_iir & DE_PIPEB_CRC_DONE)
1543 ilk_pipe_crc_update(dev, PIPE_B);
1544
c008bc6e
PZ		 1545 if (de_iir & DE_PLANEA_FLIP_DONE) {
1546 intel_prepare_page_flip(dev, 0);
1547 intel_finish_page_flip_plane(dev, 0);
1548 }
1549
1550 if (de_iir & DE_PLANEB_FLIP_DONE) {
1551 intel_prepare_page_flip(dev, 1);
1552 intel_finish_page_flip_plane(dev, 1);
1553 }
1554
1555 /* check event from PCH */
1556 if (de_iir & DE_PCH_EVENT) {
1557 u32 pch_iir = I915_READ(SDEIIR);
1558
1559 if (HAS_PCH_CPT(dev))
1560 cpt_irq_handler(dev, pch_iir);
1561 else
1562 ibx_irq_handler(dev, pch_iir);
1563
1564 /* should clear PCH hotplug event before clear CPU irq */
1565 I915_WRITE(SDEIIR, pch_iir);
1566 }
1567
1568 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1569 ironlake_rps_change_irq_handler(dev);
1570}
1571
9719fb98
PZ		 1572static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
1573{
1574 struct drm_i915_private *dev_priv = dev->dev_private;
1575 int i;
1576
1577 if (de_iir & DE_ERR_INT_IVB)
1578 ivb_err_int_handler(dev);
1579
1580 if (de_iir & DE_AUX_CHANNEL_A_IVB)
1581 dp_aux_irq_handler(dev);
1582
1583 if (de_iir & DE_GSE_IVB)
1584 intel_opregion_asle_intr(dev);
1585
1586 for (i = 0; i < 3; i++) {
1587 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
1588 drm_handle_vblank(dev, i);
1589 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
1590 intel_prepare_page_flip(dev, i);
1591 intel_finish_page_flip_plane(dev, i);
1592 }
1593 }
1594
1595 /* check event from PCH */
1596 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1597 u32 pch_iir = I915_READ(SDEIIR);
1598
1599 cpt_irq_handler(dev, pch_iir);
1600
1601 /* clear PCH hotplug event before clear CPU irq */
1602 I915_WRITE(SDEIIR, pch_iir);
1603 }
1604}
1605
f1af8fc1 1606static irqreturn_t ironlake_irq_handler(int irq, void *arg)
b1f14ad0
JB		 1607{
1608 struct drm_device *dev = (struct drm_device *) arg;
1609 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
f1af8fc1 1610 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
0e43406b 1611 irqreturn_t ret = IRQ_NONE;
b1f14ad0
JB		 1612
1613 atomic_inc(&dev_priv->irq_received);
1614
8664281b
PZ		 1615 /* We get interrupts on unclaimed registers, so check for this before we
1616 * do any I915_{READ,WRITE}. */
907b28c5 1617 intel_uncore_check_errors(dev);
8664281b 1618
b1f14ad0
JB		 1619 /* disable master interrupt before clearing iir */
1620 de_ier = I915_READ(DEIER);
1621 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
23a78516 1622 POSTING_READ(DEIER);
b1f14ad0 1623
44498aea
PZ		 1624 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1625 * interrupts will will be stored on its back queue, and then we'll be
1626 * able to process them after we restore SDEIER (as soon as we restore
1627 * it, we'll get an interrupt if SDEIIR still has something to process
1628 * due to its back queue). */
ab5c608b
BW		 1629 if (!HAS_PCH_NOP(dev)) {
1630 sde_ier = I915_READ(SDEIER);
1631 I915_WRITE(SDEIER, 0);
1632 POSTING_READ(SDEIER);
1633 }
44498aea 1634
b1f14ad0 1635 gt_iir = I915_READ(GTIIR);
0e43406b 1636 if (gt_iir) {
d8fc8a47 1637 if (INTEL_INFO(dev)->gen >= 6)
f1af8fc1 1638 snb_gt_irq_handler(dev, dev_priv, gt_iir);
d8fc8a47
PZ		 1639 else
1640 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
0e43406b
CW		 1641 I915_WRITE(GTIIR, gt_iir);
1642 ret = IRQ_HANDLED;
b1f14ad0
JB		 1643 }
1644
0e43406b
CW		 1645 de_iir = I915_READ(DEIIR);
1646 if (de_iir) {
f1af8fc1
PZ		 1647 if (INTEL_INFO(dev)->gen >= 7)
1648 ivb_display_irq_handler(dev, de_iir);
1649 else
1650 ilk_display_irq_handler(dev, de_iir);
0e43406b
CW		 1651 I915_WRITE(DEIIR, de_iir);
1652 ret = IRQ_HANDLED;
b1f14ad0
JB		 1653 }
1654
f1af8fc1
PZ		 1655 if (INTEL_INFO(dev)->gen >= 6) {
1656 u32 pm_iir = I915_READ(GEN6_PMIIR);
1657 if (pm_iir) {
1403c0d4 1658 gen6_rps_irq_handler(dev_priv, pm_iir);
f1af8fc1
PZ		 1659 I915_WRITE(GEN6_PMIIR, pm_iir);
1660 ret = IRQ_HANDLED;
1661 }
0e43406b 1662 }
b1f14ad0 1663
b1f14ad0
JB		 1664 I915_WRITE(DEIER, de_ier);
1665 POSTING_READ(DEIER);
ab5c608b
BW		 1666 if (!HAS_PCH_NOP(dev)) {
1667 I915_WRITE(SDEIER, sde_ier);
1668 POSTING_READ(SDEIER);
1669 }
b1f14ad0
JB		 1670
1671 return ret;
1672}
1673
17e1df07
DV		 1674static void i915_error_wake_up(struct drm_i915_private *dev_priv,
1675 bool reset_completed)
1676{
1677 struct intel_ring_buffer *ring;
1678 int i;
1679
1680 /*
1681 * Notify all waiters for GPU completion events that reset state has
1682 * been changed, and that they need to restart their wait after
1683 * checking for potential errors (and bail out to drop locks if there is
1684 * a gpu reset pending so that i915_error_work_func can acquire them).
1685 */
1686
1687 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
1688 for_each_ring(ring, dev_priv, i)
1689 wake_up_all(&ring->irq_queue);
1690
1691 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
1692 wake_up_all(&dev_priv->pending_flip_queue);
1693
1694 /*
1695 * Signal tasks blocked in i915_gem_wait_for_error that the pending
1696 * reset state is cleared.
1697 */
1698 if (reset_completed)
1699 wake_up_all(&dev_priv->gpu_error.reset_queue);
1700}
1701
8a905236
JB		 1702/**
1703 * i915_error_work_func - do process context error handling work
1704 * @work: work struct
1705 *
1706 * Fire an error uevent so userspace can see that a hang or error
1707 * was detected.
1708 */
1709static void i915_error_work_func(struct work_struct *work)
1710{
1f83fee0
DV		 1711 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
1712 work);
1713 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1714 gpu_error);
8a905236 1715 struct drm_device *dev = dev_priv->dev;
cce723ed
BW		 1716 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1717 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1718 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
17e1df07 1719 int ret;
8a905236 1720
f316a42c
BG		 1721 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
1722
7db0ba24
DV		 1723 /*
1724 * Note that there's only one work item which does gpu resets, so we
1725 * need not worry about concurrent gpu resets potentially incrementing
1726 * error->reset_counter twice. We only need to take care of another
1727 * racing irq/hangcheck declaring the gpu dead for a second time. A
1728 * quick check for that is good enough: schedule_work ensures the
1729 * correct ordering between hang detection and this work item, and since
1730 * the reset in-progress bit is only ever set by code outside of this
1731 * work we don't need to worry about any other races.
1732 */
1733 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
f803aa55 1734 DRM_DEBUG_DRIVER("resetting chip\n");
7db0ba24
DV		 1735 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
1736 reset_event);
1f83fee0 1737
17e1df07
DV		 1738 /*
1739 * All state reset _must_ be completed before we update the
1740 * reset counter, for otherwise waiters might miss the reset
1741 * pending state and not properly drop locks, resulting in
1742 * deadlocks with the reset work.
1743 */
f69061be
DV		 1744 ret = i915_reset(dev);
1745
17e1df07
DV		 1746 intel_display_handle_reset(dev);
1747
f69061be
DV		 1748 if (ret == 0) {
1749 /*
1750 * After all the gem state is reset, increment the reset
1751 * counter and wake up everyone waiting for the reset to
1752 * complete.
1753 *
1754 * Since unlock operations are a one-sided barrier only,
1755 * we need to insert a barrier here to order any seqno
1756 * updates before
1757 * the counter increment.
1758 */
1759 smp_mb__before_atomic_inc();
1760 atomic_inc(&dev_priv->gpu_error.reset_counter);
1761
1762 kobject_uevent_env(&dev->primary->kdev.kobj,
1763 KOBJ_CHANGE, reset_done_event);
1f83fee0
DV		 1764 } else {
1765 atomic_set(&error->reset_counter, I915_WEDGED);
f316a42c 1766 }
1f83fee0 1767
17e1df07
DV		 1768 /*
1769 * Note: The wake_up also serves as a memory barrier so that
1770 * waiters see the update value of the reset counter atomic_t.
1771 */
1772 i915_error_wake_up(dev_priv, true);
f316a42c 1773 }
8a905236
JB		 1774}
1775
35aed2e6 1776static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1777{
1778 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 1779 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 1780 u32 eir = I915_READ(EIR);
050ee91f 1781 int pipe, i;
8a905236 1782
35aed2e6
CW		 1783 if (!eir)
1784 return;
8a905236 1785
a70491cc 1786 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 1787
bd9854f9
BW		 1788 i915_get_extra_instdone(dev, instdone);
1789
8a905236
JB		 1790 if (IS_G4X(dev)) {
1791 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1792 u32 ipeir = I915_READ(IPEIR_I965);
1793
a70491cc
JP		 1794 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1795 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 1796 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1797 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 1798 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1799 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1800 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1801 POSTING_READ(IPEIR_I965);
8a905236
JB		 1802 }
1803 if (eir & GM45_ERROR_PAGE_TABLE) {
1804 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1805 pr_err("page table error\n");
1806 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1807 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1808 POSTING_READ(PGTBL_ER);
8a905236
JB		 1809 }
1810 }
1811
a6c45cf0 1812 if (!IS_GEN2(dev)) {
8a905236
JB		 1813 if (eir & I915_ERROR_PAGE_TABLE) {
1814 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1815 pr_err("page table error\n");
1816 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1817 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1818 POSTING_READ(PGTBL_ER);
8a905236
JB		 1819 }
1820 }
1821
1822 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 1823 pr_err("memory refresh error:\n");
9db4a9c7 1824 for_each_pipe(pipe)
a70491cc 1825 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 1826 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 1827 /* pipestat has already been acked */
1828 }
1829 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 1830 pr_err("instruction error\n");
1831 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 1832 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1833 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 1834 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 1835 u32 ipeir = I915_READ(IPEIR);
1836
a70491cc
JP		 1837 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1838 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 1839 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 1840 I915_WRITE(IPEIR, ipeir);
3143a2bf 1841 POSTING_READ(IPEIR);
8a905236
JB		 1842 } else {
1843 u32 ipeir = I915_READ(IPEIR_I965);
1844
a70491cc
JP		 1845 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1846 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 1847 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1848 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1849 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1850 POSTING_READ(IPEIR_I965);
8a905236
JB		 1851 }
1852 }
1853
1854 I915_WRITE(EIR, eir);
3143a2bf 1855 POSTING_READ(EIR);
8a905236
JB		 1856 eir = I915_READ(EIR);
1857 if (eir) {
1858 /*
1859 * some errors might have become stuck,
1860 * mask them.
1861 */
1862 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1863 I915_WRITE(EMR, I915_READ(EMR) | eir);
1864 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1865 }
35aed2e6
CW		 1866}
1867
1868/**
1869 * i915_handle_error - handle an error interrupt
1870 * @dev: drm device
1871 *
1872 * Do some basic checking of regsiter state at error interrupt time and
1873 * dump it to the syslog. Also call i915_capture_error_state() to make
1874 * sure we get a record and make it available in debugfs. Fire a uevent
1875 * so userspace knows something bad happened (should trigger collection
1876 * of a ring dump etc.).
1877 */
527f9e90 1878void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 1879{
1880 struct drm_i915_private *dev_priv = dev->dev_private;
1881
1882 i915_capture_error_state(dev);
1883 i915_report_and_clear_eir(dev);
8a905236 1884
ba1234d1 1885 if (wedged) {
f69061be
DV		 1886 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
1887 &dev_priv->gpu_error.reset_counter);
ba1234d1 1888
11ed50ec 1889 /*
17e1df07
DV		 1890 * Wakeup waiting processes so that the reset work function
1891 * i915_error_work_func doesn't deadlock trying to grab various
1892 * locks. By bumping the reset counter first, the woken
1893 * processes will see a reset in progress and back off,
1894 * releasing their locks and then wait for the reset completion.
1895 * We must do this for _all_ gpu waiters that might hold locks
1896 * that the reset work needs to acquire.
1897 *
1898 * Note: The wake_up serves as the required memory barrier to
1899 * ensure that the waiters see the updated value of the reset
1900 * counter atomic_t.
11ed50ec 1901 */
17e1df07 1902 i915_error_wake_up(dev_priv, false);
11ed50ec
BG		 1903 }
1904
122f46ba
DV		 1905 /*
1906 * Our reset work can grab modeset locks (since it needs to reset the
1907 * state of outstanding pagelips). Hence it must not be run on our own
1908 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
1909 * code will deadlock.
1910 */
1911 schedule_work(&dev_priv->gpu_error.work);
8a905236
JB		 1912}
1913
21ad8330 1914static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
4e5359cd
SF		 1915{
1916 drm_i915_private_t *dev_priv = dev->dev_private;
1917 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1918 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 1919 struct drm_i915_gem_object *obj;
4e5359cd
SF		 1920 struct intel_unpin_work *work;
1921 unsigned long flags;
1922 bool stall_detected;
1923
1924 /* Ignore early vblank irqs */
1925 if (intel_crtc == NULL)
1926 return;
1927
1928 spin_lock_irqsave(&dev->event_lock, flags);
1929 work = intel_crtc->unpin_work;
1930
e7d841ca
CW		 1931 if (work == NULL ||
1932 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
1933 !work->enable_stall_check) {
4e5359cd
SF		 1934 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1935 spin_unlock_irqrestore(&dev->event_lock, flags);
1936 return;
1937 }
1938
1939 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 1940 obj = work->pending_flip_obj;
a6c45cf0 1941 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 1942 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545 1943 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
f343c5f6 1944 i915_gem_obj_ggtt_offset(obj);
4e5359cd 1945 } else {
9db4a9c7 1946 int dspaddr = DSPADDR(intel_crtc->plane);
f343c5f6 1947 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
01f2c773 1948 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 1949 crtc->x * crtc->fb->bits_per_pixel/8);
1950 }
1951
1952 spin_unlock_irqrestore(&dev->event_lock, flags);
1953
1954 if (stall_detected) {
1955 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1956 intel_prepare_page_flip(dev, intel_crtc->plane);
1957 }
1958}
1959
42f52ef8
KP		 1960/* Called from drm generic code, passed 'crtc' which
1961 * we use as a pipe index
1962 */
f71d4af4 1963static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1964{
1965 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1966 unsigned long irqflags;
71e0ffa5 1967
5eddb70b 1968 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 1969 return -EINVAL;
0a3e67a4 1970
1ec14ad3 1971 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 1972 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 1973 i915_enable_pipestat(dev_priv, pipe,
1974 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 1975 else
7c463586
KP		 1976 i915_enable_pipestat(dev_priv, pipe,
1977 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 1978
1979 /* maintain vblank delivery even in deep C-states */
1980 if (dev_priv->info->gen == 3)
6b26c86d 1981 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 1982 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 1983
0a3e67a4
JB		 1984 return 0;
1985}
1986
f71d4af4 1987static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1988{
1989 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1990 unsigned long irqflags;
b518421f
PZ		 1991 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
1992 DE_PIPE_VBLANK_ILK(pipe);
f796cf8f
JB		 1993
1994 if (!i915_pipe_enabled(dev, pipe))
1995 return -EINVAL;
1996
1997 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b518421f 1998 ironlake_enable_display_irq(dev_priv, bit);
b1f14ad0
JB		 1999 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2000
2001 return 0;
2002}
2003
7e231dbe
JB		 2004static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2005{
2006 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2007 unsigned long irqflags;
31acc7f5 2008 u32 imr;
7e231dbe
JB		 2009
2010 if (!i915_pipe_enabled(dev, pipe))
2011 return -EINVAL;
2012
2013 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7e231dbe 2014 imr = I915_READ(VLV_IMR);
31acc7f5 2015 if (pipe == 0)
7e231dbe 2016 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 2017 else
7e231dbe 2018 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2019 I915_WRITE(VLV_IMR, imr);
31acc7f5
JB		 2020 i915_enable_pipestat(dev_priv, pipe,
2021 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe
JB		 2022 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2023
2024 return 0;
2025}
2026
42f52ef8
KP		 2027/* Called from drm generic code, passed 'crtc' which
2028 * we use as a pipe index
2029 */
f71d4af4 2030static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 2031{
2032 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 2033 unsigned long irqflags;
0a3e67a4 2034
1ec14ad3 2035 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 2036 if (dev_priv->info->gen == 3)
6b26c86d 2037 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 2038
f796cf8f
JB		 2039 i915_disable_pipestat(dev_priv, pipe,
2040 PIPE_VBLANK_INTERRUPT_ENABLE |
2041 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2042 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2043}
2044
f71d4af4 2045static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 2046{
2047 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2048 unsigned long irqflags;
b518421f
PZ		 2049 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2050 DE_PIPE_VBLANK_ILK(pipe);
f796cf8f
JB		 2051
2052 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b518421f 2053 ironlake_disable_display_irq(dev_priv, bit);
b1f14ad0
JB		 2054 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2055}
2056
7e231dbe
JB		 2057static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2058{
2059 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2060 unsigned long irqflags;
31acc7f5 2061 u32 imr;
7e231dbe
JB		 2062
2063 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5
JB		 2064 i915_disable_pipestat(dev_priv, pipe,
2065 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe 2066 imr = I915_READ(VLV_IMR);
31acc7f5 2067 if (pipe == 0)
7e231dbe 2068 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 2069 else
7e231dbe 2070 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2071 I915_WRITE(VLV_IMR, imr);
7e231dbe
JB		 2072 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2073}
2074
893eead0
CW		 2075static u32
2076ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 2077{
893eead0
CW		 2078 return list_entry(ring->request_list.prev,
2079 struct drm_i915_gem_request, list)->seqno;
2080}
2081
9107e9d2
CW		 2082static bool
2083ring_idle(struct intel_ring_buffer *ring, u32 seqno)
2084{
2085 return (list_empty(&ring->request_list) ||
2086 i915_seqno_passed(seqno, ring_last_seqno(ring)));
f65d9421
BG		 2087}
2088
6274f212
CW		 2089static struct intel_ring_buffer *
2090semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
a24a11e6
CW		 2091{
2092 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6274f212 2093 u32 cmd, ipehr, acthd, acthd_min;
a24a11e6
CW		 2094
2095 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2096 if ((ipehr & ~(0x3 << 16)) !=
2097 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
6274f212 2098 return NULL;
a24a11e6
CW		 2099
2100 /* ACTHD is likely pointing to the dword after the actual command,
2101 * so scan backwards until we find the MBOX.
2102 */
6274f212 2103 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
a24a11e6
CW		 2104 acthd_min = max((int)acthd - 3 * 4, 0);
2105 do {
2106 cmd = ioread32(ring->virtual_start + acthd);
2107 if (cmd == ipehr)
2108 break;
2109
2110 acthd -= 4;
2111 if (acthd < acthd_min)
6274f212 2112 return NULL;
a24a11e6
CW		 2113 } while (1);
2114
6274f212
CW		 2115 *seqno = ioread32(ring->virtual_start+acthd+4)+1;
2116 return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
a24a11e6
CW		 2117}
2118
6274f212
CW		 2119static int semaphore_passed(struct intel_ring_buffer *ring)
2120{
2121 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2122 struct intel_ring_buffer *signaller;
2123 u32 seqno, ctl;
2124
2125 ring->hangcheck.deadlock = true;
2126
2127 signaller = semaphore_waits_for(ring, &seqno);
2128 if (signaller == NULL || signaller->hangcheck.deadlock)
2129 return -1;
2130
2131 /* cursory check for an unkickable deadlock */
2132 ctl = I915_READ_CTL(signaller);
2133 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2134 return -1;
2135
2136 return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2137}
2138
2139static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2140{
2141 struct intel_ring_buffer *ring;
2142 int i;
2143
2144 for_each_ring(ring, dev_priv, i)
2145 ring->hangcheck.deadlock = false;
2146}
2147
ad8beaea
MK		 2148static enum intel_ring_hangcheck_action
2149ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
1ec14ad3
CW		 2150{
2151 struct drm_device *dev = ring->dev;
2152 struct drm_i915_private *dev_priv = dev->dev_private;
9107e9d2
CW		 2153 u32 tmp;
2154
6274f212 2155 if (ring->hangcheck.acthd != acthd)
f2f4d82f 2156 return HANGCHECK_ACTIVE;
6274f212 2157
9107e9d2 2158 if (IS_GEN2(dev))
f2f4d82f 2159 return HANGCHECK_HUNG;
9107e9d2
CW		 2160
2161 /* Is the chip hanging on a WAIT_FOR_EVENT?
2162 * If so we can simply poke the RB_WAIT bit
2163 * and break the hang. This should work on
2164 * all but the second generation chipsets.
2165 */
2166 tmp = I915_READ_CTL(ring);
1ec14ad3
CW		 2167 if (tmp & RING_WAIT) {
2168 DRM_ERROR("Kicking stuck wait on %s\n",
2169 ring->name);
09e14bf3 2170 i915_handle_error(dev, false);
1ec14ad3 2171 I915_WRITE_CTL(ring, tmp);
f2f4d82f 2172 return HANGCHECK_KICK;
6274f212
CW		 2173 }
2174
2175 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2176 switch (semaphore_passed(ring)) {
2177 default:
f2f4d82f 2178 return HANGCHECK_HUNG;
6274f212
CW		 2179 case 1:
2180 DRM_ERROR("Kicking stuck semaphore on %s\n",
2181 ring->name);
09e14bf3 2182 i915_handle_error(dev, false);
6274f212 2183 I915_WRITE_CTL(ring, tmp);
f2f4d82f 2184 return HANGCHECK_KICK;
6274f212 2185 case 0:
f2f4d82f 2186 return HANGCHECK_WAIT;
6274f212 2187 }
9107e9d2 2188 }
ed5cbb03 2189
f2f4d82f 2190 return HANGCHECK_HUNG;
ed5cbb03
MK		 2191}
2192
f65d9421
BG		 2193/**
2194 * This is called when the chip hasn't reported back with completed
05407ff8
MK		 2195 * batchbuffers in a long time. We keep track per ring seqno progress and
2196 * if there are no progress, hangcheck score for that ring is increased.
2197 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2198 * we kick the ring. If we see no progress on three subsequent calls
2199 * we assume chip is wedged and try to fix it by resetting the chip.
f65d9421 2200 */
a658b5d2 2201static void i915_hangcheck_elapsed(unsigned long data)
f65d9421
BG		 2202{
2203 struct drm_device *dev = (struct drm_device *)data;
2204 drm_i915_private_t *dev_priv = dev->dev_private;
b4519513 2205 struct intel_ring_buffer *ring;
b4519513 2206 int i;
05407ff8 2207 int busy_count = 0, rings_hung = 0;
9107e9d2
CW		 2208 bool stuck[I915_NUM_RINGS] = { 0 };
2209#define BUSY 1
2210#define KICK 5
2211#define HUNG 20
2212#define FIRE 30
893eead0 2213
3e0dc6b0
BW		 2214 if (!i915_enable_hangcheck)
2215 return;
2216
b4519513 2217 for_each_ring(ring, dev_priv, i) {
05407ff8 2218 u32 seqno, acthd;
9107e9d2 2219 bool busy = true;
05407ff8 2220
6274f212
CW		 2221 semaphore_clear_deadlocks(dev_priv);
2222
05407ff8
MK		 2223 seqno = ring->get_seqno(ring, false);
2224 acthd = intel_ring_get_active_head(ring);
b4519513 2225
9107e9d2
CW		 2226 if (ring->hangcheck.seqno == seqno) {
2227 if (ring_idle(ring, seqno)) {
da661464
MK		 2228 ring->hangcheck.action = HANGCHECK_IDLE;
2229
9107e9d2
CW		 2230 if (waitqueue_active(&ring->irq_queue)) {
2231 /* Issue a wake-up to catch stuck h/w. */
094f9a54
CW		 2232 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2233 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2234 ring->name);
2235 wake_up_all(&ring->irq_queue);
2236 }
2237 /* Safeguard against driver failure */
2238 ring->hangcheck.score += BUSY;
9107e9d2
CW		 2239 } else
2240 busy = false;
05407ff8 2241 } else {
6274f212
CW		 2242 /* We always increment the hangcheck score
2243 * if the ring is busy and still processing
2244 * the same request, so that no single request
2245 * can run indefinitely (such as a chain of
2246 * batches). The only time we do not increment
2247 * the hangcheck score on this ring, if this
2248 * ring is in a legitimate wait for another
2249 * ring. In that case the waiting ring is a
2250 * victim and we want to be sure we catch the
2251 * right culprit. Then every time we do kick
2252 * the ring, add a small increment to the
2253 * score so that we can catch a batch that is
2254 * being repeatedly kicked and so responsible
2255 * for stalling the machine.
2256 */
ad8beaea
MK		 2257 ring->hangcheck.action = ring_stuck(ring,
2258 acthd);
2259
2260 switch (ring->hangcheck.action) {
da661464 2261 case HANGCHECK_IDLE:
f2f4d82f 2262 case HANGCHECK_WAIT:
6274f212 2263 break;
f2f4d82f 2264 case HANGCHECK_ACTIVE:
ea04cb31 2265 ring->hangcheck.score += BUSY;
6274f212 2266 break;
f2f4d82f 2267 case HANGCHECK_KICK:
ea04cb31 2268 ring->hangcheck.score += KICK;
6274f212 2269 break;
f2f4d82f 2270 case HANGCHECK_HUNG:
ea04cb31 2271 ring->hangcheck.score += HUNG;
6274f212
CW		 2272 stuck[i] = true;
2273 break;
2274 }
05407ff8 2275 }
9107e9d2 2276 } else {
da661464
MK		 2277 ring->hangcheck.action = HANGCHECK_ACTIVE;
2278
9107e9d2
CW		 2279 /* Gradually reduce the count so that we catch DoS
2280 * attempts across multiple batches.
2281 */
2282 if (ring->hangcheck.score > 0)
2283 ring->hangcheck.score--;
d1e61e7f
CW		 2284 }
2285
05407ff8
MK		 2286 ring->hangcheck.seqno = seqno;
2287 ring->hangcheck.acthd = acthd;
9107e9d2 2288 busy_count += busy;
893eead0 2289 }
b9201c14 2290
92cab734 2291 for_each_ring(ring, dev_priv, i) {
9107e9d2 2292 if (ring->hangcheck.score > FIRE) {
b8d88d1d
DV		 2293 DRM_INFO("%s on %s\n",
2294 stuck[i] ? "stuck" : "no progress",
2295 ring->name);
a43adf07 2296 rings_hung++;
92cab734
MK		 2297 }
2298 }
2299
05407ff8
MK		 2300 if (rings_hung)
2301 return i915_handle_error(dev, true);
f65d9421 2302
05407ff8
MK		 2303 if (busy_count)
2304 /* Reset timer case chip hangs without another request
2305 * being added */
10cd45b6
MK		 2306 i915_queue_hangcheck(dev);
2307}
2308
2309void i915_queue_hangcheck(struct drm_device *dev)
2310{
2311 struct drm_i915_private *dev_priv = dev->dev_private;
2312 if (!i915_enable_hangcheck)
2313 return;
2314
2315 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2316 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
f65d9421
BG		 2317}
2318
91738a95
PZ		 2319static void ibx_irq_preinstall(struct drm_device *dev)
2320{
2321 struct drm_i915_private *dev_priv = dev->dev_private;
2322
2323 if (HAS_PCH_NOP(dev))
2324 return;
2325
2326 /* south display irq */
2327 I915_WRITE(SDEIMR, 0xffffffff);
2328 /*
2329 * SDEIER is also touched by the interrupt handler to work around missed
2330 * PCH interrupts. Hence we can't update it after the interrupt handler
2331 * is enabled - instead we unconditionally enable all PCH interrupt
2332 * sources here, but then only unmask them as needed with SDEIMR.
2333 */
2334 I915_WRITE(SDEIER, 0xffffffff);
2335 POSTING_READ(SDEIER);
2336}
2337
d18ea1b5
DV		 2338static void gen5_gt_irq_preinstall(struct drm_device *dev)
2339{
2340 struct drm_i915_private *dev_priv = dev->dev_private;
2341
2342 /* and GT */
2343 I915_WRITE(GTIMR, 0xffffffff);
2344 I915_WRITE(GTIER, 0x0);
2345 POSTING_READ(GTIER);
2346
2347 if (INTEL_INFO(dev)->gen >= 6) {
2348 /* and PM */
2349 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2350 I915_WRITE(GEN6_PMIER, 0x0);
2351 POSTING_READ(GEN6_PMIER);
2352 }
2353}
2354
1da177e4
LT		 2355/* drm_dma.h hooks
2356*/
f71d4af4 2357static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 2358{
2359 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2360
4697995b
JB		 2361 atomic_set(&dev_priv->irq_received, 0);
2362
036a4a7d 2363 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 2364
036a4a7d
ZW		 2365 I915_WRITE(DEIMR, 0xffffffff);
2366 I915_WRITE(DEIER, 0x0);
3143a2bf 2367 POSTING_READ(DEIER);
036a4a7d 2368
d18ea1b5 2369 gen5_gt_irq_preinstall(dev);
c650156a 2370
91738a95 2371 ibx_irq_preinstall(dev);
7d99163d
BW		 2372}
2373
7e231dbe
JB		 2374static void valleyview_irq_preinstall(struct drm_device *dev)
2375{
2376 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2377 int pipe;
2378
2379 atomic_set(&dev_priv->irq_received, 0);
2380
7e231dbe
JB		 2381 /* VLV magic */
2382 I915_WRITE(VLV_IMR, 0);
2383 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2384 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2385 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2386
7e231dbe
JB		 2387 /* and GT */
2388 I915_WRITE(GTIIR, I915_READ(GTIIR));
2389 I915_WRITE(GTIIR, I915_READ(GTIIR));
d18ea1b5
DV		 2390
2391 gen5_gt_irq_preinstall(dev);
7e231dbe
JB		 2392
2393 I915_WRITE(DPINVGTT, 0xff);
2394
2395 I915_WRITE(PORT_HOTPLUG_EN, 0);
2396 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2397 for_each_pipe(pipe)
2398 I915_WRITE(PIPESTAT(pipe), 0xffff);
2399 I915_WRITE(VLV_IIR, 0xffffffff);
2400 I915_WRITE(VLV_IMR, 0xffffffff);
2401 I915_WRITE(VLV_IER, 0x0);
2402 POSTING_READ(VLV_IER);
2403}
2404
82a28bcf 2405static void ibx_hpd_irq_setup(struct drm_device *dev)
7fe0b973
KP		 2406{
2407 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82a28bcf
DV		 2408 struct drm_mode_config *mode_config = &dev->mode_config;
2409 struct intel_encoder *intel_encoder;
fee884ed 2410 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
82a28bcf
DV		 2411
2412 if (HAS_PCH_IBX(dev)) {
fee884ed 2413 hotplug_irqs = SDE_HOTPLUG_MASK;
82a28bcf 2414 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed 2415 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
fee884ed 2416 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
82a28bcf 2417 } else {
fee884ed 2418 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
82a28bcf 2419 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed 2420 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
fee884ed 2421 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
82a28bcf 2422 }
7fe0b973 2423
fee884ed 2424 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
82a28bcf
DV		 2425
2426 /*
2427 * Enable digital hotplug on the PCH, and configure the DP short pulse
2428 * duration to 2ms (which is the minimum in the Display Port spec)
2429 *
2430 * This register is the same on all known PCH chips.
2431 */
7fe0b973
KP		 2432 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2433 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2434 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2435 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2436 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2437 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2438}
2439
d46da437
PZ		 2440static void ibx_irq_postinstall(struct drm_device *dev)
2441{
2442 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82a28bcf 2443 u32 mask;
e5868a31 2444
692a04cf
DV		 2445 if (HAS_PCH_NOP(dev))
2446 return;
2447
8664281b
PZ		 2448 if (HAS_PCH_IBX(dev)) {
2449 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
de032bf4 2450 SDE_TRANSA_FIFO_UNDER | SDE_POISON;
8664281b
PZ		 2451 } else {
2452 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2453
2454 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2455 }
ab5c608b 2456
d46da437
PZ		 2457 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2458 I915_WRITE(SDEIMR, ~mask);
d46da437
PZ		 2459}
2460
0a9a8c91
DV		 2461static void gen5_gt_irq_postinstall(struct drm_device *dev)
2462{
2463 struct drm_i915_private *dev_priv = dev->dev_private;
2464 u32 pm_irqs, gt_irqs;
2465
2466 pm_irqs = gt_irqs = 0;
2467
2468 dev_priv->gt_irq_mask = ~0;
040d2baa 2469 if (HAS_L3_DPF(dev)) {
0a9a8c91 2470 /* L3 parity interrupt is always unmasked. */
35a85ac6
BW		 2471 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
2472 gt_irqs |= GT_PARITY_ERROR(dev);
0a9a8c91
DV		 2473 }
2474
2475 gt_irqs |= GT_RENDER_USER_INTERRUPT;
2476 if (IS_GEN5(dev)) {
2477 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2478 ILK_BSD_USER_INTERRUPT;
2479 } else {
2480 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
2481 }
2482
2483 I915_WRITE(GTIIR, I915_READ(GTIIR));
2484 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2485 I915_WRITE(GTIER, gt_irqs);
2486 POSTING_READ(GTIER);
2487
2488 if (INTEL_INFO(dev)->gen >= 6) {
2489 pm_irqs |= GEN6_PM_RPS_EVENTS;
2490
2491 if (HAS_VEBOX(dev))
2492 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
2493
605cd25b 2494 dev_priv->pm_irq_mask = 0xffffffff;
0a9a8c91 2495 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
605cd25b 2496 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
0a9a8c91
DV		 2497 I915_WRITE(GEN6_PMIER, pm_irqs);
2498 POSTING_READ(GEN6_PMIER);
2499 }
2500}
2501
f71d4af4 2502static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d 2503{
4bc9d430 2504 unsigned long irqflags;
036a4a7d 2505 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8e76f8dc
PZ		 2506 u32 display_mask, extra_mask;
2507
2508 if (INTEL_INFO(dev)->gen >= 7) {
2509 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
2510 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
2511 DE_PLANEB_FLIP_DONE_IVB |
2512 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB |
2513 DE_ERR_INT_IVB);
2514 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
2515 DE_PIPEA_VBLANK_IVB);
2516
2517 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2518 } else {
2519 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2520 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
5b3a856b
DV		 2521 DE_AUX_CHANNEL_A |
2522 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
2523 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
2524 DE_POISON);
8e76f8dc
PZ		 2525 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT;
2526 }
036a4a7d 2527
1ec14ad3 2528 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 2529
2530 /* should always can generate irq */
2531 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3 2532 I915_WRITE(DEIMR, dev_priv->irq_mask);
8e76f8dc 2533 I915_WRITE(DEIER, display_mask | extra_mask);
3143a2bf 2534 POSTING_READ(DEIER);
036a4a7d 2535
0a9a8c91 2536 gen5_gt_irq_postinstall(dev);
036a4a7d 2537
d46da437 2538 ibx_irq_postinstall(dev);
7fe0b973 2539
f97108d1 2540 if (IS_IRONLAKE_M(dev)) {
6005ce42
DV		 2541 /* Enable PCU event interrupts
2542 *
2543 * spinlocking not required here for correctness since interrupt
4bc9d430
DV		 2544 * setup is guaranteed to run in single-threaded context. But we
2545 * need it to make the assert_spin_locked happy. */
2546 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f97108d1 2547 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
4bc9d430 2548 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
f97108d1
JB		 2549 }
2550
036a4a7d
ZW		 2551 return 0;
2552}
2553
7e231dbe
JB		 2554static int valleyview_irq_postinstall(struct drm_device *dev)
2555{
2556 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7e231dbe 2557 u32 enable_mask;
31acc7f5 2558 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
b79480ba 2559 unsigned long irqflags;
7e231dbe
JB		 2560
2561 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
31acc7f5
JB		 2562 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2563 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2564 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
7e231dbe
JB		 2565 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2566
31acc7f5
JB		 2567 /*
2568 *Leave vblank interrupts masked initially. enable/disable will
2569 * toggle them based on usage.
2570 */
2571 dev_priv->irq_mask = (~enable_mask) |
2572 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2573 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2574
20afbda2
DV		 2575 I915_WRITE(PORT_HOTPLUG_EN, 0);
2576 POSTING_READ(PORT_HOTPLUG_EN);
2577
7e231dbe
JB		 2578 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2579 I915_WRITE(VLV_IER, enable_mask);
2580 I915_WRITE(VLV_IIR, 0xffffffff);
2581 I915_WRITE(PIPESTAT(0), 0xffff);
2582 I915_WRITE(PIPESTAT(1), 0xffff);
2583 POSTING_READ(VLV_IER);
2584
b79480ba
DV		 2585 /* Interrupt setup is already guaranteed to be single-threaded, this is
2586 * just to make the assert_spin_locked check happy. */
2587 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5 2588 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
515ac2bb 2589 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
31acc7f5 2590 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
b79480ba 2591 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
31acc7f5 2592
7e231dbe
JB		 2593 I915_WRITE(VLV_IIR, 0xffffffff);
2594 I915_WRITE(VLV_IIR, 0xffffffff);
2595
0a9a8c91 2596 gen5_gt_irq_postinstall(dev);
7e231dbe
JB		 2597
2598 /* ack & enable invalid PTE error interrupts */
2599#if 0 /* FIXME: add support to irq handler for checking these bits */
2600 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2601 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2602#endif
2603
2604 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
20afbda2
DV		 2605
2606 return 0;
2607}
2608
7e231dbe
JB		 2609static void valleyview_irq_uninstall(struct drm_device *dev)
2610{
2611 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2612 int pipe;
2613
2614 if (!dev_priv)
2615 return;
2616
ac4c16c5
EE		 2617 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2618
7e231dbe
JB		 2619 for_each_pipe(pipe)
2620 I915_WRITE(PIPESTAT(pipe), 0xffff);
2621
2622 I915_WRITE(HWSTAM, 0xffffffff);
2623 I915_WRITE(PORT_HOTPLUG_EN, 0);
2624 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2625 for_each_pipe(pipe)
2626 I915_WRITE(PIPESTAT(pipe), 0xffff);
2627 I915_WRITE(VLV_IIR, 0xffffffff);
2628 I915_WRITE(VLV_IMR, 0xffffffff);
2629 I915_WRITE(VLV_IER, 0x0);
2630 POSTING_READ(VLV_IER);
2631}
2632
f71d4af4 2633static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 2634{
2635 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 2636
2637 if (!dev_priv)
2638 return;
2639
ac4c16c5
EE		 2640 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2641
036a4a7d
ZW		 2642 I915_WRITE(HWSTAM, 0xffffffff);
2643
2644 I915_WRITE(DEIMR, 0xffffffff);
2645 I915_WRITE(DEIER, 0x0);
2646 I915_WRITE(DEIIR, I915_READ(DEIIR));
8664281b
PZ		 2647 if (IS_GEN7(dev))
2648 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
036a4a7d
ZW		 2649
2650 I915_WRITE(GTIMR, 0xffffffff);
2651 I915_WRITE(GTIER, 0x0);
2652 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f 2653
ab5c608b
BW		 2654 if (HAS_PCH_NOP(dev))
2655 return;
2656
192aac1f
KP		 2657 I915_WRITE(SDEIMR, 0xffffffff);
2658 I915_WRITE(SDEIER, 0x0);
2659 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
8664281b
PZ		 2660 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
2661 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
036a4a7d
ZW		 2662}
2663
a266c7d5 2664static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 2665{
2666 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2667 int pipe;
91e3738e 2668
a266c7d5 2669 atomic_set(&dev_priv->irq_received, 0);
5ca58282 2670
9db4a9c7
JB		 2671 for_each_pipe(pipe)
2672 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 2673 I915_WRITE16(IMR, 0xffff);
2674 I915_WRITE16(IER, 0x0);
2675 POSTING_READ16(IER);
c2798b19
CW		 2676}
2677
2678static int i8xx_irq_postinstall(struct drm_device *dev)
2679{
2680 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2681
c2798b19
CW		 2682 I915_WRITE16(EMR,
2683 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2684
2685 /* Unmask the interrupts that we always want on. */
2686 dev_priv->irq_mask =
2687 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2688 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2689 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2690 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2691 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2692 I915_WRITE16(IMR, dev_priv->irq_mask);
2693
2694 I915_WRITE16(IER,
2695 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2696 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2697 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2698 I915_USER_INTERRUPT);
2699 POSTING_READ16(IER);
2700
2701 return 0;
2702}
2703
90a72f87
VS		 2704/*
2705 * Returns true when a page flip has completed.
2706 */
2707static bool i8xx_handle_vblank(struct drm_device *dev,
2708 int pipe, u16 iir)
2709{
2710 drm_i915_private_t *dev_priv = dev->dev_private;
2711 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
2712
2713 if (!drm_handle_vblank(dev, pipe))
2714 return false;
2715
2716 if ((iir & flip_pending) == 0)
2717 return false;
2718
2719 intel_prepare_page_flip(dev, pipe);
2720
2721 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2722 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2723 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2724 * the flip is completed (no longer pending). Since this doesn't raise
2725 * an interrupt per se, we watch for the change at vblank.
2726 */
2727 if (I915_READ16(ISR) & flip_pending)
2728 return false;
2729
2730 intel_finish_page_flip(dev, pipe);
2731
2732 return true;
2733}
2734
ff1f525e 2735static irqreturn_t i8xx_irq_handler(int irq, void *arg)
c2798b19
CW		 2736{
2737 struct drm_device *dev = (struct drm_device *) arg;
2738 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 2739 u16 iir, new_iir;
2740 u32 pipe_stats[2];
2741 unsigned long irqflags;
c2798b19
CW		 2742 int pipe;
2743 u16 flip_mask =
2744 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2745 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2746
2747 atomic_inc(&dev_priv->irq_received);
2748
2749 iir = I915_READ16(IIR);
2750 if (iir == 0)
2751 return IRQ_NONE;
2752
2753 while (iir & ~flip_mask) {
2754 /* Can't rely on pipestat interrupt bit in iir as it might
2755 * have been cleared after the pipestat interrupt was received.
2756 * It doesn't set the bit in iir again, but it still produces
2757 * interrupts (for non-MSI).
2758 */
2759 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2760 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2761 i915_handle_error(dev, false);
2762
2763 for_each_pipe(pipe) {
2764 int reg = PIPESTAT(pipe);
2765 pipe_stats[pipe] = I915_READ(reg);
2766
2767 /*
2768 * Clear the PIPE*STAT regs before the IIR
2769 */
2770 if (pipe_stats[pipe] & 0x8000ffff) {
2771 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2772 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2773 pipe_name(pipe));
2774 I915_WRITE(reg, pipe_stats[pipe]);
c2798b19
CW		 2775 }
2776 }
2777 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2778
2779 I915_WRITE16(IIR, iir & ~flip_mask);
2780 new_iir = I915_READ16(IIR); /* Flush posted writes */
2781
d05c617e 2782 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 2783
2784 if (iir & I915_USER_INTERRUPT)
2785 notify_ring(dev, &dev_priv->ring[RCS]);
2786
2787 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2788 i8xx_handle_vblank(dev, 0, iir))
2789 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
c2798b19
CW		 2790
2791 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2792 i8xx_handle_vblank(dev, 1, iir))
2793 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
c2798b19
CW		 2794
2795 iir = new_iir;
2796 }
2797
2798 return IRQ_HANDLED;
2799}
2800
2801static void i8xx_irq_uninstall(struct drm_device * dev)
2802{
2803 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2804 int pipe;
2805
c2798b19
CW		 2806 for_each_pipe(pipe) {
2807 /* Clear enable bits; then clear status bits */
2808 I915_WRITE(PIPESTAT(pipe), 0);
2809 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2810 }
2811 I915_WRITE16(IMR, 0xffff);
2812 I915_WRITE16(IER, 0x0);
2813 I915_WRITE16(IIR, I915_READ16(IIR));
2814}
2815
a266c7d5
CW		 2816static void i915_irq_preinstall(struct drm_device * dev)
2817{
2818 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2819 int pipe;
2820
2821 atomic_set(&dev_priv->irq_received, 0);
2822
2823 if (I915_HAS_HOTPLUG(dev)) {
2824 I915_WRITE(PORT_HOTPLUG_EN, 0);
2825 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2826 }
2827
00d98ebd 2828 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 2829 for_each_pipe(pipe)
2830 I915_WRITE(PIPESTAT(pipe), 0);
2831 I915_WRITE(IMR, 0xffffffff);
2832 I915_WRITE(IER, 0x0);
2833 POSTING_READ(IER);
2834}
2835
2836static int i915_irq_postinstall(struct drm_device *dev)
2837{
2838 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 2839 u32 enable_mask;
a266c7d5 2840
38bde180
CW		 2841 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2842
2843 /* Unmask the interrupts that we always want on. */
2844 dev_priv->irq_mask =
2845 ~(I915_ASLE_INTERRUPT |
2846 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2847 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2848 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2849 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2850 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2851
2852 enable_mask =
2853 I915_ASLE_INTERRUPT |
2854 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2855 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2856 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2857 I915_USER_INTERRUPT;
2858
a266c7d5 2859 if (I915_HAS_HOTPLUG(dev)) {
20afbda2
DV		 2860 I915_WRITE(PORT_HOTPLUG_EN, 0);
2861 POSTING_READ(PORT_HOTPLUG_EN);
2862
a266c7d5
CW		 2863 /* Enable in IER... */
2864 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2865 /* and unmask in IMR */
2866 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2867 }
2868
a266c7d5
CW		 2869 I915_WRITE(IMR, dev_priv->irq_mask);
2870 I915_WRITE(IER, enable_mask);
2871 POSTING_READ(IER);
2872
f49e38dd 2873 i915_enable_asle_pipestat(dev);
20afbda2
DV		 2874
2875 return 0;
2876}
2877
90a72f87
VS		 2878/*
2879 * Returns true when a page flip has completed.
2880 */
2881static bool i915_handle_vblank(struct drm_device *dev,
2882 int plane, int pipe, u32 iir)
2883{
2884 drm_i915_private_t *dev_priv = dev->dev_private;
2885 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
2886
2887 if (!drm_handle_vblank(dev, pipe))
2888 return false;
2889
2890 if ((iir & flip_pending) == 0)
2891 return false;
2892
2893 intel_prepare_page_flip(dev, plane);
2894
2895 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2896 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2897 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2898 * the flip is completed (no longer pending). Since this doesn't raise
2899 * an interrupt per se, we watch for the change at vblank.
2900 */
2901 if (I915_READ(ISR) & flip_pending)
2902 return false;
2903
2904 intel_finish_page_flip(dev, pipe);
2905
2906 return true;
2907}
2908
ff1f525e 2909static irqreturn_t i915_irq_handler(int irq, void *arg)
a266c7d5
CW		 2910{
2911 struct drm_device *dev = (struct drm_device *) arg;
2912 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 2913 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 2914 unsigned long irqflags;
38bde180
CW		 2915 u32 flip_mask =
2916 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2917 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
38bde180 2918 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 2919
2920 atomic_inc(&dev_priv->irq_received);
2921
2922 iir = I915_READ(IIR);
38bde180
CW		 2923 do {
2924 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 2925 bool blc_event = false;
a266c7d5
CW		 2926
2927 /* Can't rely on pipestat interrupt bit in iir as it might
2928 * have been cleared after the pipestat interrupt was received.
2929 * It doesn't set the bit in iir again, but it still produces
2930 * interrupts (for non-MSI).
2931 */
2932 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2933 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2934 i915_handle_error(dev, false);
2935
2936 for_each_pipe(pipe) {
2937 int reg = PIPESTAT(pipe);
2938 pipe_stats[pipe] = I915_READ(reg);
2939
38bde180 2940 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 2941 if (pipe_stats[pipe] & 0x8000ffff) {
2942 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2943 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2944 pipe_name(pipe));
2945 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 2946 irq_received = true;
a266c7d5
CW		 2947 }
2948 }
2949 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2950
2951 if (!irq_received)
2952 break;
2953
a266c7d5
CW		 2954 /* Consume port. Then clear IIR or we'll miss events */
2955 if ((I915_HAS_HOTPLUG(dev)) &&
2956 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2957 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04 2958 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
a266c7d5
CW		 2959
2960 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2961 hotplug_status);
91d131d2
DV		 2962
2963 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
2964
a266c7d5 2965 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 2966 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 2967 }
2968
38bde180 2969 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2970 new_iir = I915_READ(IIR); /* Flush posted writes */
2971
a266c7d5
CW		 2972 if (iir & I915_USER_INTERRUPT)
2973 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 2974
a266c7d5 2975 for_each_pipe(pipe) {
38bde180
CW		 2976 int plane = pipe;
2977 if (IS_MOBILE(dev))
2978 plane = !plane;
90a72f87 2979
8291ee90 2980 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2981 i915_handle_vblank(dev, plane, pipe, iir))
2982 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
a266c7d5
CW		 2983
2984 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2985 blc_event = true;
2986 }
2987
a266c7d5
CW		 2988 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2989 intel_opregion_asle_intr(dev);
2990
2991 /* With MSI, interrupts are only generated when iir
2992 * transitions from zero to nonzero. If another bit got
2993 * set while we were handling the existing iir bits, then
2994 * we would never get another interrupt.
2995 *
2996 * This is fine on non-MSI as well, as if we hit this path
2997 * we avoid exiting the interrupt handler only to generate
2998 * another one.
2999 *
3000 * Note that for MSI this could cause a stray interrupt report
3001 * if an interrupt landed in the time between writing IIR and
3002 * the posting read. This should be rare enough to never
3003 * trigger the 99% of 100,000 interrupts test for disabling
3004 * stray interrupts.
3005 */
38bde180 3006 ret = IRQ_HANDLED;
a266c7d5 3007 iir = new_iir;
38bde180 3008 } while (iir & ~flip_mask);
a266c7d5 3009
d05c617e 3010 i915_update_dri1_breadcrumb(dev);
8291ee90 3011
a266c7d5
CW		 3012 return ret;
3013}
3014
3015static void i915_irq_uninstall(struct drm_device * dev)
3016{
3017 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3018 int pipe;
3019
ac4c16c5
EE		 3020 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3021
a266c7d5
CW		 3022 if (I915_HAS_HOTPLUG(dev)) {
3023 I915_WRITE(PORT_HOTPLUG_EN, 0);
3024 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3025 }
3026
00d98ebd 3027 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 3028 for_each_pipe(pipe) {
3029 /* Clear enable bits; then clear status bits */
a266c7d5 3030 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 3031 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3032 }
a266c7d5
CW		 3033 I915_WRITE(IMR, 0xffffffff);
3034 I915_WRITE(IER, 0x0);
3035
a266c7d5
CW		 3036 I915_WRITE(IIR, I915_READ(IIR));
3037}
3038
3039static void i965_irq_preinstall(struct drm_device * dev)
3040{
3041 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3042 int pipe;
3043
3044 atomic_set(&dev_priv->irq_received, 0);
3045
adca4730
CW		 3046 I915_WRITE(PORT_HOTPLUG_EN, 0);
3047 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 3048
3049 I915_WRITE(HWSTAM, 0xeffe);
3050 for_each_pipe(pipe)
3051 I915_WRITE(PIPESTAT(pipe), 0);
3052 I915_WRITE(IMR, 0xffffffff);
3053 I915_WRITE(IER, 0x0);
3054 POSTING_READ(IER);
3055}
3056
3057static int i965_irq_postinstall(struct drm_device *dev)
3058{
3059 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
bbba0a97 3060 u32 enable_mask;
a266c7d5 3061 u32 error_mask;
b79480ba 3062 unsigned long irqflags;
a266c7d5 3063
a266c7d5 3064 /* Unmask the interrupts that we always want on. */
bbba0a97 3065 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 3066 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 3067 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3068 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3069 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3070 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3071 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3072
3073 enable_mask = ~dev_priv->irq_mask;
21ad8330
VS		 3074 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3075 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
bbba0a97
CW		 3076 enable_mask |= I915_USER_INTERRUPT;
3077
3078 if (IS_G4X(dev))
3079 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5 3080
b79480ba
DV		 3081 /* Interrupt setup is already guaranteed to be single-threaded, this is
3082 * just to make the assert_spin_locked check happy. */
3083 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
515ac2bb 3084 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
b79480ba 3085 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
a266c7d5 3086
a266c7d5
CW		 3087 /*
3088 * Enable some error detection, note the instruction error mask
3089 * bit is reserved, so we leave it masked.
3090 */
3091 if (IS_G4X(dev)) {
3092 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3093 GM45_ERROR_MEM_PRIV |
3094 GM45_ERROR_CP_PRIV |
3095 I915_ERROR_MEMORY_REFRESH);
3096 } else {
3097 error_mask = ~(I915_ERROR_PAGE_TABLE |
3098 I915_ERROR_MEMORY_REFRESH);
3099 }
3100 I915_WRITE(EMR, error_mask);
3101
3102 I915_WRITE(IMR, dev_priv->irq_mask);
3103 I915_WRITE(IER, enable_mask);
3104 POSTING_READ(IER);
3105
20afbda2
DV		 3106 I915_WRITE(PORT_HOTPLUG_EN, 0);
3107 POSTING_READ(PORT_HOTPLUG_EN);
3108
f49e38dd 3109 i915_enable_asle_pipestat(dev);
20afbda2
DV		 3110
3111 return 0;
3112}
3113
bac56d5b 3114static void i915_hpd_irq_setup(struct drm_device *dev)
20afbda2
DV		 3115{
3116 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e5868a31 3117 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed 3118 struct intel_encoder *intel_encoder;
20afbda2
DV		 3119 u32 hotplug_en;
3120
b5ea2d56
DV		 3121 assert_spin_locked(&dev_priv->irq_lock);
3122
bac56d5b
EE		 3123 if (I915_HAS_HOTPLUG(dev)) {
3124 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3125 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3126 /* Note HDMI and DP share hotplug bits */
e5868a31 3127 /* enable bits are the same for all generations */
cd569aed
EE		 3128 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3129 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3130 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
bac56d5b
EE		 3131 /* Programming the CRT detection parameters tends
3132 to generate a spurious hotplug event about three
3133 seconds later. So just do it once.
3134 */
3135 if (IS_G4X(dev))
3136 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
85fc95ba 3137 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
bac56d5b 3138 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
a266c7d5 3139
bac56d5b
EE		 3140 /* Ignore TV since it's buggy */
3141 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3142 }
a266c7d5
CW		 3143}
3144
ff1f525e 3145static irqreturn_t i965_irq_handler(int irq, void *arg)
a266c7d5
CW		 3146{
3147 struct drm_device *dev = (struct drm_device *) arg;
3148 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 3149 u32 iir, new_iir;
3150 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 3151 unsigned long irqflags;
3152 int irq_received;
3153 int ret = IRQ_NONE, pipe;
21ad8330
VS		 3154 u32 flip_mask =
3155 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3156 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
a266c7d5
CW		 3157
3158 atomic_inc(&dev_priv->irq_received);
3159
3160 iir = I915_READ(IIR);
3161
a266c7d5 3162 for (;;) {
2c8ba29f
CW		 3163 bool blc_event = false;
3164
21ad8330 3165 irq_received = (iir & ~flip_mask) != 0;
a266c7d5
CW		 3166
3167 /* Can't rely on pipestat interrupt bit in iir as it might
3168 * have been cleared after the pipestat interrupt was received.
3169 * It doesn't set the bit in iir again, but it still produces
3170 * interrupts (for non-MSI).
3171 */
3172 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3173 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3174 i915_handle_error(dev, false);
3175
3176 for_each_pipe(pipe) {
3177 int reg = PIPESTAT(pipe);
3178 pipe_stats[pipe] = I915_READ(reg);
3179
3180 /*
3181 * Clear the PIPE*STAT regs before the IIR
3182 */
3183 if (pipe_stats[pipe] & 0x8000ffff) {
3184 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3185 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3186 pipe_name(pipe));
3187 I915_WRITE(reg, pipe_stats[pipe]);
3188 irq_received = 1;
3189 }
3190 }
3191 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3192
3193 if (!irq_received)
3194 break;
3195
3196 ret = IRQ_HANDLED;
3197
3198 /* Consume port. Then clear IIR or we'll miss events */
adca4730 3199 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
a266c7d5 3200 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04
EE		 3201 u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
3202 HOTPLUG_INT_STATUS_G4X :
4f7fd709 3203 HOTPLUG_INT_STATUS_I915);
a266c7d5
CW		 3204
3205 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3206 hotplug_status);
91d131d2
DV		 3207
3208 intel_hpd_irq_handler(dev, hotplug_trigger,
3209 IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915);
3210
a266c7d5
CW		 3211 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3212 I915_READ(PORT_HOTPLUG_STAT);
3213 }
3214
21ad8330 3215 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 3216 new_iir = I915_READ(IIR); /* Flush posted writes */
3217
a266c7d5
CW		 3218 if (iir & I915_USER_INTERRUPT)
3219 notify_ring(dev, &dev_priv->ring[RCS]);
3220 if (iir & I915_BSD_USER_INTERRUPT)
3221 notify_ring(dev, &dev_priv->ring[VCS]);
3222
a266c7d5 3223 for_each_pipe(pipe) {
2c8ba29f 3224 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3225 i915_handle_vblank(dev, pipe, pipe, iir))
3226 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
a266c7d5
CW		 3227
3228 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3229 blc_event = true;
3230 }
3231
3232
3233 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3234 intel_opregion_asle_intr(dev);
3235
515ac2bb
DV		 3236 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3237 gmbus_irq_handler(dev);
3238
a266c7d5
CW		 3239 /* With MSI, interrupts are only generated when iir
3240 * transitions from zero to nonzero. If another bit got
3241 * set while we were handling the existing iir bits, then
3242 * we would never get another interrupt.
3243 *
3244 * This is fine on non-MSI as well, as if we hit this path
3245 * we avoid exiting the interrupt handler only to generate
3246 * another one.
3247 *
3248 * Note that for MSI this could cause a stray interrupt report
3249 * if an interrupt landed in the time between writing IIR and
3250 * the posting read. This should be rare enough to never
3251 * trigger the 99% of 100,000 interrupts test for disabling
3252 * stray interrupts.
3253 */
3254 iir = new_iir;
3255 }
3256
d05c617e 3257 i915_update_dri1_breadcrumb(dev);
2c8ba29f 3258
a266c7d5
CW		 3259 return ret;
3260}
3261
3262static void i965_irq_uninstall(struct drm_device * dev)
3263{
3264 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3265 int pipe;
3266
3267 if (!dev_priv)
3268 return;
3269
ac4c16c5
EE		 3270 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3271
adca4730
CW		 3272 I915_WRITE(PORT_HOTPLUG_EN, 0);
3273 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 3274
3275 I915_WRITE(HWSTAM, 0xffffffff);
3276 for_each_pipe(pipe)
3277 I915_WRITE(PIPESTAT(pipe), 0);
3278 I915_WRITE(IMR, 0xffffffff);
3279 I915_WRITE(IER, 0x0);
3280
3281 for_each_pipe(pipe)
3282 I915_WRITE(PIPESTAT(pipe),
3283 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3284 I915_WRITE(IIR, I915_READ(IIR));
3285}
3286
ac4c16c5
EE		 3287static void i915_reenable_hotplug_timer_func(unsigned long data)
3288{
3289 drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3290 struct drm_device *dev = dev_priv->dev;
3291 struct drm_mode_config *mode_config = &dev->mode_config;
3292 unsigned long irqflags;
3293 int i;
3294
3295 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3296 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3297 struct drm_connector *connector;
3298
3299 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3300 continue;
3301
3302 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3303
3304 list_for_each_entry(connector, &mode_config->connector_list, head) {
3305 struct intel_connector *intel_connector = to_intel_connector(connector);
3306
3307 if (intel_connector->encoder->hpd_pin == i) {
3308 if (connector->polled != intel_connector->polled)
3309 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3310 drm_get_connector_name(connector));
3311 connector->polled = intel_connector->polled;
3312 if (!connector->polled)
3313 connector->polled = DRM_CONNECTOR_POLL_HPD;
3314 }
3315 }
3316 }
3317 if (dev_priv->display.hpd_irq_setup)
3318 dev_priv->display.hpd_irq_setup(dev);
3319 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3320}
3321
f71d4af4
JB		 3322void intel_irq_init(struct drm_device *dev)
3323{
8b2e326d
CW		 3324 struct drm_i915_private *dev_priv = dev->dev_private;
3325
3326 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
99584db3 3327 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
c6a828d3 3328 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
a4da4fa4 3329 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
8b2e326d 3330
99584db3
DV		 3331 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3332 i915_hangcheck_elapsed,
61bac78e 3333 (unsigned long) dev);
ac4c16c5
EE		 3334 setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
3335 (unsigned long) dev_priv);
61bac78e 3336
97a19a24 3337 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
9ee32fea 3338
4cdb83ec
VS		 3339 if (IS_GEN2(dev)) {
3340 dev->max_vblank_count = 0;
3341 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
3342 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 3343 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3344 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
391f75e2
VS		 3345 } else {
3346 dev->driver->get_vblank_counter = i915_get_vblank_counter;
3347 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
f71d4af4
JB		 3348 }
3349
c2baf4b7 3350 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
c3613de9 3351 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
c2baf4b7
VS		 3352 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3353 }
f71d4af4 3354
7e231dbe
JB		 3355 if (IS_VALLEYVIEW(dev)) {
3356 dev->driver->irq_handler = valleyview_irq_handler;
3357 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3358 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3359 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3360 dev->driver->enable_vblank = valleyview_enable_vblank;
3361 dev->driver->disable_vblank = valleyview_disable_vblank;
fa00abe0 3362 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
f71d4af4
JB		 3363 } else if (HAS_PCH_SPLIT(dev)) {
3364 dev->driver->irq_handler = ironlake_irq_handler;
3365 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3366 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3367 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3368 dev->driver->enable_vblank = ironlake_enable_vblank;
3369 dev->driver->disable_vblank = ironlake_disable_vblank;
82a28bcf 3370 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4 3371 } else {
c2798b19
CW		 3372 if (INTEL_INFO(dev)->gen == 2) {
3373 dev->driver->irq_preinstall = i8xx_irq_preinstall;
3374 dev->driver->irq_postinstall = i8xx_irq_postinstall;
3375 dev->driver->irq_handler = i8xx_irq_handler;
3376 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5
CW		 3377 } else if (INTEL_INFO(dev)->gen == 3) {
3378 dev->driver->irq_preinstall = i915_irq_preinstall;
3379 dev->driver->irq_postinstall = i915_irq_postinstall;
3380 dev->driver->irq_uninstall = i915_irq_uninstall;
3381 dev->driver->irq_handler = i915_irq_handler;
20afbda2 3382 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 3383 } else {
a266c7d5
CW		 3384 dev->driver->irq_preinstall = i965_irq_preinstall;
3385 dev->driver->irq_postinstall = i965_irq_postinstall;
3386 dev->driver->irq_uninstall = i965_irq_uninstall;
3387 dev->driver->irq_handler = i965_irq_handler;
bac56d5b 3388 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 3389 }
f71d4af4
JB		 3390 dev->driver->enable_vblank = i915_enable_vblank;
3391 dev->driver->disable_vblank = i915_disable_vblank;
3392 }
3393}
20afbda2
DV		 3394
3395void intel_hpd_init(struct drm_device *dev)
3396{
3397 struct drm_i915_private *dev_priv = dev->dev_private;
821450c6
EE		 3398 struct drm_mode_config *mode_config = &dev->mode_config;
3399 struct drm_connector *connector;
b5ea2d56 3400 unsigned long irqflags;
821450c6 3401 int i;
20afbda2 3402
821450c6
EE		 3403 for (i = 1; i < HPD_NUM_PINS; i++) {
3404 dev_priv->hpd_stats[i].hpd_cnt = 0;
3405 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3406 }
3407 list_for_each_entry(connector, &mode_config->connector_list, head) {
3408 struct intel_connector *intel_connector = to_intel_connector(connector);
3409 connector->polled = intel_connector->polled;
3410 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3411 connector->polled = DRM_CONNECTOR_POLL_HPD;
3412 }
b5ea2d56
DV		 3413
3414 /* Interrupt setup is already guaranteed to be single-threaded, this is
3415 * just to make the assert_spin_locked checks happy. */
3416 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
20afbda2
DV		 3417 if (dev_priv->display.hpd_irq_setup)
3418 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 3419 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
20afbda2 3420}
c67a470b
PZ		 3421
3422/* Disable interrupts so we can allow Package C8+. */
3423void hsw_pc8_disable_interrupts(struct drm_device *dev)
3424{
3425 struct drm_i915_private *dev_priv = dev->dev_private;
3426 unsigned long irqflags;
3427
3428 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3429
3430 dev_priv->pc8.regsave.deimr = I915_READ(DEIMR);
3431 dev_priv->pc8.regsave.sdeimr = I915_READ(SDEIMR);
3432 dev_priv->pc8.regsave.gtimr = I915_READ(GTIMR);
3433 dev_priv->pc8.regsave.gtier = I915_READ(GTIER);
3434 dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR);
3435
3436 ironlake_disable_display_irq(dev_priv, ~DE_PCH_EVENT_IVB);
3437 ibx_disable_display_interrupt(dev_priv, ~SDE_HOTPLUG_MASK_CPT);
3438 ilk_disable_gt_irq(dev_priv, 0xffffffff);
3439 snb_disable_pm_irq(dev_priv, 0xffffffff);
3440
3441 dev_priv->pc8.irqs_disabled = true;
3442
3443 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3444}
3445
3446/* Restore interrupts so we can recover from Package C8+. */
3447void hsw_pc8_restore_interrupts(struct drm_device *dev)
3448{
3449 struct drm_i915_private *dev_priv = dev->dev_private;
3450 unsigned long irqflags;
3451 uint32_t val, expected;
3452
3453 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3454
3455 val = I915_READ(DEIMR);
3456 expected = ~DE_PCH_EVENT_IVB;
3457 WARN(val != expected, "DEIMR is 0x%08x, not 0x%08x\n", val, expected);
3458
3459 val = I915_READ(SDEIMR) & ~SDE_HOTPLUG_MASK_CPT;
3460 expected = ~SDE_HOTPLUG_MASK_CPT;
3461 WARN(val != expected, "SDEIMR non-HPD bits are 0x%08x, not 0x%08x\n",
3462 val, expected);
3463
3464 val = I915_READ(GTIMR);
3465 expected = 0xffffffff;
3466 WARN(val != expected, "GTIMR is 0x%08x, not 0x%08x\n", val, expected);
3467
3468 val = I915_READ(GEN6_PMIMR);
3469 expected = 0xffffffff;
3470 WARN(val != expected, "GEN6_PMIMR is 0x%08x, not 0x%08x\n", val,
3471 expected);
3472
3473 dev_priv->pc8.irqs_disabled = false;
3474
3475 ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr);
3476 ibx_enable_display_interrupt(dev_priv,
3477 ~dev_priv->pc8.regsave.sdeimr &
3478 ~SDE_HOTPLUG_MASK_CPT);
3479 ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr);
3480 snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr);
3481 I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier);
3482
3483 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3484}
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