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drm/i915: Dynamic Parity Detection handling
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
1da177e4
LT		 33#include "drmP.h"
34#include "drm.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
1c5d22f7 37#include "i915_trace.h"
79e53945 38#include "intel_drv.h"
1da177e4 39
036a4a7d 40/* For display hotplug interrupt */
995b6762 41static void
f2b115e6 42ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 43{
1ec14ad3
CW		 44 if ((dev_priv->irq_mask & mask) != 0) {
45 dev_priv->irq_mask &= ~mask;
46 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 47 POSTING_READ(DEIMR);
036a4a7d
ZW		 48 }
49}
50
51static inline void
f2b115e6 52ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 53{
1ec14ad3
CW		 54 if ((dev_priv->irq_mask & mask) != mask) {
55 dev_priv->irq_mask |= mask;
56 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 57 POSTING_READ(DEIMR);
036a4a7d
ZW		 58 }
59}
60
7c463586
KP		 61void
62i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
63{
64 if ((dev_priv->pipestat[pipe] & mask) != mask) {
9db4a9c7 65 u32 reg = PIPESTAT(pipe);
7c463586
KP		 66
67 dev_priv->pipestat[pipe] |= mask;
68 /* Enable the interrupt, clear any pending status */
69 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
3143a2bf 70 POSTING_READ(reg);
7c463586
KP		 71 }
72}
73
74void
75i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
76{
77 if ((dev_priv->pipestat[pipe] & mask) != 0) {
9db4a9c7 78 u32 reg = PIPESTAT(pipe);
7c463586
KP		 79
80 dev_priv->pipestat[pipe] &= ~mask;
81 I915_WRITE(reg, dev_priv->pipestat[pipe]);
3143a2bf 82 POSTING_READ(reg);
7c463586
KP		 83 }
84}
85
01c66889
ZY		 86/**
87 * intel_enable_asle - enable ASLE interrupt for OpRegion
88 */
1ec14ad3 89void intel_enable_asle(struct drm_device *dev)
01c66889 90{
1ec14ad3
CW		 91 drm_i915_private_t *dev_priv = dev->dev_private;
92 unsigned long irqflags;
93
7e231dbe
JB		 94 /* FIXME: opregion/asle for VLV */
95 if (IS_VALLEYVIEW(dev))
96 return;
97
1ec14ad3 98 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 99
c619eed4 100 if (HAS_PCH_SPLIT(dev))
f2b115e6 101 ironlake_enable_display_irq(dev_priv, DE_GSE);
edcb49ca 102 else {
01c66889 103 i915_enable_pipestat(dev_priv, 1,
d874bcff 104 PIPE_LEGACY_BLC_EVENT_ENABLE);
a6c45cf0 105 if (INTEL_INFO(dev)->gen >= 4)
edcb49ca 106 i915_enable_pipestat(dev_priv, 0,
d874bcff 107 PIPE_LEGACY_BLC_EVENT_ENABLE);
edcb49ca 108 }
1ec14ad3
CW		 109
110 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 111}
112
0a3e67a4
JB		 113/**
114 * i915_pipe_enabled - check if a pipe is enabled
115 * @dev: DRM device
116 * @pipe: pipe to check
117 *
118 * Reading certain registers when the pipe is disabled can hang the chip.
119 * Use this routine to make sure the PLL is running and the pipe is active
120 * before reading such registers if unsure.
121 */
122static int
123i915_pipe_enabled(struct drm_device *dev, int pipe)
124{
125 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
5eddb70b 126 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
0a3e67a4
JB		 127}
128
42f52ef8
KP		 129/* Called from drm generic code, passed a 'crtc', which
130 * we use as a pipe index
131 */
f71d4af4 132static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 133{
134 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
135 unsigned long high_frame;
136 unsigned long low_frame;
5eddb70b 137 u32 high1, high2, low;
0a3e67a4
JB		 138
139 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 140 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 141 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 142 return 0;
143 }
144
9db4a9c7
JB		 145 high_frame = PIPEFRAME(pipe);
146 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 147
0a3e67a4
JB		 148 /*
149 * High & low register fields aren't synchronized, so make sure
150 * we get a low value that's stable across two reads of the high
151 * register.
152 */
153 do {
5eddb70b
CW		 154 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
155 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
156 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 157 } while (high1 != high2);
158
5eddb70b
CW		 159 high1 >>= PIPE_FRAME_HIGH_SHIFT;
160 low >>= PIPE_FRAME_LOW_SHIFT;
161 return (high1 << 8) | low;
0a3e67a4
JB		 162}
163
f71d4af4 164static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 165{
166 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 167 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 168
169 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 170 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 171 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 172 return 0;
173 }
174
175 return I915_READ(reg);
176}
177
f71d4af4 178static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 179 int *vpos, int *hpos)
180{
181 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
182 u32 vbl = 0, position = 0;
183 int vbl_start, vbl_end, htotal, vtotal;
184 bool in_vbl = true;
185 int ret = 0;
186
187 if (!i915_pipe_enabled(dev, pipe)) {
188 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 189 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 190 return 0;
191 }
192
193 /* Get vtotal. */
194 vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
195
196 if (INTEL_INFO(dev)->gen >= 4) {
197 /* No obvious pixelcount register. Only query vertical
198 * scanout position from Display scan line register.
199 */
200 position = I915_READ(PIPEDSL(pipe));
201
202 /* Decode into vertical scanout position. Don't have
203 * horizontal scanout position.
204 */
205 *vpos = position & 0x1fff;
206 *hpos = 0;
207 } else {
208 /* Have access to pixelcount since start of frame.
209 * We can split this into vertical and horizontal
210 * scanout position.
211 */
212 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
213
214 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
215 *vpos = position / htotal;
216 *hpos = position - (*vpos * htotal);
217 }
218
219 /* Query vblank area. */
220 vbl = I915_READ(VBLANK(pipe));
221
222 /* Test position against vblank region. */
223 vbl_start = vbl & 0x1fff;
224 vbl_end = (vbl >> 16) & 0x1fff;
225
226 if ((*vpos < vbl_start) || (*vpos > vbl_end))
227 in_vbl = false;
228
229 /* Inside "upper part" of vblank area? Apply corrective offset: */
230 if (in_vbl && (*vpos >= vbl_start))
231 *vpos = *vpos - vtotal;
232
233 /* Readouts valid? */
234 if (vbl > 0)
235 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
236
237 /* In vblank? */
238 if (in_vbl)
239 ret |= DRM_SCANOUTPOS_INVBL;
240
241 return ret;
242}
243
f71d4af4 244static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 245 int *max_error,
246 struct timeval *vblank_time,
247 unsigned flags)
248{
4041b853
CW		 249 struct drm_i915_private *dev_priv = dev->dev_private;
250 struct drm_crtc *crtc;
0af7e4df 251
4041b853
CW		 252 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
253 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 254 return -EINVAL;
255 }
256
257 /* Get drm_crtc to timestamp: */
4041b853
CW		 258 crtc = intel_get_crtc_for_pipe(dev, pipe);
259 if (crtc == NULL) {
260 DRM_ERROR("Invalid crtc %d\n", pipe);
261 return -EINVAL;
262 }
263
264 if (!crtc->enabled) {
265 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
266 return -EBUSY;
267 }
0af7e4df
MK		 268
269 /* Helper routine in DRM core does all the work: */
4041b853
CW		 270 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
271 vblank_time, flags,
272 crtc);
0af7e4df
MK		 273}
274
5ca58282
JB		 275/*
276 * Handle hotplug events outside the interrupt handler proper.
277 */
278static void i915_hotplug_work_func(struct work_struct *work)
279{
280 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
281 hotplug_work);
282 struct drm_device *dev = dev_priv->dev;
c31c4ba3 283 struct drm_mode_config *mode_config = &dev->mode_config;
4ef69c7a
CW		 284 struct intel_encoder *encoder;
285
a65e34c7 286 mutex_lock(&mode_config->mutex);
e67189ab
JB		 287 DRM_DEBUG_KMS("running encoder hotplug functions\n");
288
4ef69c7a
CW		 289 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
290 if (encoder->hot_plug)
291 encoder->hot_plug(encoder);
292
40ee3381
KP		 293 mutex_unlock(&mode_config->mutex);
294
5ca58282 295 /* Just fire off a uevent and let userspace tell us what to do */
eb1f8e4f 296 drm_helper_hpd_irq_event(dev);
5ca58282
JB		 297}
298
f97108d1
JB		 299static void i915_handle_rps_change(struct drm_device *dev)
300{
301 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 302 u32 busy_up, busy_down, max_avg, min_avg;
f97108d1
JB		 303 u8 new_delay = dev_priv->cur_delay;
304
7648fa99 305 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 306 busy_up = I915_READ(RCPREVBSYTUPAVG);
307 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 308 max_avg = I915_READ(RCBMAXAVG);
309 min_avg = I915_READ(RCBMINAVG);
310
311 /* Handle RCS change request from hw */
b5b72e89 312 if (busy_up > max_avg) {
f97108d1
JB		 313 if (dev_priv->cur_delay != dev_priv->max_delay)
314 new_delay = dev_priv->cur_delay - 1;
315 if (new_delay < dev_priv->max_delay)
316 new_delay = dev_priv->max_delay;
b5b72e89 317 } else if (busy_down < min_avg) {
f97108d1
JB		 318 if (dev_priv->cur_delay != dev_priv->min_delay)
319 new_delay = dev_priv->cur_delay + 1;
320 if (new_delay > dev_priv->min_delay)
321 new_delay = dev_priv->min_delay;
322 }
323
7648fa99
JB		 324 if (ironlake_set_drps(dev, new_delay))
325 dev_priv->cur_delay = new_delay;
f97108d1
JB		 326
327 return;
328}
329
549f7365
CW		 330static void notify_ring(struct drm_device *dev,
331 struct intel_ring_buffer *ring)
332{
333 struct drm_i915_private *dev_priv = dev->dev_private;
9862e600 334
475553de
CW		 335 if (ring->obj == NULL)
336 return;
337
6d171cb4 338 trace_i915_gem_request_complete(ring, ring->get_seqno(ring));
9862e600 339
549f7365 340 wake_up_all(&ring->irq_queue);
3e0dc6b0
BW		 341 if (i915_enable_hangcheck) {
342 dev_priv->hangcheck_count = 0;
343 mod_timer(&dev_priv->hangcheck_timer,
344 jiffies +
345 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
346 }
549f7365
CW		 347}
348
4912d041 349static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 350{
4912d041
BW		 351 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
352 rps_work);
3b8d8d91 353 u8 new_delay = dev_priv->cur_delay;
4912d041
BW		 354 u32 pm_iir, pm_imr;
355
356 spin_lock_irq(&dev_priv->rps_lock);
357 pm_iir = dev_priv->pm_iir;
358 dev_priv->pm_iir = 0;
359 pm_imr = I915_READ(GEN6_PMIMR);
a9e2641d 360 I915_WRITE(GEN6_PMIMR, 0);
4912d041 361 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91 362
3b8d8d91
JB		 363 if (!pm_iir)
364 return;
365
4912d041 366 mutex_lock(&dev_priv->dev->struct_mutex);
3b8d8d91
JB		 367 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
368 if (dev_priv->cur_delay != dev_priv->max_delay)
369 new_delay = dev_priv->cur_delay + 1;
370 if (new_delay > dev_priv->max_delay)
371 new_delay = dev_priv->max_delay;
372 } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
4912d041 373 gen6_gt_force_wake_get(dev_priv);
3b8d8d91
JB		 374 if (dev_priv->cur_delay != dev_priv->min_delay)
375 new_delay = dev_priv->cur_delay - 1;
376 if (new_delay < dev_priv->min_delay) {
377 new_delay = dev_priv->min_delay;
378 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
379 I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
380 ((new_delay << 16) & 0x3f0000));
381 } else {
382 /* Make sure we continue to get down interrupts
383 * until we hit the minimum frequency */
384 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
385 I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
386 }
4912d041 387 gen6_gt_force_wake_put(dev_priv);
3b8d8d91
JB		 388 }
389
4912d041 390 gen6_set_rps(dev_priv->dev, new_delay);
3b8d8d91
JB		 391 dev_priv->cur_delay = new_delay;
392
4912d041
BW		 393 /*
394 * rps_lock not held here because clearing is non-destructive. There is
395 * an *extremely* unlikely race with gen6_rps_enable() that is prevented
396 * by holding struct_mutex for the duration of the write.
397 */
4912d041 398 mutex_unlock(&dev_priv->dev->struct_mutex);
3b8d8d91
JB		 399}
400
e3689190
BW		 401
402/**
403 * ivybridge_parity_work - Workqueue called when a parity error interrupt
404 * occurred.
405 * @work: workqueue struct
406 *
407 * Doesn't actually do anything except notify userspace. As a consequence of
408 * this event, userspace should try to remap the bad rows since statistically
409 * it is likely the same row is more likely to go bad again.
410 */
411static void ivybridge_parity_work(struct work_struct *work)
412{
413 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
414 parity_error_work);
415 u32 error_status, row, bank, subbank;
416 char *parity_event[5];
417 uint32_t misccpctl;
418 unsigned long flags;
419
420 /* We must turn off DOP level clock gating to access the L3 registers.
421 * In order to prevent a get/put style interface, acquire struct mutex
422 * any time we access those registers.
423 */
424 mutex_lock(&dev_priv->dev->struct_mutex);
425
426 misccpctl = I915_READ(GEN7_MISCCPCTL);
427 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
428 POSTING_READ(GEN7_MISCCPCTL);
429
430 error_status = I915_READ(GEN7_L3CDERRST1);
431 row = GEN7_PARITY_ERROR_ROW(error_status);
432 bank = GEN7_PARITY_ERROR_BANK(error_status);
433 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
434
435 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
436 GEN7_L3CDERRST1_ENABLE);
437 POSTING_READ(GEN7_L3CDERRST1);
438
439 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
440
441 spin_lock_irqsave(&dev_priv->irq_lock, flags);
442 dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
443 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
444 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
445
446 mutex_unlock(&dev_priv->dev->struct_mutex);
447
448 parity_event[0] = "L3_PARITY_ERROR=1";
449 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
450 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
451 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
452 parity_event[4] = NULL;
453
454 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
455 KOBJ_CHANGE, parity_event);
456
457 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
458 row, bank, subbank);
459
460 kfree(parity_event[3]);
461 kfree(parity_event[2]);
462 kfree(parity_event[1]);
463}
464
465void ivybridge_handle_parity_error(struct drm_device *dev)
466{
467 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
468 unsigned long flags;
469
470 if (!IS_IVYBRIDGE(dev))
471 return;
472
473 spin_lock_irqsave(&dev_priv->irq_lock, flags);
474 dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
475 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
476 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
477
478 queue_work(dev_priv->wq, &dev_priv->parity_error_work);
479}
480
e7b4c6b1
DV		 481static void snb_gt_irq_handler(struct drm_device *dev,
482 struct drm_i915_private *dev_priv,
483 u32 gt_iir)
484{
485
486 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
487 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
488 notify_ring(dev, &dev_priv->ring[RCS]);
489 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
490 notify_ring(dev, &dev_priv->ring[VCS]);
491 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
492 notify_ring(dev, &dev_priv->ring[BCS]);
493
494 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
495 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
496 GT_RENDER_CS_ERROR_INTERRUPT)) {
497 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
498 i915_handle_error(dev, false);
499 }
e3689190
BW		 500
501 if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
502 ivybridge_handle_parity_error(dev);
e7b4c6b1
DV		 503}
504
fc6826d1
CW		 505static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
506 u32 pm_iir)
507{
508 unsigned long flags;
509
510 /*
511 * IIR bits should never already be set because IMR should
512 * prevent an interrupt from being shown in IIR. The warning
513 * displays a case where we've unsafely cleared
514 * dev_priv->pm_iir. Although missing an interrupt of the same
515 * type is not a problem, it displays a problem in the logic.
516 *
517 * The mask bit in IMR is cleared by rps_work.
518 */
519
520 spin_lock_irqsave(&dev_priv->rps_lock, flags);
521 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
522 dev_priv->pm_iir |= pm_iir;
523 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
524 POSTING_READ(GEN6_PMIMR);
525 spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
526
527 queue_work(dev_priv->wq, &dev_priv->rps_work);
528}
529
7e231dbe
JB		 530static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
531{
532 struct drm_device *dev = (struct drm_device *) arg;
533 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
534 u32 iir, gt_iir, pm_iir;
535 irqreturn_t ret = IRQ_NONE;
536 unsigned long irqflags;
537 int pipe;
538 u32 pipe_stats[I915_MAX_PIPES];
539 u32 vblank_status;
540 int vblank = 0;
541 bool blc_event;
542
543 atomic_inc(&dev_priv->irq_received);
544
545 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS |
546 PIPE_VBLANK_INTERRUPT_STATUS;
547
548 while (true) {
549 iir = I915_READ(VLV_IIR);
550 gt_iir = I915_READ(GTIIR);
551 pm_iir = I915_READ(GEN6_PMIIR);
552
553 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
554 goto out;
555
556 ret = IRQ_HANDLED;
557
e7b4c6b1 558 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 559
560 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
561 for_each_pipe(pipe) {
562 int reg = PIPESTAT(pipe);
563 pipe_stats[pipe] = I915_READ(reg);
564
565 /*
566 * Clear the PIPE*STAT regs before the IIR
567 */
568 if (pipe_stats[pipe] & 0x8000ffff) {
569 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
570 DRM_DEBUG_DRIVER("pipe %c underrun\n",
571 pipe_name(pipe));
572 I915_WRITE(reg, pipe_stats[pipe]);
573 }
574 }
575 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
576
577 /* Consume port. Then clear IIR or we'll miss events */
578 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
579 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
580
581 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
582 hotplug_status);
583 if (hotplug_status & dev_priv->hotplug_supported_mask)
584 queue_work(dev_priv->wq,
585 &dev_priv->hotplug_work);
586
587 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
588 I915_READ(PORT_HOTPLUG_STAT);
589 }
590
591
592 if (iir & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) {
593 drm_handle_vblank(dev, 0);
594 vblank++;
e0f608d7 595 intel_finish_page_flip(dev, 0);
7e231dbe
JB		 596 }
597
598 if (iir & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) {
599 drm_handle_vblank(dev, 1);
600 vblank++;
e0f608d7 601 intel_finish_page_flip(dev, 0);
7e231dbe
JB		 602 }
603
604 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
605 blc_event = true;
606
fc6826d1
CW		 607 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
608 gen6_queue_rps_work(dev_priv, pm_iir);
7e231dbe
JB		 609
610 I915_WRITE(GTIIR, gt_iir);
611 I915_WRITE(GEN6_PMIIR, pm_iir);
612 I915_WRITE(VLV_IIR, iir);
613 }
614
615out:
616 return ret;
617}
618
9adab8b5 619static void pch_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 620{
621 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 622 int pipe;
776ad806 623
776ad806
JB		 624 if (pch_iir & SDE_AUDIO_POWER_MASK)
625 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
626 (pch_iir & SDE_AUDIO_POWER_MASK) >>
627 SDE_AUDIO_POWER_SHIFT);
628
629 if (pch_iir & SDE_GMBUS)
630 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
631
632 if (pch_iir & SDE_AUDIO_HDCP_MASK)
633 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
634
635 if (pch_iir & SDE_AUDIO_TRANS_MASK)
636 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
637
638 if (pch_iir & SDE_POISON)
639 DRM_ERROR("PCH poison interrupt\n");
640
9db4a9c7
JB		 641 if (pch_iir & SDE_FDI_MASK)
642 for_each_pipe(pipe)
643 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
644 pipe_name(pipe),
645 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 646
647 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
648 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
649
650 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
651 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
652
653 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
654 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
655 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
656 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
657}
658
f71d4af4 659static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
b1f14ad0
JB		 660{
661 struct drm_device *dev = (struct drm_device *) arg;
662 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
0e43406b
CW		 663 u32 de_iir, gt_iir, de_ier, pm_iir;
664 irqreturn_t ret = IRQ_NONE;
665 int i;
b1f14ad0
JB		 666
667 atomic_inc(&dev_priv->irq_received);
668
669 /* disable master interrupt before clearing iir */
670 de_ier = I915_READ(DEIER);
671 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
b1f14ad0 672
b1f14ad0 673 gt_iir = I915_READ(GTIIR);
0e43406b
CW		 674 if (gt_iir) {
675 snb_gt_irq_handler(dev, dev_priv, gt_iir);
676 I915_WRITE(GTIIR, gt_iir);
677 ret = IRQ_HANDLED;
b1f14ad0
JB		 678 }
679
0e43406b
CW		 680 de_iir = I915_READ(DEIIR);
681 if (de_iir) {
682 if (de_iir & DE_GSE_IVB)
683 intel_opregion_gse_intr(dev);
684
685 for (i = 0; i < 3; i++) {
686 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
687 intel_prepare_page_flip(dev, i);
688 intel_finish_page_flip_plane(dev, i);
689 }
690 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
691 drm_handle_vblank(dev, i);
692 }
b615b57a 693
0e43406b
CW		 694 /* check event from PCH */
695 if (de_iir & DE_PCH_EVENT_IVB) {
696 u32 pch_iir = I915_READ(SDEIIR);
b1f14ad0 697
0e43406b
CW		 698 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
699 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
700 pch_irq_handler(dev, pch_iir);
b1f14ad0 701
0e43406b
CW		 702 /* clear PCH hotplug event before clear CPU irq */
703 I915_WRITE(SDEIIR, pch_iir);
704 }
b615b57a 705
0e43406b
CW		 706 I915_WRITE(DEIIR, de_iir);
707 ret = IRQ_HANDLED;
b1f14ad0
JB		 708 }
709
0e43406b
CW		 710 pm_iir = I915_READ(GEN6_PMIIR);
711 if (pm_iir) {
712 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
713 gen6_queue_rps_work(dev_priv, pm_iir);
714 I915_WRITE(GEN6_PMIIR, pm_iir);
715 ret = IRQ_HANDLED;
716 }
b1f14ad0 717
b1f14ad0
JB		 718 I915_WRITE(DEIER, de_ier);
719 POSTING_READ(DEIER);
720
721 return ret;
722}
723
e7b4c6b1
DV		 724static void ilk_gt_irq_handler(struct drm_device *dev,
725 struct drm_i915_private *dev_priv,
726 u32 gt_iir)
727{
728 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
729 notify_ring(dev, &dev_priv->ring[RCS]);
730 if (gt_iir & GT_BSD_USER_INTERRUPT)
731 notify_ring(dev, &dev_priv->ring[VCS]);
732}
733
f71d4af4 734static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
036a4a7d 735{
4697995b 736 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 737 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
738 int ret = IRQ_NONE;
3b8d8d91 739 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
2d7b8366 740 u32 hotplug_mask;
881f47b6 741
4697995b
JB		 742 atomic_inc(&dev_priv->irq_received);
743
2d109a84
ZN		 744 /* disable master interrupt before clearing iir */
745 de_ier = I915_READ(DEIER);
746 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 747 POSTING_READ(DEIER);
2d109a84 748
036a4a7d
ZW		 749 de_iir = I915_READ(DEIIR);
750 gt_iir = I915_READ(GTIIR);
c650156a 751 pch_iir = I915_READ(SDEIIR);
3b8d8d91 752 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 753
3b8d8d91
JB		 754 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
755 (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 756 goto done;
036a4a7d 757
2d7b8366
YL		 758 if (HAS_PCH_CPT(dev))
759 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
760 else
761 hotplug_mask = SDE_HOTPLUG_MASK;
762
c7c85101 763 ret = IRQ_HANDLED;
036a4a7d 764
e7b4c6b1
DV		 765 if (IS_GEN5(dev))
766 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
767 else
768 snb_gt_irq_handler(dev, dev_priv, gt_iir);
01c66889 769
c7c85101 770 if (de_iir & DE_GSE)
3b617967 771 intel_opregion_gse_intr(dev);
c650156a 772
f072d2e7 773 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 774 intel_prepare_page_flip(dev, 0);
2bbda389 775 intel_finish_page_flip_plane(dev, 0);
f072d2e7 776 }
013d5aa2 777
f072d2e7 778 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 779 intel_prepare_page_flip(dev, 1);
2bbda389 780 intel_finish_page_flip_plane(dev, 1);
f072d2e7 781 }
013d5aa2 782
f072d2e7 783 if (de_iir & DE_PIPEA_VBLANK)
c062df61
LP		 784 drm_handle_vblank(dev, 0);
785
f072d2e7 786 if (de_iir & DE_PIPEB_VBLANK)
c062df61
LP		 787 drm_handle_vblank(dev, 1);
788
c7c85101 789 /* check event from PCH */
776ad806
JB		 790 if (de_iir & DE_PCH_EVENT) {
791 if (pch_iir & hotplug_mask)
792 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
9adab8b5 793 pch_irq_handler(dev, pch_iir);
776ad806 794 }
036a4a7d 795
f97108d1 796 if (de_iir & DE_PCU_EVENT) {
7648fa99 797 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
f97108d1
JB		 798 i915_handle_rps_change(dev);
799 }
800
fc6826d1
CW		 801 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
802 gen6_queue_rps_work(dev_priv, pm_iir);
3b8d8d91 803
c7c85101
ZN		 804 /* should clear PCH hotplug event before clear CPU irq */
805 I915_WRITE(SDEIIR, pch_iir);
806 I915_WRITE(GTIIR, gt_iir);
807 I915_WRITE(DEIIR, de_iir);
4912d041 808 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 809
810done:
2d109a84 811 I915_WRITE(DEIER, de_ier);
3143a2bf 812 POSTING_READ(DEIER);
2d109a84 813
036a4a7d
ZW		 814 return ret;
815}
816
8a905236
JB		 817/**
818 * i915_error_work_func - do process context error handling work
819 * @work: work struct
820 *
821 * Fire an error uevent so userspace can see that a hang or error
822 * was detected.
823 */
824static void i915_error_work_func(struct work_struct *work)
825{
826 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
827 error_work);
828 struct drm_device *dev = dev_priv->dev;
f316a42c
BG		 829 char *error_event[] = { "ERROR=1", NULL };
830 char *reset_event[] = { "RESET=1", NULL };
831 char *reset_done_event[] = { "ERROR=0", NULL };
8a905236 832
f316a42c
BG		 833 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
834
ba1234d1 835 if (atomic_read(&dev_priv->mm.wedged)) {
f803aa55
CW		 836 DRM_DEBUG_DRIVER("resetting chip\n");
837 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
d4b8bb2a 838 if (!i915_reset(dev)) {
f803aa55
CW		 839 atomic_set(&dev_priv->mm.wedged, 0);
840 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
f316a42c 841 }
30dbf0c0 842 complete_all(&dev_priv->error_completion);
f316a42c 843 }
8a905236
JB		 844}
845
3bd3c932 846#ifdef CONFIG_DEBUG_FS
9df30794 847static struct drm_i915_error_object *
bcfb2e28 848i915_error_object_create(struct drm_i915_private *dev_priv,
05394f39 849 struct drm_i915_gem_object *src)
9df30794
CW		 850{
851 struct drm_i915_error_object *dst;
9df30794 852 int page, page_count;
e56660dd 853 u32 reloc_offset;
9df30794 854
05394f39 855 if (src == NULL || src->pages == NULL)
9df30794
CW		 856 return NULL;
857
05394f39 858 page_count = src->base.size / PAGE_SIZE;
9df30794 859
0206e353 860 dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
9df30794
CW		 861 if (dst == NULL)
862 return NULL;
863
05394f39 864 reloc_offset = src->gtt_offset;
9df30794 865 for (page = 0; page < page_count; page++) {
788885ae 866 unsigned long flags;
e56660dd 867 void *d;
788885ae 868
e56660dd 869 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 870 if (d == NULL)
871 goto unwind;
e56660dd 872
788885ae 873 local_irq_save(flags);
74898d7e
DV		 874 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
875 src->has_global_gtt_mapping) {
172975aa
CW		 876 void __iomem *s;
877
878 /* Simply ignore tiling or any overlapping fence.
879 * It's part of the error state, and this hopefully
880 * captures what the GPU read.
881 */
882
883 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
884 reloc_offset);
885 memcpy_fromio(d, s, PAGE_SIZE);
886 io_mapping_unmap_atomic(s);
887 } else {
888 void *s;
889
890 drm_clflush_pages(&src->pages[page], 1);
891
892 s = kmap_atomic(src->pages[page]);
893 memcpy(d, s, PAGE_SIZE);
894 kunmap_atomic(s);
895
896 drm_clflush_pages(&src->pages[page], 1);
897 }
788885ae 898 local_irq_restore(flags);
e56660dd 899
9df30794 900 dst->pages[page] = d;
e56660dd
CW		 901
902 reloc_offset += PAGE_SIZE;
9df30794
CW		 903 }
904 dst->page_count = page_count;
05394f39 905 dst->gtt_offset = src->gtt_offset;
9df30794
CW		 906
907 return dst;
908
909unwind:
910 while (page--)
911 kfree(dst->pages[page]);
912 kfree(dst);
913 return NULL;
914}
915
916static void
917i915_error_object_free(struct drm_i915_error_object *obj)
918{
919 int page;
920
921 if (obj == NULL)
922 return;
923
924 for (page = 0; page < obj->page_count; page++)
925 kfree(obj->pages[page]);
926
927 kfree(obj);
928}
929
742cbee8
DV		 930void
931i915_error_state_free(struct kref *error_ref)
9df30794 932{
742cbee8
DV		 933 struct drm_i915_error_state *error = container_of(error_ref,
934 typeof(*error), ref);
e2f973d5
CW		 935 int i;
936
52d39a21
CW		 937 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
938 i915_error_object_free(error->ring[i].batchbuffer);
939 i915_error_object_free(error->ring[i].ringbuffer);
940 kfree(error->ring[i].requests);
941 }
e2f973d5 942
9df30794 943 kfree(error->active_bo);
6ef3d427 944 kfree(error->overlay);
9df30794
CW		 945 kfree(error);
946}
1b50247a
CW		 947static void capture_bo(struct drm_i915_error_buffer *err,
948 struct drm_i915_gem_object *obj)
949{
950 err->size = obj->base.size;
951 err->name = obj->base.name;
952 err->seqno = obj->last_rendering_seqno;
953 err->gtt_offset = obj->gtt_offset;
954 err->read_domains = obj->base.read_domains;
955 err->write_domain = obj->base.write_domain;
956 err->fence_reg = obj->fence_reg;
957 err->pinned = 0;
958 if (obj->pin_count > 0)
959 err->pinned = 1;
960 if (obj->user_pin_count > 0)
961 err->pinned = -1;
962 err->tiling = obj->tiling_mode;
963 err->dirty = obj->dirty;
964 err->purgeable = obj->madv != I915_MADV_WILLNEED;
965 err->ring = obj->ring ? obj->ring->id : -1;
966 err->cache_level = obj->cache_level;
967}
9df30794 968
1b50247a
CW		 969static u32 capture_active_bo(struct drm_i915_error_buffer *err,
970 int count, struct list_head *head)
c724e8a9
CW		 971{
972 struct drm_i915_gem_object *obj;
973 int i = 0;
974
975 list_for_each_entry(obj, head, mm_list) {
1b50247a 976 capture_bo(err++, obj);
c724e8a9
CW		 977 if (++i == count)
978 break;
1b50247a
CW		 979 }
980
981 return i;
982}
983
984static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
985 int count, struct list_head *head)
986{
987 struct drm_i915_gem_object *obj;
988 int i = 0;
989
990 list_for_each_entry(obj, head, gtt_list) {
991 if (obj->pin_count == 0)
992 continue;
c724e8a9 993
1b50247a
CW		 994 capture_bo(err++, obj);
995 if (++i == count)
996 break;
c724e8a9
CW		 997 }
998
999 return i;
1000}
1001
748ebc60
CW		 1002static void i915_gem_record_fences(struct drm_device *dev,
1003 struct drm_i915_error_state *error)
1004{
1005 struct drm_i915_private *dev_priv = dev->dev_private;
1006 int i;
1007
1008 /* Fences */
1009 switch (INTEL_INFO(dev)->gen) {
775d17b6 1010 case 7:
748ebc60
CW		 1011 case 6:
1012 for (i = 0; i < 16; i++)
1013 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1014 break;
1015 case 5:
1016 case 4:
1017 for (i = 0; i < 16; i++)
1018 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1019 break;
1020 case 3:
1021 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1022 for (i = 0; i < 8; i++)
1023 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1024 case 2:
1025 for (i = 0; i < 8; i++)
1026 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1027 break;
1028
1029 }
1030}
1031
bcfb2e28
CW		 1032static struct drm_i915_error_object *
1033i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1034 struct intel_ring_buffer *ring)
1035{
1036 struct drm_i915_gem_object *obj;
1037 u32 seqno;
1038
1039 if (!ring->get_seqno)
1040 return NULL;
1041
1042 seqno = ring->get_seqno(ring);
1043 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1044 if (obj->ring != ring)
1045 continue;
1046
c37d9a5d 1047 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
bcfb2e28
CW		 1048 continue;
1049
1050 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1051 continue;
1052
1053 /* We need to copy these to an anonymous buffer as the simplest
1054 * method to avoid being overwritten by userspace.
1055 */
1056 return i915_error_object_create(dev_priv, obj);
1057 }
1058
1059 return NULL;
1060}
1061
d27b1e0e
DV		 1062static void i915_record_ring_state(struct drm_device *dev,
1063 struct drm_i915_error_state *error,
1064 struct intel_ring_buffer *ring)
1065{
1066 struct drm_i915_private *dev_priv = dev->dev_private;
1067
33f3f518 1068 if (INTEL_INFO(dev)->gen >= 6) {
33f3f518 1069 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
7e3b8737
DV		 1070 error->semaphore_mboxes[ring->id][0]
1071 = I915_READ(RING_SYNC_0(ring->mmio_base));
1072 error->semaphore_mboxes[ring->id][1]
1073 = I915_READ(RING_SYNC_1(ring->mmio_base));
33f3f518 1074 }
c1cd90ed 1075
d27b1e0e 1076 if (INTEL_INFO(dev)->gen >= 4) {
9d2f41fa 1077 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
d27b1e0e
DV		 1078 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1079 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1080 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
c1cd90ed 1081 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
d27b1e0e 1082 if (ring->id == RCS) {
d27b1e0e
DV		 1083 error->instdone1 = I915_READ(INSTDONE1);
1084 error->bbaddr = I915_READ64(BB_ADDR);
1085 }
1086 } else {
9d2f41fa 1087 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
d27b1e0e
DV		 1088 error->ipeir[ring->id] = I915_READ(IPEIR);
1089 error->ipehr[ring->id] = I915_READ(IPEHR);
1090 error->instdone[ring->id] = I915_READ(INSTDONE);
d27b1e0e
DV		 1091 }
1092
9574b3fe 1093 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
c1cd90ed 1094 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
d27b1e0e
DV		 1095 error->seqno[ring->id] = ring->get_seqno(ring);
1096 error->acthd[ring->id] = intel_ring_get_active_head(ring);
c1cd90ed
DV		 1097 error->head[ring->id] = I915_READ_HEAD(ring);
1098 error->tail[ring->id] = I915_READ_TAIL(ring);
7e3b8737
DV		 1099
1100 error->cpu_ring_head[ring->id] = ring->head;
1101 error->cpu_ring_tail[ring->id] = ring->tail;
d27b1e0e
DV		 1102}
1103
52d39a21
CW		 1104static void i915_gem_record_rings(struct drm_device *dev,
1105 struct drm_i915_error_state *error)
1106{
1107 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 1108 struct intel_ring_buffer *ring;
52d39a21
CW		 1109 struct drm_i915_gem_request *request;
1110 int i, count;
1111
b4519513 1112 for_each_ring(ring, dev_priv, i) {
52d39a21
CW		 1113 i915_record_ring_state(dev, error, ring);
1114
1115 error->ring[i].batchbuffer =
1116 i915_error_first_batchbuffer(dev_priv, ring);
1117
1118 error->ring[i].ringbuffer =
1119 i915_error_object_create(dev_priv, ring->obj);
1120
1121 count = 0;
1122 list_for_each_entry(request, &ring->request_list, list)
1123 count++;
1124
1125 error->ring[i].num_requests = count;
1126 error->ring[i].requests =
1127 kmalloc(count*sizeof(struct drm_i915_error_request),
1128 GFP_ATOMIC);
1129 if (error->ring[i].requests == NULL) {
1130 error->ring[i].num_requests = 0;
1131 continue;
1132 }
1133
1134 count = 0;
1135 list_for_each_entry(request, &ring->request_list, list) {
1136 struct drm_i915_error_request *erq;
1137
1138 erq = &error->ring[i].requests[count++];
1139 erq->seqno = request->seqno;
1140 erq->jiffies = request->emitted_jiffies;
ee4f42b1 1141 erq->tail = request->tail;
52d39a21
CW		 1142 }
1143 }
1144}
1145
8a905236
JB		 1146/**
1147 * i915_capture_error_state - capture an error record for later analysis
1148 * @dev: drm device
1149 *
1150 * Should be called when an error is detected (either a hang or an error
1151 * interrupt) to capture error state from the time of the error. Fills
1152 * out a structure which becomes available in debugfs for user level tools
1153 * to pick up.
1154 */
63eeaf38
JB		 1155static void i915_capture_error_state(struct drm_device *dev)
1156{
1157 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1158 struct drm_i915_gem_object *obj;
63eeaf38
JB		 1159 struct drm_i915_error_state *error;
1160 unsigned long flags;
9db4a9c7 1161 int i, pipe;
63eeaf38
JB		 1162
1163 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1164 error = dev_priv->first_error;
1165 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1166 if (error)
1167 return;
63eeaf38 1168
9db4a9c7 1169 /* Account for pipe specific data like PIPE*STAT */
33f3f518 1170 error = kzalloc(sizeof(*error), GFP_ATOMIC);
63eeaf38 1171 if (!error) {
9df30794
CW		 1172 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1173 return;
63eeaf38
JB		 1174 }
1175
b6f7833b
CW		 1176 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1177 dev->primary->index);
2fa772f3 1178
742cbee8 1179 kref_init(&error->ref);
63eeaf38
JB		 1180 error->eir = I915_READ(EIR);
1181 error->pgtbl_er = I915_READ(PGTBL_ER);
be998e2e
BW		 1182
1183 if (HAS_PCH_SPLIT(dev))
1184 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1185 else if (IS_VALLEYVIEW(dev))
1186 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1187 else if (IS_GEN2(dev))
1188 error->ier = I915_READ16(IER);
1189 else
1190 error->ier = I915_READ(IER);
1191
9db4a9c7
JB		 1192 for_each_pipe(pipe)
1193 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
d27b1e0e 1194
33f3f518 1195 if (INTEL_INFO(dev)->gen >= 6) {
f406839f 1196 error->error = I915_READ(ERROR_GEN6);
33f3f518
DV		 1197 error->done_reg = I915_READ(DONE_REG);
1198 }
d27b1e0e 1199
748ebc60 1200 i915_gem_record_fences(dev, error);
52d39a21 1201 i915_gem_record_rings(dev, error);
9df30794 1202
c724e8a9 1203 /* Record buffers on the active and pinned lists. */
9df30794 1204 error->active_bo = NULL;
c724e8a9 1205 error->pinned_bo = NULL;
9df30794 1206
bcfb2e28
CW		 1207 i = 0;
1208 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1209 i++;
1210 error->active_bo_count = i;
1b50247a
CW		 1211 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
1212 if (obj->pin_count)
1213 i++;
bcfb2e28 1214 error->pinned_bo_count = i - error->active_bo_count;
c724e8a9 1215
8e934dbf
CW		 1216 error->active_bo = NULL;
1217 error->pinned_bo = NULL;
bcfb2e28
CW		 1218 if (i) {
1219 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
9df30794 1220 GFP_ATOMIC);
c724e8a9
CW		 1221 if (error->active_bo)
1222 error->pinned_bo =
1223 error->active_bo + error->active_bo_count;
9df30794
CW		 1224 }
1225
c724e8a9
CW		 1226 if (error->active_bo)
1227 error->active_bo_count =
1b50247a
CW		 1228 capture_active_bo(error->active_bo,
1229 error->active_bo_count,
1230 &dev_priv->mm.active_list);
c724e8a9
CW		 1231
1232 if (error->pinned_bo)
1233 error->pinned_bo_count =
1b50247a
CW		 1234 capture_pinned_bo(error->pinned_bo,
1235 error->pinned_bo_count,
1236 &dev_priv->mm.gtt_list);
c724e8a9 1237
9df30794
CW		 1238 do_gettimeofday(&error->time);
1239
6ef3d427 1240 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 1241 error->display = intel_display_capture_error_state(dev);
6ef3d427 1242
9df30794
CW		 1243 spin_lock_irqsave(&dev_priv->error_lock, flags);
1244 if (dev_priv->first_error == NULL) {
1245 dev_priv->first_error = error;
1246 error = NULL;
1247 }
63eeaf38 1248 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1249
1250 if (error)
742cbee8 1251 i915_error_state_free(&error->ref);
9df30794
CW		 1252}
1253
1254void i915_destroy_error_state(struct drm_device *dev)
1255{
1256 struct drm_i915_private *dev_priv = dev->dev_private;
1257 struct drm_i915_error_state *error;
6dc0e816 1258 unsigned long flags;
9df30794 1259
6dc0e816 1260 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1261 error = dev_priv->first_error;
1262 dev_priv->first_error = NULL;
6dc0e816 1263 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1264
1265 if (error)
742cbee8 1266 kref_put(&error->ref, i915_error_state_free);
63eeaf38 1267}
3bd3c932
CW		 1268#else
1269#define i915_capture_error_state(x)
1270#endif
63eeaf38 1271
35aed2e6 1272static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1273{
1274 struct drm_i915_private *dev_priv = dev->dev_private;
1275 u32 eir = I915_READ(EIR);
9db4a9c7 1276 int pipe;
8a905236 1277
35aed2e6
CW		 1278 if (!eir)
1279 return;
8a905236 1280
a70491cc 1281 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236
JB		 1282
1283 if (IS_G4X(dev)) {
1284 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1285 u32 ipeir = I915_READ(IPEIR_I965);
1286
a70491cc
JP		 1287 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1288 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1289 pr_err(" INSTDONE: 0x%08x\n",
8a905236 1290 I915_READ(INSTDONE_I965));
a70491cc
JP		 1291 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1292 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1293 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1294 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1295 POSTING_READ(IPEIR_I965);
8a905236
JB		 1296 }
1297 if (eir & GM45_ERROR_PAGE_TABLE) {
1298 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1299 pr_err("page table error\n");
1300 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1301 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1302 POSTING_READ(PGTBL_ER);
8a905236
JB		 1303 }
1304 }
1305
a6c45cf0 1306 if (!IS_GEN2(dev)) {
8a905236
JB		 1307 if (eir & I915_ERROR_PAGE_TABLE) {
1308 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1309 pr_err("page table error\n");
1310 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1311 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1312 POSTING_READ(PGTBL_ER);
8a905236
JB		 1313 }
1314 }
1315
1316 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 1317 pr_err("memory refresh error:\n");
9db4a9c7 1318 for_each_pipe(pipe)
a70491cc 1319 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 1320 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 1321 /* pipestat has already been acked */
1322 }
1323 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 1324 pr_err("instruction error\n");
1325 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
a6c45cf0 1326 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 1327 u32 ipeir = I915_READ(IPEIR);
1328
a70491cc
JP		 1329 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1330 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
1331 pr_err(" INSTDONE: 0x%08x\n", I915_READ(INSTDONE));
1332 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 1333 I915_WRITE(IPEIR, ipeir);
3143a2bf 1334 POSTING_READ(IPEIR);
8a905236
JB		 1335 } else {
1336 u32 ipeir = I915_READ(IPEIR_I965);
1337
a70491cc
JP		 1338 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1339 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1340 pr_err(" INSTDONE: 0x%08x\n",
8a905236 1341 I915_READ(INSTDONE_I965));
a70491cc
JP		 1342 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1343 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1344 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1345 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1346 POSTING_READ(IPEIR_I965);
8a905236
JB		 1347 }
1348 }
1349
1350 I915_WRITE(EIR, eir);
3143a2bf 1351 POSTING_READ(EIR);
8a905236
JB		 1352 eir = I915_READ(EIR);
1353 if (eir) {
1354 /*
1355 * some errors might have become stuck,
1356 * mask them.
1357 */
1358 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1359 I915_WRITE(EMR, I915_READ(EMR) | eir);
1360 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1361 }
35aed2e6
CW		 1362}
1363
1364/**
1365 * i915_handle_error - handle an error interrupt
1366 * @dev: drm device
1367 *
1368 * Do some basic checking of regsiter state at error interrupt time and
1369 * dump it to the syslog. Also call i915_capture_error_state() to make
1370 * sure we get a record and make it available in debugfs. Fire a uevent
1371 * so userspace knows something bad happened (should trigger collection
1372 * of a ring dump etc.).
1373 */
527f9e90 1374void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 1375{
1376 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513
CW		 1377 struct intel_ring_buffer *ring;
1378 int i;
35aed2e6
CW		 1379
1380 i915_capture_error_state(dev);
1381 i915_report_and_clear_eir(dev);
8a905236 1382
ba1234d1 1383 if (wedged) {
30dbf0c0 1384 INIT_COMPLETION(dev_priv->error_completion);
ba1234d1
BG		 1385 atomic_set(&dev_priv->mm.wedged, 1);
1386
11ed50ec
BG		 1387 /*
1388 * Wakeup waiting processes so they don't hang
1389 */
b4519513
CW		 1390 for_each_ring(ring, dev_priv, i)
1391 wake_up_all(&ring->irq_queue);
11ed50ec
BG		 1392 }
1393
9c9fe1f8 1394 queue_work(dev_priv->wq, &dev_priv->error_work);
8a905236
JB		 1395}
1396
4e5359cd
SF		 1397static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1398{
1399 drm_i915_private_t *dev_priv = dev->dev_private;
1400 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1401 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 1402 struct drm_i915_gem_object *obj;
4e5359cd
SF		 1403 struct intel_unpin_work *work;
1404 unsigned long flags;
1405 bool stall_detected;
1406
1407 /* Ignore early vblank irqs */
1408 if (intel_crtc == NULL)
1409 return;
1410
1411 spin_lock_irqsave(&dev->event_lock, flags);
1412 work = intel_crtc->unpin_work;
1413
1414 if (work == NULL || work->pending || !work->enable_stall_check) {
1415 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1416 spin_unlock_irqrestore(&dev->event_lock, flags);
1417 return;
1418 }
1419
1420 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 1421 obj = work->pending_flip_obj;
a6c45cf0 1422 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 1423 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545
AR		 1424 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1425 obj->gtt_offset;
4e5359cd 1426 } else {
9db4a9c7 1427 int dspaddr = DSPADDR(intel_crtc->plane);
05394f39 1428 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
01f2c773 1429 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 1430 crtc->x * crtc->fb->bits_per_pixel/8);
1431 }
1432
1433 spin_unlock_irqrestore(&dev->event_lock, flags);
1434
1435 if (stall_detected) {
1436 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1437 intel_prepare_page_flip(dev, intel_crtc->plane);
1438 }
1439}
1440
42f52ef8
KP		 1441/* Called from drm generic code, passed 'crtc' which
1442 * we use as a pipe index
1443 */
f71d4af4 1444static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1445{
1446 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1447 unsigned long irqflags;
71e0ffa5 1448
5eddb70b 1449 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 1450 return -EINVAL;
0a3e67a4 1451
1ec14ad3 1452 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 1453 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 1454 i915_enable_pipestat(dev_priv, pipe,
1455 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 1456 else
7c463586
KP		 1457 i915_enable_pipestat(dev_priv, pipe,
1458 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 1459
1460 /* maintain vblank delivery even in deep C-states */
1461 if (dev_priv->info->gen == 3)
6b26c86d 1462 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 1463 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 1464
0a3e67a4
JB		 1465 return 0;
1466}
1467
f71d4af4 1468static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1469{
1470 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1471 unsigned long irqflags;
1472
1473 if (!i915_pipe_enabled(dev, pipe))
1474 return -EINVAL;
1475
1476 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1477 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1478 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
f796cf8f
JB		 1479 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1480
1481 return 0;
1482}
1483
f71d4af4 1484static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1485{
1486 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1487 unsigned long irqflags;
1488
1489 if (!i915_pipe_enabled(dev, pipe))
1490 return -EINVAL;
1491
1492 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1493 ironlake_enable_display_irq(dev_priv,
1494 DE_PIPEA_VBLANK_IVB << (5 * pipe));
b1f14ad0
JB		 1495 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1496
1497 return 0;
1498}
1499
7e231dbe
JB		 1500static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1501{
1502 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1503 unsigned long irqflags;
1504 u32 dpfl, imr;
1505
1506 if (!i915_pipe_enabled(dev, pipe))
1507 return -EINVAL;
1508
1509 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1510 dpfl = I915_READ(VLV_DPFLIPSTAT);
1511 imr = I915_READ(VLV_IMR);
1512 if (pipe == 0) {
1513 dpfl |= PIPEA_VBLANK_INT_EN;
1514 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1515 } else {
1516 dpfl |= PIPEA_VBLANK_INT_EN;
1517 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1518 }
1519 I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1520 I915_WRITE(VLV_IMR, imr);
1521 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1522
1523 return 0;
1524}
1525
42f52ef8
KP		 1526/* Called from drm generic code, passed 'crtc' which
1527 * we use as a pipe index
1528 */
f71d4af4 1529static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1530{
1531 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1532 unsigned long irqflags;
0a3e67a4 1533
1ec14ad3 1534 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 1535 if (dev_priv->info->gen == 3)
6b26c86d 1536 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 1537
f796cf8f
JB		 1538 i915_disable_pipestat(dev_priv, pipe,
1539 PIPE_VBLANK_INTERRUPT_ENABLE |
1540 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1541 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1542}
1543
f71d4af4 1544static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1545{
1546 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1547 unsigned long irqflags;
1548
1549 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1550 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1551 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1ec14ad3 1552 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 1553}
1554
f71d4af4 1555static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1556{
1557 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1558 unsigned long irqflags;
1559
1560 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1561 ironlake_disable_display_irq(dev_priv,
1562 DE_PIPEA_VBLANK_IVB << (pipe * 5));
b1f14ad0
JB		 1563 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1564}
1565
7e231dbe
JB		 1566static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1567{
1568 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1569 unsigned long irqflags;
1570 u32 dpfl, imr;
1571
1572 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1573 dpfl = I915_READ(VLV_DPFLIPSTAT);
1574 imr = I915_READ(VLV_IMR);
1575 if (pipe == 0) {
1576 dpfl &= ~PIPEA_VBLANK_INT_EN;
1577 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1578 } else {
1579 dpfl &= ~PIPEB_VBLANK_INT_EN;
1580 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1581 }
1582 I915_WRITE(VLV_IMR, imr);
1583 I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1584 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1585}
1586
893eead0
CW		 1587static u32
1588ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 1589{
893eead0
CW		 1590 return list_entry(ring->request_list.prev,
1591 struct drm_i915_gem_request, list)->seqno;
1592}
1593
1594static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1595{
1596 if (list_empty(&ring->request_list) ||
1597 i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1598 /* Issue a wake-up to catch stuck h/w. */
9574b3fe
BW		 1599 if (waitqueue_active(&ring->irq_queue)) {
1600 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1601 ring->name);
893eead0
CW		 1602 wake_up_all(&ring->irq_queue);
1603 *err = true;
1604 }
1605 return true;
1606 }
1607 return false;
f65d9421
BG		 1608}
1609
1ec14ad3
CW		 1610static bool kick_ring(struct intel_ring_buffer *ring)
1611{
1612 struct drm_device *dev = ring->dev;
1613 struct drm_i915_private *dev_priv = dev->dev_private;
1614 u32 tmp = I915_READ_CTL(ring);
1615 if (tmp & RING_WAIT) {
1616 DRM_ERROR("Kicking stuck wait on %s\n",
1617 ring->name);
1618 I915_WRITE_CTL(ring, tmp);
1619 return true;
1620 }
1ec14ad3
CW		 1621 return false;
1622}
1623
d1e61e7f
CW		 1624static bool i915_hangcheck_hung(struct drm_device *dev)
1625{
1626 drm_i915_private_t *dev_priv = dev->dev_private;
1627
1628 if (dev_priv->hangcheck_count++ > 1) {
b4519513
CW		 1629 bool hung = true;
1630
d1e61e7f
CW		 1631 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1632 i915_handle_error(dev, true);
1633
1634 if (!IS_GEN2(dev)) {
b4519513
CW		 1635 struct intel_ring_buffer *ring;
1636 int i;
1637
d1e61e7f
CW		 1638 /* Is the chip hanging on a WAIT_FOR_EVENT?
1639 * If so we can simply poke the RB_WAIT bit
1640 * and break the hang. This should work on
1641 * all but the second generation chipsets.
1642 */
b4519513
CW		 1643 for_each_ring(ring, dev_priv, i)
1644 hung &= !kick_ring(ring);
d1e61e7f
CW		 1645 }
1646
b4519513 1647 return hung;
d1e61e7f
CW		 1648 }
1649
1650 return false;
1651}
1652
f65d9421
BG		 1653/**
1654 * This is called when the chip hasn't reported back with completed
1655 * batchbuffers in a long time. The first time this is called we simply record
1656 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1657 * again, we assume the chip is wedged and try to fix it.
1658 */
1659void i915_hangcheck_elapsed(unsigned long data)
1660{
1661 struct drm_device *dev = (struct drm_device *)data;
1662 drm_i915_private_t *dev_priv = dev->dev_private;
b4519513
CW		 1663 uint32_t acthd[I915_NUM_RINGS], instdone, instdone1;
1664 struct intel_ring_buffer *ring;
1665 bool err = false, idle;
1666 int i;
893eead0 1667
3e0dc6b0
BW		 1668 if (!i915_enable_hangcheck)
1669 return;
1670
b4519513
CW		 1671 memset(acthd, 0, sizeof(acthd));
1672 idle = true;
1673 for_each_ring(ring, dev_priv, i) {
1674 idle &= i915_hangcheck_ring_idle(ring, &err);
1675 acthd[i] = intel_ring_get_active_head(ring);
1676 }
1677
893eead0 1678 /* If all work is done then ACTHD clearly hasn't advanced. */
b4519513 1679 if (idle) {
d1e61e7f
CW		 1680 if (err) {
1681 if (i915_hangcheck_hung(dev))
1682 return;
1683
893eead0 1684 goto repeat;
d1e61e7f
CW		 1685 }
1686
1687 dev_priv->hangcheck_count = 0;
893eead0
CW		 1688 return;
1689 }
b9201c14 1690
a6c45cf0 1691 if (INTEL_INFO(dev)->gen < 4) {
cbb465e7
CW		 1692 instdone = I915_READ(INSTDONE);
1693 instdone1 = 0;
1694 } else {
cbb465e7
CW		 1695 instdone = I915_READ(INSTDONE_I965);
1696 instdone1 = I915_READ(INSTDONE1);
1697 }
b4519513
CW		 1698
1699 if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 &&
cbb465e7
CW		 1700 dev_priv->last_instdone == instdone &&
1701 dev_priv->last_instdone1 == instdone1) {
d1e61e7f 1702 if (i915_hangcheck_hung(dev))
cbb465e7 1703 return;
cbb465e7
CW		 1704 } else {
1705 dev_priv->hangcheck_count = 0;
1706
b4519513 1707 memcpy(dev_priv->last_acthd, acthd, sizeof(acthd));
cbb465e7
CW		 1708 dev_priv->last_instdone = instdone;
1709 dev_priv->last_instdone1 = instdone1;
1710 }
f65d9421 1711
893eead0 1712repeat:
f65d9421 1713 /* Reset timer case chip hangs without another request being added */
b3b079db
CW		 1714 mod_timer(&dev_priv->hangcheck_timer,
1715 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
f65d9421
BG		 1716}
1717
1da177e4
LT		 1718/* drm_dma.h hooks
1719*/
f71d4af4 1720static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 1721{
1722 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1723
4697995b
JB		 1724 atomic_set(&dev_priv->irq_received, 0);
1725
4697995b 1726
e3689190
BW		 1727 if (IS_IVYBRIDGE(dev))
1728 INIT_WORK(&dev_priv->parity_error_work, ivybridge_parity_work);
1729
036a4a7d 1730 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 1731
036a4a7d
ZW		 1732 /* XXX hotplug from PCH */
1733
1734 I915_WRITE(DEIMR, 0xffffffff);
1735 I915_WRITE(DEIER, 0x0);
3143a2bf 1736 POSTING_READ(DEIER);
036a4a7d
ZW		 1737
1738 /* and GT */
1739 I915_WRITE(GTIMR, 0xffffffff);
1740 I915_WRITE(GTIER, 0x0);
3143a2bf 1741 POSTING_READ(GTIER);
c650156a
ZW		 1742
1743 /* south display irq */
1744 I915_WRITE(SDEIMR, 0xffffffff);
1745 I915_WRITE(SDEIER, 0x0);
3143a2bf 1746 POSTING_READ(SDEIER);
036a4a7d
ZW		 1747}
1748
7e231dbe
JB		 1749static void valleyview_irq_preinstall(struct drm_device *dev)
1750{
1751 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1752 int pipe;
1753
1754 atomic_set(&dev_priv->irq_received, 0);
1755
7e231dbe
JB		 1756 /* VLV magic */
1757 I915_WRITE(VLV_IMR, 0);
1758 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1759 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1760 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1761
7e231dbe
JB		 1762 /* and GT */
1763 I915_WRITE(GTIIR, I915_READ(GTIIR));
1764 I915_WRITE(GTIIR, I915_READ(GTIIR));
1765 I915_WRITE(GTIMR, 0xffffffff);
1766 I915_WRITE(GTIER, 0x0);
1767 POSTING_READ(GTIER);
1768
1769 I915_WRITE(DPINVGTT, 0xff);
1770
1771 I915_WRITE(PORT_HOTPLUG_EN, 0);
1772 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1773 for_each_pipe(pipe)
1774 I915_WRITE(PIPESTAT(pipe), 0xffff);
1775 I915_WRITE(VLV_IIR, 0xffffffff);
1776 I915_WRITE(VLV_IMR, 0xffffffff);
1777 I915_WRITE(VLV_IER, 0x0);
1778 POSTING_READ(VLV_IER);
1779}
1780
7fe0b973
KP		 1781/*
1782 * Enable digital hotplug on the PCH, and configure the DP short pulse
1783 * duration to 2ms (which is the minimum in the Display Port spec)
1784 *
1785 * This register is the same on all known PCH chips.
1786 */
1787
1788static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1789{
1790 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1791 u32 hotplug;
1792
1793 hotplug = I915_READ(PCH_PORT_HOTPLUG);
1794 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1795 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1796 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1797 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1798 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1799}
1800
f71d4af4 1801static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d
ZW		 1802{
1803 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1804 /* enable kind of interrupts always enabled */
013d5aa2
JB		 1805 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1806 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1ec14ad3 1807 u32 render_irqs;
2d7b8366 1808 u32 hotplug_mask;
036a4a7d 1809
1ec14ad3 1810 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 1811
1812 /* should always can generate irq */
1813 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3
CW		 1814 I915_WRITE(DEIMR, dev_priv->irq_mask);
1815 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
3143a2bf 1816 POSTING_READ(DEIER);
036a4a7d 1817
1ec14ad3 1818 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 1819
1820 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 1821 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 1822
1ec14ad3
CW		 1823 if (IS_GEN6(dev))
1824 render_irqs =
1825 GT_USER_INTERRUPT |
e2a1e2f0
BW		 1826 GEN6_BSD_USER_INTERRUPT |
1827 GEN6_BLITTER_USER_INTERRUPT;
1ec14ad3
CW		 1828 else
1829 render_irqs =
88f23b8f 1830 GT_USER_INTERRUPT |
c6df541c 1831 GT_PIPE_NOTIFY |
1ec14ad3
CW		 1832 GT_BSD_USER_INTERRUPT;
1833 I915_WRITE(GTIER, render_irqs);
3143a2bf 1834 POSTING_READ(GTIER);
036a4a7d 1835
2d7b8366 1836 if (HAS_PCH_CPT(dev)) {
9035a97a
CW		 1837 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1838 SDE_PORTB_HOTPLUG_CPT |
1839 SDE_PORTC_HOTPLUG_CPT |
1840 SDE_PORTD_HOTPLUG_CPT);
2d7b8366 1841 } else {
9035a97a
CW		 1842 hotplug_mask = (SDE_CRT_HOTPLUG |
1843 SDE_PORTB_HOTPLUG |
1844 SDE_PORTC_HOTPLUG |
1845 SDE_PORTD_HOTPLUG |
1846 SDE_AUX_MASK);
2d7b8366
YL		 1847 }
1848
1ec14ad3 1849 dev_priv->pch_irq_mask = ~hotplug_mask;
c650156a
ZW		 1850
1851 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1ec14ad3
CW		 1852 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1853 I915_WRITE(SDEIER, hotplug_mask);
3143a2bf 1854 POSTING_READ(SDEIER);
c650156a 1855
7fe0b973
KP		 1856 ironlake_enable_pch_hotplug(dev);
1857
f97108d1
JB		 1858 if (IS_IRONLAKE_M(dev)) {
1859 /* Clear & enable PCU event interrupts */
1860 I915_WRITE(DEIIR, DE_PCU_EVENT);
1861 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1862 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1863 }
1864
036a4a7d
ZW		 1865 return 0;
1866}
1867
f71d4af4 1868static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 1869{
1870 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1871 /* enable kind of interrupts always enabled */
b615b57a
CW		 1872 u32 display_mask =
1873 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
1874 DE_PLANEC_FLIP_DONE_IVB |
1875 DE_PLANEB_FLIP_DONE_IVB |
1876 DE_PLANEA_FLIP_DONE_IVB;
b1f14ad0
JB		 1877 u32 render_irqs;
1878 u32 hotplug_mask;
1879
b1f14ad0
JB		 1880 dev_priv->irq_mask = ~display_mask;
1881
1882 /* should always can generate irq */
1883 I915_WRITE(DEIIR, I915_READ(DEIIR));
1884 I915_WRITE(DEIMR, dev_priv->irq_mask);
b615b57a
CW		 1885 I915_WRITE(DEIER,
1886 display_mask |
1887 DE_PIPEC_VBLANK_IVB |
1888 DE_PIPEB_VBLANK_IVB |
1889 DE_PIPEA_VBLANK_IVB);
b1f14ad0
JB		 1890 POSTING_READ(DEIER);
1891
1892 dev_priv->gt_irq_mask = ~0;
1893
1894 I915_WRITE(GTIIR, I915_READ(GTIIR));
1895 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1896
e2a1e2f0
BW		 1897 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
1898 GEN6_BLITTER_USER_INTERRUPT;
b1f14ad0
JB		 1899 I915_WRITE(GTIER, render_irqs);
1900 POSTING_READ(GTIER);
1901
1902 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1903 SDE_PORTB_HOTPLUG_CPT |
1904 SDE_PORTC_HOTPLUG_CPT |
1905 SDE_PORTD_HOTPLUG_CPT);
1906 dev_priv->pch_irq_mask = ~hotplug_mask;
1907
1908 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1909 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1910 I915_WRITE(SDEIER, hotplug_mask);
1911 POSTING_READ(SDEIER);
1912
7fe0b973
KP		 1913 ironlake_enable_pch_hotplug(dev);
1914
b1f14ad0
JB		 1915 return 0;
1916}
1917
7e231dbe
JB		 1918static int valleyview_irq_postinstall(struct drm_device *dev)
1919{
1920 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1921 u32 render_irqs;
1922 u32 enable_mask;
1923 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1924 u16 msid;
1925
1926 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
1927 enable_mask |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1928 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1929
1930 dev_priv->irq_mask = ~enable_mask;
1931
7e231dbe
JB		 1932 dev_priv->pipestat[0] = 0;
1933 dev_priv->pipestat[1] = 0;
1934
7e231dbe
JB		 1935 /* Hack for broken MSIs on VLV */
1936 pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
1937 pci_read_config_word(dev->pdev, 0x98, &msid);
1938 msid &= 0xff; /* mask out delivery bits */
1939 msid |= (1<<14);
1940 pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
1941
1942 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
1943 I915_WRITE(VLV_IER, enable_mask);
1944 I915_WRITE(VLV_IIR, 0xffffffff);
1945 I915_WRITE(PIPESTAT(0), 0xffff);
1946 I915_WRITE(PIPESTAT(1), 0xffff);
1947 POSTING_READ(VLV_IER);
1948
1949 I915_WRITE(VLV_IIR, 0xffffffff);
1950 I915_WRITE(VLV_IIR, 0xffffffff);
1951
1952 render_irqs = GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
1953 GT_GEN6_BLT_CS_ERROR_INTERRUPT |
e2a1e2f0 1954 GT_GEN6_BLT_USER_INTERRUPT |
7e231dbe
JB		 1955 GT_GEN6_BSD_USER_INTERRUPT |
1956 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
1957 GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
1958 GT_PIPE_NOTIFY |
1959 GT_RENDER_CS_ERROR_INTERRUPT |
1960 GT_SYNC_STATUS |
1961 GT_USER_INTERRUPT;
1962
1963 dev_priv->gt_irq_mask = ~render_irqs;
1964
1965 I915_WRITE(GTIIR, I915_READ(GTIIR));
1966 I915_WRITE(GTIIR, I915_READ(GTIIR));
1967 I915_WRITE(GTIMR, 0);
1968 I915_WRITE(GTIER, render_irqs);
1969 POSTING_READ(GTIER);
1970
1971 /* ack & enable invalid PTE error interrupts */
1972#if 0 /* FIXME: add support to irq handler for checking these bits */
1973 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
1974 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
1975#endif
1976
1977 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1978#if 0 /* FIXME: check register definitions; some have moved */
1979 /* Note HDMI and DP share bits */
1980 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1981 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1982 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1983 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1984 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1985 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1986 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1987 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1988 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1989 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1990 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1991 hotplug_en |= CRT_HOTPLUG_INT_EN;
1992 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1993 }
1994#endif
1995
1996 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1997
1998 return 0;
1999}
2000
7e231dbe
JB		 2001static void valleyview_irq_uninstall(struct drm_device *dev)
2002{
2003 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2004 int pipe;
2005
2006 if (!dev_priv)
2007 return;
2008
7e231dbe
JB		 2009 for_each_pipe(pipe)
2010 I915_WRITE(PIPESTAT(pipe), 0xffff);
2011
2012 I915_WRITE(HWSTAM, 0xffffffff);
2013 I915_WRITE(PORT_HOTPLUG_EN, 0);
2014 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2015 for_each_pipe(pipe)
2016 I915_WRITE(PIPESTAT(pipe), 0xffff);
2017 I915_WRITE(VLV_IIR, 0xffffffff);
2018 I915_WRITE(VLV_IMR, 0xffffffff);
2019 I915_WRITE(VLV_IER, 0x0);
2020 POSTING_READ(VLV_IER);
2021}
2022
f71d4af4 2023static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 2024{
2025 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 2026
2027 if (!dev_priv)
2028 return;
2029
036a4a7d
ZW		 2030 I915_WRITE(HWSTAM, 0xffffffff);
2031
2032 I915_WRITE(DEIMR, 0xffffffff);
2033 I915_WRITE(DEIER, 0x0);
2034 I915_WRITE(DEIIR, I915_READ(DEIIR));
2035
2036 I915_WRITE(GTIMR, 0xffffffff);
2037 I915_WRITE(GTIER, 0x0);
2038 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f
KP		 2039
2040 I915_WRITE(SDEIMR, 0xffffffff);
2041 I915_WRITE(SDEIER, 0x0);
2042 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
036a4a7d
ZW		 2043}
2044
a266c7d5 2045static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 2046{
2047 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2048 int pipe;
91e3738e 2049
a266c7d5 2050 atomic_set(&dev_priv->irq_received, 0);
5ca58282 2051
9db4a9c7
JB		 2052 for_each_pipe(pipe)
2053 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 2054 I915_WRITE16(IMR, 0xffff);
2055 I915_WRITE16(IER, 0x0);
2056 POSTING_READ16(IER);
c2798b19
CW		 2057}
2058
2059static int i8xx_irq_postinstall(struct drm_device *dev)
2060{
2061 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2062
c2798b19
CW		 2063 dev_priv->pipestat[0] = 0;
2064 dev_priv->pipestat[1] = 0;
2065
2066 I915_WRITE16(EMR,
2067 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2068
2069 /* Unmask the interrupts that we always want on. */
2070 dev_priv->irq_mask =
2071 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2072 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2073 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2074 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2075 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2076 I915_WRITE16(IMR, dev_priv->irq_mask);
2077
2078 I915_WRITE16(IER,
2079 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2080 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2081 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2082 I915_USER_INTERRUPT);
2083 POSTING_READ16(IER);
2084
2085 return 0;
2086}
2087
2088static irqreturn_t i8xx_irq_handler(DRM_IRQ_ARGS)
2089{
2090 struct drm_device *dev = (struct drm_device *) arg;
2091 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 2092 u16 iir, new_iir;
2093 u32 pipe_stats[2];
2094 unsigned long irqflags;
2095 int irq_received;
2096 int pipe;
2097 u16 flip_mask =
2098 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2099 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2100
2101 atomic_inc(&dev_priv->irq_received);
2102
2103 iir = I915_READ16(IIR);
2104 if (iir == 0)
2105 return IRQ_NONE;
2106
2107 while (iir & ~flip_mask) {
2108 /* Can't rely on pipestat interrupt bit in iir as it might
2109 * have been cleared after the pipestat interrupt was received.
2110 * It doesn't set the bit in iir again, but it still produces
2111 * interrupts (for non-MSI).
2112 */
2113 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2114 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2115 i915_handle_error(dev, false);
2116
2117 for_each_pipe(pipe) {
2118 int reg = PIPESTAT(pipe);
2119 pipe_stats[pipe] = I915_READ(reg);
2120
2121 /*
2122 * Clear the PIPE*STAT regs before the IIR
2123 */
2124 if (pipe_stats[pipe] & 0x8000ffff) {
2125 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2126 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2127 pipe_name(pipe));
2128 I915_WRITE(reg, pipe_stats[pipe]);
2129 irq_received = 1;
2130 }
2131 }
2132 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2133
2134 I915_WRITE16(IIR, iir & ~flip_mask);
2135 new_iir = I915_READ16(IIR); /* Flush posted writes */
2136
d05c617e 2137 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 2138
2139 if (iir & I915_USER_INTERRUPT)
2140 notify_ring(dev, &dev_priv->ring[RCS]);
2141
2142 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2143 drm_handle_vblank(dev, 0)) {
2144 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2145 intel_prepare_page_flip(dev, 0);
2146 intel_finish_page_flip(dev, 0);
2147 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2148 }
2149 }
2150
2151 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2152 drm_handle_vblank(dev, 1)) {
2153 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2154 intel_prepare_page_flip(dev, 1);
2155 intel_finish_page_flip(dev, 1);
2156 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2157 }
2158 }
2159
2160 iir = new_iir;
2161 }
2162
2163 return IRQ_HANDLED;
2164}
2165
2166static void i8xx_irq_uninstall(struct drm_device * dev)
2167{
2168 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2169 int pipe;
2170
c2798b19
CW		 2171 for_each_pipe(pipe) {
2172 /* Clear enable bits; then clear status bits */
2173 I915_WRITE(PIPESTAT(pipe), 0);
2174 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2175 }
2176 I915_WRITE16(IMR, 0xffff);
2177 I915_WRITE16(IER, 0x0);
2178 I915_WRITE16(IIR, I915_READ16(IIR));
2179}
2180
a266c7d5
CW		 2181static void i915_irq_preinstall(struct drm_device * dev)
2182{
2183 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2184 int pipe;
2185
2186 atomic_set(&dev_priv->irq_received, 0);
2187
2188 if (I915_HAS_HOTPLUG(dev)) {
2189 I915_WRITE(PORT_HOTPLUG_EN, 0);
2190 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2191 }
2192
00d98ebd 2193 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 2194 for_each_pipe(pipe)
2195 I915_WRITE(PIPESTAT(pipe), 0);
2196 I915_WRITE(IMR, 0xffffffff);
2197 I915_WRITE(IER, 0x0);
2198 POSTING_READ(IER);
2199}
2200
2201static int i915_irq_postinstall(struct drm_device *dev)
2202{
2203 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 2204 u32 enable_mask;
a266c7d5 2205
a266c7d5
CW		 2206 dev_priv->pipestat[0] = 0;
2207 dev_priv->pipestat[1] = 0;
2208
38bde180
CW		 2209 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2210
2211 /* Unmask the interrupts that we always want on. */
2212 dev_priv->irq_mask =
2213 ~(I915_ASLE_INTERRUPT |
2214 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2215 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2216 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2217 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2218 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2219
2220 enable_mask =
2221 I915_ASLE_INTERRUPT |
2222 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2223 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2224 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2225 I915_USER_INTERRUPT;
2226
a266c7d5
CW		 2227 if (I915_HAS_HOTPLUG(dev)) {
2228 /* Enable in IER... */
2229 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2230 /* and unmask in IMR */
2231 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2232 }
2233
a266c7d5
CW		 2234 I915_WRITE(IMR, dev_priv->irq_mask);
2235 I915_WRITE(IER, enable_mask);
2236 POSTING_READ(IER);
2237
2238 if (I915_HAS_HOTPLUG(dev)) {
2239 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2240
a266c7d5
CW		 2241 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2242 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2243 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2244 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2245 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2246 hotplug_en |= HDMID_HOTPLUG_INT_EN;
084b612e 2247 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
a266c7d5 2248 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
084b612e 2249 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
a266c7d5
CW		 2250 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2251 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2252 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5
CW		 2253 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2254 }
2255
2256 /* Ignore TV since it's buggy */
2257
2258 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2259 }
2260
2261 intel_opregion_enable_asle(dev);
2262
2263 return 0;
2264}
2265
2266static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
2267{
2268 struct drm_device *dev = (struct drm_device *) arg;
2269 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 2270 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 2271 unsigned long irqflags;
38bde180
CW		 2272 u32 flip_mask =
2273 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2274 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2275 u32 flip[2] = {
2276 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2277 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2278 };
2279 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 2280
2281 atomic_inc(&dev_priv->irq_received);
2282
2283 iir = I915_READ(IIR);
38bde180
CW		 2284 do {
2285 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 2286 bool blc_event = false;
a266c7d5
CW		 2287
2288 /* Can't rely on pipestat interrupt bit in iir as it might
2289 * have been cleared after the pipestat interrupt was received.
2290 * It doesn't set the bit in iir again, but it still produces
2291 * interrupts (for non-MSI).
2292 */
2293 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2294 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2295 i915_handle_error(dev, false);
2296
2297 for_each_pipe(pipe) {
2298 int reg = PIPESTAT(pipe);
2299 pipe_stats[pipe] = I915_READ(reg);
2300
38bde180 2301 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 2302 if (pipe_stats[pipe] & 0x8000ffff) {
2303 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2304 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2305 pipe_name(pipe));
2306 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 2307 irq_received = true;
a266c7d5
CW		 2308 }
2309 }
2310 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2311
2312 if (!irq_received)
2313 break;
2314
a266c7d5
CW		 2315 /* Consume port. Then clear IIR or we'll miss events */
2316 if ((I915_HAS_HOTPLUG(dev)) &&
2317 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2318 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2319
2320 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2321 hotplug_status);
2322 if (hotplug_status & dev_priv->hotplug_supported_mask)
2323 queue_work(dev_priv->wq,
2324 &dev_priv->hotplug_work);
2325
2326 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 2327 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 2328 }
2329
38bde180 2330 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2331 new_iir = I915_READ(IIR); /* Flush posted writes */
2332
a266c7d5
CW		 2333 if (iir & I915_USER_INTERRUPT)
2334 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 2335
a266c7d5 2336 for_each_pipe(pipe) {
38bde180
CW		 2337 int plane = pipe;
2338 if (IS_MOBILE(dev))
2339 plane = !plane;
8291ee90 2340 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2341 drm_handle_vblank(dev, pipe)) {
38bde180
CW		 2342 if (iir & flip[plane]) {
2343 intel_prepare_page_flip(dev, plane);
2344 intel_finish_page_flip(dev, pipe);
2345 flip_mask &= ~flip[plane];
2346 }
a266c7d5
CW		 2347 }
2348
2349 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2350 blc_event = true;
2351 }
2352
a266c7d5
CW		 2353 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2354 intel_opregion_asle_intr(dev);
2355
2356 /* With MSI, interrupts are only generated when iir
2357 * transitions from zero to nonzero. If another bit got
2358 * set while we were handling the existing iir bits, then
2359 * we would never get another interrupt.
2360 *
2361 * This is fine on non-MSI as well, as if we hit this path
2362 * we avoid exiting the interrupt handler only to generate
2363 * another one.
2364 *
2365 * Note that for MSI this could cause a stray interrupt report
2366 * if an interrupt landed in the time between writing IIR and
2367 * the posting read. This should be rare enough to never
2368 * trigger the 99% of 100,000 interrupts test for disabling
2369 * stray interrupts.
2370 */
38bde180 2371 ret = IRQ_HANDLED;
a266c7d5 2372 iir = new_iir;
38bde180 2373 } while (iir & ~flip_mask);
a266c7d5 2374
d05c617e 2375 i915_update_dri1_breadcrumb(dev);
8291ee90 2376
a266c7d5
CW		 2377 return ret;
2378}
2379
2380static void i915_irq_uninstall(struct drm_device * dev)
2381{
2382 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2383 int pipe;
2384
a266c7d5
CW		 2385 if (I915_HAS_HOTPLUG(dev)) {
2386 I915_WRITE(PORT_HOTPLUG_EN, 0);
2387 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2388 }
2389
00d98ebd 2390 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 2391 for_each_pipe(pipe) {
2392 /* Clear enable bits; then clear status bits */
a266c7d5 2393 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 2394 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2395 }
a266c7d5
CW		 2396 I915_WRITE(IMR, 0xffffffff);
2397 I915_WRITE(IER, 0x0);
2398
a266c7d5
CW		 2399 I915_WRITE(IIR, I915_READ(IIR));
2400}
2401
2402static void i965_irq_preinstall(struct drm_device * dev)
2403{
2404 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2405 int pipe;
2406
2407 atomic_set(&dev_priv->irq_received, 0);
2408
adca4730
CW		 2409 I915_WRITE(PORT_HOTPLUG_EN, 0);
2410 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2411
2412 I915_WRITE(HWSTAM, 0xeffe);
2413 for_each_pipe(pipe)
2414 I915_WRITE(PIPESTAT(pipe), 0);
2415 I915_WRITE(IMR, 0xffffffff);
2416 I915_WRITE(IER, 0x0);
2417 POSTING_READ(IER);
2418}
2419
2420static int i965_irq_postinstall(struct drm_device *dev)
2421{
2422 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
adca4730 2423 u32 hotplug_en;
bbba0a97 2424 u32 enable_mask;
a266c7d5
CW		 2425 u32 error_mask;
2426
a266c7d5 2427 /* Unmask the interrupts that we always want on. */
bbba0a97 2428 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 2429 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 2430 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2431 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2432 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2433 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2434 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2435
2436 enable_mask = ~dev_priv->irq_mask;
2437 enable_mask |= I915_USER_INTERRUPT;
2438
2439 if (IS_G4X(dev))
2440 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5
CW		 2441
2442 dev_priv->pipestat[0] = 0;
2443 dev_priv->pipestat[1] = 0;
2444
a266c7d5
CW		 2445 /*
2446 * Enable some error detection, note the instruction error mask
2447 * bit is reserved, so we leave it masked.
2448 */
2449 if (IS_G4X(dev)) {
2450 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2451 GM45_ERROR_MEM_PRIV |
2452 GM45_ERROR_CP_PRIV |
2453 I915_ERROR_MEMORY_REFRESH);
2454 } else {
2455 error_mask = ~(I915_ERROR_PAGE_TABLE |
2456 I915_ERROR_MEMORY_REFRESH);
2457 }
2458 I915_WRITE(EMR, error_mask);
2459
2460 I915_WRITE(IMR, dev_priv->irq_mask);
2461 I915_WRITE(IER, enable_mask);
2462 POSTING_READ(IER);
2463
adca4730
CW		 2464 /* Note HDMI and DP share hotplug bits */
2465 hotplug_en = 0;
2466 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2467 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2468 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2469 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2470 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2471 hotplug_en |= HDMID_HOTPLUG_INT_EN;
084b612e
CW		 2472 if (IS_G4X(dev)) {
2473 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
2474 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2475 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
2476 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2477 } else {
2478 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
2479 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2480 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
2481 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2482 }
adca4730
CW		 2483 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2484 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5 2485
adca4730
CW		 2486 /* Programming the CRT detection parameters tends
2487 to generate a spurious hotplug event about three
2488 seconds later. So just do it once.
2489 */
2490 if (IS_G4X(dev))
2491 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2492 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2493 }
a266c7d5 2494
adca4730 2495 /* Ignore TV since it's buggy */
a266c7d5 2496
adca4730 2497 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
a266c7d5
CW		 2498
2499 intel_opregion_enable_asle(dev);
2500
2501 return 0;
2502}
2503
2504static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS)
2505{
2506 struct drm_device *dev = (struct drm_device *) arg;
2507 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 2508 u32 iir, new_iir;
2509 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 2510 unsigned long irqflags;
2511 int irq_received;
2512 int ret = IRQ_NONE, pipe;
a266c7d5
CW		 2513
2514 atomic_inc(&dev_priv->irq_received);
2515
2516 iir = I915_READ(IIR);
2517
a266c7d5 2518 for (;;) {
2c8ba29f
CW		 2519 bool blc_event = false;
2520
a266c7d5
CW		 2521 irq_received = iir != 0;
2522
2523 /* Can't rely on pipestat interrupt bit in iir as it might
2524 * have been cleared after the pipestat interrupt was received.
2525 * It doesn't set the bit in iir again, but it still produces
2526 * interrupts (for non-MSI).
2527 */
2528 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2529 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2530 i915_handle_error(dev, false);
2531
2532 for_each_pipe(pipe) {
2533 int reg = PIPESTAT(pipe);
2534 pipe_stats[pipe] = I915_READ(reg);
2535
2536 /*
2537 * Clear the PIPE*STAT regs before the IIR
2538 */
2539 if (pipe_stats[pipe] & 0x8000ffff) {
2540 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2541 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2542 pipe_name(pipe));
2543 I915_WRITE(reg, pipe_stats[pipe]);
2544 irq_received = 1;
2545 }
2546 }
2547 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2548
2549 if (!irq_received)
2550 break;
2551
2552 ret = IRQ_HANDLED;
2553
2554 /* Consume port. Then clear IIR or we'll miss events */
adca4730 2555 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
a266c7d5
CW		 2556 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2557
2558 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2559 hotplug_status);
2560 if (hotplug_status & dev_priv->hotplug_supported_mask)
2561 queue_work(dev_priv->wq,
2562 &dev_priv->hotplug_work);
2563
2564 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2565 I915_READ(PORT_HOTPLUG_STAT);
2566 }
2567
2568 I915_WRITE(IIR, iir);
2569 new_iir = I915_READ(IIR); /* Flush posted writes */
2570
a266c7d5
CW		 2571 if (iir & I915_USER_INTERRUPT)
2572 notify_ring(dev, &dev_priv->ring[RCS]);
2573 if (iir & I915_BSD_USER_INTERRUPT)
2574 notify_ring(dev, &dev_priv->ring[VCS]);
2575
4f7d1e79 2576 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
a266c7d5 2577 intel_prepare_page_flip(dev, 0);
a266c7d5 2578
4f7d1e79 2579 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
a266c7d5 2580 intel_prepare_page_flip(dev, 1);
a266c7d5
CW		 2581
2582 for_each_pipe(pipe) {
2c8ba29f 2583 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2584 drm_handle_vblank(dev, pipe)) {
4f7d1e79
CW		 2585 i915_pageflip_stall_check(dev, pipe);
2586 intel_finish_page_flip(dev, pipe);
a266c7d5
CW		 2587 }
2588
2589 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2590 blc_event = true;
2591 }
2592
2593
2594 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2595 intel_opregion_asle_intr(dev);
2596
2597 /* With MSI, interrupts are only generated when iir
2598 * transitions from zero to nonzero. If another bit got
2599 * set while we were handling the existing iir bits, then
2600 * we would never get another interrupt.
2601 *
2602 * This is fine on non-MSI as well, as if we hit this path
2603 * we avoid exiting the interrupt handler only to generate
2604 * another one.
2605 *
2606 * Note that for MSI this could cause a stray interrupt report
2607 * if an interrupt landed in the time between writing IIR and
2608 * the posting read. This should be rare enough to never
2609 * trigger the 99% of 100,000 interrupts test for disabling
2610 * stray interrupts.
2611 */
2612 iir = new_iir;
2613 }
2614
d05c617e 2615 i915_update_dri1_breadcrumb(dev);
2c8ba29f 2616
a266c7d5
CW		 2617 return ret;
2618}
2619
2620static void i965_irq_uninstall(struct drm_device * dev)
2621{
2622 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2623 int pipe;
2624
2625 if (!dev_priv)
2626 return;
2627
adca4730
CW		 2628 I915_WRITE(PORT_HOTPLUG_EN, 0);
2629 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2630
2631 I915_WRITE(HWSTAM, 0xffffffff);
2632 for_each_pipe(pipe)
2633 I915_WRITE(PIPESTAT(pipe), 0);
2634 I915_WRITE(IMR, 0xffffffff);
2635 I915_WRITE(IER, 0x0);
2636
2637 for_each_pipe(pipe)
2638 I915_WRITE(PIPESTAT(pipe),
2639 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2640 I915_WRITE(IIR, I915_READ(IIR));
2641}
2642
f71d4af4
JB		 2643void intel_irq_init(struct drm_device *dev)
2644{
8b2e326d
CW		 2645 struct drm_i915_private *dev_priv = dev->dev_private;
2646
2647 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2648 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
2649 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
2650
f71d4af4
JB		 2651 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2652 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7d4e146f 2653 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 2654 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2655 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2656 }
2657
c3613de9
KP		 2658 if (drm_core_check_feature(dev, DRIVER_MODESET))
2659 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2660 else
2661 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 2662 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2663
7e231dbe
JB		 2664 if (IS_VALLEYVIEW(dev)) {
2665 dev->driver->irq_handler = valleyview_irq_handler;
2666 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2667 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2668 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2669 dev->driver->enable_vblank = valleyview_enable_vblank;
2670 dev->driver->disable_vblank = valleyview_disable_vblank;
2671 } else if (IS_IVYBRIDGE(dev)) {
f71d4af4
JB		 2672 /* Share pre & uninstall handlers with ILK/SNB */
2673 dev->driver->irq_handler = ivybridge_irq_handler;
2674 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2675 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2676 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2677 dev->driver->enable_vblank = ivybridge_enable_vblank;
2678 dev->driver->disable_vblank = ivybridge_disable_vblank;
7d4e146f
ED		 2679 } else if (IS_HASWELL(dev)) {
2680 /* Share interrupts handling with IVB */
2681 dev->driver->irq_handler = ivybridge_irq_handler;
2682 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2683 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2684 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2685 dev->driver->enable_vblank = ivybridge_enable_vblank;
2686 dev->driver->disable_vblank = ivybridge_disable_vblank;
f71d4af4
JB		 2687 } else if (HAS_PCH_SPLIT(dev)) {
2688 dev->driver->irq_handler = ironlake_irq_handler;
2689 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2690 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2691 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2692 dev->driver->enable_vblank = ironlake_enable_vblank;
2693 dev->driver->disable_vblank = ironlake_disable_vblank;
2694 } else {
c2798b19
CW		 2695 if (INTEL_INFO(dev)->gen == 2) {
2696 dev->driver->irq_preinstall = i8xx_irq_preinstall;
2697 dev->driver->irq_postinstall = i8xx_irq_postinstall;
2698 dev->driver->irq_handler = i8xx_irq_handler;
2699 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5 2700 } else if (INTEL_INFO(dev)->gen == 3) {
4f7d1e79
CW		 2701 /* IIR "flip pending" means done if this bit is set */
2702 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
2703
a266c7d5
CW		 2704 dev->driver->irq_preinstall = i915_irq_preinstall;
2705 dev->driver->irq_postinstall = i915_irq_postinstall;
2706 dev->driver->irq_uninstall = i915_irq_uninstall;
2707 dev->driver->irq_handler = i915_irq_handler;
c2798b19 2708 } else {
a266c7d5
CW		 2709 dev->driver->irq_preinstall = i965_irq_preinstall;
2710 dev->driver->irq_postinstall = i965_irq_postinstall;
2711 dev->driver->irq_uninstall = i965_irq_uninstall;
2712 dev->driver->irq_handler = i965_irq_handler;
c2798b19 2713 }
f71d4af4
JB		 2714 dev->driver->enable_vblank = i915_enable_vblank;
2715 dev->driver->disable_vblank = i915_disable_vblank;
2716 }
2717}
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