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drm/i915: add workarounds to gen7_render_ring_flush
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / i915_irq.c
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0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
1da177e4
LT		 33#include "drmP.h"
34#include "drm.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
1c5d22f7 37#include "i915_trace.h"
79e53945 38#include "intel_drv.h"
1da177e4 39
036a4a7d 40/* For display hotplug interrupt */
995b6762 41static void
f2b115e6 42ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 43{
1ec14ad3
CW		 44 if ((dev_priv->irq_mask & mask) != 0) {
45 dev_priv->irq_mask &= ~mask;
46 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 47 POSTING_READ(DEIMR);
036a4a7d
ZW		 48 }
49}
50
51static inline void
f2b115e6 52ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 53{
1ec14ad3
CW		 54 if ((dev_priv->irq_mask & mask) != mask) {
55 dev_priv->irq_mask |= mask;
56 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 57 POSTING_READ(DEIMR);
036a4a7d
ZW		 58 }
59}
60
7c463586
KP		 61void
62i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
63{
64 if ((dev_priv->pipestat[pipe] & mask) != mask) {
9db4a9c7 65 u32 reg = PIPESTAT(pipe);
7c463586
KP		 66
67 dev_priv->pipestat[pipe] |= mask;
68 /* Enable the interrupt, clear any pending status */
69 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
3143a2bf 70 POSTING_READ(reg);
7c463586
KP		 71 }
72}
73
74void
75i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
76{
77 if ((dev_priv->pipestat[pipe] & mask) != 0) {
9db4a9c7 78 u32 reg = PIPESTAT(pipe);
7c463586
KP		 79
80 dev_priv->pipestat[pipe] &= ~mask;
81 I915_WRITE(reg, dev_priv->pipestat[pipe]);
3143a2bf 82 POSTING_READ(reg);
7c463586
KP		 83 }
84}
85
01c66889
ZY		 86/**
87 * intel_enable_asle - enable ASLE interrupt for OpRegion
88 */
1ec14ad3 89void intel_enable_asle(struct drm_device *dev)
01c66889 90{
1ec14ad3
CW		 91 drm_i915_private_t *dev_priv = dev->dev_private;
92 unsigned long irqflags;
93
7e231dbe
JB		 94 /* FIXME: opregion/asle for VLV */
95 if (IS_VALLEYVIEW(dev))
96 return;
97
1ec14ad3 98 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 99
c619eed4 100 if (HAS_PCH_SPLIT(dev))
f2b115e6 101 ironlake_enable_display_irq(dev_priv, DE_GSE);
edcb49ca 102 else {
01c66889 103 i915_enable_pipestat(dev_priv, 1,
d874bcff 104 PIPE_LEGACY_BLC_EVENT_ENABLE);
a6c45cf0 105 if (INTEL_INFO(dev)->gen >= 4)
edcb49ca 106 i915_enable_pipestat(dev_priv, 0,
d874bcff 107 PIPE_LEGACY_BLC_EVENT_ENABLE);
edcb49ca 108 }
1ec14ad3
CW		 109
110 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 111}
112
0a3e67a4
JB		 113/**
114 * i915_pipe_enabled - check if a pipe is enabled
115 * @dev: DRM device
116 * @pipe: pipe to check
117 *
118 * Reading certain registers when the pipe is disabled can hang the chip.
119 * Use this routine to make sure the PLL is running and the pipe is active
120 * before reading such registers if unsure.
121 */
122static int
123i915_pipe_enabled(struct drm_device *dev, int pipe)
124{
125 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
5eddb70b 126 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
0a3e67a4
JB		 127}
128
42f52ef8
KP		 129/* Called from drm generic code, passed a 'crtc', which
130 * we use as a pipe index
131 */
f71d4af4 132static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 133{
134 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
135 unsigned long high_frame;
136 unsigned long low_frame;
5eddb70b 137 u32 high1, high2, low;
0a3e67a4
JB		 138
139 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 140 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 141 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 142 return 0;
143 }
144
9db4a9c7
JB		 145 high_frame = PIPEFRAME(pipe);
146 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 147
0a3e67a4
JB		 148 /*
149 * High & low register fields aren't synchronized, so make sure
150 * we get a low value that's stable across two reads of the high
151 * register.
152 */
153 do {
5eddb70b
CW		 154 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
155 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
156 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 157 } while (high1 != high2);
158
5eddb70b
CW		 159 high1 >>= PIPE_FRAME_HIGH_SHIFT;
160 low >>= PIPE_FRAME_LOW_SHIFT;
161 return (high1 << 8) | low;
0a3e67a4
JB		 162}
163
f71d4af4 164static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 165{
166 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 167 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 168
169 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 170 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 171 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 172 return 0;
173 }
174
175 return I915_READ(reg);
176}
177
f71d4af4 178static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 179 int *vpos, int *hpos)
180{
181 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
182 u32 vbl = 0, position = 0;
183 int vbl_start, vbl_end, htotal, vtotal;
184 bool in_vbl = true;
185 int ret = 0;
186
187 if (!i915_pipe_enabled(dev, pipe)) {
188 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 189 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 190 return 0;
191 }
192
193 /* Get vtotal. */
194 vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
195
196 if (INTEL_INFO(dev)->gen >= 4) {
197 /* No obvious pixelcount register. Only query vertical
198 * scanout position from Display scan line register.
199 */
200 position = I915_READ(PIPEDSL(pipe));
201
202 /* Decode into vertical scanout position. Don't have
203 * horizontal scanout position.
204 */
205 *vpos = position & 0x1fff;
206 *hpos = 0;
207 } else {
208 /* Have access to pixelcount since start of frame.
209 * We can split this into vertical and horizontal
210 * scanout position.
211 */
212 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
213
214 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
215 *vpos = position / htotal;
216 *hpos = position - (*vpos * htotal);
217 }
218
219 /* Query vblank area. */
220 vbl = I915_READ(VBLANK(pipe));
221
222 /* Test position against vblank region. */
223 vbl_start = vbl & 0x1fff;
224 vbl_end = (vbl >> 16) & 0x1fff;
225
226 if ((*vpos < vbl_start) || (*vpos > vbl_end))
227 in_vbl = false;
228
229 /* Inside "upper part" of vblank area? Apply corrective offset: */
230 if (in_vbl && (*vpos >= vbl_start))
231 *vpos = *vpos - vtotal;
232
233 /* Readouts valid? */
234 if (vbl > 0)
235 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
236
237 /* In vblank? */
238 if (in_vbl)
239 ret |= DRM_SCANOUTPOS_INVBL;
240
241 return ret;
242}
243
f71d4af4 244static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 245 int *max_error,
246 struct timeval *vblank_time,
247 unsigned flags)
248{
4041b853
CW		 249 struct drm_i915_private *dev_priv = dev->dev_private;
250 struct drm_crtc *crtc;
0af7e4df 251
4041b853
CW		 252 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
253 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 254 return -EINVAL;
255 }
256
257 /* Get drm_crtc to timestamp: */
4041b853
CW		 258 crtc = intel_get_crtc_for_pipe(dev, pipe);
259 if (crtc == NULL) {
260 DRM_ERROR("Invalid crtc %d\n", pipe);
261 return -EINVAL;
262 }
263
264 if (!crtc->enabled) {
265 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
266 return -EBUSY;
267 }
0af7e4df
MK		 268
269 /* Helper routine in DRM core does all the work: */
4041b853
CW		 270 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
271 vblank_time, flags,
272 crtc);
0af7e4df
MK		 273}
274
5ca58282
JB		 275/*
276 * Handle hotplug events outside the interrupt handler proper.
277 */
278static void i915_hotplug_work_func(struct work_struct *work)
279{
280 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
281 hotplug_work);
282 struct drm_device *dev = dev_priv->dev;
c31c4ba3 283 struct drm_mode_config *mode_config = &dev->mode_config;
4ef69c7a
CW		 284 struct intel_encoder *encoder;
285
a65e34c7 286 mutex_lock(&mode_config->mutex);
e67189ab
JB		 287 DRM_DEBUG_KMS("running encoder hotplug functions\n");
288
4ef69c7a
CW		 289 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
290 if (encoder->hot_plug)
291 encoder->hot_plug(encoder);
292
40ee3381
KP		 293 mutex_unlock(&mode_config->mutex);
294
5ca58282 295 /* Just fire off a uevent and let userspace tell us what to do */
eb1f8e4f 296 drm_helper_hpd_irq_event(dev);
5ca58282
JB		 297}
298
9270388e
DV		 299/* defined intel_pm.c */
300extern spinlock_t mchdev_lock;
301
73edd18f 302static void ironlake_handle_rps_change(struct drm_device *dev)
f97108d1
JB		 303{
304 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 305 u32 busy_up, busy_down, max_avg, min_avg;
9270388e
DV		 306 u8 new_delay;
307 unsigned long flags;
308
309 spin_lock_irqsave(&mchdev_lock, flags);
f97108d1 310
73edd18f
DV		 311 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
312
9270388e
DV		 313 new_delay = dev_priv->cur_delay;
314
7648fa99 315 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 316 busy_up = I915_READ(RCPREVBSYTUPAVG);
317 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 318 max_avg = I915_READ(RCBMAXAVG);
319 min_avg = I915_READ(RCBMINAVG);
320
321 /* Handle RCS change request from hw */
b5b72e89 322 if (busy_up > max_avg) {
f97108d1
JB		 323 if (dev_priv->cur_delay != dev_priv->max_delay)
324 new_delay = dev_priv->cur_delay - 1;
325 if (new_delay < dev_priv->max_delay)
326 new_delay = dev_priv->max_delay;
b5b72e89 327 } else if (busy_down < min_avg) {
f97108d1
JB		 328 if (dev_priv->cur_delay != dev_priv->min_delay)
329 new_delay = dev_priv->cur_delay + 1;
330 if (new_delay > dev_priv->min_delay)
331 new_delay = dev_priv->min_delay;
332 }
333
7648fa99
JB		 334 if (ironlake_set_drps(dev, new_delay))
335 dev_priv->cur_delay = new_delay;
f97108d1 336
9270388e
DV		 337 spin_unlock_irqrestore(&mchdev_lock, flags);
338
f97108d1
JB		 339 return;
340}
341
549f7365
CW		 342static void notify_ring(struct drm_device *dev,
343 struct intel_ring_buffer *ring)
344{
345 struct drm_i915_private *dev_priv = dev->dev_private;
9862e600 346
475553de
CW		 347 if (ring->obj == NULL)
348 return;
349
b2eadbc8 350 trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
9862e600 351
549f7365 352 wake_up_all(&ring->irq_queue);
3e0dc6b0
BW		 353 if (i915_enable_hangcheck) {
354 dev_priv->hangcheck_count = 0;
355 mod_timer(&dev_priv->hangcheck_timer,
356 jiffies +
357 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
358 }
549f7365
CW		 359}
360
4912d041 361static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 362{
4912d041 363 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
c6a828d3 364 rps.work);
4912d041 365 u32 pm_iir, pm_imr;
7b9e0ae6 366 u8 new_delay;
4912d041 367
c6a828d3
DV		 368 spin_lock_irq(&dev_priv->rps.lock);
369 pm_iir = dev_priv->rps.pm_iir;
370 dev_priv->rps.pm_iir = 0;
4912d041 371 pm_imr = I915_READ(GEN6_PMIMR);
a9e2641d 372 I915_WRITE(GEN6_PMIMR, 0);
c6a828d3 373 spin_unlock_irq(&dev_priv->rps.lock);
3b8d8d91 374
7b9e0ae6 375 if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
3b8d8d91
JB		 376 return;
377
4912d041 378 mutex_lock(&dev_priv->dev->struct_mutex);
7b9e0ae6
CW		 379
380 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
c6a828d3 381 new_delay = dev_priv->rps.cur_delay + 1;
7b9e0ae6 382 else
c6a828d3 383 new_delay = dev_priv->rps.cur_delay - 1;
3b8d8d91 384
4912d041 385 gen6_set_rps(dev_priv->dev, new_delay);
3b8d8d91 386
4912d041 387 mutex_unlock(&dev_priv->dev->struct_mutex);
3b8d8d91
JB		 388}
389
e3689190
BW		 390
391/**
392 * ivybridge_parity_work - Workqueue called when a parity error interrupt
393 * occurred.
394 * @work: workqueue struct
395 *
396 * Doesn't actually do anything except notify userspace. As a consequence of
397 * this event, userspace should try to remap the bad rows since statistically
398 * it is likely the same row is more likely to go bad again.
399 */
400static void ivybridge_parity_work(struct work_struct *work)
401{
402 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
403 parity_error_work);
404 u32 error_status, row, bank, subbank;
405 char *parity_event[5];
406 uint32_t misccpctl;
407 unsigned long flags;
408
409 /* We must turn off DOP level clock gating to access the L3 registers.
410 * In order to prevent a get/put style interface, acquire struct mutex
411 * any time we access those registers.
412 */
413 mutex_lock(&dev_priv->dev->struct_mutex);
414
415 misccpctl = I915_READ(GEN7_MISCCPCTL);
416 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
417 POSTING_READ(GEN7_MISCCPCTL);
418
419 error_status = I915_READ(GEN7_L3CDERRST1);
420 row = GEN7_PARITY_ERROR_ROW(error_status);
421 bank = GEN7_PARITY_ERROR_BANK(error_status);
422 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
423
424 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
425 GEN7_L3CDERRST1_ENABLE);
426 POSTING_READ(GEN7_L3CDERRST1);
427
428 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
429
430 spin_lock_irqsave(&dev_priv->irq_lock, flags);
431 dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
432 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
433 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
434
435 mutex_unlock(&dev_priv->dev->struct_mutex);
436
437 parity_event[0] = "L3_PARITY_ERROR=1";
438 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
439 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
440 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
441 parity_event[4] = NULL;
442
443 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
444 KOBJ_CHANGE, parity_event);
445
446 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
447 row, bank, subbank);
448
449 kfree(parity_event[3]);
450 kfree(parity_event[2]);
451 kfree(parity_event[1]);
452}
453
d2ba8470 454static void ivybridge_handle_parity_error(struct drm_device *dev)
e3689190
BW		 455{
456 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
457 unsigned long flags;
458
e1ef7cc2 459 if (!HAS_L3_GPU_CACHE(dev))
e3689190
BW		 460 return;
461
462 spin_lock_irqsave(&dev_priv->irq_lock, flags);
463 dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
464 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
465 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
466
467 queue_work(dev_priv->wq, &dev_priv->parity_error_work);
468}
469
e7b4c6b1
DV		 470static void snb_gt_irq_handler(struct drm_device *dev,
471 struct drm_i915_private *dev_priv,
472 u32 gt_iir)
473{
474
475 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
476 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
477 notify_ring(dev, &dev_priv->ring[RCS]);
478 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
479 notify_ring(dev, &dev_priv->ring[VCS]);
480 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
481 notify_ring(dev, &dev_priv->ring[BCS]);
482
483 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
484 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
485 GT_RENDER_CS_ERROR_INTERRUPT)) {
486 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
487 i915_handle_error(dev, false);
488 }
e3689190
BW		 489
490 if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
491 ivybridge_handle_parity_error(dev);
e7b4c6b1
DV		 492}
493
fc6826d1
CW		 494static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
495 u32 pm_iir)
496{
497 unsigned long flags;
498
499 /*
500 * IIR bits should never already be set because IMR should
501 * prevent an interrupt from being shown in IIR. The warning
502 * displays a case where we've unsafely cleared
c6a828d3 503 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
fc6826d1
CW		 504 * type is not a problem, it displays a problem in the logic.
505 *
c6a828d3 506 * The mask bit in IMR is cleared by dev_priv->rps.work.
fc6826d1
CW		 507 */
508
c6a828d3 509 spin_lock_irqsave(&dev_priv->rps.lock, flags);
c6a828d3
DV		 510 dev_priv->rps.pm_iir |= pm_iir;
511 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
fc6826d1 512 POSTING_READ(GEN6_PMIMR);
c6a828d3 513 spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
fc6826d1 514
c6a828d3 515 queue_work(dev_priv->wq, &dev_priv->rps.work);
fc6826d1
CW		 516}
517
7e231dbe
JB		 518static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
519{
520 struct drm_device *dev = (struct drm_device *) arg;
521 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
522 u32 iir, gt_iir, pm_iir;
523 irqreturn_t ret = IRQ_NONE;
524 unsigned long irqflags;
525 int pipe;
526 u32 pipe_stats[I915_MAX_PIPES];
7e231dbe
JB		 527 bool blc_event;
528
529 atomic_inc(&dev_priv->irq_received);
530
7e231dbe
JB		 531 while (true) {
532 iir = I915_READ(VLV_IIR);
533 gt_iir = I915_READ(GTIIR);
534 pm_iir = I915_READ(GEN6_PMIIR);
535
536 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
537 goto out;
538
539 ret = IRQ_HANDLED;
540
e7b4c6b1 541 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 542
543 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
544 for_each_pipe(pipe) {
545 int reg = PIPESTAT(pipe);
546 pipe_stats[pipe] = I915_READ(reg);
547
548 /*
549 * Clear the PIPE*STAT regs before the IIR
550 */
551 if (pipe_stats[pipe] & 0x8000ffff) {
552 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
553 DRM_DEBUG_DRIVER("pipe %c underrun\n",
554 pipe_name(pipe));
555 I915_WRITE(reg, pipe_stats[pipe]);
556 }
557 }
558 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
559
31acc7f5
JB		 560 for_each_pipe(pipe) {
561 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
562 drm_handle_vblank(dev, pipe);
563
564 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
565 intel_prepare_page_flip(dev, pipe);
566 intel_finish_page_flip(dev, pipe);
567 }
568 }
569
7e231dbe
JB		 570 /* Consume port. Then clear IIR or we'll miss events */
571 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
572 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
573
574 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
575 hotplug_status);
576 if (hotplug_status & dev_priv->hotplug_supported_mask)
577 queue_work(dev_priv->wq,
578 &dev_priv->hotplug_work);
579
580 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
581 I915_READ(PORT_HOTPLUG_STAT);
582 }
583
7e231dbe
JB		 584 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
585 blc_event = true;
586
fc6826d1
CW		 587 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
588 gen6_queue_rps_work(dev_priv, pm_iir);
7e231dbe
JB		 589
590 I915_WRITE(GTIIR, gt_iir);
591 I915_WRITE(GEN6_PMIIR, pm_iir);
592 I915_WRITE(VLV_IIR, iir);
593 }
594
595out:
596 return ret;
597}
598
23e81d69 599static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 600{
601 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 602 int pipe;
776ad806 603
776ad806
JB		 604 if (pch_iir & SDE_AUDIO_POWER_MASK)
605 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
606 (pch_iir & SDE_AUDIO_POWER_MASK) >>
607 SDE_AUDIO_POWER_SHIFT);
608
609 if (pch_iir & SDE_GMBUS)
610 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
611
612 if (pch_iir & SDE_AUDIO_HDCP_MASK)
613 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
614
615 if (pch_iir & SDE_AUDIO_TRANS_MASK)
616 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
617
618 if (pch_iir & SDE_POISON)
619 DRM_ERROR("PCH poison interrupt\n");
620
9db4a9c7
JB		 621 if (pch_iir & SDE_FDI_MASK)
622 for_each_pipe(pipe)
623 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
624 pipe_name(pipe),
625 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 626
627 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
628 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
629
630 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
631 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
632
633 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
634 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
635 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
636 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
637}
638
23e81d69
AJ		 639static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
640{
641 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
642 int pipe;
643
644 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
645 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
646 (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
647 SDE_AUDIO_POWER_SHIFT_CPT);
648
649 if (pch_iir & SDE_AUX_MASK_CPT)
650 DRM_DEBUG_DRIVER("AUX channel interrupt\n");
651
652 if (pch_iir & SDE_GMBUS_CPT)
653 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
654
655 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
656 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
657
658 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
659 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
660
661 if (pch_iir & SDE_FDI_MASK_CPT)
662 for_each_pipe(pipe)
663 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
664 pipe_name(pipe),
665 I915_READ(FDI_RX_IIR(pipe)));
666}
667
f71d4af4 668static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
b1f14ad0
JB		 669{
670 struct drm_device *dev = (struct drm_device *) arg;
671 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
0e43406b
CW		 672 u32 de_iir, gt_iir, de_ier, pm_iir;
673 irqreturn_t ret = IRQ_NONE;
674 int i;
b1f14ad0
JB		 675
676 atomic_inc(&dev_priv->irq_received);
677
678 /* disable master interrupt before clearing iir */
679 de_ier = I915_READ(DEIER);
680 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
b1f14ad0 681
b1f14ad0 682 gt_iir = I915_READ(GTIIR);
0e43406b
CW		 683 if (gt_iir) {
684 snb_gt_irq_handler(dev, dev_priv, gt_iir);
685 I915_WRITE(GTIIR, gt_iir);
686 ret = IRQ_HANDLED;
b1f14ad0
JB		 687 }
688
0e43406b
CW		 689 de_iir = I915_READ(DEIIR);
690 if (de_iir) {
691 if (de_iir & DE_GSE_IVB)
692 intel_opregion_gse_intr(dev);
693
694 for (i = 0; i < 3; i++) {
695 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
696 intel_prepare_page_flip(dev, i);
697 intel_finish_page_flip_plane(dev, i);
698 }
699 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
700 drm_handle_vblank(dev, i);
701 }
b615b57a 702
0e43406b
CW		 703 /* check event from PCH */
704 if (de_iir & DE_PCH_EVENT_IVB) {
705 u32 pch_iir = I915_READ(SDEIIR);
b1f14ad0 706
0e43406b
CW		 707 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
708 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
23e81d69 709 cpt_irq_handler(dev, pch_iir);
b1f14ad0 710
0e43406b
CW		 711 /* clear PCH hotplug event before clear CPU irq */
712 I915_WRITE(SDEIIR, pch_iir);
713 }
b615b57a 714
0e43406b
CW		 715 I915_WRITE(DEIIR, de_iir);
716 ret = IRQ_HANDLED;
b1f14ad0
JB		 717 }
718
0e43406b
CW		 719 pm_iir = I915_READ(GEN6_PMIIR);
720 if (pm_iir) {
721 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
722 gen6_queue_rps_work(dev_priv, pm_iir);
723 I915_WRITE(GEN6_PMIIR, pm_iir);
724 ret = IRQ_HANDLED;
725 }
b1f14ad0 726
b1f14ad0
JB		 727 I915_WRITE(DEIER, de_ier);
728 POSTING_READ(DEIER);
729
730 return ret;
731}
732
e7b4c6b1
DV		 733static void ilk_gt_irq_handler(struct drm_device *dev,
734 struct drm_i915_private *dev_priv,
735 u32 gt_iir)
736{
737 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
738 notify_ring(dev, &dev_priv->ring[RCS]);
739 if (gt_iir & GT_BSD_USER_INTERRUPT)
740 notify_ring(dev, &dev_priv->ring[VCS]);
741}
742
f71d4af4 743static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
036a4a7d 744{
4697995b 745 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 746 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
747 int ret = IRQ_NONE;
3b8d8d91 748 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
2d7b8366 749 u32 hotplug_mask;
881f47b6 750
4697995b
JB		 751 atomic_inc(&dev_priv->irq_received);
752
2d109a84
ZN		 753 /* disable master interrupt before clearing iir */
754 de_ier = I915_READ(DEIER);
755 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 756 POSTING_READ(DEIER);
2d109a84 757
036a4a7d
ZW		 758 de_iir = I915_READ(DEIIR);
759 gt_iir = I915_READ(GTIIR);
c650156a 760 pch_iir = I915_READ(SDEIIR);
3b8d8d91 761 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 762
3b8d8d91
JB		 763 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
764 (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 765 goto done;
036a4a7d 766
2d7b8366
YL		 767 if (HAS_PCH_CPT(dev))
768 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
769 else
770 hotplug_mask = SDE_HOTPLUG_MASK;
771
c7c85101 772 ret = IRQ_HANDLED;
036a4a7d 773
e7b4c6b1
DV		 774 if (IS_GEN5(dev))
775 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
776 else
777 snb_gt_irq_handler(dev, dev_priv, gt_iir);
01c66889 778
c7c85101 779 if (de_iir & DE_GSE)
3b617967 780 intel_opregion_gse_intr(dev);
c650156a 781
f072d2e7 782 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 783 intel_prepare_page_flip(dev, 0);
2bbda389 784 intel_finish_page_flip_plane(dev, 0);
f072d2e7 785 }
013d5aa2 786
f072d2e7 787 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 788 intel_prepare_page_flip(dev, 1);
2bbda389 789 intel_finish_page_flip_plane(dev, 1);
f072d2e7 790 }
013d5aa2 791
f072d2e7 792 if (de_iir & DE_PIPEA_VBLANK)
c062df61
LP		 793 drm_handle_vblank(dev, 0);
794
f072d2e7 795 if (de_iir & DE_PIPEB_VBLANK)
c062df61
LP		 796 drm_handle_vblank(dev, 1);
797
c7c85101 798 /* check event from PCH */
776ad806
JB		 799 if (de_iir & DE_PCH_EVENT) {
800 if (pch_iir & hotplug_mask)
801 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
23e81d69
AJ		 802 if (HAS_PCH_CPT(dev))
803 cpt_irq_handler(dev, pch_iir);
804 else
805 ibx_irq_handler(dev, pch_iir);
776ad806 806 }
036a4a7d 807
73edd18f
DV		 808 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
809 ironlake_handle_rps_change(dev);
f97108d1 810
fc6826d1
CW		 811 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
812 gen6_queue_rps_work(dev_priv, pm_iir);
3b8d8d91 813
c7c85101
ZN		 814 /* should clear PCH hotplug event before clear CPU irq */
815 I915_WRITE(SDEIIR, pch_iir);
816 I915_WRITE(GTIIR, gt_iir);
817 I915_WRITE(DEIIR, de_iir);
4912d041 818 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 819
820done:
2d109a84 821 I915_WRITE(DEIER, de_ier);
3143a2bf 822 POSTING_READ(DEIER);
2d109a84 823
036a4a7d
ZW		 824 return ret;
825}
826
8a905236
JB		 827/**
828 * i915_error_work_func - do process context error handling work
829 * @work: work struct
830 *
831 * Fire an error uevent so userspace can see that a hang or error
832 * was detected.
833 */
834static void i915_error_work_func(struct work_struct *work)
835{
836 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
837 error_work);
838 struct drm_device *dev = dev_priv->dev;
f316a42c
BG		 839 char *error_event[] = { "ERROR=1", NULL };
840 char *reset_event[] = { "RESET=1", NULL };
841 char *reset_done_event[] = { "ERROR=0", NULL };
8a905236 842
f316a42c
BG		 843 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
844
ba1234d1 845 if (atomic_read(&dev_priv->mm.wedged)) {
f803aa55
CW		 846 DRM_DEBUG_DRIVER("resetting chip\n");
847 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
d4b8bb2a 848 if (!i915_reset(dev)) {
f803aa55
CW		 849 atomic_set(&dev_priv->mm.wedged, 0);
850 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
f316a42c 851 }
30dbf0c0 852 complete_all(&dev_priv->error_completion);
f316a42c 853 }
8a905236
JB		 854}
855
85f9e50d
DV		 856/* NB: please notice the memset */
857static void i915_get_extra_instdone(struct drm_device *dev,
858 uint32_t *instdone)
859{
860 struct drm_i915_private *dev_priv = dev->dev_private;
861 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
862
863 switch(INTEL_INFO(dev)->gen) {
864 case 2:
865 case 3:
866 instdone[0] = I915_READ(INSTDONE);
867 break;
868 case 4:
869 case 5:
870 case 6:
871 instdone[0] = I915_READ(INSTDONE_I965);
872 instdone[1] = I915_READ(INSTDONE1);
873 break;
874 default:
875 WARN_ONCE(1, "Unsupported platform\n");
876 case 7:
877 instdone[0] = I915_READ(GEN7_INSTDONE_1);
878 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
879 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
880 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
881 break;
882 }
883}
884
3bd3c932 885#ifdef CONFIG_DEBUG_FS
9df30794 886static struct drm_i915_error_object *
bcfb2e28 887i915_error_object_create(struct drm_i915_private *dev_priv,
05394f39 888 struct drm_i915_gem_object *src)
9df30794
CW		 889{
890 struct drm_i915_error_object *dst;
9df30794 891 int page, page_count;
e56660dd 892 u32 reloc_offset;
9df30794 893
05394f39 894 if (src == NULL || src->pages == NULL)
9df30794
CW		 895 return NULL;
896
05394f39 897 page_count = src->base.size / PAGE_SIZE;
9df30794 898
0206e353 899 dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
9df30794
CW		 900 if (dst == NULL)
901 return NULL;
902
05394f39 903 reloc_offset = src->gtt_offset;
9df30794 904 for (page = 0; page < page_count; page++) {
788885ae 905 unsigned long flags;
e56660dd 906 void *d;
788885ae 907
e56660dd 908 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 909 if (d == NULL)
910 goto unwind;
e56660dd 911
788885ae 912 local_irq_save(flags);
74898d7e
DV		 913 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
914 src->has_global_gtt_mapping) {
172975aa
CW		 915 void __iomem *s;
916
917 /* Simply ignore tiling or any overlapping fence.
918 * It's part of the error state, and this hopefully
919 * captures what the GPU read.
920 */
921
922 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
923 reloc_offset);
924 memcpy_fromio(d, s, PAGE_SIZE);
925 io_mapping_unmap_atomic(s);
926 } else {
927 void *s;
928
929 drm_clflush_pages(&src->pages[page], 1);
930
931 s = kmap_atomic(src->pages[page]);
932 memcpy(d, s, PAGE_SIZE);
933 kunmap_atomic(s);
934
935 drm_clflush_pages(&src->pages[page], 1);
936 }
788885ae 937 local_irq_restore(flags);
e56660dd 938
9df30794 939 dst->pages[page] = d;
e56660dd
CW		 940
941 reloc_offset += PAGE_SIZE;
9df30794
CW		 942 }
943 dst->page_count = page_count;
05394f39 944 dst->gtt_offset = src->gtt_offset;
9df30794
CW		 945
946 return dst;
947
948unwind:
949 while (page--)
950 kfree(dst->pages[page]);
951 kfree(dst);
952 return NULL;
953}
954
955static void
956i915_error_object_free(struct drm_i915_error_object *obj)
957{
958 int page;
959
960 if (obj == NULL)
961 return;
962
963 for (page = 0; page < obj->page_count; page++)
964 kfree(obj->pages[page]);
965
966 kfree(obj);
967}
968
742cbee8
DV		 969void
970i915_error_state_free(struct kref *error_ref)
9df30794 971{
742cbee8
DV		 972 struct drm_i915_error_state *error = container_of(error_ref,
973 typeof(*error), ref);
e2f973d5
CW		 974 int i;
975
52d39a21
CW		 976 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
977 i915_error_object_free(error->ring[i].batchbuffer);
978 i915_error_object_free(error->ring[i].ringbuffer);
979 kfree(error->ring[i].requests);
980 }
e2f973d5 981
9df30794 982 kfree(error->active_bo);
6ef3d427 983 kfree(error->overlay);
9df30794
CW		 984 kfree(error);
985}
1b50247a
CW		 986static void capture_bo(struct drm_i915_error_buffer *err,
987 struct drm_i915_gem_object *obj)
988{
989 err->size = obj->base.size;
990 err->name = obj->base.name;
0201f1ec
CW		 991 err->rseqno = obj->last_read_seqno;
992 err->wseqno = obj->last_write_seqno;
1b50247a
CW		 993 err->gtt_offset = obj->gtt_offset;
994 err->read_domains = obj->base.read_domains;
995 err->write_domain = obj->base.write_domain;
996 err->fence_reg = obj->fence_reg;
997 err->pinned = 0;
998 if (obj->pin_count > 0)
999 err->pinned = 1;
1000 if (obj->user_pin_count > 0)
1001 err->pinned = -1;
1002 err->tiling = obj->tiling_mode;
1003 err->dirty = obj->dirty;
1004 err->purgeable = obj->madv != I915_MADV_WILLNEED;
1005 err->ring = obj->ring ? obj->ring->id : -1;
1006 err->cache_level = obj->cache_level;
1007}
9df30794 1008
1b50247a
CW		 1009static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1010 int count, struct list_head *head)
c724e8a9
CW		 1011{
1012 struct drm_i915_gem_object *obj;
1013 int i = 0;
1014
1015 list_for_each_entry(obj, head, mm_list) {
1b50247a 1016 capture_bo(err++, obj);
c724e8a9
CW		 1017 if (++i == count)
1018 break;
1b50247a
CW		 1019 }
1020
1021 return i;
1022}
1023
1024static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1025 int count, struct list_head *head)
1026{
1027 struct drm_i915_gem_object *obj;
1028 int i = 0;
1029
1030 list_for_each_entry(obj, head, gtt_list) {
1031 if (obj->pin_count == 0)
1032 continue;
c724e8a9 1033
1b50247a
CW		 1034 capture_bo(err++, obj);
1035 if (++i == count)
1036 break;
c724e8a9
CW		 1037 }
1038
1039 return i;
1040}
1041
748ebc60
CW		 1042static void i915_gem_record_fences(struct drm_device *dev,
1043 struct drm_i915_error_state *error)
1044{
1045 struct drm_i915_private *dev_priv = dev->dev_private;
1046 int i;
1047
1048 /* Fences */
1049 switch (INTEL_INFO(dev)->gen) {
775d17b6 1050 case 7:
748ebc60
CW		 1051 case 6:
1052 for (i = 0; i < 16; i++)
1053 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1054 break;
1055 case 5:
1056 case 4:
1057 for (i = 0; i < 16; i++)
1058 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1059 break;
1060 case 3:
1061 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1062 for (i = 0; i < 8; i++)
1063 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1064 case 2:
1065 for (i = 0; i < 8; i++)
1066 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1067 break;
1068
1069 }
1070}
1071
bcfb2e28
CW		 1072static struct drm_i915_error_object *
1073i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1074 struct intel_ring_buffer *ring)
1075{
1076 struct drm_i915_gem_object *obj;
1077 u32 seqno;
1078
1079 if (!ring->get_seqno)
1080 return NULL;
1081
b2eadbc8 1082 seqno = ring->get_seqno(ring, false);
bcfb2e28
CW		 1083 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1084 if (obj->ring != ring)
1085 continue;
1086
0201f1ec 1087 if (i915_seqno_passed(seqno, obj->last_read_seqno))
bcfb2e28
CW		 1088 continue;
1089
1090 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1091 continue;
1092
1093 /* We need to copy these to an anonymous buffer as the simplest
1094 * method to avoid being overwritten by userspace.
1095 */
1096 return i915_error_object_create(dev_priv, obj);
1097 }
1098
1099 return NULL;
1100}
1101
d27b1e0e
DV		 1102static void i915_record_ring_state(struct drm_device *dev,
1103 struct drm_i915_error_state *error,
1104 struct intel_ring_buffer *ring)
1105{
1106 struct drm_i915_private *dev_priv = dev->dev_private;
1107
33f3f518 1108 if (INTEL_INFO(dev)->gen >= 6) {
12f55818 1109 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
33f3f518 1110 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
7e3b8737
DV		 1111 error->semaphore_mboxes[ring->id][0]
1112 = I915_READ(RING_SYNC_0(ring->mmio_base));
1113 error->semaphore_mboxes[ring->id][1]
1114 = I915_READ(RING_SYNC_1(ring->mmio_base));
33f3f518 1115 }
c1cd90ed 1116
d27b1e0e 1117 if (INTEL_INFO(dev)->gen >= 4) {
9d2f41fa 1118 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
d27b1e0e
DV		 1119 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1120 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1121 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
c1cd90ed 1122 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
050ee91f 1123 if (ring->id == RCS)
d27b1e0e 1124 error->bbaddr = I915_READ64(BB_ADDR);
d27b1e0e 1125 } else {
9d2f41fa 1126 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
d27b1e0e
DV		 1127 error->ipeir[ring->id] = I915_READ(IPEIR);
1128 error->ipehr[ring->id] = I915_READ(IPEHR);
1129 error->instdone[ring->id] = I915_READ(INSTDONE);
d27b1e0e
DV		 1130 }
1131
9574b3fe 1132 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
c1cd90ed 1133 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
b2eadbc8 1134 error->seqno[ring->id] = ring->get_seqno(ring, false);
d27b1e0e 1135 error->acthd[ring->id] = intel_ring_get_active_head(ring);
c1cd90ed
DV		 1136 error->head[ring->id] = I915_READ_HEAD(ring);
1137 error->tail[ring->id] = I915_READ_TAIL(ring);
7e3b8737
DV		 1138
1139 error->cpu_ring_head[ring->id] = ring->head;
1140 error->cpu_ring_tail[ring->id] = ring->tail;
d27b1e0e
DV		 1141}
1142
52d39a21
CW		 1143static void i915_gem_record_rings(struct drm_device *dev,
1144 struct drm_i915_error_state *error)
1145{
1146 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 1147 struct intel_ring_buffer *ring;
52d39a21
CW		 1148 struct drm_i915_gem_request *request;
1149 int i, count;
1150
b4519513 1151 for_each_ring(ring, dev_priv, i) {
52d39a21
CW		 1152 i915_record_ring_state(dev, error, ring);
1153
1154 error->ring[i].batchbuffer =
1155 i915_error_first_batchbuffer(dev_priv, ring);
1156
1157 error->ring[i].ringbuffer =
1158 i915_error_object_create(dev_priv, ring->obj);
1159
1160 count = 0;
1161 list_for_each_entry(request, &ring->request_list, list)
1162 count++;
1163
1164 error->ring[i].num_requests = count;
1165 error->ring[i].requests =
1166 kmalloc(count*sizeof(struct drm_i915_error_request),
1167 GFP_ATOMIC);
1168 if (error->ring[i].requests == NULL) {
1169 error->ring[i].num_requests = 0;
1170 continue;
1171 }
1172
1173 count = 0;
1174 list_for_each_entry(request, &ring->request_list, list) {
1175 struct drm_i915_error_request *erq;
1176
1177 erq = &error->ring[i].requests[count++];
1178 erq->seqno = request->seqno;
1179 erq->jiffies = request->emitted_jiffies;
ee4f42b1 1180 erq->tail = request->tail;
52d39a21
CW		 1181 }
1182 }
1183}
1184
8a905236
JB		 1185/**
1186 * i915_capture_error_state - capture an error record for later analysis
1187 * @dev: drm device
1188 *
1189 * Should be called when an error is detected (either a hang or an error
1190 * interrupt) to capture error state from the time of the error. Fills
1191 * out a structure which becomes available in debugfs for user level tools
1192 * to pick up.
1193 */
63eeaf38
JB		 1194static void i915_capture_error_state(struct drm_device *dev)
1195{
1196 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1197 struct drm_i915_gem_object *obj;
63eeaf38
JB		 1198 struct drm_i915_error_state *error;
1199 unsigned long flags;
9db4a9c7 1200 int i, pipe;
63eeaf38
JB		 1201
1202 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1203 error = dev_priv->first_error;
1204 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1205 if (error)
1206 return;
63eeaf38 1207
9db4a9c7 1208 /* Account for pipe specific data like PIPE*STAT */
33f3f518 1209 error = kzalloc(sizeof(*error), GFP_ATOMIC);
63eeaf38 1210 if (!error) {
9df30794
CW		 1211 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1212 return;
63eeaf38
JB		 1213 }
1214
b6f7833b
CW		 1215 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1216 dev->primary->index);
2fa772f3 1217
742cbee8 1218 kref_init(&error->ref);
63eeaf38
JB		 1219 error->eir = I915_READ(EIR);
1220 error->pgtbl_er = I915_READ(PGTBL_ER);
b9a3906b 1221 error->ccid = I915_READ(CCID);
be998e2e
BW		 1222
1223 if (HAS_PCH_SPLIT(dev))
1224 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1225 else if (IS_VALLEYVIEW(dev))
1226 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1227 else if (IS_GEN2(dev))
1228 error->ier = I915_READ16(IER);
1229 else
1230 error->ier = I915_READ(IER);
1231
9db4a9c7
JB		 1232 for_each_pipe(pipe)
1233 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
d27b1e0e 1234
33f3f518 1235 if (INTEL_INFO(dev)->gen >= 6) {
f406839f 1236 error->error = I915_READ(ERROR_GEN6);
33f3f518
DV		 1237 error->done_reg = I915_READ(DONE_REG);
1238 }
d27b1e0e 1239
71e172e8
BW		 1240 if (INTEL_INFO(dev)->gen == 7)
1241 error->err_int = I915_READ(GEN7_ERR_INT);
1242
050ee91f
BW		 1243 i915_get_extra_instdone(dev, error->extra_instdone);
1244
748ebc60 1245 i915_gem_record_fences(dev, error);
52d39a21 1246 i915_gem_record_rings(dev, error);
9df30794 1247
c724e8a9 1248 /* Record buffers on the active and pinned lists. */
9df30794 1249 error->active_bo = NULL;
c724e8a9 1250 error->pinned_bo = NULL;
9df30794 1251
bcfb2e28
CW		 1252 i = 0;
1253 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1254 i++;
1255 error->active_bo_count = i;
6c085a72 1256 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
1b50247a
CW		 1257 if (obj->pin_count)
1258 i++;
bcfb2e28 1259 error->pinned_bo_count = i - error->active_bo_count;
c724e8a9 1260
8e934dbf
CW		 1261 error->active_bo = NULL;
1262 error->pinned_bo = NULL;
bcfb2e28
CW		 1263 if (i) {
1264 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
9df30794 1265 GFP_ATOMIC);
c724e8a9
CW		 1266 if (error->active_bo)
1267 error->pinned_bo =
1268 error->active_bo + error->active_bo_count;
9df30794
CW		 1269 }
1270
c724e8a9
CW		 1271 if (error->active_bo)
1272 error->active_bo_count =
1b50247a
CW		 1273 capture_active_bo(error->active_bo,
1274 error->active_bo_count,
1275 &dev_priv->mm.active_list);
c724e8a9
CW		 1276
1277 if (error->pinned_bo)
1278 error->pinned_bo_count =
1b50247a
CW		 1279 capture_pinned_bo(error->pinned_bo,
1280 error->pinned_bo_count,
6c085a72 1281 &dev_priv->mm.bound_list);
c724e8a9 1282
9df30794
CW		 1283 do_gettimeofday(&error->time);
1284
6ef3d427 1285 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 1286 error->display = intel_display_capture_error_state(dev);
6ef3d427 1287
9df30794
CW		 1288 spin_lock_irqsave(&dev_priv->error_lock, flags);
1289 if (dev_priv->first_error == NULL) {
1290 dev_priv->first_error = error;
1291 error = NULL;
1292 }
63eeaf38 1293 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1294
1295 if (error)
742cbee8 1296 i915_error_state_free(&error->ref);
9df30794
CW		 1297}
1298
1299void i915_destroy_error_state(struct drm_device *dev)
1300{
1301 struct drm_i915_private *dev_priv = dev->dev_private;
1302 struct drm_i915_error_state *error;
6dc0e816 1303 unsigned long flags;
9df30794 1304
6dc0e816 1305 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1306 error = dev_priv->first_error;
1307 dev_priv->first_error = NULL;
6dc0e816 1308 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1309
1310 if (error)
742cbee8 1311 kref_put(&error->ref, i915_error_state_free);
63eeaf38 1312}
3bd3c932
CW		 1313#else
1314#define i915_capture_error_state(x)
1315#endif
63eeaf38 1316
35aed2e6 1317static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1318{
1319 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 1320 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 1321 u32 eir = I915_READ(EIR);
050ee91f 1322 int pipe, i;
8a905236 1323
35aed2e6
CW		 1324 if (!eir)
1325 return;
8a905236 1326
a70491cc 1327 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 1328
bd9854f9
BW		 1329 i915_get_extra_instdone(dev, instdone);
1330
8a905236
JB		 1331 if (IS_G4X(dev)) {
1332 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1333 u32 ipeir = I915_READ(IPEIR_I965);
1334
a70491cc
JP		 1335 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1336 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 1337 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1338 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 1339 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1340 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1341 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1342 POSTING_READ(IPEIR_I965);
8a905236
JB		 1343 }
1344 if (eir & GM45_ERROR_PAGE_TABLE) {
1345 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1346 pr_err("page table error\n");
1347 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1348 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1349 POSTING_READ(PGTBL_ER);
8a905236
JB		 1350 }
1351 }
1352
a6c45cf0 1353 if (!IS_GEN2(dev)) {
8a905236
JB		 1354 if (eir & I915_ERROR_PAGE_TABLE) {
1355 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1356 pr_err("page table error\n");
1357 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1358 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1359 POSTING_READ(PGTBL_ER);
8a905236
JB		 1360 }
1361 }
1362
1363 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 1364 pr_err("memory refresh error:\n");
9db4a9c7 1365 for_each_pipe(pipe)
a70491cc 1366 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 1367 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 1368 /* pipestat has already been acked */
1369 }
1370 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 1371 pr_err("instruction error\n");
1372 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 1373 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1374 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 1375 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 1376 u32 ipeir = I915_READ(IPEIR);
1377
a70491cc
JP		 1378 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1379 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 1380 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 1381 I915_WRITE(IPEIR, ipeir);
3143a2bf 1382 POSTING_READ(IPEIR);
8a905236
JB		 1383 } else {
1384 u32 ipeir = I915_READ(IPEIR_I965);
1385
a70491cc
JP		 1386 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1387 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 1388 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1389 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1390 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1391 POSTING_READ(IPEIR_I965);
8a905236
JB		 1392 }
1393 }
1394
1395 I915_WRITE(EIR, eir);
3143a2bf 1396 POSTING_READ(EIR);
8a905236
JB		 1397 eir = I915_READ(EIR);
1398 if (eir) {
1399 /*
1400 * some errors might have become stuck,
1401 * mask them.
1402 */
1403 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1404 I915_WRITE(EMR, I915_READ(EMR) | eir);
1405 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1406 }
35aed2e6
CW		 1407}
1408
1409/**
1410 * i915_handle_error - handle an error interrupt
1411 * @dev: drm device
1412 *
1413 * Do some basic checking of regsiter state at error interrupt time and
1414 * dump it to the syslog. Also call i915_capture_error_state() to make
1415 * sure we get a record and make it available in debugfs. Fire a uevent
1416 * so userspace knows something bad happened (should trigger collection
1417 * of a ring dump etc.).
1418 */
527f9e90 1419void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 1420{
1421 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513
CW		 1422 struct intel_ring_buffer *ring;
1423 int i;
35aed2e6
CW		 1424
1425 i915_capture_error_state(dev);
1426 i915_report_and_clear_eir(dev);
8a905236 1427
ba1234d1 1428 if (wedged) {
30dbf0c0 1429 INIT_COMPLETION(dev_priv->error_completion);
ba1234d1
BG		 1430 atomic_set(&dev_priv->mm.wedged, 1);
1431
11ed50ec
BG		 1432 /*
1433 * Wakeup waiting processes so they don't hang
1434 */
b4519513
CW		 1435 for_each_ring(ring, dev_priv, i)
1436 wake_up_all(&ring->irq_queue);
11ed50ec
BG		 1437 }
1438
9c9fe1f8 1439 queue_work(dev_priv->wq, &dev_priv->error_work);
8a905236
JB		 1440}
1441
4e5359cd
SF		 1442static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1443{
1444 drm_i915_private_t *dev_priv = dev->dev_private;
1445 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1446 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 1447 struct drm_i915_gem_object *obj;
4e5359cd
SF		 1448 struct intel_unpin_work *work;
1449 unsigned long flags;
1450 bool stall_detected;
1451
1452 /* Ignore early vblank irqs */
1453 if (intel_crtc == NULL)
1454 return;
1455
1456 spin_lock_irqsave(&dev->event_lock, flags);
1457 work = intel_crtc->unpin_work;
1458
1459 if (work == NULL || work->pending || !work->enable_stall_check) {
1460 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1461 spin_unlock_irqrestore(&dev->event_lock, flags);
1462 return;
1463 }
1464
1465 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 1466 obj = work->pending_flip_obj;
a6c45cf0 1467 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 1468 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545
AR		 1469 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1470 obj->gtt_offset;
4e5359cd 1471 } else {
9db4a9c7 1472 int dspaddr = DSPADDR(intel_crtc->plane);
05394f39 1473 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
01f2c773 1474 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 1475 crtc->x * crtc->fb->bits_per_pixel/8);
1476 }
1477
1478 spin_unlock_irqrestore(&dev->event_lock, flags);
1479
1480 if (stall_detected) {
1481 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1482 intel_prepare_page_flip(dev, intel_crtc->plane);
1483 }
1484}
1485
42f52ef8
KP		 1486/* Called from drm generic code, passed 'crtc' which
1487 * we use as a pipe index
1488 */
f71d4af4 1489static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1490{
1491 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1492 unsigned long irqflags;
71e0ffa5 1493
5eddb70b 1494 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 1495 return -EINVAL;
0a3e67a4 1496
1ec14ad3 1497 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 1498 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 1499 i915_enable_pipestat(dev_priv, pipe,
1500 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 1501 else
7c463586
KP		 1502 i915_enable_pipestat(dev_priv, pipe,
1503 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 1504
1505 /* maintain vblank delivery even in deep C-states */
1506 if (dev_priv->info->gen == 3)
6b26c86d 1507 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 1508 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 1509
0a3e67a4
JB		 1510 return 0;
1511}
1512
f71d4af4 1513static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1514{
1515 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1516 unsigned long irqflags;
1517
1518 if (!i915_pipe_enabled(dev, pipe))
1519 return -EINVAL;
1520
1521 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1522 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1523 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
f796cf8f
JB		 1524 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1525
1526 return 0;
1527}
1528
f71d4af4 1529static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1530{
1531 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1532 unsigned long irqflags;
1533
1534 if (!i915_pipe_enabled(dev, pipe))
1535 return -EINVAL;
1536
1537 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1538 ironlake_enable_display_irq(dev_priv,
1539 DE_PIPEA_VBLANK_IVB << (5 * pipe));
b1f14ad0
JB		 1540 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1541
1542 return 0;
1543}
1544
7e231dbe
JB		 1545static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1546{
1547 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1548 unsigned long irqflags;
31acc7f5 1549 u32 imr;
7e231dbe
JB		 1550
1551 if (!i915_pipe_enabled(dev, pipe))
1552 return -EINVAL;
1553
1554 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7e231dbe 1555 imr = I915_READ(VLV_IMR);
31acc7f5 1556 if (pipe == 0)
7e231dbe 1557 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1558 else
7e231dbe 1559 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1560 I915_WRITE(VLV_IMR, imr);
31acc7f5
JB		 1561 i915_enable_pipestat(dev_priv, pipe,
1562 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe
JB		 1563 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1564
1565 return 0;
1566}
1567
42f52ef8
KP		 1568/* Called from drm generic code, passed 'crtc' which
1569 * we use as a pipe index
1570 */
f71d4af4 1571static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1572{
1573 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1574 unsigned long irqflags;
0a3e67a4 1575
1ec14ad3 1576 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 1577 if (dev_priv->info->gen == 3)
6b26c86d 1578 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 1579
f796cf8f
JB		 1580 i915_disable_pipestat(dev_priv, pipe,
1581 PIPE_VBLANK_INTERRUPT_ENABLE |
1582 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1583 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1584}
1585
f71d4af4 1586static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1587{
1588 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1589 unsigned long irqflags;
1590
1591 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1592 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1593 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1ec14ad3 1594 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 1595}
1596
f71d4af4 1597static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1598{
1599 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1600 unsigned long irqflags;
1601
1602 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1603 ironlake_disable_display_irq(dev_priv,
1604 DE_PIPEA_VBLANK_IVB << (pipe * 5));
b1f14ad0
JB		 1605 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1606}
1607
7e231dbe
JB		 1608static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1609{
1610 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1611 unsigned long irqflags;
31acc7f5 1612 u32 imr;
7e231dbe
JB		 1613
1614 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5
JB		 1615 i915_disable_pipestat(dev_priv, pipe,
1616 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe 1617 imr = I915_READ(VLV_IMR);
31acc7f5 1618 if (pipe == 0)
7e231dbe 1619 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1620 else
7e231dbe 1621 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1622 I915_WRITE(VLV_IMR, imr);
7e231dbe
JB		 1623 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1624}
1625
893eead0
CW		 1626static u32
1627ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 1628{
893eead0
CW		 1629 return list_entry(ring->request_list.prev,
1630 struct drm_i915_gem_request, list)->seqno;
1631}
1632
1633static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1634{
1635 if (list_empty(&ring->request_list) ||
b2eadbc8
CW		 1636 i915_seqno_passed(ring->get_seqno(ring, false),
1637 ring_last_seqno(ring))) {
893eead0 1638 /* Issue a wake-up to catch stuck h/w. */
9574b3fe
BW		 1639 if (waitqueue_active(&ring->irq_queue)) {
1640 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1641 ring->name);
893eead0
CW		 1642 wake_up_all(&ring->irq_queue);
1643 *err = true;
1644 }
1645 return true;
1646 }
1647 return false;
f65d9421
BG		 1648}
1649
1ec14ad3
CW		 1650static bool kick_ring(struct intel_ring_buffer *ring)
1651{
1652 struct drm_device *dev = ring->dev;
1653 struct drm_i915_private *dev_priv = dev->dev_private;
1654 u32 tmp = I915_READ_CTL(ring);
1655 if (tmp & RING_WAIT) {
1656 DRM_ERROR("Kicking stuck wait on %s\n",
1657 ring->name);
1658 I915_WRITE_CTL(ring, tmp);
1659 return true;
1660 }
1ec14ad3
CW		 1661 return false;
1662}
1663
d1e61e7f
CW		 1664static bool i915_hangcheck_hung(struct drm_device *dev)
1665{
1666 drm_i915_private_t *dev_priv = dev->dev_private;
1667
1668 if (dev_priv->hangcheck_count++ > 1) {
b4519513
CW		 1669 bool hung = true;
1670
d1e61e7f
CW		 1671 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1672 i915_handle_error(dev, true);
1673
1674 if (!IS_GEN2(dev)) {
b4519513
CW		 1675 struct intel_ring_buffer *ring;
1676 int i;
1677
d1e61e7f
CW		 1678 /* Is the chip hanging on a WAIT_FOR_EVENT?
1679 * If so we can simply poke the RB_WAIT bit
1680 * and break the hang. This should work on
1681 * all but the second generation chipsets.
1682 */
b4519513
CW		 1683 for_each_ring(ring, dev_priv, i)
1684 hung &= !kick_ring(ring);
d1e61e7f
CW		 1685 }
1686
b4519513 1687 return hung;
d1e61e7f
CW		 1688 }
1689
1690 return false;
1691}
1692
f65d9421
BG		 1693/**
1694 * This is called when the chip hasn't reported back with completed
1695 * batchbuffers in a long time. The first time this is called we simply record
1696 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1697 * again, we assume the chip is wedged and try to fix it.
1698 */
1699void i915_hangcheck_elapsed(unsigned long data)
1700{
1701 struct drm_device *dev = (struct drm_device *)data;
1702 drm_i915_private_t *dev_priv = dev->dev_private;
bd9854f9 1703 uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
b4519513
CW		 1704 struct intel_ring_buffer *ring;
1705 bool err = false, idle;
1706 int i;
893eead0 1707
3e0dc6b0
BW		 1708 if (!i915_enable_hangcheck)
1709 return;
1710
b4519513
CW		 1711 memset(acthd, 0, sizeof(acthd));
1712 idle = true;
1713 for_each_ring(ring, dev_priv, i) {
1714 idle &= i915_hangcheck_ring_idle(ring, &err);
1715 acthd[i] = intel_ring_get_active_head(ring);
1716 }
1717
893eead0 1718 /* If all work is done then ACTHD clearly hasn't advanced. */
b4519513 1719 if (idle) {
d1e61e7f
CW		 1720 if (err) {
1721 if (i915_hangcheck_hung(dev))
1722 return;
1723
893eead0 1724 goto repeat;
d1e61e7f
CW		 1725 }
1726
1727 dev_priv->hangcheck_count = 0;
893eead0
CW		 1728 return;
1729 }
b9201c14 1730
bd9854f9 1731 i915_get_extra_instdone(dev, instdone);
b4519513 1732 if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 &&
050ee91f 1733 memcmp(dev_priv->prev_instdone, instdone, sizeof(instdone)) == 0) {
d1e61e7f 1734 if (i915_hangcheck_hung(dev))
cbb465e7 1735 return;
cbb465e7
CW		 1736 } else {
1737 dev_priv->hangcheck_count = 0;
1738
b4519513 1739 memcpy(dev_priv->last_acthd, acthd, sizeof(acthd));
050ee91f 1740 memcpy(dev_priv->prev_instdone, instdone, sizeof(instdone));
cbb465e7 1741 }
f65d9421 1742
893eead0 1743repeat:
f65d9421 1744 /* Reset timer case chip hangs without another request being added */
b3b079db
CW		 1745 mod_timer(&dev_priv->hangcheck_timer,
1746 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
f65d9421
BG		 1747}
1748
1da177e4
LT		 1749/* drm_dma.h hooks
1750*/
f71d4af4 1751static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 1752{
1753 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1754
4697995b
JB		 1755 atomic_set(&dev_priv->irq_received, 0);
1756
036a4a7d 1757 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 1758
036a4a7d
ZW		 1759 /* XXX hotplug from PCH */
1760
1761 I915_WRITE(DEIMR, 0xffffffff);
1762 I915_WRITE(DEIER, 0x0);
3143a2bf 1763 POSTING_READ(DEIER);
036a4a7d
ZW		 1764
1765 /* and GT */
1766 I915_WRITE(GTIMR, 0xffffffff);
1767 I915_WRITE(GTIER, 0x0);
3143a2bf 1768 POSTING_READ(GTIER);
c650156a
ZW		 1769
1770 /* south display irq */
1771 I915_WRITE(SDEIMR, 0xffffffff);
1772 I915_WRITE(SDEIER, 0x0);
3143a2bf 1773 POSTING_READ(SDEIER);
036a4a7d
ZW		 1774}
1775
7e231dbe
JB		 1776static void valleyview_irq_preinstall(struct drm_device *dev)
1777{
1778 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1779 int pipe;
1780
1781 atomic_set(&dev_priv->irq_received, 0);
1782
7e231dbe
JB		 1783 /* VLV magic */
1784 I915_WRITE(VLV_IMR, 0);
1785 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1786 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1787 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1788
7e231dbe
JB		 1789 /* and GT */
1790 I915_WRITE(GTIIR, I915_READ(GTIIR));
1791 I915_WRITE(GTIIR, I915_READ(GTIIR));
1792 I915_WRITE(GTIMR, 0xffffffff);
1793 I915_WRITE(GTIER, 0x0);
1794 POSTING_READ(GTIER);
1795
1796 I915_WRITE(DPINVGTT, 0xff);
1797
1798 I915_WRITE(PORT_HOTPLUG_EN, 0);
1799 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1800 for_each_pipe(pipe)
1801 I915_WRITE(PIPESTAT(pipe), 0xffff);
1802 I915_WRITE(VLV_IIR, 0xffffffff);
1803 I915_WRITE(VLV_IMR, 0xffffffff);
1804 I915_WRITE(VLV_IER, 0x0);
1805 POSTING_READ(VLV_IER);
1806}
1807
7fe0b973
KP		 1808/*
1809 * Enable digital hotplug on the PCH, and configure the DP short pulse
1810 * duration to 2ms (which is the minimum in the Display Port spec)
1811 *
1812 * This register is the same on all known PCH chips.
1813 */
1814
1815static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1816{
1817 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1818 u32 hotplug;
1819
1820 hotplug = I915_READ(PCH_PORT_HOTPLUG);
1821 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1822 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1823 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1824 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1825 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1826}
1827
f71d4af4 1828static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d
ZW		 1829{
1830 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1831 /* enable kind of interrupts always enabled */
013d5aa2
JB		 1832 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1833 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1ec14ad3 1834 u32 render_irqs;
2d7b8366 1835 u32 hotplug_mask;
036a4a7d 1836
1ec14ad3 1837 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 1838
1839 /* should always can generate irq */
1840 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3
CW		 1841 I915_WRITE(DEIMR, dev_priv->irq_mask);
1842 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
3143a2bf 1843 POSTING_READ(DEIER);
036a4a7d 1844
1ec14ad3 1845 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 1846
1847 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 1848 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 1849
1ec14ad3
CW		 1850 if (IS_GEN6(dev))
1851 render_irqs =
1852 GT_USER_INTERRUPT |
e2a1e2f0
BW		 1853 GEN6_BSD_USER_INTERRUPT |
1854 GEN6_BLITTER_USER_INTERRUPT;
1ec14ad3
CW		 1855 else
1856 render_irqs =
88f23b8f 1857 GT_USER_INTERRUPT |
c6df541c 1858 GT_PIPE_NOTIFY |
1ec14ad3
CW		 1859 GT_BSD_USER_INTERRUPT;
1860 I915_WRITE(GTIER, render_irqs);
3143a2bf 1861 POSTING_READ(GTIER);
036a4a7d 1862
2d7b8366 1863 if (HAS_PCH_CPT(dev)) {
9035a97a
CW		 1864 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1865 SDE_PORTB_HOTPLUG_CPT |
1866 SDE_PORTC_HOTPLUG_CPT |
1867 SDE_PORTD_HOTPLUG_CPT);
2d7b8366 1868 } else {
9035a97a
CW		 1869 hotplug_mask = (SDE_CRT_HOTPLUG |
1870 SDE_PORTB_HOTPLUG |
1871 SDE_PORTC_HOTPLUG |
1872 SDE_PORTD_HOTPLUG |
1873 SDE_AUX_MASK);
2d7b8366
YL		 1874 }
1875
1ec14ad3 1876 dev_priv->pch_irq_mask = ~hotplug_mask;
c650156a
ZW		 1877
1878 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1ec14ad3
CW		 1879 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1880 I915_WRITE(SDEIER, hotplug_mask);
3143a2bf 1881 POSTING_READ(SDEIER);
c650156a 1882
7fe0b973
KP		 1883 ironlake_enable_pch_hotplug(dev);
1884
f97108d1
JB		 1885 if (IS_IRONLAKE_M(dev)) {
1886 /* Clear & enable PCU event interrupts */
1887 I915_WRITE(DEIIR, DE_PCU_EVENT);
1888 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1889 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1890 }
1891
036a4a7d
ZW		 1892 return 0;
1893}
1894
f71d4af4 1895static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 1896{
1897 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1898 /* enable kind of interrupts always enabled */
b615b57a
CW		 1899 u32 display_mask =
1900 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
1901 DE_PLANEC_FLIP_DONE_IVB |
1902 DE_PLANEB_FLIP_DONE_IVB |
1903 DE_PLANEA_FLIP_DONE_IVB;
b1f14ad0
JB		 1904 u32 render_irqs;
1905 u32 hotplug_mask;
1906
b1f14ad0
JB		 1907 dev_priv->irq_mask = ~display_mask;
1908
1909 /* should always can generate irq */
1910 I915_WRITE(DEIIR, I915_READ(DEIIR));
1911 I915_WRITE(DEIMR, dev_priv->irq_mask);
b615b57a
CW		 1912 I915_WRITE(DEIER,
1913 display_mask |
1914 DE_PIPEC_VBLANK_IVB |
1915 DE_PIPEB_VBLANK_IVB |
1916 DE_PIPEA_VBLANK_IVB);
b1f14ad0
JB		 1917 POSTING_READ(DEIER);
1918
15b9f80e 1919 dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 1920
1921 I915_WRITE(GTIIR, I915_READ(GTIIR));
1922 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1923
e2a1e2f0 1924 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
15b9f80e 1925 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 1926 I915_WRITE(GTIER, render_irqs);
1927 POSTING_READ(GTIER);
1928
1929 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1930 SDE_PORTB_HOTPLUG_CPT |
1931 SDE_PORTC_HOTPLUG_CPT |
1932 SDE_PORTD_HOTPLUG_CPT);
1933 dev_priv->pch_irq_mask = ~hotplug_mask;
1934
1935 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1936 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1937 I915_WRITE(SDEIER, hotplug_mask);
1938 POSTING_READ(SDEIER);
1939
7fe0b973
KP		 1940 ironlake_enable_pch_hotplug(dev);
1941
b1f14ad0
JB		 1942 return 0;
1943}
1944
7e231dbe
JB		 1945static int valleyview_irq_postinstall(struct drm_device *dev)
1946{
1947 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7e231dbe
JB		 1948 u32 enable_mask;
1949 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
31acc7f5 1950 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
7e231dbe
JB		 1951 u16 msid;
1952
1953 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
31acc7f5
JB		 1954 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
1955 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1956 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
7e231dbe
JB		 1957 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1958
31acc7f5
JB		 1959 /*
1960 *Leave vblank interrupts masked initially. enable/disable will
1961 * toggle them based on usage.
1962 */
1963 dev_priv->irq_mask = (~enable_mask) |
1964 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1965 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1966
7e231dbe
JB		 1967 dev_priv->pipestat[0] = 0;
1968 dev_priv->pipestat[1] = 0;
1969
7e231dbe
JB		 1970 /* Hack for broken MSIs on VLV */
1971 pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
1972 pci_read_config_word(dev->pdev, 0x98, &msid);
1973 msid &= 0xff; /* mask out delivery bits */
1974 msid |= (1<<14);
1975 pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
1976
1977 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
1978 I915_WRITE(VLV_IER, enable_mask);
1979 I915_WRITE(VLV_IIR, 0xffffffff);
1980 I915_WRITE(PIPESTAT(0), 0xffff);
1981 I915_WRITE(PIPESTAT(1), 0xffff);
1982 POSTING_READ(VLV_IER);
1983
31acc7f5
JB		 1984 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
1985 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
1986
7e231dbe
JB		 1987 I915_WRITE(VLV_IIR, 0xffffffff);
1988 I915_WRITE(VLV_IIR, 0xffffffff);
1989
31acc7f5 1990 dev_priv->gt_irq_mask = ~0;
7e231dbe
JB		 1991
1992 I915_WRITE(GTIIR, I915_READ(GTIIR));
1993 I915_WRITE(GTIIR, I915_READ(GTIIR));
31acc7f5
JB		 1994 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1995 I915_WRITE(GTIER, GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
1996 GT_GEN6_BLT_CS_ERROR_INTERRUPT |
1997 GT_GEN6_BLT_USER_INTERRUPT |
1998 GT_GEN6_BSD_USER_INTERRUPT |
1999 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
2000 GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
2001 GT_PIPE_NOTIFY |
2002 GT_RENDER_CS_ERROR_INTERRUPT |
2003 GT_SYNC_STATUS |
2004 GT_USER_INTERRUPT);
7e231dbe
JB		 2005 POSTING_READ(GTIER);
2006
2007 /* ack & enable invalid PTE error interrupts */
2008#if 0 /* FIXME: add support to irq handler for checking these bits */
2009 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2010 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2011#endif
2012
2013 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2014#if 0 /* FIXME: check register definitions; some have moved */
2015 /* Note HDMI and DP share bits */
2016 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2017 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2018 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2019 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2020 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2021 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2022 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2023 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2024 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2025 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2026 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2027 hotplug_en |= CRT_HOTPLUG_INT_EN;
2028 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2029 }
2030#endif
2031
2032 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2033
2034 return 0;
2035}
2036
7e231dbe
JB		 2037static void valleyview_irq_uninstall(struct drm_device *dev)
2038{
2039 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2040 int pipe;
2041
2042 if (!dev_priv)
2043 return;
2044
7e231dbe
JB		 2045 for_each_pipe(pipe)
2046 I915_WRITE(PIPESTAT(pipe), 0xffff);
2047
2048 I915_WRITE(HWSTAM, 0xffffffff);
2049 I915_WRITE(PORT_HOTPLUG_EN, 0);
2050 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2051 for_each_pipe(pipe)
2052 I915_WRITE(PIPESTAT(pipe), 0xffff);
2053 I915_WRITE(VLV_IIR, 0xffffffff);
2054 I915_WRITE(VLV_IMR, 0xffffffff);
2055 I915_WRITE(VLV_IER, 0x0);
2056 POSTING_READ(VLV_IER);
2057}
2058
f71d4af4 2059static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 2060{
2061 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 2062
2063 if (!dev_priv)
2064 return;
2065
036a4a7d
ZW		 2066 I915_WRITE(HWSTAM, 0xffffffff);
2067
2068 I915_WRITE(DEIMR, 0xffffffff);
2069 I915_WRITE(DEIER, 0x0);
2070 I915_WRITE(DEIIR, I915_READ(DEIIR));
2071
2072 I915_WRITE(GTIMR, 0xffffffff);
2073 I915_WRITE(GTIER, 0x0);
2074 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f
KP		 2075
2076 I915_WRITE(SDEIMR, 0xffffffff);
2077 I915_WRITE(SDEIER, 0x0);
2078 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
036a4a7d
ZW		 2079}
2080
a266c7d5 2081static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 2082{
2083 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2084 int pipe;
91e3738e 2085
a266c7d5 2086 atomic_set(&dev_priv->irq_received, 0);
5ca58282 2087
9db4a9c7
JB		 2088 for_each_pipe(pipe)
2089 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 2090 I915_WRITE16(IMR, 0xffff);
2091 I915_WRITE16(IER, 0x0);
2092 POSTING_READ16(IER);
c2798b19
CW		 2093}
2094
2095static int i8xx_irq_postinstall(struct drm_device *dev)
2096{
2097 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2098
c2798b19
CW		 2099 dev_priv->pipestat[0] = 0;
2100 dev_priv->pipestat[1] = 0;
2101
2102 I915_WRITE16(EMR,
2103 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2104
2105 /* Unmask the interrupts that we always want on. */
2106 dev_priv->irq_mask =
2107 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2108 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2109 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2110 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2111 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2112 I915_WRITE16(IMR, dev_priv->irq_mask);
2113
2114 I915_WRITE16(IER,
2115 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2116 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2117 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2118 I915_USER_INTERRUPT);
2119 POSTING_READ16(IER);
2120
2121 return 0;
2122}
2123
2124static irqreturn_t i8xx_irq_handler(DRM_IRQ_ARGS)
2125{
2126 struct drm_device *dev = (struct drm_device *) arg;
2127 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 2128 u16 iir, new_iir;
2129 u32 pipe_stats[2];
2130 unsigned long irqflags;
2131 int irq_received;
2132 int pipe;
2133 u16 flip_mask =
2134 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2135 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2136
2137 atomic_inc(&dev_priv->irq_received);
2138
2139 iir = I915_READ16(IIR);
2140 if (iir == 0)
2141 return IRQ_NONE;
2142
2143 while (iir & ~flip_mask) {
2144 /* Can't rely on pipestat interrupt bit in iir as it might
2145 * have been cleared after the pipestat interrupt was received.
2146 * It doesn't set the bit in iir again, but it still produces
2147 * interrupts (for non-MSI).
2148 */
2149 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2150 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2151 i915_handle_error(dev, false);
2152
2153 for_each_pipe(pipe) {
2154 int reg = PIPESTAT(pipe);
2155 pipe_stats[pipe] = I915_READ(reg);
2156
2157 /*
2158 * Clear the PIPE*STAT regs before the IIR
2159 */
2160 if (pipe_stats[pipe] & 0x8000ffff) {
2161 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2162 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2163 pipe_name(pipe));
2164 I915_WRITE(reg, pipe_stats[pipe]);
2165 irq_received = 1;
2166 }
2167 }
2168 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2169
2170 I915_WRITE16(IIR, iir & ~flip_mask);
2171 new_iir = I915_READ16(IIR); /* Flush posted writes */
2172
d05c617e 2173 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 2174
2175 if (iir & I915_USER_INTERRUPT)
2176 notify_ring(dev, &dev_priv->ring[RCS]);
2177
2178 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2179 drm_handle_vblank(dev, 0)) {
2180 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2181 intel_prepare_page_flip(dev, 0);
2182 intel_finish_page_flip(dev, 0);
2183 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2184 }
2185 }
2186
2187 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2188 drm_handle_vblank(dev, 1)) {
2189 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2190 intel_prepare_page_flip(dev, 1);
2191 intel_finish_page_flip(dev, 1);
2192 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2193 }
2194 }
2195
2196 iir = new_iir;
2197 }
2198
2199 return IRQ_HANDLED;
2200}
2201
2202static void i8xx_irq_uninstall(struct drm_device * dev)
2203{
2204 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2205 int pipe;
2206
c2798b19
CW		 2207 for_each_pipe(pipe) {
2208 /* Clear enable bits; then clear status bits */
2209 I915_WRITE(PIPESTAT(pipe), 0);
2210 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2211 }
2212 I915_WRITE16(IMR, 0xffff);
2213 I915_WRITE16(IER, 0x0);
2214 I915_WRITE16(IIR, I915_READ16(IIR));
2215}
2216
a266c7d5
CW		 2217static void i915_irq_preinstall(struct drm_device * dev)
2218{
2219 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2220 int pipe;
2221
2222 atomic_set(&dev_priv->irq_received, 0);
2223
2224 if (I915_HAS_HOTPLUG(dev)) {
2225 I915_WRITE(PORT_HOTPLUG_EN, 0);
2226 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2227 }
2228
00d98ebd 2229 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 2230 for_each_pipe(pipe)
2231 I915_WRITE(PIPESTAT(pipe), 0);
2232 I915_WRITE(IMR, 0xffffffff);
2233 I915_WRITE(IER, 0x0);
2234 POSTING_READ(IER);
2235}
2236
2237static int i915_irq_postinstall(struct drm_device *dev)
2238{
2239 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 2240 u32 enable_mask;
a266c7d5 2241
a266c7d5
CW		 2242 dev_priv->pipestat[0] = 0;
2243 dev_priv->pipestat[1] = 0;
2244
38bde180
CW		 2245 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2246
2247 /* Unmask the interrupts that we always want on. */
2248 dev_priv->irq_mask =
2249 ~(I915_ASLE_INTERRUPT |
2250 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2251 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2252 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2253 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2254 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2255
2256 enable_mask =
2257 I915_ASLE_INTERRUPT |
2258 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2259 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2260 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2261 I915_USER_INTERRUPT;
2262
a266c7d5
CW		 2263 if (I915_HAS_HOTPLUG(dev)) {
2264 /* Enable in IER... */
2265 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2266 /* and unmask in IMR */
2267 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2268 }
2269
a266c7d5
CW		 2270 I915_WRITE(IMR, dev_priv->irq_mask);
2271 I915_WRITE(IER, enable_mask);
2272 POSTING_READ(IER);
2273
2274 if (I915_HAS_HOTPLUG(dev)) {
2275 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2276
a266c7d5
CW		 2277 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2278 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2279 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2280 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2281 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2282 hotplug_en |= HDMID_HOTPLUG_INT_EN;
084b612e 2283 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
a266c7d5 2284 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
084b612e 2285 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
a266c7d5
CW		 2286 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2287 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2288 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5
CW		 2289 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2290 }
2291
2292 /* Ignore TV since it's buggy */
2293
2294 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2295 }
2296
2297 intel_opregion_enable_asle(dev);
2298
2299 return 0;
2300}
2301
2302static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
2303{
2304 struct drm_device *dev = (struct drm_device *) arg;
2305 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 2306 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 2307 unsigned long irqflags;
38bde180
CW		 2308 u32 flip_mask =
2309 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2310 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2311 u32 flip[2] = {
2312 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2313 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2314 };
2315 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 2316
2317 atomic_inc(&dev_priv->irq_received);
2318
2319 iir = I915_READ(IIR);
38bde180
CW		 2320 do {
2321 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 2322 bool blc_event = false;
a266c7d5
CW		 2323
2324 /* Can't rely on pipestat interrupt bit in iir as it might
2325 * have been cleared after the pipestat interrupt was received.
2326 * It doesn't set the bit in iir again, but it still produces
2327 * interrupts (for non-MSI).
2328 */
2329 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2330 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2331 i915_handle_error(dev, false);
2332
2333 for_each_pipe(pipe) {
2334 int reg = PIPESTAT(pipe);
2335 pipe_stats[pipe] = I915_READ(reg);
2336
38bde180 2337 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 2338 if (pipe_stats[pipe] & 0x8000ffff) {
2339 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2340 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2341 pipe_name(pipe));
2342 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 2343 irq_received = true;
a266c7d5
CW		 2344 }
2345 }
2346 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2347
2348 if (!irq_received)
2349 break;
2350
a266c7d5
CW		 2351 /* Consume port. Then clear IIR or we'll miss events */
2352 if ((I915_HAS_HOTPLUG(dev)) &&
2353 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2354 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2355
2356 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2357 hotplug_status);
2358 if (hotplug_status & dev_priv->hotplug_supported_mask)
2359 queue_work(dev_priv->wq,
2360 &dev_priv->hotplug_work);
2361
2362 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 2363 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 2364 }
2365
38bde180 2366 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2367 new_iir = I915_READ(IIR); /* Flush posted writes */
2368
a266c7d5
CW		 2369 if (iir & I915_USER_INTERRUPT)
2370 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 2371
a266c7d5 2372 for_each_pipe(pipe) {
38bde180
CW		 2373 int plane = pipe;
2374 if (IS_MOBILE(dev))
2375 plane = !plane;
8291ee90 2376 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2377 drm_handle_vblank(dev, pipe)) {
38bde180
CW		 2378 if (iir & flip[plane]) {
2379 intel_prepare_page_flip(dev, plane);
2380 intel_finish_page_flip(dev, pipe);
2381 flip_mask &= ~flip[plane];
2382 }
a266c7d5
CW		 2383 }
2384
2385 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2386 blc_event = true;
2387 }
2388
a266c7d5
CW		 2389 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2390 intel_opregion_asle_intr(dev);
2391
2392 /* With MSI, interrupts are only generated when iir
2393 * transitions from zero to nonzero. If another bit got
2394 * set while we were handling the existing iir bits, then
2395 * we would never get another interrupt.
2396 *
2397 * This is fine on non-MSI as well, as if we hit this path
2398 * we avoid exiting the interrupt handler only to generate
2399 * another one.
2400 *
2401 * Note that for MSI this could cause a stray interrupt report
2402 * if an interrupt landed in the time between writing IIR and
2403 * the posting read. This should be rare enough to never
2404 * trigger the 99% of 100,000 interrupts test for disabling
2405 * stray interrupts.
2406 */
38bde180 2407 ret = IRQ_HANDLED;
a266c7d5 2408 iir = new_iir;
38bde180 2409 } while (iir & ~flip_mask);
a266c7d5 2410
d05c617e 2411 i915_update_dri1_breadcrumb(dev);
8291ee90 2412
a266c7d5
CW		 2413 return ret;
2414}
2415
2416static void i915_irq_uninstall(struct drm_device * dev)
2417{
2418 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2419 int pipe;
2420
a266c7d5
CW		 2421 if (I915_HAS_HOTPLUG(dev)) {
2422 I915_WRITE(PORT_HOTPLUG_EN, 0);
2423 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2424 }
2425
00d98ebd 2426 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 2427 for_each_pipe(pipe) {
2428 /* Clear enable bits; then clear status bits */
a266c7d5 2429 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 2430 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2431 }
a266c7d5
CW		 2432 I915_WRITE(IMR, 0xffffffff);
2433 I915_WRITE(IER, 0x0);
2434
a266c7d5
CW		 2435 I915_WRITE(IIR, I915_READ(IIR));
2436}
2437
2438static void i965_irq_preinstall(struct drm_device * dev)
2439{
2440 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2441 int pipe;
2442
2443 atomic_set(&dev_priv->irq_received, 0);
2444
adca4730
CW		 2445 I915_WRITE(PORT_HOTPLUG_EN, 0);
2446 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2447
2448 I915_WRITE(HWSTAM, 0xeffe);
2449 for_each_pipe(pipe)
2450 I915_WRITE(PIPESTAT(pipe), 0);
2451 I915_WRITE(IMR, 0xffffffff);
2452 I915_WRITE(IER, 0x0);
2453 POSTING_READ(IER);
2454}
2455
2456static int i965_irq_postinstall(struct drm_device *dev)
2457{
2458 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
adca4730 2459 u32 hotplug_en;
bbba0a97 2460 u32 enable_mask;
a266c7d5
CW		 2461 u32 error_mask;
2462
a266c7d5 2463 /* Unmask the interrupts that we always want on. */
bbba0a97 2464 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 2465 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 2466 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2467 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2468 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2469 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2470 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2471
2472 enable_mask = ~dev_priv->irq_mask;
2473 enable_mask |= I915_USER_INTERRUPT;
2474
2475 if (IS_G4X(dev))
2476 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5
CW		 2477
2478 dev_priv->pipestat[0] = 0;
2479 dev_priv->pipestat[1] = 0;
2480
a266c7d5
CW		 2481 /*
2482 * Enable some error detection, note the instruction error mask
2483 * bit is reserved, so we leave it masked.
2484 */
2485 if (IS_G4X(dev)) {
2486 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2487 GM45_ERROR_MEM_PRIV |
2488 GM45_ERROR_CP_PRIV |
2489 I915_ERROR_MEMORY_REFRESH);
2490 } else {
2491 error_mask = ~(I915_ERROR_PAGE_TABLE |
2492 I915_ERROR_MEMORY_REFRESH);
2493 }
2494 I915_WRITE(EMR, error_mask);
2495
2496 I915_WRITE(IMR, dev_priv->irq_mask);
2497 I915_WRITE(IER, enable_mask);
2498 POSTING_READ(IER);
2499
adca4730
CW		 2500 /* Note HDMI and DP share hotplug bits */
2501 hotplug_en = 0;
2502 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2503 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2504 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2505 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2506 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2507 hotplug_en |= HDMID_HOTPLUG_INT_EN;
084b612e
CW		 2508 if (IS_G4X(dev)) {
2509 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
2510 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2511 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
2512 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2513 } else {
2514 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
2515 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2516 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
2517 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2518 }
adca4730
CW		 2519 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2520 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5 2521
adca4730
CW		 2522 /* Programming the CRT detection parameters tends
2523 to generate a spurious hotplug event about three
2524 seconds later. So just do it once.
2525 */
2526 if (IS_G4X(dev))
2527 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2528 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2529 }
a266c7d5 2530
adca4730 2531 /* Ignore TV since it's buggy */
a266c7d5 2532
adca4730 2533 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
a266c7d5
CW		 2534
2535 intel_opregion_enable_asle(dev);
2536
2537 return 0;
2538}
2539
2540static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS)
2541{
2542 struct drm_device *dev = (struct drm_device *) arg;
2543 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 2544 u32 iir, new_iir;
2545 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 2546 unsigned long irqflags;
2547 int irq_received;
2548 int ret = IRQ_NONE, pipe;
a266c7d5
CW		 2549
2550 atomic_inc(&dev_priv->irq_received);
2551
2552 iir = I915_READ(IIR);
2553
a266c7d5 2554 for (;;) {
2c8ba29f
CW		 2555 bool blc_event = false;
2556
a266c7d5
CW		 2557 irq_received = iir != 0;
2558
2559 /* Can't rely on pipestat interrupt bit in iir as it might
2560 * have been cleared after the pipestat interrupt was received.
2561 * It doesn't set the bit in iir again, but it still produces
2562 * interrupts (for non-MSI).
2563 */
2564 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2565 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2566 i915_handle_error(dev, false);
2567
2568 for_each_pipe(pipe) {
2569 int reg = PIPESTAT(pipe);
2570 pipe_stats[pipe] = I915_READ(reg);
2571
2572 /*
2573 * Clear the PIPE*STAT regs before the IIR
2574 */
2575 if (pipe_stats[pipe] & 0x8000ffff) {
2576 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2577 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2578 pipe_name(pipe));
2579 I915_WRITE(reg, pipe_stats[pipe]);
2580 irq_received = 1;
2581 }
2582 }
2583 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2584
2585 if (!irq_received)
2586 break;
2587
2588 ret = IRQ_HANDLED;
2589
2590 /* Consume port. Then clear IIR or we'll miss events */
adca4730 2591 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
a266c7d5
CW		 2592 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2593
2594 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2595 hotplug_status);
2596 if (hotplug_status & dev_priv->hotplug_supported_mask)
2597 queue_work(dev_priv->wq,
2598 &dev_priv->hotplug_work);
2599
2600 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2601 I915_READ(PORT_HOTPLUG_STAT);
2602 }
2603
2604 I915_WRITE(IIR, iir);
2605 new_iir = I915_READ(IIR); /* Flush posted writes */
2606
a266c7d5
CW		 2607 if (iir & I915_USER_INTERRUPT)
2608 notify_ring(dev, &dev_priv->ring[RCS]);
2609 if (iir & I915_BSD_USER_INTERRUPT)
2610 notify_ring(dev, &dev_priv->ring[VCS]);
2611
4f7d1e79 2612 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
a266c7d5 2613 intel_prepare_page_flip(dev, 0);
a266c7d5 2614
4f7d1e79 2615 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
a266c7d5 2616 intel_prepare_page_flip(dev, 1);
a266c7d5
CW		 2617
2618 for_each_pipe(pipe) {
2c8ba29f 2619 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2620 drm_handle_vblank(dev, pipe)) {
4f7d1e79
CW		 2621 i915_pageflip_stall_check(dev, pipe);
2622 intel_finish_page_flip(dev, pipe);
a266c7d5
CW		 2623 }
2624
2625 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2626 blc_event = true;
2627 }
2628
2629
2630 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2631 intel_opregion_asle_intr(dev);
2632
2633 /* With MSI, interrupts are only generated when iir
2634 * transitions from zero to nonzero. If another bit got
2635 * set while we were handling the existing iir bits, then
2636 * we would never get another interrupt.
2637 *
2638 * This is fine on non-MSI as well, as if we hit this path
2639 * we avoid exiting the interrupt handler only to generate
2640 * another one.
2641 *
2642 * Note that for MSI this could cause a stray interrupt report
2643 * if an interrupt landed in the time between writing IIR and
2644 * the posting read. This should be rare enough to never
2645 * trigger the 99% of 100,000 interrupts test for disabling
2646 * stray interrupts.
2647 */
2648 iir = new_iir;
2649 }
2650
d05c617e 2651 i915_update_dri1_breadcrumb(dev);
2c8ba29f 2652
a266c7d5
CW		 2653 return ret;
2654}
2655
2656static void i965_irq_uninstall(struct drm_device * dev)
2657{
2658 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2659 int pipe;
2660
2661 if (!dev_priv)
2662 return;
2663
adca4730
CW		 2664 I915_WRITE(PORT_HOTPLUG_EN, 0);
2665 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2666
2667 I915_WRITE(HWSTAM, 0xffffffff);
2668 for_each_pipe(pipe)
2669 I915_WRITE(PIPESTAT(pipe), 0);
2670 I915_WRITE(IMR, 0xffffffff);
2671 I915_WRITE(IER, 0x0);
2672
2673 for_each_pipe(pipe)
2674 I915_WRITE(PIPESTAT(pipe),
2675 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2676 I915_WRITE(IIR, I915_READ(IIR));
2677}
2678
f71d4af4
JB		 2679void intel_irq_init(struct drm_device *dev)
2680{
8b2e326d
CW		 2681 struct drm_i915_private *dev_priv = dev->dev_private;
2682
2683 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2684 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
c6a828d3 2685 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
98fd81cd 2686 INIT_WORK(&dev_priv->parity_error_work, ivybridge_parity_work);
8b2e326d 2687
f71d4af4
JB		 2688 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2689 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7d4e146f 2690 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 2691 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2692 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2693 }
2694
c3613de9
KP		 2695 if (drm_core_check_feature(dev, DRIVER_MODESET))
2696 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2697 else
2698 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 2699 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2700
7e231dbe
JB		 2701 if (IS_VALLEYVIEW(dev)) {
2702 dev->driver->irq_handler = valleyview_irq_handler;
2703 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2704 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2705 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2706 dev->driver->enable_vblank = valleyview_enable_vblank;
2707 dev->driver->disable_vblank = valleyview_disable_vblank;
2708 } else if (IS_IVYBRIDGE(dev)) {
f71d4af4
JB		 2709 /* Share pre & uninstall handlers with ILK/SNB */
2710 dev->driver->irq_handler = ivybridge_irq_handler;
2711 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2712 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2713 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2714 dev->driver->enable_vblank = ivybridge_enable_vblank;
2715 dev->driver->disable_vblank = ivybridge_disable_vblank;
7d4e146f
ED		 2716 } else if (IS_HASWELL(dev)) {
2717 /* Share interrupts handling with IVB */
2718 dev->driver->irq_handler = ivybridge_irq_handler;
2719 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2720 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2721 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2722 dev->driver->enable_vblank = ivybridge_enable_vblank;
2723 dev->driver->disable_vblank = ivybridge_disable_vblank;
f71d4af4
JB		 2724 } else if (HAS_PCH_SPLIT(dev)) {
2725 dev->driver->irq_handler = ironlake_irq_handler;
2726 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2727 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2728 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2729 dev->driver->enable_vblank = ironlake_enable_vblank;
2730 dev->driver->disable_vblank = ironlake_disable_vblank;
2731 } else {
c2798b19
CW		 2732 if (INTEL_INFO(dev)->gen == 2) {
2733 dev->driver->irq_preinstall = i8xx_irq_preinstall;
2734 dev->driver->irq_postinstall = i8xx_irq_postinstall;
2735 dev->driver->irq_handler = i8xx_irq_handler;
2736 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5 2737 } else if (INTEL_INFO(dev)->gen == 3) {
4f7d1e79
CW		 2738 /* IIR "flip pending" means done if this bit is set */
2739 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
2740
a266c7d5
CW		 2741 dev->driver->irq_preinstall = i915_irq_preinstall;
2742 dev->driver->irq_postinstall = i915_irq_postinstall;
2743 dev->driver->irq_uninstall = i915_irq_uninstall;
2744 dev->driver->irq_handler = i915_irq_handler;
c2798b19 2745 } else {
a266c7d5
CW		 2746 dev->driver->irq_preinstall = i965_irq_preinstall;
2747 dev->driver->irq_postinstall = i965_irq_postinstall;
2748 dev->driver->irq_uninstall = i965_irq_uninstall;
2749 dev->driver->irq_handler = i965_irq_handler;
c2798b19 2750 }
f71d4af4
JB		 2751 dev->driver->enable_vblank = i915_enable_vblank;
2752 dev->driver->disable_vblank = i915_disable_vblank;
2753 }
2754}
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