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drm/i915: create a race-free reset detection
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/i915_drm.h>
1da177e4 35#include "i915_drv.h"
1c5d22f7 36#include "i915_trace.h"
79e53945 37#include "intel_drv.h"
1da177e4 38
036a4a7d 39/* For display hotplug interrupt */
995b6762 40static void
f2b115e6 41ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 42{
1ec14ad3
CW		 43 if ((dev_priv->irq_mask & mask) != 0) {
44 dev_priv->irq_mask &= ~mask;
45 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 46 POSTING_READ(DEIMR);
036a4a7d
ZW		 47 }
48}
49
50static inline void
f2b115e6 51ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 52{
1ec14ad3
CW		 53 if ((dev_priv->irq_mask & mask) != mask) {
54 dev_priv->irq_mask |= mask;
55 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 56 POSTING_READ(DEIMR);
036a4a7d
ZW		 57 }
58}
59
7c463586
KP		 60void
61i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
62{
63 if ((dev_priv->pipestat[pipe] & mask) != mask) {
9db4a9c7 64 u32 reg = PIPESTAT(pipe);
7c463586
KP		 65
66 dev_priv->pipestat[pipe] |= mask;
67 /* Enable the interrupt, clear any pending status */
68 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
3143a2bf 69 POSTING_READ(reg);
7c463586
KP		 70 }
71}
72
73void
74i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
75{
76 if ((dev_priv->pipestat[pipe] & mask) != 0) {
9db4a9c7 77 u32 reg = PIPESTAT(pipe);
7c463586
KP		 78
79 dev_priv->pipestat[pipe] &= ~mask;
80 I915_WRITE(reg, dev_priv->pipestat[pipe]);
3143a2bf 81 POSTING_READ(reg);
7c463586
KP		 82 }
83}
84
01c66889
ZY		 85/**
86 * intel_enable_asle - enable ASLE interrupt for OpRegion
87 */
1ec14ad3 88void intel_enable_asle(struct drm_device *dev)
01c66889 89{
1ec14ad3
CW		 90 drm_i915_private_t *dev_priv = dev->dev_private;
91 unsigned long irqflags;
92
7e231dbe
JB		 93 /* FIXME: opregion/asle for VLV */
94 if (IS_VALLEYVIEW(dev))
95 return;
96
1ec14ad3 97 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 98
c619eed4 99 if (HAS_PCH_SPLIT(dev))
f2b115e6 100 ironlake_enable_display_irq(dev_priv, DE_GSE);
edcb49ca 101 else {
01c66889 102 i915_enable_pipestat(dev_priv, 1,
d874bcff 103 PIPE_LEGACY_BLC_EVENT_ENABLE);
a6c45cf0 104 if (INTEL_INFO(dev)->gen >= 4)
edcb49ca 105 i915_enable_pipestat(dev_priv, 0,
d874bcff 106 PIPE_LEGACY_BLC_EVENT_ENABLE);
edcb49ca 107 }
1ec14ad3
CW		 108
109 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 110}
111
0a3e67a4
JB		 112/**
113 * i915_pipe_enabled - check if a pipe is enabled
114 * @dev: DRM device
115 * @pipe: pipe to check
116 *
117 * Reading certain registers when the pipe is disabled can hang the chip.
118 * Use this routine to make sure the PLL is running and the pipe is active
119 * before reading such registers if unsure.
120 */
121static int
122i915_pipe_enabled(struct drm_device *dev, int pipe)
123{
124 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
702e7a56
PZ		 125 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
126 pipe);
127
128 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
0a3e67a4
JB		 129}
130
42f52ef8
KP		 131/* Called from drm generic code, passed a 'crtc', which
132 * we use as a pipe index
133 */
f71d4af4 134static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 135{
136 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
137 unsigned long high_frame;
138 unsigned long low_frame;
5eddb70b 139 u32 high1, high2, low;
0a3e67a4
JB		 140
141 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 142 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 143 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 144 return 0;
145 }
146
9db4a9c7
JB		 147 high_frame = PIPEFRAME(pipe);
148 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 149
0a3e67a4
JB		 150 /*
151 * High & low register fields aren't synchronized, so make sure
152 * we get a low value that's stable across two reads of the high
153 * register.
154 */
155 do {
5eddb70b
CW		 156 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
157 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
158 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 159 } while (high1 != high2);
160
5eddb70b
CW		 161 high1 >>= PIPE_FRAME_HIGH_SHIFT;
162 low >>= PIPE_FRAME_LOW_SHIFT;
163 return (high1 << 8) | low;
0a3e67a4
JB		 164}
165
f71d4af4 166static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 167{
168 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 169 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 170
171 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 172 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 173 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 174 return 0;
175 }
176
177 return I915_READ(reg);
178}
179
f71d4af4 180static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 181 int *vpos, int *hpos)
182{
183 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
184 u32 vbl = 0, position = 0;
185 int vbl_start, vbl_end, htotal, vtotal;
186 bool in_vbl = true;
187 int ret = 0;
fe2b8f9d
PZ		 188 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
189 pipe);
0af7e4df
MK		 190
191 if (!i915_pipe_enabled(dev, pipe)) {
192 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 193 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 194 return 0;
195 }
196
197 /* Get vtotal. */
fe2b8f9d 198 vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 199
200 if (INTEL_INFO(dev)->gen >= 4) {
201 /* No obvious pixelcount register. Only query vertical
202 * scanout position from Display scan line register.
203 */
204 position = I915_READ(PIPEDSL(pipe));
205
206 /* Decode into vertical scanout position. Don't have
207 * horizontal scanout position.
208 */
209 *vpos = position & 0x1fff;
210 *hpos = 0;
211 } else {
212 /* Have access to pixelcount since start of frame.
213 * We can split this into vertical and horizontal
214 * scanout position.
215 */
216 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
217
fe2b8f9d 218 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 219 *vpos = position / htotal;
220 *hpos = position - (*vpos * htotal);
221 }
222
223 /* Query vblank area. */
fe2b8f9d 224 vbl = I915_READ(VBLANK(cpu_transcoder));
0af7e4df
MK		 225
226 /* Test position against vblank region. */
227 vbl_start = vbl & 0x1fff;
228 vbl_end = (vbl >> 16) & 0x1fff;
229
230 if ((*vpos < vbl_start) || (*vpos > vbl_end))
231 in_vbl = false;
232
233 /* Inside "upper part" of vblank area? Apply corrective offset: */
234 if (in_vbl && (*vpos >= vbl_start))
235 *vpos = *vpos - vtotal;
236
237 /* Readouts valid? */
238 if (vbl > 0)
239 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
240
241 /* In vblank? */
242 if (in_vbl)
243 ret |= DRM_SCANOUTPOS_INVBL;
244
245 return ret;
246}
247
f71d4af4 248static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 249 int *max_error,
250 struct timeval *vblank_time,
251 unsigned flags)
252{
4041b853
CW		 253 struct drm_i915_private *dev_priv = dev->dev_private;
254 struct drm_crtc *crtc;
0af7e4df 255
4041b853
CW		 256 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
257 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 258 return -EINVAL;
259 }
260
261 /* Get drm_crtc to timestamp: */
4041b853
CW		 262 crtc = intel_get_crtc_for_pipe(dev, pipe);
263 if (crtc == NULL) {
264 DRM_ERROR("Invalid crtc %d\n", pipe);
265 return -EINVAL;
266 }
267
268 if (!crtc->enabled) {
269 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
270 return -EBUSY;
271 }
0af7e4df
MK		 272
273 /* Helper routine in DRM core does all the work: */
4041b853
CW		 274 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
275 vblank_time, flags,
276 crtc);
0af7e4df
MK		 277}
278
5ca58282
JB		 279/*
280 * Handle hotplug events outside the interrupt handler proper.
281 */
282static void i915_hotplug_work_func(struct work_struct *work)
283{
284 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
285 hotplug_work);
286 struct drm_device *dev = dev_priv->dev;
c31c4ba3 287 struct drm_mode_config *mode_config = &dev->mode_config;
4ef69c7a
CW		 288 struct intel_encoder *encoder;
289
52d7eced
DV		 290 /* HPD irq before everything is fully set up. */
291 if (!dev_priv->enable_hotplug_processing)
292 return;
293
a65e34c7 294 mutex_lock(&mode_config->mutex);
e67189ab
JB		 295 DRM_DEBUG_KMS("running encoder hotplug functions\n");
296
4ef69c7a
CW		 297 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
298 if (encoder->hot_plug)
299 encoder->hot_plug(encoder);
300
40ee3381
KP		 301 mutex_unlock(&mode_config->mutex);
302
5ca58282 303 /* Just fire off a uevent and let userspace tell us what to do */
eb1f8e4f 304 drm_helper_hpd_irq_event(dev);
5ca58282
JB		 305}
306
73edd18f 307static void ironlake_handle_rps_change(struct drm_device *dev)
f97108d1
JB		 308{
309 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 310 u32 busy_up, busy_down, max_avg, min_avg;
9270388e
DV		 311 u8 new_delay;
312 unsigned long flags;
313
314 spin_lock_irqsave(&mchdev_lock, flags);
f97108d1 315
73edd18f
DV		 316 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
317
20e4d407 318 new_delay = dev_priv->ips.cur_delay;
9270388e 319
7648fa99 320 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 321 busy_up = I915_READ(RCPREVBSYTUPAVG);
322 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 323 max_avg = I915_READ(RCBMAXAVG);
324 min_avg = I915_READ(RCBMINAVG);
325
326 /* Handle RCS change request from hw */
b5b72e89 327 if (busy_up > max_avg) {
20e4d407
DV		 328 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
329 new_delay = dev_priv->ips.cur_delay - 1;
330 if (new_delay < dev_priv->ips.max_delay)
331 new_delay = dev_priv->ips.max_delay;
b5b72e89 332 } else if (busy_down < min_avg) {
20e4d407
DV		 333 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
334 new_delay = dev_priv->ips.cur_delay + 1;
335 if (new_delay > dev_priv->ips.min_delay)
336 new_delay = dev_priv->ips.min_delay;
f97108d1
JB		 337 }
338
7648fa99 339 if (ironlake_set_drps(dev, new_delay))
20e4d407 340 dev_priv->ips.cur_delay = new_delay;
f97108d1 341
9270388e
DV		 342 spin_unlock_irqrestore(&mchdev_lock, flags);
343
f97108d1
JB		 344 return;
345}
346
549f7365
CW		 347static void notify_ring(struct drm_device *dev,
348 struct intel_ring_buffer *ring)
349{
350 struct drm_i915_private *dev_priv = dev->dev_private;
9862e600 351
475553de
CW		 352 if (ring->obj == NULL)
353 return;
354
b2eadbc8 355 trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
9862e600 356
549f7365 357 wake_up_all(&ring->irq_queue);
3e0dc6b0 358 if (i915_enable_hangcheck) {
99584db3
DV		 359 dev_priv->gpu_error.hangcheck_count = 0;
360 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
cecc21fe 361 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
3e0dc6b0 362 }
549f7365
CW		 363}
364
4912d041 365static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 366{
4912d041 367 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
c6a828d3 368 rps.work);
4912d041 369 u32 pm_iir, pm_imr;
7b9e0ae6 370 u8 new_delay;
4912d041 371
c6a828d3
DV		 372 spin_lock_irq(&dev_priv->rps.lock);
373 pm_iir = dev_priv->rps.pm_iir;
374 dev_priv->rps.pm_iir = 0;
4912d041 375 pm_imr = I915_READ(GEN6_PMIMR);
a9e2641d 376 I915_WRITE(GEN6_PMIMR, 0);
c6a828d3 377 spin_unlock_irq(&dev_priv->rps.lock);
3b8d8d91 378
7b9e0ae6 379 if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
3b8d8d91
JB		 380 return;
381
4fc688ce 382 mutex_lock(&dev_priv->rps.hw_lock);
7b9e0ae6
CW		 383
384 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
c6a828d3 385 new_delay = dev_priv->rps.cur_delay + 1;
7b9e0ae6 386 else
c6a828d3 387 new_delay = dev_priv->rps.cur_delay - 1;
3b8d8d91 388
79249636
BW		 389 /* sysfs frequency interfaces may have snuck in while servicing the
390 * interrupt
391 */
392 if (!(new_delay > dev_priv->rps.max_delay ||
393 new_delay < dev_priv->rps.min_delay)) {
394 gen6_set_rps(dev_priv->dev, new_delay);
395 }
3b8d8d91 396
4fc688ce 397 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91
JB		 398}
399
e3689190
BW		 400
401/**
402 * ivybridge_parity_work - Workqueue called when a parity error interrupt
403 * occurred.
404 * @work: workqueue struct
405 *
406 * Doesn't actually do anything except notify userspace. As a consequence of
407 * this event, userspace should try to remap the bad rows since statistically
408 * it is likely the same row is more likely to go bad again.
409 */
410static void ivybridge_parity_work(struct work_struct *work)
411{
412 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
a4da4fa4 413 l3_parity.error_work);
e3689190
BW		 414 u32 error_status, row, bank, subbank;
415 char *parity_event[5];
416 uint32_t misccpctl;
417 unsigned long flags;
418
419 /* We must turn off DOP level clock gating to access the L3 registers.
420 * In order to prevent a get/put style interface, acquire struct mutex
421 * any time we access those registers.
422 */
423 mutex_lock(&dev_priv->dev->struct_mutex);
424
425 misccpctl = I915_READ(GEN7_MISCCPCTL);
426 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
427 POSTING_READ(GEN7_MISCCPCTL);
428
429 error_status = I915_READ(GEN7_L3CDERRST1);
430 row = GEN7_PARITY_ERROR_ROW(error_status);
431 bank = GEN7_PARITY_ERROR_BANK(error_status);
432 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
433
434 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
435 GEN7_L3CDERRST1_ENABLE);
436 POSTING_READ(GEN7_L3CDERRST1);
437
438 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
439
440 spin_lock_irqsave(&dev_priv->irq_lock, flags);
441 dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
442 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
443 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
444
445 mutex_unlock(&dev_priv->dev->struct_mutex);
446
447 parity_event[0] = "L3_PARITY_ERROR=1";
448 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
449 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
450 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
451 parity_event[4] = NULL;
452
453 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
454 KOBJ_CHANGE, parity_event);
455
456 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
457 row, bank, subbank);
458
459 kfree(parity_event[3]);
460 kfree(parity_event[2]);
461 kfree(parity_event[1]);
462}
463
d2ba8470 464static void ivybridge_handle_parity_error(struct drm_device *dev)
e3689190
BW		 465{
466 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
467 unsigned long flags;
468
e1ef7cc2 469 if (!HAS_L3_GPU_CACHE(dev))
e3689190
BW		 470 return;
471
472 spin_lock_irqsave(&dev_priv->irq_lock, flags);
473 dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
474 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
475 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
476
a4da4fa4 477 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
e3689190
BW		 478}
479
e7b4c6b1
DV		 480static void snb_gt_irq_handler(struct drm_device *dev,
481 struct drm_i915_private *dev_priv,
482 u32 gt_iir)
483{
484
485 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
486 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
487 notify_ring(dev, &dev_priv->ring[RCS]);
488 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
489 notify_ring(dev, &dev_priv->ring[VCS]);
490 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
491 notify_ring(dev, &dev_priv->ring[BCS]);
492
493 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
494 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
495 GT_RENDER_CS_ERROR_INTERRUPT)) {
496 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
497 i915_handle_error(dev, false);
498 }
e3689190
BW		 499
500 if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
501 ivybridge_handle_parity_error(dev);
e7b4c6b1
DV		 502}
503
fc6826d1
CW		 504static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
505 u32 pm_iir)
506{
507 unsigned long flags;
508
509 /*
510 * IIR bits should never already be set because IMR should
511 * prevent an interrupt from being shown in IIR. The warning
512 * displays a case where we've unsafely cleared
c6a828d3 513 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
fc6826d1
CW		 514 * type is not a problem, it displays a problem in the logic.
515 *
c6a828d3 516 * The mask bit in IMR is cleared by dev_priv->rps.work.
fc6826d1
CW		 517 */
518
c6a828d3 519 spin_lock_irqsave(&dev_priv->rps.lock, flags);
c6a828d3
DV		 520 dev_priv->rps.pm_iir |= pm_iir;
521 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
fc6826d1 522 POSTING_READ(GEN6_PMIMR);
c6a828d3 523 spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
fc6826d1 524
c6a828d3 525 queue_work(dev_priv->wq, &dev_priv->rps.work);
fc6826d1
CW		 526}
527
515ac2bb
DV		 528static void gmbus_irq_handler(struct drm_device *dev)
529{
28c70f16
DV		 530 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
531
28c70f16 532 wake_up_all(&dev_priv->gmbus_wait_queue);
515ac2bb
DV		 533}
534
ce99c256
DV		 535static void dp_aux_irq_handler(struct drm_device *dev)
536{
9ee32fea
DV		 537 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
538
9ee32fea 539 wake_up_all(&dev_priv->gmbus_wait_queue);
ce99c256
DV		 540}
541
ff1f525e 542static irqreturn_t valleyview_irq_handler(int irq, void *arg)
7e231dbe
JB		 543{
544 struct drm_device *dev = (struct drm_device *) arg;
545 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
546 u32 iir, gt_iir, pm_iir;
547 irqreturn_t ret = IRQ_NONE;
548 unsigned long irqflags;
549 int pipe;
550 u32 pipe_stats[I915_MAX_PIPES];
7e231dbe
JB		 551
552 atomic_inc(&dev_priv->irq_received);
553
7e231dbe
JB		 554 while (true) {
555 iir = I915_READ(VLV_IIR);
556 gt_iir = I915_READ(GTIIR);
557 pm_iir = I915_READ(GEN6_PMIIR);
558
559 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
560 goto out;
561
562 ret = IRQ_HANDLED;
563
e7b4c6b1 564 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 565
566 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
567 for_each_pipe(pipe) {
568 int reg = PIPESTAT(pipe);
569 pipe_stats[pipe] = I915_READ(reg);
570
571 /*
572 * Clear the PIPE*STAT regs before the IIR
573 */
574 if (pipe_stats[pipe] & 0x8000ffff) {
575 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
576 DRM_DEBUG_DRIVER("pipe %c underrun\n",
577 pipe_name(pipe));
578 I915_WRITE(reg, pipe_stats[pipe]);
579 }
580 }
581 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
582
31acc7f5
JB		 583 for_each_pipe(pipe) {
584 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
585 drm_handle_vblank(dev, pipe);
586
587 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
588 intel_prepare_page_flip(dev, pipe);
589 intel_finish_page_flip(dev, pipe);
590 }
591 }
592
7e231dbe
JB		 593 /* Consume port. Then clear IIR or we'll miss events */
594 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
595 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
596
597 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
598 hotplug_status);
599 if (hotplug_status & dev_priv->hotplug_supported_mask)
600 queue_work(dev_priv->wq,
601 &dev_priv->hotplug_work);
602
603 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
604 I915_READ(PORT_HOTPLUG_STAT);
605 }
606
515ac2bb
DV		 607 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
608 gmbus_irq_handler(dev);
7e231dbe 609
fc6826d1
CW		 610 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
611 gen6_queue_rps_work(dev_priv, pm_iir);
7e231dbe
JB		 612
613 I915_WRITE(GTIIR, gt_iir);
614 I915_WRITE(GEN6_PMIIR, pm_iir);
615 I915_WRITE(VLV_IIR, iir);
616 }
617
618out:
619 return ret;
620}
621
23e81d69 622static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 623{
624 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 625 int pipe;
776ad806 626
76e43830
DV		 627 if (pch_iir & SDE_HOTPLUG_MASK)
628 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
629
776ad806
JB		 630 if (pch_iir & SDE_AUDIO_POWER_MASK)
631 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
632 (pch_iir & SDE_AUDIO_POWER_MASK) >>
633 SDE_AUDIO_POWER_SHIFT);
634
ce99c256
DV		 635 if (pch_iir & SDE_AUX_MASK)
636 dp_aux_irq_handler(dev);
637
776ad806 638 if (pch_iir & SDE_GMBUS)
515ac2bb 639 gmbus_irq_handler(dev);
776ad806
JB		 640
641 if (pch_iir & SDE_AUDIO_HDCP_MASK)
642 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
643
644 if (pch_iir & SDE_AUDIO_TRANS_MASK)
645 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
646
647 if (pch_iir & SDE_POISON)
648 DRM_ERROR("PCH poison interrupt\n");
649
9db4a9c7
JB		 650 if (pch_iir & SDE_FDI_MASK)
651 for_each_pipe(pipe)
652 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
653 pipe_name(pipe),
654 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 655
656 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
657 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
658
659 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
660 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
661
662 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
663 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
664 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
665 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
666}
667
23e81d69
AJ		 668static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
669{
670 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
671 int pipe;
672
76e43830
DV		 673 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
674 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
675
23e81d69
AJ		 676 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
677 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
678 (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
679 SDE_AUDIO_POWER_SHIFT_CPT);
680
681 if (pch_iir & SDE_AUX_MASK_CPT)
ce99c256 682 dp_aux_irq_handler(dev);
23e81d69
AJ		 683
684 if (pch_iir & SDE_GMBUS_CPT)
515ac2bb 685 gmbus_irq_handler(dev);
23e81d69
AJ		 686
687 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
688 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
689
690 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
691 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
692
693 if (pch_iir & SDE_FDI_MASK_CPT)
694 for_each_pipe(pipe)
695 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
696 pipe_name(pipe),
697 I915_READ(FDI_RX_IIR(pipe)));
698}
699
ff1f525e 700static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
b1f14ad0
JB		 701{
702 struct drm_device *dev = (struct drm_device *) arg;
703 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
0e43406b
CW		 704 u32 de_iir, gt_iir, de_ier, pm_iir;
705 irqreturn_t ret = IRQ_NONE;
706 int i;
b1f14ad0
JB		 707
708 atomic_inc(&dev_priv->irq_received);
709
710 /* disable master interrupt before clearing iir */
711 de_ier = I915_READ(DEIER);
712 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
b1f14ad0 713
b1f14ad0 714 gt_iir = I915_READ(GTIIR);
0e43406b
CW		 715 if (gt_iir) {
716 snb_gt_irq_handler(dev, dev_priv, gt_iir);
717 I915_WRITE(GTIIR, gt_iir);
718 ret = IRQ_HANDLED;
b1f14ad0
JB		 719 }
720
0e43406b
CW		 721 de_iir = I915_READ(DEIIR);
722 if (de_iir) {
ce99c256
DV		 723 if (de_iir & DE_AUX_CHANNEL_A_IVB)
724 dp_aux_irq_handler(dev);
725
0e43406b
CW		 726 if (de_iir & DE_GSE_IVB)
727 intel_opregion_gse_intr(dev);
728
729 for (i = 0; i < 3; i++) {
74d44445
DV		 730 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
731 drm_handle_vblank(dev, i);
0e43406b
CW		 732 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
733 intel_prepare_page_flip(dev, i);
734 intel_finish_page_flip_plane(dev, i);
735 }
0e43406b 736 }
b615b57a 737
0e43406b
CW		 738 /* check event from PCH */
739 if (de_iir & DE_PCH_EVENT_IVB) {
740 u32 pch_iir = I915_READ(SDEIIR);
b1f14ad0 741
23e81d69 742 cpt_irq_handler(dev, pch_iir);
b1f14ad0 743
0e43406b
CW		 744 /* clear PCH hotplug event before clear CPU irq */
745 I915_WRITE(SDEIIR, pch_iir);
746 }
b615b57a 747
0e43406b
CW		 748 I915_WRITE(DEIIR, de_iir);
749 ret = IRQ_HANDLED;
b1f14ad0
JB		 750 }
751
0e43406b
CW		 752 pm_iir = I915_READ(GEN6_PMIIR);
753 if (pm_iir) {
754 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
755 gen6_queue_rps_work(dev_priv, pm_iir);
756 I915_WRITE(GEN6_PMIIR, pm_iir);
757 ret = IRQ_HANDLED;
758 }
b1f14ad0 759
b1f14ad0
JB		 760 I915_WRITE(DEIER, de_ier);
761 POSTING_READ(DEIER);
762
763 return ret;
764}
765
e7b4c6b1
DV		 766static void ilk_gt_irq_handler(struct drm_device *dev,
767 struct drm_i915_private *dev_priv,
768 u32 gt_iir)
769{
770 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
771 notify_ring(dev, &dev_priv->ring[RCS]);
772 if (gt_iir & GT_BSD_USER_INTERRUPT)
773 notify_ring(dev, &dev_priv->ring[VCS]);
774}
775
ff1f525e 776static irqreturn_t ironlake_irq_handler(int irq, void *arg)
036a4a7d 777{
4697995b 778 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 779 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
780 int ret = IRQ_NONE;
acd15b6c 781 u32 de_iir, gt_iir, de_ier, pm_iir;
881f47b6 782
4697995b
JB		 783 atomic_inc(&dev_priv->irq_received);
784
2d109a84
ZN		 785 /* disable master interrupt before clearing iir */
786 de_ier = I915_READ(DEIER);
787 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 788 POSTING_READ(DEIER);
2d109a84 789
036a4a7d
ZW		 790 de_iir = I915_READ(DEIIR);
791 gt_iir = I915_READ(GTIIR);
3b8d8d91 792 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 793
acd15b6c 794 if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 795 goto done;
036a4a7d 796
c7c85101 797 ret = IRQ_HANDLED;
036a4a7d 798
e7b4c6b1
DV		 799 if (IS_GEN5(dev))
800 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
801 else
802 snb_gt_irq_handler(dev, dev_priv, gt_iir);
01c66889 803
ce99c256
DV		 804 if (de_iir & DE_AUX_CHANNEL_A)
805 dp_aux_irq_handler(dev);
806
c7c85101 807 if (de_iir & DE_GSE)
3b617967 808 intel_opregion_gse_intr(dev);
c650156a 809
74d44445
DV		 810 if (de_iir & DE_PIPEA_VBLANK)
811 drm_handle_vblank(dev, 0);
812
813 if (de_iir & DE_PIPEB_VBLANK)
814 drm_handle_vblank(dev, 1);
815
f072d2e7 816 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 817 intel_prepare_page_flip(dev, 0);
2bbda389 818 intel_finish_page_flip_plane(dev, 0);
f072d2e7 819 }
013d5aa2 820
f072d2e7 821 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 822 intel_prepare_page_flip(dev, 1);
2bbda389 823 intel_finish_page_flip_plane(dev, 1);
f072d2e7 824 }
013d5aa2 825
c7c85101 826 /* check event from PCH */
776ad806 827 if (de_iir & DE_PCH_EVENT) {
acd15b6c
DV		 828 u32 pch_iir = I915_READ(SDEIIR);
829
23e81d69
AJ		 830 if (HAS_PCH_CPT(dev))
831 cpt_irq_handler(dev, pch_iir);
832 else
833 ibx_irq_handler(dev, pch_iir);
acd15b6c
DV		 834
835 /* should clear PCH hotplug event before clear CPU irq */
836 I915_WRITE(SDEIIR, pch_iir);
776ad806 837 }
036a4a7d 838
73edd18f
DV		 839 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
840 ironlake_handle_rps_change(dev);
f97108d1 841
fc6826d1
CW		 842 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
843 gen6_queue_rps_work(dev_priv, pm_iir);
3b8d8d91 844
c7c85101
ZN		 845 I915_WRITE(GTIIR, gt_iir);
846 I915_WRITE(DEIIR, de_iir);
4912d041 847 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 848
849done:
2d109a84 850 I915_WRITE(DEIER, de_ier);
3143a2bf 851 POSTING_READ(DEIER);
2d109a84 852
036a4a7d
ZW		 853 return ret;
854}
855
8a905236
JB		 856/**
857 * i915_error_work_func - do process context error handling work
858 * @work: work struct
859 *
860 * Fire an error uevent so userspace can see that a hang or error
861 * was detected.
862 */
863static void i915_error_work_func(struct work_struct *work)
864{
1f83fee0
DV		 865 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
866 work);
867 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
868 gpu_error);
8a905236 869 struct drm_device *dev = dev_priv->dev;
f69061be 870 struct intel_ring_buffer *ring;
f316a42c
BG		 871 char *error_event[] = { "ERROR=1", NULL };
872 char *reset_event[] = { "RESET=1", NULL };
873 char *reset_done_event[] = { "ERROR=0", NULL };
f69061be 874 int i, ret;
8a905236 875
f316a42c
BG		 876 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
877
1f83fee0 878 if (i915_reset_in_progress(error)) {
f803aa55
CW		 879 DRM_DEBUG_DRIVER("resetting chip\n");
880 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
1f83fee0 881
f69061be
DV		 882 ret = i915_reset(dev);
883
884 if (ret == 0) {
885 /*
886 * After all the gem state is reset, increment the reset
887 * counter and wake up everyone waiting for the reset to
888 * complete.
889 *
890 * Since unlock operations are a one-sided barrier only,
891 * we need to insert a barrier here to order any seqno
892 * updates before
893 * the counter increment.
894 */
895 smp_mb__before_atomic_inc();
896 atomic_inc(&dev_priv->gpu_error.reset_counter);
897
898 kobject_uevent_env(&dev->primary->kdev.kobj,
899 KOBJ_CHANGE, reset_done_event);
1f83fee0
DV		 900 } else {
901 atomic_set(&error->reset_counter, I915_WEDGED);
f316a42c 902 }
1f83fee0 903
f69061be
DV		 904 for_each_ring(ring, dev_priv, i)
905 wake_up_all(&ring->irq_queue);
906
1f83fee0 907 wake_up_all(&dev_priv->gpu_error.reset_queue);
f316a42c 908 }
8a905236
JB		 909}
910
85f9e50d
DV		 911/* NB: please notice the memset */
912static void i915_get_extra_instdone(struct drm_device *dev,
913 uint32_t *instdone)
914{
915 struct drm_i915_private *dev_priv = dev->dev_private;
916 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
917
918 switch(INTEL_INFO(dev)->gen) {
919 case 2:
920 case 3:
921 instdone[0] = I915_READ(INSTDONE);
922 break;
923 case 4:
924 case 5:
925 case 6:
926 instdone[0] = I915_READ(INSTDONE_I965);
927 instdone[1] = I915_READ(INSTDONE1);
928 break;
929 default:
930 WARN_ONCE(1, "Unsupported platform\n");
931 case 7:
932 instdone[0] = I915_READ(GEN7_INSTDONE_1);
933 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
934 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
935 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
936 break;
937 }
938}
939
3bd3c932 940#ifdef CONFIG_DEBUG_FS
9df30794 941static struct drm_i915_error_object *
bcfb2e28 942i915_error_object_create(struct drm_i915_private *dev_priv,
05394f39 943 struct drm_i915_gem_object *src)
9df30794
CW		 944{
945 struct drm_i915_error_object *dst;
9da3da66 946 int i, count;
e56660dd 947 u32 reloc_offset;
9df30794 948
05394f39 949 if (src == NULL || src->pages == NULL)
9df30794
CW		 950 return NULL;
951
9da3da66 952 count = src->base.size / PAGE_SIZE;
9df30794 953
9da3da66 954 dst = kmalloc(sizeof(*dst) + count * sizeof(u32 *), GFP_ATOMIC);
9df30794
CW		 955 if (dst == NULL)
956 return NULL;
957
05394f39 958 reloc_offset = src->gtt_offset;
9da3da66 959 for (i = 0; i < count; i++) {
788885ae 960 unsigned long flags;
e56660dd 961 void *d;
788885ae 962
e56660dd 963 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 964 if (d == NULL)
965 goto unwind;
e56660dd 966
788885ae 967 local_irq_save(flags);
5d4545ae 968 if (reloc_offset < dev_priv->gtt.mappable_end &&
74898d7e 969 src->has_global_gtt_mapping) {
172975aa
CW		 970 void __iomem *s;
971
972 /* Simply ignore tiling or any overlapping fence.
973 * It's part of the error state, and this hopefully
974 * captures what the GPU read.
975 */
976
5d4545ae 977 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
172975aa
CW		 978 reloc_offset);
979 memcpy_fromio(d, s, PAGE_SIZE);
980 io_mapping_unmap_atomic(s);
960e3564
CW		 981 } else if (src->stolen) {
982 unsigned long offset;
983
984 offset = dev_priv->mm.stolen_base;
985 offset += src->stolen->start;
986 offset += i << PAGE_SHIFT;
987
1a240d4d 988 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
172975aa 989 } else {
9da3da66 990 struct page *page;
172975aa
CW		 991 void *s;
992
9da3da66 993 page = i915_gem_object_get_page(src, i);
172975aa 994
9da3da66
CW		 995 drm_clflush_pages(&page, 1);
996
997 s = kmap_atomic(page);
172975aa
CW		 998 memcpy(d, s, PAGE_SIZE);
999 kunmap_atomic(s);
1000
9da3da66 1001 drm_clflush_pages(&page, 1);
172975aa 1002 }
788885ae 1003 local_irq_restore(flags);
e56660dd 1004
9da3da66 1005 dst->pages[i] = d;
e56660dd
CW		 1006
1007 reloc_offset += PAGE_SIZE;
9df30794 1008 }
9da3da66 1009 dst->page_count = count;
05394f39 1010 dst->gtt_offset = src->gtt_offset;
9df30794
CW		 1011
1012 return dst;
1013
1014unwind:
9da3da66
CW		 1015 while (i--)
1016 kfree(dst->pages[i]);
9df30794
CW		 1017 kfree(dst);
1018 return NULL;
1019}
1020
1021static void
1022i915_error_object_free(struct drm_i915_error_object *obj)
1023{
1024 int page;
1025
1026 if (obj == NULL)
1027 return;
1028
1029 for (page = 0; page < obj->page_count; page++)
1030 kfree(obj->pages[page]);
1031
1032 kfree(obj);
1033}
1034
742cbee8
DV		 1035void
1036i915_error_state_free(struct kref *error_ref)
9df30794 1037{
742cbee8
DV		 1038 struct drm_i915_error_state *error = container_of(error_ref,
1039 typeof(*error), ref);
e2f973d5
CW		 1040 int i;
1041
52d39a21
CW		 1042 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
1043 i915_error_object_free(error->ring[i].batchbuffer);
1044 i915_error_object_free(error->ring[i].ringbuffer);
1045 kfree(error->ring[i].requests);
1046 }
e2f973d5 1047
9df30794 1048 kfree(error->active_bo);
6ef3d427 1049 kfree(error->overlay);
9df30794
CW		 1050 kfree(error);
1051}
1b50247a
CW		 1052static void capture_bo(struct drm_i915_error_buffer *err,
1053 struct drm_i915_gem_object *obj)
1054{
1055 err->size = obj->base.size;
1056 err->name = obj->base.name;
0201f1ec
CW		 1057 err->rseqno = obj->last_read_seqno;
1058 err->wseqno = obj->last_write_seqno;
1b50247a
CW		 1059 err->gtt_offset = obj->gtt_offset;
1060 err->read_domains = obj->base.read_domains;
1061 err->write_domain = obj->base.write_domain;
1062 err->fence_reg = obj->fence_reg;
1063 err->pinned = 0;
1064 if (obj->pin_count > 0)
1065 err->pinned = 1;
1066 if (obj->user_pin_count > 0)
1067 err->pinned = -1;
1068 err->tiling = obj->tiling_mode;
1069 err->dirty = obj->dirty;
1070 err->purgeable = obj->madv != I915_MADV_WILLNEED;
1071 err->ring = obj->ring ? obj->ring->id : -1;
1072 err->cache_level = obj->cache_level;
1073}
9df30794 1074
1b50247a
CW		 1075static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1076 int count, struct list_head *head)
c724e8a9
CW		 1077{
1078 struct drm_i915_gem_object *obj;
1079 int i = 0;
1080
1081 list_for_each_entry(obj, head, mm_list) {
1b50247a 1082 capture_bo(err++, obj);
c724e8a9
CW		 1083 if (++i == count)
1084 break;
1b50247a
CW		 1085 }
1086
1087 return i;
1088}
1089
1090static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1091 int count, struct list_head *head)
1092{
1093 struct drm_i915_gem_object *obj;
1094 int i = 0;
1095
1096 list_for_each_entry(obj, head, gtt_list) {
1097 if (obj->pin_count == 0)
1098 continue;
c724e8a9 1099
1b50247a
CW		 1100 capture_bo(err++, obj);
1101 if (++i == count)
1102 break;
c724e8a9
CW		 1103 }
1104
1105 return i;
1106}
1107
748ebc60
CW		 1108static void i915_gem_record_fences(struct drm_device *dev,
1109 struct drm_i915_error_state *error)
1110{
1111 struct drm_i915_private *dev_priv = dev->dev_private;
1112 int i;
1113
1114 /* Fences */
1115 switch (INTEL_INFO(dev)->gen) {
775d17b6 1116 case 7:
748ebc60
CW		 1117 case 6:
1118 for (i = 0; i < 16; i++)
1119 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1120 break;
1121 case 5:
1122 case 4:
1123 for (i = 0; i < 16; i++)
1124 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1125 break;
1126 case 3:
1127 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1128 for (i = 0; i < 8; i++)
1129 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1130 case 2:
1131 for (i = 0; i < 8; i++)
1132 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1133 break;
1134
7dbf9d6e
BW		 1135 default:
1136 BUG();
748ebc60
CW		 1137 }
1138}
1139
bcfb2e28
CW		 1140static struct drm_i915_error_object *
1141i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1142 struct intel_ring_buffer *ring)
1143{
1144 struct drm_i915_gem_object *obj;
1145 u32 seqno;
1146
1147 if (!ring->get_seqno)
1148 return NULL;
1149
b45305fc
DV		 1150 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
1151 u32 acthd = I915_READ(ACTHD);
1152
1153 if (WARN_ON(ring->id != RCS))
1154 return NULL;
1155
1156 obj = ring->private;
1157 if (acthd >= obj->gtt_offset &&
1158 acthd < obj->gtt_offset + obj->base.size)
1159 return i915_error_object_create(dev_priv, obj);
1160 }
1161
b2eadbc8 1162 seqno = ring->get_seqno(ring, false);
bcfb2e28
CW		 1163 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1164 if (obj->ring != ring)
1165 continue;
1166
0201f1ec 1167 if (i915_seqno_passed(seqno, obj->last_read_seqno))
bcfb2e28
CW		 1168 continue;
1169
1170 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1171 continue;
1172
1173 /* We need to copy these to an anonymous buffer as the simplest
1174 * method to avoid being overwritten by userspace.
1175 */
1176 return i915_error_object_create(dev_priv, obj);
1177 }
1178
1179 return NULL;
1180}
1181
d27b1e0e
DV		 1182static void i915_record_ring_state(struct drm_device *dev,
1183 struct drm_i915_error_state *error,
1184 struct intel_ring_buffer *ring)
1185{
1186 struct drm_i915_private *dev_priv = dev->dev_private;
1187
33f3f518 1188 if (INTEL_INFO(dev)->gen >= 6) {
12f55818 1189 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
33f3f518 1190 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
7e3b8737
DV		 1191 error->semaphore_mboxes[ring->id][0]
1192 = I915_READ(RING_SYNC_0(ring->mmio_base));
1193 error->semaphore_mboxes[ring->id][1]
1194 = I915_READ(RING_SYNC_1(ring->mmio_base));
df2b23d9
CW		 1195 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
1196 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
33f3f518 1197 }
c1cd90ed 1198
d27b1e0e 1199 if (INTEL_INFO(dev)->gen >= 4) {
9d2f41fa 1200 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
d27b1e0e
DV		 1201 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1202 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1203 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
c1cd90ed 1204 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
050ee91f 1205 if (ring->id == RCS)
d27b1e0e 1206 error->bbaddr = I915_READ64(BB_ADDR);
d27b1e0e 1207 } else {
9d2f41fa 1208 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
d27b1e0e
DV		 1209 error->ipeir[ring->id] = I915_READ(IPEIR);
1210 error->ipehr[ring->id] = I915_READ(IPEHR);
1211 error->instdone[ring->id] = I915_READ(INSTDONE);
d27b1e0e
DV		 1212 }
1213
9574b3fe 1214 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
c1cd90ed 1215 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
b2eadbc8 1216 error->seqno[ring->id] = ring->get_seqno(ring, false);
d27b1e0e 1217 error->acthd[ring->id] = intel_ring_get_active_head(ring);
c1cd90ed
DV		 1218 error->head[ring->id] = I915_READ_HEAD(ring);
1219 error->tail[ring->id] = I915_READ_TAIL(ring);
7e3b8737
DV		 1220
1221 error->cpu_ring_head[ring->id] = ring->head;
1222 error->cpu_ring_tail[ring->id] = ring->tail;
d27b1e0e
DV		 1223}
1224
52d39a21
CW		 1225static void i915_gem_record_rings(struct drm_device *dev,
1226 struct drm_i915_error_state *error)
1227{
1228 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 1229 struct intel_ring_buffer *ring;
52d39a21
CW		 1230 struct drm_i915_gem_request *request;
1231 int i, count;
1232
b4519513 1233 for_each_ring(ring, dev_priv, i) {
52d39a21
CW		 1234 i915_record_ring_state(dev, error, ring);
1235
1236 error->ring[i].batchbuffer =
1237 i915_error_first_batchbuffer(dev_priv, ring);
1238
1239 error->ring[i].ringbuffer =
1240 i915_error_object_create(dev_priv, ring->obj);
1241
1242 count = 0;
1243 list_for_each_entry(request, &ring->request_list, list)
1244 count++;
1245
1246 error->ring[i].num_requests = count;
1247 error->ring[i].requests =
1248 kmalloc(count*sizeof(struct drm_i915_error_request),
1249 GFP_ATOMIC);
1250 if (error->ring[i].requests == NULL) {
1251 error->ring[i].num_requests = 0;
1252 continue;
1253 }
1254
1255 count = 0;
1256 list_for_each_entry(request, &ring->request_list, list) {
1257 struct drm_i915_error_request *erq;
1258
1259 erq = &error->ring[i].requests[count++];
1260 erq->seqno = request->seqno;
1261 erq->jiffies = request->emitted_jiffies;
ee4f42b1 1262 erq->tail = request->tail;
52d39a21
CW		 1263 }
1264 }
1265}
1266
8a905236
JB		 1267/**
1268 * i915_capture_error_state - capture an error record for later analysis
1269 * @dev: drm device
1270 *
1271 * Should be called when an error is detected (either a hang or an error
1272 * interrupt) to capture error state from the time of the error. Fills
1273 * out a structure which becomes available in debugfs for user level tools
1274 * to pick up.
1275 */
63eeaf38
JB		 1276static void i915_capture_error_state(struct drm_device *dev)
1277{
1278 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1279 struct drm_i915_gem_object *obj;
63eeaf38
JB		 1280 struct drm_i915_error_state *error;
1281 unsigned long flags;
9db4a9c7 1282 int i, pipe;
63eeaf38 1283
99584db3
DV		 1284 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1285 error = dev_priv->gpu_error.first_error;
1286 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 1287 if (error)
1288 return;
63eeaf38 1289
9db4a9c7 1290 /* Account for pipe specific data like PIPE*STAT */
33f3f518 1291 error = kzalloc(sizeof(*error), GFP_ATOMIC);
63eeaf38 1292 if (!error) {
9df30794
CW		 1293 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1294 return;
63eeaf38
JB		 1295 }
1296
b6f7833b
CW		 1297 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1298 dev->primary->index);
2fa772f3 1299
742cbee8 1300 kref_init(&error->ref);
63eeaf38
JB		 1301 error->eir = I915_READ(EIR);
1302 error->pgtbl_er = I915_READ(PGTBL_ER);
b9a3906b 1303 error->ccid = I915_READ(CCID);
be998e2e
BW		 1304
1305 if (HAS_PCH_SPLIT(dev))
1306 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1307 else if (IS_VALLEYVIEW(dev))
1308 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1309 else if (IS_GEN2(dev))
1310 error->ier = I915_READ16(IER);
1311 else
1312 error->ier = I915_READ(IER);
1313
9db4a9c7
JB		 1314 for_each_pipe(pipe)
1315 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
d27b1e0e 1316
33f3f518 1317 if (INTEL_INFO(dev)->gen >= 6) {
f406839f 1318 error->error = I915_READ(ERROR_GEN6);
33f3f518
DV		 1319 error->done_reg = I915_READ(DONE_REG);
1320 }
d27b1e0e 1321
71e172e8
BW		 1322 if (INTEL_INFO(dev)->gen == 7)
1323 error->err_int = I915_READ(GEN7_ERR_INT);
1324
050ee91f
BW		 1325 i915_get_extra_instdone(dev, error->extra_instdone);
1326
748ebc60 1327 i915_gem_record_fences(dev, error);
52d39a21 1328 i915_gem_record_rings(dev, error);
9df30794 1329
c724e8a9 1330 /* Record buffers on the active and pinned lists. */
9df30794 1331 error->active_bo = NULL;
c724e8a9 1332 error->pinned_bo = NULL;
9df30794 1333
bcfb2e28
CW		 1334 i = 0;
1335 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1336 i++;
1337 error->active_bo_count = i;
6c085a72 1338 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
1b50247a
CW		 1339 if (obj->pin_count)
1340 i++;
bcfb2e28 1341 error->pinned_bo_count = i - error->active_bo_count;
c724e8a9 1342
8e934dbf
CW		 1343 error->active_bo = NULL;
1344 error->pinned_bo = NULL;
bcfb2e28
CW		 1345 if (i) {
1346 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
9df30794 1347 GFP_ATOMIC);
c724e8a9
CW		 1348 if (error->active_bo)
1349 error->pinned_bo =
1350 error->active_bo + error->active_bo_count;
9df30794
CW		 1351 }
1352
c724e8a9
CW		 1353 if (error->active_bo)
1354 error->active_bo_count =
1b50247a
CW		 1355 capture_active_bo(error->active_bo,
1356 error->active_bo_count,
1357 &dev_priv->mm.active_list);
c724e8a9
CW		 1358
1359 if (error->pinned_bo)
1360 error->pinned_bo_count =
1b50247a
CW		 1361 capture_pinned_bo(error->pinned_bo,
1362 error->pinned_bo_count,
6c085a72 1363 &dev_priv->mm.bound_list);
c724e8a9 1364
9df30794
CW		 1365 do_gettimeofday(&error->time);
1366
6ef3d427 1367 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 1368 error->display = intel_display_capture_error_state(dev);
6ef3d427 1369
99584db3
DV		 1370 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1371 if (dev_priv->gpu_error.first_error == NULL) {
1372 dev_priv->gpu_error.first_error = error;
9df30794
CW		 1373 error = NULL;
1374 }
99584db3 1375 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 1376
1377 if (error)
742cbee8 1378 i915_error_state_free(&error->ref);
9df30794
CW		 1379}
1380
1381void i915_destroy_error_state(struct drm_device *dev)
1382{
1383 struct drm_i915_private *dev_priv = dev->dev_private;
1384 struct drm_i915_error_state *error;
6dc0e816 1385 unsigned long flags;
9df30794 1386
99584db3
DV		 1387 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1388 error = dev_priv->gpu_error.first_error;
1389 dev_priv->gpu_error.first_error = NULL;
1390 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 1391
1392 if (error)
742cbee8 1393 kref_put(&error->ref, i915_error_state_free);
63eeaf38 1394}
3bd3c932
CW		 1395#else
1396#define i915_capture_error_state(x)
1397#endif
63eeaf38 1398
35aed2e6 1399static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1400{
1401 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 1402 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 1403 u32 eir = I915_READ(EIR);
050ee91f 1404 int pipe, i;
8a905236 1405
35aed2e6
CW		 1406 if (!eir)
1407 return;
8a905236 1408
a70491cc 1409 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 1410
bd9854f9
BW		 1411 i915_get_extra_instdone(dev, instdone);
1412
8a905236
JB		 1413 if (IS_G4X(dev)) {
1414 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1415 u32 ipeir = I915_READ(IPEIR_I965);
1416
a70491cc
JP		 1417 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1418 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 1419 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1420 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 1421 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1422 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1423 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1424 POSTING_READ(IPEIR_I965);
8a905236
JB		 1425 }
1426 if (eir & GM45_ERROR_PAGE_TABLE) {
1427 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1428 pr_err("page table error\n");
1429 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1430 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1431 POSTING_READ(PGTBL_ER);
8a905236
JB		 1432 }
1433 }
1434
a6c45cf0 1435 if (!IS_GEN2(dev)) {
8a905236
JB		 1436 if (eir & I915_ERROR_PAGE_TABLE) {
1437 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1438 pr_err("page table error\n");
1439 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1440 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1441 POSTING_READ(PGTBL_ER);
8a905236
JB		 1442 }
1443 }
1444
1445 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 1446 pr_err("memory refresh error:\n");
9db4a9c7 1447 for_each_pipe(pipe)
a70491cc 1448 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 1449 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 1450 /* pipestat has already been acked */
1451 }
1452 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 1453 pr_err("instruction error\n");
1454 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 1455 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1456 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 1457 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 1458 u32 ipeir = I915_READ(IPEIR);
1459
a70491cc
JP		 1460 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1461 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 1462 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 1463 I915_WRITE(IPEIR, ipeir);
3143a2bf 1464 POSTING_READ(IPEIR);
8a905236
JB		 1465 } else {
1466 u32 ipeir = I915_READ(IPEIR_I965);
1467
a70491cc
JP		 1468 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1469 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 1470 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1471 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1472 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1473 POSTING_READ(IPEIR_I965);
8a905236
JB		 1474 }
1475 }
1476
1477 I915_WRITE(EIR, eir);
3143a2bf 1478 POSTING_READ(EIR);
8a905236
JB		 1479 eir = I915_READ(EIR);
1480 if (eir) {
1481 /*
1482 * some errors might have become stuck,
1483 * mask them.
1484 */
1485 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1486 I915_WRITE(EMR, I915_READ(EMR) | eir);
1487 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1488 }
35aed2e6
CW		 1489}
1490
1491/**
1492 * i915_handle_error - handle an error interrupt
1493 * @dev: drm device
1494 *
1495 * Do some basic checking of regsiter state at error interrupt time and
1496 * dump it to the syslog. Also call i915_capture_error_state() to make
1497 * sure we get a record and make it available in debugfs. Fire a uevent
1498 * so userspace knows something bad happened (should trigger collection
1499 * of a ring dump etc.).
1500 */
527f9e90 1501void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 1502{
1503 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513
CW		 1504 struct intel_ring_buffer *ring;
1505 int i;
35aed2e6
CW		 1506
1507 i915_capture_error_state(dev);
1508 i915_report_and_clear_eir(dev);
8a905236 1509
ba1234d1 1510 if (wedged) {
f69061be
DV		 1511 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
1512 &dev_priv->gpu_error.reset_counter);
ba1234d1 1513
11ed50ec 1514 /*
1f83fee0
DV		 1515 * Wakeup waiting processes so that the reset work item
1516 * doesn't deadlock trying to grab various locks.
11ed50ec 1517 */
b4519513
CW		 1518 for_each_ring(ring, dev_priv, i)
1519 wake_up_all(&ring->irq_queue);
11ed50ec
BG		 1520 }
1521
99584db3 1522 queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
8a905236
JB		 1523}
1524
4e5359cd
SF		 1525static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1526{
1527 drm_i915_private_t *dev_priv = dev->dev_private;
1528 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1529 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 1530 struct drm_i915_gem_object *obj;
4e5359cd
SF		 1531 struct intel_unpin_work *work;
1532 unsigned long flags;
1533 bool stall_detected;
1534
1535 /* Ignore early vblank irqs */
1536 if (intel_crtc == NULL)
1537 return;
1538
1539 spin_lock_irqsave(&dev->event_lock, flags);
1540 work = intel_crtc->unpin_work;
1541
e7d841ca
CW		 1542 if (work == NULL ||
1543 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
1544 !work->enable_stall_check) {
4e5359cd
SF		 1545 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1546 spin_unlock_irqrestore(&dev->event_lock, flags);
1547 return;
1548 }
1549
1550 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 1551 obj = work->pending_flip_obj;
a6c45cf0 1552 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 1553 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545
AR		 1554 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1555 obj->gtt_offset;
4e5359cd 1556 } else {
9db4a9c7 1557 int dspaddr = DSPADDR(intel_crtc->plane);
05394f39 1558 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
01f2c773 1559 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 1560 crtc->x * crtc->fb->bits_per_pixel/8);
1561 }
1562
1563 spin_unlock_irqrestore(&dev->event_lock, flags);
1564
1565 if (stall_detected) {
1566 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1567 intel_prepare_page_flip(dev, intel_crtc->plane);
1568 }
1569}
1570
42f52ef8
KP		 1571/* Called from drm generic code, passed 'crtc' which
1572 * we use as a pipe index
1573 */
f71d4af4 1574static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1575{
1576 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1577 unsigned long irqflags;
71e0ffa5 1578
5eddb70b 1579 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 1580 return -EINVAL;
0a3e67a4 1581
1ec14ad3 1582 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 1583 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 1584 i915_enable_pipestat(dev_priv, pipe,
1585 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 1586 else
7c463586
KP		 1587 i915_enable_pipestat(dev_priv, pipe,
1588 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 1589
1590 /* maintain vblank delivery even in deep C-states */
1591 if (dev_priv->info->gen == 3)
6b26c86d 1592 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 1593 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 1594
0a3e67a4
JB		 1595 return 0;
1596}
1597
f71d4af4 1598static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1599{
1600 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1601 unsigned long irqflags;
1602
1603 if (!i915_pipe_enabled(dev, pipe))
1604 return -EINVAL;
1605
1606 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1607 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1608 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
f796cf8f
JB		 1609 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1610
1611 return 0;
1612}
1613
f71d4af4 1614static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1615{
1616 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1617 unsigned long irqflags;
1618
1619 if (!i915_pipe_enabled(dev, pipe))
1620 return -EINVAL;
1621
1622 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1623 ironlake_enable_display_irq(dev_priv,
1624 DE_PIPEA_VBLANK_IVB << (5 * pipe));
b1f14ad0
JB		 1625 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1626
1627 return 0;
1628}
1629
7e231dbe
JB		 1630static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1631{
1632 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1633 unsigned long irqflags;
31acc7f5 1634 u32 imr;
7e231dbe
JB		 1635
1636 if (!i915_pipe_enabled(dev, pipe))
1637 return -EINVAL;
1638
1639 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7e231dbe 1640 imr = I915_READ(VLV_IMR);
31acc7f5 1641 if (pipe == 0)
7e231dbe 1642 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1643 else
7e231dbe 1644 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1645 I915_WRITE(VLV_IMR, imr);
31acc7f5
JB		 1646 i915_enable_pipestat(dev_priv, pipe,
1647 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe
JB		 1648 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1649
1650 return 0;
1651}
1652
42f52ef8
KP		 1653/* Called from drm generic code, passed 'crtc' which
1654 * we use as a pipe index
1655 */
f71d4af4 1656static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1657{
1658 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1659 unsigned long irqflags;
0a3e67a4 1660
1ec14ad3 1661 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 1662 if (dev_priv->info->gen == 3)
6b26c86d 1663 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 1664
f796cf8f
JB		 1665 i915_disable_pipestat(dev_priv, pipe,
1666 PIPE_VBLANK_INTERRUPT_ENABLE |
1667 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1668 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1669}
1670
f71d4af4 1671static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1672{
1673 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1674 unsigned long irqflags;
1675
1676 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1677 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1678 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1ec14ad3 1679 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 1680}
1681
f71d4af4 1682static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1683{
1684 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1685 unsigned long irqflags;
1686
1687 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1688 ironlake_disable_display_irq(dev_priv,
1689 DE_PIPEA_VBLANK_IVB << (pipe * 5));
b1f14ad0
JB		 1690 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1691}
1692
7e231dbe
JB		 1693static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1694{
1695 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1696 unsigned long irqflags;
31acc7f5 1697 u32 imr;
7e231dbe
JB		 1698
1699 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5
JB		 1700 i915_disable_pipestat(dev_priv, pipe,
1701 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe 1702 imr = I915_READ(VLV_IMR);
31acc7f5 1703 if (pipe == 0)
7e231dbe 1704 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1705 else
7e231dbe 1706 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1707 I915_WRITE(VLV_IMR, imr);
7e231dbe
JB		 1708 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1709}
1710
893eead0
CW		 1711static u32
1712ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 1713{
893eead0
CW		 1714 return list_entry(ring->request_list.prev,
1715 struct drm_i915_gem_request, list)->seqno;
1716}
1717
1718static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1719{
1720 if (list_empty(&ring->request_list) ||
b2eadbc8
CW		 1721 i915_seqno_passed(ring->get_seqno(ring, false),
1722 ring_last_seqno(ring))) {
893eead0 1723 /* Issue a wake-up to catch stuck h/w. */
9574b3fe
BW		 1724 if (waitqueue_active(&ring->irq_queue)) {
1725 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1726 ring->name);
893eead0
CW		 1727 wake_up_all(&ring->irq_queue);
1728 *err = true;
1729 }
1730 return true;
1731 }
1732 return false;
f65d9421
BG		 1733}
1734
1ec14ad3
CW		 1735static bool kick_ring(struct intel_ring_buffer *ring)
1736{
1737 struct drm_device *dev = ring->dev;
1738 struct drm_i915_private *dev_priv = dev->dev_private;
1739 u32 tmp = I915_READ_CTL(ring);
1740 if (tmp & RING_WAIT) {
1741 DRM_ERROR("Kicking stuck wait on %s\n",
1742 ring->name);
1743 I915_WRITE_CTL(ring, tmp);
1744 return true;
1745 }
1ec14ad3
CW		 1746 return false;
1747}
1748
d1e61e7f
CW		 1749static bool i915_hangcheck_hung(struct drm_device *dev)
1750{
1751 drm_i915_private_t *dev_priv = dev->dev_private;
1752
99584db3 1753 if (dev_priv->gpu_error.hangcheck_count++ > 1) {
b4519513
CW		 1754 bool hung = true;
1755
d1e61e7f
CW		 1756 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1757 i915_handle_error(dev, true);
1758
1759 if (!IS_GEN2(dev)) {
b4519513
CW		 1760 struct intel_ring_buffer *ring;
1761 int i;
1762
d1e61e7f
CW		 1763 /* Is the chip hanging on a WAIT_FOR_EVENT?
1764 * If so we can simply poke the RB_WAIT bit
1765 * and break the hang. This should work on
1766 * all but the second generation chipsets.
1767 */
b4519513
CW		 1768 for_each_ring(ring, dev_priv, i)
1769 hung &= !kick_ring(ring);
d1e61e7f
CW		 1770 }
1771
b4519513 1772 return hung;
d1e61e7f
CW		 1773 }
1774
1775 return false;
1776}
1777
f65d9421
BG		 1778/**
1779 * This is called when the chip hasn't reported back with completed
1780 * batchbuffers in a long time. The first time this is called we simply record
1781 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1782 * again, we assume the chip is wedged and try to fix it.
1783 */
1784void i915_hangcheck_elapsed(unsigned long data)
1785{
1786 struct drm_device *dev = (struct drm_device *)data;
1787 drm_i915_private_t *dev_priv = dev->dev_private;
bd9854f9 1788 uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
b4519513
CW		 1789 struct intel_ring_buffer *ring;
1790 bool err = false, idle;
1791 int i;
893eead0 1792
3e0dc6b0
BW		 1793 if (!i915_enable_hangcheck)
1794 return;
1795
b4519513
CW		 1796 memset(acthd, 0, sizeof(acthd));
1797 idle = true;
1798 for_each_ring(ring, dev_priv, i) {
1799 idle &= i915_hangcheck_ring_idle(ring, &err);
1800 acthd[i] = intel_ring_get_active_head(ring);
1801 }
1802
893eead0 1803 /* If all work is done then ACTHD clearly hasn't advanced. */
b4519513 1804 if (idle) {
d1e61e7f
CW		 1805 if (err) {
1806 if (i915_hangcheck_hung(dev))
1807 return;
1808
893eead0 1809 goto repeat;
d1e61e7f
CW		 1810 }
1811
99584db3 1812 dev_priv->gpu_error.hangcheck_count = 0;
893eead0
CW		 1813 return;
1814 }
b9201c14 1815
bd9854f9 1816 i915_get_extra_instdone(dev, instdone);
99584db3
DV		 1817 if (memcmp(dev_priv->gpu_error.last_acthd, acthd,
1818 sizeof(acthd)) == 0 &&
1819 memcmp(dev_priv->gpu_error.prev_instdone, instdone,
1820 sizeof(instdone)) == 0) {
d1e61e7f 1821 if (i915_hangcheck_hung(dev))
cbb465e7 1822 return;
cbb465e7 1823 } else {
99584db3 1824 dev_priv->gpu_error.hangcheck_count = 0;
cbb465e7 1825
99584db3
DV		 1826 memcpy(dev_priv->gpu_error.last_acthd, acthd,
1827 sizeof(acthd));
1828 memcpy(dev_priv->gpu_error.prev_instdone, instdone,
1829 sizeof(instdone));
cbb465e7 1830 }
f65d9421 1831
893eead0 1832repeat:
f65d9421 1833 /* Reset timer case chip hangs without another request being added */
99584db3 1834 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
cecc21fe 1835 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
f65d9421
BG		 1836}
1837
1da177e4
LT		 1838/* drm_dma.h hooks
1839*/
f71d4af4 1840static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 1841{
1842 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1843
4697995b
JB		 1844 atomic_set(&dev_priv->irq_received, 0);
1845
036a4a7d 1846 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 1847
036a4a7d
ZW		 1848 /* XXX hotplug from PCH */
1849
1850 I915_WRITE(DEIMR, 0xffffffff);
1851 I915_WRITE(DEIER, 0x0);
3143a2bf 1852 POSTING_READ(DEIER);
036a4a7d
ZW		 1853
1854 /* and GT */
1855 I915_WRITE(GTIMR, 0xffffffff);
1856 I915_WRITE(GTIER, 0x0);
3143a2bf 1857 POSTING_READ(GTIER);
c650156a
ZW		 1858
1859 /* south display irq */
1860 I915_WRITE(SDEIMR, 0xffffffff);
1861 I915_WRITE(SDEIER, 0x0);
3143a2bf 1862 POSTING_READ(SDEIER);
036a4a7d
ZW		 1863}
1864
7e231dbe
JB		 1865static void valleyview_irq_preinstall(struct drm_device *dev)
1866{
1867 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1868 int pipe;
1869
1870 atomic_set(&dev_priv->irq_received, 0);
1871
7e231dbe
JB		 1872 /* VLV magic */
1873 I915_WRITE(VLV_IMR, 0);
1874 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1875 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1876 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1877
7e231dbe
JB		 1878 /* and GT */
1879 I915_WRITE(GTIIR, I915_READ(GTIIR));
1880 I915_WRITE(GTIIR, I915_READ(GTIIR));
1881 I915_WRITE(GTIMR, 0xffffffff);
1882 I915_WRITE(GTIER, 0x0);
1883 POSTING_READ(GTIER);
1884
1885 I915_WRITE(DPINVGTT, 0xff);
1886
1887 I915_WRITE(PORT_HOTPLUG_EN, 0);
1888 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1889 for_each_pipe(pipe)
1890 I915_WRITE(PIPESTAT(pipe), 0xffff);
1891 I915_WRITE(VLV_IIR, 0xffffffff);
1892 I915_WRITE(VLV_IMR, 0xffffffff);
1893 I915_WRITE(VLV_IER, 0x0);
1894 POSTING_READ(VLV_IER);
1895}
1896
7fe0b973
KP		 1897/*
1898 * Enable digital hotplug on the PCH, and configure the DP short pulse
1899 * duration to 2ms (which is the minimum in the Display Port spec)
1900 *
1901 * This register is the same on all known PCH chips.
1902 */
1903
1904static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1905{
1906 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1907 u32 hotplug;
1908
1909 hotplug = I915_READ(PCH_PORT_HOTPLUG);
1910 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1911 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1912 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1913 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1914 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1915}
1916
f71d4af4 1917static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d
ZW		 1918{
1919 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1920 /* enable kind of interrupts always enabled */
013d5aa2 1921 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
ce99c256
DV		 1922 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
1923 DE_AUX_CHANNEL_A;
1ec14ad3 1924 u32 render_irqs;
2d7b8366 1925 u32 hotplug_mask;
af5163ac 1926 u32 pch_irq_mask;
036a4a7d 1927
1ec14ad3 1928 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 1929
1930 /* should always can generate irq */
1931 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3
CW		 1932 I915_WRITE(DEIMR, dev_priv->irq_mask);
1933 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
3143a2bf 1934 POSTING_READ(DEIER);
036a4a7d 1935
1ec14ad3 1936 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 1937
1938 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 1939 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 1940
1ec14ad3
CW		 1941 if (IS_GEN6(dev))
1942 render_irqs =
1943 GT_USER_INTERRUPT |
e2a1e2f0
BW		 1944 GEN6_BSD_USER_INTERRUPT |
1945 GEN6_BLITTER_USER_INTERRUPT;
1ec14ad3
CW		 1946 else
1947 render_irqs =
88f23b8f 1948 GT_USER_INTERRUPT |
c6df541c 1949 GT_PIPE_NOTIFY |
1ec14ad3
CW		 1950 GT_BSD_USER_INTERRUPT;
1951 I915_WRITE(GTIER, render_irqs);
3143a2bf 1952 POSTING_READ(GTIER);
036a4a7d 1953
2d7b8366 1954 if (HAS_PCH_CPT(dev)) {
9035a97a
CW		 1955 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1956 SDE_PORTB_HOTPLUG_CPT |
1957 SDE_PORTC_HOTPLUG_CPT |
515ac2bb 1958 SDE_PORTD_HOTPLUG_CPT |
ce99c256
DV		 1959 SDE_GMBUS_CPT |
1960 SDE_AUX_MASK_CPT);
2d7b8366 1961 } else {
9035a97a
CW		 1962 hotplug_mask = (SDE_CRT_HOTPLUG |
1963 SDE_PORTB_HOTPLUG |
1964 SDE_PORTC_HOTPLUG |
1965 SDE_PORTD_HOTPLUG |
515ac2bb 1966 SDE_GMBUS |
9035a97a 1967 SDE_AUX_MASK);
2d7b8366
YL		 1968 }
1969
af5163ac 1970 pch_irq_mask = ~hotplug_mask;
c650156a
ZW		 1971
1972 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
af5163ac 1973 I915_WRITE(SDEIMR, pch_irq_mask);
1ec14ad3 1974 I915_WRITE(SDEIER, hotplug_mask);
3143a2bf 1975 POSTING_READ(SDEIER);
c650156a 1976
7fe0b973
KP		 1977 ironlake_enable_pch_hotplug(dev);
1978
f97108d1
JB		 1979 if (IS_IRONLAKE_M(dev)) {
1980 /* Clear & enable PCU event interrupts */
1981 I915_WRITE(DEIIR, DE_PCU_EVENT);
1982 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1983 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1984 }
1985
036a4a7d
ZW		 1986 return 0;
1987}
1988
f71d4af4 1989static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 1990{
1991 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1992 /* enable kind of interrupts always enabled */
b615b57a
CW		 1993 u32 display_mask =
1994 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
1995 DE_PLANEC_FLIP_DONE_IVB |
1996 DE_PLANEB_FLIP_DONE_IVB |
ce99c256
DV		 1997 DE_PLANEA_FLIP_DONE_IVB |
1998 DE_AUX_CHANNEL_A_IVB;
b1f14ad0
JB		 1999 u32 render_irqs;
2000 u32 hotplug_mask;
af5163ac 2001 u32 pch_irq_mask;
b1f14ad0 2002
b1f14ad0
JB		 2003 dev_priv->irq_mask = ~display_mask;
2004
2005 /* should always can generate irq */
2006 I915_WRITE(DEIIR, I915_READ(DEIIR));
2007 I915_WRITE(DEIMR, dev_priv->irq_mask);
b615b57a
CW		 2008 I915_WRITE(DEIER,
2009 display_mask |
2010 DE_PIPEC_VBLANK_IVB |
2011 DE_PIPEB_VBLANK_IVB |
2012 DE_PIPEA_VBLANK_IVB);
b1f14ad0
JB		 2013 POSTING_READ(DEIER);
2014
15b9f80e 2015 dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 2016
2017 I915_WRITE(GTIIR, I915_READ(GTIIR));
2018 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2019
e2a1e2f0 2020 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
15b9f80e 2021 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 2022 I915_WRITE(GTIER, render_irqs);
2023 POSTING_READ(GTIER);
2024
2025 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
2026 SDE_PORTB_HOTPLUG_CPT |
2027 SDE_PORTC_HOTPLUG_CPT |
515ac2bb 2028 SDE_PORTD_HOTPLUG_CPT |
ce99c256
DV		 2029 SDE_GMBUS_CPT |
2030 SDE_AUX_MASK_CPT);
af5163ac 2031 pch_irq_mask = ~hotplug_mask;
b1f14ad0
JB		 2032
2033 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
af5163ac 2034 I915_WRITE(SDEIMR, pch_irq_mask);
b1f14ad0
JB		 2035 I915_WRITE(SDEIER, hotplug_mask);
2036 POSTING_READ(SDEIER);
2037
7fe0b973
KP		 2038 ironlake_enable_pch_hotplug(dev);
2039
b1f14ad0
JB		 2040 return 0;
2041}
2042
7e231dbe
JB		 2043static int valleyview_irq_postinstall(struct drm_device *dev)
2044{
2045 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7e231dbe 2046 u32 enable_mask;
31acc7f5 2047 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
3bcedbe5 2048 u32 render_irqs;
7e231dbe
JB		 2049 u16 msid;
2050
2051 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
31acc7f5
JB		 2052 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2053 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2054 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
7e231dbe
JB		 2055 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2056
31acc7f5
JB		 2057 /*
2058 *Leave vblank interrupts masked initially. enable/disable will
2059 * toggle them based on usage.
2060 */
2061 dev_priv->irq_mask = (~enable_mask) |
2062 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2063 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2064
7e231dbe
JB		 2065 dev_priv->pipestat[0] = 0;
2066 dev_priv->pipestat[1] = 0;
2067
7e231dbe
JB		 2068 /* Hack for broken MSIs on VLV */
2069 pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
2070 pci_read_config_word(dev->pdev, 0x98, &msid);
2071 msid &= 0xff; /* mask out delivery bits */
2072 msid |= (1<<14);
2073 pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
2074
20afbda2
DV		 2075 I915_WRITE(PORT_HOTPLUG_EN, 0);
2076 POSTING_READ(PORT_HOTPLUG_EN);
2077
7e231dbe
JB		 2078 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2079 I915_WRITE(VLV_IER, enable_mask);
2080 I915_WRITE(VLV_IIR, 0xffffffff);
2081 I915_WRITE(PIPESTAT(0), 0xffff);
2082 I915_WRITE(PIPESTAT(1), 0xffff);
2083 POSTING_READ(VLV_IER);
2084
31acc7f5 2085 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
515ac2bb 2086 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
31acc7f5
JB		 2087 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
2088
7e231dbe
JB		 2089 I915_WRITE(VLV_IIR, 0xffffffff);
2090 I915_WRITE(VLV_IIR, 0xffffffff);
2091
7e231dbe 2092 I915_WRITE(GTIIR, I915_READ(GTIIR));
31acc7f5 2093 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
3bcedbe5
JB		 2094
2095 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2096 GEN6_BLITTER_USER_INTERRUPT;
2097 I915_WRITE(GTIER, render_irqs);
7e231dbe
JB		 2098 POSTING_READ(GTIER);
2099
2100 /* ack & enable invalid PTE error interrupts */
2101#if 0 /* FIXME: add support to irq handler for checking these bits */
2102 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2103 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2104#endif
2105
2106 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
20afbda2
DV		 2107
2108 return 0;
2109}
2110
2111static void valleyview_hpd_irq_setup(struct drm_device *dev)
2112{
2113 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2114 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2115
7e231dbe
JB		 2116 /* Note HDMI and DP share bits */
2117 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2118 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2119 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2120 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2121 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2122 hotplug_en |= HDMID_HOTPLUG_INT_EN;
ae33cdcf 2123 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
7e231dbe 2124 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
ae33cdcf 2125 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
7e231dbe
JB		 2126 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2127 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2128 hotplug_en |= CRT_HOTPLUG_INT_EN;
2129 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2130 }
7e231dbe
JB		 2131
2132 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
7e231dbe
JB		 2133}
2134
7e231dbe
JB		 2135static void valleyview_irq_uninstall(struct drm_device *dev)
2136{
2137 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2138 int pipe;
2139
2140 if (!dev_priv)
2141 return;
2142
7e231dbe
JB		 2143 for_each_pipe(pipe)
2144 I915_WRITE(PIPESTAT(pipe), 0xffff);
2145
2146 I915_WRITE(HWSTAM, 0xffffffff);
2147 I915_WRITE(PORT_HOTPLUG_EN, 0);
2148 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2149 for_each_pipe(pipe)
2150 I915_WRITE(PIPESTAT(pipe), 0xffff);
2151 I915_WRITE(VLV_IIR, 0xffffffff);
2152 I915_WRITE(VLV_IMR, 0xffffffff);
2153 I915_WRITE(VLV_IER, 0x0);
2154 POSTING_READ(VLV_IER);
2155}
2156
f71d4af4 2157static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 2158{
2159 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 2160
2161 if (!dev_priv)
2162 return;
2163
036a4a7d
ZW		 2164 I915_WRITE(HWSTAM, 0xffffffff);
2165
2166 I915_WRITE(DEIMR, 0xffffffff);
2167 I915_WRITE(DEIER, 0x0);
2168 I915_WRITE(DEIIR, I915_READ(DEIIR));
2169
2170 I915_WRITE(GTIMR, 0xffffffff);
2171 I915_WRITE(GTIER, 0x0);
2172 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f
KP		 2173
2174 I915_WRITE(SDEIMR, 0xffffffff);
2175 I915_WRITE(SDEIER, 0x0);
2176 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
036a4a7d
ZW		 2177}
2178
a266c7d5 2179static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 2180{
2181 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2182 int pipe;
91e3738e 2183
a266c7d5 2184 atomic_set(&dev_priv->irq_received, 0);
5ca58282 2185
9db4a9c7
JB		 2186 for_each_pipe(pipe)
2187 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 2188 I915_WRITE16(IMR, 0xffff);
2189 I915_WRITE16(IER, 0x0);
2190 POSTING_READ16(IER);
c2798b19
CW		 2191}
2192
2193static int i8xx_irq_postinstall(struct drm_device *dev)
2194{
2195 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2196
c2798b19
CW		 2197 dev_priv->pipestat[0] = 0;
2198 dev_priv->pipestat[1] = 0;
2199
2200 I915_WRITE16(EMR,
2201 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2202
2203 /* Unmask the interrupts that we always want on. */
2204 dev_priv->irq_mask =
2205 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2206 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2207 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2208 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2209 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2210 I915_WRITE16(IMR, dev_priv->irq_mask);
2211
2212 I915_WRITE16(IER,
2213 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2214 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2215 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2216 I915_USER_INTERRUPT);
2217 POSTING_READ16(IER);
2218
2219 return 0;
2220}
2221
ff1f525e 2222static irqreturn_t i8xx_irq_handler(int irq, void *arg)
c2798b19
CW		 2223{
2224 struct drm_device *dev = (struct drm_device *) arg;
2225 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 2226 u16 iir, new_iir;
2227 u32 pipe_stats[2];
2228 unsigned long irqflags;
2229 int irq_received;
2230 int pipe;
2231 u16 flip_mask =
2232 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2233 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2234
2235 atomic_inc(&dev_priv->irq_received);
2236
2237 iir = I915_READ16(IIR);
2238 if (iir == 0)
2239 return IRQ_NONE;
2240
2241 while (iir & ~flip_mask) {
2242 /* Can't rely on pipestat interrupt bit in iir as it might
2243 * have been cleared after the pipestat interrupt was received.
2244 * It doesn't set the bit in iir again, but it still produces
2245 * interrupts (for non-MSI).
2246 */
2247 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2248 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2249 i915_handle_error(dev, false);
2250
2251 for_each_pipe(pipe) {
2252 int reg = PIPESTAT(pipe);
2253 pipe_stats[pipe] = I915_READ(reg);
2254
2255 /*
2256 * Clear the PIPE*STAT regs before the IIR
2257 */
2258 if (pipe_stats[pipe] & 0x8000ffff) {
2259 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2260 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2261 pipe_name(pipe));
2262 I915_WRITE(reg, pipe_stats[pipe]);
2263 irq_received = 1;
2264 }
2265 }
2266 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2267
2268 I915_WRITE16(IIR, iir & ~flip_mask);
2269 new_iir = I915_READ16(IIR); /* Flush posted writes */
2270
d05c617e 2271 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 2272
2273 if (iir & I915_USER_INTERRUPT)
2274 notify_ring(dev, &dev_priv->ring[RCS]);
2275
2276 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2277 drm_handle_vblank(dev, 0)) {
2278 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2279 intel_prepare_page_flip(dev, 0);
2280 intel_finish_page_flip(dev, 0);
2281 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2282 }
2283 }
2284
2285 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2286 drm_handle_vblank(dev, 1)) {
2287 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2288 intel_prepare_page_flip(dev, 1);
2289 intel_finish_page_flip(dev, 1);
2290 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2291 }
2292 }
2293
2294 iir = new_iir;
2295 }
2296
2297 return IRQ_HANDLED;
2298}
2299
2300static void i8xx_irq_uninstall(struct drm_device * dev)
2301{
2302 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2303 int pipe;
2304
c2798b19
CW		 2305 for_each_pipe(pipe) {
2306 /* Clear enable bits; then clear status bits */
2307 I915_WRITE(PIPESTAT(pipe), 0);
2308 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2309 }
2310 I915_WRITE16(IMR, 0xffff);
2311 I915_WRITE16(IER, 0x0);
2312 I915_WRITE16(IIR, I915_READ16(IIR));
2313}
2314
a266c7d5
CW		 2315static void i915_irq_preinstall(struct drm_device * dev)
2316{
2317 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2318 int pipe;
2319
2320 atomic_set(&dev_priv->irq_received, 0);
2321
2322 if (I915_HAS_HOTPLUG(dev)) {
2323 I915_WRITE(PORT_HOTPLUG_EN, 0);
2324 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2325 }
2326
00d98ebd 2327 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 2328 for_each_pipe(pipe)
2329 I915_WRITE(PIPESTAT(pipe), 0);
2330 I915_WRITE(IMR, 0xffffffff);
2331 I915_WRITE(IER, 0x0);
2332 POSTING_READ(IER);
2333}
2334
2335static int i915_irq_postinstall(struct drm_device *dev)
2336{
2337 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 2338 u32 enable_mask;
a266c7d5 2339
a266c7d5
CW		 2340 dev_priv->pipestat[0] = 0;
2341 dev_priv->pipestat[1] = 0;
2342
38bde180
CW		 2343 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2344
2345 /* Unmask the interrupts that we always want on. */
2346 dev_priv->irq_mask =
2347 ~(I915_ASLE_INTERRUPT |
2348 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2349 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2350 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2351 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2352 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2353
2354 enable_mask =
2355 I915_ASLE_INTERRUPT |
2356 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2357 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2358 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2359 I915_USER_INTERRUPT;
2360
a266c7d5 2361 if (I915_HAS_HOTPLUG(dev)) {
20afbda2
DV		 2362 I915_WRITE(PORT_HOTPLUG_EN, 0);
2363 POSTING_READ(PORT_HOTPLUG_EN);
2364
a266c7d5
CW		 2365 /* Enable in IER... */
2366 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2367 /* and unmask in IMR */
2368 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2369 }
2370
a266c7d5
CW		 2371 I915_WRITE(IMR, dev_priv->irq_mask);
2372 I915_WRITE(IER, enable_mask);
2373 POSTING_READ(IER);
2374
20afbda2
DV		 2375 intel_opregion_enable_asle(dev);
2376
2377 return 0;
2378}
2379
2380static void i915_hpd_irq_setup(struct drm_device *dev)
2381{
2382 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2383 u32 hotplug_en;
2384
a266c7d5 2385 if (I915_HAS_HOTPLUG(dev)) {
20afbda2 2386 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
a266c7d5 2387
a266c7d5
CW		 2388 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2389 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2390 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2391 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2392 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2393 hotplug_en |= HDMID_HOTPLUG_INT_EN;
084b612e 2394 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
a266c7d5 2395 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
084b612e 2396 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
a266c7d5
CW		 2397 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2398 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2399 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5
CW		 2400 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2401 }
2402
2403 /* Ignore TV since it's buggy */
2404
2405 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2406 }
a266c7d5
CW		 2407}
2408
ff1f525e 2409static irqreturn_t i915_irq_handler(int irq, void *arg)
a266c7d5
CW		 2410{
2411 struct drm_device *dev = (struct drm_device *) arg;
2412 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 2413 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 2414 unsigned long irqflags;
38bde180
CW		 2415 u32 flip_mask =
2416 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2417 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2418 u32 flip[2] = {
2419 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2420 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2421 };
2422 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 2423
2424 atomic_inc(&dev_priv->irq_received);
2425
2426 iir = I915_READ(IIR);
38bde180
CW		 2427 do {
2428 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 2429 bool blc_event = false;
a266c7d5
CW		 2430
2431 /* Can't rely on pipestat interrupt bit in iir as it might
2432 * have been cleared after the pipestat interrupt was received.
2433 * It doesn't set the bit in iir again, but it still produces
2434 * interrupts (for non-MSI).
2435 */
2436 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2437 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2438 i915_handle_error(dev, false);
2439
2440 for_each_pipe(pipe) {
2441 int reg = PIPESTAT(pipe);
2442 pipe_stats[pipe] = I915_READ(reg);
2443
38bde180 2444 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 2445 if (pipe_stats[pipe] & 0x8000ffff) {
2446 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2447 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2448 pipe_name(pipe));
2449 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 2450 irq_received = true;
a266c7d5
CW		 2451 }
2452 }
2453 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2454
2455 if (!irq_received)
2456 break;
2457
a266c7d5
CW		 2458 /* Consume port. Then clear IIR or we'll miss events */
2459 if ((I915_HAS_HOTPLUG(dev)) &&
2460 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2461 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2462
2463 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2464 hotplug_status);
2465 if (hotplug_status & dev_priv->hotplug_supported_mask)
2466 queue_work(dev_priv->wq,
2467 &dev_priv->hotplug_work);
2468
2469 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 2470 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 2471 }
2472
38bde180 2473 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2474 new_iir = I915_READ(IIR); /* Flush posted writes */
2475
a266c7d5
CW		 2476 if (iir & I915_USER_INTERRUPT)
2477 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 2478
a266c7d5 2479 for_each_pipe(pipe) {
38bde180
CW		 2480 int plane = pipe;
2481 if (IS_MOBILE(dev))
2482 plane = !plane;
8291ee90 2483 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2484 drm_handle_vblank(dev, pipe)) {
38bde180
CW		 2485 if (iir & flip[plane]) {
2486 intel_prepare_page_flip(dev, plane);
2487 intel_finish_page_flip(dev, pipe);
2488 flip_mask &= ~flip[plane];
2489 }
a266c7d5
CW		 2490 }
2491
2492 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2493 blc_event = true;
2494 }
2495
a266c7d5
CW		 2496 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2497 intel_opregion_asle_intr(dev);
2498
2499 /* With MSI, interrupts are only generated when iir
2500 * transitions from zero to nonzero. If another bit got
2501 * set while we were handling the existing iir bits, then
2502 * we would never get another interrupt.
2503 *
2504 * This is fine on non-MSI as well, as if we hit this path
2505 * we avoid exiting the interrupt handler only to generate
2506 * another one.
2507 *
2508 * Note that for MSI this could cause a stray interrupt report
2509 * if an interrupt landed in the time between writing IIR and
2510 * the posting read. This should be rare enough to never
2511 * trigger the 99% of 100,000 interrupts test for disabling
2512 * stray interrupts.
2513 */
38bde180 2514 ret = IRQ_HANDLED;
a266c7d5 2515 iir = new_iir;
38bde180 2516 } while (iir & ~flip_mask);
a266c7d5 2517
d05c617e 2518 i915_update_dri1_breadcrumb(dev);
8291ee90 2519
a266c7d5
CW		 2520 return ret;
2521}
2522
2523static void i915_irq_uninstall(struct drm_device * dev)
2524{
2525 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2526 int pipe;
2527
a266c7d5
CW		 2528 if (I915_HAS_HOTPLUG(dev)) {
2529 I915_WRITE(PORT_HOTPLUG_EN, 0);
2530 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2531 }
2532
00d98ebd 2533 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 2534 for_each_pipe(pipe) {
2535 /* Clear enable bits; then clear status bits */
a266c7d5 2536 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 2537 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2538 }
a266c7d5
CW		 2539 I915_WRITE(IMR, 0xffffffff);
2540 I915_WRITE(IER, 0x0);
2541
a266c7d5
CW		 2542 I915_WRITE(IIR, I915_READ(IIR));
2543}
2544
2545static void i965_irq_preinstall(struct drm_device * dev)
2546{
2547 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2548 int pipe;
2549
2550 atomic_set(&dev_priv->irq_received, 0);
2551
adca4730
CW		 2552 I915_WRITE(PORT_HOTPLUG_EN, 0);
2553 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2554
2555 I915_WRITE(HWSTAM, 0xeffe);
2556 for_each_pipe(pipe)
2557 I915_WRITE(PIPESTAT(pipe), 0);
2558 I915_WRITE(IMR, 0xffffffff);
2559 I915_WRITE(IER, 0x0);
2560 POSTING_READ(IER);
2561}
2562
2563static int i965_irq_postinstall(struct drm_device *dev)
2564{
2565 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
bbba0a97 2566 u32 enable_mask;
a266c7d5
CW		 2567 u32 error_mask;
2568
a266c7d5 2569 /* Unmask the interrupts that we always want on. */
bbba0a97 2570 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 2571 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 2572 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2573 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2574 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2575 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2576 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2577
2578 enable_mask = ~dev_priv->irq_mask;
2579 enable_mask |= I915_USER_INTERRUPT;
2580
2581 if (IS_G4X(dev))
2582 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5
CW		 2583
2584 dev_priv->pipestat[0] = 0;
2585 dev_priv->pipestat[1] = 0;
515ac2bb 2586 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
a266c7d5 2587
a266c7d5
CW		 2588 /*
2589 * Enable some error detection, note the instruction error mask
2590 * bit is reserved, so we leave it masked.
2591 */
2592 if (IS_G4X(dev)) {
2593 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2594 GM45_ERROR_MEM_PRIV |
2595 GM45_ERROR_CP_PRIV |
2596 I915_ERROR_MEMORY_REFRESH);
2597 } else {
2598 error_mask = ~(I915_ERROR_PAGE_TABLE |
2599 I915_ERROR_MEMORY_REFRESH);
2600 }
2601 I915_WRITE(EMR, error_mask);
2602
2603 I915_WRITE(IMR, dev_priv->irq_mask);
2604 I915_WRITE(IER, enable_mask);
2605 POSTING_READ(IER);
2606
20afbda2
DV		 2607 I915_WRITE(PORT_HOTPLUG_EN, 0);
2608 POSTING_READ(PORT_HOTPLUG_EN);
2609
2610 intel_opregion_enable_asle(dev);
2611
2612 return 0;
2613}
2614
2615static void i965_hpd_irq_setup(struct drm_device *dev)
2616{
2617 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2618 u32 hotplug_en;
2619
adca4730
CW		 2620 /* Note HDMI and DP share hotplug bits */
2621 hotplug_en = 0;
2622 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2623 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2624 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2625 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2626 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2627 hotplug_en |= HDMID_HOTPLUG_INT_EN;
084b612e
CW		 2628 if (IS_G4X(dev)) {
2629 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
2630 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2631 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
2632 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2633 } else {
2634 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
2635 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2636 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
2637 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2638 }
adca4730
CW		 2639 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2640 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5 2641
adca4730
CW		 2642 /* Programming the CRT detection parameters tends
2643 to generate a spurious hotplug event about three
2644 seconds later. So just do it once.
2645 */
2646 if (IS_G4X(dev))
2647 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2648 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2649 }
a266c7d5 2650
adca4730 2651 /* Ignore TV since it's buggy */
a266c7d5 2652
adca4730 2653 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
a266c7d5
CW		 2654}
2655
ff1f525e 2656static irqreturn_t i965_irq_handler(int irq, void *arg)
a266c7d5
CW		 2657{
2658 struct drm_device *dev = (struct drm_device *) arg;
2659 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 2660 u32 iir, new_iir;
2661 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 2662 unsigned long irqflags;
2663 int irq_received;
2664 int ret = IRQ_NONE, pipe;
a266c7d5
CW		 2665
2666 atomic_inc(&dev_priv->irq_received);
2667
2668 iir = I915_READ(IIR);
2669
a266c7d5 2670 for (;;) {
2c8ba29f
CW		 2671 bool blc_event = false;
2672
a266c7d5
CW		 2673 irq_received = iir != 0;
2674
2675 /* Can't rely on pipestat interrupt bit in iir as it might
2676 * have been cleared after the pipestat interrupt was received.
2677 * It doesn't set the bit in iir again, but it still produces
2678 * interrupts (for non-MSI).
2679 */
2680 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2681 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2682 i915_handle_error(dev, false);
2683
2684 for_each_pipe(pipe) {
2685 int reg = PIPESTAT(pipe);
2686 pipe_stats[pipe] = I915_READ(reg);
2687
2688 /*
2689 * Clear the PIPE*STAT regs before the IIR
2690 */
2691 if (pipe_stats[pipe] & 0x8000ffff) {
2692 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2693 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2694 pipe_name(pipe));
2695 I915_WRITE(reg, pipe_stats[pipe]);
2696 irq_received = 1;
2697 }
2698 }
2699 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2700
2701 if (!irq_received)
2702 break;
2703
2704 ret = IRQ_HANDLED;
2705
2706 /* Consume port. Then clear IIR or we'll miss events */
adca4730 2707 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
a266c7d5
CW		 2708 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2709
2710 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2711 hotplug_status);
2712 if (hotplug_status & dev_priv->hotplug_supported_mask)
2713 queue_work(dev_priv->wq,
2714 &dev_priv->hotplug_work);
2715
2716 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2717 I915_READ(PORT_HOTPLUG_STAT);
2718 }
2719
2720 I915_WRITE(IIR, iir);
2721 new_iir = I915_READ(IIR); /* Flush posted writes */
2722
a266c7d5
CW		 2723 if (iir & I915_USER_INTERRUPT)
2724 notify_ring(dev, &dev_priv->ring[RCS]);
2725 if (iir & I915_BSD_USER_INTERRUPT)
2726 notify_ring(dev, &dev_priv->ring[VCS]);
2727
4f7d1e79 2728 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
a266c7d5 2729 intel_prepare_page_flip(dev, 0);
a266c7d5 2730
4f7d1e79 2731 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
a266c7d5 2732 intel_prepare_page_flip(dev, 1);
a266c7d5
CW		 2733
2734 for_each_pipe(pipe) {
2c8ba29f 2735 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2736 drm_handle_vblank(dev, pipe)) {
4f7d1e79
CW		 2737 i915_pageflip_stall_check(dev, pipe);
2738 intel_finish_page_flip(dev, pipe);
a266c7d5
CW		 2739 }
2740
2741 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2742 blc_event = true;
2743 }
2744
2745
2746 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2747 intel_opregion_asle_intr(dev);
2748
515ac2bb
DV		 2749 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
2750 gmbus_irq_handler(dev);
2751
a266c7d5
CW		 2752 /* With MSI, interrupts are only generated when iir
2753 * transitions from zero to nonzero. If another bit got
2754 * set while we were handling the existing iir bits, then
2755 * we would never get another interrupt.
2756 *
2757 * This is fine on non-MSI as well, as if we hit this path
2758 * we avoid exiting the interrupt handler only to generate
2759 * another one.
2760 *
2761 * Note that for MSI this could cause a stray interrupt report
2762 * if an interrupt landed in the time between writing IIR and
2763 * the posting read. This should be rare enough to never
2764 * trigger the 99% of 100,000 interrupts test for disabling
2765 * stray interrupts.
2766 */
2767 iir = new_iir;
2768 }
2769
d05c617e 2770 i915_update_dri1_breadcrumb(dev);
2c8ba29f 2771
a266c7d5
CW		 2772 return ret;
2773}
2774
2775static void i965_irq_uninstall(struct drm_device * dev)
2776{
2777 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2778 int pipe;
2779
2780 if (!dev_priv)
2781 return;
2782
adca4730
CW		 2783 I915_WRITE(PORT_HOTPLUG_EN, 0);
2784 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2785
2786 I915_WRITE(HWSTAM, 0xffffffff);
2787 for_each_pipe(pipe)
2788 I915_WRITE(PIPESTAT(pipe), 0);
2789 I915_WRITE(IMR, 0xffffffff);
2790 I915_WRITE(IER, 0x0);
2791
2792 for_each_pipe(pipe)
2793 I915_WRITE(PIPESTAT(pipe),
2794 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2795 I915_WRITE(IIR, I915_READ(IIR));
2796}
2797
f71d4af4
JB		 2798void intel_irq_init(struct drm_device *dev)
2799{
8b2e326d
CW		 2800 struct drm_i915_private *dev_priv = dev->dev_private;
2801
2802 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
99584db3 2803 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
c6a828d3 2804 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
a4da4fa4 2805 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
8b2e326d 2806
99584db3
DV		 2807 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
2808 i915_hangcheck_elapsed,
61bac78e
DV		 2809 (unsigned long) dev);
2810
97a19a24 2811 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
9ee32fea 2812
f71d4af4
JB		 2813 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2814 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7d4e146f 2815 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 2816 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2817 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2818 }
2819
c3613de9
KP		 2820 if (drm_core_check_feature(dev, DRIVER_MODESET))
2821 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2822 else
2823 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 2824 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2825
7e231dbe
JB		 2826 if (IS_VALLEYVIEW(dev)) {
2827 dev->driver->irq_handler = valleyview_irq_handler;
2828 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2829 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2830 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2831 dev->driver->enable_vblank = valleyview_enable_vblank;
2832 dev->driver->disable_vblank = valleyview_disable_vblank;
20afbda2 2833 dev_priv->display.hpd_irq_setup = valleyview_hpd_irq_setup;
4a06e201 2834 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
f71d4af4
JB		 2835 /* Share pre & uninstall handlers with ILK/SNB */
2836 dev->driver->irq_handler = ivybridge_irq_handler;
2837 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2838 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2839 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2840 dev->driver->enable_vblank = ivybridge_enable_vblank;
2841 dev->driver->disable_vblank = ivybridge_disable_vblank;
2842 } else if (HAS_PCH_SPLIT(dev)) {
2843 dev->driver->irq_handler = ironlake_irq_handler;
2844 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2845 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2846 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2847 dev->driver->enable_vblank = ironlake_enable_vblank;
2848 dev->driver->disable_vblank = ironlake_disable_vblank;
2849 } else {
c2798b19
CW		 2850 if (INTEL_INFO(dev)->gen == 2) {
2851 dev->driver->irq_preinstall = i8xx_irq_preinstall;
2852 dev->driver->irq_postinstall = i8xx_irq_postinstall;
2853 dev->driver->irq_handler = i8xx_irq_handler;
2854 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5
CW		 2855 } else if (INTEL_INFO(dev)->gen == 3) {
2856 dev->driver->irq_preinstall = i915_irq_preinstall;
2857 dev->driver->irq_postinstall = i915_irq_postinstall;
2858 dev->driver->irq_uninstall = i915_irq_uninstall;
2859 dev->driver->irq_handler = i915_irq_handler;
20afbda2 2860 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 2861 } else {
a266c7d5
CW		 2862 dev->driver->irq_preinstall = i965_irq_preinstall;
2863 dev->driver->irq_postinstall = i965_irq_postinstall;
2864 dev->driver->irq_uninstall = i965_irq_uninstall;
2865 dev->driver->irq_handler = i965_irq_handler;
20afbda2 2866 dev_priv->display.hpd_irq_setup = i965_hpd_irq_setup;
c2798b19 2867 }
f71d4af4
JB		 2868 dev->driver->enable_vblank = i915_enable_vblank;
2869 dev->driver->disable_vblank = i915_disable_vblank;
2870 }
2871}
20afbda2
DV		 2872
2873void intel_hpd_init(struct drm_device *dev)
2874{
2875 struct drm_i915_private *dev_priv = dev->dev_private;
2876
2877 if (dev_priv->display.hpd_irq_setup)
2878 dev_priv->display.hpd_irq_setup(dev);
2879}
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