]>
Commit | Line | Data |
---|---|---|
0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
63eeaf38 | 29 | #include <linux/sysrq.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
1da177e4 LT |
31 | #include "drmP.h" |
32 | #include "drm.h" | |
33 | #include "i915_drm.h" | |
34 | #include "i915_drv.h" | |
1c5d22f7 | 35 | #include "i915_trace.h" |
79e53945 | 36 | #include "intel_drv.h" |
1da177e4 | 37 | |
1da177e4 | 38 | #define MAX_NOPID ((u32)~0) |
1da177e4 | 39 | |
7c463586 KP |
40 | /** |
41 | * Interrupts that are always left unmasked. | |
42 | * | |
43 | * Since pipe events are edge-triggered from the PIPESTAT register to IIR, | |
44 | * we leave them always unmasked in IMR and then control enabling them through | |
45 | * PIPESTAT alone. | |
46 | */ | |
6b95a207 KH |
47 | #define I915_INTERRUPT_ENABLE_FIX \ |
48 | (I915_ASLE_INTERRUPT | \ | |
49 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ | |
50 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \ | |
51 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \ | |
52 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \ | |
53 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
7c463586 KP |
54 | |
55 | /** Interrupts that we mask and unmask at runtime. */ | |
d1b851fc | 56 | #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT) |
7c463586 | 57 | |
79e53945 JB |
58 | #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\ |
59 | PIPE_VBLANK_INTERRUPT_STATUS) | |
60 | ||
61 | #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\ | |
62 | PIPE_VBLANK_INTERRUPT_ENABLE) | |
63 | ||
64 | #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \ | |
65 | DRM_I915_VBLANK_PIPE_B) | |
66 | ||
036a4a7d | 67 | void |
f2b115e6 | 68 | ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d ZW |
69 | { |
70 | if ((dev_priv->gt_irq_mask_reg & mask) != 0) { | |
71 | dev_priv->gt_irq_mask_reg &= ~mask; | |
72 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); | |
73 | (void) I915_READ(GTIMR); | |
74 | } | |
75 | } | |
76 | ||
62fdfeaf | 77 | void |
f2b115e6 | 78 | ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d ZW |
79 | { |
80 | if ((dev_priv->gt_irq_mask_reg & mask) != mask) { | |
81 | dev_priv->gt_irq_mask_reg |= mask; | |
82 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); | |
83 | (void) I915_READ(GTIMR); | |
84 | } | |
85 | } | |
86 | ||
87 | /* For display hotplug interrupt */ | |
995b6762 | 88 | static void |
f2b115e6 | 89 | ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d ZW |
90 | { |
91 | if ((dev_priv->irq_mask_reg & mask) != 0) { | |
92 | dev_priv->irq_mask_reg &= ~mask; | |
93 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); | |
94 | (void) I915_READ(DEIMR); | |
95 | } | |
96 | } | |
97 | ||
98 | static inline void | |
f2b115e6 | 99 | ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d ZW |
100 | { |
101 | if ((dev_priv->irq_mask_reg & mask) != mask) { | |
102 | dev_priv->irq_mask_reg |= mask; | |
103 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); | |
104 | (void) I915_READ(DEIMR); | |
105 | } | |
106 | } | |
107 | ||
8ee1c3db | 108 | void |
ed4cb414 EA |
109 | i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
110 | { | |
111 | if ((dev_priv->irq_mask_reg & mask) != 0) { | |
112 | dev_priv->irq_mask_reg &= ~mask; | |
113 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
114 | (void) I915_READ(IMR); | |
115 | } | |
116 | } | |
117 | ||
62fdfeaf | 118 | void |
ed4cb414 EA |
119 | i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) |
120 | { | |
121 | if ((dev_priv->irq_mask_reg & mask) != mask) { | |
122 | dev_priv->irq_mask_reg |= mask; | |
123 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
124 | (void) I915_READ(IMR); | |
125 | } | |
126 | } | |
127 | ||
7c463586 KP |
128 | static inline u32 |
129 | i915_pipestat(int pipe) | |
130 | { | |
131 | if (pipe == 0) | |
132 | return PIPEASTAT; | |
133 | if (pipe == 1) | |
134 | return PIPEBSTAT; | |
9c84ba4e | 135 | BUG(); |
7c463586 KP |
136 | } |
137 | ||
138 | void | |
139 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
140 | { | |
141 | if ((dev_priv->pipestat[pipe] & mask) != mask) { | |
142 | u32 reg = i915_pipestat(pipe); | |
143 | ||
144 | dev_priv->pipestat[pipe] |= mask; | |
145 | /* Enable the interrupt, clear any pending status */ | |
146 | I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); | |
147 | (void) I915_READ(reg); | |
148 | } | |
149 | } | |
150 | ||
151 | void | |
152 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
153 | { | |
154 | if ((dev_priv->pipestat[pipe] & mask) != 0) { | |
155 | u32 reg = i915_pipestat(pipe); | |
156 | ||
157 | dev_priv->pipestat[pipe] &= ~mask; | |
158 | I915_WRITE(reg, dev_priv->pipestat[pipe]); | |
159 | (void) I915_READ(reg); | |
160 | } | |
161 | } | |
162 | ||
01c66889 ZY |
163 | /** |
164 | * intel_enable_asle - enable ASLE interrupt for OpRegion | |
165 | */ | |
166 | void intel_enable_asle (struct drm_device *dev) | |
167 | { | |
168 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
169 | ||
c619eed4 | 170 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 171 | ironlake_enable_display_irq(dev_priv, DE_GSE); |
edcb49ca | 172 | else { |
01c66889 | 173 | i915_enable_pipestat(dev_priv, 1, |
d874bcff | 174 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
a6c45cf0 | 175 | if (INTEL_INFO(dev)->gen >= 4) |
edcb49ca | 176 | i915_enable_pipestat(dev_priv, 0, |
d874bcff | 177 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
edcb49ca | 178 | } |
01c66889 ZY |
179 | } |
180 | ||
0a3e67a4 JB |
181 | /** |
182 | * i915_pipe_enabled - check if a pipe is enabled | |
183 | * @dev: DRM device | |
184 | * @pipe: pipe to check | |
185 | * | |
186 | * Reading certain registers when the pipe is disabled can hang the chip. | |
187 | * Use this routine to make sure the PLL is running and the pipe is active | |
188 | * before reading such registers if unsure. | |
189 | */ | |
190 | static int | |
191 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
192 | { | |
193 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
5eddb70b | 194 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; |
0a3e67a4 JB |
195 | } |
196 | ||
42f52ef8 KP |
197 | /* Called from drm generic code, passed a 'crtc', which |
198 | * we use as a pipe index | |
199 | */ | |
200 | u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
201 | { |
202 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
203 | unsigned long high_frame; | |
204 | unsigned long low_frame; | |
5eddb70b | 205 | u32 high1, high2, low; |
0a3e67a4 JB |
206 | |
207 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 ZY |
208 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
209 | "pipe %d\n", pipe); | |
0a3e67a4 JB |
210 | return 0; |
211 | } | |
212 | ||
5eddb70b CW |
213 | high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH; |
214 | low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL; | |
215 | ||
0a3e67a4 JB |
216 | /* |
217 | * High & low register fields aren't synchronized, so make sure | |
218 | * we get a low value that's stable across two reads of the high | |
219 | * register. | |
220 | */ | |
221 | do { | |
5eddb70b CW |
222 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
223 | low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK; | |
224 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; | |
0a3e67a4 JB |
225 | } while (high1 != high2); |
226 | ||
5eddb70b CW |
227 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
228 | low >>= PIPE_FRAME_LOW_SHIFT; | |
229 | return (high1 << 8) | low; | |
0a3e67a4 JB |
230 | } |
231 | ||
9880b7a5 JB |
232 | u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
233 | { | |
234 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
235 | int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45; | |
236 | ||
237 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 ZY |
238 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
239 | "pipe %d\n", pipe); | |
9880b7a5 JB |
240 | return 0; |
241 | } | |
242 | ||
243 | return I915_READ(reg); | |
244 | } | |
245 | ||
5ca58282 JB |
246 | /* |
247 | * Handle hotplug events outside the interrupt handler proper. | |
248 | */ | |
249 | static void i915_hotplug_work_func(struct work_struct *work) | |
250 | { | |
251 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
252 | hotplug_work); | |
253 | struct drm_device *dev = dev_priv->dev; | |
c31c4ba3 | 254 | struct drm_mode_config *mode_config = &dev->mode_config; |
4ef69c7a CW |
255 | struct intel_encoder *encoder; |
256 | ||
257 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) | |
258 | if (encoder->hot_plug) | |
259 | encoder->hot_plug(encoder); | |
260 | ||
5ca58282 | 261 | /* Just fire off a uevent and let userspace tell us what to do */ |
eb1f8e4f | 262 | drm_helper_hpd_irq_event(dev); |
5ca58282 JB |
263 | } |
264 | ||
f97108d1 JB |
265 | static void i915_handle_rps_change(struct drm_device *dev) |
266 | { | |
267 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b5b72e89 | 268 | u32 busy_up, busy_down, max_avg, min_avg; |
f97108d1 JB |
269 | u8 new_delay = dev_priv->cur_delay; |
270 | ||
7648fa99 | 271 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
272 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
273 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
274 | max_avg = I915_READ(RCBMAXAVG); |
275 | min_avg = I915_READ(RCBMINAVG); | |
276 | ||
277 | /* Handle RCS change request from hw */ | |
b5b72e89 | 278 | if (busy_up > max_avg) { |
f97108d1 JB |
279 | if (dev_priv->cur_delay != dev_priv->max_delay) |
280 | new_delay = dev_priv->cur_delay - 1; | |
281 | if (new_delay < dev_priv->max_delay) | |
282 | new_delay = dev_priv->max_delay; | |
b5b72e89 | 283 | } else if (busy_down < min_avg) { |
f97108d1 JB |
284 | if (dev_priv->cur_delay != dev_priv->min_delay) |
285 | new_delay = dev_priv->cur_delay + 1; | |
286 | if (new_delay > dev_priv->min_delay) | |
287 | new_delay = dev_priv->min_delay; | |
288 | } | |
289 | ||
7648fa99 JB |
290 | if (ironlake_set_drps(dev, new_delay)) |
291 | dev_priv->cur_delay = new_delay; | |
f97108d1 JB |
292 | |
293 | return; | |
294 | } | |
295 | ||
995b6762 | 296 | static irqreturn_t ironlake_irq_handler(struct drm_device *dev) |
036a4a7d ZW |
297 | { |
298 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
299 | int ret = IRQ_NONE; | |
3ff99164 | 300 | u32 de_iir, gt_iir, de_ier, pch_iir; |
036a4a7d | 301 | struct drm_i915_master_private *master_priv; |
852835f3 | 302 | struct intel_ring_buffer *render_ring = &dev_priv->render_ring; |
881f47b6 XH |
303 | u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT; |
304 | ||
305 | if (IS_GEN6(dev)) | |
306 | bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT; | |
036a4a7d | 307 | |
2d109a84 ZN |
308 | /* disable master interrupt before clearing iir */ |
309 | de_ier = I915_READ(DEIER); | |
310 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
311 | (void)I915_READ(DEIER); | |
312 | ||
036a4a7d ZW |
313 | de_iir = I915_READ(DEIIR); |
314 | gt_iir = I915_READ(GTIIR); | |
c650156a | 315 | pch_iir = I915_READ(SDEIIR); |
036a4a7d | 316 | |
c7c85101 ZN |
317 | if (de_iir == 0 && gt_iir == 0 && pch_iir == 0) |
318 | goto done; | |
036a4a7d | 319 | |
c7c85101 | 320 | ret = IRQ_HANDLED; |
036a4a7d | 321 | |
c7c85101 ZN |
322 | if (dev->primary->master) { |
323 | master_priv = dev->primary->master->driver_priv; | |
324 | if (master_priv->sarea_priv) | |
325 | master_priv->sarea_priv->last_dispatch = | |
326 | READ_BREADCRUMB(dev_priv); | |
327 | } | |
036a4a7d | 328 | |
e552eb70 | 329 | if (gt_iir & GT_PIPE_NOTIFY) { |
f787a5f5 | 330 | u32 seqno = render_ring->get_seqno(dev, render_ring); |
852835f3 | 331 | render_ring->irq_gem_seqno = seqno; |
c7c85101 | 332 | trace_i915_gem_request_complete(dev, seqno); |
f787a5f5 | 333 | wake_up_all(&dev_priv->render_ring.irq_queue); |
c7c85101 | 334 | dev_priv->hangcheck_count = 0; |
b3b079db CW |
335 | mod_timer(&dev_priv->hangcheck_timer, |
336 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
c7c85101 | 337 | } |
881f47b6 | 338 | if (gt_iir & bsd_usr_interrupt) |
f787a5f5 | 339 | wake_up_all(&dev_priv->bsd_ring.irq_queue); |
d1b851fc | 340 | |
c7c85101 | 341 | if (de_iir & DE_GSE) |
3b617967 | 342 | intel_opregion_gse_intr(dev); |
c650156a | 343 | |
f072d2e7 | 344 | if (de_iir & DE_PLANEA_FLIP_DONE) { |
013d5aa2 | 345 | intel_prepare_page_flip(dev, 0); |
2bbda389 | 346 | intel_finish_page_flip_plane(dev, 0); |
f072d2e7 | 347 | } |
013d5aa2 | 348 | |
f072d2e7 | 349 | if (de_iir & DE_PLANEB_FLIP_DONE) { |
013d5aa2 | 350 | intel_prepare_page_flip(dev, 1); |
2bbda389 | 351 | intel_finish_page_flip_plane(dev, 1); |
f072d2e7 | 352 | } |
013d5aa2 | 353 | |
f072d2e7 | 354 | if (de_iir & DE_PIPEA_VBLANK) |
c062df61 LP |
355 | drm_handle_vblank(dev, 0); |
356 | ||
f072d2e7 | 357 | if (de_iir & DE_PIPEB_VBLANK) |
c062df61 LP |
358 | drm_handle_vblank(dev, 1); |
359 | ||
c7c85101 ZN |
360 | /* check event from PCH */ |
361 | if ((de_iir & DE_PCH_EVENT) && | |
362 | (pch_iir & SDE_HOTPLUG_MASK)) { | |
363 | queue_work(dev_priv->wq, &dev_priv->hotplug_work); | |
036a4a7d ZW |
364 | } |
365 | ||
f97108d1 | 366 | if (de_iir & DE_PCU_EVENT) { |
7648fa99 | 367 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
f97108d1 JB |
368 | i915_handle_rps_change(dev); |
369 | } | |
370 | ||
c7c85101 ZN |
371 | /* should clear PCH hotplug event before clear CPU irq */ |
372 | I915_WRITE(SDEIIR, pch_iir); | |
373 | I915_WRITE(GTIIR, gt_iir); | |
374 | I915_WRITE(DEIIR, de_iir); | |
375 | ||
376 | done: | |
2d109a84 ZN |
377 | I915_WRITE(DEIER, de_ier); |
378 | (void)I915_READ(DEIER); | |
379 | ||
036a4a7d ZW |
380 | return ret; |
381 | } | |
382 | ||
8a905236 JB |
383 | /** |
384 | * i915_error_work_func - do process context error handling work | |
385 | * @work: work struct | |
386 | * | |
387 | * Fire an error uevent so userspace can see that a hang or error | |
388 | * was detected. | |
389 | */ | |
390 | static void i915_error_work_func(struct work_struct *work) | |
391 | { | |
392 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
393 | error_work); | |
394 | struct drm_device *dev = dev_priv->dev; | |
f316a42c BG |
395 | char *error_event[] = { "ERROR=1", NULL }; |
396 | char *reset_event[] = { "RESET=1", NULL }; | |
397 | char *reset_done_event[] = { "ERROR=0", NULL }; | |
8a905236 | 398 | |
44d98a61 | 399 | DRM_DEBUG_DRIVER("generating error event\n"); |
f316a42c BG |
400 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); |
401 | ||
ba1234d1 | 402 | if (atomic_read(&dev_priv->mm.wedged)) { |
f803aa55 CW |
403 | DRM_DEBUG_DRIVER("resetting chip\n"); |
404 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); | |
405 | if (!i915_reset(dev, GRDOM_RENDER)) { | |
406 | atomic_set(&dev_priv->mm.wedged, 0); | |
407 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); | |
f316a42c BG |
408 | } |
409 | } | |
8a905236 JB |
410 | } |
411 | ||
3bd3c932 | 412 | #ifdef CONFIG_DEBUG_FS |
9df30794 CW |
413 | static struct drm_i915_error_object * |
414 | i915_error_object_create(struct drm_device *dev, | |
415 | struct drm_gem_object *src) | |
416 | { | |
e56660dd | 417 | drm_i915_private_t *dev_priv = dev->dev_private; |
9df30794 CW |
418 | struct drm_i915_error_object *dst; |
419 | struct drm_i915_gem_object *src_priv; | |
420 | int page, page_count; | |
e56660dd | 421 | u32 reloc_offset; |
9df30794 CW |
422 | |
423 | if (src == NULL) | |
424 | return NULL; | |
425 | ||
23010e43 | 426 | src_priv = to_intel_bo(src); |
9df30794 CW |
427 | if (src_priv->pages == NULL) |
428 | return NULL; | |
429 | ||
430 | page_count = src->size / PAGE_SIZE; | |
431 | ||
432 | dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC); | |
433 | if (dst == NULL) | |
434 | return NULL; | |
435 | ||
e56660dd | 436 | reloc_offset = src_priv->gtt_offset; |
9df30794 | 437 | for (page = 0; page < page_count; page++) { |
788885ae | 438 | unsigned long flags; |
e56660dd CW |
439 | void __iomem *s; |
440 | void *d; | |
788885ae | 441 | |
e56660dd | 442 | d = kmalloc(PAGE_SIZE, GFP_ATOMIC); |
9df30794 CW |
443 | if (d == NULL) |
444 | goto unwind; | |
e56660dd | 445 | |
788885ae | 446 | local_irq_save(flags); |
e56660dd CW |
447 | s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
448 | reloc_offset, | |
449 | KM_IRQ0); | |
450 | memcpy_fromio(d, s, PAGE_SIZE); | |
451 | io_mapping_unmap_atomic(s, KM_IRQ0); | |
788885ae | 452 | local_irq_restore(flags); |
e56660dd | 453 | |
9df30794 | 454 | dst->pages[page] = d; |
e56660dd CW |
455 | |
456 | reloc_offset += PAGE_SIZE; | |
9df30794 CW |
457 | } |
458 | dst->page_count = page_count; | |
459 | dst->gtt_offset = src_priv->gtt_offset; | |
460 | ||
461 | return dst; | |
462 | ||
463 | unwind: | |
464 | while (page--) | |
465 | kfree(dst->pages[page]); | |
466 | kfree(dst); | |
467 | return NULL; | |
468 | } | |
469 | ||
470 | static void | |
471 | i915_error_object_free(struct drm_i915_error_object *obj) | |
472 | { | |
473 | int page; | |
474 | ||
475 | if (obj == NULL) | |
476 | return; | |
477 | ||
478 | for (page = 0; page < obj->page_count; page++) | |
479 | kfree(obj->pages[page]); | |
480 | ||
481 | kfree(obj); | |
482 | } | |
483 | ||
484 | static void | |
485 | i915_error_state_free(struct drm_device *dev, | |
486 | struct drm_i915_error_state *error) | |
487 | { | |
488 | i915_error_object_free(error->batchbuffer[0]); | |
489 | i915_error_object_free(error->batchbuffer[1]); | |
490 | i915_error_object_free(error->ringbuffer); | |
491 | kfree(error->active_bo); | |
6ef3d427 | 492 | kfree(error->overlay); |
9df30794 CW |
493 | kfree(error); |
494 | } | |
495 | ||
496 | static u32 | |
497 | i915_get_bbaddr(struct drm_device *dev, u32 *ring) | |
498 | { | |
499 | u32 cmd; | |
500 | ||
501 | if (IS_I830(dev) || IS_845G(dev)) | |
502 | cmd = MI_BATCH_BUFFER; | |
a6c45cf0 | 503 | else if (INTEL_INFO(dev)->gen >= 4) |
9df30794 CW |
504 | cmd = (MI_BATCH_BUFFER_START | (2 << 6) | |
505 | MI_BATCH_NON_SECURE_I965); | |
506 | else | |
507 | cmd = (MI_BATCH_BUFFER_START | (2 << 6)); | |
508 | ||
509 | return ring[0] == cmd ? ring[1] : 0; | |
510 | } | |
511 | ||
512 | static u32 | |
513 | i915_ringbuffer_last_batch(struct drm_device *dev) | |
514 | { | |
515 | struct drm_i915_private *dev_priv = dev->dev_private; | |
516 | u32 head, bbaddr; | |
517 | u32 *ring; | |
518 | ||
519 | /* Locate the current position in the ringbuffer and walk back | |
520 | * to find the most recently dispatched batch buffer. | |
521 | */ | |
522 | bbaddr = 0; | |
523 | head = I915_READ(PRB0_HEAD) & HEAD_ADDR; | |
d3301d86 | 524 | ring = (u32 *)(dev_priv->render_ring.virtual_start + head); |
9df30794 | 525 | |
d3301d86 | 526 | while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) { |
9df30794 CW |
527 | bbaddr = i915_get_bbaddr(dev, ring); |
528 | if (bbaddr) | |
529 | break; | |
530 | } | |
531 | ||
532 | if (bbaddr == 0) { | |
8187a2b7 ZN |
533 | ring = (u32 *)(dev_priv->render_ring.virtual_start |
534 | + dev_priv->render_ring.size); | |
d3301d86 | 535 | while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) { |
9df30794 CW |
536 | bbaddr = i915_get_bbaddr(dev, ring); |
537 | if (bbaddr) | |
538 | break; | |
539 | } | |
540 | } | |
541 | ||
542 | return bbaddr; | |
543 | } | |
544 | ||
8a905236 JB |
545 | /** |
546 | * i915_capture_error_state - capture an error record for later analysis | |
547 | * @dev: drm device | |
548 | * | |
549 | * Should be called when an error is detected (either a hang or an error | |
550 | * interrupt) to capture error state from the time of the error. Fills | |
551 | * out a structure which becomes available in debugfs for user level tools | |
552 | * to pick up. | |
553 | */ | |
63eeaf38 JB |
554 | static void i915_capture_error_state(struct drm_device *dev) |
555 | { | |
556 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9df30794 | 557 | struct drm_i915_gem_object *obj_priv; |
63eeaf38 | 558 | struct drm_i915_error_state *error; |
9df30794 | 559 | struct drm_gem_object *batchbuffer[2]; |
63eeaf38 | 560 | unsigned long flags; |
9df30794 CW |
561 | u32 bbaddr; |
562 | int count; | |
63eeaf38 JB |
563 | |
564 | spin_lock_irqsave(&dev_priv->error_lock, flags); | |
9df30794 CW |
565 | error = dev_priv->first_error; |
566 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); | |
567 | if (error) | |
568 | return; | |
63eeaf38 JB |
569 | |
570 | error = kmalloc(sizeof(*error), GFP_ATOMIC); | |
571 | if (!error) { | |
9df30794 CW |
572 | DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); |
573 | return; | |
63eeaf38 JB |
574 | } |
575 | ||
f787a5f5 CW |
576 | error->seqno = |
577 | dev_priv->render_ring.get_seqno(dev, &dev_priv->render_ring); | |
63eeaf38 JB |
578 | error->eir = I915_READ(EIR); |
579 | error->pgtbl_er = I915_READ(PGTBL_ER); | |
580 | error->pipeastat = I915_READ(PIPEASTAT); | |
581 | error->pipebstat = I915_READ(PIPEBSTAT); | |
582 | error->instpm = I915_READ(INSTPM); | |
a6c45cf0 | 583 | if (INTEL_INFO(dev)->gen < 4) { |
63eeaf38 JB |
584 | error->ipeir = I915_READ(IPEIR); |
585 | error->ipehr = I915_READ(IPEHR); | |
586 | error->instdone = I915_READ(INSTDONE); | |
587 | error->acthd = I915_READ(ACTHD); | |
9df30794 | 588 | error->bbaddr = 0; |
63eeaf38 JB |
589 | } else { |
590 | error->ipeir = I915_READ(IPEIR_I965); | |
591 | error->ipehr = I915_READ(IPEHR_I965); | |
592 | error->instdone = I915_READ(INSTDONE_I965); | |
593 | error->instps = I915_READ(INSTPS); | |
594 | error->instdone1 = I915_READ(INSTDONE1); | |
595 | error->acthd = I915_READ(ACTHD_I965); | |
9df30794 | 596 | error->bbaddr = I915_READ64(BB_ADDR); |
63eeaf38 JB |
597 | } |
598 | ||
9df30794 | 599 | bbaddr = i915_ringbuffer_last_batch(dev); |
8a905236 | 600 | |
9df30794 CW |
601 | /* Grab the current batchbuffer, most likely to have crashed. */ |
602 | batchbuffer[0] = NULL; | |
603 | batchbuffer[1] = NULL; | |
604 | count = 0; | |
852835f3 ZN |
605 | list_for_each_entry(obj_priv, |
606 | &dev_priv->render_ring.active_list, list) { | |
607 | ||
a8089e84 | 608 | struct drm_gem_object *obj = &obj_priv->base; |
63eeaf38 | 609 | |
9df30794 CW |
610 | if (batchbuffer[0] == NULL && |
611 | bbaddr >= obj_priv->gtt_offset && | |
612 | bbaddr < obj_priv->gtt_offset + obj->size) | |
613 | batchbuffer[0] = obj; | |
614 | ||
615 | if (batchbuffer[1] == NULL && | |
616 | error->acthd >= obj_priv->gtt_offset && | |
e56660dd | 617 | error->acthd < obj_priv->gtt_offset + obj->size) |
9df30794 CW |
618 | batchbuffer[1] = obj; |
619 | ||
620 | count++; | |
621 | } | |
e56660dd CW |
622 | /* Scan the other lists for completeness for those bizarre errors. */ |
623 | if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) { | |
624 | list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) { | |
625 | struct drm_gem_object *obj = &obj_priv->base; | |
626 | ||
627 | if (batchbuffer[0] == NULL && | |
628 | bbaddr >= obj_priv->gtt_offset && | |
629 | bbaddr < obj_priv->gtt_offset + obj->size) | |
630 | batchbuffer[0] = obj; | |
631 | ||
632 | if (batchbuffer[1] == NULL && | |
633 | error->acthd >= obj_priv->gtt_offset && | |
634 | error->acthd < obj_priv->gtt_offset + obj->size) | |
635 | batchbuffer[1] = obj; | |
636 | ||
637 | if (batchbuffer[0] && batchbuffer[1]) | |
638 | break; | |
639 | } | |
640 | } | |
641 | if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) { | |
642 | list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) { | |
643 | struct drm_gem_object *obj = &obj_priv->base; | |
644 | ||
645 | if (batchbuffer[0] == NULL && | |
646 | bbaddr >= obj_priv->gtt_offset && | |
647 | bbaddr < obj_priv->gtt_offset + obj->size) | |
648 | batchbuffer[0] = obj; | |
649 | ||
650 | if (batchbuffer[1] == NULL && | |
651 | error->acthd >= obj_priv->gtt_offset && | |
652 | error->acthd < obj_priv->gtt_offset + obj->size) | |
653 | batchbuffer[1] = obj; | |
654 | ||
655 | if (batchbuffer[0] && batchbuffer[1]) | |
656 | break; | |
657 | } | |
658 | } | |
9df30794 CW |
659 | |
660 | /* We need to copy these to an anonymous buffer as the simplest | |
661 | * method to avoid being overwritten by userpace. | |
662 | */ | |
663 | error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]); | |
e56660dd CW |
664 | if (batchbuffer[1] != batchbuffer[0]) |
665 | error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]); | |
666 | else | |
667 | error->batchbuffer[1] = NULL; | |
9df30794 CW |
668 | |
669 | /* Record the ringbuffer */ | |
8187a2b7 ZN |
670 | error->ringbuffer = i915_error_object_create(dev, |
671 | dev_priv->render_ring.gem_object); | |
9df30794 CW |
672 | |
673 | /* Record buffers on the active list. */ | |
674 | error->active_bo = NULL; | |
675 | error->active_bo_count = 0; | |
676 | ||
677 | if (count) | |
678 | error->active_bo = kmalloc(sizeof(*error->active_bo)*count, | |
679 | GFP_ATOMIC); | |
680 | ||
681 | if (error->active_bo) { | |
682 | int i = 0; | |
852835f3 ZN |
683 | list_for_each_entry(obj_priv, |
684 | &dev_priv->render_ring.active_list, list) { | |
a8089e84 | 685 | struct drm_gem_object *obj = &obj_priv->base; |
9df30794 CW |
686 | |
687 | error->active_bo[i].size = obj->size; | |
688 | error->active_bo[i].name = obj->name; | |
689 | error->active_bo[i].seqno = obj_priv->last_rendering_seqno; | |
690 | error->active_bo[i].gtt_offset = obj_priv->gtt_offset; | |
691 | error->active_bo[i].read_domains = obj->read_domains; | |
692 | error->active_bo[i].write_domain = obj->write_domain; | |
693 | error->active_bo[i].fence_reg = obj_priv->fence_reg; | |
694 | error->active_bo[i].pinned = 0; | |
695 | if (obj_priv->pin_count > 0) | |
696 | error->active_bo[i].pinned = 1; | |
697 | if (obj_priv->user_pin_count > 0) | |
698 | error->active_bo[i].pinned = -1; | |
699 | error->active_bo[i].tiling = obj_priv->tiling_mode; | |
700 | error->active_bo[i].dirty = obj_priv->dirty; | |
701 | error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED; | |
702 | ||
703 | if (++i == count) | |
704 | break; | |
705 | } | |
706 | error->active_bo_count = i; | |
707 | } | |
708 | ||
709 | do_gettimeofday(&error->time); | |
710 | ||
6ef3d427 CW |
711 | error->overlay = intel_overlay_capture_error_state(dev); |
712 | ||
9df30794 CW |
713 | spin_lock_irqsave(&dev_priv->error_lock, flags); |
714 | if (dev_priv->first_error == NULL) { | |
715 | dev_priv->first_error = error; | |
716 | error = NULL; | |
717 | } | |
63eeaf38 | 718 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); |
9df30794 CW |
719 | |
720 | if (error) | |
721 | i915_error_state_free(dev, error); | |
722 | } | |
723 | ||
724 | void i915_destroy_error_state(struct drm_device *dev) | |
725 | { | |
726 | struct drm_i915_private *dev_priv = dev->dev_private; | |
727 | struct drm_i915_error_state *error; | |
728 | ||
729 | spin_lock(&dev_priv->error_lock); | |
730 | error = dev_priv->first_error; | |
731 | dev_priv->first_error = NULL; | |
732 | spin_unlock(&dev_priv->error_lock); | |
733 | ||
734 | if (error) | |
735 | i915_error_state_free(dev, error); | |
63eeaf38 | 736 | } |
3bd3c932 CW |
737 | #else |
738 | #define i915_capture_error_state(x) | |
739 | #endif | |
63eeaf38 | 740 | |
35aed2e6 | 741 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
742 | { |
743 | struct drm_i915_private *dev_priv = dev->dev_private; | |
744 | u32 eir = I915_READ(EIR); | |
8a905236 | 745 | |
35aed2e6 CW |
746 | if (!eir) |
747 | return; | |
8a905236 JB |
748 | |
749 | printk(KERN_ERR "render error detected, EIR: 0x%08x\n", | |
750 | eir); | |
751 | ||
752 | if (IS_G4X(dev)) { | |
753 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
754 | u32 ipeir = I915_READ(IPEIR_I965); | |
755 | ||
756 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
757 | I915_READ(IPEIR_I965)); | |
758 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
759 | I915_READ(IPEHR_I965)); | |
760 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
761 | I915_READ(INSTDONE_I965)); | |
762 | printk(KERN_ERR " INSTPS: 0x%08x\n", | |
763 | I915_READ(INSTPS)); | |
764 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", | |
765 | I915_READ(INSTDONE1)); | |
766 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
767 | I915_READ(ACTHD_I965)); | |
768 | I915_WRITE(IPEIR_I965, ipeir); | |
769 | (void)I915_READ(IPEIR_I965); | |
770 | } | |
771 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
772 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
773 | printk(KERN_ERR "page table error\n"); | |
774 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", | |
775 | pgtbl_err); | |
776 | I915_WRITE(PGTBL_ER, pgtbl_err); | |
777 | (void)I915_READ(PGTBL_ER); | |
778 | } | |
779 | } | |
780 | ||
a6c45cf0 | 781 | if (!IS_GEN2(dev)) { |
8a905236 JB |
782 | if (eir & I915_ERROR_PAGE_TABLE) { |
783 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
784 | printk(KERN_ERR "page table error\n"); | |
785 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", | |
786 | pgtbl_err); | |
787 | I915_WRITE(PGTBL_ER, pgtbl_err); | |
788 | (void)I915_READ(PGTBL_ER); | |
789 | } | |
790 | } | |
791 | ||
792 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
35aed2e6 CW |
793 | u32 pipea_stats = I915_READ(PIPEASTAT); |
794 | u32 pipeb_stats = I915_READ(PIPEBSTAT); | |
795 | ||
8a905236 JB |
796 | printk(KERN_ERR "memory refresh error\n"); |
797 | printk(KERN_ERR "PIPEASTAT: 0x%08x\n", | |
798 | pipea_stats); | |
799 | printk(KERN_ERR "PIPEBSTAT: 0x%08x\n", | |
800 | pipeb_stats); | |
801 | /* pipestat has already been acked */ | |
802 | } | |
803 | if (eir & I915_ERROR_INSTRUCTION) { | |
804 | printk(KERN_ERR "instruction error\n"); | |
805 | printk(KERN_ERR " INSTPM: 0x%08x\n", | |
806 | I915_READ(INSTPM)); | |
a6c45cf0 | 807 | if (INTEL_INFO(dev)->gen < 4) { |
8a905236 JB |
808 | u32 ipeir = I915_READ(IPEIR); |
809 | ||
810 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
811 | I915_READ(IPEIR)); | |
812 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
813 | I915_READ(IPEHR)); | |
814 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
815 | I915_READ(INSTDONE)); | |
816 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
817 | I915_READ(ACTHD)); | |
818 | I915_WRITE(IPEIR, ipeir); | |
819 | (void)I915_READ(IPEIR); | |
820 | } else { | |
821 | u32 ipeir = I915_READ(IPEIR_I965); | |
822 | ||
823 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
824 | I915_READ(IPEIR_I965)); | |
825 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
826 | I915_READ(IPEHR_I965)); | |
827 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
828 | I915_READ(INSTDONE_I965)); | |
829 | printk(KERN_ERR " INSTPS: 0x%08x\n", | |
830 | I915_READ(INSTPS)); | |
831 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", | |
832 | I915_READ(INSTDONE1)); | |
833 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
834 | I915_READ(ACTHD_I965)); | |
835 | I915_WRITE(IPEIR_I965, ipeir); | |
836 | (void)I915_READ(IPEIR_I965); | |
837 | } | |
838 | } | |
839 | ||
840 | I915_WRITE(EIR, eir); | |
841 | (void)I915_READ(EIR); | |
842 | eir = I915_READ(EIR); | |
843 | if (eir) { | |
844 | /* | |
845 | * some errors might have become stuck, | |
846 | * mask them. | |
847 | */ | |
848 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
849 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
850 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
851 | } | |
35aed2e6 CW |
852 | } |
853 | ||
854 | /** | |
855 | * i915_handle_error - handle an error interrupt | |
856 | * @dev: drm device | |
857 | * | |
858 | * Do some basic checking of regsiter state at error interrupt time and | |
859 | * dump it to the syslog. Also call i915_capture_error_state() to make | |
860 | * sure we get a record and make it available in debugfs. Fire a uevent | |
861 | * so userspace knows something bad happened (should trigger collection | |
862 | * of a ring dump etc.). | |
863 | */ | |
864 | static void i915_handle_error(struct drm_device *dev, bool wedged) | |
865 | { | |
866 | struct drm_i915_private *dev_priv = dev->dev_private; | |
867 | ||
868 | i915_capture_error_state(dev); | |
869 | i915_report_and_clear_eir(dev); | |
8a905236 | 870 | |
ba1234d1 BG |
871 | if (wedged) { |
872 | atomic_set(&dev_priv->mm.wedged, 1); | |
873 | ||
11ed50ec BG |
874 | /* |
875 | * Wakeup waiting processes so they don't hang | |
876 | */ | |
f787a5f5 CW |
877 | wake_up_all(&dev_priv->render_ring.irq_queue); |
878 | if (HAS_BSD(dev)) | |
879 | wake_up_all(&dev_priv->bsd_ring.irq_queue); | |
11ed50ec BG |
880 | } |
881 | ||
9c9fe1f8 | 882 | queue_work(dev_priv->wq, &dev_priv->error_work); |
8a905236 JB |
883 | } |
884 | ||
4e5359cd SF |
885 | static void i915_pageflip_stall_check(struct drm_device *dev, int pipe) |
886 | { | |
887 | drm_i915_private_t *dev_priv = dev->dev_private; | |
888 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
889 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
890 | struct drm_i915_gem_object *obj_priv; | |
891 | struct intel_unpin_work *work; | |
892 | unsigned long flags; | |
893 | bool stall_detected; | |
894 | ||
895 | /* Ignore early vblank irqs */ | |
896 | if (intel_crtc == NULL) | |
897 | return; | |
898 | ||
899 | spin_lock_irqsave(&dev->event_lock, flags); | |
900 | work = intel_crtc->unpin_work; | |
901 | ||
902 | if (work == NULL || work->pending || !work->enable_stall_check) { | |
903 | /* Either the pending flip IRQ arrived, or we're too early. Don't check */ | |
904 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
905 | return; | |
906 | } | |
907 | ||
908 | /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ | |
909 | obj_priv = to_intel_bo(work->pending_flip_obj); | |
a6c45cf0 | 910 | if (INTEL_INFO(dev)->gen >= 4) { |
4e5359cd SF |
911 | int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF; |
912 | stall_detected = I915_READ(dspsurf) == obj_priv->gtt_offset; | |
913 | } else { | |
914 | int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR; | |
915 | stall_detected = I915_READ(dspaddr) == (obj_priv->gtt_offset + | |
916 | crtc->y * crtc->fb->pitch + | |
917 | crtc->x * crtc->fb->bits_per_pixel/8); | |
918 | } | |
919 | ||
920 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
921 | ||
922 | if (stall_detected) { | |
923 | DRM_DEBUG_DRIVER("Pageflip stall detected\n"); | |
924 | intel_prepare_page_flip(dev, intel_crtc->plane); | |
925 | } | |
926 | } | |
927 | ||
1da177e4 LT |
928 | irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) |
929 | { | |
84b1fd10 | 930 | struct drm_device *dev = (struct drm_device *) arg; |
1da177e4 | 931 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 932 | struct drm_i915_master_private *master_priv; |
cdfbc41f EA |
933 | u32 iir, new_iir; |
934 | u32 pipea_stats, pipeb_stats; | |
05eff845 | 935 | u32 vblank_status; |
0a3e67a4 | 936 | int vblank = 0; |
7c463586 | 937 | unsigned long irqflags; |
05eff845 KP |
938 | int irq_received; |
939 | int ret = IRQ_NONE; | |
852835f3 | 940 | struct intel_ring_buffer *render_ring = &dev_priv->render_ring; |
6e5fca53 | 941 | |
630681d9 EA |
942 | atomic_inc(&dev_priv->irq_received); |
943 | ||
bad720ff | 944 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 945 | return ironlake_irq_handler(dev); |
036a4a7d | 946 | |
ed4cb414 | 947 | iir = I915_READ(IIR); |
a6b54f3f | 948 | |
a6c45cf0 | 949 | if (INTEL_INFO(dev)->gen >= 4) |
d874bcff | 950 | vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS; |
e25e6601 | 951 | else |
d874bcff | 952 | vblank_status = PIPE_VBLANK_INTERRUPT_STATUS; |
af6061af | 953 | |
05eff845 KP |
954 | for (;;) { |
955 | irq_received = iir != 0; | |
956 | ||
957 | /* Can't rely on pipestat interrupt bit in iir as it might | |
958 | * have been cleared after the pipestat interrupt was received. | |
959 | * It doesn't set the bit in iir again, but it still produces | |
960 | * interrupts (for non-MSI). | |
961 | */ | |
962 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); | |
963 | pipea_stats = I915_READ(PIPEASTAT); | |
964 | pipeb_stats = I915_READ(PIPEBSTAT); | |
79e53945 | 965 | |
8a905236 | 966 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
ba1234d1 | 967 | i915_handle_error(dev, false); |
8a905236 | 968 | |
cdfbc41f EA |
969 | /* |
970 | * Clear the PIPE(A|B)STAT regs before the IIR | |
971 | */ | |
05eff845 | 972 | if (pipea_stats & 0x8000ffff) { |
7662c8bd | 973 | if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS) |
44d98a61 | 974 | DRM_DEBUG_DRIVER("pipe a underrun\n"); |
cdfbc41f | 975 | I915_WRITE(PIPEASTAT, pipea_stats); |
05eff845 | 976 | irq_received = 1; |
cdfbc41f | 977 | } |
1da177e4 | 978 | |
05eff845 | 979 | if (pipeb_stats & 0x8000ffff) { |
7662c8bd | 980 | if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS) |
44d98a61 | 981 | DRM_DEBUG_DRIVER("pipe b underrun\n"); |
cdfbc41f | 982 | I915_WRITE(PIPEBSTAT, pipeb_stats); |
05eff845 | 983 | irq_received = 1; |
cdfbc41f | 984 | } |
05eff845 KP |
985 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
986 | ||
987 | if (!irq_received) | |
988 | break; | |
989 | ||
990 | ret = IRQ_HANDLED; | |
8ee1c3db | 991 | |
5ca58282 JB |
992 | /* Consume port. Then clear IIR or we'll miss events */ |
993 | if ((I915_HAS_HOTPLUG(dev)) && | |
994 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { | |
995 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
996 | ||
44d98a61 | 997 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
5ca58282 JB |
998 | hotplug_status); |
999 | if (hotplug_status & dev_priv->hotplug_supported_mask) | |
9c9fe1f8 EA |
1000 | queue_work(dev_priv->wq, |
1001 | &dev_priv->hotplug_work); | |
5ca58282 JB |
1002 | |
1003 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
1004 | I915_READ(PORT_HOTPLUG_STAT); | |
1005 | } | |
1006 | ||
cdfbc41f EA |
1007 | I915_WRITE(IIR, iir); |
1008 | new_iir = I915_READ(IIR); /* Flush posted writes */ | |
7c463586 | 1009 | |
7c1c2871 DA |
1010 | if (dev->primary->master) { |
1011 | master_priv = dev->primary->master->driver_priv; | |
1012 | if (master_priv->sarea_priv) | |
1013 | master_priv->sarea_priv->last_dispatch = | |
1014 | READ_BREADCRUMB(dev_priv); | |
1015 | } | |
0a3e67a4 | 1016 | |
cdfbc41f | 1017 | if (iir & I915_USER_INTERRUPT) { |
f787a5f5 | 1018 | u32 seqno = render_ring->get_seqno(dev, render_ring); |
852835f3 | 1019 | render_ring->irq_gem_seqno = seqno; |
1c5d22f7 | 1020 | trace_i915_gem_request_complete(dev, seqno); |
f787a5f5 | 1021 | wake_up_all(&dev_priv->render_ring.irq_queue); |
f65d9421 | 1022 | dev_priv->hangcheck_count = 0; |
b3b079db CW |
1023 | mod_timer(&dev_priv->hangcheck_timer, |
1024 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
cdfbc41f | 1025 | } |
673a394b | 1026 | |
d1b851fc | 1027 | if (HAS_BSD(dev) && (iir & I915_BSD_USER_INTERRUPT)) |
f787a5f5 | 1028 | wake_up_all(&dev_priv->bsd_ring.irq_queue); |
d1b851fc | 1029 | |
1afe3e9d | 1030 | if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) { |
6b95a207 | 1031 | intel_prepare_page_flip(dev, 0); |
1afe3e9d JB |
1032 | if (dev_priv->flip_pending_is_done) |
1033 | intel_finish_page_flip_plane(dev, 0); | |
1034 | } | |
6b95a207 | 1035 | |
1afe3e9d | 1036 | if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) { |
70565d00 | 1037 | intel_prepare_page_flip(dev, 1); |
1afe3e9d JB |
1038 | if (dev_priv->flip_pending_is_done) |
1039 | intel_finish_page_flip_plane(dev, 1); | |
1afe3e9d | 1040 | } |
6b95a207 | 1041 | |
05eff845 | 1042 | if (pipea_stats & vblank_status) { |
cdfbc41f EA |
1043 | vblank++; |
1044 | drm_handle_vblank(dev, 0); | |
4e5359cd SF |
1045 | if (!dev_priv->flip_pending_is_done) { |
1046 | i915_pageflip_stall_check(dev, 0); | |
1afe3e9d | 1047 | intel_finish_page_flip(dev, 0); |
4e5359cd | 1048 | } |
cdfbc41f | 1049 | } |
7c463586 | 1050 | |
05eff845 | 1051 | if (pipeb_stats & vblank_status) { |
cdfbc41f EA |
1052 | vblank++; |
1053 | drm_handle_vblank(dev, 1); | |
4e5359cd SF |
1054 | if (!dev_priv->flip_pending_is_done) { |
1055 | i915_pageflip_stall_check(dev, 1); | |
1afe3e9d | 1056 | intel_finish_page_flip(dev, 1); |
4e5359cd | 1057 | } |
cdfbc41f | 1058 | } |
7c463586 | 1059 | |
d874bcff JB |
1060 | if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) || |
1061 | (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) || | |
cdfbc41f | 1062 | (iir & I915_ASLE_INTERRUPT)) |
3b617967 | 1063 | intel_opregion_asle_intr(dev); |
cdfbc41f EA |
1064 | |
1065 | /* With MSI, interrupts are only generated when iir | |
1066 | * transitions from zero to nonzero. If another bit got | |
1067 | * set while we were handling the existing iir bits, then | |
1068 | * we would never get another interrupt. | |
1069 | * | |
1070 | * This is fine on non-MSI as well, as if we hit this path | |
1071 | * we avoid exiting the interrupt handler only to generate | |
1072 | * another one. | |
1073 | * | |
1074 | * Note that for MSI this could cause a stray interrupt report | |
1075 | * if an interrupt landed in the time between writing IIR and | |
1076 | * the posting read. This should be rare enough to never | |
1077 | * trigger the 99% of 100,000 interrupts test for disabling | |
1078 | * stray interrupts. | |
1079 | */ | |
1080 | iir = new_iir; | |
05eff845 | 1081 | } |
0a3e67a4 | 1082 | |
05eff845 | 1083 | return ret; |
1da177e4 LT |
1084 | } |
1085 | ||
af6061af | 1086 | static int i915_emit_irq(struct drm_device * dev) |
1da177e4 LT |
1087 | { |
1088 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 1089 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 LT |
1090 | |
1091 | i915_kernel_lost_context(dev); | |
1092 | ||
44d98a61 | 1093 | DRM_DEBUG_DRIVER("\n"); |
1da177e4 | 1094 | |
c99b058f | 1095 | dev_priv->counter++; |
c29b669c | 1096 | if (dev_priv->counter > 0x7FFFFFFFUL) |
c99b058f | 1097 | dev_priv->counter = 1; |
7c1c2871 DA |
1098 | if (master_priv->sarea_priv) |
1099 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; | |
c29b669c | 1100 | |
0baf823a | 1101 | BEGIN_LP_RING(4); |
585fb111 | 1102 | OUT_RING(MI_STORE_DWORD_INDEX); |
0baf823a | 1103 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
c29b669c | 1104 | OUT_RING(dev_priv->counter); |
585fb111 | 1105 | OUT_RING(MI_USER_INTERRUPT); |
1da177e4 | 1106 | ADVANCE_LP_RING(); |
bc5f4523 | 1107 | |
c29b669c | 1108 | return dev_priv->counter; |
1da177e4 LT |
1109 | } |
1110 | ||
9d34e5db CW |
1111 | void i915_trace_irq_get(struct drm_device *dev, u32 seqno) |
1112 | { | |
1113 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
8187a2b7 | 1114 | struct intel_ring_buffer *render_ring = &dev_priv->render_ring; |
9d34e5db CW |
1115 | |
1116 | if (dev_priv->trace_irq_seqno == 0) | |
8187a2b7 | 1117 | render_ring->user_irq_get(dev, render_ring); |
9d34e5db CW |
1118 | |
1119 | dev_priv->trace_irq_seqno = seqno; | |
1120 | } | |
1121 | ||
84b1fd10 | 1122 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) |
1da177e4 LT |
1123 | { |
1124 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
7c1c2871 | 1125 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 1126 | int ret = 0; |
8187a2b7 | 1127 | struct intel_ring_buffer *render_ring = &dev_priv->render_ring; |
1da177e4 | 1128 | |
44d98a61 | 1129 | DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr, |
1da177e4 LT |
1130 | READ_BREADCRUMB(dev_priv)); |
1131 | ||
ed4cb414 | 1132 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { |
7c1c2871 DA |
1133 | if (master_priv->sarea_priv) |
1134 | master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); | |
1da177e4 | 1135 | return 0; |
ed4cb414 | 1136 | } |
1da177e4 | 1137 | |
7c1c2871 DA |
1138 | if (master_priv->sarea_priv) |
1139 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1da177e4 | 1140 | |
8187a2b7 | 1141 | render_ring->user_irq_get(dev, render_ring); |
852835f3 | 1142 | DRM_WAIT_ON(ret, dev_priv->render_ring.irq_queue, 3 * DRM_HZ, |
1da177e4 | 1143 | READ_BREADCRUMB(dev_priv) >= irq_nr); |
8187a2b7 | 1144 | render_ring->user_irq_put(dev, render_ring); |
1da177e4 | 1145 | |
20caafa6 | 1146 | if (ret == -EBUSY) { |
3e684eae | 1147 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", |
1da177e4 LT |
1148 | READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); |
1149 | } | |
1150 | ||
af6061af DA |
1151 | return ret; |
1152 | } | |
1153 | ||
1da177e4 LT |
1154 | /* Needs the lock as it touches the ring. |
1155 | */ | |
c153f45f EA |
1156 | int i915_irq_emit(struct drm_device *dev, void *data, |
1157 | struct drm_file *file_priv) | |
1da177e4 | 1158 | { |
1da177e4 | 1159 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1160 | drm_i915_irq_emit_t *emit = data; |
1da177e4 LT |
1161 | int result; |
1162 | ||
d3301d86 | 1163 | if (!dev_priv || !dev_priv->render_ring.virtual_start) { |
3e684eae | 1164 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1165 | return -EINVAL; |
1da177e4 | 1166 | } |
299eb93c EA |
1167 | |
1168 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); | |
1169 | ||
546b0974 | 1170 | mutex_lock(&dev->struct_mutex); |
1da177e4 | 1171 | result = i915_emit_irq(dev); |
546b0974 | 1172 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 1173 | |
c153f45f | 1174 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { |
1da177e4 | 1175 | DRM_ERROR("copy_to_user\n"); |
20caafa6 | 1176 | return -EFAULT; |
1da177e4 LT |
1177 | } |
1178 | ||
1179 | return 0; | |
1180 | } | |
1181 | ||
1182 | /* Doesn't need the hardware lock. | |
1183 | */ | |
c153f45f EA |
1184 | int i915_irq_wait(struct drm_device *dev, void *data, |
1185 | struct drm_file *file_priv) | |
1da177e4 | 1186 | { |
1da177e4 | 1187 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1188 | drm_i915_irq_wait_t *irqwait = data; |
1da177e4 LT |
1189 | |
1190 | if (!dev_priv) { | |
3e684eae | 1191 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1192 | return -EINVAL; |
1da177e4 LT |
1193 | } |
1194 | ||
c153f45f | 1195 | return i915_wait_irq(dev, irqwait->irq_seq); |
1da177e4 LT |
1196 | } |
1197 | ||
42f52ef8 KP |
1198 | /* Called from drm generic code, passed 'crtc' which |
1199 | * we use as a pipe index | |
1200 | */ | |
1201 | int i915_enable_vblank(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
1202 | { |
1203 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 1204 | unsigned long irqflags; |
71e0ffa5 | 1205 | |
5eddb70b | 1206 | if (!i915_pipe_enabled(dev, pipe)) |
71e0ffa5 | 1207 | return -EINVAL; |
0a3e67a4 | 1208 | |
e9d21d7f | 1209 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
bad720ff | 1210 | if (HAS_PCH_SPLIT(dev)) |
c062df61 LP |
1211 | ironlake_enable_display_irq(dev_priv, (pipe == 0) ? |
1212 | DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); | |
a6c45cf0 | 1213 | else if (INTEL_INFO(dev)->gen >= 4) |
7c463586 KP |
1214 | i915_enable_pipestat(dev_priv, pipe, |
1215 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 1216 | else |
7c463586 KP |
1217 | i915_enable_pipestat(dev_priv, pipe, |
1218 | PIPE_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 1219 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
0a3e67a4 JB |
1220 | return 0; |
1221 | } | |
1222 | ||
42f52ef8 KP |
1223 | /* Called from drm generic code, passed 'crtc' which |
1224 | * we use as a pipe index | |
1225 | */ | |
1226 | void i915_disable_vblank(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
1227 | { |
1228 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 1229 | unsigned long irqflags; |
0a3e67a4 | 1230 | |
e9d21d7f | 1231 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
bad720ff | 1232 | if (HAS_PCH_SPLIT(dev)) |
c062df61 LP |
1233 | ironlake_disable_display_irq(dev_priv, (pipe == 0) ? |
1234 | DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); | |
1235 | else | |
1236 | i915_disable_pipestat(dev_priv, pipe, | |
1237 | PIPE_VBLANK_INTERRUPT_ENABLE | | |
1238 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 1239 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
0a3e67a4 JB |
1240 | } |
1241 | ||
79e53945 JB |
1242 | void i915_enable_interrupt (struct drm_device *dev) |
1243 | { | |
1244 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e170b030 | 1245 | |
bad720ff | 1246 | if (!HAS_PCH_SPLIT(dev)) |
3b617967 | 1247 | intel_opregion_enable_asle(dev); |
79e53945 JB |
1248 | dev_priv->irq_enabled = 1; |
1249 | } | |
1250 | ||
1251 | ||
702880f2 DA |
1252 | /* Set the vblank monitor pipe |
1253 | */ | |
c153f45f EA |
1254 | int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
1255 | struct drm_file *file_priv) | |
702880f2 | 1256 | { |
702880f2 | 1257 | drm_i915_private_t *dev_priv = dev->dev_private; |
702880f2 DA |
1258 | |
1259 | if (!dev_priv) { | |
3e684eae | 1260 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1261 | return -EINVAL; |
702880f2 DA |
1262 | } |
1263 | ||
5b51694a | 1264 | return 0; |
702880f2 DA |
1265 | } |
1266 | ||
c153f45f EA |
1267 | int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
1268 | struct drm_file *file_priv) | |
702880f2 | 1269 | { |
702880f2 | 1270 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1271 | drm_i915_vblank_pipe_t *pipe = data; |
702880f2 DA |
1272 | |
1273 | if (!dev_priv) { | |
3e684eae | 1274 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1275 | return -EINVAL; |
702880f2 DA |
1276 | } |
1277 | ||
0a3e67a4 | 1278 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
c153f45f | 1279 | |
702880f2 DA |
1280 | return 0; |
1281 | } | |
1282 | ||
a6b54f3f MD |
1283 | /** |
1284 | * Schedule buffer swap at given vertical blank. | |
1285 | */ | |
c153f45f EA |
1286 | int i915_vblank_swap(struct drm_device *dev, void *data, |
1287 | struct drm_file *file_priv) | |
a6b54f3f | 1288 | { |
bd95e0a4 EA |
1289 | /* The delayed swap mechanism was fundamentally racy, and has been |
1290 | * removed. The model was that the client requested a delayed flip/swap | |
1291 | * from the kernel, then waited for vblank before continuing to perform | |
1292 | * rendering. The problem was that the kernel might wake the client | |
1293 | * up before it dispatched the vblank swap (since the lock has to be | |
1294 | * held while touching the ringbuffer), in which case the client would | |
1295 | * clear and start the next frame before the swap occurred, and | |
1296 | * flicker would occur in addition to likely missing the vblank. | |
1297 | * | |
1298 | * In the absence of this ioctl, userland falls back to a correct path | |
1299 | * of waiting for a vblank, then dispatching the swap on its own. | |
1300 | * Context switching to userland and back is plenty fast enough for | |
1301 | * meeting the requirements of vblank swapping. | |
0a3e67a4 | 1302 | */ |
bd95e0a4 | 1303 | return -EINVAL; |
a6b54f3f MD |
1304 | } |
1305 | ||
995b6762 | 1306 | static struct drm_i915_gem_request * |
852835f3 ZN |
1307 | i915_get_tail_request(struct drm_device *dev) |
1308 | { | |
f65d9421 | 1309 | drm_i915_private_t *dev_priv = dev->dev_private; |
852835f3 ZN |
1310 | return list_entry(dev_priv->render_ring.request_list.prev, |
1311 | struct drm_i915_gem_request, list); | |
f65d9421 BG |
1312 | } |
1313 | ||
1314 | /** | |
1315 | * This is called when the chip hasn't reported back with completed | |
1316 | * batchbuffers in a long time. The first time this is called we simply record | |
1317 | * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses | |
1318 | * again, we assume the chip is wedged and try to fix it. | |
1319 | */ | |
1320 | void i915_hangcheck_elapsed(unsigned long data) | |
1321 | { | |
1322 | struct drm_device *dev = (struct drm_device *)data; | |
1323 | drm_i915_private_t *dev_priv = dev->dev_private; | |
cbb465e7 | 1324 | uint32_t acthd, instdone, instdone1; |
b9201c14 | 1325 | |
a6c45cf0 | 1326 | if (INTEL_INFO(dev)->gen < 4) { |
f65d9421 | 1327 | acthd = I915_READ(ACTHD); |
cbb465e7 CW |
1328 | instdone = I915_READ(INSTDONE); |
1329 | instdone1 = 0; | |
1330 | } else { | |
f65d9421 | 1331 | acthd = I915_READ(ACTHD_I965); |
cbb465e7 CW |
1332 | instdone = I915_READ(INSTDONE_I965); |
1333 | instdone1 = I915_READ(INSTDONE1); | |
1334 | } | |
f65d9421 BG |
1335 | |
1336 | /* If all work is done then ACTHD clearly hasn't advanced. */ | |
852835f3 | 1337 | if (list_empty(&dev_priv->render_ring.request_list) || |
f787a5f5 CW |
1338 | i915_seqno_passed(dev_priv->render_ring.get_seqno(dev, &dev_priv->render_ring), |
1339 | i915_get_tail_request(dev)->seqno)) { | |
7839d956 CW |
1340 | bool missed_wakeup = false; |
1341 | ||
f65d9421 | 1342 | dev_priv->hangcheck_count = 0; |
e78d73b1 CW |
1343 | |
1344 | /* Issue a wake-up to catch stuck h/w. */ | |
7839d956 CW |
1345 | if (dev_priv->render_ring.waiting_gem_seqno && |
1346 | waitqueue_active(&dev_priv->render_ring.irq_queue)) { | |
f787a5f5 | 1347 | wake_up_all(&dev_priv->render_ring.irq_queue); |
7839d956 CW |
1348 | missed_wakeup = true; |
1349 | } | |
1350 | ||
1351 | if (dev_priv->bsd_ring.waiting_gem_seqno && | |
1352 | waitqueue_active(&dev_priv->bsd_ring.irq_queue)) { | |
f787a5f5 | 1353 | wake_up_all(&dev_priv->bsd_ring.irq_queue); |
7839d956 | 1354 | missed_wakeup = true; |
e78d73b1 | 1355 | } |
7839d956 CW |
1356 | |
1357 | if (missed_wakeup) | |
1358 | DRM_ERROR("Hangcheck timer elapsed... GPU idle, missed IRQ.\n"); | |
f65d9421 BG |
1359 | return; |
1360 | } | |
1361 | ||
cbb465e7 CW |
1362 | if (dev_priv->last_acthd == acthd && |
1363 | dev_priv->last_instdone == instdone && | |
1364 | dev_priv->last_instdone1 == instdone1) { | |
1365 | if (dev_priv->hangcheck_count++ > 1) { | |
1366 | DRM_ERROR("Hangcheck timer elapsed... GPU hung\n"); | |
8c80b59b CW |
1367 | |
1368 | if (!IS_GEN2(dev)) { | |
1369 | /* Is the chip hanging on a WAIT_FOR_EVENT? | |
1370 | * If so we can simply poke the RB_WAIT bit | |
1371 | * and break the hang. This should work on | |
1372 | * all but the second generation chipsets. | |
1373 | */ | |
1374 | u32 tmp = I915_READ(PRB0_CTL); | |
1375 | if (tmp & RING_WAIT) { | |
1376 | I915_WRITE(PRB0_CTL, tmp); | |
1377 | POSTING_READ(PRB0_CTL); | |
1378 | goto out; | |
1379 | } | |
1380 | } | |
1381 | ||
cbb465e7 CW |
1382 | i915_handle_error(dev, true); |
1383 | return; | |
1384 | } | |
1385 | } else { | |
1386 | dev_priv->hangcheck_count = 0; | |
1387 | ||
1388 | dev_priv->last_acthd = acthd; | |
1389 | dev_priv->last_instdone = instdone; | |
1390 | dev_priv->last_instdone1 = instdone1; | |
1391 | } | |
f65d9421 | 1392 | |
8c80b59b | 1393 | out: |
f65d9421 | 1394 | /* Reset timer case chip hangs without another request being added */ |
b3b079db CW |
1395 | mod_timer(&dev_priv->hangcheck_timer, |
1396 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
f65d9421 BG |
1397 | } |
1398 | ||
1da177e4 LT |
1399 | /* drm_dma.h hooks |
1400 | */ | |
f2b115e6 | 1401 | static void ironlake_irq_preinstall(struct drm_device *dev) |
036a4a7d ZW |
1402 | { |
1403 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1404 | ||
1405 | I915_WRITE(HWSTAM, 0xeffe); | |
1406 | ||
1407 | /* XXX hotplug from PCH */ | |
1408 | ||
1409 | I915_WRITE(DEIMR, 0xffffffff); | |
1410 | I915_WRITE(DEIER, 0x0); | |
1411 | (void) I915_READ(DEIER); | |
1412 | ||
1413 | /* and GT */ | |
1414 | I915_WRITE(GTIMR, 0xffffffff); | |
1415 | I915_WRITE(GTIER, 0x0); | |
1416 | (void) I915_READ(GTIER); | |
c650156a ZW |
1417 | |
1418 | /* south display irq */ | |
1419 | I915_WRITE(SDEIMR, 0xffffffff); | |
1420 | I915_WRITE(SDEIER, 0x0); | |
1421 | (void) I915_READ(SDEIER); | |
036a4a7d ZW |
1422 | } |
1423 | ||
f2b115e6 | 1424 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d ZW |
1425 | { |
1426 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1427 | /* enable kind of interrupts always enabled */ | |
013d5aa2 JB |
1428 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | |
1429 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; | |
d1b851fc | 1430 | u32 render_mask = GT_PIPE_NOTIFY | GT_BSD_USER_INTERRUPT; |
c650156a ZW |
1431 | u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG | |
1432 | SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG; | |
036a4a7d ZW |
1433 | |
1434 | dev_priv->irq_mask_reg = ~display_mask; | |
643ced9b | 1435 | dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK; |
036a4a7d ZW |
1436 | |
1437 | /* should always can generate irq */ | |
1438 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1439 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); | |
1440 | I915_WRITE(DEIER, dev_priv->de_irq_enable_reg); | |
1441 | (void) I915_READ(DEIER); | |
1442 | ||
3fdef020 | 1443 | if (IS_GEN6(dev)) |
881f47b6 | 1444 | render_mask = GT_PIPE_NOTIFY | GT_GEN6_BSD_USER_INTERRUPT; |
3fdef020 | 1445 | |
852835f3 | 1446 | dev_priv->gt_irq_mask_reg = ~render_mask; |
036a4a7d ZW |
1447 | dev_priv->gt_irq_enable_reg = render_mask; |
1448 | ||
1449 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1450 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); | |
881f47b6 | 1451 | if (IS_GEN6(dev)) { |
3fdef020 | 1452 | I915_WRITE(GEN6_RENDER_IMR, ~GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT); |
881f47b6 XH |
1453 | I915_WRITE(GEN6_BSD_IMR, ~GEN6_BSD_IMR_USER_INTERRUPT); |
1454 | } | |
1455 | ||
036a4a7d ZW |
1456 | I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg); |
1457 | (void) I915_READ(GTIER); | |
1458 | ||
c650156a ZW |
1459 | dev_priv->pch_irq_mask_reg = ~hotplug_mask; |
1460 | dev_priv->pch_irq_enable_reg = hotplug_mask; | |
1461 | ||
1462 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | |
1463 | I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg); | |
1464 | I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg); | |
1465 | (void) I915_READ(SDEIER); | |
1466 | ||
f97108d1 JB |
1467 | if (IS_IRONLAKE_M(dev)) { |
1468 | /* Clear & enable PCU event interrupts */ | |
1469 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
1470 | I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT); | |
1471 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); | |
1472 | } | |
1473 | ||
036a4a7d ZW |
1474 | return 0; |
1475 | } | |
1476 | ||
84b1fd10 | 1477 | void i915_driver_irq_preinstall(struct drm_device * dev) |
1da177e4 LT |
1478 | { |
1479 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1480 | ||
79e53945 JB |
1481 | atomic_set(&dev_priv->irq_received, 0); |
1482 | ||
036a4a7d | 1483 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); |
8a905236 | 1484 | INIT_WORK(&dev_priv->error_work, i915_error_work_func); |
036a4a7d | 1485 | |
bad720ff | 1486 | if (HAS_PCH_SPLIT(dev)) { |
f2b115e6 | 1487 | ironlake_irq_preinstall(dev); |
036a4a7d ZW |
1488 | return; |
1489 | } | |
1490 | ||
5ca58282 JB |
1491 | if (I915_HAS_HOTPLUG(dev)) { |
1492 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
1493 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
1494 | } | |
1495 | ||
0a3e67a4 | 1496 | I915_WRITE(HWSTAM, 0xeffe); |
7c463586 KP |
1497 | I915_WRITE(PIPEASTAT, 0); |
1498 | I915_WRITE(PIPEBSTAT, 0); | |
0a3e67a4 | 1499 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 1500 | I915_WRITE(IER, 0x0); |
7c463586 | 1501 | (void) I915_READ(IER); |
1da177e4 LT |
1502 | } |
1503 | ||
b01f2c3a JB |
1504 | /* |
1505 | * Must be called after intel_modeset_init or hotplug interrupts won't be | |
1506 | * enabled correctly. | |
1507 | */ | |
0a3e67a4 | 1508 | int i915_driver_irq_postinstall(struct drm_device *dev) |
1da177e4 LT |
1509 | { |
1510 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
5ca58282 | 1511 | u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR; |
63eeaf38 | 1512 | u32 error_mask; |
0a3e67a4 | 1513 | |
852835f3 | 1514 | DRM_INIT_WAITQUEUE(&dev_priv->render_ring.irq_queue); |
036a4a7d | 1515 | |
d1b851fc ZN |
1516 | if (HAS_BSD(dev)) |
1517 | DRM_INIT_WAITQUEUE(&dev_priv->bsd_ring.irq_queue); | |
1518 | ||
0a3e67a4 | 1519 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
0a3e67a4 | 1520 | |
bad720ff | 1521 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 1522 | return ironlake_irq_postinstall(dev); |
036a4a7d | 1523 | |
7c463586 KP |
1524 | /* Unmask the interrupts that we always want on. */ |
1525 | dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX; | |
1526 | ||
1527 | dev_priv->pipestat[0] = 0; | |
1528 | dev_priv->pipestat[1] = 0; | |
1529 | ||
5ca58282 | 1530 | if (I915_HAS_HOTPLUG(dev)) { |
5ca58282 JB |
1531 | /* Enable in IER... */ |
1532 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
1533 | /* and unmask in IMR */ | |
c496fa1f | 1534 | dev_priv->irq_mask_reg &= ~I915_DISPLAY_PORT_INTERRUPT; |
5ca58282 JB |
1535 | } |
1536 | ||
63eeaf38 JB |
1537 | /* |
1538 | * Enable some error detection, note the instruction error mask | |
1539 | * bit is reserved, so we leave it masked. | |
1540 | */ | |
1541 | if (IS_G4X(dev)) { | |
1542 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
1543 | GM45_ERROR_MEM_PRIV | | |
1544 | GM45_ERROR_CP_PRIV | | |
1545 | I915_ERROR_MEMORY_REFRESH); | |
1546 | } else { | |
1547 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
1548 | I915_ERROR_MEMORY_REFRESH); | |
1549 | } | |
1550 | I915_WRITE(EMR, error_mask); | |
1551 | ||
7c463586 | 1552 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
c496fa1f | 1553 | I915_WRITE(IER, enable_mask); |
ed4cb414 EA |
1554 | (void) I915_READ(IER); |
1555 | ||
c496fa1f AJ |
1556 | if (I915_HAS_HOTPLUG(dev)) { |
1557 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
1558 | ||
1559 | /* Note HDMI and DP share bits */ | |
1560 | if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) | |
1561 | hotplug_en |= HDMIB_HOTPLUG_INT_EN; | |
1562 | if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) | |
1563 | hotplug_en |= HDMIC_HOTPLUG_INT_EN; | |
1564 | if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) | |
1565 | hotplug_en |= HDMID_HOTPLUG_INT_EN; | |
1566 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS) | |
1567 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; | |
1568 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS) | |
1569 | hotplug_en |= SDVOB_HOTPLUG_INT_EN; | |
2d1c9752 | 1570 | if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { |
c496fa1f | 1571 | hotplug_en |= CRT_HOTPLUG_INT_EN; |
2d1c9752 AL |
1572 | |
1573 | /* Programming the CRT detection parameters tends | |
1574 | to generate a spurious hotplug event about three | |
1575 | seconds later. So just do it once. | |
1576 | */ | |
1577 | if (IS_G4X(dev)) | |
1578 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
1579 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; | |
1580 | } | |
1581 | ||
c496fa1f AJ |
1582 | /* Ignore TV since it's buggy */ |
1583 | ||
1584 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
1585 | } | |
1586 | ||
3b617967 | 1587 | intel_opregion_enable_asle(dev); |
0a3e67a4 JB |
1588 | |
1589 | return 0; | |
1da177e4 LT |
1590 | } |
1591 | ||
f2b115e6 | 1592 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d ZW |
1593 | { |
1594 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1595 | I915_WRITE(HWSTAM, 0xffffffff); | |
1596 | ||
1597 | I915_WRITE(DEIMR, 0xffffffff); | |
1598 | I915_WRITE(DEIER, 0x0); | |
1599 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1600 | ||
1601 | I915_WRITE(GTIMR, 0xffffffff); | |
1602 | I915_WRITE(GTIER, 0x0); | |
1603 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1604 | } | |
1605 | ||
84b1fd10 | 1606 | void i915_driver_irq_uninstall(struct drm_device * dev) |
1da177e4 LT |
1607 | { |
1608 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
91e3738e | 1609 | |
1da177e4 LT |
1610 | if (!dev_priv) |
1611 | return; | |
1612 | ||
0a3e67a4 JB |
1613 | dev_priv->vblank_pipe = 0; |
1614 | ||
bad720ff | 1615 | if (HAS_PCH_SPLIT(dev)) { |
f2b115e6 | 1616 | ironlake_irq_uninstall(dev); |
036a4a7d ZW |
1617 | return; |
1618 | } | |
1619 | ||
5ca58282 JB |
1620 | if (I915_HAS_HOTPLUG(dev)) { |
1621 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
1622 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
1623 | } | |
1624 | ||
0a3e67a4 | 1625 | I915_WRITE(HWSTAM, 0xffffffff); |
7c463586 KP |
1626 | I915_WRITE(PIPEASTAT, 0); |
1627 | I915_WRITE(PIPEBSTAT, 0); | |
0a3e67a4 | 1628 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 1629 | I915_WRITE(IER, 0x0); |
af6061af | 1630 | |
7c463586 KP |
1631 | I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); |
1632 | I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); | |
1633 | I915_WRITE(IIR, I915_READ(IIR)); | |
1da177e4 | 1634 | } |