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d330a953 JN |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the | |
6 | * "Software"), to deal in the Software without restriction, including | |
7 | * without limitation the rights to use, copy, modify, merge, publish, | |
8 | * distribute, sub license, and/or sell copies of the Software, and to | |
9 | * permit persons to whom the Software is furnished to do so, subject to | |
10 | * the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the | |
13 | * next paragraph) shall be included in all copies or substantial portions | |
14 | * of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | */ | |
24 | ||
c838d719 | 25 | #include "i915_params.h" |
d330a953 JN |
26 | #include "i915_drv.h" |
27 | ||
28 | struct i915_params i915 __read_mostly = { | |
29 | .modeset = -1, | |
30 | .panel_ignore_lid = 1, | |
d330a953 | 31 | .semaphores = -1, |
d330a953 JN |
32 | .lvds_channel_mode = 0, |
33 | .panel_use_ssc = -1, | |
34 | .vbt_sdvo_panel_type = -1, | |
35 | .enable_rc6 = -1, | |
443646c7 | 36 | .enable_dc = -1, |
d330a953 | 37 | .enable_fbc = -1, |
27401d12 | 38 | .enable_execlists = -1, |
d330a953 JN |
39 | .enable_hangcheck = true, |
40 | .enable_ppgtt = -1, | |
d94d6e87 | 41 | .enable_psr = -1, |
c007fb4a | 42 | .alpha_support = IS_ENABLED(CONFIG_DRM_I915_ALPHA_SUPPORT), |
1b0e3a04 | 43 | .disable_power_well = -1, |
d330a953 | 44 | .enable_ips = 1, |
73831236 | 45 | .fastboot = 0, |
d330a953 | 46 | .prefault_disable = 0, |
5bedeb2d | 47 | .load_detect_test = 0, |
522a63de | 48 | .force_reset_modeset_test = 0, |
ed35dd7b | 49 | .reset = 1, |
98a2f411 | 50 | .error_capture = true, |
d330a953 | 51 | .invert_brightness = 0, |
a0bae57f | 52 | .disable_display = 0, |
41736a8e | 53 | .enable_cmd_parser = true, |
5a21b665 | 54 | .use_mmio_flip = 0, |
5978118c | 55 | .mmio_debug = 0, |
e2c719b7 | 56 | .verbose_state_checks = 1, |
c5b852f3 | 57 | .nuclear_pageflip = 0, |
9e458034 | 58 | .edp_vswing = 0, |
fe993bc9 RV |
59 | .enable_guc_loading = 0, |
60 | .enable_guc_submission = 0, | |
63dc0449 | 61 | .guc_log_level = -1, |
b3420dde AH |
62 | .guc_firmware_path = NULL, |
63 | .huc_firmware_path = NULL, | |
7cc96139 | 64 | .enable_dp_mst = true, |
4fec15d1 | 65 | .inject_load_failure = 0, |
e7156c83 | 66 | .enable_dpcd_backlight = false, |
0ad35fed | 67 | .enable_gvt = false, |
d330a953 JN |
68 | }; |
69 | ||
70 | module_param_named(modeset, i915.modeset, int, 0400); | |
71 | MODULE_PARM_DESC(modeset, | |
bf13af56 | 72 | "Use kernel modesetting [KMS] (0=disable, " |
d330a953 JN |
73 | "1=on, -1=force vga console preference [default])"); |
74 | ||
25e1793f | 75 | module_param_named_unsafe(panel_ignore_lid, i915.panel_ignore_lid, int, 0600); |
d330a953 JN |
76 | MODULE_PARM_DESC(panel_ignore_lid, |
77 | "Override lid status (0=autodetect, 1=autodetect disabled [default], " | |
78 | "-1=force lid closed, -2=force lid open)"); | |
79 | ||
fc9740ce | 80 | module_param_named_unsafe(semaphores, i915.semaphores, int, 0400); |
d330a953 JN |
81 | MODULE_PARM_DESC(semaphores, |
82 | "Use semaphores for inter-ring sync " | |
83 | "(default: -1 (use per-chip defaults))"); | |
84 | ||
fc9740ce | 85 | module_param_named_unsafe(enable_rc6, i915.enable_rc6, int, 0400); |
3adee7a7 | 86 | MODULE_PARM_DESC(enable_rc6, |
d330a953 JN |
87 | "Enable power-saving render C-state 6. " |
88 | "Different stages can be selected via bitmask values " | |
89 | "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). " | |
90 | "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. " | |
91 | "default: -1 (use per-chip default)"); | |
92 | ||
443646c7 PJ |
93 | module_param_named_unsafe(enable_dc, i915.enable_dc, int, 0400); |
94 | MODULE_PARM_DESC(enable_dc, | |
95 | "Enable power-saving display C-states. " | |
96 | "(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6)"); | |
97 | ||
fc9740ce | 98 | module_param_named_unsafe(enable_fbc, i915.enable_fbc, int, 0600); |
3adee7a7 | 99 | MODULE_PARM_DESC(enable_fbc, |
d330a953 JN |
100 | "Enable frame buffer compression for power savings " |
101 | "(default: -1 (use per-chip default))"); | |
102 | ||
57b63d00 | 103 | module_param_named_unsafe(lvds_channel_mode, i915.lvds_channel_mode, int, 0400); |
d330a953 JN |
104 | MODULE_PARM_DESC(lvds_channel_mode, |
105 | "Specify LVDS channel mode " | |
106 | "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)"); | |
107 | ||
25e1793f | 108 | module_param_named_unsafe(lvds_use_ssc, i915.panel_use_ssc, int, 0600); |
d330a953 JN |
109 | MODULE_PARM_DESC(lvds_use_ssc, |
110 | "Use Spread Spectrum Clock with panels [LVDS/eDP] " | |
111 | "(default: auto from VBT)"); | |
112 | ||
57b63d00 | 113 | module_param_named_unsafe(vbt_sdvo_panel_type, i915.vbt_sdvo_panel_type, int, 0400); |
d330a953 JN |
114 | MODULE_PARM_DESC(vbt_sdvo_panel_type, |
115 | "Override/Ignore selection of SDVO panel mode in the VBT " | |
116 | "(-2=ignore, -1=auto [default], index in VBT BIOS table)"); | |
117 | ||
ed35dd7b MT |
118 | module_param_named_unsafe(reset, i915.reset, int, 0600); |
119 | MODULE_PARM_DESC(reset, "Attempt GPU resets (0=disabled, 1=full gpu reset [default], 2=engine reset)"); | |
d330a953 | 120 | |
98a2f411 CW |
121 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
122 | module_param_named(error_capture, i915.error_capture, bool, 0600); | |
123 | MODULE_PARM_DESC(error_capture, | |
124 | "Record the GPU state following a hang. " | |
125 | "This information in /sys/class/drm/card<N>/error is vital for " | |
126 | "triaging and debugging hangs."); | |
127 | #endif | |
128 | ||
25e1793f | 129 | module_param_named_unsafe(enable_hangcheck, i915.enable_hangcheck, bool, 0644); |
d330a953 JN |
130 | MODULE_PARM_DESC(enable_hangcheck, |
131 | "Periodically check GPU activity for detecting hangs. " | |
132 | "WARNING: Disabling this can cause system wide hangs. " | |
133 | "(default: true)"); | |
134 | ||
fc9740ce | 135 | module_param_named_unsafe(enable_ppgtt, i915.enable_ppgtt, int, 0400); |
3adee7a7 | 136 | MODULE_PARM_DESC(enable_ppgtt, |
d330a953 | 137 | "Override PPGTT usage. " |
1f9a99e0 | 138 | "(-1=auto [default], 0=disabled, 1=aliasing, 2=full, 3=full with extended address space)"); |
d330a953 | 139 | |
25e1793f | 140 | module_param_named_unsafe(enable_execlists, i915.enable_execlists, int, 0400); |
127f1003 OM |
141 | MODULE_PARM_DESC(enable_execlists, |
142 | "Override execlists usage. " | |
27401d12 | 143 | "(-1=auto [default], 0=disabled, 1=enabled)"); |
127f1003 | 144 | |
25e1793f | 145 | module_param_named_unsafe(enable_psr, i915.enable_psr, int, 0600); |
65f61b42 | 146 | MODULE_PARM_DESC(enable_psr, "Enable PSR " |
d94d6e87 RV |
147 | "(0=disabled, 1=enabled - link mode chosen per-platform, 2=force link-standby mode, 3=force link-off mode) " |
148 | "Default: -1 (use per-chip default)"); | |
d330a953 | 149 | |
1a2010ca | 150 | module_param_named_unsafe(alpha_support, i915.alpha_support, bool, 0400); |
c007fb4a JN |
151 | MODULE_PARM_DESC(alpha_support, |
152 | "Enable alpha quality driver support for latest hardware. " | |
153 | "See also CONFIG_DRM_I915_ALPHA_SUPPORT."); | |
d330a953 | 154 | |
d314cd43 | 155 | module_param_named_unsafe(disable_power_well, i915.disable_power_well, int, 0400); |
d330a953 | 156 | MODULE_PARM_DESC(disable_power_well, |
1b0e3a04 ID |
157 | "Disable display power wells when possible " |
158 | "(-1=auto [default], 0=power wells always on, 1=power wells disabled when possible)"); | |
d330a953 | 159 | |
25e1793f | 160 | module_param_named_unsafe(enable_ips, i915.enable_ips, int, 0600); |
d330a953 JN |
161 | MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)"); |
162 | ||
73831236 JN |
163 | module_param_named(fastboot, i915.fastboot, bool, 0600); |
164 | MODULE_PARM_DESC(fastboot, | |
165 | "Try to skip unnecessary mode sets at boot time (default: false)"); | |
166 | ||
5bedeb2d | 167 | module_param_named_unsafe(prefault_disable, i915.prefault_disable, bool, 0600); |
d330a953 JN |
168 | MODULE_PARM_DESC(prefault_disable, |
169 | "Disable page prefaulting for pread/pwrite/reloc (default:false). " | |
170 | "For developers only."); | |
171 | ||
5bedeb2d DV |
172 | module_param_named_unsafe(load_detect_test, i915.load_detect_test, bool, 0600); |
173 | MODULE_PARM_DESC(load_detect_test, | |
174 | "Force-enable the VGA load detect code for testing (default:false). " | |
175 | "For developers only."); | |
176 | ||
522a63de ML |
177 | module_param_named_unsafe(force_reset_modeset_test, i915.force_reset_modeset_test, bool, 0600); |
178 | MODULE_PARM_DESC(force_reset_modeset_test, | |
179 | "Force a modeset during gpu reset for testing (default:false). " | |
180 | "For developers only."); | |
181 | ||
25e1793f | 182 | module_param_named_unsafe(invert_brightness, i915.invert_brightness, int, 0600); |
d330a953 JN |
183 | MODULE_PARM_DESC(invert_brightness, |
184 | "Invert backlight brightness " | |
185 | "(-1 force normal, 0 machine defaults, 1 force inversion), please " | |
186 | "report PCI device ID, subsystem vendor and subsystem device ID " | |
187 | "to dri-devel@lists.freedesktop.org, if your machine needs it. " | |
188 | "It will then be included in an upcoming module version."); | |
a0bae57f | 189 | |
57b63d00 | 190 | module_param_named(disable_display, i915.disable_display, bool, 0400); |
a0bae57f | 191 | MODULE_PARM_DESC(disable_display, "Disable display (default: false)"); |
351e3db2 | 192 | |
41736a8e | 193 | module_param_named_unsafe(enable_cmd_parser, i915.enable_cmd_parser, bool, 0400); |
351e3db2 | 194 | MODULE_PARM_DESC(enable_cmd_parser, |
41736a8e | 195 | "Enable command parsing (true=enabled [default], false=disabled)"); |
84c33a64 | 196 | |
5a21b665 DV |
197 | module_param_named_unsafe(use_mmio_flip, i915.use_mmio_flip, int, 0600); |
198 | MODULE_PARM_DESC(use_mmio_flip, | |
199 | "use MMIO flips (-1=never, 0=driver discretion [default], 1=always)"); | |
200 | ||
48572edd | 201 | module_param_named(mmio_debug, i915.mmio_debug, int, 0600); |
5978118c | 202 | MODULE_PARM_DESC(mmio_debug, |
48572edd CW |
203 | "Enable the MMIO debug code for the first N failures (default: off). " |
204 | "This may negatively affect performance."); | |
e2c719b7 RC |
205 | |
206 | module_param_named(verbose_state_checks, i915.verbose_state_checks, bool, 0600); | |
207 | MODULE_PARM_DESC(verbose_state_checks, | |
208 | "Enable verbose logs (ie. WARN_ON()) in case of unexpected hw state conditions."); | |
b2e7723b | 209 | |
8d2b47dd | 210 | module_param_named_unsafe(nuclear_pageflip, i915.nuclear_pageflip, bool, 0400); |
c5b852f3 | 211 | MODULE_PARM_DESC(nuclear_pageflip, |
8d2b47dd | 212 | "Force enable atomic functionality on platforms that don't have full support yet."); |
c5b852f3 | 213 | |
9e458034 SJ |
214 | /* WA to get away with the default setting in VBT for early platforms.Will be removed */ |
215 | module_param_named_unsafe(edp_vswing, i915.edp_vswing, int, 0400); | |
216 | MODULE_PARM_DESC(edp_vswing, | |
217 | "Ignore/Override vswing pre-emph table selection from VBT " | |
218 | "(0=use value from vbt [default], 1=low power swing(200mV)," | |
219 | "2=default swing(400mV))"); | |
63dc0449 | 220 | |
fce91f22 DG |
221 | module_param_named_unsafe(enable_guc_loading, i915.enable_guc_loading, int, 0400); |
222 | MODULE_PARM_DESC(enable_guc_loading, | |
223 | "Enable GuC firmware loading " | |
fe993bc9 | 224 | "(-1=auto, 0=never [default], 1=if available, 2=required)"); |
fce91f22 DG |
225 | |
226 | module_param_named_unsafe(enable_guc_submission, i915.enable_guc_submission, int, 0400); | |
227 | MODULE_PARM_DESC(enable_guc_submission, | |
228 | "Enable GuC submission " | |
fe993bc9 | 229 | "(-1=auto, 0=never [default], 1=if available, 2=required)"); |
63dc0449 AD |
230 | |
231 | module_param_named(guc_log_level, i915.guc_log_level, int, 0400); | |
232 | MODULE_PARM_DESC(guc_log_level, | |
233 | "GuC firmware logging level (-1:disabled (default), 0-3:enabled)"); | |
7cc96139 | 234 | |
b3420dde AH |
235 | module_param_named_unsafe(guc_firmware_path, i915.guc_firmware_path, charp, 0400); |
236 | MODULE_PARM_DESC(guc_firmware_path, | |
237 | "GuC firmware path to use instead of the default one"); | |
238 | ||
239 | module_param_named_unsafe(huc_firmware_path, i915.huc_firmware_path, charp, 0400); | |
240 | MODULE_PARM_DESC(huc_firmware_path, | |
241 | "HuC firmware path to use instead of the default one"); | |
242 | ||
7cc96139 NS |
243 | module_param_named_unsafe(enable_dp_mst, i915.enable_dp_mst, bool, 0600); |
244 | MODULE_PARM_DESC(enable_dp_mst, | |
245 | "Enable multi-stream transport (MST) for new DisplayPort sinks. (default: true)"); | |
4fec15d1 ID |
246 | module_param_named_unsafe(inject_load_failure, i915.inject_load_failure, uint, 0400); |
247 | MODULE_PARM_DESC(inject_load_failure, | |
248 | "Force an error after a number of failure check points (0:disabled (default), N:force failure at the Nth failure check point)"); | |
e7156c83 YA |
249 | module_param_named(enable_dpcd_backlight, i915.enable_dpcd_backlight, bool, 0600); |
250 | MODULE_PARM_DESC(enable_dpcd_backlight, | |
251 | "Enable support for DPCD backlight control (default:false)"); | |
0ad35fed | 252 | |
77ca04cc | 253 | module_param_named(enable_gvt, i915.enable_gvt, bool, 0400); |
0ad35fed ZW |
254 | MODULE_PARM_DESC(enable_gvt, |
255 | "Enable support for Intel GVT-g graphics virtualization host support(default:false)"); |