]>
Commit | Line | Data |
---|---|---|
42f5551d CW |
1 | /* |
2 | * Copyright © 2016 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
a09d0ba1 | 25 | #include <linux/console.h> |
42f5551d CW |
26 | #include <linux/vgaarb.h> |
27 | #include <linux/vga_switcheroo.h> | |
28 | ||
29 | #include "i915_drv.h" | |
953c7f82 | 30 | #include "i915_selftest.h" |
42f5551d CW |
31 | |
32 | #define GEN_DEFAULT_PIPEOFFSETS \ | |
33 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ | |
34 | PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \ | |
35 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ | |
36 | TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \ | |
37 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET } | |
38 | ||
39 | #define GEN_CHV_PIPEOFFSETS \ | |
40 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ | |
41 | CHV_PIPE_C_OFFSET }, \ | |
42 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ | |
43 | CHV_TRANSCODER_C_OFFSET, }, \ | |
44 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \ | |
45 | CHV_PALETTE_C_OFFSET } | |
46 | ||
47 | #define CURSOR_OFFSETS \ | |
48 | .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET } | |
49 | ||
50 | #define IVB_CURSOR_OFFSETS \ | |
51 | .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } | |
52 | ||
53 | #define BDW_COLORS \ | |
54 | .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 } | |
55 | #define CHV_COLORS \ | |
56 | .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 } | |
57 | ||
a5ce929b | 58 | /* Keep in gen based order, and chronological order within a gen */ |
0eec8dc7 CS |
59 | #define GEN2_FEATURES \ |
60 | .gen = 2, .num_pipes = 1, \ | |
61 | .has_overlay = 1, .overlay_needs_physical = 1, \ | |
804b8712 | 62 | .has_gmch_display = 1, \ |
3177659a | 63 | .hws_needs_physical = 1, \ |
f4ce766f | 64 | .unfenced_needs_alignment = 1, \ |
0eec8dc7 CS |
65 | .ring_mask = RENDER_RING, \ |
66 | GEN_DEFAULT_PIPEOFFSETS, \ | |
67 | CURSOR_OFFSETS | |
68 | ||
42f5551d | 69 | static const struct intel_device_info intel_i830_info = { |
0eec8dc7 | 70 | GEN2_FEATURES, |
2e0d26f8 | 71 | .platform = INTEL_I830, |
0eec8dc7 CS |
72 | .is_mobile = 1, .cursor_needs_physical = 1, |
73 | .num_pipes = 2, /* legal, last one wins */ | |
42f5551d CW |
74 | }; |
75 | ||
2a307c2e | 76 | static const struct intel_device_info intel_i845g_info = { |
0eec8dc7 | 77 | GEN2_FEATURES, |
2e0d26f8 | 78 | .platform = INTEL_I845G, |
42f5551d CW |
79 | }; |
80 | ||
81 | static const struct intel_device_info intel_i85x_info = { | |
0eec8dc7 | 82 | GEN2_FEATURES, |
2e0d26f8 | 83 | .platform = INTEL_I85X, .is_mobile = 1, |
0eec8dc7 | 84 | .num_pipes = 2, /* legal, last one wins */ |
42f5551d | 85 | .cursor_needs_physical = 1, |
42f5551d | 86 | .has_fbc = 1, |
42f5551d CW |
87 | }; |
88 | ||
89 | static const struct intel_device_info intel_i865g_info = { | |
0eec8dc7 | 90 | GEN2_FEATURES, |
2e0d26f8 | 91 | .platform = INTEL_I865G, |
42f5551d CW |
92 | }; |
93 | ||
54d2a6a1 CS |
94 | #define GEN3_FEATURES \ |
95 | .gen = 3, .num_pipes = 2, \ | |
804b8712 | 96 | .has_gmch_display = 1, \ |
54d2a6a1 CS |
97 | .ring_mask = RENDER_RING, \ |
98 | GEN_DEFAULT_PIPEOFFSETS, \ | |
99 | CURSOR_OFFSETS | |
100 | ||
42f5551d | 101 | static const struct intel_device_info intel_i915g_info = { |
54d2a6a1 | 102 | GEN3_FEATURES, |
2e0d26f8 | 103 | .platform = INTEL_I915G, .cursor_needs_physical = 1, |
42f5551d | 104 | .has_overlay = 1, .overlay_needs_physical = 1, |
3177659a | 105 | .hws_needs_physical = 1, |
f4ce766f | 106 | .unfenced_needs_alignment = 1, |
42f5551d | 107 | }; |
a5ce929b | 108 | |
42f5551d | 109 | static const struct intel_device_info intel_i915gm_info = { |
54d2a6a1 | 110 | GEN3_FEATURES, |
2e0d26f8 | 111 | .platform = INTEL_I915GM, |
54d2a6a1 | 112 | .is_mobile = 1, |
42f5551d CW |
113 | .cursor_needs_physical = 1, |
114 | .has_overlay = 1, .overlay_needs_physical = 1, | |
115 | .supports_tv = 1, | |
116 | .has_fbc = 1, | |
3177659a | 117 | .hws_needs_physical = 1, |
f4ce766f | 118 | .unfenced_needs_alignment = 1, |
42f5551d | 119 | }; |
a5ce929b | 120 | |
42f5551d | 121 | static const struct intel_device_info intel_i945g_info = { |
54d2a6a1 | 122 | GEN3_FEATURES, |
2e0d26f8 | 123 | .platform = INTEL_I945G, |
54d2a6a1 | 124 | .has_hotplug = 1, .cursor_needs_physical = 1, |
42f5551d | 125 | .has_overlay = 1, .overlay_needs_physical = 1, |
3177659a | 126 | .hws_needs_physical = 1, |
f4ce766f | 127 | .unfenced_needs_alignment = 1, |
42f5551d | 128 | }; |
a5ce929b | 129 | |
42f5551d | 130 | static const struct intel_device_info intel_i945gm_info = { |
54d2a6a1 | 131 | GEN3_FEATURES, |
2e0d26f8 | 132 | .platform = INTEL_I945GM, .is_mobile = 1, |
42f5551d CW |
133 | .has_hotplug = 1, .cursor_needs_physical = 1, |
134 | .has_overlay = 1, .overlay_needs_physical = 1, | |
135 | .supports_tv = 1, | |
136 | .has_fbc = 1, | |
3177659a | 137 | .hws_needs_physical = 1, |
f4ce766f | 138 | .unfenced_needs_alignment = 1, |
42f5551d CW |
139 | }; |
140 | ||
a5ce929b JN |
141 | static const struct intel_device_info intel_g33_info = { |
142 | GEN3_FEATURES, | |
143 | .platform = INTEL_G33, | |
144 | .has_hotplug = 1, | |
145 | .has_overlay = 1, | |
146 | }; | |
147 | ||
148 | static const struct intel_device_info intel_pineview_info = { | |
149 | GEN3_FEATURES, | |
73f67aa8 | 150 | .platform = INTEL_PINEVIEW, .is_mobile = 1, |
a5ce929b JN |
151 | .has_hotplug = 1, |
152 | .has_overlay = 1, | |
153 | }; | |
154 | ||
4d495bea CS |
155 | #define GEN4_FEATURES \ |
156 | .gen = 4, .num_pipes = 2, \ | |
157 | .has_hotplug = 1, \ | |
804b8712 | 158 | .has_gmch_display = 1, \ |
4d495bea CS |
159 | .ring_mask = RENDER_RING, \ |
160 | GEN_DEFAULT_PIPEOFFSETS, \ | |
161 | CURSOR_OFFSETS | |
162 | ||
42f5551d | 163 | static const struct intel_device_info intel_i965g_info = { |
4d495bea | 164 | GEN4_FEATURES, |
c0f86832 | 165 | .platform = INTEL_I965G, |
42f5551d | 166 | .has_overlay = 1, |
3177659a | 167 | .hws_needs_physical = 1, |
42f5551d CW |
168 | }; |
169 | ||
170 | static const struct intel_device_info intel_i965gm_info = { | |
4d495bea | 171 | GEN4_FEATURES, |
c0f86832 | 172 | .platform = INTEL_I965GM, |
4d495bea | 173 | .is_mobile = 1, .has_fbc = 1, |
42f5551d CW |
174 | .has_overlay = 1, |
175 | .supports_tv = 1, | |
3177659a | 176 | .hws_needs_physical = 1, |
42f5551d CW |
177 | }; |
178 | ||
42f5551d | 179 | static const struct intel_device_info intel_g45_info = { |
4d495bea | 180 | GEN4_FEATURES, |
f69c11ae | 181 | .platform = INTEL_G45, |
4d495bea | 182 | .has_pipe_cxsr = 1, |
42f5551d | 183 | .ring_mask = RENDER_RING | BSD_RING, |
42f5551d CW |
184 | }; |
185 | ||
186 | static const struct intel_device_info intel_gm45_info = { | |
4d495bea | 187 | GEN4_FEATURES, |
f69c11ae | 188 | .platform = INTEL_GM45, |
3177659a | 189 | .is_mobile = 1, .has_fbc = 1, |
4d495bea | 190 | .has_pipe_cxsr = 1, |
42f5551d CW |
191 | .supports_tv = 1, |
192 | .ring_mask = RENDER_RING | BSD_RING, | |
42f5551d CW |
193 | }; |
194 | ||
a1323380 CS |
195 | #define GEN5_FEATURES \ |
196 | .gen = 5, .num_pipes = 2, \ | |
3177659a | 197 | .has_hotplug = 1, \ |
b355f109 | 198 | .has_gmbus_irq = 1, \ |
a1323380 CS |
199 | .ring_mask = RENDER_RING | BSD_RING, \ |
200 | GEN_DEFAULT_PIPEOFFSETS, \ | |
201 | CURSOR_OFFSETS | |
202 | ||
42f5551d | 203 | static const struct intel_device_info intel_ironlake_d_info = { |
a1323380 | 204 | GEN5_FEATURES, |
2e0d26f8 | 205 | .platform = INTEL_IRONLAKE, |
42f5551d CW |
206 | }; |
207 | ||
208 | static const struct intel_device_info intel_ironlake_m_info = { | |
a1323380 | 209 | GEN5_FEATURES, |
2e0d26f8 | 210 | .platform = INTEL_IRONLAKE, |
c2d1a0ce | 211 | .is_mobile = 1, .has_fbc = 1, |
42f5551d CW |
212 | }; |
213 | ||
07db6be7 CS |
214 | #define GEN6_FEATURES \ |
215 | .gen = 6, .num_pipes = 2, \ | |
3177659a | 216 | .has_hotplug = 1, \ |
07db6be7 CS |
217 | .has_fbc = 1, \ |
218 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ | |
219 | .has_llc = 1, \ | |
86f3624b | 220 | .has_rc6 = 1, \ |
33b5bf82 | 221 | .has_rc6p = 1, \ |
b355f109 | 222 | .has_gmbus_irq = 1, \ |
9e1d0e60 | 223 | .has_aliasing_ppgtt = 1, \ |
07db6be7 CS |
224 | GEN_DEFAULT_PIPEOFFSETS, \ |
225 | CURSOR_OFFSETS | |
226 | ||
0890540e LL |
227 | #define SNB_D_PLATFORM \ |
228 | GEN6_FEATURES, \ | |
229 | .platform = INTEL_SANDYBRIDGE | |
230 | ||
231 | static const struct intel_device_info intel_sandybridge_d_gt1_info = { | |
232 | SNB_D_PLATFORM, | |
233 | .gt = 1, | |
42f5551d CW |
234 | }; |
235 | ||
0890540e LL |
236 | static const struct intel_device_info intel_sandybridge_d_gt2_info = { |
237 | SNB_D_PLATFORM, | |
238 | .gt = 2, | |
239 | }; | |
240 | ||
241 | #define SNB_M_PLATFORM \ | |
242 | GEN6_FEATURES, \ | |
243 | .platform = INTEL_SANDYBRIDGE, \ | |
244 | .is_mobile = 1 | |
245 | ||
246 | ||
247 | static const struct intel_device_info intel_sandybridge_m_gt1_info = { | |
248 | SNB_M_PLATFORM, | |
249 | .gt = 1, | |
250 | }; | |
251 | ||
252 | static const struct intel_device_info intel_sandybridge_m_gt2_info = { | |
253 | SNB_M_PLATFORM, | |
254 | .gt = 2, | |
42f5551d CW |
255 | }; |
256 | ||
257 | #define GEN7_FEATURES \ | |
258 | .gen = 7, .num_pipes = 3, \ | |
3177659a | 259 | .has_hotplug = 1, \ |
42f5551d CW |
260 | .has_fbc = 1, \ |
261 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ | |
262 | .has_llc = 1, \ | |
86f3624b | 263 | .has_rc6 = 1, \ |
33b5bf82 | 264 | .has_rc6p = 1, \ |
b355f109 | 265 | .has_gmbus_irq = 1, \ |
9e1d0e60 MT |
266 | .has_aliasing_ppgtt = 1, \ |
267 | .has_full_ppgtt = 1, \ | |
42f5551d CW |
268 | GEN_DEFAULT_PIPEOFFSETS, \ |
269 | IVB_CURSOR_OFFSETS | |
270 | ||
0890540e LL |
271 | #define IVB_D_PLATFORM \ |
272 | GEN7_FEATURES, \ | |
273 | .platform = INTEL_IVYBRIDGE, \ | |
274 | .has_l3_dpf = 1 | |
275 | ||
276 | static const struct intel_device_info intel_ivybridge_d_gt1_info = { | |
277 | IVB_D_PLATFORM, | |
278 | .gt = 1, | |
42f5551d CW |
279 | }; |
280 | ||
0890540e LL |
281 | static const struct intel_device_info intel_ivybridge_d_gt2_info = { |
282 | IVB_D_PLATFORM, | |
283 | .gt = 2, | |
284 | }; | |
285 | ||
286 | #define IVB_M_PLATFORM \ | |
287 | GEN7_FEATURES, \ | |
288 | .platform = INTEL_IVYBRIDGE, \ | |
289 | .is_mobile = 1, \ | |
290 | .has_l3_dpf = 1 | |
291 | ||
292 | static const struct intel_device_info intel_ivybridge_m_gt1_info = { | |
293 | IVB_M_PLATFORM, | |
294 | .gt = 1, | |
295 | }; | |
296 | ||
297 | static const struct intel_device_info intel_ivybridge_m_gt2_info = { | |
298 | IVB_M_PLATFORM, | |
299 | .gt = 2, | |
42f5551d CW |
300 | }; |
301 | ||
302 | static const struct intel_device_info intel_ivybridge_q_info = { | |
303 | GEN7_FEATURES, | |
2e0d26f8 | 304 | .platform = INTEL_IVYBRIDGE, |
0890540e | 305 | .gt = 2, |
42f5551d | 306 | .num_pipes = 0, /* legal, last one wins */ |
ca9c4523 | 307 | .has_l3_dpf = 1, |
42f5551d CW |
308 | }; |
309 | ||
8d9c20e1 | 310 | static const struct intel_device_info intel_valleyview_info = { |
2e0d26f8 | 311 | .platform = INTEL_VALLEYVIEW, |
eb6f771b RV |
312 | .gen = 7, |
313 | .is_lp = 1, | |
314 | .num_pipes = 2, | |
315 | .has_psr = 1, | |
316 | .has_runtime_pm = 1, | |
317 | .has_rc6 = 1, | |
318 | .has_gmbus_irq = 1, | |
eb6f771b RV |
319 | .has_gmch_display = 1, |
320 | .has_hotplug = 1, | |
321 | .has_aliasing_ppgtt = 1, | |
322 | .has_full_ppgtt = 1, | |
323 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, | |
324 | .display_mmio_offset = VLV_DISPLAY_BASE, | |
325 | GEN_DEFAULT_PIPEOFFSETS, | |
326 | CURSOR_OFFSETS | |
42f5551d CW |
327 | }; |
328 | ||
329 | #define HSW_FEATURES \ | |
330 | GEN7_FEATURES, \ | |
331 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ | |
332 | .has_ddi = 1, \ | |
6e3b84d8 | 333 | .has_fpga_dbg = 1, \ |
4aa4c23f | 334 | .has_psr = 1, \ |
53233f08 | 335 | .has_resource_streamer = 1, \ |
1d3fe53b | 336 | .has_dp_mst = 1, \ |
33b5bf82 | 337 | .has_rc6p = 0 /* RC6p removed-by HSW */, \ |
4aa4c23f | 338 | .has_runtime_pm = 1 |
42f5551d | 339 | |
0890540e LL |
340 | #define HSW_PLATFORM \ |
341 | HSW_FEATURES, \ | |
342 | .platform = INTEL_HASWELL, \ | |
343 | .has_l3_dpf = 1 | |
344 | ||
345 | static const struct intel_device_info intel_haswell_gt1_info = { | |
346 | HSW_PLATFORM, | |
347 | .gt = 1, | |
348 | }; | |
349 | ||
350 | static const struct intel_device_info intel_haswell_gt2_info = { | |
351 | HSW_PLATFORM, | |
352 | .gt = 2, | |
353 | }; | |
354 | ||
355 | static const struct intel_device_info intel_haswell_gt3_info = { | |
356 | HSW_PLATFORM, | |
357 | .gt = 3, | |
42f5551d CW |
358 | }; |
359 | ||
42f5551d CW |
360 | #define BDW_FEATURES \ |
361 | HSW_FEATURES, \ | |
4586f1d0 | 362 | BDW_COLORS, \ |
dfc5148f | 363 | .has_logical_ring_contexts = 1, \ |
9e1d0e60 | 364 | .has_full_48bit_ppgtt = 1, \ |
142bc7d9 MT |
365 | .has_64bit_reloc = 1, \ |
366 | .has_reset_engine = 1 | |
42f5551d | 367 | |
94829de4 RV |
368 | #define BDW_PLATFORM \ |
369 | BDW_FEATURES, \ | |
370 | .gen = 8, \ | |
371 | .platform = INTEL_BROADWELL | |
372 | ||
0890540e LL |
373 | static const struct intel_device_info intel_broadwell_gt1_info = { |
374 | BDW_PLATFORM, | |
375 | .gt = 1, | |
376 | }; | |
377 | ||
378 | static const struct intel_device_info intel_broadwell_gt2_info = { | |
94829de4 | 379 | BDW_PLATFORM, |
0890540e LL |
380 | .gt = 2, |
381 | }; | |
382 | ||
383 | static const struct intel_device_info intel_broadwell_rsvd_info = { | |
384 | BDW_PLATFORM, | |
385 | .gt = 3, | |
386 | /* According to the device ID those devices are GT3, they were | |
387 | * previously treated as not GT3, keep it like that. | |
388 | */ | |
42f5551d CW |
389 | }; |
390 | ||
8d9c20e1 | 391 | static const struct intel_device_info intel_broadwell_gt3_info = { |
94829de4 | 392 | BDW_PLATFORM, |
0890540e | 393 | .gt = 3, |
42f5551d CW |
394 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
395 | }; | |
396 | ||
42f5551d CW |
397 | static const struct intel_device_info intel_cherryview_info = { |
398 | .gen = 8, .num_pipes = 3, | |
3177659a | 399 | .has_hotplug = 1, |
8727dc09 | 400 | .is_lp = 1, |
42f5551d | 401 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
2e0d26f8 | 402 | .platform = INTEL_CHERRYVIEW, |
dfc5148f | 403 | .has_64bit_reloc = 1, |
6e3b84d8 | 404 | .has_psr = 1, |
4aa4c23f | 405 | .has_runtime_pm = 1, |
53233f08 | 406 | .has_resource_streamer = 1, |
86f3624b | 407 | .has_rc6 = 1, |
b355f109 | 408 | .has_gmbus_irq = 1, |
4586f1d0 | 409 | .has_logical_ring_contexts = 1, |
804b8712 | 410 | .has_gmch_display = 1, |
9e1d0e60 MT |
411 | .has_aliasing_ppgtt = 1, |
412 | .has_full_ppgtt = 1, | |
142bc7d9 | 413 | .has_reset_engine = 1, |
42f5551d CW |
414 | .display_mmio_offset = VLV_DISPLAY_BASE, |
415 | GEN_CHV_PIPEOFFSETS, | |
416 | CURSOR_OFFSETS, | |
417 | CHV_COLORS, | |
418 | }; | |
419 | ||
94829de4 RV |
420 | #define SKL_PLATFORM \ |
421 | BDW_FEATURES, \ | |
422 | .gen = 9, \ | |
423 | .platform = INTEL_SKYLAKE, \ | |
424 | .has_csr = 1, \ | |
425 | .has_guc = 1, \ | |
426 | .ddb_size = 896 | |
427 | ||
0890540e | 428 | static const struct intel_device_info intel_skylake_gt1_info = { |
94829de4 | 429 | SKL_PLATFORM, |
0890540e | 430 | .gt = 1, |
42f5551d CW |
431 | }; |
432 | ||
0890540e | 433 | static const struct intel_device_info intel_skylake_gt2_info = { |
94829de4 | 434 | SKL_PLATFORM, |
0890540e LL |
435 | .gt = 2, |
436 | }; | |
437 | ||
438 | #define SKL_GT3_PLUS_PLATFORM \ | |
439 | SKL_PLATFORM, \ | |
440 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING | |
441 | ||
442 | ||
443 | static const struct intel_device_info intel_skylake_gt3_info = { | |
444 | SKL_GT3_PLUS_PLATFORM, | |
445 | .gt = 3, | |
446 | }; | |
447 | ||
448 | static const struct intel_device_info intel_skylake_gt4_info = { | |
449 | SKL_GT3_PLUS_PLATFORM, | |
450 | .gt = 4, | |
42f5551d CW |
451 | }; |
452 | ||
80fa66b6 RV |
453 | #define GEN9_LP_FEATURES \ |
454 | .gen = 9, \ | |
3e4274f8 | 455 | .is_lp = 1, \ |
80fa66b6 RV |
456 | .has_hotplug = 1, \ |
457 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ | |
458 | .num_pipes = 3, \ | |
459 | .has_64bit_reloc = 1, \ | |
460 | .has_ddi = 1, \ | |
461 | .has_fpga_dbg = 1, \ | |
462 | .has_fbc = 1, \ | |
463 | .has_runtime_pm = 1, \ | |
464 | .has_pooled_eu = 0, \ | |
465 | .has_csr = 1, \ | |
466 | .has_resource_streamer = 1, \ | |
467 | .has_rc6 = 1, \ | |
468 | .has_dp_mst = 1, \ | |
469 | .has_gmbus_irq = 1, \ | |
80fa66b6 RV |
470 | .has_logical_ring_contexts = 1, \ |
471 | .has_guc = 1, \ | |
9e1d0e60 MT |
472 | .has_aliasing_ppgtt = 1, \ |
473 | .has_full_ppgtt = 1, \ | |
474 | .has_full_48bit_ppgtt = 1, \ | |
142bc7d9 | 475 | .has_reset_engine = 1, \ |
80fa66b6 RV |
476 | GEN_DEFAULT_PIPEOFFSETS, \ |
477 | IVB_CURSOR_OFFSETS, \ | |
478 | BDW_COLORS | |
479 | ||
42f5551d | 480 | static const struct intel_device_info intel_broxton_info = { |
80fa66b6 | 481 | GEN9_LP_FEATURES, |
2e0d26f8 | 482 | .platform = INTEL_BROXTON, |
6f3fff60 | 483 | .ddb_size = 512, |
42f5551d CW |
484 | }; |
485 | ||
c22097fa | 486 | static const struct intel_device_info intel_geminilake_info = { |
c22097fa | 487 | GEN9_LP_FEATURES, |
2e0d26f8 | 488 | .platform = INTEL_GEMINILAKE, |
c22097fa | 489 | .ddb_size = 1024, |
9751bafc | 490 | .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 } |
c22097fa ACO |
491 | }; |
492 | ||
94829de4 RV |
493 | #define KBL_PLATFORM \ |
494 | BDW_FEATURES, \ | |
495 | .gen = 9, \ | |
496 | .platform = INTEL_KABYLAKE, \ | |
497 | .has_csr = 1, \ | |
498 | .has_guc = 1, \ | |
499 | .ddb_size = 896 | |
500 | ||
0890540e | 501 | static const struct intel_device_info intel_kabylake_gt1_info = { |
94829de4 | 502 | KBL_PLATFORM, |
0890540e LL |
503 | .gt = 1, |
504 | }; | |
505 | ||
506 | static const struct intel_device_info intel_kabylake_gt2_info = { | |
507 | KBL_PLATFORM, | |
508 | .gt = 2, | |
42f5551d CW |
509 | }; |
510 | ||
511 | static const struct intel_device_info intel_kabylake_gt3_info = { | |
94829de4 | 512 | KBL_PLATFORM, |
0890540e | 513 | .gt = 3, |
42f5551d CW |
514 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
515 | }; | |
516 | ||
71851fa8 RV |
517 | #define CFL_PLATFORM \ |
518 | .is_alpha_support = 1, \ | |
519 | BDW_FEATURES, \ | |
520 | .gen = 9, \ | |
521 | .platform = INTEL_COFFEELAKE, \ | |
84cd843e | 522 | .has_csr = 1, \ |
c0f82960 | 523 | .has_guc = 1, \ |
71851fa8 RV |
524 | .ddb_size = 896 |
525 | ||
0890540e LL |
526 | static const struct intel_device_info intel_coffeelake_gt1_info = { |
527 | CFL_PLATFORM, | |
528 | .gt = 1, | |
529 | }; | |
530 | ||
531 | static const struct intel_device_info intel_coffeelake_gt2_info = { | |
71851fa8 | 532 | CFL_PLATFORM, |
0890540e | 533 | .gt = 2, |
71851fa8 RV |
534 | }; |
535 | ||
536 | static const struct intel_device_info intel_coffeelake_gt3_info = { | |
537 | CFL_PLATFORM, | |
0890540e | 538 | .gt = 3, |
71851fa8 RV |
539 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
540 | }; | |
541 | ||
0890540e | 542 | static const struct intel_device_info intel_cannonlake_gt2_info = { |
413f3c19 RV |
543 | BDW_FEATURES, |
544 | .is_alpha_support = 1, | |
545 | .platform = INTEL_CANNONLAKE, | |
546 | .gen = 10, | |
0890540e | 547 | .gt = 2, |
413f3c19 | 548 | .ddb_size = 1024, |
cebfcead | 549 | .has_csr = 1, |
6602be0e | 550 | .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 } |
413f3c19 RV |
551 | }; |
552 | ||
42f5551d CW |
553 | /* |
554 | * Make sure any device matches here are from most specific to most | |
555 | * general. For example, since the Quanta match is based on the subsystem | |
556 | * and subvendor IDs, we need it to come before the more general IVB | |
557 | * PCI ID matches, otherwise we'll use the wrong info struct above. | |
558 | */ | |
559 | static const struct pci_device_id pciidlist[] = { | |
560 | INTEL_I830_IDS(&intel_i830_info), | |
2a307c2e | 561 | INTEL_I845G_IDS(&intel_i845g_info), |
42f5551d CW |
562 | INTEL_I85X_IDS(&intel_i85x_info), |
563 | INTEL_I865G_IDS(&intel_i865g_info), | |
564 | INTEL_I915G_IDS(&intel_i915g_info), | |
565 | INTEL_I915GM_IDS(&intel_i915gm_info), | |
566 | INTEL_I945G_IDS(&intel_i945g_info), | |
567 | INTEL_I945GM_IDS(&intel_i945gm_info), | |
568 | INTEL_I965G_IDS(&intel_i965g_info), | |
569 | INTEL_G33_IDS(&intel_g33_info), | |
570 | INTEL_I965GM_IDS(&intel_i965gm_info), | |
571 | INTEL_GM45_IDS(&intel_gm45_info), | |
572 | INTEL_G45_IDS(&intel_g45_info), | |
573 | INTEL_PINEVIEW_IDS(&intel_pineview_info), | |
574 | INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), | |
575 | INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), | |
0890540e LL |
576 | INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info), |
577 | INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info), | |
578 | INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info), | |
579 | INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info), | |
42f5551d | 580 | INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ |
0890540e LL |
581 | INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info), |
582 | INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info), | |
583 | INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info), | |
584 | INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info), | |
585 | INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info), | |
586 | INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info), | |
587 | INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info), | |
8d9c20e1 | 588 | INTEL_VLV_IDS(&intel_valleyview_info), |
0890540e LL |
589 | INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info), |
590 | INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info), | |
8d9c20e1 | 591 | INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info), |
0890540e | 592 | INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info), |
42f5551d | 593 | INTEL_CHV_IDS(&intel_cherryview_info), |
0890540e LL |
594 | INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info), |
595 | INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info), | |
42f5551d | 596 | INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), |
0890540e | 597 | INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info), |
42f5551d | 598 | INTEL_BXT_IDS(&intel_broxton_info), |
8363e3c3 | 599 | INTEL_GLK_IDS(&intel_geminilake_info), |
0890540e LL |
600 | INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info), |
601 | INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info), | |
42f5551d CW |
602 | INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info), |
603 | INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info), | |
0890540e LL |
604 | INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info), |
605 | INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info), | |
606 | INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info), | |
607 | INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info), | |
608 | INTEL_CNL_U_GT2_IDS(&intel_cannonlake_gt2_info), | |
609 | INTEL_CNL_Y_GT2_IDS(&intel_cannonlake_gt2_info), | |
42f5551d CW |
610 | {0, 0, 0} |
611 | }; | |
612 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
613 | ||
953c7f82 CW |
614 | static void i915_pci_remove(struct pci_dev *pdev) |
615 | { | |
616 | struct drm_device *dev = pci_get_drvdata(pdev); | |
617 | ||
618 | i915_driver_unload(dev); | |
619 | drm_dev_unref(dev); | |
620 | } | |
621 | ||
42f5551d CW |
622 | static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
623 | { | |
624 | struct intel_device_info *intel_info = | |
625 | (struct intel_device_info *) ent->driver_data; | |
953c7f82 | 626 | int err; |
42f5551d | 627 | |
c007fb4a JN |
628 | if (IS_ALPHA_SUPPORT(intel_info) && !i915.alpha_support) { |
629 | DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n" | |
630 | "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n" | |
631 | "to enable support in this kernel version, or check for kernel updates.\n"); | |
42f5551d CW |
632 | return -ENODEV; |
633 | } | |
634 | ||
635 | /* Only bind to function 0 of the device. Early generations | |
636 | * used function 1 as a placeholder for multi-head. This causes | |
637 | * us confusion instead, especially on the systems where both | |
638 | * functions have the same PCI-ID! | |
639 | */ | |
640 | if (PCI_FUNC(pdev->devfn)) | |
641 | return -ENODEV; | |
642 | ||
643 | /* | |
644 | * apple-gmux is needed on dual GPU MacBook Pro | |
645 | * to probe the panel if we're the inactive GPU. | |
646 | */ | |
647 | if (vga_switcheroo_client_probe_defer(pdev)) | |
648 | return -EPROBE_DEFER; | |
649 | ||
953c7f82 CW |
650 | err = i915_driver_load(pdev, ent); |
651 | if (err) | |
652 | return err; | |
42f5551d | 653 | |
953c7f82 CW |
654 | err = i915_live_selftests(pdev); |
655 | if (err) { | |
656 | i915_pci_remove(pdev); | |
657 | return err > 0 ? -ENOTTY : err; | |
658 | } | |
42f5551d | 659 | |
953c7f82 | 660 | return 0; |
42f5551d CW |
661 | } |
662 | ||
a09d0ba1 | 663 | static struct pci_driver i915_pci_driver = { |
42f5551d CW |
664 | .name = DRIVER_NAME, |
665 | .id_table = pciidlist, | |
666 | .probe = i915_pci_probe, | |
667 | .remove = i915_pci_remove, | |
668 | .driver.pm = &i915_pm_ops, | |
669 | }; | |
a09d0ba1 CW |
670 | |
671 | static int __init i915_init(void) | |
672 | { | |
673 | bool use_kms = true; | |
953c7f82 CW |
674 | int err; |
675 | ||
676 | err = i915_mock_selftests(); | |
677 | if (err) | |
678 | return err > 0 ? 0 : err; | |
a09d0ba1 CW |
679 | |
680 | /* | |
681 | * Enable KMS by default, unless explicitly overriden by | |
682 | * either the i915.modeset prarameter or by the | |
683 | * vga_text_mode_force boot option. | |
684 | */ | |
685 | ||
686 | if (i915.modeset == 0) | |
687 | use_kms = false; | |
688 | ||
689 | if (vgacon_text_force() && i915.modeset == -1) | |
690 | use_kms = false; | |
691 | ||
692 | if (!use_kms) { | |
693 | /* Silently fail loading to not upset userspace. */ | |
694 | DRM_DEBUG_DRIVER("KMS disabled.\n"); | |
695 | return 0; | |
696 | } | |
697 | ||
698 | return pci_register_driver(&i915_pci_driver); | |
699 | } | |
700 | ||
701 | static void __exit i915_exit(void) | |
702 | { | |
703 | if (!i915_pci_driver.driver.owner) | |
704 | return; | |
705 | ||
706 | pci_unregister_driver(&i915_pci_driver); | |
707 | } | |
708 | ||
709 | module_init(i915_init); | |
710 | module_exit(i915_exit); | |
711 | ||
712 | MODULE_AUTHOR("Tungsten Graphics, Inc."); | |
713 | MODULE_AUTHOR("Intel Corporation"); | |
714 | ||
715 | MODULE_DESCRIPTION(DRIVER_DESC); | |
716 | MODULE_LICENSE("GPL and additional rights"); |