[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / i915_pci.c

/*
 * Copyright © 2016 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 */

#include <linux/console.h>
#include <linux/vgaarb.h>
#include <linux/vga_switcheroo.h>

#include "i915_drv.h"

#define GEN_DEFAULT_PIPEOFFSETS \
	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
			  PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
			   TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }

#define GEN_CHV_PIPEOFFSETS \
	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
			  CHV_PIPE_C_OFFSET }, \
	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
			   CHV_TRANSCODER_C_OFFSET, }, \
	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
			     CHV_PALETTE_C_OFFSET }

#define CURSOR_OFFSETS \
	.cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }

#define IVB_CURSOR_OFFSETS \
	.cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }

#define BDW_COLORS \
	.color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
#define CHV_COLORS \
	.color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }

/* Keep in gen based order, and chronological order within a gen */
#define GEN2_FEATURES \
	.gen = 2, .num_pipes = 1, \
	.has_overlay = 1, .overlay_needs_physical = 1, \
	.has_gmch_display = 1, \
	.hws_needs_physical = 1, \
	.ring_mask = RENDER_RING, \
	GEN_DEFAULT_PIPEOFFSETS, \
	CURSOR_OFFSETS

static const struct intel_device_info intel_i830_info = {
	GEN2_FEATURES,
	.platform = INTEL_I830,
	.is_mobile = 1, .cursor_needs_physical = 1,
	.num_pipes = 2, /* legal, last one wins */
};

static const struct intel_device_info intel_i845g_info = {
	GEN2_FEATURES,
	.platform = INTEL_I845G,
};

static const struct intel_device_info intel_i85x_info = {
	GEN2_FEATURES,
	.platform = INTEL_I85X, .is_mobile = 1,
	.num_pipes = 2, /* legal, last one wins */
	.cursor_needs_physical = 1,
	.has_fbc = 1,
};

static const struct intel_device_info intel_i865g_info = {
	GEN2_FEATURES,
	.platform = INTEL_I865G,
};

#define GEN3_FEATURES \
	.gen = 3, .num_pipes = 2, \
	.has_gmch_display = 1, \
	.ring_mask = RENDER_RING, \
	GEN_DEFAULT_PIPEOFFSETS, \
	CURSOR_OFFSETS

static const struct intel_device_info intel_i915g_info = {
	GEN3_FEATURES,
	.platform = INTEL_I915G, .cursor_needs_physical = 1,
	.has_overlay = 1, .overlay_needs_physical = 1,
	.hws_needs_physical = 1,
};

static const struct intel_device_info intel_i915gm_info = {
	GEN3_FEATURES,
	.platform = INTEL_I915GM,
	.is_mobile = 1,
	.cursor_needs_physical = 1,
	.has_overlay = 1, .overlay_needs_physical = 1,
	.supports_tv = 1,
	.has_fbc = 1,
	.hws_needs_physical = 1,
};

static const struct intel_device_info intel_i945g_info = {
	GEN3_FEATURES,
	.platform = INTEL_I945G,
	.has_hotplug = 1, .cursor_needs_physical = 1,
	.has_overlay = 1, .overlay_needs_physical = 1,
	.hws_needs_physical = 1,
};

static const struct intel_device_info intel_i945gm_info = {
	GEN3_FEATURES,
	.platform = INTEL_I945GM, .is_mobile = 1,
	.has_hotplug = 1, .cursor_needs_physical = 1,
	.has_overlay = 1, .overlay_needs_physical = 1,
	.supports_tv = 1,
	.has_fbc = 1,
	.hws_needs_physical = 1,
};

static const struct intel_device_info intel_g33_info = {
	GEN3_FEATURES,
	.platform = INTEL_G33,
	.has_hotplug = 1,
	.has_overlay = 1,
};

static const struct intel_device_info intel_pineview_info = {
	GEN3_FEATURES,
	.platform = INTEL_G33, .is_pineview = 1, .is_mobile = 1,
	.has_hotplug = 1,
	.has_overlay = 1,
};

#define GEN4_FEATURES \
	.gen = 4, .num_pipes = 2, \
	.has_hotplug = 1, \
	.has_gmch_display = 1, \
	.ring_mask = RENDER_RING, \
	GEN_DEFAULT_PIPEOFFSETS, \
	CURSOR_OFFSETS

static const struct intel_device_info intel_i965g_info = {
	GEN4_FEATURES,
	.platform = INTEL_I965G,
	.has_overlay = 1,
	.hws_needs_physical = 1,
};

static const struct intel_device_info intel_i965gm_info = {
	GEN4_FEATURES,
	.platform = INTEL_I965GM,
	.is_mobile = 1, .has_fbc = 1,
	.has_overlay = 1,
	.supports_tv = 1,
	.hws_needs_physical = 1,
};

static const struct intel_device_info intel_g45_info = {
	GEN4_FEATURES,
	.platform = INTEL_G4X,
	.has_pipe_cxsr = 1,
	.ring_mask = RENDER_RING | BSD_RING,
};

static const struct intel_device_info intel_gm45_info = {
	GEN4_FEATURES,
	.platform = INTEL_G4X,
	.is_mobile = 1, .has_fbc = 1,
	.has_pipe_cxsr = 1,
	.supports_tv = 1,
	.ring_mask = RENDER_RING | BSD_RING,
};

#define GEN5_FEATURES \
	.gen = 5, .num_pipes = 2, \
	.has_hotplug = 1, \
	.has_gmbus_irq = 1, \
	.ring_mask = RENDER_RING | BSD_RING, \
	GEN_DEFAULT_PIPEOFFSETS, \
	CURSOR_OFFSETS

static const struct intel_device_info intel_ironlake_d_info = {
	GEN5_FEATURES,
	.platform = INTEL_IRONLAKE,
};

static const struct intel_device_info intel_ironlake_m_info = {
	GEN5_FEATURES,
	.platform = INTEL_IRONLAKE,
	.is_mobile = 1,
};

#define GEN6_FEATURES \
	.gen = 6, .num_pipes = 2, \
	.has_hotplug = 1, \
	.has_fbc = 1, \
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
	.has_llc = 1, \
	.has_rc6 = 1, \
	.has_rc6p = 1, \
	.has_gmbus_irq = 1, \
	.has_hw_contexts = 1, \
	.has_aliasing_ppgtt = 1, \
	GEN_DEFAULT_PIPEOFFSETS, \
	CURSOR_OFFSETS

static const struct intel_device_info intel_sandybridge_d_info = {
	GEN6_FEATURES,
	.platform = INTEL_SANDYBRIDGE,
};

static const struct intel_device_info intel_sandybridge_m_info = {
	GEN6_FEATURES,
	.platform = INTEL_SANDYBRIDGE,
	.is_mobile = 1,
};

#define GEN7_FEATURES  \
	.gen = 7, .num_pipes = 3, \
	.has_hotplug = 1, \
	.has_fbc = 1, \
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
	.has_llc = 1, \
	.has_rc6 = 1, \
	.has_rc6p = 1, \
	.has_gmbus_irq = 1, \
	.has_hw_contexts = 1, \
	.has_aliasing_ppgtt = 1, \
	.has_full_ppgtt = 1, \
	GEN_DEFAULT_PIPEOFFSETS, \
	IVB_CURSOR_OFFSETS

static const struct intel_device_info intel_ivybridge_d_info = {
	GEN7_FEATURES,
	.platform = INTEL_IVYBRIDGE,
	.has_l3_dpf = 1,
};

static const struct intel_device_info intel_ivybridge_m_info = {
	GEN7_FEATURES,
	.platform = INTEL_IVYBRIDGE,
	.is_mobile = 1,
	.has_l3_dpf = 1,
};

static const struct intel_device_info intel_ivybridge_q_info = {
	GEN7_FEATURES,
	.platform = INTEL_IVYBRIDGE,
	.num_pipes = 0, /* legal, last one wins */
	.has_l3_dpf = 1,
};

#define VLV_FEATURES  \
	.gen = 7, .num_pipes = 2, \
	.has_psr = 1, \
	.has_runtime_pm = 1, \
	.has_rc6 = 1, \
	.has_gmbus_irq = 1, \
	.has_hw_contexts = 1, \
	.has_gmch_display = 1, \
	.has_hotplug = 1, \
	.has_aliasing_ppgtt = 1, \
	.has_full_ppgtt = 1, \
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
	.display_mmio_offset = VLV_DISPLAY_BASE, \
	GEN_DEFAULT_PIPEOFFSETS, \
	CURSOR_OFFSETS

static const struct intel_device_info intel_valleyview_info = {
	VLV_FEATURES,
	.platform = INTEL_VALLEYVIEW,
};

#define HSW_FEATURES  \
	GEN7_FEATURES, \
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
	.has_ddi = 1, \
	.has_fpga_dbg = 1, \
	.has_psr = 1, \
	.has_resource_streamer = 1, \
	.has_dp_mst = 1, \
	.has_rc6p = 0 /* RC6p removed-by HSW */, \
	.has_runtime_pm = 1

static const struct intel_device_info intel_haswell_info = {
	HSW_FEATURES,
	.platform = INTEL_HASWELL,
	.has_l3_dpf = 1,
};

#define BDW_FEATURES \
	HSW_FEATURES, \
	BDW_COLORS, \
	.has_logical_ring_contexts = 1, \
	.has_full_48bit_ppgtt = 1, \
	.has_64bit_reloc = 1

static const struct intel_device_info intel_broadwell_info = {
	BDW_FEATURES,
	.gen = 8,
	.platform = INTEL_BROADWELL,
};

static const struct intel_device_info intel_broadwell_gt3_info = {
	BDW_FEATURES,
	.gen = 8,
	.platform = INTEL_BROADWELL,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};

static const struct intel_device_info intel_cherryview_info = {
	.gen = 8, .num_pipes = 3,
	.has_hotplug = 1,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
	.platform = INTEL_CHERRYVIEW,
	.has_64bit_reloc = 1,
	.has_psr = 1,
	.has_runtime_pm = 1,
	.has_resource_streamer = 1,
	.has_rc6 = 1,
	.has_gmbus_irq = 1,
	.has_hw_contexts = 1,
	.has_logical_ring_contexts = 1,
	.has_gmch_display = 1,
	.has_aliasing_ppgtt = 1,
	.has_full_ppgtt = 1,
	.display_mmio_offset = VLV_DISPLAY_BASE,
	GEN_CHV_PIPEOFFSETS,
	CURSOR_OFFSETS,
	CHV_COLORS,
};

static const struct intel_device_info intel_skylake_info = {
	BDW_FEATURES,
	.platform = INTEL_SKYLAKE,
	.gen = 9,
	.has_csr = 1,
	.has_guc = 1,
	.ddb_size = 896,
};

static const struct intel_device_info intel_skylake_gt3_info = {
	BDW_FEATURES,
	.platform = INTEL_SKYLAKE,
	.gen = 9,
	.has_csr = 1,
	.has_guc = 1,
	.ddb_size = 896,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};

#define GEN9_LP_FEATURES \
	.gen = 9, \
	.is_lp = 1, \
	.has_hotplug = 1, \
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
	.num_pipes = 3, \
	.has_64bit_reloc = 1, \
	.has_ddi = 1, \
	.has_fpga_dbg = 1, \
	.has_fbc = 1, \
	.has_runtime_pm = 1, \
	.has_pooled_eu = 0, \
	.has_csr = 1, \
	.has_resource_streamer = 1, \
	.has_rc6 = 1, \
	.has_dp_mst = 1, \
	.has_gmbus_irq = 1, \
	.has_hw_contexts = 1, \
	.has_logical_ring_contexts = 1, \
	.has_guc = 1, \
	.has_decoupled_mmio = 1, \
	.has_aliasing_ppgtt = 1, \
	.has_full_ppgtt = 1, \
	.has_full_48bit_ppgtt = 1, \
	GEN_DEFAULT_PIPEOFFSETS, \
	IVB_CURSOR_OFFSETS, \
	BDW_COLORS

static const struct intel_device_info intel_broxton_info = {
	GEN9_LP_FEATURES,
	.platform = INTEL_BROXTON,
	.ddb_size = 512,
};

static const struct intel_device_info intel_geminilake_info = {
	GEN9_LP_FEATURES,
	.platform = INTEL_GEMINILAKE,
	.is_alpha_support = 1,
	.ddb_size = 1024,
};

static const struct intel_device_info intel_kabylake_info = {
	BDW_FEATURES,
	.platform = INTEL_KABYLAKE,
	.gen = 9,
	.has_csr = 1,
	.has_guc = 1,
	.ddb_size = 896,
};

static const struct intel_device_info intel_kabylake_gt3_info = {
	BDW_FEATURES,
	.platform = INTEL_KABYLAKE,
	.gen = 9,
	.has_csr = 1,
	.has_guc = 1,
	.ddb_size = 896,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};

/*
 * Make sure any device matches here are from most specific to most
 * general.  For example, since the Quanta match is based on the subsystem
 * and subvendor IDs, we need it to come before the more general IVB
 * PCI ID matches, otherwise we'll use the wrong info struct above.
 */
static const struct pci_device_id pciidlist[] = {
	INTEL_I830_IDS(&intel_i830_info),
	INTEL_I845G_IDS(&intel_i845g_info),
	INTEL_I85X_IDS(&intel_i85x_info),
	INTEL_I865G_IDS(&intel_i865g_info),
	INTEL_I915G_IDS(&intel_i915g_info),
	INTEL_I915GM_IDS(&intel_i915gm_info),
	INTEL_I945G_IDS(&intel_i945g_info),
	INTEL_I945GM_IDS(&intel_i945gm_info),
	INTEL_I965G_IDS(&intel_i965g_info),
	INTEL_G33_IDS(&intel_g33_info),
	INTEL_I965GM_IDS(&intel_i965gm_info),
	INTEL_GM45_IDS(&intel_gm45_info),
	INTEL_G45_IDS(&intel_g45_info),
	INTEL_PINEVIEW_IDS(&intel_pineview_info),
	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
	INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
	INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
	INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
	INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
	INTEL_HSW_IDS(&intel_haswell_info),
	INTEL_VLV_IDS(&intel_valleyview_info),
	INTEL_BDW_GT12_IDS(&intel_broadwell_info),
	INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
	INTEL_CHV_IDS(&intel_cherryview_info),
	INTEL_SKL_GT1_IDS(&intel_skylake_info),
	INTEL_SKL_GT2_IDS(&intel_skylake_info),
	INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
	INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
	INTEL_BXT_IDS(&intel_broxton_info),
	INTEL_GLK_IDS(&intel_geminilake_info),
	INTEL_KBL_GT1_IDS(&intel_kabylake_info),
	INTEL_KBL_GT2_IDS(&intel_kabylake_info),
	INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
	INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
	{0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, pciidlist);

static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	struct intel_device_info *intel_info =
		(struct intel_device_info *) ent->driver_data;

	if (IS_ALPHA_SUPPORT(intel_info) && !i915.alpha_support) {
		DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
			 "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
			 "to enable support in this kernel version, or check for kernel updates.\n");
		return -ENODEV;
	}

	/* Only bind to function 0 of the device. Early generations
	 * used function 1 as a placeholder for multi-head. This causes
	 * us confusion instead, especially on the systems where both
	 * functions have the same PCI-ID!
	 */
	if (PCI_FUNC(pdev->devfn))
		return -ENODEV;

	/*
	 * apple-gmux is needed on dual GPU MacBook Pro
	 * to probe the panel if we're the inactive GPU.
	 */
	if (vga_switcheroo_client_probe_defer(pdev))
		return -EPROBE_DEFER;

	return i915_driver_load(pdev, ent);
}

static void i915_pci_remove(struct pci_dev *pdev)
{
	struct drm_device *dev = pci_get_drvdata(pdev);

	i915_driver_unload(dev);
	drm_dev_unref(dev);
}

static struct pci_driver i915_pci_driver = {
	.name = DRIVER_NAME,
	.id_table = pciidlist,
	.probe = i915_pci_probe,
	.remove = i915_pci_remove,
	.driver.pm = &i915_pm_ops,
};

static int __init i915_init(void)
{
	bool use_kms = true;

	/*
	 * Enable KMS by default, unless explicitly overriden by
	 * either the i915.modeset prarameter or by the
	 * vga_text_mode_force boot option.
	 */

	if (i915.modeset == 0)
		use_kms = false;

	if (vgacon_text_force() && i915.modeset == -1)
		use_kms = false;

	if (!use_kms) {
		/* Silently fail loading to not upset userspace. */
		DRM_DEBUG_DRIVER("KMS disabled.\n");
		return 0;
	}

	return pci_register_driver(&i915_pci_driver);
}

static void __exit i915_exit(void)
{
	if (!i915_pci_driver.driver.owner)
		return;

	pci_unregister_driver(&i915_pci_driver);
}

module_init(i915_init);
module_exit(i915_exit);

MODULE_AUTHOR("Tungsten Graphics, Inc.");
MODULE_AUTHOR("Intel Corporation");

MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL and additional rights");
Commit	Line	Data
42f5551d CW	1	/*
	2	* Copyright © 2016 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	*/
	24
a09d0ba1	25	#include <linux/console.h>
42f5551d CW	26	#include <linux/vgaarb.h>
	27	#include <linux/vga_switcheroo.h>
	28
	29	#include "i915_drv.h"
	30
	31	#define GEN_DEFAULT_PIPEOFFSETS \
	32	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
	33	PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
	34	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
	35	TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
	36	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
	37
	38	#define GEN_CHV_PIPEOFFSETS \
	39	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
	40	CHV_PIPE_C_OFFSET }, \
	41	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
	42	CHV_TRANSCODER_C_OFFSET, }, \
	43	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
	44	CHV_PALETTE_C_OFFSET }
	45
	46	#define CURSOR_OFFSETS \
	47	.cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
	48
	49	#define IVB_CURSOR_OFFSETS \
	50	.cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
	51
	52	#define BDW_COLORS \
	53	.color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
	54	#define CHV_COLORS \
	55	.color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
	56
a5ce929b	57	/* Keep in gen based order, and chronological order within a gen */
0eec8dc7 CS	58	#define GEN2_FEATURES \
	59	.gen = 2, .num_pipes = 1, \
	60	.has_overlay = 1, .overlay_needs_physical = 1, \
804b8712	61	.has_gmch_display = 1, \
3177659a	62	.hws_needs_physical = 1, \
0eec8dc7 CS	63	.ring_mask = RENDER_RING, \
	64	GEN_DEFAULT_PIPEOFFSETS, \
	65	CURSOR_OFFSETS
	66
42f5551d	67	static const struct intel_device_info intel_i830_info = {
0eec8dc7	68	GEN2_FEATURES,
2e0d26f8	69	.platform = INTEL_I830,
0eec8dc7 CS	70	.is_mobile = 1, .cursor_needs_physical = 1,
0eec8dc7 CS	71	.num_pipes = 2, /* legal, last one wins */
42f5551d CW	72	};
42f5551d CW	73
2a307c2e	74	static const struct intel_device_info intel_i845g_info = {
0eec8dc7	75	GEN2_FEATURES,
2e0d26f8	76	.platform = INTEL_I845G,
42f5551d CW	77	};
	78
	79	static const struct intel_device_info intel_i85x_info = {
0eec8dc7	80	GEN2_FEATURES,
2e0d26f8	81	.platform = INTEL_I85X, .is_mobile = 1,
0eec8dc7	82	.num_pipes = 2, /* legal, last one wins */
42f5551d	83	.cursor_needs_physical = 1,
42f5551d	84	.has_fbc = 1,
42f5551d CW	85	};
	86
	87	static const struct intel_device_info intel_i865g_info = {
0eec8dc7	88	GEN2_FEATURES,
2e0d26f8	89	.platform = INTEL_I865G,
42f5551d CW	90	};
42f5551d CW	91
54d2a6a1 CS	92	#define GEN3_FEATURES \
54d2a6a1 CS	93	.gen = 3, .num_pipes = 2, \
804b8712	94	.has_gmch_display = 1, \
54d2a6a1 CS	95	.ring_mask = RENDER_RING, \
	96	GEN_DEFAULT_PIPEOFFSETS, \
	97	CURSOR_OFFSETS
	98
42f5551d	99	static const struct intel_device_info intel_i915g_info = {
54d2a6a1	100	GEN3_FEATURES,
2e0d26f8	101	.platform = INTEL_I915G, .cursor_needs_physical = 1,
42f5551d	102	.has_overlay = 1, .overlay_needs_physical = 1,
3177659a	103	.hws_needs_physical = 1,
42f5551d	104	};
a5ce929b	105
42f5551d	106	static const struct intel_device_info intel_i915gm_info = {
54d2a6a1	107	GEN3_FEATURES,
2e0d26f8	108	.platform = INTEL_I915GM,
54d2a6a1	109	.is_mobile = 1,
42f5551d CW	110	.cursor_needs_physical = 1,
	111	.has_overlay = 1, .overlay_needs_physical = 1,
	112	.supports_tv = 1,
	113	.has_fbc = 1,
3177659a	114	.hws_needs_physical = 1,
42f5551d	115	};
a5ce929b	116
42f5551d	117	static const struct intel_device_info intel_i945g_info = {
54d2a6a1	118	GEN3_FEATURES,
2e0d26f8	119	.platform = INTEL_I945G,
54d2a6a1	120	.has_hotplug = 1, .cursor_needs_physical = 1,
42f5551d	121	.has_overlay = 1, .overlay_needs_physical = 1,
3177659a	122	.hws_needs_physical = 1,
42f5551d	123	};
a5ce929b	124
42f5551d	125	static const struct intel_device_info intel_i945gm_info = {
54d2a6a1	126	GEN3_FEATURES,
2e0d26f8	127	.platform = INTEL_I945GM, .is_mobile = 1,
42f5551d CW	128	.has_hotplug = 1, .cursor_needs_physical = 1,
	129	.has_overlay = 1, .overlay_needs_physical = 1,
	130	.supports_tv = 1,
	131	.has_fbc = 1,
3177659a	132	.hws_needs_physical = 1,
42f5551d CW	133	};
42f5551d CW	134
a5ce929b JN	135	static const struct intel_device_info intel_g33_info = {
	136	GEN3_FEATURES,
	137	.platform = INTEL_G33,
	138	.has_hotplug = 1,
	139	.has_overlay = 1,
	140	};
	141
	142	static const struct intel_device_info intel_pineview_info = {
	143	GEN3_FEATURES,
	144	.platform = INTEL_G33, .is_pineview = 1, .is_mobile = 1,
	145	.has_hotplug = 1,
	146	.has_overlay = 1,
	147	};
	148
4d495bea CS	149	#define GEN4_FEATURES \
	150	.gen = 4, .num_pipes = 2, \
	151	.has_hotplug = 1, \
804b8712	152	.has_gmch_display = 1, \
4d495bea CS	153	.ring_mask = RENDER_RING, \
	154	GEN_DEFAULT_PIPEOFFSETS, \
	155	CURSOR_OFFSETS
	156
42f5551d	157	static const struct intel_device_info intel_i965g_info = {
4d495bea	158	GEN4_FEATURES,
c0f86832	159	.platform = INTEL_I965G,
42f5551d	160	.has_overlay = 1,
3177659a	161	.hws_needs_physical = 1,
42f5551d CW	162	};
	163
	164	static const struct intel_device_info intel_i965gm_info = {
4d495bea	165	GEN4_FEATURES,
c0f86832	166	.platform = INTEL_I965GM,
4d495bea	167	.is_mobile = 1, .has_fbc = 1,
42f5551d CW	168	.has_overlay = 1,
42f5551d CW	169	.supports_tv = 1,
3177659a	170	.hws_needs_physical = 1,
42f5551d CW	171	};
42f5551d CW	172
42f5551d	173	static const struct intel_device_info intel_g45_info = {
4d495bea	174	GEN4_FEATURES,
2e0d26f8	175	.platform = INTEL_G4X,
4d495bea	176	.has_pipe_cxsr = 1,
42f5551d	177	.ring_mask = RENDER_RING \| BSD_RING,
42f5551d CW	178	};
	179
	180	static const struct intel_device_info intel_gm45_info = {
4d495bea	181	GEN4_FEATURES,
2e0d26f8	182	.platform = INTEL_G4X,
3177659a	183	.is_mobile = 1, .has_fbc = 1,
4d495bea	184	.has_pipe_cxsr = 1,
42f5551d CW	185	.supports_tv = 1,
42f5551d CW	186	.ring_mask = RENDER_RING \| BSD_RING,
42f5551d CW	187	};
42f5551d CW	188
a1323380 CS	189	#define GEN5_FEATURES \
a1323380 CS	190	.gen = 5, .num_pipes = 2, \
3177659a	191	.has_hotplug = 1, \
b355f109	192	.has_gmbus_irq = 1, \
a1323380 CS	193	.ring_mask = RENDER_RING \| BSD_RING, \
	194	GEN_DEFAULT_PIPEOFFSETS, \
	195	CURSOR_OFFSETS
	196
42f5551d	197	static const struct intel_device_info intel_ironlake_d_info = {
a1323380	198	GEN5_FEATURES,
2e0d26f8	199	.platform = INTEL_IRONLAKE,
42f5551d CW	200	};
	201
	202	static const struct intel_device_info intel_ironlake_m_info = {
a1323380	203	GEN5_FEATURES,
2e0d26f8	204	.platform = INTEL_IRONLAKE,
a1323380	205	.is_mobile = 1,
42f5551d CW	206	};
42f5551d CW	207
07db6be7 CS	208	#define GEN6_FEATURES \
07db6be7 CS	209	.gen = 6, .num_pipes = 2, \
3177659a	210	.has_hotplug = 1, \
07db6be7 CS	211	.has_fbc = 1, \
	212	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING, \
	213	.has_llc = 1, \
86f3624b	214	.has_rc6 = 1, \
33b5bf82	215	.has_rc6p = 1, \
b355f109	216	.has_gmbus_irq = 1, \
e1a52536	217	.has_hw_contexts = 1, \
9e1d0e60	218	.has_aliasing_ppgtt = 1, \
07db6be7 CS	219	GEN_DEFAULT_PIPEOFFSETS, \
	220	CURSOR_OFFSETS
	221
42f5551d	222	static const struct intel_device_info intel_sandybridge_d_info = {
07db6be7	223	GEN6_FEATURES,
2e0d26f8	224	.platform = INTEL_SANDYBRIDGE,
42f5551d CW	225	};
	226
	227	static const struct intel_device_info intel_sandybridge_m_info = {
07db6be7	228	GEN6_FEATURES,
2e0d26f8	229	.platform = INTEL_SANDYBRIDGE,
07db6be7	230	.is_mobile = 1,
42f5551d CW	231	};
	232
	233	#define GEN7_FEATURES \
	234	.gen = 7, .num_pipes = 3, \
3177659a	235	.has_hotplug = 1, \
42f5551d CW	236	.has_fbc = 1, \
	237	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING, \
	238	.has_llc = 1, \
86f3624b	239	.has_rc6 = 1, \
33b5bf82	240	.has_rc6p = 1, \
b355f109	241	.has_gmbus_irq = 1, \
e1a52536	242	.has_hw_contexts = 1, \
9e1d0e60 MT	243	.has_aliasing_ppgtt = 1, \
9e1d0e60 MT	244	.has_full_ppgtt = 1, \
42f5551d CW	245	GEN_DEFAULT_PIPEOFFSETS, \
	246	IVB_CURSOR_OFFSETS
	247
	248	static const struct intel_device_info intel_ivybridge_d_info = {
	249	GEN7_FEATURES,
2e0d26f8	250	.platform = INTEL_IVYBRIDGE,
ca9c4523	251	.has_l3_dpf = 1,
42f5551d CW	252	};
	253
	254	static const struct intel_device_info intel_ivybridge_m_info = {
	255	GEN7_FEATURES,
2e0d26f8	256	.platform = INTEL_IVYBRIDGE,
42f5551d	257	.is_mobile = 1,
ca9c4523	258	.has_l3_dpf = 1,
42f5551d CW	259	};
	260
	261	static const struct intel_device_info intel_ivybridge_q_info = {
	262	GEN7_FEATURES,
2e0d26f8	263	.platform = INTEL_IVYBRIDGE,
42f5551d	264	.num_pipes = 0, /* legal, last one wins */
ca9c4523	265	.has_l3_dpf = 1,
42f5551d CW	266	};
	267
	268	#define VLV_FEATURES \
	269	.gen = 7, .num_pipes = 2, \
6e3b84d8	270	.has_psr = 1, \
4aa4c23f	271	.has_runtime_pm = 1, \
86f3624b	272	.has_rc6 = 1, \
b355f109	273	.has_gmbus_irq = 1, \
e1a52536	274	.has_hw_contexts = 1, \
804b8712	275	.has_gmch_display = 1, \
3177659a	276	.has_hotplug = 1, \
9e1d0e60 MT	277	.has_aliasing_ppgtt = 1, \
9e1d0e60 MT	278	.has_full_ppgtt = 1, \
42f5551d CW	279	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING, \
	280	.display_mmio_offset = VLV_DISPLAY_BASE, \
	281	GEN_DEFAULT_PIPEOFFSETS, \
	282	CURSOR_OFFSETS
	283
8d9c20e1	284	static const struct intel_device_info intel_valleyview_info = {
42f5551d	285	VLV_FEATURES,
2e0d26f8	286	.platform = INTEL_VALLEYVIEW,
42f5551d CW	287	};
	288
	289	#define HSW_FEATURES \
	290	GEN7_FEATURES, \
	291	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING, \
	292	.has_ddi = 1, \
6e3b84d8	293	.has_fpga_dbg = 1, \
4aa4c23f	294	.has_psr = 1, \
53233f08	295	.has_resource_streamer = 1, \
1d3fe53b	296	.has_dp_mst = 1, \
33b5bf82	297	.has_rc6p = 0 /* RC6p removed-by HSW */, \
4aa4c23f	298	.has_runtime_pm = 1
42f5551d	299
8d9c20e1	300	static const struct intel_device_info intel_haswell_info = {
42f5551d	301	HSW_FEATURES,
2e0d26f8	302	.platform = INTEL_HASWELL,
ca9c4523	303	.has_l3_dpf = 1,
42f5551d CW	304	};
42f5551d CW	305
42f5551d CW	306	#define BDW_FEATURES \
42f5551d CW	307	HSW_FEATURES, \
4586f1d0	308	BDW_COLORS, \
dfc5148f	309	.has_logical_ring_contexts = 1, \
9e1d0e60	310	.has_full_48bit_ppgtt = 1, \
dfc5148f	311	.has_64bit_reloc = 1
42f5551d	312
8d9c20e1	313	static const struct intel_device_info intel_broadwell_info = {
42f5551d CW	314	BDW_FEATURES,
42f5551d CW	315	.gen = 8,
2e0d26f8	316	.platform = INTEL_BROADWELL,
42f5551d CW	317	};
42f5551d CW	318
8d9c20e1	319	static const struct intel_device_info intel_broadwell_gt3_info = {
42f5551d CW	320	BDW_FEATURES,
42f5551d CW	321	.gen = 8,
2e0d26f8	322	.platform = INTEL_BROADWELL,
42f5551d CW	323	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING \| BSD2_RING,
	324	};
	325
42f5551d CW	326	static const struct intel_device_info intel_cherryview_info = {
42f5551d CW	327	.gen = 8, .num_pipes = 3,
3177659a	328	.has_hotplug = 1,
42f5551d	329	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING,
2e0d26f8	330	.platform = INTEL_CHERRYVIEW,
dfc5148f	331	.has_64bit_reloc = 1,
6e3b84d8	332	.has_psr = 1,
4aa4c23f	333	.has_runtime_pm = 1,
53233f08	334	.has_resource_streamer = 1,
86f3624b	335	.has_rc6 = 1,
b355f109	336	.has_gmbus_irq = 1,
e1a52536	337	.has_hw_contexts = 1,
4586f1d0	338	.has_logical_ring_contexts = 1,
804b8712	339	.has_gmch_display = 1,
9e1d0e60 MT	340	.has_aliasing_ppgtt = 1,
9e1d0e60 MT	341	.has_full_ppgtt = 1,
42f5551d CW	342	.display_mmio_offset = VLV_DISPLAY_BASE,
	343	GEN_CHV_PIPEOFFSETS,
	344	CURSOR_OFFSETS,
	345	CHV_COLORS,
	346	};
	347
	348	static const struct intel_device_info intel_skylake_info = {
	349	BDW_FEATURES,
2e0d26f8	350	.platform = INTEL_SKYLAKE,
42f5551d	351	.gen = 9,
3bacde19	352	.has_csr = 1,
3d810fbe	353	.has_guc = 1,
6f3fff60	354	.ddb_size = 896,
42f5551d CW	355	};
	356
	357	static const struct intel_device_info intel_skylake_gt3_info = {
	358	BDW_FEATURES,
2e0d26f8	359	.platform = INTEL_SKYLAKE,
42f5551d	360	.gen = 9,
3bacde19	361	.has_csr = 1,
3d810fbe	362	.has_guc = 1,
6f3fff60	363	.ddb_size = 896,
42f5551d CW	364	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING \| BSD2_RING,
	365	};
	366
80fa66b6 RV	367	#define GEN9_LP_FEATURES \
80fa66b6 RV	368	.gen = 9, \
3e4274f8	369	.is_lp = 1, \
80fa66b6 RV	370	.has_hotplug = 1, \
	371	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING, \
	372	.num_pipes = 3, \
	373	.has_64bit_reloc = 1, \
	374	.has_ddi = 1, \
	375	.has_fpga_dbg = 1, \
	376	.has_fbc = 1, \
	377	.has_runtime_pm = 1, \
	378	.has_pooled_eu = 0, \
	379	.has_csr = 1, \
	380	.has_resource_streamer = 1, \
	381	.has_rc6 = 1, \
	382	.has_dp_mst = 1, \
	383	.has_gmbus_irq = 1, \
	384	.has_hw_contexts = 1, \
	385	.has_logical_ring_contexts = 1, \
	386	.has_guc = 1, \
	387	.has_decoupled_mmio = 1, \
9e1d0e60 MT	388	.has_aliasing_ppgtt = 1, \
	389	.has_full_ppgtt = 1, \
	390	.has_full_48bit_ppgtt = 1, \
80fa66b6 RV	391	GEN_DEFAULT_PIPEOFFSETS, \
	392	IVB_CURSOR_OFFSETS, \
	393	BDW_COLORS
	394
42f5551d	395	static const struct intel_device_info intel_broxton_info = {
80fa66b6	396	GEN9_LP_FEATURES,
2e0d26f8	397	.platform = INTEL_BROXTON,
6f3fff60	398	.ddb_size = 512,
42f5551d CW	399	};
42f5551d CW	400
c22097fa	401	static const struct intel_device_info intel_geminilake_info = {
c22097fa	402	GEN9_LP_FEATURES,
2e0d26f8 JN	403	.platform = INTEL_GEMINILAKE,
2e0d26f8 JN	404	.is_alpha_support = 1,
c22097fa ACO	405	.ddb_size = 1024,
	406	};
	407
42f5551d CW	408	static const struct intel_device_info intel_kabylake_info = {
42f5551d CW	409	BDW_FEATURES,
2e0d26f8	410	.platform = INTEL_KABYLAKE,
42f5551d	411	.gen = 9,
3bacde19	412	.has_csr = 1,
3d810fbe	413	.has_guc = 1,
6f3fff60	414	.ddb_size = 896,
42f5551d CW	415	};
	416
	417	static const struct intel_device_info intel_kabylake_gt3_info = {
	418	BDW_FEATURES,
2e0d26f8	419	.platform = INTEL_KABYLAKE,
42f5551d	420	.gen = 9,
3bacde19	421	.has_csr = 1,
3d810fbe	422	.has_guc = 1,
6f3fff60	423	.ddb_size = 896,
42f5551d CW	424	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING \| BSD2_RING,
	425	};
	426
	427	/*
	428	* Make sure any device matches here are from most specific to most
	429	* general. For example, since the Quanta match is based on the subsystem
	430	* and subvendor IDs, we need it to come before the more general IVB
	431	* PCI ID matches, otherwise we'll use the wrong info struct above.
	432	*/
	433	static const struct pci_device_id pciidlist[] = {
	434	INTEL_I830_IDS(&intel_i830_info),
2a307c2e	435	INTEL_I845G_IDS(&intel_i845g_info),
42f5551d CW	436	INTEL_I85X_IDS(&intel_i85x_info),
	437	INTEL_I865G_IDS(&intel_i865g_info),
	438	INTEL_I915G_IDS(&intel_i915g_info),
	439	INTEL_I915GM_IDS(&intel_i915gm_info),
	440	INTEL_I945G_IDS(&intel_i945g_info),
	441	INTEL_I945GM_IDS(&intel_i945gm_info),
	442	INTEL_I965G_IDS(&intel_i965g_info),
	443	INTEL_G33_IDS(&intel_g33_info),
	444	INTEL_I965GM_IDS(&intel_i965gm_info),
	445	INTEL_GM45_IDS(&intel_gm45_info),
	446	INTEL_G45_IDS(&intel_g45_info),
	447	INTEL_PINEVIEW_IDS(&intel_pineview_info),
	448	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
	449	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
	450	INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
	451	INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
	452	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
	453	INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
	454	INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
8d9c20e1 CS	455	INTEL_HSW_IDS(&intel_haswell_info),
	456	INTEL_VLV_IDS(&intel_valleyview_info),
	457	INTEL_BDW_GT12_IDS(&intel_broadwell_info),
	458	INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
42f5551d CW	459	INTEL_CHV_IDS(&intel_cherryview_info),
	460	INTEL_SKL_GT1_IDS(&intel_skylake_info),
	461	INTEL_SKL_GT2_IDS(&intel_skylake_info),
	462	INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
	463	INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
	464	INTEL_BXT_IDS(&intel_broxton_info),
8363e3c3	465	INTEL_GLK_IDS(&intel_geminilake_info),
42f5551d CW	466	INTEL_KBL_GT1_IDS(&intel_kabylake_info),
	467	INTEL_KBL_GT2_IDS(&intel_kabylake_info),
	468	INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
	469	INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
	470	{0, 0, 0}
	471	};
	472	MODULE_DEVICE_TABLE(pci, pciidlist);
	473
42f5551d CW	474	static int i915_pci_probe(struct pci_dev pdev, const struct pci_device_id ent)
	475	{
	476	struct intel_device_info *intel_info =
	477	(struct intel_device_info *) ent->driver_data;
	478
c007fb4a JN	479	if (IS_ALPHA_SUPPORT(intel_info) && !i915.alpha_support) {
	480	DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
	481	"See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
	482	"to enable support in this kernel version, or check for kernel updates.\n");
42f5551d CW	483	return -ENODEV;
	484	}
	485
	486	/* Only bind to function 0 of the device. Early generations
	487	* used function 1 as a placeholder for multi-head. This causes
	488	* us confusion instead, especially on the systems where both
	489	* functions have the same PCI-ID!
	490	*/
	491	if (PCI_FUNC(pdev->devfn))
	492	return -ENODEV;
	493
	494	/*
	495	* apple-gmux is needed on dual GPU MacBook Pro
	496	* to probe the panel if we're the inactive GPU.
	497	*/
	498	if (vga_switcheroo_client_probe_defer(pdev))
	499	return -EPROBE_DEFER;
	500
	501	return i915_driver_load(pdev, ent);
	502	}
	503
42f5551d CW	504	static void i915_pci_remove(struct pci_dev *pdev)
	505	{
	506	struct drm_device *dev = pci_get_drvdata(pdev);
	507
	508	i915_driver_unload(dev);
	509	drm_dev_unref(dev);
	510	}
	511
a09d0ba1	512	static struct pci_driver i915_pci_driver = {
42f5551d CW	513	.name = DRIVER_NAME,
	514	.id_table = pciidlist,
	515	.probe = i915_pci_probe,
	516	.remove = i915_pci_remove,
	517	.driver.pm = &i915_pm_ops,
	518	};
a09d0ba1 CW	519
	520	static int __init i915_init(void)
	521	{
	522	bool use_kms = true;
	523
	524	/*
	525	* Enable KMS by default, unless explicitly overriden by
	526	* either the i915.modeset prarameter or by the
	527	* vga_text_mode_force boot option.
	528	*/
	529
	530	if (i915.modeset == 0)
	531	use_kms = false;
	532
	533	if (vgacon_text_force() && i915.modeset == -1)
	534	use_kms = false;
	535
	536	if (!use_kms) {
	537	/* Silently fail loading to not upset userspace. */
	538	DRM_DEBUG_DRIVER("KMS disabled.\n");
	539	return 0;
	540	}
	541
	542	return pci_register_driver(&i915_pci_driver);
	543	}
	544
	545	static void __exit i915_exit(void)
	546	{
	547	if (!i915_pci_driver.driver.owner)
	548	return;
	549
	550	pci_unregister_driver(&i915_pci_driver);
	551	}
	552
	553	module_init(i915_init);
	554	module_exit(i915_exit);
	555
	556	MODULE_AUTHOR("Tungsten Graphics, Inc.");
	557	MODULE_AUTHOR("Intel Corporation");
	558
	559	MODULE_DESCRIPTION(DRIVER_DESC);
	560	MODULE_LICENSE("GPL and additional rights");