[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_pci.c

/*
 * Copyright © 2016 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 */

#include <linux/console.h>
#include <linux/vgaarb.h>
#include <linux/vga_switcheroo.h>

#include "i915_drv.h"

#define GEN_DEFAULT_PIPEOFFSETS \
	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
			  PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
			   TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }

#define GEN_CHV_PIPEOFFSETS \
	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
			  CHV_PIPE_C_OFFSET }, \
	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
			   CHV_TRANSCODER_C_OFFSET, }, \
	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
			     CHV_PALETTE_C_OFFSET }

#define CURSOR_OFFSETS \
	.cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }

#define IVB_CURSOR_OFFSETS \
	.cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }

#define BDW_COLORS \
	.color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
#define CHV_COLORS \
	.color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }

/* Keep in gen based order, and chronological order within a gen */
#define GEN2_FEATURES \
	.gen = 2, .num_pipes = 1, \
	.has_overlay = 1, .overlay_needs_physical = 1, \
	.has_gmch_display = 1, \
	.hws_needs_physical = 1, \
	.unfenced_needs_alignment = 1, \
	.ring_mask = RENDER_RING, \
	GEN_DEFAULT_PIPEOFFSETS, \
	CURSOR_OFFSETS

static const struct intel_device_info intel_i830_info = {
	GEN2_FEATURES,
	.platform = INTEL_I830,
	.is_mobile = 1, .cursor_needs_physical = 1,
	.num_pipes = 2, /* legal, last one wins */
};

static const struct intel_device_info intel_i845g_info = {
	GEN2_FEATURES,
	.platform = INTEL_I845G,
};

static const struct intel_device_info intel_i85x_info = {
	GEN2_FEATURES,
	.platform = INTEL_I85X, .is_mobile = 1,
	.num_pipes = 2, /* legal, last one wins */
	.cursor_needs_physical = 1,
	.has_fbc = 1,
};

static const struct intel_device_info intel_i865g_info = {
	GEN2_FEATURES,
	.platform = INTEL_I865G,
};

#define GEN3_FEATURES \
	.gen = 3, .num_pipes = 2, \
	.has_gmch_display = 1, \
	.ring_mask = RENDER_RING, \
	GEN_DEFAULT_PIPEOFFSETS, \
	CURSOR_OFFSETS

static const struct intel_device_info intel_i915g_info = {
	GEN3_FEATURES,
	.platform = INTEL_I915G, .cursor_needs_physical = 1,
	.has_overlay = 1, .overlay_needs_physical = 1,
	.hws_needs_physical = 1,
	.unfenced_needs_alignment = 1,
};

static const struct intel_device_info intel_i915gm_info = {
	GEN3_FEATURES,
	.platform = INTEL_I915GM,
	.is_mobile = 1,
	.cursor_needs_physical = 1,
	.has_overlay = 1, .overlay_needs_physical = 1,
	.supports_tv = 1,
	.has_fbc = 1,
	.hws_needs_physical = 1,
	.unfenced_needs_alignment = 1,
};

static const struct intel_device_info intel_i945g_info = {
	GEN3_FEATURES,
	.platform = INTEL_I945G,
	.has_hotplug = 1, .cursor_needs_physical = 1,
	.has_overlay = 1, .overlay_needs_physical = 1,
	.hws_needs_physical = 1,
	.unfenced_needs_alignment = 1,
};

static const struct intel_device_info intel_i945gm_info = {
	GEN3_FEATURES,
	.platform = INTEL_I945GM, .is_mobile = 1,
	.has_hotplug = 1, .cursor_needs_physical = 1,
	.has_overlay = 1, .overlay_needs_physical = 1,
	.supports_tv = 1,
	.has_fbc = 1,
	.hws_needs_physical = 1,
	.unfenced_needs_alignment = 1,
};

static const struct intel_device_info intel_g33_info = {
	GEN3_FEATURES,
	.platform = INTEL_G33,
	.has_hotplug = 1,
	.has_overlay = 1,
};

static const struct intel_device_info intel_pineview_info = {
	GEN3_FEATURES,
	.platform = INTEL_PINEVIEW, .is_mobile = 1,
	.has_hotplug = 1,
	.has_overlay = 1,
};

#define GEN4_FEATURES \
	.gen = 4, .num_pipes = 2, \
	.has_hotplug = 1, \
	.has_gmch_display = 1, \
	.ring_mask = RENDER_RING, \
	GEN_DEFAULT_PIPEOFFSETS, \
	CURSOR_OFFSETS

static const struct intel_device_info intel_i965g_info = {
	GEN4_FEATURES,
	.platform = INTEL_I965G,
	.has_overlay = 1,
	.hws_needs_physical = 1,
};

static const struct intel_device_info intel_i965gm_info = {
	GEN4_FEATURES,
	.platform = INTEL_I965GM,
	.is_mobile = 1, .has_fbc = 1,
	.has_overlay = 1,
	.supports_tv = 1,
	.hws_needs_physical = 1,
};

static const struct intel_device_info intel_g45_info = {
	GEN4_FEATURES,
	.platform = INTEL_G45,
	.has_pipe_cxsr = 1,
	.ring_mask = RENDER_RING | BSD_RING,
};

static const struct intel_device_info intel_gm45_info = {
	GEN4_FEATURES,
	.platform = INTEL_GM45,
	.is_mobile = 1, .has_fbc = 1,
	.has_pipe_cxsr = 1,
	.supports_tv = 1,
	.ring_mask = RENDER_RING | BSD_RING,
};

#define GEN5_FEATURES \
	.gen = 5, .num_pipes = 2, \
	.has_hotplug = 1, \
	.has_gmbus_irq = 1, \
	.ring_mask = RENDER_RING | BSD_RING, \
	GEN_DEFAULT_PIPEOFFSETS, \
	CURSOR_OFFSETS

static const struct intel_device_info intel_ironlake_d_info = {
	GEN5_FEATURES,
	.platform = INTEL_IRONLAKE,
};

static const struct intel_device_info intel_ironlake_m_info = {
	GEN5_FEATURES,
	.platform = INTEL_IRONLAKE,
	.is_mobile = 1,
};

#define GEN6_FEATURES \
	.gen = 6, .num_pipes = 2, \
	.has_hotplug = 1, \
	.has_fbc = 1, \
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
	.has_llc = 1, \
	.has_rc6 = 1, \
	.has_rc6p = 1, \
	.has_gmbus_irq = 1, \
	.has_hw_contexts = 1, \
	.has_aliasing_ppgtt = 1, \
	GEN_DEFAULT_PIPEOFFSETS, \
	CURSOR_OFFSETS

static const struct intel_device_info intel_sandybridge_d_info = {
	GEN6_FEATURES,
	.platform = INTEL_SANDYBRIDGE,
};

static const struct intel_device_info intel_sandybridge_m_info = {
	GEN6_FEATURES,
	.platform = INTEL_SANDYBRIDGE,
	.is_mobile = 1,
};

#define GEN7_FEATURES  \
	.gen = 7, .num_pipes = 3, \
	.has_hotplug = 1, \
	.has_fbc = 1, \
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
	.has_llc = 1, \
	.has_rc6 = 1, \
	.has_rc6p = 1, \
	.has_gmbus_irq = 1, \
	.has_hw_contexts = 1, \
	.has_aliasing_ppgtt = 1, \
	.has_full_ppgtt = 1, \
	GEN_DEFAULT_PIPEOFFSETS, \
	IVB_CURSOR_OFFSETS

static const struct intel_device_info intel_ivybridge_d_info = {
	GEN7_FEATURES,
	.platform = INTEL_IVYBRIDGE,
	.has_l3_dpf = 1,
};

static const struct intel_device_info intel_ivybridge_m_info = {
	GEN7_FEATURES,
	.platform = INTEL_IVYBRIDGE,
	.is_mobile = 1,
	.has_l3_dpf = 1,
};

static const struct intel_device_info intel_ivybridge_q_info = {
	GEN7_FEATURES,
	.platform = INTEL_IVYBRIDGE,
	.num_pipes = 0, /* legal, last one wins */
	.has_l3_dpf = 1,
};

static const struct intel_device_info intel_valleyview_info = {
	.platform = INTEL_VALLEYVIEW,
	.gen = 7,
	.is_lp = 1,
	.num_pipes = 2,
	.has_psr = 1,
	.has_runtime_pm = 1,
	.has_rc6 = 1,
	.has_gmbus_irq = 1,
	.has_hw_contexts = 1,
	.has_gmch_display = 1,
	.has_hotplug = 1,
	.has_aliasing_ppgtt = 1,
	.has_full_ppgtt = 1,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
	.display_mmio_offset = VLV_DISPLAY_BASE,
	GEN_DEFAULT_PIPEOFFSETS,
	CURSOR_OFFSETS
};

#define HSW_FEATURES  \
	GEN7_FEATURES, \
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
	.has_ddi = 1, \
	.has_fpga_dbg = 1, \
	.has_psr = 1, \
	.has_resource_streamer = 1, \
	.has_dp_mst = 1, \
	.has_rc6p = 0 /* RC6p removed-by HSW */, \
	.has_runtime_pm = 1

static const struct intel_device_info intel_haswell_info = {
	HSW_FEATURES,
	.platform = INTEL_HASWELL,
	.has_l3_dpf = 1,
};

#define BDW_FEATURES \
	HSW_FEATURES, \
	BDW_COLORS, \
	.has_logical_ring_contexts = 1, \
	.has_full_48bit_ppgtt = 1, \
	.has_64bit_reloc = 1

static const struct intel_device_info intel_broadwell_info = {
	BDW_FEATURES,
	.gen = 8,
	.platform = INTEL_BROADWELL,
};

static const struct intel_device_info intel_broadwell_gt3_info = {
	BDW_FEATURES,
	.gen = 8,
	.platform = INTEL_BROADWELL,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};

static const struct intel_device_info intel_cherryview_info = {
	.gen = 8, .num_pipes = 3,
	.has_hotplug = 1,
	.is_lp = 1,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
	.platform = INTEL_CHERRYVIEW,
	.has_64bit_reloc = 1,
	.has_psr = 1,
	.has_runtime_pm = 1,
	.has_resource_streamer = 1,
	.has_rc6 = 1,
	.has_gmbus_irq = 1,
	.has_hw_contexts = 1,
	.has_logical_ring_contexts = 1,
	.has_gmch_display = 1,
	.has_aliasing_ppgtt = 1,
	.has_full_ppgtt = 1,
	.display_mmio_offset = VLV_DISPLAY_BASE,
	GEN_CHV_PIPEOFFSETS,
	CURSOR_OFFSETS,
	CHV_COLORS,
};

static const struct intel_device_info intel_skylake_info = {
	BDW_FEATURES,
	.platform = INTEL_SKYLAKE,
	.gen = 9,
	.has_csr = 1,
	.has_guc = 1,
	.ddb_size = 896,
};

static const struct intel_device_info intel_skylake_gt3_info = {
	BDW_FEATURES,
	.platform = INTEL_SKYLAKE,
	.gen = 9,
	.has_csr = 1,
	.has_guc = 1,
	.ddb_size = 896,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};

#define GEN9_LP_FEATURES \
	.gen = 9, \
	.is_lp = 1, \
	.has_hotplug = 1, \
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
	.num_pipes = 3, \
	.has_64bit_reloc = 1, \
	.has_ddi = 1, \
	.has_fpga_dbg = 1, \
	.has_fbc = 1, \
	.has_runtime_pm = 1, \
	.has_pooled_eu = 0, \
	.has_csr = 1, \
	.has_resource_streamer = 1, \
	.has_rc6 = 1, \
	.has_dp_mst = 1, \
	.has_gmbus_irq = 1, \
	.has_hw_contexts = 1, \
	.has_logical_ring_contexts = 1, \
	.has_guc = 1, \
	.has_decoupled_mmio = 1, \
	.has_aliasing_ppgtt = 1, \
	.has_full_ppgtt = 1, \
	.has_full_48bit_ppgtt = 1, \
	GEN_DEFAULT_PIPEOFFSETS, \
	IVB_CURSOR_OFFSETS, \
	BDW_COLORS

static const struct intel_device_info intel_broxton_info = {
	GEN9_LP_FEATURES,
	.platform = INTEL_BROXTON,
	.ddb_size = 512,
};

static const struct intel_device_info intel_geminilake_info = {
	GEN9_LP_FEATURES,
	.platform = INTEL_GEMINILAKE,
	.is_alpha_support = 1,
	.ddb_size = 1024,
};

static const struct intel_device_info intel_kabylake_info = {
	BDW_FEATURES,
	.platform = INTEL_KABYLAKE,
	.gen = 9,
	.has_csr = 1,
	.has_guc = 1,
	.ddb_size = 896,
};

static const struct intel_device_info intel_kabylake_gt3_info = {
	BDW_FEATURES,
	.platform = INTEL_KABYLAKE,
	.gen = 9,
	.has_csr = 1,
	.has_guc = 1,
	.ddb_size = 896,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};

/*
 * Make sure any device matches here are from most specific to most
 * general.  For example, since the Quanta match is based on the subsystem
 * and subvendor IDs, we need it to come before the more general IVB
 * PCI ID matches, otherwise we'll use the wrong info struct above.
 */
static const struct pci_device_id pciidlist[] = {
	INTEL_I830_IDS(&intel_i830_info),
	INTEL_I845G_IDS(&intel_i845g_info),
	INTEL_I85X_IDS(&intel_i85x_info),
	INTEL_I865G_IDS(&intel_i865g_info),
	INTEL_I915G_IDS(&intel_i915g_info),
	INTEL_I915GM_IDS(&intel_i915gm_info),
	INTEL_I945G_IDS(&intel_i945g_info),
	INTEL_I945GM_IDS(&intel_i945gm_info),
	INTEL_I965G_IDS(&intel_i965g_info),
	INTEL_G33_IDS(&intel_g33_info),
	INTEL_I965GM_IDS(&intel_i965gm_info),
	INTEL_GM45_IDS(&intel_gm45_info),
	INTEL_G45_IDS(&intel_g45_info),
	INTEL_PINEVIEW_IDS(&intel_pineview_info),
	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
	INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
	INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
	INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
	INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
	INTEL_HSW_IDS(&intel_haswell_info),
	INTEL_VLV_IDS(&intel_valleyview_info),
	INTEL_BDW_GT12_IDS(&intel_broadwell_info),
	INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
	INTEL_BDW_RSVD_IDS(&intel_broadwell_info),
	INTEL_CHV_IDS(&intel_cherryview_info),
	INTEL_SKL_GT1_IDS(&intel_skylake_info),
	INTEL_SKL_GT2_IDS(&intel_skylake_info),
	INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
	INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
	INTEL_BXT_IDS(&intel_broxton_info),
	INTEL_GLK_IDS(&intel_geminilake_info),
	INTEL_KBL_GT1_IDS(&intel_kabylake_info),
	INTEL_KBL_GT2_IDS(&intel_kabylake_info),
	INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
	INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
	{0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, pciidlist);

static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	struct intel_device_info *intel_info =
		(struct intel_device_info *) ent->driver_data;

	if (IS_ALPHA_SUPPORT(intel_info) && !i915.alpha_support) {
		DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
			 "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
			 "to enable support in this kernel version, or check for kernel updates.\n");
		return -ENODEV;
	}

	/* Only bind to function 0 of the device. Early generations
	 * used function 1 as a placeholder for multi-head. This causes
	 * us confusion instead, especially on the systems where both
	 * functions have the same PCI-ID!
	 */
	if (PCI_FUNC(pdev->devfn))
		return -ENODEV;

	/*
	 * apple-gmux is needed on dual GPU MacBook Pro
	 * to probe the panel if we're the inactive GPU.
	 */
	if (vga_switcheroo_client_probe_defer(pdev))
		return -EPROBE_DEFER;

	return i915_driver_load(pdev, ent);
}

static void i915_pci_remove(struct pci_dev *pdev)
{
	struct drm_device *dev = pci_get_drvdata(pdev);

	i915_driver_unload(dev);
	drm_dev_unref(dev);
}

static struct pci_driver i915_pci_driver = {
	.name = DRIVER_NAME,
	.id_table = pciidlist,
	.probe = i915_pci_probe,
	.remove = i915_pci_remove,
	.driver.pm = &i915_pm_ops,
};

static int __init i915_init(void)
{
	bool use_kms = true;

	/*
	 * Enable KMS by default, unless explicitly overriden by
	 * either the i915.modeset prarameter or by the
	 * vga_text_mode_force boot option.
	 */

	if (i915.modeset == 0)
		use_kms = false;

	if (vgacon_text_force() && i915.modeset == -1)
		use_kms = false;

	if (!use_kms) {
		/* Silently fail loading to not upset userspace. */
		DRM_DEBUG_DRIVER("KMS disabled.\n");
		return 0;
	}

	return pci_register_driver(&i915_pci_driver);
}

static void __exit i915_exit(void)
{
	if (!i915_pci_driver.driver.owner)
		return;

	pci_unregister_driver(&i915_pci_driver);
}

module_init(i915_init);
module_exit(i915_exit);

MODULE_AUTHOR("Tungsten Graphics, Inc.");
MODULE_AUTHOR("Intel Corporation");

MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL and additional rights");
Commit	Line	Data
42f5551d CW	1	/*
	2	* Copyright © 2016 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	*/
	24
a09d0ba1	25	#include <linux/console.h>
42f5551d CW	26	#include <linux/vgaarb.h>
	27	#include <linux/vga_switcheroo.h>
	28
	29	#include "i915_drv.h"
	30
	31	#define GEN_DEFAULT_PIPEOFFSETS \
	32	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
	33	PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
	34	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
	35	TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
	36	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
	37
	38	#define GEN_CHV_PIPEOFFSETS \
	39	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
	40	CHV_PIPE_C_OFFSET }, \
	41	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
	42	CHV_TRANSCODER_C_OFFSET, }, \
	43	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
	44	CHV_PALETTE_C_OFFSET }
	45
	46	#define CURSOR_OFFSETS \
	47	.cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
	48
	49	#define IVB_CURSOR_OFFSETS \
	50	.cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
	51
	52	#define BDW_COLORS \
	53	.color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
	54	#define CHV_COLORS \
	55	.color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
	56
a5ce929b	57	/* Keep in gen based order, and chronological order within a gen */
0eec8dc7 CS	58	#define GEN2_FEATURES \
	59	.gen = 2, .num_pipes = 1, \
	60	.has_overlay = 1, .overlay_needs_physical = 1, \
804b8712	61	.has_gmch_display = 1, \
3177659a	62	.hws_needs_physical = 1, \
9e176430	63	.unfenced_needs_alignment = 1, \
0eec8dc7 CS	64	.ring_mask = RENDER_RING, \
	65	GEN_DEFAULT_PIPEOFFSETS, \
	66	CURSOR_OFFSETS
	67
42f5551d	68	static const struct intel_device_info intel_i830_info = {
0eec8dc7	69	GEN2_FEATURES,
2e0d26f8	70	.platform = INTEL_I830,
0eec8dc7 CS	71	.is_mobile = 1, .cursor_needs_physical = 1,
0eec8dc7 CS	72	.num_pipes = 2, /* legal, last one wins */
42f5551d CW	73	};
42f5551d CW	74
2a307c2e	75	static const struct intel_device_info intel_i845g_info = {
0eec8dc7	76	GEN2_FEATURES,
2e0d26f8	77	.platform = INTEL_I845G,
42f5551d CW	78	};
	79
	80	static const struct intel_device_info intel_i85x_info = {
0eec8dc7	81	GEN2_FEATURES,
2e0d26f8	82	.platform = INTEL_I85X, .is_mobile = 1,
0eec8dc7	83	.num_pipes = 2, /* legal, last one wins */
42f5551d	84	.cursor_needs_physical = 1,
42f5551d	85	.has_fbc = 1,
42f5551d CW	86	};
	87
	88	static const struct intel_device_info intel_i865g_info = {
0eec8dc7	89	GEN2_FEATURES,
2e0d26f8	90	.platform = INTEL_I865G,
42f5551d CW	91	};
42f5551d CW	92
54d2a6a1 CS	93	#define GEN3_FEATURES \
54d2a6a1 CS	94	.gen = 3, .num_pipes = 2, \
804b8712	95	.has_gmch_display = 1, \
54d2a6a1 CS	96	.ring_mask = RENDER_RING, \
	97	GEN_DEFAULT_PIPEOFFSETS, \
	98	CURSOR_OFFSETS
	99
42f5551d	100	static const struct intel_device_info intel_i915g_info = {
54d2a6a1	101	GEN3_FEATURES,
2e0d26f8	102	.platform = INTEL_I915G, .cursor_needs_physical = 1,
42f5551d	103	.has_overlay = 1, .overlay_needs_physical = 1,
3177659a	104	.hws_needs_physical = 1,
9e176430	105	.unfenced_needs_alignment = 1,
42f5551d	106	};
a5ce929b	107
42f5551d	108	static const struct intel_device_info intel_i915gm_info = {
54d2a6a1	109	GEN3_FEATURES,
2e0d26f8	110	.platform = INTEL_I915GM,
54d2a6a1	111	.is_mobile = 1,
42f5551d CW	112	.cursor_needs_physical = 1,
	113	.has_overlay = 1, .overlay_needs_physical = 1,
	114	.supports_tv = 1,
	115	.has_fbc = 1,
3177659a	116	.hws_needs_physical = 1,
9e176430	117	.unfenced_needs_alignment = 1,
42f5551d	118	};
a5ce929b	119
42f5551d	120	static const struct intel_device_info intel_i945g_info = {
54d2a6a1	121	GEN3_FEATURES,
2e0d26f8	122	.platform = INTEL_I945G,
54d2a6a1	123	.has_hotplug = 1, .cursor_needs_physical = 1,
42f5551d	124	.has_overlay = 1, .overlay_needs_physical = 1,
3177659a	125	.hws_needs_physical = 1,
9e176430	126	.unfenced_needs_alignment = 1,
42f5551d	127	};
a5ce929b	128
42f5551d	129	static const struct intel_device_info intel_i945gm_info = {
54d2a6a1	130	GEN3_FEATURES,
2e0d26f8	131	.platform = INTEL_I945GM, .is_mobile = 1,
42f5551d CW	132	.has_hotplug = 1, .cursor_needs_physical = 1,
	133	.has_overlay = 1, .overlay_needs_physical = 1,
	134	.supports_tv = 1,
	135	.has_fbc = 1,
3177659a	136	.hws_needs_physical = 1,
9e176430	137	.unfenced_needs_alignment = 1,
42f5551d CW	138	};
42f5551d CW	139
a5ce929b JN	140	static const struct intel_device_info intel_g33_info = {
	141	GEN3_FEATURES,
	142	.platform = INTEL_G33,
	143	.has_hotplug = 1,
	144	.has_overlay = 1,
	145	};
	146
	147	static const struct intel_device_info intel_pineview_info = {
	148	GEN3_FEATURES,
73f67aa8	149	.platform = INTEL_PINEVIEW, .is_mobile = 1,
a5ce929b JN	150	.has_hotplug = 1,
	151	.has_overlay = 1,
	152	};
	153
4d495bea CS	154	#define GEN4_FEATURES \
	155	.gen = 4, .num_pipes = 2, \
	156	.has_hotplug = 1, \
804b8712	157	.has_gmch_display = 1, \
4d495bea CS	158	.ring_mask = RENDER_RING, \
	159	GEN_DEFAULT_PIPEOFFSETS, \
	160	CURSOR_OFFSETS
	161
42f5551d	162	static const struct intel_device_info intel_i965g_info = {
4d495bea	163	GEN4_FEATURES,
c0f86832	164	.platform = INTEL_I965G,
42f5551d	165	.has_overlay = 1,
3177659a	166	.hws_needs_physical = 1,
42f5551d CW	167	};
	168
	169	static const struct intel_device_info intel_i965gm_info = {
4d495bea	170	GEN4_FEATURES,
c0f86832	171	.platform = INTEL_I965GM,
4d495bea	172	.is_mobile = 1, .has_fbc = 1,
42f5551d CW	173	.has_overlay = 1,
42f5551d CW	174	.supports_tv = 1,
3177659a	175	.hws_needs_physical = 1,
42f5551d CW	176	};
42f5551d CW	177
42f5551d	178	static const struct intel_device_info intel_g45_info = {
4d495bea	179	GEN4_FEATURES,
f69c11ae	180	.platform = INTEL_G45,
4d495bea	181	.has_pipe_cxsr = 1,
42f5551d	182	.ring_mask = RENDER_RING \| BSD_RING,
42f5551d CW	183	};
	184
	185	static const struct intel_device_info intel_gm45_info = {
4d495bea	186	GEN4_FEATURES,
f69c11ae	187	.platform = INTEL_GM45,
3177659a	188	.is_mobile = 1, .has_fbc = 1,
4d495bea	189	.has_pipe_cxsr = 1,
42f5551d CW	190	.supports_tv = 1,
42f5551d CW	191	.ring_mask = RENDER_RING \| BSD_RING,
42f5551d CW	192	};
42f5551d CW	193
a1323380 CS	194	#define GEN5_FEATURES \
a1323380 CS	195	.gen = 5, .num_pipes = 2, \
3177659a	196	.has_hotplug = 1, \
b355f109	197	.has_gmbus_irq = 1, \
a1323380 CS	198	.ring_mask = RENDER_RING \| BSD_RING, \
	199	GEN_DEFAULT_PIPEOFFSETS, \
	200	CURSOR_OFFSETS
	201
42f5551d	202	static const struct intel_device_info intel_ironlake_d_info = {
a1323380	203	GEN5_FEATURES,
2e0d26f8	204	.platform = INTEL_IRONLAKE,
42f5551d CW	205	};
	206
	207	static const struct intel_device_info intel_ironlake_m_info = {
a1323380	208	GEN5_FEATURES,
2e0d26f8	209	.platform = INTEL_IRONLAKE,
a1323380	210	.is_mobile = 1,
42f5551d CW	211	};
42f5551d CW	212
07db6be7 CS	213	#define GEN6_FEATURES \
07db6be7 CS	214	.gen = 6, .num_pipes = 2, \
3177659a	215	.has_hotplug = 1, \
07db6be7 CS	216	.has_fbc = 1, \
	217	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING, \
	218	.has_llc = 1, \
86f3624b	219	.has_rc6 = 1, \
33b5bf82	220	.has_rc6p = 1, \
b355f109	221	.has_gmbus_irq = 1, \
e1a52536	222	.has_hw_contexts = 1, \
9e1d0e60	223	.has_aliasing_ppgtt = 1, \
07db6be7 CS	224	GEN_DEFAULT_PIPEOFFSETS, \
	225	CURSOR_OFFSETS
	226
42f5551d	227	static const struct intel_device_info intel_sandybridge_d_info = {
07db6be7	228	GEN6_FEATURES,
2e0d26f8	229	.platform = INTEL_SANDYBRIDGE,
42f5551d CW	230	};
	231
	232	static const struct intel_device_info intel_sandybridge_m_info = {
07db6be7	233	GEN6_FEATURES,
2e0d26f8	234	.platform = INTEL_SANDYBRIDGE,
07db6be7	235	.is_mobile = 1,
42f5551d CW	236	};
	237
	238	#define GEN7_FEATURES \
	239	.gen = 7, .num_pipes = 3, \
3177659a	240	.has_hotplug = 1, \
42f5551d CW	241	.has_fbc = 1, \
	242	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING, \
	243	.has_llc = 1, \
86f3624b	244	.has_rc6 = 1, \
33b5bf82	245	.has_rc6p = 1, \
b355f109	246	.has_gmbus_irq = 1, \
e1a52536	247	.has_hw_contexts = 1, \
9e1d0e60 MT	248	.has_aliasing_ppgtt = 1, \
9e1d0e60 MT	249	.has_full_ppgtt = 1, \
42f5551d CW	250	GEN_DEFAULT_PIPEOFFSETS, \
	251	IVB_CURSOR_OFFSETS
	252
	253	static const struct intel_device_info intel_ivybridge_d_info = {
	254	GEN7_FEATURES,
2e0d26f8	255	.platform = INTEL_IVYBRIDGE,
ca9c4523	256	.has_l3_dpf = 1,
42f5551d CW	257	};
	258
	259	static const struct intel_device_info intel_ivybridge_m_info = {
	260	GEN7_FEATURES,
2e0d26f8	261	.platform = INTEL_IVYBRIDGE,
42f5551d	262	.is_mobile = 1,
ca9c4523	263	.has_l3_dpf = 1,
42f5551d CW	264	};
	265
	266	static const struct intel_device_info intel_ivybridge_q_info = {
	267	GEN7_FEATURES,
2e0d26f8	268	.platform = INTEL_IVYBRIDGE,
42f5551d	269	.num_pipes = 0, /* legal, last one wins */
ca9c4523	270	.has_l3_dpf = 1,
42f5551d CW	271	};
42f5551d CW	272
8d9c20e1	273	static const struct intel_device_info intel_valleyview_info = {
2e0d26f8	274	.platform = INTEL_VALLEYVIEW,
eb6f771b RV	275	.gen = 7,
	276	.is_lp = 1,
	277	.num_pipes = 2,
	278	.has_psr = 1,
	279	.has_runtime_pm = 1,
	280	.has_rc6 = 1,
	281	.has_gmbus_irq = 1,
	282	.has_hw_contexts = 1,
	283	.has_gmch_display = 1,
	284	.has_hotplug = 1,
	285	.has_aliasing_ppgtt = 1,
	286	.has_full_ppgtt = 1,
	287	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING,
	288	.display_mmio_offset = VLV_DISPLAY_BASE,
	289	GEN_DEFAULT_PIPEOFFSETS,
	290	CURSOR_OFFSETS
42f5551d CW	291	};
	292
	293	#define HSW_FEATURES \
	294	GEN7_FEATURES, \
	295	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING, \
	296	.has_ddi = 1, \
6e3b84d8	297	.has_fpga_dbg = 1, \
4aa4c23f	298	.has_psr = 1, \
53233f08	299	.has_resource_streamer = 1, \
1d3fe53b	300	.has_dp_mst = 1, \
33b5bf82	301	.has_rc6p = 0 /* RC6p removed-by HSW */, \
4aa4c23f	302	.has_runtime_pm = 1
42f5551d	303
8d9c20e1	304	static const struct intel_device_info intel_haswell_info = {
42f5551d	305	HSW_FEATURES,
2e0d26f8	306	.platform = INTEL_HASWELL,
ca9c4523	307	.has_l3_dpf = 1,
42f5551d CW	308	};
42f5551d CW	309
42f5551d CW	310	#define BDW_FEATURES \
42f5551d CW	311	HSW_FEATURES, \
4586f1d0	312	BDW_COLORS, \
dfc5148f	313	.has_logical_ring_contexts = 1, \
9e1d0e60	314	.has_full_48bit_ppgtt = 1, \
dfc5148f	315	.has_64bit_reloc = 1
42f5551d	316
8d9c20e1	317	static const struct intel_device_info intel_broadwell_info = {
42f5551d CW	318	BDW_FEATURES,
42f5551d CW	319	.gen = 8,
2e0d26f8	320	.platform = INTEL_BROADWELL,
42f5551d CW	321	};
42f5551d CW	322
8d9c20e1	323	static const struct intel_device_info intel_broadwell_gt3_info = {
42f5551d CW	324	BDW_FEATURES,
42f5551d CW	325	.gen = 8,
2e0d26f8	326	.platform = INTEL_BROADWELL,
42f5551d CW	327	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING \| BSD2_RING,
	328	};
	329
42f5551d CW	330	static const struct intel_device_info intel_cherryview_info = {
42f5551d CW	331	.gen = 8, .num_pipes = 3,
3177659a	332	.has_hotplug = 1,
8727dc09	333	.is_lp = 1,
42f5551d	334	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING,
2e0d26f8	335	.platform = INTEL_CHERRYVIEW,
dfc5148f	336	.has_64bit_reloc = 1,
6e3b84d8	337	.has_psr = 1,
4aa4c23f	338	.has_runtime_pm = 1,
53233f08	339	.has_resource_streamer = 1,
86f3624b	340	.has_rc6 = 1,
b355f109	341	.has_gmbus_irq = 1,
e1a52536	342	.has_hw_contexts = 1,
4586f1d0	343	.has_logical_ring_contexts = 1,
804b8712	344	.has_gmch_display = 1,
9e1d0e60 MT	345	.has_aliasing_ppgtt = 1,
9e1d0e60 MT	346	.has_full_ppgtt = 1,
42f5551d CW	347	.display_mmio_offset = VLV_DISPLAY_BASE,
	348	GEN_CHV_PIPEOFFSETS,
	349	CURSOR_OFFSETS,
	350	CHV_COLORS,
	351	};
	352
	353	static const struct intel_device_info intel_skylake_info = {
	354	BDW_FEATURES,
2e0d26f8	355	.platform = INTEL_SKYLAKE,
42f5551d	356	.gen = 9,
3bacde19	357	.has_csr = 1,
3d810fbe	358	.has_guc = 1,
6f3fff60	359	.ddb_size = 896,
42f5551d CW	360	};
	361
	362	static const struct intel_device_info intel_skylake_gt3_info = {
	363	BDW_FEATURES,
2e0d26f8	364	.platform = INTEL_SKYLAKE,
42f5551d	365	.gen = 9,
3bacde19	366	.has_csr = 1,
3d810fbe	367	.has_guc = 1,
6f3fff60	368	.ddb_size = 896,
42f5551d CW	369	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING \| BSD2_RING,
	370	};
	371
80fa66b6 RV	372	#define GEN9_LP_FEATURES \
80fa66b6 RV	373	.gen = 9, \
3e4274f8	374	.is_lp = 1, \
80fa66b6 RV	375	.has_hotplug = 1, \
	376	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING, \
	377	.num_pipes = 3, \
	378	.has_64bit_reloc = 1, \
	379	.has_ddi = 1, \
	380	.has_fpga_dbg = 1, \
	381	.has_fbc = 1, \
	382	.has_runtime_pm = 1, \
	383	.has_pooled_eu = 0, \
	384	.has_csr = 1, \
	385	.has_resource_streamer = 1, \
	386	.has_rc6 = 1, \
	387	.has_dp_mst = 1, \
	388	.has_gmbus_irq = 1, \
	389	.has_hw_contexts = 1, \
	390	.has_logical_ring_contexts = 1, \
	391	.has_guc = 1, \
	392	.has_decoupled_mmio = 1, \
9e1d0e60 MT	393	.has_aliasing_ppgtt = 1, \
	394	.has_full_ppgtt = 1, \
	395	.has_full_48bit_ppgtt = 1, \
80fa66b6 RV	396	GEN_DEFAULT_PIPEOFFSETS, \
	397	IVB_CURSOR_OFFSETS, \
	398	BDW_COLORS
	399
42f5551d	400	static const struct intel_device_info intel_broxton_info = {
80fa66b6	401	GEN9_LP_FEATURES,
2e0d26f8	402	.platform = INTEL_BROXTON,
6f3fff60	403	.ddb_size = 512,
42f5551d CW	404	};
42f5551d CW	405
c22097fa	406	static const struct intel_device_info intel_geminilake_info = {
c22097fa	407	GEN9_LP_FEATURES,
2e0d26f8 JN	408	.platform = INTEL_GEMINILAKE,
2e0d26f8 JN	409	.is_alpha_support = 1,
c22097fa ACO	410	.ddb_size = 1024,
	411	};
	412
42f5551d CW	413	static const struct intel_device_info intel_kabylake_info = {
42f5551d CW	414	BDW_FEATURES,
2e0d26f8	415	.platform = INTEL_KABYLAKE,
42f5551d	416	.gen = 9,
3bacde19	417	.has_csr = 1,
3d810fbe	418	.has_guc = 1,
6f3fff60	419	.ddb_size = 896,
42f5551d CW	420	};
	421
	422	static const struct intel_device_info intel_kabylake_gt3_info = {
	423	BDW_FEATURES,
2e0d26f8	424	.platform = INTEL_KABYLAKE,
42f5551d	425	.gen = 9,
3bacde19	426	.has_csr = 1,
3d810fbe	427	.has_guc = 1,
6f3fff60	428	.ddb_size = 896,
42f5551d CW	429	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING \| BSD2_RING,
	430	};
	431
	432	/*
	433	* Make sure any device matches here are from most specific to most
	434	* general. For example, since the Quanta match is based on the subsystem
	435	* and subvendor IDs, we need it to come before the more general IVB
	436	* PCI ID matches, otherwise we'll use the wrong info struct above.
	437	*/
	438	static const struct pci_device_id pciidlist[] = {
	439	INTEL_I830_IDS(&intel_i830_info),
2a307c2e	440	INTEL_I845G_IDS(&intel_i845g_info),
42f5551d CW	441	INTEL_I85X_IDS(&intel_i85x_info),
	442	INTEL_I865G_IDS(&intel_i865g_info),
	443	INTEL_I915G_IDS(&intel_i915g_info),
	444	INTEL_I915GM_IDS(&intel_i915gm_info),
	445	INTEL_I945G_IDS(&intel_i945g_info),
	446	INTEL_I945GM_IDS(&intel_i945gm_info),
	447	INTEL_I965G_IDS(&intel_i965g_info),
	448	INTEL_G33_IDS(&intel_g33_info),
	449	INTEL_I965GM_IDS(&intel_i965gm_info),
	450	INTEL_GM45_IDS(&intel_gm45_info),
	451	INTEL_G45_IDS(&intel_g45_info),
	452	INTEL_PINEVIEW_IDS(&intel_pineview_info),
	453	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
	454	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
	455	INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
	456	INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
	457	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
	458	INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
	459	INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
8d9c20e1 CS	460	INTEL_HSW_IDS(&intel_haswell_info),
	461	INTEL_VLV_IDS(&intel_valleyview_info),
	462	INTEL_BDW_GT12_IDS(&intel_broadwell_info),
	463	INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
98b2f01c	464	INTEL_BDW_RSVD_IDS(&intel_broadwell_info),
42f5551d CW	465	INTEL_CHV_IDS(&intel_cherryview_info),
	466	INTEL_SKL_GT1_IDS(&intel_skylake_info),
	467	INTEL_SKL_GT2_IDS(&intel_skylake_info),
	468	INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
	469	INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
	470	INTEL_BXT_IDS(&intel_broxton_info),
8363e3c3	471	INTEL_GLK_IDS(&intel_geminilake_info),
42f5551d CW	472	INTEL_KBL_GT1_IDS(&intel_kabylake_info),
	473	INTEL_KBL_GT2_IDS(&intel_kabylake_info),
	474	INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
	475	INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
	476	{0, 0, 0}
	477	};
	478	MODULE_DEVICE_TABLE(pci, pciidlist);
	479
42f5551d CW	480	static int i915_pci_probe(struct pci_dev pdev, const struct pci_device_id ent)
	481	{
	482	struct intel_device_info *intel_info =
	483	(struct intel_device_info *) ent->driver_data;
	484
c007fb4a JN	485	if (IS_ALPHA_SUPPORT(intel_info) && !i915.alpha_support) {
	486	DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
	487	"See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
	488	"to enable support in this kernel version, or check for kernel updates.\n");
42f5551d CW	489	return -ENODEV;
	490	}
	491
	492	/* Only bind to function 0 of the device. Early generations
	493	* used function 1 as a placeholder for multi-head. This causes
	494	* us confusion instead, especially on the systems where both
	495	* functions have the same PCI-ID!
	496	*/
	497	if (PCI_FUNC(pdev->devfn))
	498	return -ENODEV;
	499
	500	/*
	501	* apple-gmux is needed on dual GPU MacBook Pro
	502	* to probe the panel if we're the inactive GPU.
	503	*/
	504	if (vga_switcheroo_client_probe_defer(pdev))
	505	return -EPROBE_DEFER;
	506
	507	return i915_driver_load(pdev, ent);
	508	}
	509
42f5551d CW	510	static void i915_pci_remove(struct pci_dev *pdev)
	511	{
	512	struct drm_device *dev = pci_get_drvdata(pdev);
	513
	514	i915_driver_unload(dev);
	515	drm_dev_unref(dev);
	516	}
	517
a09d0ba1	518	static struct pci_driver i915_pci_driver = {
42f5551d CW	519	.name = DRIVER_NAME,
	520	.id_table = pciidlist,
	521	.probe = i915_pci_probe,
	522	.remove = i915_pci_remove,
	523	.driver.pm = &i915_pm_ops,
	524	};
a09d0ba1 CW	525
	526	static int __init i915_init(void)
	527	{
	528	bool use_kms = true;
	529
	530	/*
	531	* Enable KMS by default, unless explicitly overriden by
	532	* either the i915.modeset prarameter or by the
	533	* vga_text_mode_force boot option.
	534	*/
	535
	536	if (i915.modeset == 0)
	537	use_kms = false;
	538
	539	if (vgacon_text_force() && i915.modeset == -1)
	540	use_kms = false;
	541
	542	if (!use_kms) {
	543	/* Silently fail loading to not upset userspace. */
	544	DRM_DEBUG_DRIVER("KMS disabled.\n");
	545	return 0;
	546	}
	547
	548	return pci_register_driver(&i915_pci_driver);
	549	}
	550
	551	static void __exit i915_exit(void)
	552	{
	553	if (!i915_pci_driver.driver.owner)
	554	return;
	555
	556	pci_unregister_driver(&i915_pci_driver);
	557	}
	558
	559	module_init(i915_init);
	560	module_exit(i915_exit);
	561
	562	MODULE_AUTHOR("Tungsten Graphics, Inc.");
	563	MODULE_AUTHOR("Intel Corporation");
	564
	565	MODULE_DESCRIPTION(DRIVER_DESC);
	566	MODULE_LICENSE("GPL and additional rights");