[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / i915_pci.c

/*
 * Copyright © 2016 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 */

#include <linux/console.h>
#include <linux/vgaarb.h>
#include <linux/vga_switcheroo.h>

#include "i915_drv.h"
#include "i915_selftest.h"

#define GEN_DEFAULT_PIPEOFFSETS \
	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
			  PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
			   TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }

#define GEN_CHV_PIPEOFFSETS \
	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
			  CHV_PIPE_C_OFFSET }, \
	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
			   CHV_TRANSCODER_C_OFFSET, }, \
	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
			     CHV_PALETTE_C_OFFSET }

#define CURSOR_OFFSETS \
	.cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }

#define IVB_CURSOR_OFFSETS \
	.cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }

#define BDW_COLORS \
	.color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
#define CHV_COLORS \
	.color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }

/* Keep in gen based order, and chronological order within a gen */
#define GEN2_FEATURES \
	.gen = 2, .num_pipes = 1, \
	.has_overlay = 1, .overlay_needs_physical = 1, \
	.has_gmch_display = 1, \
	.hws_needs_physical = 1, \
	.unfenced_needs_alignment = 1, \
	.ring_mask = RENDER_RING, \
	GEN_DEFAULT_PIPEOFFSETS, \
	CURSOR_OFFSETS

static const struct intel_device_info intel_i830_info = {
	GEN2_FEATURES,
	.platform = INTEL_I830,
	.is_mobile = 1, .cursor_needs_physical = 1,
	.num_pipes = 2, /* legal, last one wins */
};

static const struct intel_device_info intel_i845g_info = {
	GEN2_FEATURES,
	.platform = INTEL_I845G,
};

static const struct intel_device_info intel_i85x_info = {
	GEN2_FEATURES,
	.platform = INTEL_I85X, .is_mobile = 1,
	.num_pipes = 2, /* legal, last one wins */
	.cursor_needs_physical = 1,
	.has_fbc = 1,
};

static const struct intel_device_info intel_i865g_info = {
	GEN2_FEATURES,
	.platform = INTEL_I865G,
};

#define GEN3_FEATURES \
	.gen = 3, .num_pipes = 2, \
	.has_gmch_display = 1, \
	.ring_mask = RENDER_RING, \
	GEN_DEFAULT_PIPEOFFSETS, \
	CURSOR_OFFSETS

static const struct intel_device_info intel_i915g_info = {
	GEN3_FEATURES,
	.platform = INTEL_I915G, .cursor_needs_physical = 1,
	.has_overlay = 1, .overlay_needs_physical = 1,
	.hws_needs_physical = 1,
	.unfenced_needs_alignment = 1,
};

static const struct intel_device_info intel_i915gm_info = {
	GEN3_FEATURES,
	.platform = INTEL_I915GM,
	.is_mobile = 1,
	.cursor_needs_physical = 1,
	.has_overlay = 1, .overlay_needs_physical = 1,
	.supports_tv = 1,
	.has_fbc = 1,
	.hws_needs_physical = 1,
	.unfenced_needs_alignment = 1,
};

static const struct intel_device_info intel_i945g_info = {
	GEN3_FEATURES,
	.platform = INTEL_I945G,
	.has_hotplug = 1, .cursor_needs_physical = 1,
	.has_overlay = 1, .overlay_needs_physical = 1,
	.hws_needs_physical = 1,
	.unfenced_needs_alignment = 1,
};

static const struct intel_device_info intel_i945gm_info = {
	GEN3_FEATURES,
	.platform = INTEL_I945GM, .is_mobile = 1,
	.has_hotplug = 1, .cursor_needs_physical = 1,
	.has_overlay = 1, .overlay_needs_physical = 1,
	.supports_tv = 1,
	.has_fbc = 1,
	.hws_needs_physical = 1,
	.unfenced_needs_alignment = 1,
};

static const struct intel_device_info intel_g33_info = {
	GEN3_FEATURES,
	.platform = INTEL_G33,
	.has_hotplug = 1,
	.has_overlay = 1,
};

static const struct intel_device_info intel_pineview_info = {
	GEN3_FEATURES,
	.platform = INTEL_PINEVIEW, .is_mobile = 1,
	.has_hotplug = 1,
	.has_overlay = 1,
};

#define GEN4_FEATURES \
	.gen = 4, .num_pipes = 2, \
	.has_hotplug = 1, \
	.has_gmch_display = 1, \
	.ring_mask = RENDER_RING, \
	GEN_DEFAULT_PIPEOFFSETS, \
	CURSOR_OFFSETS

static const struct intel_device_info intel_i965g_info = {
	GEN4_FEATURES,
	.platform = INTEL_I965G,
	.has_overlay = 1,
	.hws_needs_physical = 1,
};

static const struct intel_device_info intel_i965gm_info = {
	GEN4_FEATURES,
	.platform = INTEL_I965GM,
	.is_mobile = 1, .has_fbc = 1,
	.has_overlay = 1,
	.supports_tv = 1,
	.hws_needs_physical = 1,
};

static const struct intel_device_info intel_g45_info = {
	GEN4_FEATURES,
	.platform = INTEL_G45,
	.has_pipe_cxsr = 1,
	.ring_mask = RENDER_RING | BSD_RING,
};

static const struct intel_device_info intel_gm45_info = {
	GEN4_FEATURES,
	.platform = INTEL_GM45,
	.is_mobile = 1, .has_fbc = 1,
	.has_pipe_cxsr = 1,
	.supports_tv = 1,
	.ring_mask = RENDER_RING | BSD_RING,
};

#define GEN5_FEATURES \
	.gen = 5, .num_pipes = 2, \
	.has_hotplug = 1, \
	.has_gmbus_irq = 1, \
	.ring_mask = RENDER_RING | BSD_RING, \
	GEN_DEFAULT_PIPEOFFSETS, \
	CURSOR_OFFSETS

static const struct intel_device_info intel_ironlake_d_info = {
	GEN5_FEATURES,
	.platform = INTEL_IRONLAKE,
};

static const struct intel_device_info intel_ironlake_m_info = {
	GEN5_FEATURES,
	.platform = INTEL_IRONLAKE,
	.is_mobile = 1, .has_fbc = 1,
};

#define GEN6_FEATURES \
	.gen = 6, .num_pipes = 2, \
	.has_hotplug = 1, \
	.has_fbc = 1, \
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
	.has_llc = 1, \
	.has_rc6 = 1, \
	.has_rc6p = 1, \
	.has_gmbus_irq = 1, \
	.has_hw_contexts = 1, \
	.has_aliasing_ppgtt = 1, \
	GEN_DEFAULT_PIPEOFFSETS, \
	CURSOR_OFFSETS

static const struct intel_device_info intel_sandybridge_d_info = {
	GEN6_FEATURES,
	.platform = INTEL_SANDYBRIDGE,
};

static const struct intel_device_info intel_sandybridge_m_info = {
	GEN6_FEATURES,
	.platform = INTEL_SANDYBRIDGE,
	.is_mobile = 1,
};

#define GEN7_FEATURES  \
	.gen = 7, .num_pipes = 3, \
	.has_hotplug = 1, \
	.has_fbc = 1, \
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
	.has_llc = 1, \
	.has_rc6 = 1, \
	.has_rc6p = 1, \
	.has_gmbus_irq = 1, \
	.has_hw_contexts = 1, \
	.has_aliasing_ppgtt = 1, \
	.has_full_ppgtt = 1, \
	GEN_DEFAULT_PIPEOFFSETS, \
	IVB_CURSOR_OFFSETS

static const struct intel_device_info intel_ivybridge_d_info = {
	GEN7_FEATURES,
	.platform = INTEL_IVYBRIDGE,
	.has_l3_dpf = 1,
};

static const struct intel_device_info intel_ivybridge_m_info = {
	GEN7_FEATURES,
	.platform = INTEL_IVYBRIDGE,
	.is_mobile = 1,
	.has_l3_dpf = 1,
};

static const struct intel_device_info intel_ivybridge_q_info = {
	GEN7_FEATURES,
	.platform = INTEL_IVYBRIDGE,
	.num_pipes = 0, /* legal, last one wins */
	.has_l3_dpf = 1,
};

static const struct intel_device_info intel_valleyview_info = {
	.platform = INTEL_VALLEYVIEW,
	.gen = 7,
	.is_lp = 1,
	.num_pipes = 2,
	.has_psr = 1,
	.has_runtime_pm = 1,
	.has_rc6 = 1,
	.has_gmbus_irq = 1,
	.has_hw_contexts = 1,
	.has_gmch_display = 1,
	.has_hotplug = 1,
	.has_aliasing_ppgtt = 1,
	.has_full_ppgtt = 1,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
	.display_mmio_offset = VLV_DISPLAY_BASE,
	GEN_DEFAULT_PIPEOFFSETS,
	CURSOR_OFFSETS
};

#define HSW_FEATURES  \
	GEN7_FEATURES, \
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
	.has_ddi = 1, \
	.has_fpga_dbg = 1, \
	.has_psr = 1, \
	.has_resource_streamer = 1, \
	.has_dp_mst = 1, \
	.has_rc6p = 0 /* RC6p removed-by HSW */, \
	.has_runtime_pm = 1

static const struct intel_device_info intel_haswell_info = {
	HSW_FEATURES,
	.platform = INTEL_HASWELL,
	.has_l3_dpf = 1,
};

#define BDW_FEATURES \
	HSW_FEATURES, \
	BDW_COLORS, \
	.has_logical_ring_contexts = 1, \
	.has_full_48bit_ppgtt = 1, \
	.has_64bit_reloc = 1

static const struct intel_device_info intel_broadwell_info = {
	BDW_FEATURES,
	.gen = 8,
	.platform = INTEL_BROADWELL,
};

static const struct intel_device_info intel_broadwell_gt3_info = {
	BDW_FEATURES,
	.gen = 8,
	.platform = INTEL_BROADWELL,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};

static const struct intel_device_info intel_cherryview_info = {
	.gen = 8, .num_pipes = 3,
	.has_hotplug = 1,
	.is_lp = 1,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
	.platform = INTEL_CHERRYVIEW,
	.has_64bit_reloc = 1,
	.has_psr = 1,
	.has_runtime_pm = 1,
	.has_resource_streamer = 1,
	.has_rc6 = 1,
	.has_gmbus_irq = 1,
	.has_hw_contexts = 1,
	.has_logical_ring_contexts = 1,
	.has_gmch_display = 1,
	.has_aliasing_ppgtt = 1,
	.has_full_ppgtt = 1,
	.display_mmio_offset = VLV_DISPLAY_BASE,
	GEN_CHV_PIPEOFFSETS,
	CURSOR_OFFSETS,
	CHV_COLORS,
};

static const struct intel_device_info intel_skylake_info = {
	BDW_FEATURES,
	.platform = INTEL_SKYLAKE,
	.gen = 9,
	.has_csr = 1,
	.has_guc = 1,
	.ddb_size = 896,
};

static const struct intel_device_info intel_skylake_gt3_info = {
	BDW_FEATURES,
	.platform = INTEL_SKYLAKE,
	.gen = 9,
	.has_csr = 1,
	.has_guc = 1,
	.ddb_size = 896,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};

#define GEN9_LP_FEATURES \
	.gen = 9, \
	.is_lp = 1, \
	.has_hotplug = 1, \
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
	.num_pipes = 3, \
	.has_64bit_reloc = 1, \
	.has_ddi = 1, \
	.has_fpga_dbg = 1, \
	.has_fbc = 1, \
	.has_runtime_pm = 1, \
	.has_pooled_eu = 0, \
	.has_csr = 1, \
	.has_resource_streamer = 1, \
	.has_rc6 = 1, \
	.has_dp_mst = 1, \
	.has_gmbus_irq = 1, \
	.has_hw_contexts = 1, \
	.has_logical_ring_contexts = 1, \
	.has_guc = 1, \
	.has_aliasing_ppgtt = 1, \
	.has_full_ppgtt = 1, \
	.has_full_48bit_ppgtt = 1, \
	GEN_DEFAULT_PIPEOFFSETS, \
	IVB_CURSOR_OFFSETS, \
	BDW_COLORS

static const struct intel_device_info intel_broxton_info = {
	GEN9_LP_FEATURES,
	.platform = INTEL_BROXTON,
	.ddb_size = 512,
};

static const struct intel_device_info intel_geminilake_info = {
	GEN9_LP_FEATURES,
	.platform = INTEL_GEMINILAKE,
	.is_alpha_support = 1,
	.ddb_size = 1024,
	.color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
};

static const struct intel_device_info intel_kabylake_info = {
	BDW_FEATURES,
	.platform = INTEL_KABYLAKE,
	.gen = 9,
	.has_csr = 1,
	.has_guc = 1,
	.ddb_size = 896,
};

static const struct intel_device_info intel_kabylake_gt3_info = {
	BDW_FEATURES,
	.platform = INTEL_KABYLAKE,
	.gen = 9,
	.has_csr = 1,
	.has_guc = 1,
	.ddb_size = 896,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};

/*
 * Make sure any device matches here are from most specific to most
 * general.  For example, since the Quanta match is based on the subsystem
 * and subvendor IDs, we need it to come before the more general IVB
 * PCI ID matches, otherwise we'll use the wrong info struct above.
 */
static const struct pci_device_id pciidlist[] = {
	INTEL_I830_IDS(&intel_i830_info),
	INTEL_I845G_IDS(&intel_i845g_info),
	INTEL_I85X_IDS(&intel_i85x_info),
	INTEL_I865G_IDS(&intel_i865g_info),
	INTEL_I915G_IDS(&intel_i915g_info),
	INTEL_I915GM_IDS(&intel_i915gm_info),
	INTEL_I945G_IDS(&intel_i945g_info),
	INTEL_I945GM_IDS(&intel_i945gm_info),
	INTEL_I965G_IDS(&intel_i965g_info),
	INTEL_G33_IDS(&intel_g33_info),
	INTEL_I965GM_IDS(&intel_i965gm_info),
	INTEL_GM45_IDS(&intel_gm45_info),
	INTEL_G45_IDS(&intel_g45_info),
	INTEL_PINEVIEW_IDS(&intel_pineview_info),
	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
	INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
	INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
	INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
	INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
	INTEL_HSW_IDS(&intel_haswell_info),
	INTEL_VLV_IDS(&intel_valleyview_info),
	INTEL_BDW_GT12_IDS(&intel_broadwell_info),
	INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
	INTEL_BDW_RSVD_IDS(&intel_broadwell_info),
	INTEL_CHV_IDS(&intel_cherryview_info),
	INTEL_SKL_GT1_IDS(&intel_skylake_info),
	INTEL_SKL_GT2_IDS(&intel_skylake_info),
	INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
	INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
	INTEL_BXT_IDS(&intel_broxton_info),
	INTEL_GLK_IDS(&intel_geminilake_info),
	INTEL_KBL_GT1_IDS(&intel_kabylake_info),
	INTEL_KBL_GT2_IDS(&intel_kabylake_info),
	INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
	INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
	{0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, pciidlist);

static void i915_pci_remove(struct pci_dev *pdev)
{
	struct drm_device *dev = pci_get_drvdata(pdev);

	i915_driver_unload(dev);
	drm_dev_unref(dev);
}

static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	struct intel_device_info *intel_info =
		(struct intel_device_info *) ent->driver_data;
	int err;

	if (IS_ALPHA_SUPPORT(intel_info) && !i915.alpha_support) {
		DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
			 "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
			 "to enable support in this kernel version, or check for kernel updates.\n");
		return -ENODEV;
	}

	/* Only bind to function 0 of the device. Early generations
	 * used function 1 as a placeholder for multi-head. This causes
	 * us confusion instead, especially on the systems where both
	 * functions have the same PCI-ID!
	 */
	if (PCI_FUNC(pdev->devfn))
		return -ENODEV;

	/*
	 * apple-gmux is needed on dual GPU MacBook Pro
	 * to probe the panel if we're the inactive GPU.
	 */
	if (vga_switcheroo_client_probe_defer(pdev))
		return -EPROBE_DEFER;

	err = i915_driver_load(pdev, ent);
	if (err)
		return err;

	err = i915_live_selftests(pdev);
	if (err) {
		i915_pci_remove(pdev);
		return err > 0 ? -ENOTTY : err;
	}

	return 0;
}

static struct pci_driver i915_pci_driver = {
	.name = DRIVER_NAME,
	.id_table = pciidlist,
	.probe = i915_pci_probe,
	.remove = i915_pci_remove,
	.driver.pm = &i915_pm_ops,
};

static int __init i915_init(void)
{
	bool use_kms = true;
	int err;

	err = i915_mock_selftests();
	if (err)
		return err > 0 ? 0 : err;

	/*
	 * Enable KMS by default, unless explicitly overriden by
	 * either the i915.modeset prarameter or by the
	 * vga_text_mode_force boot option.
	 */

	if (i915.modeset == 0)
		use_kms = false;

	if (vgacon_text_force() && i915.modeset == -1)
		use_kms = false;

	if (!use_kms) {
		/* Silently fail loading to not upset userspace. */
		DRM_DEBUG_DRIVER("KMS disabled.\n");
		return 0;
	}

	return pci_register_driver(&i915_pci_driver);
}

static void __exit i915_exit(void)
{
	if (!i915_pci_driver.driver.owner)
		return;

	pci_unregister_driver(&i915_pci_driver);
}

module_init(i915_init);
module_exit(i915_exit);

MODULE_AUTHOR("Tungsten Graphics, Inc.");
MODULE_AUTHOR("Intel Corporation");

MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL and additional rights");
Commit	Line	Data
42f5551d CW	1	/*
	2	* Copyright © 2016 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	*/
	24
a09d0ba1	25	#include <linux/console.h>
42f5551d CW	26	#include <linux/vgaarb.h>
	27	#include <linux/vga_switcheroo.h>
	28
	29	#include "i915_drv.h"
953c7f82	30	#include "i915_selftest.h"
42f5551d CW	31
	32	#define GEN_DEFAULT_PIPEOFFSETS \
	33	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
	34	PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
	35	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
	36	TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
	37	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
	38
	39	#define GEN_CHV_PIPEOFFSETS \
	40	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
	41	CHV_PIPE_C_OFFSET }, \
	42	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
	43	CHV_TRANSCODER_C_OFFSET, }, \
	44	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
	45	CHV_PALETTE_C_OFFSET }
	46
	47	#define CURSOR_OFFSETS \
	48	.cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
	49
	50	#define IVB_CURSOR_OFFSETS \
	51	.cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
	52
	53	#define BDW_COLORS \
	54	.color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
	55	#define CHV_COLORS \
	56	.color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
	57
a5ce929b	58	/* Keep in gen based order, and chronological order within a gen */
0eec8dc7 CS	59	#define GEN2_FEATURES \
	60	.gen = 2, .num_pipes = 1, \
	61	.has_overlay = 1, .overlay_needs_physical = 1, \
804b8712	62	.has_gmch_display = 1, \
3177659a	63	.hws_needs_physical = 1, \
f4ce766f	64	.unfenced_needs_alignment = 1, \
0eec8dc7 CS	65	.ring_mask = RENDER_RING, \
	66	GEN_DEFAULT_PIPEOFFSETS, \
	67	CURSOR_OFFSETS
	68
42f5551d	69	static const struct intel_device_info intel_i830_info = {
0eec8dc7	70	GEN2_FEATURES,
2e0d26f8	71	.platform = INTEL_I830,
0eec8dc7 CS	72	.is_mobile = 1, .cursor_needs_physical = 1,
0eec8dc7 CS	73	.num_pipes = 2, /* legal, last one wins */
42f5551d CW	74	};
42f5551d CW	75
2a307c2e	76	static const struct intel_device_info intel_i845g_info = {
0eec8dc7	77	GEN2_FEATURES,
2e0d26f8	78	.platform = INTEL_I845G,
42f5551d CW	79	};
	80
	81	static const struct intel_device_info intel_i85x_info = {
0eec8dc7	82	GEN2_FEATURES,
2e0d26f8	83	.platform = INTEL_I85X, .is_mobile = 1,
0eec8dc7	84	.num_pipes = 2, /* legal, last one wins */
42f5551d	85	.cursor_needs_physical = 1,
42f5551d	86	.has_fbc = 1,
42f5551d CW	87	};
	88
	89	static const struct intel_device_info intel_i865g_info = {
0eec8dc7	90	GEN2_FEATURES,
2e0d26f8	91	.platform = INTEL_I865G,
42f5551d CW	92	};
42f5551d CW	93
54d2a6a1 CS	94	#define GEN3_FEATURES \
54d2a6a1 CS	95	.gen = 3, .num_pipes = 2, \
804b8712	96	.has_gmch_display = 1, \
54d2a6a1 CS	97	.ring_mask = RENDER_RING, \
	98	GEN_DEFAULT_PIPEOFFSETS, \
	99	CURSOR_OFFSETS
	100
42f5551d	101	static const struct intel_device_info intel_i915g_info = {
54d2a6a1	102	GEN3_FEATURES,
2e0d26f8	103	.platform = INTEL_I915G, .cursor_needs_physical = 1,
42f5551d	104	.has_overlay = 1, .overlay_needs_physical = 1,
3177659a	105	.hws_needs_physical = 1,
f4ce766f	106	.unfenced_needs_alignment = 1,
42f5551d	107	};
a5ce929b	108
42f5551d	109	static const struct intel_device_info intel_i915gm_info = {
54d2a6a1	110	GEN3_FEATURES,
2e0d26f8	111	.platform = INTEL_I915GM,
54d2a6a1	112	.is_mobile = 1,
42f5551d CW	113	.cursor_needs_physical = 1,
	114	.has_overlay = 1, .overlay_needs_physical = 1,
	115	.supports_tv = 1,
	116	.has_fbc = 1,
3177659a	117	.hws_needs_physical = 1,
f4ce766f	118	.unfenced_needs_alignment = 1,
42f5551d	119	};
a5ce929b	120
42f5551d	121	static const struct intel_device_info intel_i945g_info = {
54d2a6a1	122	GEN3_FEATURES,
2e0d26f8	123	.platform = INTEL_I945G,
54d2a6a1	124	.has_hotplug = 1, .cursor_needs_physical = 1,
42f5551d	125	.has_overlay = 1, .overlay_needs_physical = 1,
3177659a	126	.hws_needs_physical = 1,
f4ce766f	127	.unfenced_needs_alignment = 1,
42f5551d	128	};
a5ce929b	129
42f5551d	130	static const struct intel_device_info intel_i945gm_info = {
54d2a6a1	131	GEN3_FEATURES,
2e0d26f8	132	.platform = INTEL_I945GM, .is_mobile = 1,
42f5551d CW	133	.has_hotplug = 1, .cursor_needs_physical = 1,
	134	.has_overlay = 1, .overlay_needs_physical = 1,
	135	.supports_tv = 1,
	136	.has_fbc = 1,
3177659a	137	.hws_needs_physical = 1,
f4ce766f	138	.unfenced_needs_alignment = 1,
42f5551d CW	139	};
42f5551d CW	140
a5ce929b JN	141	static const struct intel_device_info intel_g33_info = {
	142	GEN3_FEATURES,
	143	.platform = INTEL_G33,
	144	.has_hotplug = 1,
	145	.has_overlay = 1,
	146	};
	147
	148	static const struct intel_device_info intel_pineview_info = {
	149	GEN3_FEATURES,
73f67aa8	150	.platform = INTEL_PINEVIEW, .is_mobile = 1,
a5ce929b JN	151	.has_hotplug = 1,
	152	.has_overlay = 1,
	153	};
	154
4d495bea CS	155	#define GEN4_FEATURES \
	156	.gen = 4, .num_pipes = 2, \
	157	.has_hotplug = 1, \
804b8712	158	.has_gmch_display = 1, \
4d495bea CS	159	.ring_mask = RENDER_RING, \
	160	GEN_DEFAULT_PIPEOFFSETS, \
	161	CURSOR_OFFSETS
	162
42f5551d	163	static const struct intel_device_info intel_i965g_info = {
4d495bea	164	GEN4_FEATURES,
c0f86832	165	.platform = INTEL_I965G,
42f5551d	166	.has_overlay = 1,
3177659a	167	.hws_needs_physical = 1,
42f5551d CW	168	};
	169
	170	static const struct intel_device_info intel_i965gm_info = {
4d495bea	171	GEN4_FEATURES,
c0f86832	172	.platform = INTEL_I965GM,
4d495bea	173	.is_mobile = 1, .has_fbc = 1,
42f5551d CW	174	.has_overlay = 1,
42f5551d CW	175	.supports_tv = 1,
3177659a	176	.hws_needs_physical = 1,
42f5551d CW	177	};
42f5551d CW	178
42f5551d	179	static const struct intel_device_info intel_g45_info = {
4d495bea	180	GEN4_FEATURES,
f69c11ae	181	.platform = INTEL_G45,
4d495bea	182	.has_pipe_cxsr = 1,
42f5551d	183	.ring_mask = RENDER_RING \| BSD_RING,
42f5551d CW	184	};
	185
	186	static const struct intel_device_info intel_gm45_info = {
4d495bea	187	GEN4_FEATURES,
f69c11ae	188	.platform = INTEL_GM45,
3177659a	189	.is_mobile = 1, .has_fbc = 1,
4d495bea	190	.has_pipe_cxsr = 1,
42f5551d CW	191	.supports_tv = 1,
42f5551d CW	192	.ring_mask = RENDER_RING \| BSD_RING,
42f5551d CW	193	};
42f5551d CW	194
a1323380 CS	195	#define GEN5_FEATURES \
a1323380 CS	196	.gen = 5, .num_pipes = 2, \
3177659a	197	.has_hotplug = 1, \
b355f109	198	.has_gmbus_irq = 1, \
a1323380 CS	199	.ring_mask = RENDER_RING \| BSD_RING, \
	200	GEN_DEFAULT_PIPEOFFSETS, \
	201	CURSOR_OFFSETS
	202
42f5551d	203	static const struct intel_device_info intel_ironlake_d_info = {
a1323380	204	GEN5_FEATURES,
2e0d26f8	205	.platform = INTEL_IRONLAKE,
42f5551d CW	206	};
	207
	208	static const struct intel_device_info intel_ironlake_m_info = {
a1323380	209	GEN5_FEATURES,
2e0d26f8	210	.platform = INTEL_IRONLAKE,
27fe407c	211	.is_mobile = 1, .has_fbc = 1,
42f5551d CW	212	};
42f5551d CW	213
07db6be7 CS	214	#define GEN6_FEATURES \
07db6be7 CS	215	.gen = 6, .num_pipes = 2, \
3177659a	216	.has_hotplug = 1, \
07db6be7 CS	217	.has_fbc = 1, \
	218	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING, \
	219	.has_llc = 1, \
86f3624b	220	.has_rc6 = 1, \
33b5bf82	221	.has_rc6p = 1, \
b355f109	222	.has_gmbus_irq = 1, \
e1a52536	223	.has_hw_contexts = 1, \
9e1d0e60	224	.has_aliasing_ppgtt = 1, \
07db6be7 CS	225	GEN_DEFAULT_PIPEOFFSETS, \
	226	CURSOR_OFFSETS
	227
42f5551d	228	static const struct intel_device_info intel_sandybridge_d_info = {
07db6be7	229	GEN6_FEATURES,
2e0d26f8	230	.platform = INTEL_SANDYBRIDGE,
42f5551d CW	231	};
	232
	233	static const struct intel_device_info intel_sandybridge_m_info = {
07db6be7	234	GEN6_FEATURES,
2e0d26f8	235	.platform = INTEL_SANDYBRIDGE,
07db6be7	236	.is_mobile = 1,
42f5551d CW	237	};
	238
	239	#define GEN7_FEATURES \
	240	.gen = 7, .num_pipes = 3, \
3177659a	241	.has_hotplug = 1, \
42f5551d CW	242	.has_fbc = 1, \
	243	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING, \
	244	.has_llc = 1, \
86f3624b	245	.has_rc6 = 1, \
33b5bf82	246	.has_rc6p = 1, \
b355f109	247	.has_gmbus_irq = 1, \
e1a52536	248	.has_hw_contexts = 1, \
9e1d0e60 MT	249	.has_aliasing_ppgtt = 1, \
9e1d0e60 MT	250	.has_full_ppgtt = 1, \
42f5551d CW	251	GEN_DEFAULT_PIPEOFFSETS, \
	252	IVB_CURSOR_OFFSETS
	253
	254	static const struct intel_device_info intel_ivybridge_d_info = {
	255	GEN7_FEATURES,
2e0d26f8	256	.platform = INTEL_IVYBRIDGE,
ca9c4523	257	.has_l3_dpf = 1,
42f5551d CW	258	};
	259
	260	static const struct intel_device_info intel_ivybridge_m_info = {
	261	GEN7_FEATURES,
2e0d26f8	262	.platform = INTEL_IVYBRIDGE,
42f5551d	263	.is_mobile = 1,
ca9c4523	264	.has_l3_dpf = 1,
42f5551d CW	265	};
	266
	267	static const struct intel_device_info intel_ivybridge_q_info = {
	268	GEN7_FEATURES,
2e0d26f8	269	.platform = INTEL_IVYBRIDGE,
42f5551d	270	.num_pipes = 0, /* legal, last one wins */
ca9c4523	271	.has_l3_dpf = 1,
42f5551d CW	272	};
42f5551d CW	273
8d9c20e1	274	static const struct intel_device_info intel_valleyview_info = {
2e0d26f8	275	.platform = INTEL_VALLEYVIEW,
eb6f771b RV	276	.gen = 7,
	277	.is_lp = 1,
	278	.num_pipes = 2,
	279	.has_psr = 1,
	280	.has_runtime_pm = 1,
	281	.has_rc6 = 1,
	282	.has_gmbus_irq = 1,
	283	.has_hw_contexts = 1,
	284	.has_gmch_display = 1,
	285	.has_hotplug = 1,
	286	.has_aliasing_ppgtt = 1,
	287	.has_full_ppgtt = 1,
	288	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING,
	289	.display_mmio_offset = VLV_DISPLAY_BASE,
	290	GEN_DEFAULT_PIPEOFFSETS,
	291	CURSOR_OFFSETS
42f5551d CW	292	};
	293
	294	#define HSW_FEATURES \
	295	GEN7_FEATURES, \
	296	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING, \
	297	.has_ddi = 1, \
6e3b84d8	298	.has_fpga_dbg = 1, \
4aa4c23f	299	.has_psr = 1, \
53233f08	300	.has_resource_streamer = 1, \
1d3fe53b	301	.has_dp_mst = 1, \
33b5bf82	302	.has_rc6p = 0 /* RC6p removed-by HSW */, \
4aa4c23f	303	.has_runtime_pm = 1
42f5551d	304
8d9c20e1	305	static const struct intel_device_info intel_haswell_info = {
42f5551d	306	HSW_FEATURES,
2e0d26f8	307	.platform = INTEL_HASWELL,
ca9c4523	308	.has_l3_dpf = 1,
42f5551d CW	309	};
42f5551d CW	310
42f5551d CW	311	#define BDW_FEATURES \
42f5551d CW	312	HSW_FEATURES, \
4586f1d0	313	BDW_COLORS, \
dfc5148f	314	.has_logical_ring_contexts = 1, \
9e1d0e60	315	.has_full_48bit_ppgtt = 1, \
dfc5148f	316	.has_64bit_reloc = 1
42f5551d	317
8d9c20e1	318	static const struct intel_device_info intel_broadwell_info = {
42f5551d CW	319	BDW_FEATURES,
42f5551d CW	320	.gen = 8,
2e0d26f8	321	.platform = INTEL_BROADWELL,
42f5551d CW	322	};
42f5551d CW	323
8d9c20e1	324	static const struct intel_device_info intel_broadwell_gt3_info = {
42f5551d CW	325	BDW_FEATURES,
42f5551d CW	326	.gen = 8,
2e0d26f8	327	.platform = INTEL_BROADWELL,
42f5551d CW	328	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING \| BSD2_RING,
	329	};
	330
42f5551d CW	331	static const struct intel_device_info intel_cherryview_info = {
42f5551d CW	332	.gen = 8, .num_pipes = 3,
3177659a	333	.has_hotplug = 1,
8727dc09	334	.is_lp = 1,
42f5551d	335	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING,
2e0d26f8	336	.platform = INTEL_CHERRYVIEW,
dfc5148f	337	.has_64bit_reloc = 1,
6e3b84d8	338	.has_psr = 1,
4aa4c23f	339	.has_runtime_pm = 1,
53233f08	340	.has_resource_streamer = 1,
86f3624b	341	.has_rc6 = 1,
b355f109	342	.has_gmbus_irq = 1,
e1a52536	343	.has_hw_contexts = 1,
4586f1d0	344	.has_logical_ring_contexts = 1,
804b8712	345	.has_gmch_display = 1,
9e1d0e60 MT	346	.has_aliasing_ppgtt = 1,
9e1d0e60 MT	347	.has_full_ppgtt = 1,
42f5551d CW	348	.display_mmio_offset = VLV_DISPLAY_BASE,
	349	GEN_CHV_PIPEOFFSETS,
	350	CURSOR_OFFSETS,
	351	CHV_COLORS,
	352	};
	353
	354	static const struct intel_device_info intel_skylake_info = {
	355	BDW_FEATURES,
2e0d26f8	356	.platform = INTEL_SKYLAKE,
42f5551d	357	.gen = 9,
3bacde19	358	.has_csr = 1,
3d810fbe	359	.has_guc = 1,
6f3fff60	360	.ddb_size = 896,
42f5551d CW	361	};
	362
	363	static const struct intel_device_info intel_skylake_gt3_info = {
	364	BDW_FEATURES,
2e0d26f8	365	.platform = INTEL_SKYLAKE,
42f5551d	366	.gen = 9,
3bacde19	367	.has_csr = 1,
3d810fbe	368	.has_guc = 1,
6f3fff60	369	.ddb_size = 896,
42f5551d CW	370	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING \| BSD2_RING,
	371	};
	372
80fa66b6 RV	373	#define GEN9_LP_FEATURES \
80fa66b6 RV	374	.gen = 9, \
3e4274f8	375	.is_lp = 1, \
80fa66b6 RV	376	.has_hotplug = 1, \
	377	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING, \
	378	.num_pipes = 3, \
	379	.has_64bit_reloc = 1, \
	380	.has_ddi = 1, \
	381	.has_fpga_dbg = 1, \
	382	.has_fbc = 1, \
	383	.has_runtime_pm = 1, \
	384	.has_pooled_eu = 0, \
	385	.has_csr = 1, \
	386	.has_resource_streamer = 1, \
	387	.has_rc6 = 1, \
	388	.has_dp_mst = 1, \
	389	.has_gmbus_irq = 1, \
	390	.has_hw_contexts = 1, \
	391	.has_logical_ring_contexts = 1, \
	392	.has_guc = 1, \
9e1d0e60 MT	393	.has_aliasing_ppgtt = 1, \
	394	.has_full_ppgtt = 1, \
	395	.has_full_48bit_ppgtt = 1, \
80fa66b6 RV	396	GEN_DEFAULT_PIPEOFFSETS, \
	397	IVB_CURSOR_OFFSETS, \
	398	BDW_COLORS
	399
42f5551d	400	static const struct intel_device_info intel_broxton_info = {
80fa66b6	401	GEN9_LP_FEATURES,
2e0d26f8	402	.platform = INTEL_BROXTON,
6f3fff60	403	.ddb_size = 512,
42f5551d CW	404	};
42f5551d CW	405
c22097fa	406	static const struct intel_device_info intel_geminilake_info = {
c22097fa	407	GEN9_LP_FEATURES,
2e0d26f8 JN	408	.platform = INTEL_GEMINILAKE,
2e0d26f8 JN	409	.is_alpha_support = 1,
c22097fa	410	.ddb_size = 1024,
9751bafc	411	.color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
c22097fa ACO	412	};
c22097fa ACO	413
42f5551d CW	414	static const struct intel_device_info intel_kabylake_info = {
42f5551d CW	415	BDW_FEATURES,
2e0d26f8	416	.platform = INTEL_KABYLAKE,
42f5551d	417	.gen = 9,
3bacde19	418	.has_csr = 1,
3d810fbe	419	.has_guc = 1,
6f3fff60	420	.ddb_size = 896,
42f5551d CW	421	};
	422
	423	static const struct intel_device_info intel_kabylake_gt3_info = {
	424	BDW_FEATURES,
2e0d26f8	425	.platform = INTEL_KABYLAKE,
42f5551d	426	.gen = 9,
3bacde19	427	.has_csr = 1,
3d810fbe	428	.has_guc = 1,
6f3fff60	429	.ddb_size = 896,
42f5551d CW	430	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING \| BSD2_RING,
	431	};
	432
	433	/*
	434	* Make sure any device matches here are from most specific to most
	435	* general. For example, since the Quanta match is based on the subsystem
	436	* and subvendor IDs, we need it to come before the more general IVB
	437	* PCI ID matches, otherwise we'll use the wrong info struct above.
	438	*/
	439	static const struct pci_device_id pciidlist[] = {
	440	INTEL_I830_IDS(&intel_i830_info),
2a307c2e	441	INTEL_I845G_IDS(&intel_i845g_info),
42f5551d CW	442	INTEL_I85X_IDS(&intel_i85x_info),
	443	INTEL_I865G_IDS(&intel_i865g_info),
	444	INTEL_I915G_IDS(&intel_i915g_info),
	445	INTEL_I915GM_IDS(&intel_i915gm_info),
	446	INTEL_I945G_IDS(&intel_i945g_info),
	447	INTEL_I945GM_IDS(&intel_i945gm_info),
	448	INTEL_I965G_IDS(&intel_i965g_info),
	449	INTEL_G33_IDS(&intel_g33_info),
	450	INTEL_I965GM_IDS(&intel_i965gm_info),
	451	INTEL_GM45_IDS(&intel_gm45_info),
	452	INTEL_G45_IDS(&intel_g45_info),
	453	INTEL_PINEVIEW_IDS(&intel_pineview_info),
	454	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
	455	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
	456	INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
	457	INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
	458	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
	459	INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
	460	INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
8d9c20e1 CS	461	INTEL_HSW_IDS(&intel_haswell_info),
	462	INTEL_VLV_IDS(&intel_valleyview_info),
	463	INTEL_BDW_GT12_IDS(&intel_broadwell_info),
	464	INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
98b2f01c	465	INTEL_BDW_RSVD_IDS(&intel_broadwell_info),
42f5551d CW	466	INTEL_CHV_IDS(&intel_cherryview_info),
	467	INTEL_SKL_GT1_IDS(&intel_skylake_info),
	468	INTEL_SKL_GT2_IDS(&intel_skylake_info),
	469	INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
	470	INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
	471	INTEL_BXT_IDS(&intel_broxton_info),
8363e3c3	472	INTEL_GLK_IDS(&intel_geminilake_info),
42f5551d CW	473	INTEL_KBL_GT1_IDS(&intel_kabylake_info),
	474	INTEL_KBL_GT2_IDS(&intel_kabylake_info),
	475	INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
	476	INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
	477	{0, 0, 0}
	478	};
	479	MODULE_DEVICE_TABLE(pci, pciidlist);
	480
953c7f82 CW	481	static void i915_pci_remove(struct pci_dev *pdev)
	482	{
	483	struct drm_device *dev = pci_get_drvdata(pdev);
	484
	485	i915_driver_unload(dev);
	486	drm_dev_unref(dev);
	487	}
	488
42f5551d CW	489	static int i915_pci_probe(struct pci_dev pdev, const struct pci_device_id ent)
	490	{
	491	struct intel_device_info *intel_info =
	492	(struct intel_device_info *) ent->driver_data;
953c7f82	493	int err;
42f5551d	494
c007fb4a JN	495	if (IS_ALPHA_SUPPORT(intel_info) && !i915.alpha_support) {
	496	DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
	497	"See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
	498	"to enable support in this kernel version, or check for kernel updates.\n");
42f5551d CW	499	return -ENODEV;
	500	}
	501
	502	/* Only bind to function 0 of the device. Early generations
	503	* used function 1 as a placeholder for multi-head. This causes
	504	* us confusion instead, especially on the systems where both
	505	* functions have the same PCI-ID!
	506	*/
	507	if (PCI_FUNC(pdev->devfn))
	508	return -ENODEV;
	509
	510	/*
	511	* apple-gmux is needed on dual GPU MacBook Pro
	512	* to probe the panel if we're the inactive GPU.
	513	*/
	514	if (vga_switcheroo_client_probe_defer(pdev))
	515	return -EPROBE_DEFER;
	516
953c7f82 CW	517	err = i915_driver_load(pdev, ent);
	518	if (err)
	519	return err;
42f5551d	520
953c7f82 CW	521	err = i915_live_selftests(pdev);
	522	if (err) {
	523	i915_pci_remove(pdev);
	524	return err > 0 ? -ENOTTY : err;
	525	}
42f5551d	526
953c7f82	527	return 0;
42f5551d CW	528	}
42f5551d CW	529
a09d0ba1	530	static struct pci_driver i915_pci_driver = {
42f5551d CW	531	.name = DRIVER_NAME,
	532	.id_table = pciidlist,
	533	.probe = i915_pci_probe,
	534	.remove = i915_pci_remove,
	535	.driver.pm = &i915_pm_ops,
	536	};
a09d0ba1 CW	537
	538	static int __init i915_init(void)
	539	{
	540	bool use_kms = true;
953c7f82 CW	541	int err;
	542
	543	err = i915_mock_selftests();
	544	if (err)
	545	return err > 0 ? 0 : err;
a09d0ba1 CW	546
	547	/*
	548	* Enable KMS by default, unless explicitly overriden by
	549	* either the i915.modeset prarameter or by the
	550	* vga_text_mode_force boot option.
	551	*/
	552
	553	if (i915.modeset == 0)
	554	use_kms = false;
	555
	556	if (vgacon_text_force() && i915.modeset == -1)
	557	use_kms = false;
	558
	559	if (!use_kms) {
	560	/* Silently fail loading to not upset userspace. */
	561	DRM_DEBUG_DRIVER("KMS disabled.\n");
	562	return 0;
	563	}
	564
	565	return pci_register_driver(&i915_pci_driver);
	566	}
	567
	568	static void __exit i915_exit(void)
	569	{
	570	if (!i915_pci_driver.driver.owner)
	571	return;
	572
	573	pci_unregister_driver(&i915_pci_driver);
	574	}
	575
	576	module_init(i915_init);
	577	module_exit(i915_exit);
	578
	579	MODULE_AUTHOR("Tungsten Graphics, Inc.");
	580	MODULE_AUTHOR("Intel Corporation");
	581
	582	MODULE_DESCRIPTION(DRIVER_DESC);
	583	MODULE_LICENSE("GPL and additional rights");