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42f5551d CW |
1 | /* |
2 | * Copyright © 2016 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
a09d0ba1 | 25 | #include <linux/console.h> |
42f5551d CW |
26 | #include <linux/vgaarb.h> |
27 | #include <linux/vga_switcheroo.h> | |
28 | ||
29 | #include "i915_drv.h" | |
953c7f82 | 30 | #include "i915_selftest.h" |
42f5551d CW |
31 | |
32 | #define GEN_DEFAULT_PIPEOFFSETS \ | |
33 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ | |
34 | PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \ | |
35 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ | |
36 | TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \ | |
37 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET } | |
38 | ||
39 | #define GEN_CHV_PIPEOFFSETS \ | |
40 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ | |
41 | CHV_PIPE_C_OFFSET }, \ | |
42 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ | |
43 | CHV_TRANSCODER_C_OFFSET, }, \ | |
44 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \ | |
45 | CHV_PALETTE_C_OFFSET } | |
46 | ||
47 | #define CURSOR_OFFSETS \ | |
48 | .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET } | |
49 | ||
50 | #define IVB_CURSOR_OFFSETS \ | |
51 | .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } | |
52 | ||
53 | #define BDW_COLORS \ | |
54 | .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 } | |
55 | #define CHV_COLORS \ | |
56 | .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 } | |
57 | ||
a5ce929b | 58 | /* Keep in gen based order, and chronological order within a gen */ |
0eec8dc7 CS |
59 | #define GEN2_FEATURES \ |
60 | .gen = 2, .num_pipes = 1, \ | |
61 | .has_overlay = 1, .overlay_needs_physical = 1, \ | |
804b8712 | 62 | .has_gmch_display = 1, \ |
3177659a | 63 | .hws_needs_physical = 1, \ |
f4ce766f | 64 | .unfenced_needs_alignment = 1, \ |
0eec8dc7 | 65 | .ring_mask = RENDER_RING, \ |
5d95c248 | 66 | .has_snoop = true, \ |
0eec8dc7 CS |
67 | GEN_DEFAULT_PIPEOFFSETS, \ |
68 | CURSOR_OFFSETS | |
69 | ||
5b54eddd | 70 | static const struct intel_device_info intel_i830_info __initconst = { |
0eec8dc7 | 71 | GEN2_FEATURES, |
2e0d26f8 | 72 | .platform = INTEL_I830, |
0eec8dc7 CS |
73 | .is_mobile = 1, .cursor_needs_physical = 1, |
74 | .num_pipes = 2, /* legal, last one wins */ | |
42f5551d CW |
75 | }; |
76 | ||
5b54eddd | 77 | static const struct intel_device_info intel_i845g_info __initconst = { |
0eec8dc7 | 78 | GEN2_FEATURES, |
2e0d26f8 | 79 | .platform = INTEL_I845G, |
42f5551d CW |
80 | }; |
81 | ||
5b54eddd | 82 | static const struct intel_device_info intel_i85x_info __initconst = { |
0eec8dc7 | 83 | GEN2_FEATURES, |
2e0d26f8 | 84 | .platform = INTEL_I85X, .is_mobile = 1, |
0eec8dc7 | 85 | .num_pipes = 2, /* legal, last one wins */ |
42f5551d | 86 | .cursor_needs_physical = 1, |
42f5551d | 87 | .has_fbc = 1, |
42f5551d CW |
88 | }; |
89 | ||
5b54eddd | 90 | static const struct intel_device_info intel_i865g_info __initconst = { |
0eec8dc7 | 91 | GEN2_FEATURES, |
2e0d26f8 | 92 | .platform = INTEL_I865G, |
42f5551d CW |
93 | }; |
94 | ||
54d2a6a1 CS |
95 | #define GEN3_FEATURES \ |
96 | .gen = 3, .num_pipes = 2, \ | |
804b8712 | 97 | .has_gmch_display = 1, \ |
54d2a6a1 | 98 | .ring_mask = RENDER_RING, \ |
5d95c248 | 99 | .has_snoop = true, \ |
54d2a6a1 CS |
100 | GEN_DEFAULT_PIPEOFFSETS, \ |
101 | CURSOR_OFFSETS | |
102 | ||
5b54eddd | 103 | static const struct intel_device_info intel_i915g_info __initconst = { |
54d2a6a1 | 104 | GEN3_FEATURES, |
2e0d26f8 | 105 | .platform = INTEL_I915G, .cursor_needs_physical = 1, |
42f5551d | 106 | .has_overlay = 1, .overlay_needs_physical = 1, |
3177659a | 107 | .hws_needs_physical = 1, |
f4ce766f | 108 | .unfenced_needs_alignment = 1, |
42f5551d | 109 | }; |
a5ce929b | 110 | |
5b54eddd | 111 | static const struct intel_device_info intel_i915gm_info __initconst = { |
54d2a6a1 | 112 | GEN3_FEATURES, |
2e0d26f8 | 113 | .platform = INTEL_I915GM, |
54d2a6a1 | 114 | .is_mobile = 1, |
42f5551d CW |
115 | .cursor_needs_physical = 1, |
116 | .has_overlay = 1, .overlay_needs_physical = 1, | |
117 | .supports_tv = 1, | |
118 | .has_fbc = 1, | |
3177659a | 119 | .hws_needs_physical = 1, |
f4ce766f | 120 | .unfenced_needs_alignment = 1, |
42f5551d | 121 | }; |
a5ce929b | 122 | |
5b54eddd | 123 | static const struct intel_device_info intel_i945g_info __initconst = { |
54d2a6a1 | 124 | GEN3_FEATURES, |
2e0d26f8 | 125 | .platform = INTEL_I945G, |
54d2a6a1 | 126 | .has_hotplug = 1, .cursor_needs_physical = 1, |
42f5551d | 127 | .has_overlay = 1, .overlay_needs_physical = 1, |
3177659a | 128 | .hws_needs_physical = 1, |
f4ce766f | 129 | .unfenced_needs_alignment = 1, |
42f5551d | 130 | }; |
a5ce929b | 131 | |
5b54eddd | 132 | static const struct intel_device_info intel_i945gm_info __initconst = { |
54d2a6a1 | 133 | GEN3_FEATURES, |
2e0d26f8 | 134 | .platform = INTEL_I945GM, .is_mobile = 1, |
42f5551d CW |
135 | .has_hotplug = 1, .cursor_needs_physical = 1, |
136 | .has_overlay = 1, .overlay_needs_physical = 1, | |
137 | .supports_tv = 1, | |
138 | .has_fbc = 1, | |
3177659a | 139 | .hws_needs_physical = 1, |
f4ce766f | 140 | .unfenced_needs_alignment = 1, |
42f5551d CW |
141 | }; |
142 | ||
5b54eddd | 143 | static const struct intel_device_info intel_g33_info __initconst = { |
a5ce929b JN |
144 | GEN3_FEATURES, |
145 | .platform = INTEL_G33, | |
146 | .has_hotplug = 1, | |
147 | .has_overlay = 1, | |
148 | }; | |
149 | ||
5b54eddd | 150 | static const struct intel_device_info intel_pineview_info __initconst = { |
a5ce929b | 151 | GEN3_FEATURES, |
73f67aa8 | 152 | .platform = INTEL_PINEVIEW, .is_mobile = 1, |
a5ce929b JN |
153 | .has_hotplug = 1, |
154 | .has_overlay = 1, | |
155 | }; | |
156 | ||
4d495bea CS |
157 | #define GEN4_FEATURES \ |
158 | .gen = 4, .num_pipes = 2, \ | |
159 | .has_hotplug = 1, \ | |
804b8712 | 160 | .has_gmch_display = 1, \ |
4d495bea | 161 | .ring_mask = RENDER_RING, \ |
5d95c248 | 162 | .has_snoop = true, \ |
4d495bea CS |
163 | GEN_DEFAULT_PIPEOFFSETS, \ |
164 | CURSOR_OFFSETS | |
165 | ||
5b54eddd | 166 | static const struct intel_device_info intel_i965g_info __initconst = { |
4d495bea | 167 | GEN4_FEATURES, |
c0f86832 | 168 | .platform = INTEL_I965G, |
42f5551d | 169 | .has_overlay = 1, |
3177659a | 170 | .hws_needs_physical = 1, |
df0700e5 | 171 | .has_snoop = false, |
42f5551d CW |
172 | }; |
173 | ||
5b54eddd | 174 | static const struct intel_device_info intel_i965gm_info __initconst = { |
4d495bea | 175 | GEN4_FEATURES, |
c0f86832 | 176 | .platform = INTEL_I965GM, |
4d495bea | 177 | .is_mobile = 1, .has_fbc = 1, |
42f5551d CW |
178 | .has_overlay = 1, |
179 | .supports_tv = 1, | |
3177659a | 180 | .hws_needs_physical = 1, |
df0700e5 | 181 | .has_snoop = false, |
42f5551d CW |
182 | }; |
183 | ||
5b54eddd | 184 | static const struct intel_device_info intel_g45_info __initconst = { |
4d495bea | 185 | GEN4_FEATURES, |
f69c11ae | 186 | .platform = INTEL_G45, |
4d495bea | 187 | .has_pipe_cxsr = 1, |
42f5551d | 188 | .ring_mask = RENDER_RING | BSD_RING, |
42f5551d CW |
189 | }; |
190 | ||
5b54eddd | 191 | static const struct intel_device_info intel_gm45_info __initconst = { |
4d495bea | 192 | GEN4_FEATURES, |
f69c11ae | 193 | .platform = INTEL_GM45, |
3177659a | 194 | .is_mobile = 1, .has_fbc = 1, |
4d495bea | 195 | .has_pipe_cxsr = 1, |
42f5551d CW |
196 | .supports_tv = 1, |
197 | .ring_mask = RENDER_RING | BSD_RING, | |
42f5551d CW |
198 | }; |
199 | ||
a1323380 CS |
200 | #define GEN5_FEATURES \ |
201 | .gen = 5, .num_pipes = 2, \ | |
3177659a | 202 | .has_hotplug = 1, \ |
a1323380 | 203 | .ring_mask = RENDER_RING | BSD_RING, \ |
5d95c248 | 204 | .has_snoop = true, \ |
a1323380 CS |
205 | GEN_DEFAULT_PIPEOFFSETS, \ |
206 | CURSOR_OFFSETS | |
207 | ||
5b54eddd | 208 | static const struct intel_device_info intel_ironlake_d_info __initconst = { |
a1323380 | 209 | GEN5_FEATURES, |
2e0d26f8 | 210 | .platform = INTEL_IRONLAKE, |
42f5551d CW |
211 | }; |
212 | ||
5b54eddd | 213 | static const struct intel_device_info intel_ironlake_m_info __initconst = { |
a1323380 | 214 | GEN5_FEATURES, |
2e0d26f8 | 215 | .platform = INTEL_IRONLAKE, |
c2d1a0ce | 216 | .is_mobile = 1, .has_fbc = 1, |
42f5551d CW |
217 | }; |
218 | ||
07db6be7 CS |
219 | #define GEN6_FEATURES \ |
220 | .gen = 6, .num_pipes = 2, \ | |
3177659a | 221 | .has_hotplug = 1, \ |
07db6be7 CS |
222 | .has_fbc = 1, \ |
223 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ | |
224 | .has_llc = 1, \ | |
86f3624b | 225 | .has_rc6 = 1, \ |
33b5bf82 | 226 | .has_rc6p = 1, \ |
9e1d0e60 | 227 | .has_aliasing_ppgtt = 1, \ |
07db6be7 CS |
228 | GEN_DEFAULT_PIPEOFFSETS, \ |
229 | CURSOR_OFFSETS | |
230 | ||
0890540e LL |
231 | #define SNB_D_PLATFORM \ |
232 | GEN6_FEATURES, \ | |
233 | .platform = INTEL_SANDYBRIDGE | |
234 | ||
5b54eddd | 235 | static const struct intel_device_info intel_sandybridge_d_gt1_info __initconst = { |
0890540e LL |
236 | SNB_D_PLATFORM, |
237 | .gt = 1, | |
42f5551d CW |
238 | }; |
239 | ||
5b54eddd | 240 | static const struct intel_device_info intel_sandybridge_d_gt2_info __initconst = { |
0890540e LL |
241 | SNB_D_PLATFORM, |
242 | .gt = 2, | |
243 | }; | |
244 | ||
245 | #define SNB_M_PLATFORM \ | |
246 | GEN6_FEATURES, \ | |
247 | .platform = INTEL_SANDYBRIDGE, \ | |
248 | .is_mobile = 1 | |
249 | ||
250 | ||
5b54eddd | 251 | static const struct intel_device_info intel_sandybridge_m_gt1_info __initconst = { |
0890540e LL |
252 | SNB_M_PLATFORM, |
253 | .gt = 1, | |
254 | }; | |
255 | ||
5b54eddd | 256 | static const struct intel_device_info intel_sandybridge_m_gt2_info __initconst = { |
0890540e LL |
257 | SNB_M_PLATFORM, |
258 | .gt = 2, | |
42f5551d CW |
259 | }; |
260 | ||
261 | #define GEN7_FEATURES \ | |
262 | .gen = 7, .num_pipes = 3, \ | |
3177659a | 263 | .has_hotplug = 1, \ |
42f5551d CW |
264 | .has_fbc = 1, \ |
265 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ | |
266 | .has_llc = 1, \ | |
86f3624b | 267 | .has_rc6 = 1, \ |
33b5bf82 | 268 | .has_rc6p = 1, \ |
9e1d0e60 MT |
269 | .has_aliasing_ppgtt = 1, \ |
270 | .has_full_ppgtt = 1, \ | |
42f5551d CW |
271 | GEN_DEFAULT_PIPEOFFSETS, \ |
272 | IVB_CURSOR_OFFSETS | |
273 | ||
0890540e LL |
274 | #define IVB_D_PLATFORM \ |
275 | GEN7_FEATURES, \ | |
276 | .platform = INTEL_IVYBRIDGE, \ | |
277 | .has_l3_dpf = 1 | |
278 | ||
5b54eddd | 279 | static const struct intel_device_info intel_ivybridge_d_gt1_info __initconst = { |
0890540e LL |
280 | IVB_D_PLATFORM, |
281 | .gt = 1, | |
42f5551d CW |
282 | }; |
283 | ||
5b54eddd | 284 | static const struct intel_device_info intel_ivybridge_d_gt2_info __initconst = { |
0890540e LL |
285 | IVB_D_PLATFORM, |
286 | .gt = 2, | |
287 | }; | |
288 | ||
289 | #define IVB_M_PLATFORM \ | |
290 | GEN7_FEATURES, \ | |
291 | .platform = INTEL_IVYBRIDGE, \ | |
292 | .is_mobile = 1, \ | |
293 | .has_l3_dpf = 1 | |
294 | ||
5b54eddd | 295 | static const struct intel_device_info intel_ivybridge_m_gt1_info __initconst = { |
0890540e LL |
296 | IVB_M_PLATFORM, |
297 | .gt = 1, | |
298 | }; | |
299 | ||
5b54eddd | 300 | static const struct intel_device_info intel_ivybridge_m_gt2_info __initconst = { |
0890540e LL |
301 | IVB_M_PLATFORM, |
302 | .gt = 2, | |
42f5551d CW |
303 | }; |
304 | ||
5b54eddd | 305 | static const struct intel_device_info intel_ivybridge_q_info __initconst = { |
42f5551d | 306 | GEN7_FEATURES, |
2e0d26f8 | 307 | .platform = INTEL_IVYBRIDGE, |
0890540e | 308 | .gt = 2, |
42f5551d | 309 | .num_pipes = 0, /* legal, last one wins */ |
ca9c4523 | 310 | .has_l3_dpf = 1, |
42f5551d CW |
311 | }; |
312 | ||
5b54eddd | 313 | static const struct intel_device_info intel_valleyview_info __initconst = { |
2e0d26f8 | 314 | .platform = INTEL_VALLEYVIEW, |
eb6f771b RV |
315 | .gen = 7, |
316 | .is_lp = 1, | |
317 | .num_pipes = 2, | |
318 | .has_psr = 1, | |
319 | .has_runtime_pm = 1, | |
320 | .has_rc6 = 1, | |
eb6f771b RV |
321 | .has_gmch_display = 1, |
322 | .has_hotplug = 1, | |
323 | .has_aliasing_ppgtt = 1, | |
324 | .has_full_ppgtt = 1, | |
5d95c248 | 325 | .has_snoop = true, |
eb6f771b RV |
326 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
327 | .display_mmio_offset = VLV_DISPLAY_BASE, | |
328 | GEN_DEFAULT_PIPEOFFSETS, | |
329 | CURSOR_OFFSETS | |
42f5551d CW |
330 | }; |
331 | ||
332 | #define HSW_FEATURES \ | |
333 | GEN7_FEATURES, \ | |
334 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ | |
335 | .has_ddi = 1, \ | |
6e3b84d8 | 336 | .has_fpga_dbg = 1, \ |
4aa4c23f | 337 | .has_psr = 1, \ |
53233f08 | 338 | .has_resource_streamer = 1, \ |
1d3fe53b | 339 | .has_dp_mst = 1, \ |
33b5bf82 | 340 | .has_rc6p = 0 /* RC6p removed-by HSW */, \ |
4aa4c23f | 341 | .has_runtime_pm = 1 |
42f5551d | 342 | |
0890540e LL |
343 | #define HSW_PLATFORM \ |
344 | HSW_FEATURES, \ | |
345 | .platform = INTEL_HASWELL, \ | |
346 | .has_l3_dpf = 1 | |
347 | ||
5b54eddd | 348 | static const struct intel_device_info intel_haswell_gt1_info __initconst = { |
0890540e LL |
349 | HSW_PLATFORM, |
350 | .gt = 1, | |
351 | }; | |
352 | ||
5b54eddd | 353 | static const struct intel_device_info intel_haswell_gt2_info __initconst = { |
0890540e LL |
354 | HSW_PLATFORM, |
355 | .gt = 2, | |
356 | }; | |
357 | ||
5b54eddd | 358 | static const struct intel_device_info intel_haswell_gt3_info __initconst = { |
0890540e LL |
359 | HSW_PLATFORM, |
360 | .gt = 3, | |
42f5551d CW |
361 | }; |
362 | ||
42f5551d CW |
363 | #define BDW_FEATURES \ |
364 | HSW_FEATURES, \ | |
4586f1d0 | 365 | BDW_COLORS, \ |
dfc5148f | 366 | .has_logical_ring_contexts = 1, \ |
9e1d0e60 | 367 | .has_full_48bit_ppgtt = 1, \ |
142bc7d9 MT |
368 | .has_64bit_reloc = 1, \ |
369 | .has_reset_engine = 1 | |
42f5551d | 370 | |
94829de4 RV |
371 | #define BDW_PLATFORM \ |
372 | BDW_FEATURES, \ | |
373 | .gen = 8, \ | |
374 | .platform = INTEL_BROADWELL | |
375 | ||
5b54eddd | 376 | static const struct intel_device_info intel_broadwell_gt1_info __initconst = { |
0890540e LL |
377 | BDW_PLATFORM, |
378 | .gt = 1, | |
379 | }; | |
380 | ||
5b54eddd | 381 | static const struct intel_device_info intel_broadwell_gt2_info __initconst = { |
94829de4 | 382 | BDW_PLATFORM, |
0890540e LL |
383 | .gt = 2, |
384 | }; | |
385 | ||
5b54eddd | 386 | static const struct intel_device_info intel_broadwell_rsvd_info __initconst = { |
0890540e LL |
387 | BDW_PLATFORM, |
388 | .gt = 3, | |
389 | /* According to the device ID those devices are GT3, they were | |
390 | * previously treated as not GT3, keep it like that. | |
391 | */ | |
42f5551d CW |
392 | }; |
393 | ||
5b54eddd | 394 | static const struct intel_device_info intel_broadwell_gt3_info __initconst = { |
94829de4 | 395 | BDW_PLATFORM, |
0890540e | 396 | .gt = 3, |
42f5551d CW |
397 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
398 | }; | |
399 | ||
5b54eddd | 400 | static const struct intel_device_info intel_cherryview_info __initconst = { |
42f5551d | 401 | .gen = 8, .num_pipes = 3, |
3177659a | 402 | .has_hotplug = 1, |
8727dc09 | 403 | .is_lp = 1, |
42f5551d | 404 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
2e0d26f8 | 405 | .platform = INTEL_CHERRYVIEW, |
dfc5148f | 406 | .has_64bit_reloc = 1, |
6e3b84d8 | 407 | .has_psr = 1, |
4aa4c23f | 408 | .has_runtime_pm = 1, |
53233f08 | 409 | .has_resource_streamer = 1, |
86f3624b | 410 | .has_rc6 = 1, |
4586f1d0 | 411 | .has_logical_ring_contexts = 1, |
804b8712 | 412 | .has_gmch_display = 1, |
9e1d0e60 MT |
413 | .has_aliasing_ppgtt = 1, |
414 | .has_full_ppgtt = 1, | |
142bc7d9 | 415 | .has_reset_engine = 1, |
5d95c248 | 416 | .has_snoop = true, |
42f5551d CW |
417 | .display_mmio_offset = VLV_DISPLAY_BASE, |
418 | GEN_CHV_PIPEOFFSETS, | |
419 | CURSOR_OFFSETS, | |
420 | CHV_COLORS, | |
421 | }; | |
422 | ||
94829de4 RV |
423 | #define SKL_PLATFORM \ |
424 | BDW_FEATURES, \ | |
425 | .gen = 9, \ | |
426 | .platform = INTEL_SKYLAKE, \ | |
427 | .has_csr = 1, \ | |
428 | .has_guc = 1, \ | |
429 | .ddb_size = 896 | |
430 | ||
5b54eddd | 431 | static const struct intel_device_info intel_skylake_gt1_info __initconst = { |
94829de4 | 432 | SKL_PLATFORM, |
0890540e | 433 | .gt = 1, |
42f5551d CW |
434 | }; |
435 | ||
5b54eddd | 436 | static const struct intel_device_info intel_skylake_gt2_info __initconst = { |
94829de4 | 437 | SKL_PLATFORM, |
0890540e LL |
438 | .gt = 2, |
439 | }; | |
440 | ||
441 | #define SKL_GT3_PLUS_PLATFORM \ | |
442 | SKL_PLATFORM, \ | |
443 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING | |
444 | ||
445 | ||
5b54eddd | 446 | static const struct intel_device_info intel_skylake_gt3_info __initconst = { |
0890540e LL |
447 | SKL_GT3_PLUS_PLATFORM, |
448 | .gt = 3, | |
449 | }; | |
450 | ||
5b54eddd | 451 | static const struct intel_device_info intel_skylake_gt4_info __initconst = { |
0890540e LL |
452 | SKL_GT3_PLUS_PLATFORM, |
453 | .gt = 4, | |
42f5551d CW |
454 | }; |
455 | ||
80fa66b6 RV |
456 | #define GEN9_LP_FEATURES \ |
457 | .gen = 9, \ | |
3e4274f8 | 458 | .is_lp = 1, \ |
80fa66b6 RV |
459 | .has_hotplug = 1, \ |
460 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ | |
461 | .num_pipes = 3, \ | |
462 | .has_64bit_reloc = 1, \ | |
463 | .has_ddi = 1, \ | |
464 | .has_fpga_dbg = 1, \ | |
465 | .has_fbc = 1, \ | |
466 | .has_runtime_pm = 1, \ | |
467 | .has_pooled_eu = 0, \ | |
468 | .has_csr = 1, \ | |
469 | .has_resource_streamer = 1, \ | |
470 | .has_rc6 = 1, \ | |
471 | .has_dp_mst = 1, \ | |
80fa66b6 RV |
472 | .has_logical_ring_contexts = 1, \ |
473 | .has_guc = 1, \ | |
9e1d0e60 MT |
474 | .has_aliasing_ppgtt = 1, \ |
475 | .has_full_ppgtt = 1, \ | |
476 | .has_full_48bit_ppgtt = 1, \ | |
142bc7d9 | 477 | .has_reset_engine = 1, \ |
5d95c248 | 478 | .has_snoop = true, \ |
e57f1c02 | 479 | .has_ipc = 1, \ |
80fa66b6 RV |
480 | GEN_DEFAULT_PIPEOFFSETS, \ |
481 | IVB_CURSOR_OFFSETS, \ | |
482 | BDW_COLORS | |
483 | ||
5b54eddd | 484 | static const struct intel_device_info intel_broxton_info __initconst = { |
80fa66b6 | 485 | GEN9_LP_FEATURES, |
2e0d26f8 | 486 | .platform = INTEL_BROXTON, |
6f3fff60 | 487 | .ddb_size = 512, |
42f5551d CW |
488 | }; |
489 | ||
5b54eddd | 490 | static const struct intel_device_info intel_geminilake_info __initconst = { |
c22097fa | 491 | GEN9_LP_FEATURES, |
2e0d26f8 | 492 | .platform = INTEL_GEMINILAKE, |
c22097fa | 493 | .ddb_size = 1024, |
9751bafc | 494 | .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 } |
c22097fa ACO |
495 | }; |
496 | ||
94829de4 RV |
497 | #define KBL_PLATFORM \ |
498 | BDW_FEATURES, \ | |
499 | .gen = 9, \ | |
500 | .platform = INTEL_KABYLAKE, \ | |
501 | .has_csr = 1, \ | |
502 | .has_guc = 1, \ | |
e57f1c02 | 503 | .has_ipc = 1, \ |
94829de4 RV |
504 | .ddb_size = 896 |
505 | ||
5b54eddd | 506 | static const struct intel_device_info intel_kabylake_gt1_info __initconst = { |
94829de4 | 507 | KBL_PLATFORM, |
0890540e LL |
508 | .gt = 1, |
509 | }; | |
510 | ||
5b54eddd | 511 | static const struct intel_device_info intel_kabylake_gt2_info __initconst = { |
0890540e LL |
512 | KBL_PLATFORM, |
513 | .gt = 2, | |
42f5551d CW |
514 | }; |
515 | ||
5b54eddd | 516 | static const struct intel_device_info intel_kabylake_gt3_info __initconst = { |
94829de4 | 517 | KBL_PLATFORM, |
0890540e | 518 | .gt = 3, |
42f5551d CW |
519 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
520 | }; | |
521 | ||
71851fa8 | 522 | #define CFL_PLATFORM \ |
71851fa8 RV |
523 | BDW_FEATURES, \ |
524 | .gen = 9, \ | |
525 | .platform = INTEL_COFFEELAKE, \ | |
84cd843e | 526 | .has_csr = 1, \ |
c0f82960 | 527 | .has_guc = 1, \ |
e57f1c02 | 528 | .has_ipc = 1, \ |
71851fa8 RV |
529 | .ddb_size = 896 |
530 | ||
5b54eddd | 531 | static const struct intel_device_info intel_coffeelake_gt1_info __initconst = { |
0890540e LL |
532 | CFL_PLATFORM, |
533 | .gt = 1, | |
534 | }; | |
535 | ||
5b54eddd | 536 | static const struct intel_device_info intel_coffeelake_gt2_info __initconst = { |
71851fa8 | 537 | CFL_PLATFORM, |
0890540e | 538 | .gt = 2, |
71851fa8 RV |
539 | }; |
540 | ||
5b54eddd | 541 | static const struct intel_device_info intel_coffeelake_gt3_info __initconst = { |
71851fa8 | 542 | CFL_PLATFORM, |
0890540e | 543 | .gt = 3, |
71851fa8 RV |
544 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
545 | }; | |
546 | ||
5b54eddd | 547 | static const struct intel_device_info intel_cannonlake_gt2_info __initconst = { |
413f3c19 RV |
548 | BDW_FEATURES, |
549 | .is_alpha_support = 1, | |
550 | .platform = INTEL_CANNONLAKE, | |
551 | .gen = 10, | |
0890540e | 552 | .gt = 2, |
413f3c19 | 553 | .ddb_size = 1024, |
cebfcead | 554 | .has_csr = 1, |
e57f1c02 | 555 | .has_ipc = 1, |
6602be0e | 556 | .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 } |
413f3c19 RV |
557 | }; |
558 | ||
42f5551d CW |
559 | /* |
560 | * Make sure any device matches here are from most specific to most | |
561 | * general. For example, since the Quanta match is based on the subsystem | |
562 | * and subvendor IDs, we need it to come before the more general IVB | |
563 | * PCI ID matches, otherwise we'll use the wrong info struct above. | |
564 | */ | |
565 | static const struct pci_device_id pciidlist[] = { | |
566 | INTEL_I830_IDS(&intel_i830_info), | |
2a307c2e | 567 | INTEL_I845G_IDS(&intel_i845g_info), |
42f5551d CW |
568 | INTEL_I85X_IDS(&intel_i85x_info), |
569 | INTEL_I865G_IDS(&intel_i865g_info), | |
570 | INTEL_I915G_IDS(&intel_i915g_info), | |
571 | INTEL_I915GM_IDS(&intel_i915gm_info), | |
572 | INTEL_I945G_IDS(&intel_i945g_info), | |
573 | INTEL_I945GM_IDS(&intel_i945gm_info), | |
574 | INTEL_I965G_IDS(&intel_i965g_info), | |
575 | INTEL_G33_IDS(&intel_g33_info), | |
576 | INTEL_I965GM_IDS(&intel_i965gm_info), | |
577 | INTEL_GM45_IDS(&intel_gm45_info), | |
578 | INTEL_G45_IDS(&intel_g45_info), | |
579 | INTEL_PINEVIEW_IDS(&intel_pineview_info), | |
580 | INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), | |
581 | INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), | |
0890540e LL |
582 | INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info), |
583 | INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info), | |
584 | INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info), | |
585 | INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info), | |
42f5551d | 586 | INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ |
0890540e LL |
587 | INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info), |
588 | INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info), | |
589 | INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info), | |
590 | INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info), | |
591 | INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info), | |
592 | INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info), | |
593 | INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info), | |
8d9c20e1 | 594 | INTEL_VLV_IDS(&intel_valleyview_info), |
0890540e LL |
595 | INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info), |
596 | INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info), | |
8d9c20e1 | 597 | INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info), |
0890540e | 598 | INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info), |
42f5551d | 599 | INTEL_CHV_IDS(&intel_cherryview_info), |
0890540e LL |
600 | INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info), |
601 | INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info), | |
42f5551d | 602 | INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), |
0890540e | 603 | INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info), |
42f5551d | 604 | INTEL_BXT_IDS(&intel_broxton_info), |
8363e3c3 | 605 | INTEL_GLK_IDS(&intel_geminilake_info), |
0890540e LL |
606 | INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info), |
607 | INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info), | |
42f5551d CW |
608 | INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info), |
609 | INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info), | |
0890540e LL |
610 | INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info), |
611 | INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info), | |
612 | INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info), | |
613 | INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info), | |
614 | INTEL_CNL_U_GT2_IDS(&intel_cannonlake_gt2_info), | |
615 | INTEL_CNL_Y_GT2_IDS(&intel_cannonlake_gt2_info), | |
42f5551d CW |
616 | {0, 0, 0} |
617 | }; | |
618 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
619 | ||
953c7f82 CW |
620 | static void i915_pci_remove(struct pci_dev *pdev) |
621 | { | |
622 | struct drm_device *dev = pci_get_drvdata(pdev); | |
623 | ||
624 | i915_driver_unload(dev); | |
625 | drm_dev_unref(dev); | |
626 | } | |
627 | ||
42f5551d CW |
628 | static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
629 | { | |
630 | struct intel_device_info *intel_info = | |
631 | (struct intel_device_info *) ent->driver_data; | |
953c7f82 | 632 | int err; |
42f5551d | 633 | |
c007fb4a JN |
634 | if (IS_ALPHA_SUPPORT(intel_info) && !i915.alpha_support) { |
635 | DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n" | |
636 | "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n" | |
637 | "to enable support in this kernel version, or check for kernel updates.\n"); | |
42f5551d CW |
638 | return -ENODEV; |
639 | } | |
640 | ||
641 | /* Only bind to function 0 of the device. Early generations | |
642 | * used function 1 as a placeholder for multi-head. This causes | |
643 | * us confusion instead, especially on the systems where both | |
644 | * functions have the same PCI-ID! | |
645 | */ | |
646 | if (PCI_FUNC(pdev->devfn)) | |
647 | return -ENODEV; | |
648 | ||
649 | /* | |
650 | * apple-gmux is needed on dual GPU MacBook Pro | |
651 | * to probe the panel if we're the inactive GPU. | |
652 | */ | |
653 | if (vga_switcheroo_client_probe_defer(pdev)) | |
654 | return -EPROBE_DEFER; | |
655 | ||
953c7f82 CW |
656 | err = i915_driver_load(pdev, ent); |
657 | if (err) | |
658 | return err; | |
42f5551d | 659 | |
953c7f82 CW |
660 | err = i915_live_selftests(pdev); |
661 | if (err) { | |
662 | i915_pci_remove(pdev); | |
663 | return err > 0 ? -ENOTTY : err; | |
664 | } | |
42f5551d | 665 | |
953c7f82 | 666 | return 0; |
42f5551d CW |
667 | } |
668 | ||
a09d0ba1 | 669 | static struct pci_driver i915_pci_driver = { |
42f5551d CW |
670 | .name = DRIVER_NAME, |
671 | .id_table = pciidlist, | |
672 | .probe = i915_pci_probe, | |
673 | .remove = i915_pci_remove, | |
674 | .driver.pm = &i915_pm_ops, | |
675 | }; | |
a09d0ba1 CW |
676 | |
677 | static int __init i915_init(void) | |
678 | { | |
679 | bool use_kms = true; | |
953c7f82 CW |
680 | int err; |
681 | ||
682 | err = i915_mock_selftests(); | |
683 | if (err) | |
684 | return err > 0 ? 0 : err; | |
a09d0ba1 CW |
685 | |
686 | /* | |
687 | * Enable KMS by default, unless explicitly overriden by | |
688 | * either the i915.modeset prarameter or by the | |
689 | * vga_text_mode_force boot option. | |
690 | */ | |
691 | ||
692 | if (i915.modeset == 0) | |
693 | use_kms = false; | |
694 | ||
695 | if (vgacon_text_force() && i915.modeset == -1) | |
696 | use_kms = false; | |
697 | ||
698 | if (!use_kms) { | |
699 | /* Silently fail loading to not upset userspace. */ | |
700 | DRM_DEBUG_DRIVER("KMS disabled.\n"); | |
701 | return 0; | |
702 | } | |
703 | ||
704 | return pci_register_driver(&i915_pci_driver); | |
705 | } | |
706 | ||
707 | static void __exit i915_exit(void) | |
708 | { | |
709 | if (!i915_pci_driver.driver.owner) | |
710 | return; | |
711 | ||
712 | pci_unregister_driver(&i915_pci_driver); | |
713 | } | |
714 | ||
715 | module_init(i915_init); | |
716 | module_exit(i915_exit); | |
717 | ||
718 | MODULE_AUTHOR("Tungsten Graphics, Inc."); | |
719 | MODULE_AUTHOR("Intel Corporation"); | |
720 | ||
721 | MODULE_DESCRIPTION(DRIVER_DESC); | |
722 | MODULE_LICENSE("GPL and additional rights"); |