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drm/i915: get/put runtime PM without holding rps.hw_lock
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_reg.h
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585fb111
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1/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2 * All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef _I915_REG_H_
26#define _I915_REG_H_
27
5eddb70b 28#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
a5c961d1 29#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
5eddb70b 30
2b139522
ED
31#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
32
6b26c86d
DV
33#define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
34#define _MASKED_BIT_DISABLE(a) ((a) << 16)
35
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JB
36/* PCI config space */
37
38#define HPLLCC 0xc0 /* 855 only */
652c393a 39#define GC_CLOCK_CONTROL_MASK (0xf << 0)
585fb111
JB
40#define GC_CLOCK_133_200 (0 << 0)
41#define GC_CLOCK_100_200 (1 << 0)
42#define GC_CLOCK_100_133 (2 << 0)
43#define GC_CLOCK_166_250 (3 << 0)
f97108d1 44#define GCFGC2 0xda
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JB
45#define GCFGC 0xf0 /* 915+ only */
46#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
47#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
48#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
257a7ffc
DV
49#define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
50#define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
51#define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
52#define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
53#define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
54#define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
585fb111 55#define GC_DISPLAY_CLOCK_MASK (7 << 4)
652c393a
JB
56#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
57#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
58#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
59#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
60#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
61#define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
62#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
63#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
64#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
65#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
66#define I945_GC_RENDER_CLOCK_MASK (7 << 0)
67#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
68#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
69#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
70#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
71#define I915_GC_RENDER_CLOCK_MASK (7 << 0)
72#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
73#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
74#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
7f1bdbcb
DV
75#define PCI_LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
76
eeccdcac
KG
77
78/* Graphics reset regs */
0573ed4a
KG
79#define I965_GDRST 0xc0 /* PCI config register */
80#define ILK_GDSR 0x2ca4 /* MCHBAR offset */
eeccdcac
KG
81#define GRDOM_FULL (0<<2)
82#define GRDOM_RENDER (1<<2)
83#define GRDOM_MEDIA (3<<2)
8a5c2ae7 84#define GRDOM_MASK (3<<2)
5ccce180 85#define GRDOM_RESET_ENABLE (1<<0)
585fb111 86
07b7ddd9
JB
87#define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */
88#define GEN6_MBC_SNPCR_SHIFT 21
89#define GEN6_MBC_SNPCR_MASK (3<<21)
90#define GEN6_MBC_SNPCR_MAX (0<<21)
91#define GEN6_MBC_SNPCR_MED (1<<21)
92#define GEN6_MBC_SNPCR_LOW (2<<21)
93#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
94
5eb719cd
DV
95#define GEN6_MBCTL 0x0907c
96#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
97#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
98#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
99#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
100#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
101
cff458c2
EA
102#define GEN6_GDRST 0x941c
103#define GEN6_GRDOM_FULL (1 << 0)
104#define GEN6_GRDOM_RENDER (1 << 1)
105#define GEN6_GRDOM_MEDIA (1 << 2)
106#define GEN6_GRDOM_BLT (1 << 3)
107
5eb719cd
DV
108#define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228)
109#define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518)
110#define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220)
111#define PP_DIR_DCLV_2G 0xffffffff
112
94e409c1
BW
113#define GEN8_RING_PDP_UDW(ring, n) ((ring)->mmio_base+0x270 + ((n) * 8 + 4))
114#define GEN8_RING_PDP_LDW(ring, n) ((ring)->mmio_base+0x270 + (n) * 8)
115
5eb719cd
DV
116#define GAM_ECOCHK 0x4090
117#define ECOCHK_SNB_BIT (1<<10)
e3dff585 118#define HSW_ECOCHK_ARB_PRIO_SOL (1<<6)
5eb719cd
DV
119#define ECOCHK_PPGTT_CACHE64B (0x3<<3)
120#define ECOCHK_PPGTT_CACHE4B (0x0<<3)
a6f429a5
VS
121#define ECOCHK_PPGTT_GFDT_IVB (0x1<<4)
122#define ECOCHK_PPGTT_LLC_IVB (0x1<<3)
123#define ECOCHK_PPGTT_UC_HSW (0x1<<3)
124#define ECOCHK_PPGTT_WT_HSW (0x2<<3)
125#define ECOCHK_PPGTT_WB_HSW (0x3<<3)
5eb719cd 126
48ecfa10 127#define GAC_ECO_BITS 0x14090
3b9d7888 128#define ECOBITS_SNB_BIT (1<<13)
48ecfa10
DV
129#define ECOBITS_PPGTT_CACHE64B (3<<8)
130#define ECOBITS_PPGTT_CACHE4B (0<<8)
131
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DV
132#define GAB_CTL 0x24000
133#define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8)
134
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JB
135/* VGA stuff */
136
137#define VGA_ST01_MDA 0x3ba
138#define VGA_ST01_CGA 0x3da
139
140#define VGA_MSR_WRITE 0x3c2
141#define VGA_MSR_READ 0x3cc
142#define VGA_MSR_MEM_EN (1<<1)
143#define VGA_MSR_CGA_MODE (1<<0)
144
5434fd92 145#define VGA_SR_INDEX 0x3c4
f930ddd0 146#define SR01 1
5434fd92 147#define VGA_SR_DATA 0x3c5
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JB
148
149#define VGA_AR_INDEX 0x3c0
150#define VGA_AR_VID_EN (1<<5)
151#define VGA_AR_DATA_WRITE 0x3c0
152#define VGA_AR_DATA_READ 0x3c1
153
154#define VGA_GR_INDEX 0x3ce
155#define VGA_GR_DATA 0x3cf
156/* GR05 */
157#define VGA_GR_MEM_READ_MODE_SHIFT 3
158#define VGA_GR_MEM_READ_MODE_PLANE 1
159/* GR06 */
160#define VGA_GR_MEM_MODE_MASK 0xc
161#define VGA_GR_MEM_MODE_SHIFT 2
162#define VGA_GR_MEM_A0000_AFFFF 0
163#define VGA_GR_MEM_A0000_BFFFF 1
164#define VGA_GR_MEM_B0000_B7FFF 2
165#define VGA_GR_MEM_B0000_BFFFF 3
166
167#define VGA_DACMASK 0x3c6
168#define VGA_DACRX 0x3c7
169#define VGA_DACWX 0x3c8
170#define VGA_DACDATA 0x3c9
171
172#define VGA_CR_INDEX_MDA 0x3b4
173#define VGA_CR_DATA_MDA 0x3b5
174#define VGA_CR_INDEX_CGA 0x3d4
175#define VGA_CR_DATA_CGA 0x3d5
176
177/*
178 * Memory interface instructions used by the kernel
179 */
180#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
181
182#define MI_NOOP MI_INSTR(0, 0)
183#define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
184#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
02e792fb 185#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
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JB
186#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
187#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
188#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
189#define MI_FLUSH MI_INSTR(0x04, 0)
190#define MI_READ_FLUSH (1 << 0)
191#define MI_EXE_FLUSH (1 << 1)
192#define MI_NO_WRITE_FLUSH (1 << 2)
193#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
194#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
1cafd347 195#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
0e79284d
BW
196#define MI_REPORT_HEAD MI_INSTR(0x07, 0)
197#define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
198#define MI_ARB_ENABLE (1<<0)
199#define MI_ARB_DISABLE (0<<0)
585fb111 200#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
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JB
201#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
202#define MI_SUSPEND_FLUSH_EN (1<<0)
0206e353 203#define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
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DV
204#define MI_OVERLAY_CONTINUE (0x0<<21)
205#define MI_OVERLAY_ON (0x1<<21)
206#define MI_OVERLAY_OFF (0x2<<21)
585fb111 207#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
6b95a207 208#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
1afe3e9d 209#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
6b95a207 210#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
cb05d8de
DV
211/* IVB has funny definitions for which plane to flip. */
212#define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
213#define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
214#define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
215#define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
216#define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
217#define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
0e79284d
BW
218#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */
219#define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
220#define MI_SEMAPHORE_UPDATE (1<<21)
221#define MI_SEMAPHORE_COMPARE (1<<20)
222#define MI_SEMAPHORE_REGISTER (1<<18)
223#define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */
224#define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */
225#define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */
226#define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */
227#define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */
228#define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */
229#define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */
230#define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */
231#define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */
232#define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */
233#define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */
234#define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */
235#define MI_SEMAPHORE_SYNC_INVALID (3<<16)
aa40d6bb
ZN
236#define MI_SET_CONTEXT MI_INSTR(0x18, 0)
237#define MI_MM_SPACE_GTT (1<<8)
238#define MI_MM_SPACE_PHYSICAL (0<<8)
239#define MI_SAVE_EXT_STATE_EN (1<<3)
240#define MI_RESTORE_EXT_STATE_EN (1<<2)
88271da3 241#define MI_FORCE_RESTORE (1<<1)
aa40d6bb 242#define MI_RESTORE_INHIBIT (1<<0)
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JB
243#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
244#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
245#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
246#define MI_STORE_DWORD_INDEX_SHIFT 2
c6642782
DV
247/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
248 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
249 * simply ignores the register load under certain conditions.
250 * - One can actually load arbitrary many arbitrary registers: Simply issue x
251 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
252 */
253#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
ffe74d75 254#define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*x-1)
0e79284d 255#define MI_SRM_LRM_GLOBAL_GTT (1<<22)
71a77e07 256#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
9a289771
JB
257#define MI_FLUSH_DW_STORE_INDEX (1<<21)
258#define MI_INVALIDATE_TLB (1<<18)
259#define MI_FLUSH_DW_OP_STOREDW (1<<14)
260#define MI_INVALIDATE_BSD (1<<7)
261#define MI_FLUSH_DW_USE_GTT (1<<2)
262#define MI_FLUSH_DW_USE_PPGTT (0<<2)
585fb111 263#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
d7d4eedd
CW
264#define MI_BATCH_NON_SECURE (1)
265/* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
0e79284d 266#define MI_BATCH_NON_SECURE_I965 (1<<8)
d7d4eedd 267#define MI_BATCH_PPGTT_HSW (1<<8)
0e79284d 268#define MI_BATCH_NON_SECURE_HSW (1<<13)
585fb111 269#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
65f56876 270#define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
1c7a0623 271#define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
0e79284d 272
9435373e
RV
273
274#define MI_PREDICATE_RESULT_2 (0x2214)
275#define LOWER_SLICE_ENABLED (1<<0)
276#define LOWER_SLICE_DISABLED (0<<0)
277
585fb111
JB
278/*
279 * 3D instructions used by the kernel
280 */
281#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
282
283#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
284#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
285#define SC_UPDATE_SCISSOR (0x1<<1)
286#define SC_ENABLE_MASK (0x1<<0)
287#define SC_ENABLE (0x1<<0)
288#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
289#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
290#define SCI_YMIN_MASK (0xffff<<16)
291#define SCI_XMIN_MASK (0xffff<<0)
292#define SCI_YMAX_MASK (0xffff<<16)
293#define SCI_XMAX_MASK (0xffff<<0)
294#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
295#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
296#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
297#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
298#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
299#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
300#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
301#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
302#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
303#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
304#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
305#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
306#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
307#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
308#define BLT_DEPTH_8 (0<<24)
309#define BLT_DEPTH_16_565 (1<<24)
310#define BLT_DEPTH_16_1555 (2<<24)
311#define BLT_DEPTH_32 (3<<24)
312#define BLT_ROP_GXCOPY (0xcc<<16)
313#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
314#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
315#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
316#define ASYNC_FLIP (1<<22)
317#define DISPLAY_PLANE_A (0<<20)
318#define DISPLAY_PLANE_B (1<<20)
fcbc34e4 319#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
b9e1faa7 320#define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
8d315287 321#define PIPE_CONTROL_CS_STALL (1<<20)
cc0f6398 322#define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
9d971b37
KG
323#define PIPE_CONTROL_QW_WRITE (1<<14)
324#define PIPE_CONTROL_DEPTH_STALL (1<<13)
325#define PIPE_CONTROL_WRITE_FLUSH (1<<12)
8d315287 326#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
9d971b37
KG
327#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */
328#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
329#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
330#define PIPE_CONTROL_NOTIFY (1<<8)
8d315287
JB
331#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
332#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)
333#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)
9d971b37 334#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
8d315287 335#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
e552eb70 336#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
585fb111 337
dc96e9b8
CW
338
339/*
340 * Reset registers
341 */
342#define DEBUG_RESET_I830 0x6070
343#define DEBUG_RESET_FULL (1<<7)
344#define DEBUG_RESET_RENDER (1<<8)
345#define DEBUG_RESET_DISPLAY (1<<9)
346
57f350b6 347/*
5a09ae9f
JN
348 * IOSF sideband
349 */
350#define VLV_IOSF_DOORBELL_REQ (VLV_DISPLAY_BASE + 0x2100)
351#define IOSF_DEVFN_SHIFT 24
352#define IOSF_OPCODE_SHIFT 16
353#define IOSF_PORT_SHIFT 8
354#define IOSF_BYTE_ENABLES_SHIFT 4
355#define IOSF_BAR_SHIFT 1
356#define IOSF_SB_BUSY (1<<0)
f3419158 357#define IOSF_PORT_BUNIT 0x3
5a09ae9f
JN
358#define IOSF_PORT_PUNIT 0x4
359#define IOSF_PORT_NC 0x11
360#define IOSF_PORT_DPIO 0x12
e9f882a3
JN
361#define IOSF_PORT_GPIO_NC 0x13
362#define IOSF_PORT_CCK 0x14
363#define IOSF_PORT_CCU 0xA9
364#define IOSF_PORT_GPS_CORE 0x48
e9fe51c6 365#define IOSF_PORT_FLISDSI 0x1B
5a09ae9f
JN
366#define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104)
367#define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108)
368
30a970c6
JB
369/* See configdb bunit SB addr map */
370#define BUNIT_REG_BISOC 0x11
371
5a09ae9f
JN
372#define PUNIT_OPCODE_REG_READ 6
373#define PUNIT_OPCODE_REG_WRITE 7
374
30a970c6
JB
375#define PUNIT_REG_DSPFREQ 0x36
376#define DSPFREQSTAT_SHIFT 30
377#define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
378#define DSPFREQGUAR_SHIFT 14
379#define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
02f4c9e0
CML
380#define PUNIT_REG_PWRGT_CTRL 0x60
381#define PUNIT_REG_PWRGT_STATUS 0x61
382#define PUNIT_CLK_GATE 1
383#define PUNIT_PWR_RESET 2
384#define PUNIT_PWR_GATE 3
385#define RENDER_PWRGT (PUNIT_PWR_GATE << 0)
386#define MEDIA_PWRGT (PUNIT_PWR_GATE << 2)
387#define DISP2D_PWRGT (PUNIT_PWR_GATE << 6)
388
5a09ae9f
JN
389#define PUNIT_REG_GPU_LFM 0xd3
390#define PUNIT_REG_GPU_FREQ_REQ 0xd4
391#define PUNIT_REG_GPU_FREQ_STS 0xd8
e8474409 392#define GENFREQSTATUS (1<<0)
5a09ae9f
JN
393#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
394
395#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
396#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
397
398#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
399#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
400#define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
401#define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
402#define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
403#define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
404#define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
405#define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
406#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
407#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
408
be4fc046 409/* vlv2 north clock has */
24eb2d59
CML
410#define CCK_FUSE_REG 0x8
411#define CCK_FUSE_HPLL_FREQ_MASK 0x3
be4fc046 412#define CCK_REG_DSI_PLL_FUSE 0x44
413#define CCK_REG_DSI_PLL_CONTROL 0x48
414#define DSI_PLL_VCO_EN (1 << 31)
415#define DSI_PLL_LDO_GATE (1 << 30)
416#define DSI_PLL_P1_POST_DIV_SHIFT 17
417#define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
418#define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
419#define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
420#define DSI_PLL_MUX_MASK (3 << 9)
421#define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
422#define DSI_PLL_MUX_DSI0_CCK (1 << 10)
423#define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
424#define DSI_PLL_MUX_DSI1_CCK (1 << 9)
425#define DSI_PLL_CLK_GATE_MASK (0xf << 5)
426#define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
427#define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
428#define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
429#define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
430#define DSI_PLL_LOCK (1 << 0)
431#define CCK_REG_DSI_PLL_DIVIDER 0x4c
432#define DSI_PLL_LFSR (1 << 31)
433#define DSI_PLL_FRACTION_EN (1 << 30)
434#define DSI_PLL_FRAC_COUNTER_SHIFT 27
435#define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
436#define DSI_PLL_USYNC_CNT_SHIFT 18
437#define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
438#define DSI_PLL_N1_DIV_SHIFT 16
439#define DSI_PLL_N1_DIV_MASK (3 << 16)
440#define DSI_PLL_M1_DIV_SHIFT 0
441#define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
30a970c6 442#define CCK_DISPLAY_CLOCK_CONTROL 0x6b
be4fc046 443
5a09ae9f
JN
444/*
445 * DPIO - a special bus for various display related registers to hide behind
54d9d493
VS
446 *
447 * DPIO is VLV only.
598fac6b
DV
448 *
449 * Note: digital port B is DDI0, digital pot C is DDI1
57f350b6 450 */
5a09ae9f
JN
451#define DPIO_DEVFN 0
452#define DPIO_OPCODE_REG_WRITE 1
453#define DPIO_OPCODE_REG_READ 0
454
54d9d493 455#define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110)
57f350b6
JB
456#define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */
457#define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */
458#define DPIO_SFR_BYPASS (1<<1)
40e9cf64 459#define DPIO_CMNRST (1<<0)
57f350b6 460
e4607fcf
CML
461#define DPIO_PHY(pipe) ((pipe) >> 1)
462#define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy])
463
598fac6b
DV
464/*
465 * Per pipe/PLL DPIO regs
466 */
ab3c759a 467#define _VLV_PLL_DW3_CH0 0x800c
57f350b6 468#define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
598fac6b
DV
469#define DPIO_POST_DIV_DAC 0
470#define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
471#define DPIO_POST_DIV_LVDS1 2
472#define DPIO_POST_DIV_LVDS2 3
57f350b6
JB
473#define DPIO_K_SHIFT (24) /* 4 bits */
474#define DPIO_P1_SHIFT (21) /* 3 bits */
475#define DPIO_P2_SHIFT (16) /* 5 bits */
476#define DPIO_N_SHIFT (12) /* 4 bits */
477#define DPIO_ENABLE_CALIBRATION (1<<11)
478#define DPIO_M1DIV_SHIFT (8) /* 3 bits */
479#define DPIO_M2DIV_MASK 0xff
ab3c759a
CML
480#define _VLV_PLL_DW3_CH1 0x802c
481#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
57f350b6 482
ab3c759a 483#define _VLV_PLL_DW5_CH0 0x8014
57f350b6
JB
484#define DPIO_REFSEL_OVERRIDE 27
485#define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
486#define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
487#define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
b56747aa 488#define DPIO_PLL_REFCLK_SEL_MASK 3
57f350b6
JB
489#define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
490#define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
ab3c759a
CML
491#define _VLV_PLL_DW5_CH1 0x8034
492#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
57f350b6 493
ab3c759a
CML
494#define _VLV_PLL_DW7_CH0 0x801c
495#define _VLV_PLL_DW7_CH1 0x803c
496#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
57f350b6 497
ab3c759a
CML
498#define _VLV_PLL_DW8_CH0 0x8040
499#define _VLV_PLL_DW8_CH1 0x8060
500#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
598fac6b 501
ab3c759a
CML
502#define VLV_PLL_DW9_BCAST 0xc044
503#define _VLV_PLL_DW9_CH0 0x8044
504#define _VLV_PLL_DW9_CH1 0x8064
505#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
598fac6b 506
ab3c759a
CML
507#define _VLV_PLL_DW10_CH0 0x8048
508#define _VLV_PLL_DW10_CH1 0x8068
509#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
598fac6b 510
ab3c759a
CML
511#define _VLV_PLL_DW11_CH0 0x804c
512#define _VLV_PLL_DW11_CH1 0x806c
513#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
57f350b6 514
ab3c759a
CML
515/* Spec for ref block start counts at DW10 */
516#define VLV_REF_DW13 0x80ac
598fac6b 517
ab3c759a 518#define VLV_CMN_DW0 0x8100
dc96e9b8 519
598fac6b
DV
520/*
521 * Per DDI channel DPIO regs
522 */
523
ab3c759a
CML
524#define _VLV_PCS_DW0_CH0 0x8200
525#define _VLV_PCS_DW0_CH1 0x8400
598fac6b
DV
526#define DPIO_PCS_TX_LANE2_RESET (1<<16)
527#define DPIO_PCS_TX_LANE1_RESET (1<<7)
ab3c759a 528#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
598fac6b 529
ab3c759a
CML
530#define _VLV_PCS_DW1_CH0 0x8204
531#define _VLV_PCS_DW1_CH1 0x8404
598fac6b
DV
532#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22)
533#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
534#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
535#define DPIO_PCS_CLK_SOFT_RESET (1<<5)
ab3c759a
CML
536#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
537
538#define _VLV_PCS_DW8_CH0 0x8220
539#define _VLV_PCS_DW8_CH1 0x8420
540#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
541
542#define _VLV_PCS01_DW8_CH0 0x0220
543#define _VLV_PCS23_DW8_CH0 0x0420
544#define _VLV_PCS01_DW8_CH1 0x2620
545#define _VLV_PCS23_DW8_CH1 0x2820
546#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
547#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
548
549#define _VLV_PCS_DW9_CH0 0x8224
550#define _VLV_PCS_DW9_CH1 0x8424
551#define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
552
553#define _VLV_PCS_DW11_CH0 0x822c
554#define _VLV_PCS_DW11_CH1 0x842c
555#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
556
557#define _VLV_PCS_DW12_CH0 0x8230
558#define _VLV_PCS_DW12_CH1 0x8430
559#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
560
561#define _VLV_PCS_DW14_CH0 0x8238
562#define _VLV_PCS_DW14_CH1 0x8438
563#define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
564
565#define _VLV_PCS_DW23_CH0 0x825c
566#define _VLV_PCS_DW23_CH1 0x845c
567#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
568
569#define _VLV_TX_DW2_CH0 0x8288
570#define _VLV_TX_DW2_CH1 0x8488
571#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
572
573#define _VLV_TX_DW3_CH0 0x828c
574#define _VLV_TX_DW3_CH1 0x848c
575#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
576
577#define _VLV_TX_DW4_CH0 0x8290
578#define _VLV_TX_DW4_CH1 0x8490
579#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
580
581#define _VLV_TX3_DW4_CH0 0x690
582#define _VLV_TX3_DW4_CH1 0x2a90
583#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
584
585#define _VLV_TX_DW5_CH0 0x8294
586#define _VLV_TX_DW5_CH1 0x8494
598fac6b 587#define DPIO_TX_OCALINIT_EN (1<<31)
ab3c759a
CML
588#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
589
590#define _VLV_TX_DW11_CH0 0x82ac
591#define _VLV_TX_DW11_CH1 0x84ac
592#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
593
594#define _VLV_TX_DW14_CH0 0x82b8
595#define _VLV_TX_DW14_CH1 0x84b8
596#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
b56747aa 597
585fb111 598/*
de151cf6 599 * Fence registers
585fb111 600 */
de151cf6 601#define FENCE_REG_830_0 0x2000
dc529a4f 602#define FENCE_REG_945_8 0x3000
de151cf6
JB
603#define I830_FENCE_START_MASK 0x07f80000
604#define I830_FENCE_TILING_Y_SHIFT 12
0f973f27 605#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
de151cf6
JB
606#define I830_FENCE_PITCH_SHIFT 4
607#define I830_FENCE_REG_VALID (1<<0)
c36a2a6d 608#define I915_FENCE_MAX_PITCH_VAL 4
e76a16de 609#define I830_FENCE_MAX_PITCH_VAL 6
8d7773a3 610#define I830_FENCE_MAX_SIZE_VAL (1<<8)
de151cf6
JB
611
612#define I915_FENCE_START_MASK 0x0ff00000
0f973f27 613#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
585fb111 614
de151cf6
JB
615#define FENCE_REG_965_0 0x03000
616#define I965_FENCE_PITCH_SHIFT 2
617#define I965_FENCE_TILING_Y_SHIFT 1
618#define I965_FENCE_REG_VALID (1<<0)
8d7773a3 619#define I965_FENCE_MAX_PITCH_VAL 0x0400
de151cf6 620
4e901fdc
EA
621#define FENCE_REG_SANDYBRIDGE_0 0x100000
622#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
3a062478 623#define GEN7_FENCE_MAX_PITCH_VAL 0x0800
4e901fdc 624
f691e2f4
DV
625/* control register for cpu gtt access */
626#define TILECTL 0x101000
627#define TILECTL_SWZCTL (1 << 0)
628#define TILECTL_TLB_PREFETCH_DIS (1 << 2)
629#define TILECTL_BACKSNOOP_DIS (1 << 3)
630
de151cf6
JB
631/*
632 * Instruction and interrupt control regs
633 */
63eeaf38 634#define PGTBL_ER 0x02024
333e9fe9
DV
635#define RENDER_RING_BASE 0x02000
636#define BSD_RING_BASE 0x04000
637#define GEN6_BSD_RING_BASE 0x12000
1950de14 638#define VEBOX_RING_BASE 0x1a000
549f7365 639#define BLT_RING_BASE 0x22000
3d281d8c
DV
640#define RING_TAIL(base) ((base)+0x30)
641#define RING_HEAD(base) ((base)+0x34)
642#define RING_START(base) ((base)+0x38)
643#define RING_CTL(base) ((base)+0x3c)
1ec14ad3
CW
644#define RING_SYNC_0(base) ((base)+0x40)
645#define RING_SYNC_1(base) ((base)+0x44)
1950de14
BW
646#define RING_SYNC_2(base) ((base)+0x48)
647#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
648#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
649#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
650#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
651#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
652#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
653#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
654#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
655#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
656#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
657#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
658#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
ad776f8b 659#define GEN6_NOSYNC 0
8fd26859 660#define RING_MAX_IDLE(base) ((base)+0x54)
3d281d8c
DV
661#define RING_HWS_PGA(base) ((base)+0x80)
662#define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
f691e2f4
DV
663#define ARB_MODE 0x04030
664#define ARB_MODE_SWIZZLE_SNB (1<<4)
665#define ARB_MODE_SWIZZLE_IVB (1<<5)
31a5336e 666#define GAMTARBMODE 0x04a08
4afe8d33 667#define ARB_MODE_BWGTLB_DISABLE (1<<9)
31a5336e 668#define ARB_MODE_SWIZZLE_BDW (1<<1)
4593010b 669#define RENDER_HWS_PGA_GEN7 (0x04080)
33f3f518 670#define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id)
828c7908
BW
671#define RING_FAULT_GTTSEL_MASK (1<<11)
672#define RING_FAULT_SRCID(x) ((x >> 3) & 0xff)
673#define RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3)
674#define RING_FAULT_VALID (1<<0)
33f3f518 675#define DONE_REG 0x40b0
fbe5d36e 676#define GEN8_PRIVATE_PAT 0x40e0
4593010b
EA
677#define BSD_HWS_PGA_GEN7 (0x04180)
678#define BLT_HWS_PGA_GEN7 (0x04280)
9a8a2213 679#define VEBOX_HWS_PGA_GEN7 (0x04380)
3d281d8c 680#define RING_ACTHD(base) ((base)+0x74)
1ec14ad3 681#define RING_NOPID(base) ((base)+0x94)
0f46832f 682#define RING_IMR(base) ((base)+0xa8)
c0c7babc 683#define RING_TIMESTAMP(base) ((base)+0x358)
585fb111
JB
684#define TAIL_ADDR 0x001FFFF8
685#define HEAD_WRAP_COUNT 0xFFE00000
686#define HEAD_WRAP_ONE 0x00200000
687#define HEAD_ADDR 0x001FFFFC
688#define RING_NR_PAGES 0x001FF000
689#define RING_REPORT_MASK 0x00000006
690#define RING_REPORT_64K 0x00000002
691#define RING_REPORT_128K 0x00000004
692#define RING_NO_REPORT 0x00000000
693#define RING_VALID_MASK 0x00000001
694#define RING_VALID 0x00000001
695#define RING_INVALID 0x00000000
4b60e5cb
CW
696#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
697#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
1ec14ad3 698#define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
8168bd48
CW
699#if 0
700#define PRB0_TAIL 0x02030
701#define PRB0_HEAD 0x02034
702#define PRB0_START 0x02038
703#define PRB0_CTL 0x0203c
585fb111
JB
704#define PRB1_TAIL 0x02040 /* 915+ only */
705#define PRB1_HEAD 0x02044 /* 915+ only */
706#define PRB1_START 0x02048 /* 915+ only */
707#define PRB1_CTL 0x0204c /* 915+ only */
8168bd48 708#endif
63eeaf38
JB
709#define IPEIR_I965 0x02064
710#define IPEHR_I965 0x02068
711#define INSTDONE_I965 0x0206c
d53bd484
BW
712#define GEN7_INSTDONE_1 0x0206c
713#define GEN7_SC_INSTDONE 0x07100
714#define GEN7_SAMPLER_INSTDONE 0x0e160
715#define GEN7_ROW_INSTDONE 0x0e164
716#define I915_NUM_INSTDONE_REG 4
d27b1e0e
DV
717#define RING_IPEIR(base) ((base)+0x64)
718#define RING_IPEHR(base) ((base)+0x68)
719#define RING_INSTDONE(base) ((base)+0x6c)
c1cd90ed
DV
720#define RING_INSTPS(base) ((base)+0x70)
721#define RING_DMA_FADD(base) ((base)+0x78)
722#define RING_INSTPM(base) ((base)+0xc0)
63eeaf38
JB
723#define INSTPS 0x02070 /* 965+ only */
724#define INSTDONE1 0x0207c /* 965+ only */
585fb111
JB
725#define ACTHD_I965 0x02074
726#define HWS_PGA 0x02080
727#define HWS_ADDRESS_MASK 0xfffff000
728#define HWS_START_ADDRESS_SHIFT 4
97f5ab66
JB
729#define PWRCTXA 0x2088 /* 965GM+ only */
730#define PWRCTX_EN (1<<0)
585fb111 731#define IPEIR 0x02088
63eeaf38
JB
732#define IPEHR 0x0208c
733#define INSTDONE 0x02090
585fb111
JB
734#define NOPID 0x02094
735#define HWSTAM 0x02098
9d2f41fa 736#define DMA_FADD_I8XX 0x020d0
94e39e28 737#define RING_BBSTATE(base) ((base)+0x110)
3dda20a9
VS
738#define RING_BBADDR(base) ((base)+0x140)
739#define RING_BBADDR_UDW(base) ((base)+0x168) /* gen8+ */
71cf39b1 740
f406839f 741#define ERROR_GEN6 0x040a0
71e172e8 742#define GEN7_ERR_INT 0x44040
de032bf4 743#define ERR_INT_POISON (1<<31)
8664281b 744#define ERR_INT_MMIO_UNCLAIMED (1<<13)
8bf1e9f1 745#define ERR_INT_PIPE_CRC_DONE_C (1<<8)
8664281b 746#define ERR_INT_FIFO_UNDERRUN_C (1<<6)
8bf1e9f1 747#define ERR_INT_PIPE_CRC_DONE_B (1<<5)
8664281b 748#define ERR_INT_FIFO_UNDERRUN_B (1<<3)
8bf1e9f1 749#define ERR_INT_PIPE_CRC_DONE_A (1<<2)
5a69b89f 750#define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + pipe*3))
8664281b 751#define ERR_INT_FIFO_UNDERRUN_A (1<<0)
7336df65 752#define ERR_INT_FIFO_UNDERRUN(pipe) (1<<(pipe*3))
f406839f 753
3f1e109a
PZ
754#define FPGA_DBG 0x42300
755#define FPGA_DBG_RM_NOCLAIM (1<<31)
756
0f3b6849 757#define DERRMR 0x44050
4e0bbc31 758/* Note that HBLANK events are reserved on bdw+ */
ffe74d75
CW
759#define DERRMR_PIPEA_SCANLINE (1<<0)
760#define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1)
761#define DERRMR_PIPEA_SPR_FLIP_DONE (1<<2)
762#define DERRMR_PIPEA_VBLANK (1<<3)
763#define DERRMR_PIPEA_HBLANK (1<<5)
764#define DERRMR_PIPEB_SCANLINE (1<<8)
765#define DERRMR_PIPEB_PRI_FLIP_DONE (1<<9)
766#define DERRMR_PIPEB_SPR_FLIP_DONE (1<<10)
767#define DERRMR_PIPEB_VBLANK (1<<11)
768#define DERRMR_PIPEB_HBLANK (1<<13)
769/* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
770#define DERRMR_PIPEC_SCANLINE (1<<14)
771#define DERRMR_PIPEC_PRI_FLIP_DONE (1<<15)
772#define DERRMR_PIPEC_SPR_FLIP_DONE (1<<20)
773#define DERRMR_PIPEC_VBLANK (1<<21)
774#define DERRMR_PIPEC_HBLANK (1<<22)
775
0f3b6849 776
de6e2eaf
EA
777/* GM45+ chicken bits -- debug workaround bits that may be required
778 * for various sorts of correct behavior. The top 16 bits of each are
779 * the enables for writing to the corresponding low bit.
780 */
781#define _3D_CHICKEN 0x02084
4283908e 782#define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
de6e2eaf
EA
783#define _3D_CHICKEN2 0x0208c
784/* Disables pipelining of read flushes past the SF-WIZ interface.
785 * Required on all Ironlake steppings according to the B-Spec, but the
786 * particular danger of not doing so is not specified.
787 */
788# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
789#define _3D_CHICKEN3 0x02090
87f8020e 790#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
26b6e44a 791#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
e927ecde
VS
792#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */
793#define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */
de6e2eaf 794
71cf39b1
EA
795#define MI_MODE 0x0209c
796# define VS_TIMER_DISPATCH (1 << 6)
fc74d8e0 797# define MI_FLUSH_ENABLE (1 << 12)
1c8c38c5 798# define ASYNC_FLIP_PERF_DISABLE (1 << 14)
71cf39b1 799
f8f2ac9a 800#define GEN6_GT_MODE 0x20d0
6547fbdb
DV
801#define GEN6_GT_MODE_HI (1 << 9)
802#define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
f8f2ac9a 803
1ec14ad3 804#define GFX_MODE 0x02520
b095cd0a 805#define GFX_MODE_GEN7 0x0229c
5eb719cd 806#define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c)
1ec14ad3
CW
807#define GFX_RUN_LIST_ENABLE (1<<15)
808#define GFX_TLB_INVALIDATE_ALWAYS (1<<13)
809#define GFX_SURFACE_FAULT_ENABLE (1<<12)
810#define GFX_REPLAY_MODE (1<<11)
811#define GFX_PSMI_GRANULARITY (1<<10)
812#define GFX_PPGTT_ENABLE (1<<9)
813
a7e806de
DV
814#define VLV_DISPLAY_BASE 0x180000
815
585fb111
JB
816#define SCPD0 0x0209c /* 915+ only */
817#define IER 0x020a0
818#define IIR 0x020a4
819#define IMR 0x020a8
820#define ISR 0x020ac
07ec7ec5 821#define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060)
2d809570 822#define GCFG_DIS (1<<8)
ff763010
VS
823#define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084)
824#define VLV_IER (VLV_DISPLAY_BASE + 0x20a0)
825#define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4)
826#define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8)
827#define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac)
c9cddffc 828#define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120)
90a72f87 829#define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
585fb111
JB
830#define EIR 0x020b0
831#define EMR 0x020b4
832#define ESR 0x020b8
63eeaf38
JB
833#define GM45_ERROR_PAGE_TABLE (1<<5)
834#define GM45_ERROR_MEM_PRIV (1<<4)
835#define I915_ERROR_PAGE_TABLE (1<<4)
836#define GM45_ERROR_CP_PRIV (1<<3)
837#define I915_ERROR_MEMORY_REFRESH (1<<1)
838#define I915_ERROR_INSTRUCTION (1<<0)
585fb111 839#define INSTPM 0x020c0
ee980b80 840#define INSTPM_SELF_EN (1<<12) /* 915GM only */
8692d00e
CW
841#define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts
842 will not assert AGPBUSY# and will only
843 be delivered when out of C3. */
84f9f938 844#define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */
884020bf
CW
845#define INSTPM_TLB_INVALIDATE (1<<9)
846#define INSTPM_SYNC_FLUSH (1<<5)
585fb111
JB
847#define ACTHD 0x020c8
848#define FW_BLC 0x020d8
8692d00e 849#define FW_BLC2 0x020dc
585fb111 850#define FW_BLC_SELF 0x020e0 /* 915+ only */
ee980b80
LP
851#define FW_BLC_SELF_EN_MASK (1<<31)
852#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
853#define FW_BLC_SELF_EN (1<<15) /* 945 only */
7662c8bd
SL
854#define MM_BURST_LENGTH 0x00700000
855#define MM_FIFO_WATERMARK 0x0001F000
856#define LM_BURST_LENGTH 0x00000700
857#define LM_FIFO_WATERMARK 0x0000001F
585fb111 858#define MI_ARB_STATE 0x020e4 /* 915+ only */
45503ded
KP
859
860/* Make render/texture TLB fetches lower priorty than associated data
861 * fetches. This is not turned on by default
862 */
863#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
864
865/* Isoch request wait on GTT enable (Display A/B/C streams).
866 * Make isoch requests stall on the TLB update. May cause
867 * display underruns (test mode only)
868 */
869#define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
870
871/* Block grant count for isoch requests when block count is
872 * set to a finite value.
873 */
874#define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
875#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
876#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
877#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
878#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
879
880/* Enable render writes to complete in C2/C3/C4 power states.
881 * If this isn't enabled, render writes are prevented in low
882 * power states. That seems bad to me.
883 */
884#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
885
886/* This acknowledges an async flip immediately instead
887 * of waiting for 2TLB fetches.
888 */
889#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
890
891/* Enables non-sequential data reads through arbiter
892 */
0206e353 893#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
45503ded
KP
894
895/* Disable FSB snooping of cacheable write cycles from binner/render
896 * command stream
897 */
898#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
899
900/* Arbiter time slice for non-isoch streams */
901#define MI_ARB_TIME_SLICE_MASK (7 << 5)
902#define MI_ARB_TIME_SLICE_1 (0 << 5)
903#define MI_ARB_TIME_SLICE_2 (1 << 5)
904#define MI_ARB_TIME_SLICE_4 (2 << 5)
905#define MI_ARB_TIME_SLICE_6 (3 << 5)
906#define MI_ARB_TIME_SLICE_8 (4 << 5)
907#define MI_ARB_TIME_SLICE_10 (5 << 5)
908#define MI_ARB_TIME_SLICE_14 (6 << 5)
909#define MI_ARB_TIME_SLICE_16 (7 << 5)
910
911/* Low priority grace period page size */
912#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
913#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
914
915/* Disable display A/B trickle feed */
916#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
917
918/* Set display plane priority */
919#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
920#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
921
585fb111 922#define CACHE_MODE_0 0x02120 /* 915+ only */
4358a374 923#define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
585fb111
JB
924#define CM0_IZ_OPT_DISABLE (1<<6)
925#define CM0_ZR_OPT_DISABLE (1<<5)
009be664 926#define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
585fb111
JB
927#define CM0_DEPTH_EVICT_DISABLE (1<<4)
928#define CM0_COLOR_EVICT_DISABLE (1<<3)
929#define CM0_DEPTH_WRITE_DISABLE (1<<1)
930#define CM0_RC_OP_FLUSH_DISABLE (1<<0)
931#define GFX_FLSH_CNTL 0x02170 /* 915+ only */
0f9b91c7
BW
932#define GFX_FLSH_CNTL_GEN6 0x101008
933#define GFX_FLSH_CNTL_EN (1<<0)
1afe3e9d
JB
934#define ECOSKPD 0x021d0
935#define ECO_GATING_CX_ONLY (1<<3)
936#define ECO_FLIP_DONE (1<<0)
585fb111 937
fe27c606
CW
938#define CACHE_MODE_0_GEN7 0x7000 /* IVB+ */
939#define HIZ_RAW_STALL_OPT_DISABLE (1<<2)
fb046853
JB
940#define CACHE_MODE_1 0x7004 /* IVB+ */
941#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
942
4efe0708
JB
943#define GEN6_BLITTER_ECOSKPD 0x221d0
944#define GEN6_BLITTER_LOCK_SHIFT 16
945#define GEN6_BLITTER_FBC_NOTIFY (1<<3)
946
881f47b6 947#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
12f55818
CW
948#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
949#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
950#define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
951#define GEN6_BSD_GO_INDICATOR (1 << 4)
881f47b6 952
cc609d5d
BW
953/* On modern GEN architectures interrupt control consists of two sets
954 * of registers. The first set pertains to the ring generating the
955 * interrupt. The second control is for the functional block generating the
956 * interrupt. These are PM, GT, DE, etc.
957 *
958 * Luckily *knocks on wood* all the ring interrupt bits match up with the
959 * GT interrupt bits, so we don't need to duplicate the defines.
960 *
961 * These defines should cover us well from SNB->HSW with minor exceptions
962 * it can also work on ILK.
963 */
964#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
965#define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
966#define GT_BLT_USER_INTERRUPT (1 << 22)
967#define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
968#define GT_BSD_USER_INTERRUPT (1 << 12)
35a85ac6 969#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
cc609d5d
BW
970#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
971#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
972#define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3)
973#define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
974#define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
975#define GT_RENDER_USER_INTERRUPT (1 << 0)
976
12638c57
BW
977#define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
978#define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
979
35a85ac6
BW
980#define GT_PARITY_ERROR(dev) \
981 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
45f80d53 982 (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
35a85ac6 983
cc609d5d
BW
984/* These are all the "old" interrupts */
985#define ILK_BSD_USER_INTERRUPT (1<<5)
986#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
987#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
988#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
989#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
990#define I915_HWB_OOM_INTERRUPT (1<<13)
991#define I915_SYNC_STATUS_INTERRUPT (1<<12)
992#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
993#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
994#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
995#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
996#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
997#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
998#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
999#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
1000#define I915_DEBUG_INTERRUPT (1<<2)
1001#define I915_USER_INTERRUPT (1<<1)
1002#define I915_ASLE_INTERRUPT (1<<0)
1003#define I915_BSD_USER_INTERRUPT (1 << 25)
881f47b6
XH
1004
1005#define GEN6_BSD_RNCID 0x12198
1006
a1e969e0
BW
1007#define GEN7_FF_THREAD_MODE 0x20a0
1008#define GEN7_FF_SCHED_MASK 0x0077070
ab57fff1 1009#define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
a1e969e0
BW
1010#define GEN7_FF_TS_SCHED_HS1 (0x5<<16)
1011#define GEN7_FF_TS_SCHED_HS0 (0x3<<16)
1012#define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16)
1013#define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */
41c0b3a8 1014#define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
a1e969e0
BW
1015#define GEN7_FF_VS_SCHED_HS1 (0x5<<12)
1016#define GEN7_FF_VS_SCHED_HS0 (0x3<<12)
1017#define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */
1018#define GEN7_FF_VS_SCHED_HW (0x0<<12)
1019#define GEN7_FF_DS_SCHED_HS1 (0x5<<4)
1020#define GEN7_FF_DS_SCHED_HS0 (0x3<<4)
1021#define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */
1022#define GEN7_FF_DS_SCHED_HW (0x0<<4)
1023
585fb111
JB
1024/*
1025 * Framebuffer compression (915+ only)
1026 */
1027
1028#define FBC_CFB_BASE 0x03200 /* 4k page aligned */
1029#define FBC_LL_BASE 0x03204 /* 4k page aligned */
1030#define FBC_CONTROL 0x03208
1031#define FBC_CTL_EN (1<<31)
1032#define FBC_CTL_PERIODIC (1<<30)
1033#define FBC_CTL_INTERVAL_SHIFT (16)
1034#define FBC_CTL_UNCOMPRESSIBLE (1<<14)
49677901 1035#define FBC_CTL_C3_IDLE (1<<13)
585fb111 1036#define FBC_CTL_STRIDE_SHIFT (5)
82f34496 1037#define FBC_CTL_FENCENO_SHIFT (0)
585fb111
JB
1038#define FBC_COMMAND 0x0320c
1039#define FBC_CMD_COMPRESS (1<<0)
1040#define FBC_STATUS 0x03210
1041#define FBC_STAT_COMPRESSING (1<<31)
1042#define FBC_STAT_COMPRESSED (1<<30)
1043#define FBC_STAT_MODIFIED (1<<29)
82f34496 1044#define FBC_STAT_CURRENT_LINE_SHIFT (0)
585fb111
JB
1045#define FBC_CONTROL2 0x03214
1046#define FBC_CTL_FENCE_DBL (0<<4)
1047#define FBC_CTL_IDLE_IMM (0<<2)
1048#define FBC_CTL_IDLE_FULL (1<<2)
1049#define FBC_CTL_IDLE_LINE (2<<2)
1050#define FBC_CTL_IDLE_DEBUG (3<<2)
1051#define FBC_CTL_CPU_FENCE (1<<1)
7f2cf220 1052#define FBC_CTL_PLANE(plane) ((plane)<<0)
f64f1726 1053#define FBC_FENCE_OFF 0x03218 /* BSpec typo has 321Bh */
80824003 1054#define FBC_TAG 0x03300
585fb111
JB
1055
1056#define FBC_LL_SIZE (1536)
1057
74dff282
JB
1058/* Framebuffer compression for GM45+ */
1059#define DPFC_CB_BASE 0x3200
1060#define DPFC_CONTROL 0x3208
1061#define DPFC_CTL_EN (1<<31)
7f2cf220
VS
1062#define DPFC_CTL_PLANE(plane) ((plane)<<30)
1063#define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29)
74dff282 1064#define DPFC_CTL_FENCE_EN (1<<29)
abe959c7 1065#define IVB_DPFC_CTL_FENCE_EN (1<<28)
9ce9d069 1066#define DPFC_CTL_PERSISTENT_MODE (1<<25)
74dff282
JB
1067#define DPFC_SR_EN (1<<10)
1068#define DPFC_CTL_LIMIT_1X (0<<6)
1069#define DPFC_CTL_LIMIT_2X (1<<6)
1070#define DPFC_CTL_LIMIT_4X (2<<6)
1071#define DPFC_RECOMP_CTL 0x320c
1072#define DPFC_RECOMP_STALL_EN (1<<27)
1073#define DPFC_RECOMP_STALL_WM_SHIFT (16)
1074#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
1075#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
1076#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
1077#define DPFC_STATUS 0x3210
1078#define DPFC_INVAL_SEG_SHIFT (16)
1079#define DPFC_INVAL_SEG_MASK (0x07ff0000)
1080#define DPFC_COMP_SEG_SHIFT (0)
1081#define DPFC_COMP_SEG_MASK (0x000003ff)
1082#define DPFC_STATUS2 0x3214
1083#define DPFC_FENCE_YOFF 0x3218
1084#define DPFC_CHICKEN 0x3224
1085#define DPFC_HT_MODIFY (1<<31)
1086
b52eb4dc
ZY
1087/* Framebuffer compression for Ironlake */
1088#define ILK_DPFC_CB_BASE 0x43200
1089#define ILK_DPFC_CONTROL 0x43208
1090/* The bit 28-8 is reserved */
1091#define DPFC_RESERVED (0x1FFFFF00)
1092#define ILK_DPFC_RECOMP_CTL 0x4320c
1093#define ILK_DPFC_STATUS 0x43210
1094#define ILK_DPFC_FENCE_YOFF 0x43218
1095#define ILK_DPFC_CHICKEN 0x43224
1096#define ILK_FBC_RT_BASE 0x2128
1097#define ILK_FBC_RT_VALID (1<<0)
abe959c7 1098#define SNB_FBC_FRONT_BUFFER (1<<1)
b52eb4dc
ZY
1099
1100#define ILK_DISPLAY_CHICKEN1 0x42000
1101#define ILK_FBCQ_DIS (1<<22)
0206e353 1102#define ILK_PABSTRETCH_DIS (1<<21)
1398261a 1103
b52eb4dc 1104
9c04f015
YL
1105/*
1106 * Framebuffer compression for Sandybridge
1107 *
1108 * The following two registers are of type GTTMMADR
1109 */
1110#define SNB_DPFC_CTL_SA 0x100100
1111#define SNB_CPU_FENCE_ENABLE (1<<29)
1112#define DPFC_CPU_FENCE_OFFSET 0x100104
1113
abe959c7
RV
1114/* Framebuffer compression for Ivybridge */
1115#define IVB_FBC_RT_BASE 0x7020
1116
42db64ef
PZ
1117#define IPS_CTL 0x43408
1118#define IPS_ENABLE (1 << 31)
9c04f015 1119
fd3da6c9
RV
1120#define MSG_FBC_REND_STATE 0x50380
1121#define FBC_REND_NUKE (1<<2)
1122#define FBC_REND_CACHE_CLEAN (1<<1)
1123
28554164
RV
1124#define _HSW_PIPE_SLICE_CHICKEN_1_A 0x420B0
1125#define _HSW_PIPE_SLICE_CHICKEN_1_B 0x420B4
1126#define HSW_BYPASS_FBC_QUEUE (1<<22)
1127#define HSW_PIPE_SLICE_CHICKEN_1(pipe) _PIPE(pipe, + \
1128 _HSW_PIPE_SLICE_CHICKEN_1_A, + \
1129 _HSW_PIPE_SLICE_CHICKEN_1_B)
1130
585fb111
JB
1131/*
1132 * GPIO regs
1133 */
1134#define GPIOA 0x5010
1135#define GPIOB 0x5014
1136#define GPIOC 0x5018
1137#define GPIOD 0x501c
1138#define GPIOE 0x5020
1139#define GPIOF 0x5024
1140#define GPIOG 0x5028
1141#define GPIOH 0x502c
1142# define GPIO_CLOCK_DIR_MASK (1 << 0)
1143# define GPIO_CLOCK_DIR_IN (0 << 1)
1144# define GPIO_CLOCK_DIR_OUT (1 << 1)
1145# define GPIO_CLOCK_VAL_MASK (1 << 2)
1146# define GPIO_CLOCK_VAL_OUT (1 << 3)
1147# define GPIO_CLOCK_VAL_IN (1 << 4)
1148# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
1149# define GPIO_DATA_DIR_MASK (1 << 8)
1150# define GPIO_DATA_DIR_IN (0 << 9)
1151# define GPIO_DATA_DIR_OUT (1 << 9)
1152# define GPIO_DATA_VAL_MASK (1 << 10)
1153# define GPIO_DATA_VAL_OUT (1 << 11)
1154# define GPIO_DATA_VAL_IN (1 << 12)
1155# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
1156
f899fc64
CW
1157#define GMBUS0 0x5100 /* clock/port select */
1158#define GMBUS_RATE_100KHZ (0<<8)
1159#define GMBUS_RATE_50KHZ (1<<8)
1160#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
1161#define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
1162#define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
1163#define GMBUS_PORT_DISABLED 0
1164#define GMBUS_PORT_SSC 1
1165#define GMBUS_PORT_VGADDC 2
1166#define GMBUS_PORT_PANEL 3
1167#define GMBUS_PORT_DPC 4 /* HDMIC */
1168#define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */
e4fd17af
DK
1169#define GMBUS_PORT_DPD 6 /* HDMID */
1170#define GMBUS_PORT_RESERVED 7 /* 7 reserved */
2ed06c93 1171#define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1)
f899fc64
CW
1172#define GMBUS1 0x5104 /* command/status */
1173#define GMBUS_SW_CLR_INT (1<<31)
1174#define GMBUS_SW_RDY (1<<30)
1175#define GMBUS_ENT (1<<29) /* enable timeout */
1176#define GMBUS_CYCLE_NONE (0<<25)
1177#define GMBUS_CYCLE_WAIT (1<<25)
1178#define GMBUS_CYCLE_INDEX (2<<25)
1179#define GMBUS_CYCLE_STOP (4<<25)
1180#define GMBUS_BYTE_COUNT_SHIFT 16
1181#define GMBUS_SLAVE_INDEX_SHIFT 8
1182#define GMBUS_SLAVE_ADDR_SHIFT 1
1183#define GMBUS_SLAVE_READ (1<<0)
1184#define GMBUS_SLAVE_WRITE (0<<0)
1185#define GMBUS2 0x5108 /* status */
1186#define GMBUS_INUSE (1<<15)
1187#define GMBUS_HW_WAIT_PHASE (1<<14)
1188#define GMBUS_STALL_TIMEOUT (1<<13)
1189#define GMBUS_INT (1<<12)
1190#define GMBUS_HW_RDY (1<<11)
1191#define GMBUS_SATOER (1<<10)
1192#define GMBUS_ACTIVE (1<<9)
1193#define GMBUS3 0x510c /* data buffer bytes 3-0 */
1194#define GMBUS4 0x5110 /* interrupt mask (Pineview+) */
1195#define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
1196#define GMBUS_NAK_EN (1<<3)
1197#define GMBUS_IDLE_EN (1<<2)
1198#define GMBUS_HW_WAIT_EN (1<<1)
1199#define GMBUS_HW_RDY_EN (1<<0)
1200#define GMBUS5 0x5120 /* byte index */
1201#define GMBUS_2BYTE_INDEX_EN (1<<31)
f0217c42 1202
585fb111
JB
1203/*
1204 * Clock control & power management
1205 */
a57c774a
AK
1206#define DPLL_A_OFFSET 0x6014
1207#define DPLL_B_OFFSET 0x6018
5c969aa7
DL
1208#define DPLL(pipe) (dev_priv->info.dpll_offsets[pipe] + \
1209 dev_priv->info.display_mmio_offset)
585fb111
JB
1210
1211#define VGA0 0x6000
1212#define VGA1 0x6004
1213#define VGA_PD 0x6010
1214#define VGA0_PD_P2_DIV_4 (1 << 7)
1215#define VGA0_PD_P1_DIV_2 (1 << 5)
1216#define VGA0_PD_P1_SHIFT 0
1217#define VGA0_PD_P1_MASK (0x1f << 0)
1218#define VGA1_PD_P2_DIV_4 (1 << 15)
1219#define VGA1_PD_P1_DIV_2 (1 << 13)
1220#define VGA1_PD_P1_SHIFT 8
1221#define VGA1_PD_P1_MASK (0x1f << 8)
585fb111 1222#define DPLL_VCO_ENABLE (1 << 31)
4a33e48d
DV
1223#define DPLL_SDVO_HIGH_SPEED (1 << 30)
1224#define DPLL_DVO_2X_MODE (1 << 30)
25eb05fc 1225#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
585fb111 1226#define DPLL_SYNCLOCK_ENABLE (1 << 29)
25eb05fc 1227#define DPLL_REFA_CLK_ENABLE_VLV (1 << 29)
585fb111
JB
1228#define DPLL_VGA_MODE_DIS (1 << 28)
1229#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
1230#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
1231#define DPLL_MODE_MASK (3 << 26)
1232#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
1233#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
1234#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
1235#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
1236#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
1237#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
f2b115e6 1238#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
a0c4da24 1239#define DPLL_LOCK_VLV (1<<15)
598fac6b 1240#define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14)
25eb05fc 1241#define DPLL_INTEGRATED_CLOCK_VLV (1<<13)
598fac6b
DV
1242#define DPLL_PORTC_READY_MASK (0xf << 4)
1243#define DPLL_PORTB_READY_MASK (0xf)
585fb111 1244
585fb111
JB
1245#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
1246/*
1247 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
1248 * this field (only one bit may be set).
1249 */
1250#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
1251#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
f2b115e6 1252#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
585fb111
JB
1253/* i830, required in DVO non-gang */
1254#define PLL_P2_DIVIDE_BY_4 (1 << 23)
1255#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
1256#define PLL_REF_INPUT_DREFCLK (0 << 13)
1257#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
1258#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
1259#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
1260#define PLL_REF_INPUT_MASK (3 << 13)
1261#define PLL_LOAD_PULSE_PHASE_SHIFT 9
f2b115e6 1262/* Ironlake */
b9055052
ZW
1263# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
1264# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
1265# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
1266# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
1267# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
1268
585fb111
JB
1269/*
1270 * Parallel to Serial Load Pulse phase selection.
1271 * Selects the phase for the 10X DPLL clock for the PCIe
1272 * digital display port. The range is 4 to 13; 10 or more
1273 * is just a flip delay. The default is 6
1274 */
1275#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
1276#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
1277/*
1278 * SDVO multiplier for 945G/GM. Not used on 965.
1279 */
1280#define SDVO_MULTIPLIER_MASK 0x000000ff
1281#define SDVO_MULTIPLIER_SHIFT_HIRES 4
1282#define SDVO_MULTIPLIER_SHIFT_VGA 0
a57c774a
AK
1283
1284#define DPLL_A_MD_OFFSET 0x601c /* 965+ only */
1285#define DPLL_B_MD_OFFSET 0x6020 /* 965+ only */
5c969aa7
DL
1286#define DPLL_MD(pipe) (dev_priv->info.dpll_md_offsets[pipe] + \
1287 dev_priv->info.display_mmio_offset)
a57c774a 1288
585fb111
JB
1289/*
1290 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
1291 *
1292 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
1293 */
1294#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
1295#define DPLL_MD_UDI_DIVIDER_SHIFT 24
1296/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
1297#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
1298#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
1299/*
1300 * SDVO/UDI pixel multiplier.
1301 *
1302 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
1303 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
1304 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
1305 * dummy bytes in the datastream at an increased clock rate, with both sides of
1306 * the link knowing how many bytes are fill.
1307 *
1308 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
1309 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
1310 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
1311 * through an SDVO command.
1312 *
1313 * This register field has values of multiplication factor minus 1, with
1314 * a maximum multiplier of 5 for SDVO.
1315 */
1316#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
1317#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
1318/*
1319 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
1320 * This best be set to the default value (3) or the CRT won't work. No,
1321 * I don't entirely understand what this does...
1322 */
1323#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
1324#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
25eb05fc 1325
9db4a9c7
JB
1326#define _FPA0 0x06040
1327#define _FPA1 0x06044
1328#define _FPB0 0x06048
1329#define _FPB1 0x0604c
1330#define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
1331#define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
585fb111 1332#define FP_N_DIV_MASK 0x003f0000
f2b115e6 1333#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
585fb111
JB
1334#define FP_N_DIV_SHIFT 16
1335#define FP_M1_DIV_MASK 0x00003f00
1336#define FP_M1_DIV_SHIFT 8
1337#define FP_M2_DIV_MASK 0x0000003f
f2b115e6 1338#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
585fb111
JB
1339#define FP_M2_DIV_SHIFT 0
1340#define DPLL_TEST 0x606c
1341#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
1342#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
1343#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
1344#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
1345#define DPLLB_TEST_N_BYPASS (1 << 19)
1346#define DPLLB_TEST_M_BYPASS (1 << 18)
1347#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
1348#define DPLLA_TEST_N_BYPASS (1 << 3)
1349#define DPLLA_TEST_M_BYPASS (1 << 2)
1350#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
1351#define D_STATE 0x6104
dc96e9b8 1352#define DSTATE_GFX_RESET_I830 (1<<6)
652c393a
JB
1353#define DSTATE_PLL_D3_OFF (1<<3)
1354#define DSTATE_GFX_CLOCK_GATING (1<<1)
1355#define DSTATE_DOT_CLOCK_GATING (1<<0)
5c969aa7 1356#define DSPCLK_GATE_D (dev_priv->info.display_mmio_offset + 0x6200)
652c393a
JB
1357# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
1358# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
1359# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
1360# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
1361# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
1362# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
1363# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
1364# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
1365# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
1366# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
1367# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
1368# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
1369# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
1370# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
1371# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
1372# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
1373# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
1374# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
1375# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
1376# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
1377# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
1378# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
1379# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
1380# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
1381# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
1382# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
1383# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
1384# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
1385/**
1386 * This bit must be set on the 830 to prevent hangs when turning off the
1387 * overlay scaler.
1388 */
1389# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
1390# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
1391# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
1392# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
1393# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
1394
1395#define RENCLK_GATE_D1 0x6204
1396# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
1397# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
1398# define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
1399# define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
1400# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
1401# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
1402# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
1403# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
1404# define MAG_CLOCK_GATE_DISABLE (1 << 5)
1405/** This bit must be unset on 855,865 */
1406# define MECI_CLOCK_GATE_DISABLE (1 << 4)
1407# define DCMP_CLOCK_GATE_DISABLE (1 << 3)
1408# define MEC_CLOCK_GATE_DISABLE (1 << 2)
1409# define MECO_CLOCK_GATE_DISABLE (1 << 1)
1410/** This bit must be set on 855,865. */
1411# define SV_CLOCK_GATE_DISABLE (1 << 0)
1412# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
1413# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
1414# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
1415# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
1416# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
1417# define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
1418# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
1419# define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
1420# define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
1421# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
1422# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
1423# define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
1424# define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
1425# define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
1426# define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
1427# define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
1428# define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
1429
1430# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
1431/** This bit must always be set on 965G/965GM */
1432# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
1433# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
1434# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
1435# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
1436# define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
1437# define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
1438/** This bit must always be set on 965G */
1439# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
1440# define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
1441# define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
1442# define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
1443# define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
1444# define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
1445# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
1446# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
1447# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
1448# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
1449# define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
1450# define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
1451# define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
1452# define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
1453# define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
1454# define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
1455# define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
1456# define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
1457# define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
1458
1459#define RENCLK_GATE_D2 0x6208
1460#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
1461#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
1462#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
1463#define RAMCLK_GATE_D 0x6210 /* CRL only */
1464#define DEUC 0x6214 /* CRL only */
585fb111 1465
d88b2270 1466#define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500)
ceb04246
JB
1467#define FW_CSPWRDWNEN (1<<15)
1468
e0d8d59b
VS
1469#define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504)
1470
24eb2d59
CML
1471#define CZCLK_CDCLK_FREQ_RATIO (VLV_DISPLAY_BASE + 0x6508)
1472#define CDCLK_FREQ_SHIFT 4
1473#define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
1474#define CZCLK_FREQ_MASK 0xf
1475#define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510)
1476
585fb111
JB
1477/*
1478 * Palette regs
1479 */
a57c774a
AK
1480#define PALETTE_A_OFFSET 0xa000
1481#define PALETTE_B_OFFSET 0xa800
5c969aa7
DL
1482#define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \
1483 dev_priv->info.display_mmio_offset)
585fb111 1484
673a394b
EA
1485/* MCH MMIO space */
1486
1487/*
1488 * MCHBAR mirror.
1489 *
1490 * This mirrors the MCHBAR MMIO space whose location is determined by
1491 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
1492 * every way. It is not accessible from the CP register read instructions.
1493 *
515b2392
PZ
1494 * Starting from Haswell, you can't write registers using the MCHBAR mirror,
1495 * just read.
673a394b
EA
1496 */
1497#define MCHBAR_MIRROR_BASE 0x10000
1498
1398261a
YL
1499#define MCHBAR_MIRROR_BASE_SNB 0x140000
1500
3ebecd07 1501/* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
153b4b95 1502#define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04)
3ebecd07 1503
673a394b
EA
1504/** 915-945 and GM965 MCH register controlling DRAM channel access */
1505#define DCC 0x10200
1506#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
1507#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
1508#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
1509#define DCC_ADDRESSING_MODE_MASK (3 << 0)
1510#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
a7f014f2 1511#define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
673a394b 1512
95534263
LP
1513/** Pineview MCH register contains DDR3 setting */
1514#define CSHRDDR3CTL 0x101a8
1515#define CSHRDDR3CTL_DDR3 (1 << 2)
1516
673a394b
EA
1517/** 965 MCH register controlling DRAM channel configuration */
1518#define C0DRB3 0x10206
1519#define C1DRB3 0x10606
1520
f691e2f4
DV
1521/** snb MCH registers for reading the DRAM channel configuration */
1522#define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004)
1523#define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008)
1524#define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C)
1525#define MAD_DIMM_ECC_MASK (0x3 << 24)
1526#define MAD_DIMM_ECC_OFF (0x0 << 24)
1527#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
1528#define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
1529#define MAD_DIMM_ECC_ON (0x3 << 24)
1530#define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
1531#define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
1532#define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
1533#define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
1534#define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
1535#define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
1536#define MAD_DIMM_A_SELECT (0x1 << 16)
1537/* DIMM sizes are in multiples of 256mb. */
1538#define MAD_DIMM_B_SIZE_SHIFT 8
1539#define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
1540#define MAD_DIMM_A_SIZE_SHIFT 0
1541#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
1542
1d7aaa0c
DV
1543/** snb MCH registers for priority tuning */
1544#define MCH_SSKPD (MCHBAR_MIRROR_BASE_SNB + 0x5d10)
1545#define MCH_SSKPD_WM0_MASK 0x3f
1546#define MCH_SSKPD_WM0_VAL 0xc
f691e2f4 1547
ec013e7f
JB
1548#define MCH_SECP_NRG_STTS (MCHBAR_MIRROR_BASE_SNB + 0x592c)
1549
b11248df
KP
1550/* Clocking configuration register */
1551#define CLKCFG 0x10c00
7662c8bd 1552#define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
b11248df
KP
1553#define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
1554#define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
1555#define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
1556#define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
1557#define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
7662c8bd 1558/* Note, below two are guess */
b11248df 1559#define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
7662c8bd 1560#define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
b11248df 1561#define CLKCFG_FSB_MASK (7 << 0)
7662c8bd
SL
1562#define CLKCFG_MEM_533 (1 << 4)
1563#define CLKCFG_MEM_667 (2 << 4)
1564#define CLKCFG_MEM_800 (3 << 4)
1565#define CLKCFG_MEM_MASK (7 << 4)
1566
ea056c14
JB
1567#define TSC1 0x11001
1568#define TSE (1<<0)
7648fa99
JB
1569#define TR1 0x11006
1570#define TSFS 0x11020
1571#define TSFS_SLOPE_MASK 0x0000ff00
1572#define TSFS_SLOPE_SHIFT 8
1573#define TSFS_INTR_MASK 0x000000ff
1574
f97108d1
JB
1575#define CRSTANDVID 0x11100
1576#define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
1577#define PXVFREQ_PX_MASK 0x7f000000
1578#define PXVFREQ_PX_SHIFT 24
1579#define VIDFREQ_BASE 0x11110
1580#define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
1581#define VIDFREQ2 0x11114
1582#define VIDFREQ3 0x11118
1583#define VIDFREQ4 0x1111c
1584#define VIDFREQ_P0_MASK 0x1f000000
1585#define VIDFREQ_P0_SHIFT 24
1586#define VIDFREQ_P0_CSCLK_MASK 0x00f00000
1587#define VIDFREQ_P0_CSCLK_SHIFT 20
1588#define VIDFREQ_P0_CRCLK_MASK 0x000f0000
1589#define VIDFREQ_P0_CRCLK_SHIFT 16
1590#define VIDFREQ_P1_MASK 0x00001f00
1591#define VIDFREQ_P1_SHIFT 8
1592#define VIDFREQ_P1_CSCLK_MASK 0x000000f0
1593#define VIDFREQ_P1_CSCLK_SHIFT 4
1594#define VIDFREQ_P1_CRCLK_MASK 0x0000000f
1595#define INTTOEXT_BASE_ILK 0x11300
1596#define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */
1597#define INTTOEXT_MAP3_SHIFT 24
1598#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
1599#define INTTOEXT_MAP2_SHIFT 16
1600#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
1601#define INTTOEXT_MAP1_SHIFT 8
1602#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
1603#define INTTOEXT_MAP0_SHIFT 0
1604#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
1605#define MEMSWCTL 0x11170 /* Ironlake only */
1606#define MEMCTL_CMD_MASK 0xe000
1607#define MEMCTL_CMD_SHIFT 13
1608#define MEMCTL_CMD_RCLK_OFF 0
1609#define MEMCTL_CMD_RCLK_ON 1
1610#define MEMCTL_CMD_CHFREQ 2
1611#define MEMCTL_CMD_CHVID 3
1612#define MEMCTL_CMD_VMMOFF 4
1613#define MEMCTL_CMD_VMMON 5
1614#define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
1615 when command complete */
1616#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
1617#define MEMCTL_FREQ_SHIFT 8
1618#define MEMCTL_SFCAVM (1<<7)
1619#define MEMCTL_TGT_VID_MASK 0x007f
1620#define MEMIHYST 0x1117c
1621#define MEMINTREN 0x11180 /* 16 bits */
1622#define MEMINT_RSEXIT_EN (1<<8)
1623#define MEMINT_CX_SUPR_EN (1<<7)
1624#define MEMINT_CONT_BUSY_EN (1<<6)
1625#define MEMINT_AVG_BUSY_EN (1<<5)
1626#define MEMINT_EVAL_CHG_EN (1<<4)
1627#define MEMINT_MON_IDLE_EN (1<<3)
1628#define MEMINT_UP_EVAL_EN (1<<2)
1629#define MEMINT_DOWN_EVAL_EN (1<<1)
1630#define MEMINT_SW_CMD_EN (1<<0)
1631#define MEMINTRSTR 0x11182 /* 16 bits */
1632#define MEM_RSEXIT_MASK 0xc000
1633#define MEM_RSEXIT_SHIFT 14
1634#define MEM_CONT_BUSY_MASK 0x3000
1635#define MEM_CONT_BUSY_SHIFT 12
1636#define MEM_AVG_BUSY_MASK 0x0c00
1637#define MEM_AVG_BUSY_SHIFT 10
1638#define MEM_EVAL_CHG_MASK 0x0300
1639#define MEM_EVAL_BUSY_SHIFT 8
1640#define MEM_MON_IDLE_MASK 0x00c0
1641#define MEM_MON_IDLE_SHIFT 6
1642#define MEM_UP_EVAL_MASK 0x0030
1643#define MEM_UP_EVAL_SHIFT 4
1644#define MEM_DOWN_EVAL_MASK 0x000c
1645#define MEM_DOWN_EVAL_SHIFT 2
1646#define MEM_SW_CMD_MASK 0x0003
1647#define MEM_INT_STEER_GFX 0
1648#define MEM_INT_STEER_CMR 1
1649#define MEM_INT_STEER_SMI 2
1650#define MEM_INT_STEER_SCI 3
1651#define MEMINTRSTS 0x11184
1652#define MEMINT_RSEXIT (1<<7)
1653#define MEMINT_CONT_BUSY (1<<6)
1654#define MEMINT_AVG_BUSY (1<<5)
1655#define MEMINT_EVAL_CHG (1<<4)
1656#define MEMINT_MON_IDLE (1<<3)
1657#define MEMINT_UP_EVAL (1<<2)
1658#define MEMINT_DOWN_EVAL (1<<1)
1659#define MEMINT_SW_CMD (1<<0)
1660#define MEMMODECTL 0x11190
1661#define MEMMODE_BOOST_EN (1<<31)
1662#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
1663#define MEMMODE_BOOST_FREQ_SHIFT 24
1664#define MEMMODE_IDLE_MODE_MASK 0x00030000
1665#define MEMMODE_IDLE_MODE_SHIFT 16
1666#define MEMMODE_IDLE_MODE_EVAL 0
1667#define MEMMODE_IDLE_MODE_CONT 1
1668#define MEMMODE_HWIDLE_EN (1<<15)
1669#define MEMMODE_SWMODE_EN (1<<14)
1670#define MEMMODE_RCLK_GATE (1<<13)
1671#define MEMMODE_HW_UPDATE (1<<12)
1672#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
1673#define MEMMODE_FSTART_SHIFT 8
1674#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
1675#define MEMMODE_FMAX_SHIFT 4
1676#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
1677#define RCBMAXAVG 0x1119c
1678#define MEMSWCTL2 0x1119e /* Cantiga only */
1679#define SWMEMCMD_RENDER_OFF (0 << 13)
1680#define SWMEMCMD_RENDER_ON (1 << 13)
1681#define SWMEMCMD_SWFREQ (2 << 13)
1682#define SWMEMCMD_TARVID (3 << 13)
1683#define SWMEMCMD_VRM_OFF (4 << 13)
1684#define SWMEMCMD_VRM_ON (5 << 13)
1685#define CMDSTS (1<<12)
1686#define SFCAVM (1<<11)
1687#define SWFREQ_MASK 0x0380 /* P0-7 */
1688#define SWFREQ_SHIFT 7
1689#define TARVID_MASK 0x001f
1690#define MEMSTAT_CTG 0x111a0
1691#define RCBMINAVG 0x111a0
1692#define RCUPEI 0x111b0
1693#define RCDNEI 0x111b4
88271da3
JB
1694#define RSTDBYCTL 0x111b8
1695#define RS1EN (1<<31)
1696#define RS2EN (1<<30)
1697#define RS3EN (1<<29)
1698#define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
1699#define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
1700#define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
1701#define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
1702#define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
1703#define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
1704#define RSX_STATUS_MASK (7<<20)
1705#define RSX_STATUS_ON (0<<20)
1706#define RSX_STATUS_RC1 (1<<20)
1707#define RSX_STATUS_RC1E (2<<20)
1708#define RSX_STATUS_RS1 (3<<20)
1709#define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
1710#define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
1711#define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
1712#define RSX_STATUS_RSVD2 (7<<20)
1713#define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
1714#define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
1715#define JRSC (1<<17) /* rsx coupled to cpu c-state */
1716#define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
1717#define RS1CONTSAV_MASK (3<<14)
1718#define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
1719#define RS1CONTSAV_RSVD (1<<14)
1720#define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
1721#define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
1722#define NORMSLEXLAT_MASK (3<<12)
1723#define SLOW_RS123 (0<<12)
1724#define SLOW_RS23 (1<<12)
1725#define SLOW_RS3 (2<<12)
1726#define NORMAL_RS123 (3<<12)
1727#define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
1728#define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
1729#define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
1730#define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
1731#define RS_CSTATE_MASK (3<<4)
1732#define RS_CSTATE_C367_RS1 (0<<4)
1733#define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
1734#define RS_CSTATE_RSVD (2<<4)
1735#define RS_CSTATE_C367_RS2 (3<<4)
1736#define REDSAVES (1<<3) /* no context save if was idle during rs0 */
1737#define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
f97108d1
JB
1738#define VIDCTL 0x111c0
1739#define VIDSTS 0x111c8
1740#define VIDSTART 0x111cc /* 8 bits */
1741#define MEMSTAT_ILK 0x111f8
1742#define MEMSTAT_VID_MASK 0x7f00
1743#define MEMSTAT_VID_SHIFT 8
1744#define MEMSTAT_PSTATE_MASK 0x00f8
1745#define MEMSTAT_PSTATE_SHIFT 3
1746#define MEMSTAT_MON_ACTV (1<<2)
1747#define MEMSTAT_SRC_CTL_MASK 0x0003
1748#define MEMSTAT_SRC_CTL_CORE 0
1749#define MEMSTAT_SRC_CTL_TRB 1
1750#define MEMSTAT_SRC_CTL_THM 2
1751#define MEMSTAT_SRC_CTL_STDBY 3
1752#define RCPREVBSYTUPAVG 0x113b8
1753#define RCPREVBSYTDNAVG 0x113bc
ea056c14
JB
1754#define PMMISC 0x11214
1755#define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
7648fa99
JB
1756#define SDEW 0x1124c
1757#define CSIEW0 0x11250
1758#define CSIEW1 0x11254
1759#define CSIEW2 0x11258
1760#define PEW 0x1125c
1761#define DEW 0x11270
1762#define MCHAFE 0x112c0
1763#define CSIEC 0x112e0
1764#define DMIEC 0x112e4
1765#define DDREC 0x112e8
1766#define PEG0EC 0x112ec
1767#define PEG1EC 0x112f0
1768#define GFXEC 0x112f4
1769#define RPPREVBSYTUPAVG 0x113b8
1770#define RPPREVBSYTDNAVG 0x113bc
1771#define ECR 0x11600
1772#define ECR_GPFE (1<<31)
1773#define ECR_IMONE (1<<30)
1774#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
1775#define OGW0 0x11608
1776#define OGW1 0x1160c
1777#define EG0 0x11610
1778#define EG1 0x11614
1779#define EG2 0x11618
1780#define EG3 0x1161c
1781#define EG4 0x11620
1782#define EG5 0x11624
1783#define EG6 0x11628
1784#define EG7 0x1162c
1785#define PXW 0x11664
1786#define PXWL 0x11680
1787#define LCFUSE02 0x116c0
1788#define LCFUSE_HIV_MASK 0x000000ff
1789#define CSIPLL0 0x12c10
1790#define DDRMPLL1 0X12c20
7d57382e
EA
1791#define PEG_BAND_GAP_DATA 0x14d68
1792
c4de7b0f
CW
1793#define GEN6_GT_THREAD_STATUS_REG 0x13805c
1794#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
1795#define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16))
1796
153b4b95
BW
1797#define GEN6_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x5948)
1798#define GEN6_RP_STATE_LIMITS (MCHBAR_MIRROR_BASE_SNB + 0x5994)
1799#define GEN6_RP_STATE_CAP (MCHBAR_MIRROR_BASE_SNB + 0x5998)
3b8d8d91 1800
aa40d6bb
ZN
1801/*
1802 * Logical Context regs
1803 */
1804#define CCID 0x2180
1805#define CCID_EN (1<<0)
e8016055
VS
1806/*
1807 * Notes on SNB/IVB/VLV context size:
1808 * - Power context is saved elsewhere (LLC or stolen)
1809 * - Ring/execlist context is saved on SNB, not on IVB
1810 * - Extended context size already includes render context size
1811 * - We always need to follow the extended context size.
1812 * SNB BSpec has comments indicating that we should use the
1813 * render context size instead if execlists are disabled, but
1814 * based on empirical testing that's just nonsense.
1815 * - Pipelined/VF state is saved on SNB/IVB respectively
1816 * - GT1 size just indicates how much of render context
1817 * doesn't need saving on GT1
1818 */
fe1cc68f
BW
1819#define CXT_SIZE 0x21a0
1820#define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f)
1821#define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f)
1822#define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f)
1823#define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f)
1824#define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f)
e8016055 1825#define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
fe1cc68f
BW
1826 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
1827 GEN6_CXT_PIPELINE_SIZE(cxt_reg))
4f91dd6f 1828#define GEN7_CXT_SIZE 0x21a8
6a4ea124
BW
1829#define GEN7_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 25) & 0x7f)
1830#define GEN7_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 22) & 0x7)
4f91dd6f
BW
1831#define GEN7_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f)
1832#define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f)
1833#define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7)
1834#define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f)
e8016055 1835#define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
4f91dd6f 1836 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
a0de80a0
BW
1837/* Haswell does have the CXT_SIZE register however it does not appear to be
1838 * valid. Now, docs explain in dwords what is in the context object. The full
1839 * size is 70720 bytes, however, the power context and execlist context will
1840 * never be saved (power context is stored elsewhere, and execlists don't work
1841 * on HSW) - so the final size is 66944 bytes, which rounds to 17 pages.
1842 */
1843#define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE)
8897644a
BW
1844/* Same as Haswell, but 72064 bytes now. */
1845#define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE)
1846
fe1cc68f 1847
e454a05d
JB
1848#define VLV_CLK_CTL2 0x101104
1849#define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
1850
585fb111
JB
1851/*
1852 * Overlay regs
1853 */
1854
1855#define OVADD 0x30000
1856#define DOVSTA 0x30008
1857#define OC_BUF (0x3<<20)
1858#define OGAMC5 0x30010
1859#define OGAMC4 0x30014
1860#define OGAMC3 0x30018
1861#define OGAMC2 0x3001c
1862#define OGAMC1 0x30020
1863#define OGAMC0 0x30024
1864
1865/*
1866 * Display engine regs
1867 */
1868
8bf1e9f1 1869/* Pipe A CRC regs */
a57c774a 1870#define _PIPE_CRC_CTL_A 0x60050
8bf1e9f1 1871#define PIPE_CRC_ENABLE (1 << 31)
b4437a41 1872/* ivb+ source selection */
8bf1e9f1
SH
1873#define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
1874#define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
1875#define PIPE_CRC_SOURCE_PF_IVB (2 << 29)
b4437a41 1876/* ilk+ source selection */
5a6b5c84
DV
1877#define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28)
1878#define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28)
1879#define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28)
1880/* embedded DP port on the north display block, reserved on ivb */
1881#define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28)
1882#define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */
b4437a41
DV
1883/* vlv source selection */
1884#define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27)
1885#define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27)
1886#define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27)
1887/* with DP port the pipe source is invalid */
1888#define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27)
1889#define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27)
1890#define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27)
1891/* gen3+ source selection */
1892#define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28)
1893#define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28)
1894#define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28)
1895/* with DP/TV port the pipe source is invalid */
1896#define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28)
1897#define PIPE_CRC_SOURCE_TV_PRE (4 << 28)
1898#define PIPE_CRC_SOURCE_TV_POST (5 << 28)
1899#define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28)
1900#define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28)
1901/* gen2 doesn't have source selection bits */
52f843f6 1902#define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30)
b4437a41 1903
5a6b5c84
DV
1904#define _PIPE_CRC_RES_1_A_IVB 0x60064
1905#define _PIPE_CRC_RES_2_A_IVB 0x60068
1906#define _PIPE_CRC_RES_3_A_IVB 0x6006c
1907#define _PIPE_CRC_RES_4_A_IVB 0x60070
1908#define _PIPE_CRC_RES_5_A_IVB 0x60074
1909
a57c774a
AK
1910#define _PIPE_CRC_RES_RED_A 0x60060
1911#define _PIPE_CRC_RES_GREEN_A 0x60064
1912#define _PIPE_CRC_RES_BLUE_A 0x60068
1913#define _PIPE_CRC_RES_RES1_A_I915 0x6006c
1914#define _PIPE_CRC_RES_RES2_A_G4X 0x60080
8bf1e9f1
SH
1915
1916/* Pipe B CRC regs */
5a6b5c84
DV
1917#define _PIPE_CRC_RES_1_B_IVB 0x61064
1918#define _PIPE_CRC_RES_2_B_IVB 0x61068
1919#define _PIPE_CRC_RES_3_B_IVB 0x6106c
1920#define _PIPE_CRC_RES_4_B_IVB 0x61070
1921#define _PIPE_CRC_RES_5_B_IVB 0x61074
8bf1e9f1 1922
a57c774a 1923#define PIPE_CRC_CTL(pipe) _TRANSCODER2(pipe, _PIPE_CRC_CTL_A)
8bf1e9f1 1924#define PIPE_CRC_RES_1_IVB(pipe) \
a57c774a 1925 _TRANSCODER2(pipe, _PIPE_CRC_RES_1_A_IVB)
8bf1e9f1 1926#define PIPE_CRC_RES_2_IVB(pipe) \
a57c774a 1927 _TRANSCODER2(pipe, _PIPE_CRC_RES_2_A_IVB)
8bf1e9f1 1928#define PIPE_CRC_RES_3_IVB(pipe) \
a57c774a 1929 _TRANSCODER2(pipe, _PIPE_CRC_RES_3_A_IVB)
8bf1e9f1 1930#define PIPE_CRC_RES_4_IVB(pipe) \
a57c774a 1931 _TRANSCODER2(pipe, _PIPE_CRC_RES_4_A_IVB)
8bf1e9f1 1932#define PIPE_CRC_RES_5_IVB(pipe) \
a57c774a 1933 _TRANSCODER2(pipe, _PIPE_CRC_RES_5_A_IVB)
8bf1e9f1 1934
0b5c5ed0 1935#define PIPE_CRC_RES_RED(pipe) \
a57c774a 1936 _TRANSCODER2(pipe, _PIPE_CRC_RES_RED_A)
0b5c5ed0 1937#define PIPE_CRC_RES_GREEN(pipe) \
a57c774a 1938 _TRANSCODER2(pipe, _PIPE_CRC_RES_GREEN_A)
0b5c5ed0 1939#define PIPE_CRC_RES_BLUE(pipe) \
a57c774a 1940 _TRANSCODER2(pipe, _PIPE_CRC_RES_BLUE_A)
0b5c5ed0 1941#define PIPE_CRC_RES_RES1_I915(pipe) \
a57c774a 1942 _TRANSCODER2(pipe, _PIPE_CRC_RES_RES1_A_I915)
0b5c5ed0 1943#define PIPE_CRC_RES_RES2_G4X(pipe) \
a57c774a 1944 _TRANSCODER2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
5a6b5c84 1945
585fb111 1946/* Pipe A timing regs */
a57c774a
AK
1947#define _HTOTAL_A 0x60000
1948#define _HBLANK_A 0x60004
1949#define _HSYNC_A 0x60008
1950#define _VTOTAL_A 0x6000c
1951#define _VBLANK_A 0x60010
1952#define _VSYNC_A 0x60014
1953#define _PIPEASRC 0x6001c
1954#define _BCLRPAT_A 0x60020
1955#define _VSYNCSHIFT_A 0x60028
585fb111
JB
1956
1957/* Pipe B timing regs */
a57c774a
AK
1958#define _HTOTAL_B 0x61000
1959#define _HBLANK_B 0x61004
1960#define _HSYNC_B 0x61008
1961#define _VTOTAL_B 0x6100c
1962#define _VBLANK_B 0x61010
1963#define _VSYNC_B 0x61014
1964#define _PIPEBSRC 0x6101c
1965#define _BCLRPAT_B 0x61020
1966#define _VSYNCSHIFT_B 0x61028
1967
1968#define TRANSCODER_A_OFFSET 0x60000
1969#define TRANSCODER_B_OFFSET 0x61000
1970#define TRANSCODER_C_OFFSET 0x62000
1971#define TRANSCODER_EDP_OFFSET 0x6f000
1972
5c969aa7
DL
1973#define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \
1974 dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
1975 dev_priv->info.display_mmio_offset)
a57c774a
AK
1976
1977#define HTOTAL(trans) _TRANSCODER2(trans, _HTOTAL_A)
1978#define HBLANK(trans) _TRANSCODER2(trans, _HBLANK_A)
1979#define HSYNC(trans) _TRANSCODER2(trans, _HSYNC_A)
1980#define VTOTAL(trans) _TRANSCODER2(trans, _VTOTAL_A)
1981#define VBLANK(trans) _TRANSCODER2(trans, _VBLANK_A)
1982#define VSYNC(trans) _TRANSCODER2(trans, _VSYNC_A)
1983#define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A)
1984#define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A)
1985#define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC)
5eddb70b 1986
ed8546ac
BW
1987/* HSW+ eDP PSR registers */
1988#define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800)
18b5992c 1989#define EDP_PSR_CTL(dev) (EDP_PSR_BASE(dev) + 0)
2b28bb1b
RV
1990#define EDP_PSR_ENABLE (1<<31)
1991#define EDP_PSR_LINK_DISABLE (0<<27)
1992#define EDP_PSR_LINK_STANDBY (1<<27)
1993#define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
1994#define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25)
1995#define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25)
1996#define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25)
1997#define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25)
1998#define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
1999#define EDP_PSR_SKIP_AUX_EXIT (1<<12)
2000#define EDP_PSR_TP1_TP2_SEL (0<<11)
2001#define EDP_PSR_TP1_TP3_SEL (1<<11)
2002#define EDP_PSR_TP2_TP3_TIME_500us (0<<8)
2003#define EDP_PSR_TP2_TP3_TIME_100us (1<<8)
2004#define EDP_PSR_TP2_TP3_TIME_2500us (2<<8)
2005#define EDP_PSR_TP2_TP3_TIME_0us (3<<8)
2006#define EDP_PSR_TP1_TIME_500us (0<<4)
2007#define EDP_PSR_TP1_TIME_100us (1<<4)
2008#define EDP_PSR_TP1_TIME_2500us (2<<4)
2009#define EDP_PSR_TP1_TIME_0us (3<<4)
2010#define EDP_PSR_IDLE_FRAME_SHIFT 0
2011
18b5992c
BW
2012#define EDP_PSR_AUX_CTL(dev) (EDP_PSR_BASE(dev) + 0x10)
2013#define EDP_PSR_AUX_DATA1(dev) (EDP_PSR_BASE(dev) + 0x14)
2b28bb1b 2014#define EDP_PSR_DPCD_COMMAND 0x80060000
18b5992c 2015#define EDP_PSR_AUX_DATA2(dev) (EDP_PSR_BASE(dev) + 0x18)
2b28bb1b 2016#define EDP_PSR_DPCD_NORMAL_OPERATION (1<<24)
18b5992c
BW
2017#define EDP_PSR_AUX_DATA3(dev) (EDP_PSR_BASE(dev) + 0x1c)
2018#define EDP_PSR_AUX_DATA4(dev) (EDP_PSR_BASE(dev) + 0x20)
2019#define EDP_PSR_AUX_DATA5(dev) (EDP_PSR_BASE(dev) + 0x24)
2b28bb1b 2020
18b5992c 2021#define EDP_PSR_STATUS_CTL(dev) (EDP_PSR_BASE(dev) + 0x40)
2b28bb1b 2022#define EDP_PSR_STATUS_STATE_MASK (7<<29)
e91fd8c6
RV
2023#define EDP_PSR_STATUS_STATE_IDLE (0<<29)
2024#define EDP_PSR_STATUS_STATE_SRDONACK (1<<29)
2025#define EDP_PSR_STATUS_STATE_SRDENT (2<<29)
2026#define EDP_PSR_STATUS_STATE_BUFOFF (3<<29)
2027#define EDP_PSR_STATUS_STATE_BUFON (4<<29)
2028#define EDP_PSR_STATUS_STATE_AUXACK (5<<29)
2029#define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29)
2030#define EDP_PSR_STATUS_LINK_MASK (3<<26)
2031#define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26)
2032#define EDP_PSR_STATUS_LINK_FULL_ON (1<<26)
2033#define EDP_PSR_STATUS_LINK_STANDBY (2<<26)
2034#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20
2035#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f
2036#define EDP_PSR_STATUS_COUNT_SHIFT 16
2037#define EDP_PSR_STATUS_COUNT_MASK 0xf
2038#define EDP_PSR_STATUS_AUX_ERROR (1<<15)
2039#define EDP_PSR_STATUS_AUX_SENDING (1<<12)
2040#define EDP_PSR_STATUS_SENDING_IDLE (1<<9)
2041#define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8)
2042#define EDP_PSR_STATUS_SENDING_TP1 (1<<4)
2043#define EDP_PSR_STATUS_IDLE_MASK 0xf
2044
18b5992c 2045#define EDP_PSR_PERF_CNT(dev) (EDP_PSR_BASE(dev) + 0x44)
e91fd8c6 2046#define EDP_PSR_PERF_CNT_MASK 0xffffff
2b28bb1b 2047
18b5992c 2048#define EDP_PSR_DEBUG_CTL(dev) (EDP_PSR_BASE(dev) + 0x60)
2b28bb1b
RV
2049#define EDP_PSR_DEBUG_MASK_LPSP (1<<27)
2050#define EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
2051#define EDP_PSR_DEBUG_MASK_HPD (1<<25)
2052
585fb111
JB
2053/* VGA port control */
2054#define ADPA 0x61100
ebc0fd88 2055#define PCH_ADPA 0xe1100
540a8950 2056#define VLV_ADPA (VLV_DISPLAY_BASE + ADPA)
ebc0fd88 2057
585fb111
JB
2058#define ADPA_DAC_ENABLE (1<<31)
2059#define ADPA_DAC_DISABLE 0
2060#define ADPA_PIPE_SELECT_MASK (1<<30)
2061#define ADPA_PIPE_A_SELECT 0
2062#define ADPA_PIPE_B_SELECT (1<<30)
1519b995 2063#define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
ebc0fd88
DV
2064/* CPT uses bits 29:30 for pch transcoder select */
2065#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
2066#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
2067#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
2068#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
2069#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
2070#define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
2071#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
2072#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
2073#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
2074#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
2075#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
2076#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
2077#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
2078#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
2079#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
2080#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
2081#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
2082#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
2083#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
585fb111
JB
2084#define ADPA_USE_VGA_HVPOLARITY (1<<15)
2085#define ADPA_SETS_HVPOLARITY 0
60222c0c 2086#define ADPA_VSYNC_CNTL_DISABLE (1<<10)
585fb111 2087#define ADPA_VSYNC_CNTL_ENABLE 0
60222c0c 2088#define ADPA_HSYNC_CNTL_DISABLE (1<<11)
585fb111
JB
2089#define ADPA_HSYNC_CNTL_ENABLE 0
2090#define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
2091#define ADPA_VSYNC_ACTIVE_LOW 0
2092#define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
2093#define ADPA_HSYNC_ACTIVE_LOW 0
2094#define ADPA_DPMS_MASK (~(3<<10))
2095#define ADPA_DPMS_ON (0<<10)
2096#define ADPA_DPMS_SUSPEND (1<<10)
2097#define ADPA_DPMS_STANDBY (2<<10)
2098#define ADPA_DPMS_OFF (3<<10)
2099
939fe4d7 2100
585fb111 2101/* Hotplug control (945+ only) */
5c969aa7 2102#define PORT_HOTPLUG_EN (dev_priv->info.display_mmio_offset + 0x61110)
26739f12
DV
2103#define PORTB_HOTPLUG_INT_EN (1 << 29)
2104#define PORTC_HOTPLUG_INT_EN (1 << 28)
2105#define PORTD_HOTPLUG_INT_EN (1 << 27)
585fb111
JB
2106#define SDVOB_HOTPLUG_INT_EN (1 << 26)
2107#define SDVOC_HOTPLUG_INT_EN (1 << 25)
2108#define TV_HOTPLUG_INT_EN (1 << 18)
2109#define CRT_HOTPLUG_INT_EN (1 << 9)
e5868a31
EE
2110#define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
2111 PORTC_HOTPLUG_INT_EN | \
2112 PORTD_HOTPLUG_INT_EN | \
2113 SDVOC_HOTPLUG_INT_EN | \
2114 SDVOB_HOTPLUG_INT_EN | \
2115 CRT_HOTPLUG_INT_EN)
585fb111 2116#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
771cb081
ZY
2117#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
2118/* must use period 64 on GM45 according to docs */
2119#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
2120#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
2121#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
2122#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
2123#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
2124#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
2125#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
2126#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
2127#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
2128#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
2129#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
2130#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
585fb111 2131
5c969aa7 2132#define PORT_HOTPLUG_STAT (dev_priv->info.display_mmio_offset + 0x61114)
0ce99f74
DV
2133/*
2134 * HDMI/DP bits are gen4+
2135 *
2136 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
2137 * Please check the detailed lore in the commit message for for experimental
2138 * evidence.
2139 */
232a6ee9
TP
2140#define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
2141#define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
2142#define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
2143/* VLV DP/HDMI bits again match Bspec */
2144#define PORTD_HOTPLUG_LIVE_STATUS_VLV (1 << 27)
2145#define PORTC_HOTPLUG_LIVE_STATUS_VLV (1 << 28)
2146#define PORTB_HOTPLUG_LIVE_STATUS_VLV (1 << 29)
26739f12
DV
2147#define PORTD_HOTPLUG_INT_STATUS (3 << 21)
2148#define PORTC_HOTPLUG_INT_STATUS (3 << 19)
2149#define PORTB_HOTPLUG_INT_STATUS (3 << 17)
084b612e 2150/* CRT/TV common between gen3+ */
585fb111
JB
2151#define CRT_HOTPLUG_INT_STATUS (1 << 11)
2152#define TV_HOTPLUG_INT_STATUS (1 << 10)
2153#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
2154#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
2155#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
2156#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
4aeebd74
DV
2157#define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
2158#define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
2159#define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
bfbdb420
ID
2160#define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
2161
084b612e
CW
2162/* SDVO is different across gen3/4 */
2163#define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
2164#define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
4f7fd709
DV
2165/*
2166 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
2167 * since reality corrobates that they're the same as on gen3. But keep these
2168 * bits here (and the comment!) to help any other lost wanderers back onto the
2169 * right tracks.
2170 */
084b612e
CW
2171#define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
2172#define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
2173#define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
2174#define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
e5868a31
EE
2175#define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
2176 SDVOB_HOTPLUG_INT_STATUS_G4X | \
2177 SDVOC_HOTPLUG_INT_STATUS_G4X | \
2178 PORTB_HOTPLUG_INT_STATUS | \
2179 PORTC_HOTPLUG_INT_STATUS | \
2180 PORTD_HOTPLUG_INT_STATUS)
e5868a31
EE
2181
2182#define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
2183 SDVOB_HOTPLUG_INT_STATUS_I915 | \
2184 SDVOC_HOTPLUG_INT_STATUS_I915 | \
2185 PORTB_HOTPLUG_INT_STATUS | \
2186 PORTC_HOTPLUG_INT_STATUS | \
2187 PORTD_HOTPLUG_INT_STATUS)
585fb111 2188
c20cd312
PZ
2189/* SDVO and HDMI port control.
2190 * The same register may be used for SDVO or HDMI */
2191#define GEN3_SDVOB 0x61140
2192#define GEN3_SDVOC 0x61160
2193#define GEN4_HDMIB GEN3_SDVOB
2194#define GEN4_HDMIC GEN3_SDVOC
2195#define PCH_SDVOB 0xe1140
2196#define PCH_HDMIB PCH_SDVOB
2197#define PCH_HDMIC 0xe1150
2198#define PCH_HDMID 0xe1160
2199
84093603
DV
2200#define PORT_DFT_I9XX 0x61150
2201#define DC_BALANCE_RESET (1 << 25)
2202#define PORT_DFT2_G4X 0x61154
2203#define DC_BALANCE_RESET_VLV (1 << 31)
2204#define PIPE_SCRAMBLE_RESET_MASK (0x3 << 0)
2205#define PIPE_B_SCRAMBLE_RESET (1 << 1)
2206#define PIPE_A_SCRAMBLE_RESET (1 << 0)
2207
c20cd312
PZ
2208/* Gen 3 SDVO bits: */
2209#define SDVO_ENABLE (1 << 31)
dc0fa718
PZ
2210#define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
2211#define SDVO_PIPE_SEL_MASK (1 << 30)
c20cd312
PZ
2212#define SDVO_PIPE_B_SELECT (1 << 30)
2213#define SDVO_STALL_SELECT (1 << 29)
2214#define SDVO_INTERRUPT_ENABLE (1 << 26)
585fb111
JB
2215/**
2216 * 915G/GM SDVO pixel multiplier.
585fb111 2217 * Programmed value is multiplier - 1, up to 5x.
585fb111
JB
2218 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
2219 */
c20cd312 2220#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
585fb111 2221#define SDVO_PORT_MULTIPLY_SHIFT 23
c20cd312
PZ
2222#define SDVO_PHASE_SELECT_MASK (15 << 19)
2223#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
2224#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
2225#define SDVOC_GANG_MODE (1 << 16) /* Port C only */
2226#define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
2227#define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
2228#define SDVO_DETECTED (1 << 2)
585fb111 2229/* Bits to be preserved when writing */
c20cd312
PZ
2230#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
2231 SDVO_INTERRUPT_ENABLE)
2232#define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
2233
2234/* Gen 4 SDVO/HDMI bits: */
4f3a8bc7 2235#define SDVO_COLOR_FORMAT_8bpc (0 << 26)
18442d08 2236#define SDVO_COLOR_FORMAT_MASK (7 << 26)
c20cd312
PZ
2237#define SDVO_ENCODING_SDVO (0 << 10)
2238#define SDVO_ENCODING_HDMI (2 << 10)
dc0fa718
PZ
2239#define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
2240#define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
4f3a8bc7 2241#define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
c20cd312
PZ
2242#define SDVO_AUDIO_ENABLE (1 << 6)
2243/* VSYNC/HSYNC bits new with 965, default is to be set */
2244#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
2245#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
2246
2247/* Gen 5 (IBX) SDVO/HDMI bits: */
4f3a8bc7 2248#define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
c20cd312
PZ
2249#define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
2250
2251/* Gen 6 (CPT) SDVO/HDMI bits: */
dc0fa718
PZ
2252#define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
2253#define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
c20cd312 2254
585fb111
JB
2255
2256/* DVO port control */
2257#define DVOA 0x61120
2258#define DVOB 0x61140
2259#define DVOC 0x61160
2260#define DVO_ENABLE (1 << 31)
2261#define DVO_PIPE_B_SELECT (1 << 30)
2262#define DVO_PIPE_STALL_UNUSED (0 << 28)
2263#define DVO_PIPE_STALL (1 << 28)
2264#define DVO_PIPE_STALL_TV (2 << 28)
2265#define DVO_PIPE_STALL_MASK (3 << 28)
2266#define DVO_USE_VGA_SYNC (1 << 15)
2267#define DVO_DATA_ORDER_I740 (0 << 14)
2268#define DVO_DATA_ORDER_FP (1 << 14)
2269#define DVO_VSYNC_DISABLE (1 << 11)
2270#define DVO_HSYNC_DISABLE (1 << 10)
2271#define DVO_VSYNC_TRISTATE (1 << 9)
2272#define DVO_HSYNC_TRISTATE (1 << 8)
2273#define DVO_BORDER_ENABLE (1 << 7)
2274#define DVO_DATA_ORDER_GBRG (1 << 6)
2275#define DVO_DATA_ORDER_RGGB (0 << 6)
2276#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
2277#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
2278#define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
2279#define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
2280#define DVO_BLANK_ACTIVE_HIGH (1 << 2)
2281#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
2282#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
2283#define DVO_PRESERVE_MASK (0x7<<24)
2284#define DVOA_SRCDIM 0x61124
2285#define DVOB_SRCDIM 0x61144
2286#define DVOC_SRCDIM 0x61164
2287#define DVO_SRCDIM_HORIZONTAL_SHIFT 12
2288#define DVO_SRCDIM_VERTICAL_SHIFT 0
2289
2290/* LVDS port control */
2291#define LVDS 0x61180
2292/*
2293 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
2294 * the DPLL semantics change when the LVDS is assigned to that pipe.
2295 */
2296#define LVDS_PORT_EN (1 << 31)
2297/* Selects pipe B for LVDS data. Must be set on pre-965. */
2298#define LVDS_PIPEB_SELECT (1 << 30)
47a05eca 2299#define LVDS_PIPE_MASK (1 << 30)
1519b995 2300#define LVDS_PIPE(pipe) ((pipe) << 30)
898822ce
ZY
2301/* LVDS dithering flag on 965/g4x platform */
2302#define LVDS_ENABLE_DITHER (1 << 25)
aa9b500d
BF
2303/* LVDS sync polarity flags. Set to invert (i.e. negative) */
2304#define LVDS_VSYNC_POLARITY (1 << 21)
2305#define LVDS_HSYNC_POLARITY (1 << 20)
2306
a3e17eb8
ZY
2307/* Enable border for unscaled (or aspect-scaled) display */
2308#define LVDS_BORDER_ENABLE (1 << 15)
585fb111
JB
2309/*
2310 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
2311 * pixel.
2312 */
2313#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
2314#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
2315#define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
2316/*
2317 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
2318 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
2319 * on.
2320 */
2321#define LVDS_A3_POWER_MASK (3 << 6)
2322#define LVDS_A3_POWER_DOWN (0 << 6)
2323#define LVDS_A3_POWER_UP (3 << 6)
2324/*
2325 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
2326 * is set.
2327 */
2328#define LVDS_CLKB_POWER_MASK (3 << 4)
2329#define LVDS_CLKB_POWER_DOWN (0 << 4)
2330#define LVDS_CLKB_POWER_UP (3 << 4)
2331/*
2332 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
2333 * setting for whether we are in dual-channel mode. The B3 pair will
2334 * additionally only be powered up when LVDS_A3_POWER_UP is set.
2335 */
2336#define LVDS_B0B3_POWER_MASK (3 << 2)
2337#define LVDS_B0B3_POWER_DOWN (0 << 2)
2338#define LVDS_B0B3_POWER_UP (3 << 2)
2339
3c17fe4b
DH
2340/* Video Data Island Packet control */
2341#define VIDEO_DIP_DATA 0x61178
adf00b26
PZ
2342/* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC
2343 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
2344 * of the infoframe structure specified by CEA-861. */
2345#define VIDEO_DIP_DATA_SIZE 32
2b28bb1b 2346#define VIDEO_DIP_VSC_DATA_SIZE 36
3c17fe4b 2347#define VIDEO_DIP_CTL 0x61170
2da8af54 2348/* Pre HSW: */
3c17fe4b 2349#define VIDEO_DIP_ENABLE (1 << 31)
822cdc52 2350#define VIDEO_DIP_PORT(port) ((port) << 29)
3e6e6395 2351#define VIDEO_DIP_PORT_MASK (3 << 29)
0dd87d20 2352#define VIDEO_DIP_ENABLE_GCP (1 << 25)
3c17fe4b
DH
2353#define VIDEO_DIP_ENABLE_AVI (1 << 21)
2354#define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
0dd87d20 2355#define VIDEO_DIP_ENABLE_GAMUT (4 << 21)
3c17fe4b
DH
2356#define VIDEO_DIP_ENABLE_SPD (8 << 21)
2357#define VIDEO_DIP_SELECT_AVI (0 << 19)
2358#define VIDEO_DIP_SELECT_VENDOR (1 << 19)
2359#define VIDEO_DIP_SELECT_SPD (3 << 19)
45187ace 2360#define VIDEO_DIP_SELECT_MASK (3 << 19)
3c17fe4b
DH
2361#define VIDEO_DIP_FREQ_ONCE (0 << 16)
2362#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
2363#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
60c5ea2d 2364#define VIDEO_DIP_FREQ_MASK (3 << 16)
2da8af54 2365/* HSW and later: */
0dd87d20
PZ
2366#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
2367#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
2da8af54 2368#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
0dd87d20
PZ
2369#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
2370#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
2da8af54 2371#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
3c17fe4b 2372
585fb111
JB
2373/* Panel power sequencing */
2374#define PP_STATUS 0x61200
2375#define PP_ON (1 << 31)
2376/*
2377 * Indicates that all dependencies of the panel are on:
2378 *
2379 * - PLL enabled
2380 * - pipe enabled
2381 * - LVDS/DVOB/DVOC on
2382 */
2383#define PP_READY (1 << 30)
2384#define PP_SEQUENCE_NONE (0 << 28)
99ea7127
KP
2385#define PP_SEQUENCE_POWER_UP (1 << 28)
2386#define PP_SEQUENCE_POWER_DOWN (2 << 28)
2387#define PP_SEQUENCE_MASK (3 << 28)
2388#define PP_SEQUENCE_SHIFT 28
01cb9ea6 2389#define PP_CYCLE_DELAY_ACTIVE (1 << 27)
01cb9ea6 2390#define PP_SEQUENCE_STATE_MASK 0x0000000f
99ea7127
KP
2391#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
2392#define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
2393#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
2394#define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
2395#define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
2396#define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0)
2397#define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
2398#define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
2399#define PP_SEQUENCE_STATE_RESET (0xf << 0)
585fb111
JB
2400#define PP_CONTROL 0x61204
2401#define POWER_TARGET_ON (1 << 0)
2402#define PP_ON_DELAYS 0x61208
2403#define PP_OFF_DELAYS 0x6120c
2404#define PP_DIVISOR 0x61210
2405
2406/* Panel fitting */
5c969aa7 2407#define PFIT_CONTROL (dev_priv->info.display_mmio_offset + 0x61230)
585fb111
JB
2408#define PFIT_ENABLE (1 << 31)
2409#define PFIT_PIPE_MASK (3 << 29)
2410#define PFIT_PIPE_SHIFT 29
2411#define VERT_INTERP_DISABLE (0 << 10)
2412#define VERT_INTERP_BILINEAR (1 << 10)
2413#define VERT_INTERP_MASK (3 << 10)
2414#define VERT_AUTO_SCALE (1 << 9)
2415#define HORIZ_INTERP_DISABLE (0 << 6)
2416#define HORIZ_INTERP_BILINEAR (1 << 6)
2417#define HORIZ_INTERP_MASK (3 << 6)
2418#define HORIZ_AUTO_SCALE (1 << 5)
2419#define PANEL_8TO6_DITHER_ENABLE (1 << 3)
3fbe18d6
ZY
2420#define PFIT_FILTER_FUZZY (0 << 24)
2421#define PFIT_SCALING_AUTO (0 << 26)
2422#define PFIT_SCALING_PROGRAMMED (1 << 26)
2423#define PFIT_SCALING_PILLAR (2 << 26)
2424#define PFIT_SCALING_LETTER (3 << 26)
5c969aa7 2425#define PFIT_PGM_RATIOS (dev_priv->info.display_mmio_offset + 0x61234)
3fbe18d6
ZY
2426/* Pre-965 */
2427#define PFIT_VERT_SCALE_SHIFT 20
2428#define PFIT_VERT_SCALE_MASK 0xfff00000
2429#define PFIT_HORIZ_SCALE_SHIFT 4
2430#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
2431/* 965+ */
2432#define PFIT_VERT_SCALE_SHIFT_965 16
2433#define PFIT_VERT_SCALE_MASK_965 0x1fff0000
2434#define PFIT_HORIZ_SCALE_SHIFT_965 0
2435#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
2436
5c969aa7 2437#define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238)
585fb111 2438
5c969aa7
DL
2439#define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
2440#define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
07bf139b
JB
2441#define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
2442 _VLV_BLC_PWM_CTL2_B)
2443
5c969aa7
DL
2444#define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
2445#define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
07bf139b
JB
2446#define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
2447 _VLV_BLC_PWM_CTL_B)
2448
5c969aa7
DL
2449#define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
2450#define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
07bf139b
JB
2451#define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
2452 _VLV_BLC_HIST_CTL_B)
2453
585fb111 2454/* Backlight control */
5c969aa7 2455#define BLC_PWM_CTL2 (dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
7cf41601
DV
2456#define BLM_PWM_ENABLE (1 << 31)
2457#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
2458#define BLM_PIPE_SELECT (1 << 29)
2459#define BLM_PIPE_SELECT_IVB (3 << 29)
2460#define BLM_PIPE_A (0 << 29)
2461#define BLM_PIPE_B (1 << 29)
2462#define BLM_PIPE_C (2 << 29) /* ivb + */
35ffda48
JN
2463#define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */
2464#define BLM_TRANSCODER_B BLM_PIPE_B
2465#define BLM_TRANSCODER_C BLM_PIPE_C
2466#define BLM_TRANSCODER_EDP (3 << 29)
7cf41601
DV
2467#define BLM_PIPE(pipe) ((pipe) << 29)
2468#define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
2469#define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
2470#define BLM_PHASE_IN_ENABLE (1 << 25)
2471#define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
2472#define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
2473#define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
2474#define BLM_PHASE_IN_COUNT_SHIFT (8)
2475#define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
2476#define BLM_PHASE_IN_INCR_SHIFT (0)
2477#define BLM_PHASE_IN_INCR_MASK (0xff << 0)
5c969aa7 2478#define BLC_PWM_CTL (dev_priv->info.display_mmio_offset + 0x61254)
ba3820ad
TI
2479/*
2480 * This is the most significant 15 bits of the number of backlight cycles in a
2481 * complete cycle of the modulated backlight control.
2482 *
2483 * The actual value is this field multiplied by two.
2484 */
7cf41601
DV
2485#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
2486#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
2487#define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
585fb111
JB
2488/*
2489 * This is the number of cycles out of the backlight modulation cycle for which
2490 * the backlight is on.
2491 *
2492 * This field must be no greater than the number of cycles in the complete
2493 * backlight modulation cycle.
2494 */
2495#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
2496#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
534b5a53
DV
2497#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
2498#define BLM_POLARITY_PNV (1 << 0) /* pnv only */
585fb111 2499
5c969aa7 2500#define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260)
0eb96d6e 2501
7cf41601
DV
2502/* New registers for PCH-split platforms. Safe where new bits show up, the
2503 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
2504#define BLC_PWM_CPU_CTL2 0x48250
2505#define BLC_PWM_CPU_CTL 0x48254
2506
be256dc7
PZ
2507#define HSW_BLC_PWM2_CTL 0x48350
2508
7cf41601
DV
2509/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
2510 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
2511#define BLC_PWM_PCH_CTL1 0xc8250
4b4147c3 2512#define BLM_PCH_PWM_ENABLE (1 << 31)
7cf41601
DV
2513#define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
2514#define BLM_PCH_POLARITY (1 << 29)
2515#define BLC_PWM_PCH_CTL2 0xc8254
2516
be256dc7
PZ
2517#define UTIL_PIN_CTL 0x48400
2518#define UTIL_PIN_ENABLE (1 << 31)
2519
2520#define PCH_GTC_CTL 0xe7000
2521#define PCH_GTC_ENABLE (1 << 31)
2522
585fb111
JB
2523/* TV port control */
2524#define TV_CTL 0x68000
2525/** Enables the TV encoder */
2526# define TV_ENC_ENABLE (1 << 31)
2527/** Sources the TV encoder input from pipe B instead of A. */
2528# define TV_ENC_PIPEB_SELECT (1 << 30)
2529/** Outputs composite video (DAC A only) */
2530# define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
2531/** Outputs SVideo video (DAC B/C) */
2532# define TV_ENC_OUTPUT_SVIDEO (1 << 28)
2533/** Outputs Component video (DAC A/B/C) */
2534# define TV_ENC_OUTPUT_COMPONENT (2 << 28)
2535/** Outputs Composite and SVideo (DAC A/B/C) */
2536# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
2537# define TV_TRILEVEL_SYNC (1 << 21)
2538/** Enables slow sync generation (945GM only) */
2539# define TV_SLOW_SYNC (1 << 20)
2540/** Selects 4x oversampling for 480i and 576p */
2541# define TV_OVERSAMPLE_4X (0 << 18)
2542/** Selects 2x oversampling for 720p and 1080i */
2543# define TV_OVERSAMPLE_2X (1 << 18)
2544/** Selects no oversampling for 1080p */
2545# define TV_OVERSAMPLE_NONE (2 << 18)
2546/** Selects 8x oversampling */
2547# define TV_OVERSAMPLE_8X (3 << 18)
2548/** Selects progressive mode rather than interlaced */
2549# define TV_PROGRESSIVE (1 << 17)
2550/** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
2551# define TV_PAL_BURST (1 << 16)
2552/** Field for setting delay of Y compared to C */
2553# define TV_YC_SKEW_MASK (7 << 12)
2554/** Enables a fix for 480p/576p standard definition modes on the 915GM only */
2555# define TV_ENC_SDP_FIX (1 << 11)
2556/**
2557 * Enables a fix for the 915GM only.
2558 *
2559 * Not sure what it does.
2560 */
2561# define TV_ENC_C0_FIX (1 << 10)
2562/** Bits that must be preserved by software */
d2d9f232 2563# define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
585fb111
JB
2564# define TV_FUSE_STATE_MASK (3 << 4)
2565/** Read-only state that reports all features enabled */
2566# define TV_FUSE_STATE_ENABLED (0 << 4)
2567/** Read-only state that reports that Macrovision is disabled in hardware*/
2568# define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
2569/** Read-only state that reports that TV-out is disabled in hardware. */
2570# define TV_FUSE_STATE_DISABLED (2 << 4)
2571/** Normal operation */
2572# define TV_TEST_MODE_NORMAL (0 << 0)
2573/** Encoder test pattern 1 - combo pattern */
2574# define TV_TEST_MODE_PATTERN_1 (1 << 0)
2575/** Encoder test pattern 2 - full screen vertical 75% color bars */
2576# define TV_TEST_MODE_PATTERN_2 (2 << 0)
2577/** Encoder test pattern 3 - full screen horizontal 75% color bars */
2578# define TV_TEST_MODE_PATTERN_3 (3 << 0)
2579/** Encoder test pattern 4 - random noise */
2580# define TV_TEST_MODE_PATTERN_4 (4 << 0)
2581/** Encoder test pattern 5 - linear color ramps */
2582# define TV_TEST_MODE_PATTERN_5 (5 << 0)
2583/**
2584 * This test mode forces the DACs to 50% of full output.
2585 *
2586 * This is used for load detection in combination with TVDAC_SENSE_MASK
2587 */
2588# define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
2589# define TV_TEST_MODE_MASK (7 << 0)
2590
2591#define TV_DAC 0x68004
b8ed2a4f 2592# define TV_DAC_SAVE 0x00ffff00
585fb111
JB
2593/**
2594 * Reports that DAC state change logic has reported change (RO).
2595 *
2596 * This gets cleared when TV_DAC_STATE_EN is cleared
2597*/
2598# define TVDAC_STATE_CHG (1 << 31)
2599# define TVDAC_SENSE_MASK (7 << 28)
2600/** Reports that DAC A voltage is above the detect threshold */
2601# define TVDAC_A_SENSE (1 << 30)
2602/** Reports that DAC B voltage is above the detect threshold */
2603# define TVDAC_B_SENSE (1 << 29)
2604/** Reports that DAC C voltage is above the detect threshold */
2605# define TVDAC_C_SENSE (1 << 28)
2606/**
2607 * Enables DAC state detection logic, for load-based TV detection.
2608 *
2609 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
2610 * to off, for load detection to work.
2611 */
2612# define TVDAC_STATE_CHG_EN (1 << 27)
2613/** Sets the DAC A sense value to high */
2614# define TVDAC_A_SENSE_CTL (1 << 26)
2615/** Sets the DAC B sense value to high */
2616# define TVDAC_B_SENSE_CTL (1 << 25)
2617/** Sets the DAC C sense value to high */
2618# define TVDAC_C_SENSE_CTL (1 << 24)
2619/** Overrides the ENC_ENABLE and DAC voltage levels */
2620# define DAC_CTL_OVERRIDE (1 << 7)
2621/** Sets the slew rate. Must be preserved in software */
2622# define ENC_TVDAC_SLEW_FAST (1 << 6)
2623# define DAC_A_1_3_V (0 << 4)
2624# define DAC_A_1_1_V (1 << 4)
2625# define DAC_A_0_7_V (2 << 4)
cb66c692 2626# define DAC_A_MASK (3 << 4)
585fb111
JB
2627# define DAC_B_1_3_V (0 << 2)
2628# define DAC_B_1_1_V (1 << 2)
2629# define DAC_B_0_7_V (2 << 2)
cb66c692 2630# define DAC_B_MASK (3 << 2)
585fb111
JB
2631# define DAC_C_1_3_V (0 << 0)
2632# define DAC_C_1_1_V (1 << 0)
2633# define DAC_C_0_7_V (2 << 0)
cb66c692 2634# define DAC_C_MASK (3 << 0)
585fb111
JB
2635
2636/**
2637 * CSC coefficients are stored in a floating point format with 9 bits of
2638 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
2639 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
2640 * -1 (0x3) being the only legal negative value.
2641 */
2642#define TV_CSC_Y 0x68010
2643# define TV_RY_MASK 0x07ff0000
2644# define TV_RY_SHIFT 16
2645# define TV_GY_MASK 0x00000fff
2646# define TV_GY_SHIFT 0
2647
2648#define TV_CSC_Y2 0x68014
2649# define TV_BY_MASK 0x07ff0000
2650# define TV_BY_SHIFT 16
2651/**
2652 * Y attenuation for component video.
2653 *
2654 * Stored in 1.9 fixed point.
2655 */
2656# define TV_AY_MASK 0x000003ff
2657# define TV_AY_SHIFT 0
2658
2659#define TV_CSC_U 0x68018
2660# define TV_RU_MASK 0x07ff0000
2661# define TV_RU_SHIFT 16
2662# define TV_GU_MASK 0x000007ff
2663# define TV_GU_SHIFT 0
2664
2665#define TV_CSC_U2 0x6801c
2666# define TV_BU_MASK 0x07ff0000
2667# define TV_BU_SHIFT 16
2668/**
2669 * U attenuation for component video.
2670 *
2671 * Stored in 1.9 fixed point.
2672 */
2673# define TV_AU_MASK 0x000003ff
2674# define TV_AU_SHIFT 0
2675
2676#define TV_CSC_V 0x68020
2677# define TV_RV_MASK 0x0fff0000
2678# define TV_RV_SHIFT 16
2679# define TV_GV_MASK 0x000007ff
2680# define TV_GV_SHIFT 0
2681
2682#define TV_CSC_V2 0x68024
2683# define TV_BV_MASK 0x07ff0000
2684# define TV_BV_SHIFT 16
2685/**
2686 * V attenuation for component video.
2687 *
2688 * Stored in 1.9 fixed point.
2689 */
2690# define TV_AV_MASK 0x000007ff
2691# define TV_AV_SHIFT 0
2692
2693#define TV_CLR_KNOBS 0x68028
2694/** 2s-complement brightness adjustment */
2695# define TV_BRIGHTNESS_MASK 0xff000000
2696# define TV_BRIGHTNESS_SHIFT 24
2697/** Contrast adjustment, as a 2.6 unsigned floating point number */
2698# define TV_CONTRAST_MASK 0x00ff0000
2699# define TV_CONTRAST_SHIFT 16
2700/** Saturation adjustment, as a 2.6 unsigned floating point number */
2701# define TV_SATURATION_MASK 0x0000ff00
2702# define TV_SATURATION_SHIFT 8
2703/** Hue adjustment, as an integer phase angle in degrees */
2704# define TV_HUE_MASK 0x000000ff
2705# define TV_HUE_SHIFT 0
2706
2707#define TV_CLR_LEVEL 0x6802c
2708/** Controls the DAC level for black */
2709# define TV_BLACK_LEVEL_MASK 0x01ff0000
2710# define TV_BLACK_LEVEL_SHIFT 16
2711/** Controls the DAC level for blanking */
2712# define TV_BLANK_LEVEL_MASK 0x000001ff
2713# define TV_BLANK_LEVEL_SHIFT 0
2714
2715#define TV_H_CTL_1 0x68030
2716/** Number of pixels in the hsync. */
2717# define TV_HSYNC_END_MASK 0x1fff0000
2718# define TV_HSYNC_END_SHIFT 16
2719/** Total number of pixels minus one in the line (display and blanking). */
2720# define TV_HTOTAL_MASK 0x00001fff
2721# define TV_HTOTAL_SHIFT 0
2722
2723#define TV_H_CTL_2 0x68034
2724/** Enables the colorburst (needed for non-component color) */
2725# define TV_BURST_ENA (1 << 31)
2726/** Offset of the colorburst from the start of hsync, in pixels minus one. */
2727# define TV_HBURST_START_SHIFT 16
2728# define TV_HBURST_START_MASK 0x1fff0000
2729/** Length of the colorburst */
2730# define TV_HBURST_LEN_SHIFT 0
2731# define TV_HBURST_LEN_MASK 0x0001fff
2732
2733#define TV_H_CTL_3 0x68038
2734/** End of hblank, measured in pixels minus one from start of hsync */
2735# define TV_HBLANK_END_SHIFT 16
2736# define TV_HBLANK_END_MASK 0x1fff0000
2737/** Start of hblank, measured in pixels minus one from start of hsync */
2738# define TV_HBLANK_START_SHIFT 0
2739# define TV_HBLANK_START_MASK 0x0001fff
2740
2741#define TV_V_CTL_1 0x6803c
2742/** XXX */
2743# define TV_NBR_END_SHIFT 16
2744# define TV_NBR_END_MASK 0x07ff0000
2745/** XXX */
2746# define TV_VI_END_F1_SHIFT 8
2747# define TV_VI_END_F1_MASK 0x00003f00
2748/** XXX */
2749# define TV_VI_END_F2_SHIFT 0
2750# define TV_VI_END_F2_MASK 0x0000003f
2751
2752#define TV_V_CTL_2 0x68040
2753/** Length of vsync, in half lines */
2754# define TV_VSYNC_LEN_MASK 0x07ff0000
2755# define TV_VSYNC_LEN_SHIFT 16
2756/** Offset of the start of vsync in field 1, measured in one less than the
2757 * number of half lines.
2758 */
2759# define TV_VSYNC_START_F1_MASK 0x00007f00
2760# define TV_VSYNC_START_F1_SHIFT 8
2761/**
2762 * Offset of the start of vsync in field 2, measured in one less than the
2763 * number of half lines.
2764 */
2765# define TV_VSYNC_START_F2_MASK 0x0000007f
2766# define TV_VSYNC_START_F2_SHIFT 0
2767
2768#define TV_V_CTL_3 0x68044
2769/** Enables generation of the equalization signal */
2770# define TV_EQUAL_ENA (1 << 31)
2771/** Length of vsync, in half lines */
2772# define TV_VEQ_LEN_MASK 0x007f0000
2773# define TV_VEQ_LEN_SHIFT 16
2774/** Offset of the start of equalization in field 1, measured in one less than
2775 * the number of half lines.
2776 */
2777# define TV_VEQ_START_F1_MASK 0x0007f00
2778# define TV_VEQ_START_F1_SHIFT 8
2779/**
2780 * Offset of the start of equalization in field 2, measured in one less than
2781 * the number of half lines.
2782 */
2783# define TV_VEQ_START_F2_MASK 0x000007f
2784# define TV_VEQ_START_F2_SHIFT 0
2785
2786#define TV_V_CTL_4 0x68048
2787/**
2788 * Offset to start of vertical colorburst, measured in one less than the
2789 * number of lines from vertical start.
2790 */
2791# define TV_VBURST_START_F1_MASK 0x003f0000
2792# define TV_VBURST_START_F1_SHIFT 16
2793/**
2794 * Offset to the end of vertical colorburst, measured in one less than the
2795 * number of lines from the start of NBR.
2796 */
2797# define TV_VBURST_END_F1_MASK 0x000000ff
2798# define TV_VBURST_END_F1_SHIFT 0
2799
2800#define TV_V_CTL_5 0x6804c
2801/**
2802 * Offset to start of vertical colorburst, measured in one less than the
2803 * number of lines from vertical start.
2804 */
2805# define TV_VBURST_START_F2_MASK 0x003f0000
2806# define TV_VBURST_START_F2_SHIFT 16
2807/**
2808 * Offset to the end of vertical colorburst, measured in one less than the
2809 * number of lines from the start of NBR.
2810 */
2811# define TV_VBURST_END_F2_MASK 0x000000ff
2812# define TV_VBURST_END_F2_SHIFT 0
2813
2814#define TV_V_CTL_6 0x68050
2815/**
2816 * Offset to start of vertical colorburst, measured in one less than the
2817 * number of lines from vertical start.
2818 */
2819# define TV_VBURST_START_F3_MASK 0x003f0000
2820# define TV_VBURST_START_F3_SHIFT 16
2821/**
2822 * Offset to the end of vertical colorburst, measured in one less than the
2823 * number of lines from the start of NBR.
2824 */
2825# define TV_VBURST_END_F3_MASK 0x000000ff
2826# define TV_VBURST_END_F3_SHIFT 0
2827
2828#define TV_V_CTL_7 0x68054
2829/**
2830 * Offset to start of vertical colorburst, measured in one less than the
2831 * number of lines from vertical start.
2832 */
2833# define TV_VBURST_START_F4_MASK 0x003f0000
2834# define TV_VBURST_START_F4_SHIFT 16
2835/**
2836 * Offset to the end of vertical colorburst, measured in one less than the
2837 * number of lines from the start of NBR.
2838 */
2839# define TV_VBURST_END_F4_MASK 0x000000ff
2840# define TV_VBURST_END_F4_SHIFT 0
2841
2842#define TV_SC_CTL_1 0x68060
2843/** Turns on the first subcarrier phase generation DDA */
2844# define TV_SC_DDA1_EN (1 << 31)
2845/** Turns on the first subcarrier phase generation DDA */
2846# define TV_SC_DDA2_EN (1 << 30)
2847/** Turns on the first subcarrier phase generation DDA */
2848# define TV_SC_DDA3_EN (1 << 29)
2849/** Sets the subcarrier DDA to reset frequency every other field */
2850# define TV_SC_RESET_EVERY_2 (0 << 24)
2851/** Sets the subcarrier DDA to reset frequency every fourth field */
2852# define TV_SC_RESET_EVERY_4 (1 << 24)
2853/** Sets the subcarrier DDA to reset frequency every eighth field */
2854# define TV_SC_RESET_EVERY_8 (2 << 24)
2855/** Sets the subcarrier DDA to never reset the frequency */
2856# define TV_SC_RESET_NEVER (3 << 24)
2857/** Sets the peak amplitude of the colorburst.*/
2858# define TV_BURST_LEVEL_MASK 0x00ff0000
2859# define TV_BURST_LEVEL_SHIFT 16
2860/** Sets the increment of the first subcarrier phase generation DDA */
2861# define TV_SCDDA1_INC_MASK 0x00000fff
2862# define TV_SCDDA1_INC_SHIFT 0
2863
2864#define TV_SC_CTL_2 0x68064
2865/** Sets the rollover for the second subcarrier phase generation DDA */
2866# define TV_SCDDA2_SIZE_MASK 0x7fff0000
2867# define TV_SCDDA2_SIZE_SHIFT 16
2868/** Sets the increent of the second subcarrier phase generation DDA */
2869# define TV_SCDDA2_INC_MASK 0x00007fff
2870# define TV_SCDDA2_INC_SHIFT 0
2871
2872#define TV_SC_CTL_3 0x68068
2873/** Sets the rollover for the third subcarrier phase generation DDA */
2874# define TV_SCDDA3_SIZE_MASK 0x7fff0000
2875# define TV_SCDDA3_SIZE_SHIFT 16
2876/** Sets the increent of the third subcarrier phase generation DDA */
2877# define TV_SCDDA3_INC_MASK 0x00007fff
2878# define TV_SCDDA3_INC_SHIFT 0
2879
2880#define TV_WIN_POS 0x68070
2881/** X coordinate of the display from the start of horizontal active */
2882# define TV_XPOS_MASK 0x1fff0000
2883# define TV_XPOS_SHIFT 16
2884/** Y coordinate of the display from the start of vertical active (NBR) */
2885# define TV_YPOS_MASK 0x00000fff
2886# define TV_YPOS_SHIFT 0
2887
2888#define TV_WIN_SIZE 0x68074
2889/** Horizontal size of the display window, measured in pixels*/
2890# define TV_XSIZE_MASK 0x1fff0000
2891# define TV_XSIZE_SHIFT 16
2892/**
2893 * Vertical size of the display window, measured in pixels.
2894 *
2895 * Must be even for interlaced modes.
2896 */
2897# define TV_YSIZE_MASK 0x00000fff
2898# define TV_YSIZE_SHIFT 0
2899
2900#define TV_FILTER_CTL_1 0x68080
2901/**
2902 * Enables automatic scaling calculation.
2903 *
2904 * If set, the rest of the registers are ignored, and the calculated values can
2905 * be read back from the register.
2906 */
2907# define TV_AUTO_SCALE (1 << 31)
2908/**
2909 * Disables the vertical filter.
2910 *
2911 * This is required on modes more than 1024 pixels wide */
2912# define TV_V_FILTER_BYPASS (1 << 29)
2913/** Enables adaptive vertical filtering */
2914# define TV_VADAPT (1 << 28)
2915# define TV_VADAPT_MODE_MASK (3 << 26)
2916/** Selects the least adaptive vertical filtering mode */
2917# define TV_VADAPT_MODE_LEAST (0 << 26)
2918/** Selects the moderately adaptive vertical filtering mode */
2919# define TV_VADAPT_MODE_MODERATE (1 << 26)
2920/** Selects the most adaptive vertical filtering mode */
2921# define TV_VADAPT_MODE_MOST (3 << 26)
2922/**
2923 * Sets the horizontal scaling factor.
2924 *
2925 * This should be the fractional part of the horizontal scaling factor divided
2926 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
2927 *
2928 * (src width - 1) / ((oversample * dest width) - 1)
2929 */
2930# define TV_HSCALE_FRAC_MASK 0x00003fff
2931# define TV_HSCALE_FRAC_SHIFT 0
2932
2933#define TV_FILTER_CTL_2 0x68084
2934/**
2935 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2936 *
2937 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
2938 */
2939# define TV_VSCALE_INT_MASK 0x00038000
2940# define TV_VSCALE_INT_SHIFT 15
2941/**
2942 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2943 *
2944 * \sa TV_VSCALE_INT_MASK
2945 */
2946# define TV_VSCALE_FRAC_MASK 0x00007fff
2947# define TV_VSCALE_FRAC_SHIFT 0
2948
2949#define TV_FILTER_CTL_3 0x68088
2950/**
2951 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2952 *
2953 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
2954 *
2955 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2956 */
2957# define TV_VSCALE_IP_INT_MASK 0x00038000
2958# define TV_VSCALE_IP_INT_SHIFT 15
2959/**
2960 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2961 *
2962 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2963 *
2964 * \sa TV_VSCALE_IP_INT_MASK
2965 */
2966# define TV_VSCALE_IP_FRAC_MASK 0x00007fff
2967# define TV_VSCALE_IP_FRAC_SHIFT 0
2968
2969#define TV_CC_CONTROL 0x68090
2970# define TV_CC_ENABLE (1 << 31)
2971/**
2972 * Specifies which field to send the CC data in.
2973 *
2974 * CC data is usually sent in field 0.
2975 */
2976# define TV_CC_FID_MASK (1 << 27)
2977# define TV_CC_FID_SHIFT 27
2978/** Sets the horizontal position of the CC data. Usually 135. */
2979# define TV_CC_HOFF_MASK 0x03ff0000
2980# define TV_CC_HOFF_SHIFT 16
2981/** Sets the vertical position of the CC data. Usually 21 */
2982# define TV_CC_LINE_MASK 0x0000003f
2983# define TV_CC_LINE_SHIFT 0
2984
2985#define TV_CC_DATA 0x68094
2986# define TV_CC_RDY (1 << 31)
2987/** Second word of CC data to be transmitted. */
2988# define TV_CC_DATA_2_MASK 0x007f0000
2989# define TV_CC_DATA_2_SHIFT 16
2990/** First word of CC data to be transmitted. */
2991# define TV_CC_DATA_1_MASK 0x0000007f
2992# define TV_CC_DATA_1_SHIFT 0
2993
2994#define TV_H_LUMA_0 0x68100
2995#define TV_H_LUMA_59 0x681ec
2996#define TV_H_CHROMA_0 0x68200
2997#define TV_H_CHROMA_59 0x682ec
2998#define TV_V_LUMA_0 0x68300
2999#define TV_V_LUMA_42 0x683a8
3000#define TV_V_CHROMA_0 0x68400
3001#define TV_V_CHROMA_42 0x684a8
3002
040d87f1 3003/* Display Port */
32f9d658 3004#define DP_A 0x64000 /* eDP */
040d87f1
KP
3005#define DP_B 0x64100
3006#define DP_C 0x64200
3007#define DP_D 0x64300
3008
3009#define DP_PORT_EN (1 << 31)
3010#define DP_PIPEB_SELECT (1 << 30)
47a05eca
JB
3011#define DP_PIPE_MASK (1 << 30)
3012
040d87f1
KP
3013/* Link training mode - select a suitable mode for each stage */
3014#define DP_LINK_TRAIN_PAT_1 (0 << 28)
3015#define DP_LINK_TRAIN_PAT_2 (1 << 28)
3016#define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
3017#define DP_LINK_TRAIN_OFF (3 << 28)
3018#define DP_LINK_TRAIN_MASK (3 << 28)
3019#define DP_LINK_TRAIN_SHIFT 28
3020
8db9d77b
ZW
3021/* CPT Link training mode */
3022#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
3023#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
3024#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
3025#define DP_LINK_TRAIN_OFF_CPT (3 << 8)
3026#define DP_LINK_TRAIN_MASK_CPT (7 << 8)
3027#define DP_LINK_TRAIN_SHIFT_CPT 8
3028
040d87f1
KP
3029/* Signal voltages. These are mostly controlled by the other end */
3030#define DP_VOLTAGE_0_4 (0 << 25)
3031#define DP_VOLTAGE_0_6 (1 << 25)
3032#define DP_VOLTAGE_0_8 (2 << 25)
3033#define DP_VOLTAGE_1_2 (3 << 25)
3034#define DP_VOLTAGE_MASK (7 << 25)
3035#define DP_VOLTAGE_SHIFT 25
3036
3037/* Signal pre-emphasis levels, like voltages, the other end tells us what
3038 * they want
3039 */
3040#define DP_PRE_EMPHASIS_0 (0 << 22)
3041#define DP_PRE_EMPHASIS_3_5 (1 << 22)
3042#define DP_PRE_EMPHASIS_6 (2 << 22)
3043#define DP_PRE_EMPHASIS_9_5 (3 << 22)
3044#define DP_PRE_EMPHASIS_MASK (7 << 22)
3045#define DP_PRE_EMPHASIS_SHIFT 22
3046
3047/* How many wires to use. I guess 3 was too hard */
17aa6be9 3048#define DP_PORT_WIDTH(width) (((width) - 1) << 19)
040d87f1
KP
3049#define DP_PORT_WIDTH_MASK (7 << 19)
3050
3051/* Mystic DPCD version 1.1 special mode */
3052#define DP_ENHANCED_FRAMING (1 << 18)
3053
32f9d658
ZW
3054/* eDP */
3055#define DP_PLL_FREQ_270MHZ (0 << 16)
3056#define DP_PLL_FREQ_160MHZ (1 << 16)
3057#define DP_PLL_FREQ_MASK (3 << 16)
3058
040d87f1
KP
3059/** locked once port is enabled */
3060#define DP_PORT_REVERSAL (1 << 15)
3061
32f9d658
ZW
3062/* eDP */
3063#define DP_PLL_ENABLE (1 << 14)
3064
040d87f1
KP
3065/** sends the clock on lane 15 of the PEG for debug */
3066#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
3067
3068#define DP_SCRAMBLING_DISABLE (1 << 12)
f2b115e6 3069#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
040d87f1
KP
3070
3071/** limit RGB values to avoid confusing TVs */
3072#define DP_COLOR_RANGE_16_235 (1 << 8)
3073
3074/** Turn on the audio link */
3075#define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
3076
3077/** vs and hs sync polarity */
3078#define DP_SYNC_VS_HIGH (1 << 4)
3079#define DP_SYNC_HS_HIGH (1 << 3)
3080
3081/** A fantasy */
3082#define DP_DETECTED (1 << 2)
3083
3084/** The aux channel provides a way to talk to the
3085 * signal sink for DDC etc. Max packet size supported
3086 * is 20 bytes in each direction, hence the 5 fixed
3087 * data registers
3088 */
32f9d658
ZW
3089#define DPA_AUX_CH_CTL 0x64010
3090#define DPA_AUX_CH_DATA1 0x64014
3091#define DPA_AUX_CH_DATA2 0x64018
3092#define DPA_AUX_CH_DATA3 0x6401c
3093#define DPA_AUX_CH_DATA4 0x64020
3094#define DPA_AUX_CH_DATA5 0x64024
3095
040d87f1
KP
3096#define DPB_AUX_CH_CTL 0x64110
3097#define DPB_AUX_CH_DATA1 0x64114
3098#define DPB_AUX_CH_DATA2 0x64118
3099#define DPB_AUX_CH_DATA3 0x6411c
3100#define DPB_AUX_CH_DATA4 0x64120
3101#define DPB_AUX_CH_DATA5 0x64124
3102
3103#define DPC_AUX_CH_CTL 0x64210
3104#define DPC_AUX_CH_DATA1 0x64214
3105#define DPC_AUX_CH_DATA2 0x64218
3106#define DPC_AUX_CH_DATA3 0x6421c
3107#define DPC_AUX_CH_DATA4 0x64220
3108#define DPC_AUX_CH_DATA5 0x64224
3109
3110#define DPD_AUX_CH_CTL 0x64310
3111#define DPD_AUX_CH_DATA1 0x64314
3112#define DPD_AUX_CH_DATA2 0x64318
3113#define DPD_AUX_CH_DATA3 0x6431c
3114#define DPD_AUX_CH_DATA4 0x64320
3115#define DPD_AUX_CH_DATA5 0x64324
3116
3117#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
3118#define DP_AUX_CH_CTL_DONE (1 << 30)
3119#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
3120#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
3121#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
3122#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
3123#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
3124#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
3125#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
3126#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
3127#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
3128#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
3129#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
3130#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
3131#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
3132#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
3133#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
3134#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
3135#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
3136#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
3137#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
3138
3139/*
3140 * Computing GMCH M and N values for the Display Port link
3141 *
3142 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
3143 *
3144 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
3145 *
3146 * The GMCH value is used internally
3147 *
3148 * bytes_per_pixel is the number of bytes coming out of the plane,
3149 * which is after the LUTs, so we want the bytes for our color format.
3150 * For our current usage, this is always 3, one byte for R, G and B.
3151 */
e3b95f1e
DV
3152#define _PIPEA_DATA_M_G4X 0x70050
3153#define _PIPEB_DATA_M_G4X 0x71050
040d87f1
KP
3154
3155/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
a65851af 3156#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
72419203 3157#define TU_SIZE_SHIFT 25
a65851af 3158#define TU_SIZE_MASK (0x3f << 25)
040d87f1 3159
a65851af
VS
3160#define DATA_LINK_M_N_MASK (0xffffff)
3161#define DATA_LINK_N_MAX (0x800000)
040d87f1 3162
e3b95f1e
DV
3163#define _PIPEA_DATA_N_G4X 0x70054
3164#define _PIPEB_DATA_N_G4X 0x71054
040d87f1
KP
3165#define PIPE_GMCH_DATA_N_MASK (0xffffff)
3166
3167/*
3168 * Computing Link M and N values for the Display Port link
3169 *
3170 * Link M / N = pixel_clock / ls_clk
3171 *
3172 * (the DP spec calls pixel_clock the 'strm_clk')
3173 *
3174 * The Link value is transmitted in the Main Stream
3175 * Attributes and VB-ID.
3176 */
3177
e3b95f1e
DV
3178#define _PIPEA_LINK_M_G4X 0x70060
3179#define _PIPEB_LINK_M_G4X 0x71060
040d87f1
KP
3180#define PIPEA_DP_LINK_M_MASK (0xffffff)
3181
e3b95f1e
DV
3182#define _PIPEA_LINK_N_G4X 0x70064
3183#define _PIPEB_LINK_N_G4X 0x71064
040d87f1
KP
3184#define PIPEA_DP_LINK_N_MASK (0xffffff)
3185
e3b95f1e
DV
3186#define PIPE_DATA_M_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
3187#define PIPE_DATA_N_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
3188#define PIPE_LINK_M_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
3189#define PIPE_LINK_N_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
9db4a9c7 3190
585fb111
JB
3191/* Display & cursor control */
3192
3193/* Pipe A */
a57c774a 3194#define _PIPEADSL 0x70000
837ba00f
PZ
3195#define DSL_LINEMASK_GEN2 0x00000fff
3196#define DSL_LINEMASK_GEN3 0x00001fff
a57c774a 3197#define _PIPEACONF 0x70008
5eddb70b
CW
3198#define PIPECONF_ENABLE (1<<31)
3199#define PIPECONF_DISABLE 0
3200#define PIPECONF_DOUBLE_WIDE (1<<30)
585fb111 3201#define I965_PIPECONF_ACTIVE (1<<30)
b6ec10b3 3202#define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */
f47166d2 3203#define PIPECONF_FRAME_START_DELAY_MASK (3<<27)
5eddb70b
CW
3204#define PIPECONF_SINGLE_WIDE 0
3205#define PIPECONF_PIPE_UNLOCKED 0
3206#define PIPECONF_PIPE_LOCKED (1<<25)
3207#define PIPECONF_PALETTE 0
3208#define PIPECONF_GAMMA (1<<24)
585fb111 3209#define PIPECONF_FORCE_BORDER (1<<25)
59df7b17 3210#define PIPECONF_INTERLACE_MASK (7 << 21)
ee2b0b38 3211#define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
d442ae18
DV
3212/* Note that pre-gen3 does not support interlaced display directly. Panel
3213 * fitting must be disabled on pre-ilk for interlaced. */
3214#define PIPECONF_PROGRESSIVE (0 << 21)
3215#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
3216#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
3217#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
3218#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
3219/* Ironlake and later have a complete new set of values for interlaced. PFIT
3220 * means panel fitter required, PF means progressive fetch, DBL means power
3221 * saving pixel doubling. */
3222#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
3223#define PIPECONF_INTERLACED_ILK (3 << 21)
3224#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
3225#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
1bd1bd80 3226#define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
652c393a 3227#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
3685a8f3 3228#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
dfd07d72
DV
3229#define PIPECONF_BPC_MASK (0x7 << 5)
3230#define PIPECONF_8BPC (0<<5)
3231#define PIPECONF_10BPC (1<<5)
3232#define PIPECONF_6BPC (2<<5)
3233#define PIPECONF_12BPC (3<<5)
4f0d1aff
JB
3234#define PIPECONF_DITHER_EN (1<<4)
3235#define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
3236#define PIPECONF_DITHER_TYPE_SP (0<<2)
3237#define PIPECONF_DITHER_TYPE_ST1 (1<<2)
3238#define PIPECONF_DITHER_TYPE_ST2 (2<<2)
3239#define PIPECONF_DITHER_TYPE_TEMP (3<<2)
a57c774a 3240#define _PIPEASTAT 0x70024
585fb111 3241#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
579a9b0e 3242#define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL<<30)
585fb111
JB
3243#define PIPE_CRC_ERROR_ENABLE (1UL<<29)
3244#define PIPE_CRC_DONE_ENABLE (1UL<<28)
3245#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
c46ce4d7 3246#define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26)
585fb111
JB
3247#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
3248#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
3249#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
3250#define PIPE_DPST_EVENT_ENABLE (1UL<<23)
c70af1e4 3251#define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22)
585fb111
JB
3252#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
3253#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
3254#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
10c59c51 3255#define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL<<19)
585fb111
JB
3256#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
3257#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
3258#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
c46ce4d7 3259#define PIPEA_HBLANK_INT_EN_VLV (1UL<<16)
585fb111 3260#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
579a9b0e
ID
3261#define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL<<15)
3262#define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL<<14)
585fb111
JB
3263#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
3264#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
3265#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
579a9b0e 3266#define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL<<10)
585fb111
JB
3267#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
3268#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
3269#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
3270#define PIPE_DPST_EVENT_STATUS (1UL<<7)
3271#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
10c59c51 3272#define PIPE_A_PSR_STATUS_VLV (1UL<<6)
585fb111
JB
3273#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
3274#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
10c59c51 3275#define PIPE_B_PSR_STATUS_VLV (1UL<<3)
585fb111
JB
3276#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
3277#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
3278#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
3279#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
3280
755e9019
ID
3281#define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
3282#define PIPESTAT_INT_STATUS_MASK 0x0000ffff
3283
a57c774a
AK
3284#define PIPE_A_OFFSET 0x70000
3285#define PIPE_B_OFFSET 0x71000
3286#define PIPE_C_OFFSET 0x72000
3287/*
3288 * There's actually no pipe EDP. Some pipe registers have
3289 * simply shifted from the pipe to the transcoder, while
3290 * keeping their original offset. Thus we need PIPE_EDP_OFFSET
3291 * to access such registers in transcoder EDP.
3292 */
3293#define PIPE_EDP_OFFSET 0x7f000
3294
5c969aa7
DL
3295#define _PIPE2(pipe, reg) (dev_priv->info.pipe_offsets[pipe] - \
3296 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
3297 dev_priv->info.display_mmio_offset)
a57c774a
AK
3298
3299#define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF)
3300#define PIPEDSL(pipe) _PIPE2(pipe, _PIPEADSL)
3301#define PIPEFRAME(pipe) _PIPE2(pipe, _PIPEAFRAMEHIGH)
3302#define PIPEFRAMEPIXEL(pipe) _PIPE2(pipe, _PIPEAFRAMEPIXEL)
3303#define PIPESTAT(pipe) _PIPE2(pipe, _PIPEASTAT)
5eddb70b 3304
756f85cf
PZ
3305#define _PIPE_MISC_A 0x70030
3306#define _PIPE_MISC_B 0x71030
3307#define PIPEMISC_DITHER_BPC_MASK (7<<5)
3308#define PIPEMISC_DITHER_8_BPC (0<<5)
3309#define PIPEMISC_DITHER_10_BPC (1<<5)
3310#define PIPEMISC_DITHER_6_BPC (2<<5)
3311#define PIPEMISC_DITHER_12_BPC (3<<5)
3312#define PIPEMISC_DITHER_ENABLE (1<<4)
3313#define PIPEMISC_DITHER_TYPE_MASK (3<<2)
3314#define PIPEMISC_DITHER_TYPE_SP (0<<2)
a57c774a 3315#define PIPEMISC(pipe) _PIPE2(pipe, _PIPE_MISC_A)
756f85cf 3316
b41fbda1 3317#define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028)
7983117f 3318#define PIPEB_LINE_COMPARE_INT_EN (1<<29)
c46ce4d7
JB
3319#define PIPEB_HLINE_INT_EN (1<<28)
3320#define PIPEB_VBLANK_INT_EN (1<<27)
579a9b0e
ID
3321#define SPRITED_FLIP_DONE_INT_EN (1<<26)
3322#define SPRITEC_FLIP_DONE_INT_EN (1<<25)
3323#define PLANEB_FLIP_DONE_INT_EN (1<<24)
7983117f 3324#define PIPEA_LINE_COMPARE_INT_EN (1<<21)
c46ce4d7
JB
3325#define PIPEA_HLINE_INT_EN (1<<20)
3326#define PIPEA_VBLANK_INT_EN (1<<19)
579a9b0e
ID
3327#define SPRITEB_FLIP_DONE_INT_EN (1<<18)
3328#define SPRITEA_FLIP_DONE_INT_EN (1<<17)
c46ce4d7
JB
3329#define PLANEA_FLIPDONE_INT_EN (1<<16)
3330
b41fbda1 3331#define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV only */
c46ce4d7
JB
3332#define CURSORB_INVALID_GTT_INT_EN (1<<23)
3333#define CURSORA_INVALID_GTT_INT_EN (1<<22)
3334#define SPRITED_INVALID_GTT_INT_EN (1<<21)
3335#define SPRITEC_INVALID_GTT_INT_EN (1<<20)
3336#define PLANEB_INVALID_GTT_INT_EN (1<<19)
3337#define SPRITEB_INVALID_GTT_INT_EN (1<<18)
3338#define SPRITEA_INVALID_GTT_INT_EN (1<<17)
3339#define PLANEA_INVALID_GTT_INT_EN (1<<16)
3340#define DPINVGTT_EN_MASK 0xff0000
3341#define CURSORB_INVALID_GTT_STATUS (1<<7)
3342#define CURSORA_INVALID_GTT_STATUS (1<<6)
3343#define SPRITED_INVALID_GTT_STATUS (1<<5)
3344#define SPRITEC_INVALID_GTT_STATUS (1<<4)
3345#define PLANEB_INVALID_GTT_STATUS (1<<3)
3346#define SPRITEB_INVALID_GTT_STATUS (1<<2)
3347#define SPRITEA_INVALID_GTT_STATUS (1<<1)
3348#define PLANEA_INVALID_GTT_STATUS (1<<0)
3349#define DPINVGTT_STATUS_MASK 0xff
3350
585fb111
JB
3351#define DSPARB 0x70030
3352#define DSPARB_CSTART_MASK (0x7f << 7)
3353#define DSPARB_CSTART_SHIFT 7
3354#define DSPARB_BSTART_MASK (0x7f)
3355#define DSPARB_BSTART_SHIFT 0
7662c8bd
SL
3356#define DSPARB_BEND_SHIFT 9 /* on 855 */
3357#define DSPARB_AEND_SHIFT 0
3358
5c969aa7 3359#define DSPFW1 (dev_priv->info.display_mmio_offset + 0x70034)
0e442c60 3360#define DSPFW_SR_SHIFT 23
0206e353 3361#define DSPFW_SR_MASK (0x1ff<<23)
0e442c60 3362#define DSPFW_CURSORB_SHIFT 16
d4294342 3363#define DSPFW_CURSORB_MASK (0x3f<<16)
0e442c60 3364#define DSPFW_PLANEB_SHIFT 8
d4294342
ZY
3365#define DSPFW_PLANEB_MASK (0x7f<<8)
3366#define DSPFW_PLANEA_MASK (0x7f)
5c969aa7 3367#define DSPFW2 (dev_priv->info.display_mmio_offset + 0x70038)
0e442c60 3368#define DSPFW_CURSORA_MASK 0x00003f00
21bd770b 3369#define DSPFW_CURSORA_SHIFT 8
d4294342 3370#define DSPFW_PLANEC_MASK (0x7f)
5c969aa7 3371#define DSPFW3 (dev_priv->info.display_mmio_offset + 0x7003c)
0e442c60
JB
3372#define DSPFW_HPLL_SR_EN (1<<31)
3373#define DSPFW_CURSOR_SR_SHIFT 24
f2b115e6 3374#define PINEVIEW_SELF_REFRESH_EN (1<<30)
d4294342
ZY
3375#define DSPFW_CURSOR_SR_MASK (0x3f<<24)
3376#define DSPFW_HPLL_CURSOR_SHIFT 16
3377#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
3378#define DSPFW_HPLL_SR_MASK (0x1ff)
5c969aa7
DL
3379#define DSPFW4 (dev_priv->info.display_mmio_offset + 0x70070)
3380#define DSPFW7 (dev_priv->info.display_mmio_offset + 0x7007c)
7662c8bd 3381
12a3c055
GB
3382/* drain latency register values*/
3383#define DRAIN_LATENCY_PRECISION_32 32
3384#define DRAIN_LATENCY_PRECISION_16 16
8f6d8ee9 3385#define VLV_DDL1 (VLV_DISPLAY_BASE + 0x70050)
12a3c055
GB
3386#define DDL_CURSORA_PRECISION_32 (1<<31)
3387#define DDL_CURSORA_PRECISION_16 (0<<31)
3388#define DDL_CURSORA_SHIFT 24
3389#define DDL_PLANEA_PRECISION_32 (1<<7)
3390#define DDL_PLANEA_PRECISION_16 (0<<7)
8f6d8ee9 3391#define VLV_DDL2 (VLV_DISPLAY_BASE + 0x70054)
12a3c055
GB
3392#define DDL_CURSORB_PRECISION_32 (1<<31)
3393#define DDL_CURSORB_PRECISION_16 (0<<31)
3394#define DDL_CURSORB_SHIFT 24
3395#define DDL_PLANEB_PRECISION_32 (1<<7)
3396#define DDL_PLANEB_PRECISION_16 (0<<7)
3397
7662c8bd 3398/* FIFO watermark sizes etc */
0e442c60 3399#define G4X_FIFO_LINE_SIZE 64
7662c8bd
SL
3400#define I915_FIFO_LINE_SIZE 64
3401#define I830_FIFO_LINE_SIZE 32
0e442c60 3402
ceb04246 3403#define VALLEYVIEW_FIFO_SIZE 255
0e442c60 3404#define G4X_FIFO_SIZE 127
1b07e04e
ZY
3405#define I965_FIFO_SIZE 512
3406#define I945_FIFO_SIZE 127
7662c8bd 3407#define I915_FIFO_SIZE 95
dff33cfc 3408#define I855GM_FIFO_SIZE 127 /* In cachelines */
7662c8bd 3409#define I830_FIFO_SIZE 95
0e442c60 3410
ceb04246 3411#define VALLEYVIEW_MAX_WM 0xff
0e442c60 3412#define G4X_MAX_WM 0x3f
7662c8bd
SL
3413#define I915_MAX_WM 0x3f
3414
f2b115e6
AJ
3415#define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
3416#define PINEVIEW_FIFO_LINE_SIZE 64
3417#define PINEVIEW_MAX_WM 0x1ff
3418#define PINEVIEW_DFT_WM 0x3f
3419#define PINEVIEW_DFT_HPLLOFF_WM 0
3420#define PINEVIEW_GUARD_WM 10
3421#define PINEVIEW_CURSOR_FIFO 64
3422#define PINEVIEW_CURSOR_MAX_WM 0x3f
3423#define PINEVIEW_CURSOR_DFT_WM 0
3424#define PINEVIEW_CURSOR_GUARD_WM 5
7662c8bd 3425
ceb04246 3426#define VALLEYVIEW_CURSOR_MAX_WM 64
4fe5e611
ZY
3427#define I965_CURSOR_FIFO 64
3428#define I965_CURSOR_MAX_WM 32
3429#define I965_CURSOR_DFT_WM 8
7f8a8569
ZW
3430
3431/* define the Watermark register on Ironlake */
3432#define WM0_PIPEA_ILK 0x45100
1996d624 3433#define WM0_PIPE_PLANE_MASK (0xffff<<16)
7f8a8569 3434#define WM0_PIPE_PLANE_SHIFT 16
1996d624 3435#define WM0_PIPE_SPRITE_MASK (0xff<<8)
7f8a8569 3436#define WM0_PIPE_SPRITE_SHIFT 8
1996d624 3437#define WM0_PIPE_CURSOR_MASK (0xff)
7f8a8569
ZW
3438
3439#define WM0_PIPEB_ILK 0x45104
d6c892df 3440#define WM0_PIPEC_IVB 0x45200
7f8a8569
ZW
3441#define WM1_LP_ILK 0x45108
3442#define WM1_LP_SR_EN (1<<31)
3443#define WM1_LP_LATENCY_SHIFT 24
3444#define WM1_LP_LATENCY_MASK (0x7f<<24)
4ed765f9
CW
3445#define WM1_LP_FBC_MASK (0xf<<20)
3446#define WM1_LP_FBC_SHIFT 20
416f4727 3447#define WM1_LP_FBC_SHIFT_BDW 19
1996d624 3448#define WM1_LP_SR_MASK (0x7ff<<8)
7f8a8569 3449#define WM1_LP_SR_SHIFT 8
1996d624 3450#define WM1_LP_CURSOR_MASK (0xff)
dd8849c8
JB
3451#define WM2_LP_ILK 0x4510c
3452#define WM2_LP_EN (1<<31)
3453#define WM3_LP_ILK 0x45110
3454#define WM3_LP_EN (1<<31)
3455#define WM1S_LP_ILK 0x45120
b840d907
JB
3456#define WM2S_LP_IVB 0x45124
3457#define WM3S_LP_IVB 0x45128
dd8849c8 3458#define WM1S_LP_EN (1<<31)
7f8a8569 3459
cca32e9a
PZ
3460#define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
3461 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
3462 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
3463
7f8a8569
ZW
3464/* Memory latency timer register */
3465#define MLTR_ILK 0x11222
b79d4990
JB
3466#define MLTR_WM1_SHIFT 0
3467#define MLTR_WM2_SHIFT 8
7f8a8569
ZW
3468/* the unit of memory self-refresh latency time is 0.5us */
3469#define ILK_SRLT_MASK 0x3f
3470
1398261a
YL
3471
3472/* the address where we get all kinds of latency value */
3473#define SSKPD 0x5d10
3474#define SSKPD_WM_MASK 0x3f
3475#define SSKPD_WM0_SHIFT 0
3476#define SSKPD_WM1_SHIFT 8
3477#define SSKPD_WM2_SHIFT 16
3478#define SSKPD_WM3_SHIFT 24
3479
585fb111
JB
3480/*
3481 * The two pipe frame counter registers are not synchronized, so
3482 * reading a stable value is somewhat tricky. The following code
3483 * should work:
3484 *
3485 * do {
3486 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
3487 * PIPE_FRAME_HIGH_SHIFT;
3488 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
3489 * PIPE_FRAME_LOW_SHIFT);
3490 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
3491 * PIPE_FRAME_HIGH_SHIFT);
3492 * } while (high1 != high2);
3493 * frame = (high1 << 8) | low1;
3494 */
25a2e2d0 3495#define _PIPEAFRAMEHIGH 0x70040
585fb111
JB
3496#define PIPE_FRAME_HIGH_MASK 0x0000ffff
3497#define PIPE_FRAME_HIGH_SHIFT 0
25a2e2d0 3498#define _PIPEAFRAMEPIXEL 0x70044
585fb111
JB
3499#define PIPE_FRAME_LOW_MASK 0xff000000
3500#define PIPE_FRAME_LOW_SHIFT 24
3501#define PIPE_PIXEL_MASK 0x00ffffff
3502#define PIPE_PIXEL_SHIFT 0
9880b7a5 3503/* GM45+ just has to be different */
5c969aa7
DL
3504#define _PIPEA_FRMCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x70040)
3505#define _PIPEA_FLIPCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x70044)
9db4a9c7 3506#define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
585fb111
JB
3507
3508/* Cursor A & B regs */
5c969aa7 3509#define _CURACNTR (dev_priv->info.display_mmio_offset + 0x70080)
14b60391
JB
3510/* Old style CUR*CNTR flags (desktop 8xx) */
3511#define CURSOR_ENABLE 0x80000000
3512#define CURSOR_GAMMA_ENABLE 0x40000000
3513#define CURSOR_STRIDE_MASK 0x30000000
86d3efce 3514#define CURSOR_PIPE_CSC_ENABLE (1<<24)
14b60391
JB
3515#define CURSOR_FORMAT_SHIFT 24
3516#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
3517#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
3518#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
3519#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
3520#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
3521#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
3522/* New style CUR*CNTR flags */
3523#define CURSOR_MODE 0x27
585fb111
JB
3524#define CURSOR_MODE_DISABLE 0x00
3525#define CURSOR_MODE_64_32B_AX 0x07
3526#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
14b60391
JB
3527#define MCURSOR_PIPE_SELECT (1 << 28)
3528#define MCURSOR_PIPE_A 0x00
3529#define MCURSOR_PIPE_B (1 << 28)
585fb111 3530#define MCURSOR_GAMMA_ENABLE (1 << 26)
1f5d76db 3531#define CURSOR_TRICKLE_FEED_DISABLE (1 << 14)
5c969aa7
DL
3532#define _CURABASE (dev_priv->info.display_mmio_offset + 0x70084)
3533#define _CURAPOS (dev_priv->info.display_mmio_offset + 0x70088)
585fb111
JB
3534#define CURSOR_POS_MASK 0x007FF
3535#define CURSOR_POS_SIGN 0x8000
3536#define CURSOR_X_SHIFT 0
3537#define CURSOR_Y_SHIFT 16
14b60391 3538#define CURSIZE 0x700a0
5c969aa7
DL
3539#define _CURBCNTR (dev_priv->info.display_mmio_offset + 0x700c0)
3540#define _CURBBASE (dev_priv->info.display_mmio_offset + 0x700c4)
3541#define _CURBPOS (dev_priv->info.display_mmio_offset + 0x700c8)
585fb111 3542
65a21cd6
JB
3543#define _CURBCNTR_IVB 0x71080
3544#define _CURBBASE_IVB 0x71084
3545#define _CURBPOS_IVB 0x71088
3546
9db4a9c7
JB
3547#define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR)
3548#define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE)
3549#define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS)
c4a1d9e4 3550
65a21cd6
JB
3551#define CURCNTR_IVB(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR_IVB)
3552#define CURBASE_IVB(pipe) _PIPE(pipe, _CURABASE, _CURBBASE_IVB)
3553#define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB)
3554
585fb111 3555/* Display A control */
a57c774a 3556#define _DSPACNTR 0x70180
585fb111
JB
3557#define DISPLAY_PLANE_ENABLE (1<<31)
3558#define DISPLAY_PLANE_DISABLE 0
3559#define DISPPLANE_GAMMA_ENABLE (1<<30)
3560#define DISPPLANE_GAMMA_DISABLE 0
3561#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
57779d06 3562#define DISPPLANE_YUV422 (0x0<<26)
585fb111 3563#define DISPPLANE_8BPP (0x2<<26)
57779d06
VS
3564#define DISPPLANE_BGRA555 (0x3<<26)
3565#define DISPPLANE_BGRX555 (0x4<<26)
3566#define DISPPLANE_BGRX565 (0x5<<26)
3567#define DISPPLANE_BGRX888 (0x6<<26)
3568#define DISPPLANE_BGRA888 (0x7<<26)
3569#define DISPPLANE_RGBX101010 (0x8<<26)
3570#define DISPPLANE_RGBA101010 (0x9<<26)
3571#define DISPPLANE_BGRX101010 (0xa<<26)
3572#define DISPPLANE_RGBX161616 (0xc<<26)
3573#define DISPPLANE_RGBX888 (0xe<<26)
3574#define DISPPLANE_RGBA888 (0xf<<26)
585fb111
JB
3575#define DISPPLANE_STEREO_ENABLE (1<<25)
3576#define DISPPLANE_STEREO_DISABLE 0
86d3efce 3577#define DISPPLANE_PIPE_CSC_ENABLE (1<<24)
b24e7179
JB
3578#define DISPPLANE_SEL_PIPE_SHIFT 24
3579#define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
585fb111 3580#define DISPPLANE_SEL_PIPE_A 0
b24e7179 3581#define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT)
585fb111
JB
3582#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
3583#define DISPPLANE_SRC_KEY_DISABLE 0
3584#define DISPPLANE_LINE_DOUBLE (1<<20)
3585#define DISPPLANE_NO_LINE_DOUBLE 0
3586#define DISPPLANE_STEREO_POLARITY_FIRST 0
3587#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
f2b115e6 3588#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
f544847f 3589#define DISPPLANE_TILED (1<<10)
a57c774a
AK
3590#define _DSPAADDR 0x70184
3591#define _DSPASTRIDE 0x70188
3592#define _DSPAPOS 0x7018C /* reserved */
3593#define _DSPASIZE 0x70190
3594#define _DSPASURF 0x7019C /* 965+ only */
3595#define _DSPATILEOFF 0x701A4 /* 965+ only */
3596#define _DSPAOFFSET 0x701A4 /* HSW */
3597#define _DSPASURFLIVE 0x701AC
3598
3599#define DSPCNTR(plane) _PIPE2(plane, _DSPACNTR)
3600#define DSPADDR(plane) _PIPE2(plane, _DSPAADDR)
3601#define DSPSTRIDE(plane) _PIPE2(plane, _DSPASTRIDE)
3602#define DSPPOS(plane) _PIPE2(plane, _DSPAPOS)
3603#define DSPSIZE(plane) _PIPE2(plane, _DSPASIZE)
3604#define DSPSURF(plane) _PIPE2(plane, _DSPASURF)
3605#define DSPTILEOFF(plane) _PIPE2(plane, _DSPATILEOFF)
e506a0c6 3606#define DSPLINOFF(plane) DSPADDR(plane)
a57c774a
AK
3607#define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET)
3608#define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE)
5eddb70b 3609
446f2545
AR
3610/* Display/Sprite base address macros */
3611#define DISP_BASEADDR_MASK (0xfffff000)
3612#define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK)
3613#define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK)
446f2545 3614
585fb111 3615/* VBIOS flags */
5c969aa7
DL
3616#define SWF00 (dev_priv->info.display_mmio_offset + 0x71410)
3617#define SWF01 (dev_priv->info.display_mmio_offset + 0x71414)
3618#define SWF02 (dev_priv->info.display_mmio_offset + 0x71418)
3619#define SWF03 (dev_priv->info.display_mmio_offset + 0x7141c)
3620#define SWF04 (dev_priv->info.display_mmio_offset + 0x71420)
3621#define SWF05 (dev_priv->info.display_mmio_offset + 0x71424)
3622#define SWF06 (dev_priv->info.display_mmio_offset + 0x71428)
3623#define SWF10 (dev_priv->info.display_mmio_offset + 0x70410)
3624#define SWF11 (dev_priv->info.display_mmio_offset + 0x70414)
3625#define SWF14 (dev_priv->info.display_mmio_offset + 0x71420)
3626#define SWF30 (dev_priv->info.display_mmio_offset + 0x72414)
3627#define SWF31 (dev_priv->info.display_mmio_offset + 0x72418)
3628#define SWF32 (dev_priv->info.display_mmio_offset + 0x7241c)
585fb111
JB
3629
3630/* Pipe B */
5c969aa7
DL
3631#define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)
3632#define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008)
3633#define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024)
25a2e2d0
VS
3634#define _PIPEBFRAMEHIGH 0x71040
3635#define _PIPEBFRAMEPIXEL 0x71044
5c969aa7
DL
3636#define _PIPEB_FRMCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71040)
3637#define _PIPEB_FLIPCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71044)
9880b7a5 3638
585fb111
JB
3639
3640/* Display B control */
5c969aa7 3641#define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180)
585fb111
JB
3642#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
3643#define DISPPLANE_ALPHA_TRANS_DISABLE 0
3644#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
3645#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
5c969aa7
DL
3646#define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184)
3647#define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188)
3648#define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C)
3649#define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190)
3650#define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C)
3651#define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4)
3652#define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4)
3653#define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC)
585fb111 3654
b840d907
JB
3655/* Sprite A control */
3656#define _DVSACNTR 0x72180
3657#define DVS_ENABLE (1<<31)
3658#define DVS_GAMMA_ENABLE (1<<30)
3659#define DVS_PIXFORMAT_MASK (3<<25)
3660#define DVS_FORMAT_YUV422 (0<<25)
3661#define DVS_FORMAT_RGBX101010 (1<<25)
3662#define DVS_FORMAT_RGBX888 (2<<25)
3663#define DVS_FORMAT_RGBX161616 (3<<25)
86d3efce 3664#define DVS_PIPE_CSC_ENABLE (1<<24)
b840d907 3665#define DVS_SOURCE_KEY (1<<22)
ab2f9df1 3666#define DVS_RGB_ORDER_XBGR (1<<20)
b840d907
JB
3667#define DVS_YUV_BYTE_ORDER_MASK (3<<16)
3668#define DVS_YUV_ORDER_YUYV (0<<16)
3669#define DVS_YUV_ORDER_UYVY (1<<16)
3670#define DVS_YUV_ORDER_YVYU (2<<16)
3671#define DVS_YUV_ORDER_VYUY (3<<16)
3672#define DVS_DEST_KEY (1<<2)
3673#define DVS_TRICKLE_FEED_DISABLE (1<<14)
3674#define DVS_TILED (1<<10)
3675#define _DVSALINOFF 0x72184
3676#define _DVSASTRIDE 0x72188
3677#define _DVSAPOS 0x7218c
3678#define _DVSASIZE 0x72190
3679#define _DVSAKEYVAL 0x72194
3680#define _DVSAKEYMSK 0x72198
3681#define _DVSASURF 0x7219c
3682#define _DVSAKEYMAXVAL 0x721a0
3683#define _DVSATILEOFF 0x721a4
3684#define _DVSASURFLIVE 0x721ac
3685#define _DVSASCALE 0x72204
3686#define DVS_SCALE_ENABLE (1<<31)
3687#define DVS_FILTER_MASK (3<<29)
3688#define DVS_FILTER_MEDIUM (0<<29)
3689#define DVS_FILTER_ENHANCING (1<<29)
3690#define DVS_FILTER_SOFTENING (2<<29)
3691#define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
3692#define DVS_VERTICAL_OFFSET_ENABLE (1<<27)
3693#define _DVSAGAMC 0x72300
3694
3695#define _DVSBCNTR 0x73180
3696#define _DVSBLINOFF 0x73184
3697#define _DVSBSTRIDE 0x73188
3698#define _DVSBPOS 0x7318c
3699#define _DVSBSIZE 0x73190
3700#define _DVSBKEYVAL 0x73194
3701#define _DVSBKEYMSK 0x73198
3702#define _DVSBSURF 0x7319c
3703#define _DVSBKEYMAXVAL 0x731a0
3704#define _DVSBTILEOFF 0x731a4
3705#define _DVSBSURFLIVE 0x731ac
3706#define _DVSBSCALE 0x73204
3707#define _DVSBGAMC 0x73300
3708
3709#define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)
3710#define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
3711#define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
3712#define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)
3713#define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)
8ea30864 3714#define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
b840d907
JB
3715#define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
3716#define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
3717#define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
8ea30864
JB
3718#define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
3719#define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
32ae46bf 3720#define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
b840d907
JB
3721
3722#define _SPRA_CTL 0x70280
3723#define SPRITE_ENABLE (1<<31)
3724#define SPRITE_GAMMA_ENABLE (1<<30)
3725#define SPRITE_PIXFORMAT_MASK (7<<25)
3726#define SPRITE_FORMAT_YUV422 (0<<25)
3727#define SPRITE_FORMAT_RGBX101010 (1<<25)
3728#define SPRITE_FORMAT_RGBX888 (2<<25)
3729#define SPRITE_FORMAT_RGBX161616 (3<<25)
3730#define SPRITE_FORMAT_YUV444 (4<<25)
3731#define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */
86d3efce 3732#define SPRITE_PIPE_CSC_ENABLE (1<<24)
b840d907
JB
3733#define SPRITE_SOURCE_KEY (1<<22)
3734#define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */
3735#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19)
3736#define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */
3737#define SPRITE_YUV_BYTE_ORDER_MASK (3<<16)
3738#define SPRITE_YUV_ORDER_YUYV (0<<16)
3739#define SPRITE_YUV_ORDER_UYVY (1<<16)
3740#define SPRITE_YUV_ORDER_YVYU (2<<16)
3741#define SPRITE_YUV_ORDER_VYUY (3<<16)
3742#define SPRITE_TRICKLE_FEED_DISABLE (1<<14)
3743#define SPRITE_INT_GAMMA_ENABLE (1<<13)
3744#define SPRITE_TILED (1<<10)
3745#define SPRITE_DEST_KEY (1<<2)
3746#define _SPRA_LINOFF 0x70284
3747#define _SPRA_STRIDE 0x70288
3748#define _SPRA_POS 0x7028c
3749#define _SPRA_SIZE 0x70290
3750#define _SPRA_KEYVAL 0x70294
3751#define _SPRA_KEYMSK 0x70298
3752#define _SPRA_SURF 0x7029c
3753#define _SPRA_KEYMAX 0x702a0
3754#define _SPRA_TILEOFF 0x702a4
c54173a8 3755#define _SPRA_OFFSET 0x702a4
32ae46bf 3756#define _SPRA_SURFLIVE 0x702ac
b840d907
JB
3757#define _SPRA_SCALE 0x70304
3758#define SPRITE_SCALE_ENABLE (1<<31)
3759#define SPRITE_FILTER_MASK (3<<29)
3760#define SPRITE_FILTER_MEDIUM (0<<29)
3761#define SPRITE_FILTER_ENHANCING (1<<29)
3762#define SPRITE_FILTER_SOFTENING (2<<29)
3763#define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
3764#define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27)
3765#define _SPRA_GAMC 0x70400
3766
3767#define _SPRB_CTL 0x71280
3768#define _SPRB_LINOFF 0x71284
3769#define _SPRB_STRIDE 0x71288
3770#define _SPRB_POS 0x7128c
3771#define _SPRB_SIZE 0x71290
3772#define _SPRB_KEYVAL 0x71294
3773#define _SPRB_KEYMSK 0x71298
3774#define _SPRB_SURF 0x7129c
3775#define _SPRB_KEYMAX 0x712a0
3776#define _SPRB_TILEOFF 0x712a4
c54173a8 3777#define _SPRB_OFFSET 0x712a4
32ae46bf 3778#define _SPRB_SURFLIVE 0x712ac
b840d907
JB
3779#define _SPRB_SCALE 0x71304
3780#define _SPRB_GAMC 0x71400
3781
3782#define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
3783#define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
3784#define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
3785#define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS)
3786#define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
3787#define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
3788#define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
3789#define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
3790#define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
3791#define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
c54173a8 3792#define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
b840d907
JB
3793#define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
3794#define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
32ae46bf 3795#define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
b840d907 3796
921c3b67 3797#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
7f1f3851 3798#define SP_ENABLE (1<<31)
4ea67bc7 3799#define SP_GAMMA_ENABLE (1<<30)
7f1f3851
JB
3800#define SP_PIXFORMAT_MASK (0xf<<26)
3801#define SP_FORMAT_YUV422 (0<<26)
3802#define SP_FORMAT_BGR565 (5<<26)
3803#define SP_FORMAT_BGRX8888 (6<<26)
3804#define SP_FORMAT_BGRA8888 (7<<26)
3805#define SP_FORMAT_RGBX1010102 (8<<26)
3806#define SP_FORMAT_RGBA1010102 (9<<26)
3807#define SP_FORMAT_RGBX8888 (0xe<<26)
3808#define SP_FORMAT_RGBA8888 (0xf<<26)
3809#define SP_SOURCE_KEY (1<<22)
3810#define SP_YUV_BYTE_ORDER_MASK (3<<16)
3811#define SP_YUV_ORDER_YUYV (0<<16)
3812#define SP_YUV_ORDER_UYVY (1<<16)
3813#define SP_YUV_ORDER_YVYU (2<<16)
3814#define SP_YUV_ORDER_VYUY (3<<16)
3815#define SP_TILED (1<<10)
921c3b67
VS
3816#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
3817#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
3818#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
3819#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
3820#define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
3821#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
3822#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
3823#define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
3824#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
3825#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
3826#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4)
3827
3828#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
3829#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
3830#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
3831#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
3832#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
3833#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
3834#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
3835#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
3836#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
3837#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
3838#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
3839#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4)
7f1f3851
JB
3840
3841#define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
3842#define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
3843#define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
3844#define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
3845#define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
3846#define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL)
3847#define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK)
3848#define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF)
3849#define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL)
3850#define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF)
3851#define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA)
3852#define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC)
3853
585fb111
JB
3854/* VBIOS regs */
3855#define VGACNTRL 0x71400
3856# define VGA_DISP_DISABLE (1 << 31)
3857# define VGA_2X_MODE (1 << 30)
3858# define VGA_PIPE_B_SELECT (1 << 29)
3859
766aa1c4
VS
3860#define VLV_VGACNTRL (VLV_DISPLAY_BASE + 0x71400)
3861
f2b115e6 3862/* Ironlake */
b9055052
ZW
3863
3864#define CPU_VGACNTRL 0x41000
3865
3866#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
3867#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
3868#define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
3869#define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
3870#define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
3871#define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
3872#define DIGITAL_PORTA_NO_DETECT (0 << 0)
3873#define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
3874#define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
3875
3876/* refresh rate hardware control */
3877#define RR_HW_CTL 0x45300
3878#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
3879#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
3880
3881#define FDI_PLL_BIOS_0 0x46000
021357ac 3882#define FDI_PLL_FB_CLOCK_MASK 0xff
b9055052
ZW
3883#define FDI_PLL_BIOS_1 0x46004
3884#define FDI_PLL_BIOS_2 0x46008
3885#define DISPLAY_PORT_PLL_BIOS_0 0x4600c
3886#define DISPLAY_PORT_PLL_BIOS_1 0x46010
3887#define DISPLAY_PORT_PLL_BIOS_2 0x46014
3888
8956c8bb
EA
3889#define PCH_3DCGDIS0 0x46020
3890# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
3891# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
3892
06f37751
EA
3893#define PCH_3DCGDIS1 0x46024
3894# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
3895
b9055052
ZW
3896#define FDI_PLL_FREQ_CTL 0x46030
3897#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
3898#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
3899#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
3900
3901
a57c774a 3902#define _PIPEA_DATA_M1 0x60030
5eddb70b 3903#define PIPE_DATA_M1_OFFSET 0
a57c774a 3904#define _PIPEA_DATA_N1 0x60034
5eddb70b 3905#define PIPE_DATA_N1_OFFSET 0
b9055052 3906
a57c774a 3907#define _PIPEA_DATA_M2 0x60038
5eddb70b 3908#define PIPE_DATA_M2_OFFSET 0
a57c774a 3909#define _PIPEA_DATA_N2 0x6003c
5eddb70b 3910#define PIPE_DATA_N2_OFFSET 0
b9055052 3911
a57c774a 3912#define _PIPEA_LINK_M1 0x60040
5eddb70b 3913#define PIPE_LINK_M1_OFFSET 0
a57c774a 3914#define _PIPEA_LINK_N1 0x60044
5eddb70b 3915#define PIPE_LINK_N1_OFFSET 0
b9055052 3916
a57c774a 3917#define _PIPEA_LINK_M2 0x60048
5eddb70b 3918#define PIPE_LINK_M2_OFFSET 0
a57c774a 3919#define _PIPEA_LINK_N2 0x6004c
5eddb70b 3920#define PIPE_LINK_N2_OFFSET 0
b9055052
ZW
3921
3922/* PIPEB timing regs are same start from 0x61000 */
3923
a57c774a
AK
3924#define _PIPEB_DATA_M1 0x61030
3925#define _PIPEB_DATA_N1 0x61034
3926#define _PIPEB_DATA_M2 0x61038
3927#define _PIPEB_DATA_N2 0x6103c
3928#define _PIPEB_LINK_M1 0x61040
3929#define _PIPEB_LINK_N1 0x61044
3930#define _PIPEB_LINK_M2 0x61048
3931#define _PIPEB_LINK_N2 0x6104c
3932
3933#define PIPE_DATA_M1(tran) _TRANSCODER2(tran, _PIPEA_DATA_M1)
3934#define PIPE_DATA_N1(tran) _TRANSCODER2(tran, _PIPEA_DATA_N1)
3935#define PIPE_DATA_M2(tran) _TRANSCODER2(tran, _PIPEA_DATA_M2)
3936#define PIPE_DATA_N2(tran) _TRANSCODER2(tran, _PIPEA_DATA_N2)
3937#define PIPE_LINK_M1(tran) _TRANSCODER2(tran, _PIPEA_LINK_M1)
3938#define PIPE_LINK_N1(tran) _TRANSCODER2(tran, _PIPEA_LINK_N1)
3939#define PIPE_LINK_M2(tran) _TRANSCODER2(tran, _PIPEA_LINK_M2)
3940#define PIPE_LINK_N2(tran) _TRANSCODER2(tran, _PIPEA_LINK_N2)
b9055052
ZW
3941
3942/* CPU panel fitter */
9db4a9c7
JB
3943/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
3944#define _PFA_CTL_1 0x68080
3945#define _PFB_CTL_1 0x68880
b9055052 3946#define PF_ENABLE (1<<31)
13888d78
PZ
3947#define PF_PIPE_SEL_MASK_IVB (3<<29)
3948#define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29)
b1f60b70
ZW
3949#define PF_FILTER_MASK (3<<23)
3950#define PF_FILTER_PROGRAMMED (0<<23)
3951#define PF_FILTER_MED_3x3 (1<<23)
3952#define PF_FILTER_EDGE_ENHANCE (2<<23)
3953#define PF_FILTER_EDGE_SOFTEN (3<<23)
9db4a9c7
JB
3954#define _PFA_WIN_SZ 0x68074
3955#define _PFB_WIN_SZ 0x68874
3956#define _PFA_WIN_POS 0x68070
3957#define _PFB_WIN_POS 0x68870
3958#define _PFA_VSCALE 0x68084
3959#define _PFB_VSCALE 0x68884
3960#define _PFA_HSCALE 0x68090
3961#define _PFB_HSCALE 0x68890
3962
3963#define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
3964#define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
3965#define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
3966#define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
3967#define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
b9055052
ZW
3968
3969/* legacy palette */
9db4a9c7
JB
3970#define _LGC_PALETTE_A 0x4a000
3971#define _LGC_PALETTE_B 0x4a800
3972#define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
b9055052 3973
42db64ef
PZ
3974#define _GAMMA_MODE_A 0x4a480
3975#define _GAMMA_MODE_B 0x4ac80
3976#define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
3977#define GAMMA_MODE_MODE_MASK (3 << 0)
3eff4faa
DV
3978#define GAMMA_MODE_MODE_8BIT (0 << 0)
3979#define GAMMA_MODE_MODE_10BIT (1 << 0)
3980#define GAMMA_MODE_MODE_12BIT (2 << 0)
42db64ef
PZ
3981#define GAMMA_MODE_MODE_SPLIT (3 << 0)
3982
b9055052
ZW
3983/* interrupts */
3984#define DE_MASTER_IRQ_CONTROL (1 << 31)
3985#define DE_SPRITEB_FLIP_DONE (1 << 29)
3986#define DE_SPRITEA_FLIP_DONE (1 << 28)
3987#define DE_PLANEB_FLIP_DONE (1 << 27)
3988#define DE_PLANEA_FLIP_DONE (1 << 26)
40da17c2 3989#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
b9055052
ZW
3990#define DE_PCU_EVENT (1 << 25)
3991#define DE_GTT_FAULT (1 << 24)
3992#define DE_POISON (1 << 23)
3993#define DE_PERFORM_COUNTER (1 << 22)
3994#define DE_PCH_EVENT (1 << 21)
3995#define DE_AUX_CHANNEL_A (1 << 20)
3996#define DE_DP_A_HOTPLUG (1 << 19)
3997#define DE_GSE (1 << 18)
3998#define DE_PIPEB_VBLANK (1 << 15)
3999#define DE_PIPEB_EVEN_FIELD (1 << 14)
4000#define DE_PIPEB_ODD_FIELD (1 << 13)
4001#define DE_PIPEB_LINE_COMPARE (1 << 12)
4002#define DE_PIPEB_VSYNC (1 << 11)
5b3a856b 4003#define DE_PIPEB_CRC_DONE (1 << 10)
b9055052
ZW
4004#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
4005#define DE_PIPEA_VBLANK (1 << 7)
40da17c2 4006#define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe)))
b9055052
ZW
4007#define DE_PIPEA_EVEN_FIELD (1 << 6)
4008#define DE_PIPEA_ODD_FIELD (1 << 5)
4009#define DE_PIPEA_LINE_COMPARE (1 << 4)
4010#define DE_PIPEA_VSYNC (1 << 3)
5b3a856b 4011#define DE_PIPEA_CRC_DONE (1 << 2)
40da17c2 4012#define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe)))
b9055052 4013#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
40da17c2 4014#define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe)))
b9055052 4015
b1f14ad0 4016/* More Ivybridge lolz */
8664281b 4017#define DE_ERR_INT_IVB (1<<30)
b1f14ad0
JB
4018#define DE_GSE_IVB (1<<29)
4019#define DE_PCH_EVENT_IVB (1<<28)
4020#define DE_DP_A_HOTPLUG_IVB (1<<27)
4021#define DE_AUX_CHANNEL_A_IVB (1<<26)
b615b57a
CW
4022#define DE_SPRITEC_FLIP_DONE_IVB (1<<14)
4023#define DE_PLANEC_FLIP_DONE_IVB (1<<13)
4024#define DE_PIPEC_VBLANK_IVB (1<<10)
b1f14ad0 4025#define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
b1f14ad0 4026#define DE_PLANEB_FLIP_DONE_IVB (1<<8)
b1f14ad0 4027#define DE_PIPEB_VBLANK_IVB (1<<5)
b615b57a
CW
4028#define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
4029#define DE_PLANEA_FLIP_DONE_IVB (1<<3)
40da17c2 4030#define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane)))
b1f14ad0 4031#define DE_PIPEA_VBLANK_IVB (1<<0)
b518421f
PZ
4032#define DE_PIPE_VBLANK_IVB(pipe) (1 << (pipe * 5))
4033
7eea1ddf
JB
4034#define VLV_MASTER_IER 0x4400c /* Gunit master IER */
4035#define MASTER_INTERRUPT_ENABLE (1<<31)
4036
b9055052
ZW
4037#define DEISR 0x44000
4038#define DEIMR 0x44004
4039#define DEIIR 0x44008
4040#define DEIER 0x4400c
4041
b9055052
ZW
4042#define GTISR 0x44010
4043#define GTIMR 0x44014
4044#define GTIIR 0x44018
4045#define GTIER 0x4401c
4046
abd58f01
BW
4047#define GEN8_MASTER_IRQ 0x44200
4048#define GEN8_MASTER_IRQ_CONTROL (1<<31)
4049#define GEN8_PCU_IRQ (1<<30)
4050#define GEN8_DE_PCH_IRQ (1<<23)
4051#define GEN8_DE_MISC_IRQ (1<<22)
4052#define GEN8_DE_PORT_IRQ (1<<20)
4053#define GEN8_DE_PIPE_C_IRQ (1<<18)
4054#define GEN8_DE_PIPE_B_IRQ (1<<17)
4055#define GEN8_DE_PIPE_A_IRQ (1<<16)
c42664cc 4056#define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+pipe))
abd58f01
BW
4057#define GEN8_GT_VECS_IRQ (1<<6)
4058#define GEN8_GT_VCS2_IRQ (1<<3)
4059#define GEN8_GT_VCS1_IRQ (1<<2)
4060#define GEN8_GT_BCS_IRQ (1<<1)
4061#define GEN8_GT_RCS_IRQ (1<<0)
abd58f01
BW
4062
4063#define GEN8_GT_ISR(which) (0x44300 + (0x10 * (which)))
4064#define GEN8_GT_IMR(which) (0x44304 + (0x10 * (which)))
4065#define GEN8_GT_IIR(which) (0x44308 + (0x10 * (which)))
4066#define GEN8_GT_IER(which) (0x4430c + (0x10 * (which)))
4067
4068#define GEN8_BCS_IRQ_SHIFT 16
4069#define GEN8_RCS_IRQ_SHIFT 0
4070#define GEN8_VCS2_IRQ_SHIFT 16
4071#define GEN8_VCS1_IRQ_SHIFT 0
4072#define GEN8_VECS_IRQ_SHIFT 0
4073
4074#define GEN8_DE_PIPE_ISR(pipe) (0x44400 + (0x10 * (pipe)))
4075#define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe)))
4076#define GEN8_DE_PIPE_IIR(pipe) (0x44408 + (0x10 * (pipe)))
4077#define GEN8_DE_PIPE_IER(pipe) (0x4440c + (0x10 * (pipe)))
38d83c96 4078#define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
abd58f01
BW
4079#define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
4080#define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
4081#define GEN8_PIPE_CURSOR_FAULT (1 << 10)
4082#define GEN8_PIPE_SPRITE_FAULT (1 << 9)
4083#define GEN8_PIPE_PRIMARY_FAULT (1 << 8)
4084#define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5)
4085#define GEN8_PIPE_FLIP_DONE (1 << 4)
4086#define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2)
4087#define GEN8_PIPE_VSYNC (1 << 1)
4088#define GEN8_PIPE_VBLANK (1 << 0)
30100f2b
DV
4089#define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
4090 (GEN8_PIPE_CURSOR_FAULT | \
4091 GEN8_PIPE_SPRITE_FAULT | \
4092 GEN8_PIPE_PRIMARY_FAULT)
abd58f01
BW
4093
4094#define GEN8_DE_PORT_ISR 0x44440
4095#define GEN8_DE_PORT_IMR 0x44444
4096#define GEN8_DE_PORT_IIR 0x44448
4097#define GEN8_DE_PORT_IER 0x4444c
6d766f02
DV
4098#define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
4099#define GEN8_AUX_CHANNEL_A (1 << 0)
abd58f01
BW
4100
4101#define GEN8_DE_MISC_ISR 0x44460
4102#define GEN8_DE_MISC_IMR 0x44464
4103#define GEN8_DE_MISC_IIR 0x44468
4104#define GEN8_DE_MISC_IER 0x4446c
4105#define GEN8_DE_MISC_GSE (1 << 27)
4106
4107#define GEN8_PCU_ISR 0x444e0
4108#define GEN8_PCU_IMR 0x444e4
4109#define GEN8_PCU_IIR 0x444e8
4110#define GEN8_PCU_IER 0x444ec
4111
7f8a8569 4112#define ILK_DISPLAY_CHICKEN2 0x42004
67e92af0
EA
4113/* Required on all Ironlake and Sandybridge according to the B-Spec. */
4114#define ILK_ELPIN_409_SELECT (1 << 25)
7f8a8569
ZW
4115#define ILK_DPARB_GATE (1<<22)
4116#define ILK_VSDPFD_FULL (1<<21)
e3589908
DL
4117#define FUSE_STRAP 0x42014
4118#define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
4119#define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
4120#define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
4121#define ILK_HDCP_DISABLE (1 << 25)
4122#define ILK_eDP_A_DISABLE (1 << 24)
4123#define HSW_CDCLK_LIMIT (1 << 24)
4124#define ILK_DESKTOP (1 << 23)
231e54f6
DL
4125
4126#define ILK_DSPCLK_GATE_D 0x42020
4127#define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
4128#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
4129#define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
4130#define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
4131#define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
7f8a8569 4132
116ac8d2
EA
4133#define IVB_CHICKEN3 0x4200c
4134# define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
4135# define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
4136
90a88643 4137#define CHICKEN_PAR1_1 0x42080
fe4ab3ce 4138#define DPA_MASK_VBLANK_SRD (1 << 15)
90a88643
PZ
4139#define FORCE_ARB_IDLE_PLANES (1 << 14)
4140
fe4ab3ce
BW
4141#define _CHICKEN_PIPESL_1_A 0x420b0
4142#define _CHICKEN_PIPESL_1_B 0x420b4
4143#define DPRS_MASK_VBLANK_SRD (1 << 0)
4144#define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
4145
553bd149
ZW
4146#define DISP_ARB_CTL 0x45000
4147#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
7f8a8569 4148#define DISP_FBC_WM_DIS (1<<15)
ac9545fd
VS
4149#define DISP_ARB_CTL2 0x45004
4150#define DISP_DATA_PARTITION_5_6 (1<<6)
88a2b2a3
BW
4151#define GEN7_MSG_CTL 0x45010
4152#define WAIT_FOR_PCH_RESET_ACK (1<<1)
4153#define WAIT_FOR_PCH_FLR_ACK (1<<0)
6ba844b0
DV
4154#define HSW_NDE_RSTWRN_OPT 0x46408
4155#define RESET_PCH_HANDSHAKE_ENABLE (1<<4)
553bd149 4156
e4e0c058 4157/* GEN7 chicken */
d71de14d
KG
4158#define GEN7_COMMON_SLICE_CHICKEN1 0x7010
4159# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
a75f3628
BW
4160#define COMMON_SLICE_CHICKEN2 0x7014
4161# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
d71de14d 4162
031994ee
VS
4163#define GEN7_L3SQCREG1 0xB010
4164#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
4165
e4e0c058
ED
4166#define GEN7_L3CNTLREG1 0xB01C
4167#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C
d0cf5ead 4168#define GEN7_L3AGDIS (1<<19)
e4e0c058
ED
4169
4170#define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030
4171#define GEN7_WA_L3_CHICKEN_MODE 0x20000000
4172
61939d97
JB
4173#define GEN7_L3SQCREG4 0xb034
4174#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)
4175
63801f21
BW
4176/* GEN8 chicken */
4177#define HDC_CHICKEN0 0x7300
4178#define HDC_FORCE_NON_COHERENT (1<<4)
4179
db099c8f
ED
4180/* WaCatErrorRejectionIssue */
4181#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
4182#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
4183
f3fc4884
FJ
4184#define HSW_SCRATCH1 0xb038
4185#define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27)
4186
b9055052
ZW
4187/* PCH */
4188
23e81d69 4189/* south display engine interrupt: IBX */
776ad806
JB
4190#define SDE_AUDIO_POWER_D (1 << 27)
4191#define SDE_AUDIO_POWER_C (1 << 26)
4192#define SDE_AUDIO_POWER_B (1 << 25)
4193#define SDE_AUDIO_POWER_SHIFT (25)
4194#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
4195#define SDE_GMBUS (1 << 24)
4196#define SDE_AUDIO_HDCP_TRANSB (1 << 23)
4197#define SDE_AUDIO_HDCP_TRANSA (1 << 22)
4198#define SDE_AUDIO_HDCP_MASK (3 << 22)
4199#define SDE_AUDIO_TRANSB (1 << 21)
4200#define SDE_AUDIO_TRANSA (1 << 20)
4201#define SDE_AUDIO_TRANS_MASK (3 << 20)
4202#define SDE_POISON (1 << 19)
4203/* 18 reserved */
4204#define SDE_FDI_RXB (1 << 17)
4205#define SDE_FDI_RXA (1 << 16)
4206#define SDE_FDI_MASK (3 << 16)
4207#define SDE_AUXD (1 << 15)
4208#define SDE_AUXC (1 << 14)
4209#define SDE_AUXB (1 << 13)
4210#define SDE_AUX_MASK (7 << 13)
4211/* 12 reserved */
b9055052
ZW
4212#define SDE_CRT_HOTPLUG (1 << 11)
4213#define SDE_PORTD_HOTPLUG (1 << 10)
4214#define SDE_PORTC_HOTPLUG (1 << 9)
4215#define SDE_PORTB_HOTPLUG (1 << 8)
4216#define SDE_SDVOB_HOTPLUG (1 << 6)
e5868a31
EE
4217#define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
4218 SDE_SDVOB_HOTPLUG | \
4219 SDE_PORTB_HOTPLUG | \
4220 SDE_PORTC_HOTPLUG | \
4221 SDE_PORTD_HOTPLUG)
776ad806
JB
4222#define SDE_TRANSB_CRC_DONE (1 << 5)
4223#define SDE_TRANSB_CRC_ERR (1 << 4)
4224#define SDE_TRANSB_FIFO_UNDER (1 << 3)
4225#define SDE_TRANSA_CRC_DONE (1 << 2)
4226#define SDE_TRANSA_CRC_ERR (1 << 1)
4227#define SDE_TRANSA_FIFO_UNDER (1 << 0)
4228#define SDE_TRANS_MASK (0x3f)
23e81d69
AJ
4229
4230/* south display engine interrupt: CPT/PPT */
4231#define SDE_AUDIO_POWER_D_CPT (1 << 31)
4232#define SDE_AUDIO_POWER_C_CPT (1 << 30)
4233#define SDE_AUDIO_POWER_B_CPT (1 << 29)
4234#define SDE_AUDIO_POWER_SHIFT_CPT 29
4235#define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
4236#define SDE_AUXD_CPT (1 << 27)
4237#define SDE_AUXC_CPT (1 << 26)
4238#define SDE_AUXB_CPT (1 << 25)
4239#define SDE_AUX_MASK_CPT (7 << 25)
8db9d77b
ZW
4240#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
4241#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
4242#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
23e81d69 4243#define SDE_CRT_HOTPLUG_CPT (1 << 19)
73c352a2 4244#define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
2d7b8366 4245#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
73c352a2 4246 SDE_SDVOB_HOTPLUG_CPT | \
2d7b8366
YL
4247 SDE_PORTD_HOTPLUG_CPT | \
4248 SDE_PORTC_HOTPLUG_CPT | \
4249 SDE_PORTB_HOTPLUG_CPT)
23e81d69 4250#define SDE_GMBUS_CPT (1 << 17)
8664281b 4251#define SDE_ERROR_CPT (1 << 16)
23e81d69
AJ
4252#define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
4253#define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
4254#define SDE_FDI_RXC_CPT (1 << 8)
4255#define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
4256#define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
4257#define SDE_FDI_RXB_CPT (1 << 4)
4258#define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
4259#define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
4260#define SDE_FDI_RXA_CPT (1 << 0)
4261#define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
4262 SDE_AUDIO_CP_REQ_B_CPT | \
4263 SDE_AUDIO_CP_REQ_A_CPT)
4264#define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
4265 SDE_AUDIO_CP_CHG_B_CPT | \
4266 SDE_AUDIO_CP_CHG_A_CPT)
4267#define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
4268 SDE_FDI_RXB_CPT | \
4269 SDE_FDI_RXA_CPT)
b9055052
ZW
4270
4271#define SDEISR 0xc4000
4272#define SDEIMR 0xc4004
4273#define SDEIIR 0xc4008
4274#define SDEIER 0xc400c
4275
8664281b 4276#define SERR_INT 0xc4040
de032bf4 4277#define SERR_INT_POISON (1<<31)
8664281b
PZ
4278#define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6)
4279#define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3)
4280#define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0)
1dd246fb 4281#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<(pipe*3))
8664281b 4282
b9055052 4283/* digital port hotplug */
7fe0b973 4284#define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */
b9055052
ZW
4285#define PORTD_HOTPLUG_ENABLE (1 << 20)
4286#define PORTD_PULSE_DURATION_2ms (0)
4287#define PORTD_PULSE_DURATION_4_5ms (1 << 18)
4288#define PORTD_PULSE_DURATION_6ms (2 << 18)
4289#define PORTD_PULSE_DURATION_100ms (3 << 18)
7fe0b973 4290#define PORTD_PULSE_DURATION_MASK (3 << 18)
b696519e
DL
4291#define PORTD_HOTPLUG_STATUS_MASK (0x3 << 16)
4292#define PORTD_HOTPLUG_NO_DETECT (0 << 16)
4293#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
4294#define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
b9055052
ZW
4295#define PORTC_HOTPLUG_ENABLE (1 << 12)
4296#define PORTC_PULSE_DURATION_2ms (0)
4297#define PORTC_PULSE_DURATION_4_5ms (1 << 10)
4298#define PORTC_PULSE_DURATION_6ms (2 << 10)
4299#define PORTC_PULSE_DURATION_100ms (3 << 10)
7fe0b973 4300#define PORTC_PULSE_DURATION_MASK (3 << 10)
b696519e
DL
4301#define PORTC_HOTPLUG_STATUS_MASK (0x3 << 8)
4302#define PORTC_HOTPLUG_NO_DETECT (0 << 8)
4303#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
4304#define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
b9055052
ZW
4305#define PORTB_HOTPLUG_ENABLE (1 << 4)
4306#define PORTB_PULSE_DURATION_2ms (0)
4307#define PORTB_PULSE_DURATION_4_5ms (1 << 2)
4308#define PORTB_PULSE_DURATION_6ms (2 << 2)
4309#define PORTB_PULSE_DURATION_100ms (3 << 2)
7fe0b973 4310#define PORTB_PULSE_DURATION_MASK (3 << 2)
b696519e
DL
4311#define PORTB_HOTPLUG_STATUS_MASK (0x3 << 0)
4312#define PORTB_HOTPLUG_NO_DETECT (0 << 0)
4313#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
4314#define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
b9055052
ZW
4315
4316#define PCH_GPIOA 0xc5010
4317#define PCH_GPIOB 0xc5014
4318#define PCH_GPIOC 0xc5018
4319#define PCH_GPIOD 0xc501c
4320#define PCH_GPIOE 0xc5020
4321#define PCH_GPIOF 0xc5024
4322
f0217c42
EA
4323#define PCH_GMBUS0 0xc5100
4324#define PCH_GMBUS1 0xc5104
4325#define PCH_GMBUS2 0xc5108
4326#define PCH_GMBUS3 0xc510c
4327#define PCH_GMBUS4 0xc5110
4328#define PCH_GMBUS5 0xc5120
4329
9db4a9c7
JB
4330#define _PCH_DPLL_A 0xc6014
4331#define _PCH_DPLL_B 0xc6018
e9a632a5 4332#define PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
b9055052 4333
9db4a9c7 4334#define _PCH_FPA0 0xc6040
c1858123 4335#define FP_CB_TUNE (0x3<<22)
9db4a9c7
JB
4336#define _PCH_FPA1 0xc6044
4337#define _PCH_FPB0 0xc6048
4338#define _PCH_FPB1 0xc604c
e9a632a5
DV
4339#define PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
4340#define PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
b9055052
ZW
4341
4342#define PCH_DPLL_TEST 0xc606c
4343
4344#define PCH_DREF_CONTROL 0xC6200
4345#define DREF_CONTROL_MASK 0x7fc3
4346#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
4347#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
4348#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
4349#define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
4350#define DREF_SSC_SOURCE_DISABLE (0<<11)
4351#define DREF_SSC_SOURCE_ENABLE (2<<11)
c038e51e 4352#define DREF_SSC_SOURCE_MASK (3<<11)
b9055052
ZW
4353#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
4354#define DREF_NONSPREAD_CK505_ENABLE (1<<9)
4355#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
c038e51e 4356#define DREF_NONSPREAD_SOURCE_MASK (3<<9)
b9055052
ZW
4357#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
4358#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
92f2584a 4359#define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
b9055052
ZW
4360#define DREF_SSC4_DOWNSPREAD (0<<6)
4361#define DREF_SSC4_CENTERSPREAD (1<<6)
4362#define DREF_SSC1_DISABLE (0<<1)
4363#define DREF_SSC1_ENABLE (1<<1)
4364#define DREF_SSC4_DISABLE (0)
4365#define DREF_SSC4_ENABLE (1)
4366
4367#define PCH_RAWCLK_FREQ 0xc6204
4368#define FDL_TP1_TIMER_SHIFT 12
4369#define FDL_TP1_TIMER_MASK (3<<12)
4370#define FDL_TP2_TIMER_SHIFT 10
4371#define FDL_TP2_TIMER_MASK (3<<10)
4372#define RAWCLK_FREQ_MASK 0x3ff
4373
4374#define PCH_DPLL_TMR_CFG 0xc6208
4375
4376#define PCH_SSC4_PARMS 0xc6210
4377#define PCH_SSC4_AUX_PARMS 0xc6214
4378
8db9d77b 4379#define PCH_DPLL_SEL 0xc7000
11887397
DV
4380#define TRANS_DPLLB_SEL(pipe) (1 << (pipe * 4))
4381#define TRANS_DPLLA_SEL(pipe) 0
4382#define TRANS_DPLL_ENABLE(pipe) (1 << (pipe * 4 + 3))
8db9d77b 4383
b9055052
ZW
4384/* transcoder */
4385
275f01b2
DV
4386#define _PCH_TRANS_HTOTAL_A 0xe0000
4387#define TRANS_HTOTAL_SHIFT 16
4388#define TRANS_HACTIVE_SHIFT 0
4389#define _PCH_TRANS_HBLANK_A 0xe0004
4390#define TRANS_HBLANK_END_SHIFT 16
4391#define TRANS_HBLANK_START_SHIFT 0
4392#define _PCH_TRANS_HSYNC_A 0xe0008
4393#define TRANS_HSYNC_END_SHIFT 16
4394#define TRANS_HSYNC_START_SHIFT 0
4395#define _PCH_TRANS_VTOTAL_A 0xe000c
4396#define TRANS_VTOTAL_SHIFT 16
4397#define TRANS_VACTIVE_SHIFT 0
4398#define _PCH_TRANS_VBLANK_A 0xe0010
4399#define TRANS_VBLANK_END_SHIFT 16
4400#define TRANS_VBLANK_START_SHIFT 0
4401#define _PCH_TRANS_VSYNC_A 0xe0014
4402#define TRANS_VSYNC_END_SHIFT 16
4403#define TRANS_VSYNC_START_SHIFT 0
4404#define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
b9055052 4405
e3b95f1e
DV
4406#define _PCH_TRANSA_DATA_M1 0xe0030
4407#define _PCH_TRANSA_DATA_N1 0xe0034
4408#define _PCH_TRANSA_DATA_M2 0xe0038
4409#define _PCH_TRANSA_DATA_N2 0xe003c
4410#define _PCH_TRANSA_LINK_M1 0xe0040
4411#define _PCH_TRANSA_LINK_N1 0xe0044
4412#define _PCH_TRANSA_LINK_M2 0xe0048
4413#define _PCH_TRANSA_LINK_N2 0xe004c
9db4a9c7 4414
b055c8f3
JB
4415/* Per-transcoder DIP controls */
4416
4417#define _VIDEO_DIP_CTL_A 0xe0200
4418#define _VIDEO_DIP_DATA_A 0xe0208
4419#define _VIDEO_DIP_GCP_A 0xe0210
4420
4421#define _VIDEO_DIP_CTL_B 0xe1200
4422#define _VIDEO_DIP_DATA_B 0xe1208
4423#define _VIDEO_DIP_GCP_B 0xe1210
4424
4425#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
4426#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
4427#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
4428
b906487c
VS
4429#define VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
4430#define VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
4431#define VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
90b107c8 4432
b906487c
VS
4433#define VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
4434#define VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
4435#define VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
90b107c8
SK
4436
4437#define VLV_TVIDEO_DIP_CTL(pipe) \
4438 _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B)
4439#define VLV_TVIDEO_DIP_DATA(pipe) \
4440 _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B)
4441#define VLV_TVIDEO_DIP_GCP(pipe) \
4442 _PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
4443
8c5f5f7c
ED
4444/* Haswell DIP controls */
4445#define HSW_VIDEO_DIP_CTL_A 0x60200
4446#define HSW_VIDEO_DIP_AVI_DATA_A 0x60220
4447#define HSW_VIDEO_DIP_VS_DATA_A 0x60260
4448#define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
4449#define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
4450#define HSW_VIDEO_DIP_VSC_DATA_A 0x60320
4451#define HSW_VIDEO_DIP_AVI_ECC_A 0x60240
4452#define HSW_VIDEO_DIP_VS_ECC_A 0x60280
4453#define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
4454#define HSW_VIDEO_DIP_GMP_ECC_A 0x60300
4455#define HSW_VIDEO_DIP_VSC_ECC_A 0x60344
4456#define HSW_VIDEO_DIP_GCP_A 0x60210
4457
4458#define HSW_VIDEO_DIP_CTL_B 0x61200
4459#define HSW_VIDEO_DIP_AVI_DATA_B 0x61220
4460#define HSW_VIDEO_DIP_VS_DATA_B 0x61260
4461#define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
4462#define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
4463#define HSW_VIDEO_DIP_VSC_DATA_B 0x61320
4464#define HSW_VIDEO_DIP_BVI_ECC_B 0x61240
4465#define HSW_VIDEO_DIP_VS_ECC_B 0x61280
4466#define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
4467#define HSW_VIDEO_DIP_GMP_ECC_B 0x61300
4468#define HSW_VIDEO_DIP_VSC_ECC_B 0x61344
4469#define HSW_VIDEO_DIP_GCP_B 0x61210
4470
7d9bcebe 4471#define HSW_TVIDEO_DIP_CTL(trans) \
a57c774a 4472 _TRANSCODER2(trans, HSW_VIDEO_DIP_CTL_A)
7d9bcebe 4473#define HSW_TVIDEO_DIP_AVI_DATA(trans) \
a57c774a 4474 _TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A)
c8bb75af 4475#define HSW_TVIDEO_DIP_VS_DATA(trans) \
a57c774a 4476 _TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A)
7d9bcebe 4477#define HSW_TVIDEO_DIP_SPD_DATA(trans) \
a57c774a 4478 _TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A)
7d9bcebe 4479#define HSW_TVIDEO_DIP_GCP(trans) \
a57c774a 4480 _TRANSCODER2(trans, HSW_VIDEO_DIP_GCP_A)
7d9bcebe 4481#define HSW_TVIDEO_DIP_VSC_DATA(trans) \
a57c774a 4482 _TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A)
8c5f5f7c 4483
3f51e471
RV
4484#define HSW_STEREO_3D_CTL_A 0x70020
4485#define S3D_ENABLE (1<<31)
4486#define HSW_STEREO_3D_CTL_B 0x71020
4487
4488#define HSW_STEREO_3D_CTL(trans) \
a57c774a 4489 _PIPE2(trans, HSW_STEREO_3D_CTL_A)
3f51e471 4490
275f01b2
DV
4491#define _PCH_TRANS_HTOTAL_B 0xe1000
4492#define _PCH_TRANS_HBLANK_B 0xe1004
4493#define _PCH_TRANS_HSYNC_B 0xe1008
4494#define _PCH_TRANS_VTOTAL_B 0xe100c
4495#define _PCH_TRANS_VBLANK_B 0xe1010
4496#define _PCH_TRANS_VSYNC_B 0xe1014
4497#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
4498
4499#define PCH_TRANS_HTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
4500#define PCH_TRANS_HBLANK(pipe) _PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
4501#define PCH_TRANS_HSYNC(pipe) _PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
4502#define PCH_TRANS_VTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
4503#define PCH_TRANS_VBLANK(pipe) _PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
4504#define PCH_TRANS_VSYNC(pipe) _PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
4505#define PCH_TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, \
4506 _PCH_TRANS_VSYNCSHIFT_B)
9db4a9c7 4507
e3b95f1e
DV
4508#define _PCH_TRANSB_DATA_M1 0xe1030
4509#define _PCH_TRANSB_DATA_N1 0xe1034
4510#define _PCH_TRANSB_DATA_M2 0xe1038
4511#define _PCH_TRANSB_DATA_N2 0xe103c
4512#define _PCH_TRANSB_LINK_M1 0xe1040
4513#define _PCH_TRANSB_LINK_N1 0xe1044
4514#define _PCH_TRANSB_LINK_M2 0xe1048
4515#define _PCH_TRANSB_LINK_N2 0xe104c
4516
4517#define PCH_TRANS_DATA_M1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
4518#define PCH_TRANS_DATA_N1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
4519#define PCH_TRANS_DATA_M2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
4520#define PCH_TRANS_DATA_N2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
4521#define PCH_TRANS_LINK_M1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
4522#define PCH_TRANS_LINK_N1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
4523#define PCH_TRANS_LINK_M2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
4524#define PCH_TRANS_LINK_N2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
9db4a9c7 4525
ab9412ba
DV
4526#define _PCH_TRANSACONF 0xf0008
4527#define _PCH_TRANSBCONF 0xf1008
4528#define PCH_TRANSCONF(pipe) _PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
4529#define LPT_TRANSCONF _PCH_TRANSACONF /* lpt has only one transcoder */
b9055052
ZW
4530#define TRANS_DISABLE (0<<31)
4531#define TRANS_ENABLE (1<<31)
4532#define TRANS_STATE_MASK (1<<30)
4533#define TRANS_STATE_DISABLE (0<<30)
4534#define TRANS_STATE_ENABLE (1<<30)
4535#define TRANS_FSYNC_DELAY_HB1 (0<<27)
4536#define TRANS_FSYNC_DELAY_HB2 (1<<27)
4537#define TRANS_FSYNC_DELAY_HB3 (2<<27)
4538#define TRANS_FSYNC_DELAY_HB4 (3<<27)
5f7f726d 4539#define TRANS_INTERLACE_MASK (7<<21)
b9055052 4540#define TRANS_PROGRESSIVE (0<<21)
5f7f726d 4541#define TRANS_INTERLACED (3<<21)
7c26e5c6 4542#define TRANS_LEGACY_INTERLACED_ILK (2<<21)
b9055052
ZW
4543#define TRANS_8BPC (0<<5)
4544#define TRANS_10BPC (1<<5)
4545#define TRANS_6BPC (2<<5)
4546#define TRANS_12BPC (3<<5)
4547
ce40141f
DV
4548#define _TRANSA_CHICKEN1 0xf0060
4549#define _TRANSB_CHICKEN1 0xf1060
4550#define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
4551#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4)
3bcf603f
JB
4552#define _TRANSA_CHICKEN2 0xf0064
4553#define _TRANSB_CHICKEN2 0xf1064
4554#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
dc4bd2d1
PZ
4555#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
4556#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
4557#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27)
4558#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26)
4559#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25)
3bcf603f 4560
291427f5
JB
4561#define SOUTH_CHICKEN1 0xc2000
4562#define FDIA_PHASE_SYNC_SHIFT_OVR 19
4563#define FDIA_PHASE_SYNC_SHIFT_EN 18
01a415fd
DV
4564#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
4565#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
4566#define FDI_BC_BIFURCATION_SELECT (1 << 12)
645c62a5 4567#define SOUTH_CHICKEN2 0xc2004
dde86e2d
PZ
4568#define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)
4569#define FDI_MPHY_IOSFSB_RESET_CTL (1<<12)
4570#define DPLS_EDP_PPS_FIX_DIS (1<<0)
645c62a5 4571
9db4a9c7
JB
4572#define _FDI_RXA_CHICKEN 0xc200c
4573#define _FDI_RXB_CHICKEN 0xc2010
6f06ce18
JB
4574#define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
4575#define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
9db4a9c7 4576#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
b9055052 4577
382b0936 4578#define SOUTH_DSPCLK_GATE_D 0xc2020
cd664078 4579#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
382b0936 4580#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
cd664078 4581#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
17a303ec 4582#define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
382b0936 4583
b9055052 4584/* CPU: FDI_TX */
9db4a9c7
JB
4585#define _FDI_TXA_CTL 0x60100
4586#define _FDI_TXB_CTL 0x61100
4587#define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
b9055052
ZW
4588#define FDI_TX_DISABLE (0<<31)
4589#define FDI_TX_ENABLE (1<<31)
4590#define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
4591#define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
4592#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
4593#define FDI_LINK_TRAIN_NONE (3<<28)
4594#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
4595#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
4596#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
4597#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
4598#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
4599#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
4600#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
4601#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
8db9d77b
ZW
4602/* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
4603 SNB has different settings. */
4604/* SNB A-stepping */
4605#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
4606#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
4607#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
4608#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
4609/* SNB B-stepping */
4610#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
4611#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
4612#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
4613#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
4614#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
627eb5a3
DV
4615#define FDI_DP_PORT_WIDTH_SHIFT 19
4616#define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
4617#define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
b9055052 4618#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
f2b115e6 4619/* Ironlake: hardwired to 1 */
b9055052 4620#define FDI_TX_PLL_ENABLE (1<<14)
357555c0
JB
4621
4622/* Ivybridge has different bits for lolz */
4623#define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
4624#define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
4625#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
4626#define FDI_LINK_TRAIN_NONE_IVB (3<<8)
4627
b9055052 4628/* both Tx and Rx */
c4f9c4c2 4629#define FDI_COMPOSITE_SYNC (1<<11)
357555c0 4630#define FDI_LINK_TRAIN_AUTO (1<<10)
b9055052
ZW
4631#define FDI_SCRAMBLING_ENABLE (0<<7)
4632#define FDI_SCRAMBLING_DISABLE (1<<7)
4633
4634/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
9db4a9c7
JB
4635#define _FDI_RXA_CTL 0xf000c
4636#define _FDI_RXB_CTL 0xf100c
4637#define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
b9055052 4638#define FDI_RX_ENABLE (1<<31)
b9055052 4639/* train, dp width same as FDI_TX */
357555c0
JB
4640#define FDI_FS_ERRC_ENABLE (1<<27)
4641#define FDI_FE_ERRC_ENABLE (1<<26)
68d18ad7 4642#define FDI_RX_POLARITY_REVERSED_LPT (1<<16)
b9055052
ZW
4643#define FDI_8BPC (0<<16)
4644#define FDI_10BPC (1<<16)
4645#define FDI_6BPC (2<<16)
4646#define FDI_12BPC (3<<16)
3e68320e 4647#define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15)
b9055052
ZW
4648#define FDI_DMI_LINK_REVERSE_MASK (1<<14)
4649#define FDI_RX_PLL_ENABLE (1<<13)
4650#define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
4651#define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
4652#define FDI_FS_ERR_REPORT_ENABLE (1<<9)
4653#define FDI_FE_ERR_REPORT_ENABLE (1<<8)
4654#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
5eddb70b 4655#define FDI_PCDCLK (1<<4)
8db9d77b
ZW
4656/* CPT */
4657#define FDI_AUTO_TRAINING (1<<10)
4658#define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
4659#define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
4660#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
4661#define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
4662#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
b9055052 4663
04945641
PZ
4664#define _FDI_RXA_MISC 0xf0010
4665#define _FDI_RXB_MISC 0xf1010
4666#define FDI_RX_PWRDN_LANE1_MASK (3<<26)
4667#define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26)
4668#define FDI_RX_PWRDN_LANE0_MASK (3<<24)
4669#define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24)
4670#define FDI_RX_TP1_TO_TP2_48 (2<<20)
4671#define FDI_RX_TP1_TO_TP2_64 (3<<20)
4672#define FDI_RX_FDI_DELAY_90 (0x90<<0)
4673#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
4674
9db4a9c7
JB
4675#define _FDI_RXA_TUSIZE1 0xf0030
4676#define _FDI_RXA_TUSIZE2 0xf0038
4677#define _FDI_RXB_TUSIZE1 0xf1030
4678#define _FDI_RXB_TUSIZE2 0xf1038
9db4a9c7
JB
4679#define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
4680#define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
b9055052
ZW
4681
4682/* FDI_RX interrupt register format */
4683#define FDI_RX_INTER_LANE_ALIGN (1<<10)
4684#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
4685#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
4686#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
4687#define FDI_RX_FS_CODE_ERR (1<<6)
4688#define FDI_RX_FE_CODE_ERR (1<<5)
4689#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
4690#define FDI_RX_HDCP_LINK_FAIL (1<<3)
4691#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
4692#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
4693#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
4694
9db4a9c7
JB
4695#define _FDI_RXA_IIR 0xf0014
4696#define _FDI_RXA_IMR 0xf0018
4697#define _FDI_RXB_IIR 0xf1014
4698#define _FDI_RXB_IMR 0xf1018
4699#define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
4700#define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
b9055052
ZW
4701
4702#define FDI_PLL_CTL_1 0xfe000
4703#define FDI_PLL_CTL_2 0xfe004
4704
b9055052
ZW
4705#define PCH_LVDS 0xe1180
4706#define LVDS_DETECTED (1 << 1)
4707
98364379 4708/* vlv has 2 sets of panel control regs. */
f12c47b2
VS
4709#define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200)
4710#define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204)
4711#define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208)
a24c144c
JN
4712#define PANEL_PORT_SELECT_DPB_VLV (1 << 30)
4713#define PANEL_PORT_SELECT_DPC_VLV (2 << 30)
f12c47b2
VS
4714#define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c)
4715#define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210)
4716
4717#define PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300)
4718#define PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304)
4719#define PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308)
4720#define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c)
4721#define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310)
98364379 4722
453c5420
JB
4723#define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
4724#define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
4725#define VLV_PIPE_PP_ON_DELAYS(pipe) \
4726 _PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
4727#define VLV_PIPE_PP_OFF_DELAYS(pipe) \
4728 _PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
4729#define VLV_PIPE_PP_DIVISOR(pipe) \
4730 _PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
4731
b9055052
ZW
4732#define PCH_PP_STATUS 0xc7200
4733#define PCH_PP_CONTROL 0xc7204
4a655f04 4734#define PANEL_UNLOCK_REGS (0xabcd << 16)
1c0ae80a 4735#define PANEL_UNLOCK_MASK (0xffff << 16)
b9055052
ZW
4736#define EDP_FORCE_VDD (1 << 3)
4737#define EDP_BLC_ENABLE (1 << 2)
4738#define PANEL_POWER_RESET (1 << 1)
4739#define PANEL_POWER_OFF (0 << 0)
4740#define PANEL_POWER_ON (1 << 0)
4741#define PCH_PP_ON_DELAYS 0xc7208
f01eca2e
KP
4742#define PANEL_PORT_SELECT_MASK (3 << 30)
4743#define PANEL_PORT_SELECT_LVDS (0 << 30)
4744#define PANEL_PORT_SELECT_DPA (1 << 30)
f01eca2e
KP
4745#define PANEL_PORT_SELECT_DPC (2 << 30)
4746#define PANEL_PORT_SELECT_DPD (3 << 30)
4747#define PANEL_POWER_UP_DELAY_MASK (0x1fff0000)
4748#define PANEL_POWER_UP_DELAY_SHIFT 16
4749#define PANEL_LIGHT_ON_DELAY_MASK (0x1fff)
4750#define PANEL_LIGHT_ON_DELAY_SHIFT 0
4751
b9055052 4752#define PCH_PP_OFF_DELAYS 0xc720c
f01eca2e
KP
4753#define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)
4754#define PANEL_POWER_DOWN_DELAY_SHIFT 16
4755#define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)
4756#define PANEL_LIGHT_OFF_DELAY_SHIFT 0
4757
b9055052 4758#define PCH_PP_DIVISOR 0xc7210
f01eca2e
KP
4759#define PP_REFERENCE_DIVIDER_MASK (0xffffff00)
4760#define PP_REFERENCE_DIVIDER_SHIFT 8
4761#define PANEL_POWER_CYCLE_DELAY_MASK (0x1f)
4762#define PANEL_POWER_CYCLE_DELAY_SHIFT 0
b9055052 4763
5eb08b69
ZW
4764#define PCH_DP_B 0xe4100
4765#define PCH_DPB_AUX_CH_CTL 0xe4110
4766#define PCH_DPB_AUX_CH_DATA1 0xe4114
4767#define PCH_DPB_AUX_CH_DATA2 0xe4118
4768#define PCH_DPB_AUX_CH_DATA3 0xe411c
4769#define PCH_DPB_AUX_CH_DATA4 0xe4120
4770#define PCH_DPB_AUX_CH_DATA5 0xe4124
4771
4772#define PCH_DP_C 0xe4200
4773#define PCH_DPC_AUX_CH_CTL 0xe4210
4774#define PCH_DPC_AUX_CH_DATA1 0xe4214
4775#define PCH_DPC_AUX_CH_DATA2 0xe4218
4776#define PCH_DPC_AUX_CH_DATA3 0xe421c
4777#define PCH_DPC_AUX_CH_DATA4 0xe4220
4778#define PCH_DPC_AUX_CH_DATA5 0xe4224
4779
4780#define PCH_DP_D 0xe4300
4781#define PCH_DPD_AUX_CH_CTL 0xe4310
4782#define PCH_DPD_AUX_CH_DATA1 0xe4314
4783#define PCH_DPD_AUX_CH_DATA2 0xe4318
4784#define PCH_DPD_AUX_CH_DATA3 0xe431c
4785#define PCH_DPD_AUX_CH_DATA4 0xe4320
4786#define PCH_DPD_AUX_CH_DATA5 0xe4324
4787
8db9d77b
ZW
4788/* CPT */
4789#define PORT_TRANS_A_SEL_CPT 0
4790#define PORT_TRANS_B_SEL_CPT (1<<29)
4791#define PORT_TRANS_C_SEL_CPT (2<<29)
4792#define PORT_TRANS_SEL_MASK (3<<29)
1519b995 4793#define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
19d8fe15
DV
4794#define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30)
4795#define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29)
8db9d77b
ZW
4796
4797#define TRANS_DP_CTL_A 0xe0300
4798#define TRANS_DP_CTL_B 0xe1300
4799#define TRANS_DP_CTL_C 0xe2300
23670b32 4800#define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)
8db9d77b
ZW
4801#define TRANS_DP_OUTPUT_ENABLE (1<<31)
4802#define TRANS_DP_PORT_SEL_B (0<<29)
4803#define TRANS_DP_PORT_SEL_C (1<<29)
4804#define TRANS_DP_PORT_SEL_D (2<<29)
cb3543c6 4805#define TRANS_DP_PORT_SEL_NONE (3<<29)
8db9d77b
ZW
4806#define TRANS_DP_PORT_SEL_MASK (3<<29)
4807#define TRANS_DP_AUDIO_ONLY (1<<26)
4808#define TRANS_DP_ENH_FRAMING (1<<18)
4809#define TRANS_DP_8BPC (0<<9)
4810#define TRANS_DP_10BPC (1<<9)
4811#define TRANS_DP_6BPC (2<<9)
4812#define TRANS_DP_12BPC (3<<9)
220cad3c 4813#define TRANS_DP_BPC_MASK (3<<9)
8db9d77b
ZW
4814#define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
4815#define TRANS_DP_VSYNC_ACTIVE_LOW 0
4816#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
4817#define TRANS_DP_HSYNC_ACTIVE_LOW 0
94113cec 4818#define TRANS_DP_SYNC_MASK (3<<3)
8db9d77b
ZW
4819
4820/* SNB eDP training params */
4821/* SNB A-stepping */
4822#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
4823#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
4824#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
4825#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
4826/* SNB B-stepping */
3c5a62b5
YL
4827#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
4828#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
4829#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
4830#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
4831#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
8db9d77b
ZW
4832#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
4833
1a2eb460
KP
4834/* IVB */
4835#define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22)
4836#define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22)
4837#define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22)
4838#define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22)
4839#define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22)
4840#define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22)
77fa4cbd 4841#define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22)
1a2eb460
KP
4842
4843/* legacy values */
4844#define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22)
4845#define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22)
4846#define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22)
4847#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22)
4848#define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22)
4849
4850#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22)
4851
cae5852d 4852#define FORCEWAKE 0xA18C
575155a9
JB
4853#define FORCEWAKE_VLV 0x1300b0
4854#define FORCEWAKE_ACK_VLV 0x1300b4
ed5de399
JB
4855#define FORCEWAKE_MEDIA_VLV 0x1300b8
4856#define FORCEWAKE_ACK_MEDIA_VLV 0x1300bc
e7911c48 4857#define FORCEWAKE_ACK_HSW 0x130044
eb43f4af 4858#define FORCEWAKE_ACK 0x130090
d62b4892
JB
4859#define VLV_GTLC_WAKE_CTRL 0x130090
4860#define VLV_GTLC_PW_STATUS 0x130094
669ab5aa
D
4861#define VLV_GTLC_PW_RENDER_STATUS_MASK 0x80
4862#define VLV_GTLC_PW_MEDIA_STATUS_MASK 0x20
8d715f00 4863#define FORCEWAKE_MT 0xa188 /* multi-threaded */
c5836c27
CW
4864#define FORCEWAKE_KERNEL 0x1
4865#define FORCEWAKE_USER 0x2
8d715f00
KP
4866#define FORCEWAKE_MT_ACK 0x130040
4867#define ECOBUS 0xa180
4868#define FORCEWAKE_MT_ENABLE (1<<5)
8fd26859 4869
dd202c6d 4870#define GTFIFODBG 0x120000
90f256b5
VS
4871#define GT_FIFO_SBDROPERR (1<<6)
4872#define GT_FIFO_BLOBDROPERR (1<<5)
4873#define GT_FIFO_SB_READ_ABORTERR (1<<4)
4874#define GT_FIFO_DROPERR (1<<3)
dd202c6d
BW
4875#define GT_FIFO_OVFERR (1<<2)
4876#define GT_FIFO_IAWRERR (1<<1)
4877#define GT_FIFO_IARDERR (1<<0)
4878
46520e2b
VS
4879#define GTFIFOCTL 0x120008
4880#define GT_FIFO_FREE_ENTRIES_MASK 0x7f
95736720 4881#define GT_FIFO_NUM_RESERVED_ENTRIES 20
91355834 4882
05e21cc4
BW
4883#define HSW_IDICR 0x9008
4884#define IDIHASHMSK(x) (((x) & 0x3f) << 16)
4885#define HSW_EDRAM_PRESENT 0x120010
4886
80e829fa
DV
4887#define GEN6_UCGCTL1 0x9400
4888# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
de4a8bd1 4889# define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
80e829fa 4890
406478dc 4891#define GEN6_UCGCTL2 0x9404
0f846f81 4892# define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
6edaa7fc 4893# define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
eae66b50 4894# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
406478dc 4895# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
9ca1d10d 4896# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
406478dc 4897
e3f33d46
JB
4898#define GEN7_UCGCTL4 0x940c
4899#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)
4900
3b8d8d91 4901#define GEN6_RPNSWREQ 0xA008
8fd26859
CW
4902#define GEN6_TURBO_DISABLE (1<<31)
4903#define GEN6_FREQUENCY(x) ((x)<<25)
92bd1bf0 4904#define HSW_FREQUENCY(x) ((x)<<24)
8fd26859
CW
4905#define GEN6_OFFSET(x) ((x)<<19)
4906#define GEN6_AGGRESSIVE_TURBO (0<<15)
4907#define GEN6_RC_VIDEO_FREQ 0xA00C
4908#define GEN6_RC_CONTROL 0xA090
4909#define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
4910#define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
4911#define GEN6_RC_CTL_RC6_ENABLE (1<<18)
4912#define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
4913#define GEN6_RC_CTL_RC7_ENABLE (1<<22)
6b88f295 4914#define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24)
0a073b84 4915#define GEN7_RC_CTL_TO_MODE (1<<28)
8fd26859
CW
4916#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
4917#define GEN6_RC_CTL_HW_ENABLE (1<<31)
4918#define GEN6_RP_DOWN_TIMEOUT 0xA010
4919#define GEN6_RP_INTERRUPT_LIMITS 0xA014
3b8d8d91 4920#define GEN6_RPSTAT1 0xA01C
ccab5c82 4921#define GEN6_CAGF_SHIFT 8
f82855d3 4922#define HSW_CAGF_SHIFT 7
ccab5c82 4923#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
f82855d3 4924#define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
8fd26859
CW
4925#define GEN6_RP_CONTROL 0xA024
4926#define GEN6_RP_MEDIA_TURBO (1<<11)
6ed55ee7
BW
4927#define GEN6_RP_MEDIA_MODE_MASK (3<<9)
4928#define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9)
4929#define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9)
4930#define GEN6_RP_MEDIA_HW_MODE (1<<9)
4931#define GEN6_RP_MEDIA_SW_MODE (0<<9)
8fd26859
CW
4932#define GEN6_RP_MEDIA_IS_GFX (1<<8)
4933#define GEN6_RP_ENABLE (1<<7)
ccab5c82
JB
4934#define GEN6_RP_UP_IDLE_MIN (0x1<<3)
4935#define GEN6_RP_UP_BUSY_AVG (0x2<<3)
4936#define GEN6_RP_UP_BUSY_CONT (0x4<<3)
dd75fdc8 4937#define GEN6_RP_DOWN_IDLE_AVG (0x2<<0)
ccab5c82 4938#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
8fd26859
CW
4939#define GEN6_RP_UP_THRESHOLD 0xA02C
4940#define GEN6_RP_DOWN_THRESHOLD 0xA030
ccab5c82
JB
4941#define GEN6_RP_CUR_UP_EI 0xA050
4942#define GEN6_CURICONT_MASK 0xffffff
4943#define GEN6_RP_CUR_UP 0xA054
4944#define GEN6_CURBSYTAVG_MASK 0xffffff
4945#define GEN6_RP_PREV_UP 0xA058
4946#define GEN6_RP_CUR_DOWN_EI 0xA05C
4947#define GEN6_CURIAVG_MASK 0xffffff
4948#define GEN6_RP_CUR_DOWN 0xA060
4949#define GEN6_RP_PREV_DOWN 0xA064
8fd26859
CW
4950#define GEN6_RP_UP_EI 0xA068
4951#define GEN6_RP_DOWN_EI 0xA06C
4952#define GEN6_RP_IDLE_HYSTERSIS 0xA070
4953#define GEN6_RC_STATE 0xA094
4954#define GEN6_RC1_WAKE_RATE_LIMIT 0xA098
4955#define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C
4956#define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0
4957#define GEN6_RC_EVALUATION_INTERVAL 0xA0A8
4958#define GEN6_RC_IDLE_HYSTERSIS 0xA0AC
4959#define GEN6_RC_SLEEP 0xA0B0
4960#define GEN6_RC1e_THRESHOLD 0xA0B4
4961#define GEN6_RC6_THRESHOLD 0xA0B8
4962#define GEN6_RC6p_THRESHOLD 0xA0BC
4963#define GEN6_RC6pp_THRESHOLD 0xA0C0
3b8d8d91 4964#define GEN6_PMINTRMSK 0xA168
8fd26859
CW
4965
4966#define GEN6_PMISR 0x44020
4912d041 4967#define GEN6_PMIMR 0x44024 /* rps_lock */
8fd26859
CW
4968#define GEN6_PMIIR 0x44028
4969#define GEN6_PMIER 0x4402C
4970#define GEN6_PM_MBOX_EVENT (1<<25)
4971#define GEN6_PM_THERMAL_EVENT (1<<24)
4972#define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
4973#define GEN6_PM_RP_UP_THRESHOLD (1<<5)
4974#define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
4975#define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
4976#define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
4848405c 4977#define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
4912d041
BW
4978 GEN6_PM_RP_DOWN_THRESHOLD | \
4979 GEN6_PM_RP_DOWN_TIMEOUT)
8fd26859 4980
76c3552f
D
4981#define VLV_GTLC_SURVIVABILITY_REG 0x130098
4982#define VLV_GFX_CLK_STATUS_BIT (1<<3)
4983#define VLV_GFX_CLK_FORCE_ON_BIT (1<<2)
4984
cce66a28 4985#define GEN6_GT_GFX_RC6_LOCKED 0x138104
49798eb2
JB
4986#define VLV_COUNTER_CONTROL 0x138104
4987#define VLV_COUNT_RANGE_HIGH (1<<15)
4988#define VLV_MEDIA_RC6_COUNT_EN (1<<1)
4989#define VLV_RENDER_RC6_COUNT_EN (1<<0)
cce66a28
BW
4990#define GEN6_GT_GFX_RC6 0x138108
4991#define GEN6_GT_GFX_RC6p 0x13810C
4992#define GEN6_GT_GFX_RC6pp 0x138110
4993
8fd26859
CW
4994#define GEN6_PCODE_MAILBOX 0x138124
4995#define GEN6_PCODE_READY (1<<31)
a6044e23 4996#define GEN6_READ_OC_PARAMS 0xc
23b2f8bb
JB
4997#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
4998#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
31643d54
BW
4999#define GEN6_PCODE_WRITE_RC6VIDS 0x4
5000#define GEN6_PCODE_READ_RC6VIDS 0x5
515b2392
PZ
5001#define GEN6_PCODE_READ_D_COMP 0x10
5002#define GEN6_PCODE_WRITE_D_COMP 0x11
7083e050
BW
5003#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
5004#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
2a114cc1 5005#define DISPLAY_IPS_CONTROL 0x19
8fd26859 5006#define GEN6_PCODE_DATA 0x138128
23b2f8bb 5007#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
3ebecd07 5008#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
8fd26859 5009
4d85529d
BW
5010#define GEN6_GT_CORE_STATUS 0x138060
5011#define GEN6_CORE_CPD_STATE_MASK (7<<4)
5012#define GEN6_RCn_MASK 7
5013#define GEN6_RC0 0
5014#define GEN6_RC3 2
5015#define GEN6_RC6 3
5016#define GEN6_RC7 4
5017
e3689190
BW
5018#define GEN7_MISCCPCTL (0x9424)
5019#define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0)
5020
5021/* IVYBRIDGE DPF */
5022#define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */
35a85ac6 5023#define HSW_L3CDERRST11 0xB208 /* L3CD Error Status register 1 slice 1 */
e3689190
BW
5024#define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
5025#define GEN7_PARITY_ERROR_VALID (1<<13)
5026#define GEN7_L3CDERRST1_BANK_MASK (3<<11)
5027#define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8)
5028#define GEN7_PARITY_ERROR_ROW(reg) \
5029 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
5030#define GEN7_PARITY_ERROR_BANK(reg) \
5031 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
5032#define GEN7_PARITY_ERROR_SUBBANK(reg) \
5033 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
5034#define GEN7_L3CDERRST1_ENABLE (1<<7)
5035
b9524a1e 5036#define GEN7_L3LOG_BASE 0xB070
35a85ac6 5037#define HSW_L3LOG_BASE_SLICE1 0xB270
b9524a1e
BW
5038#define GEN7_L3LOG_SIZE 0x80
5039
12f3382b
JB
5040#define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */
5041#define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100
5042#define GEN7_MAX_PS_THREAD_DEP (8<<12)
4c2e7a5f 5043#define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10)
12f3382b
JB
5044#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3)
5045
8ab43976
JB
5046#define GEN7_ROW_CHICKEN2 0xe4f4
5047#define GEN7_ROW_CHICKEN2_GT2 0xf4f4
5048#define DOP_CLOCK_GATING_DISABLE (1<<0)
5049
f3fc4884
FJ
5050#define HSW_ROW_CHICKEN3 0xe49c
5051#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
5052
fd392b60
BW
5053#define HALF_SLICE_CHICKEN3 0xe184
5054#define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8)
bf66347c 5055#define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
fd392b60 5056
5c969aa7 5057#define G4X_AUD_VID_DID (dev_priv->info.display_mmio_offset + 0x62020)
e0dac65e
WF
5058#define INTEL_AUDIO_DEVCL 0x808629FB
5059#define INTEL_AUDIO_DEVBLC 0x80862801
5060#define INTEL_AUDIO_DEVCTG 0x80862802
5061
5062#define G4X_AUD_CNTL_ST 0x620B4
5063#define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
5064#define G4X_ELDV_DEVCTG (1 << 14)
5065#define G4X_ELD_ADDR (0xf << 5)
5066#define G4X_ELD_ACK (1 << 4)
5067#define G4X_HDMIW_HDMIEDID 0x6210C
5068
1202b4c6 5069#define IBX_HDMIW_HDMIEDID_A 0xE2050
9b138a83
WX
5070#define IBX_HDMIW_HDMIEDID_B 0xE2150
5071#define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
5072 IBX_HDMIW_HDMIEDID_A, \
5073 IBX_HDMIW_HDMIEDID_B)
1202b4c6 5074#define IBX_AUD_CNTL_ST_A 0xE20B4
9b138a83
WX
5075#define IBX_AUD_CNTL_ST_B 0xE21B4
5076#define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
5077 IBX_AUD_CNTL_ST_A, \
5078 IBX_AUD_CNTL_ST_B)
1202b4c6
WF
5079#define IBX_ELD_BUFFER_SIZE (0x1f << 10)
5080#define IBX_ELD_ADDRESS (0x1f << 5)
5081#define IBX_ELD_ACK (1 << 4)
5082#define IBX_AUD_CNTL_ST2 0xE20C0
5083#define IBX_ELD_VALIDB (1 << 0)
5084#define IBX_CP_READYB (1 << 1)
5085
5086#define CPT_HDMIW_HDMIEDID_A 0xE5050
9b138a83
WX
5087#define CPT_HDMIW_HDMIEDID_B 0xE5150
5088#define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
5089 CPT_HDMIW_HDMIEDID_A, \
5090 CPT_HDMIW_HDMIEDID_B)
1202b4c6 5091#define CPT_AUD_CNTL_ST_A 0xE50B4
9b138a83
WX
5092#define CPT_AUD_CNTL_ST_B 0xE51B4
5093#define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
5094 CPT_AUD_CNTL_ST_A, \
5095 CPT_AUD_CNTL_ST_B)
1202b4c6 5096#define CPT_AUD_CNTRL_ST2 0xE50C0
e0dac65e 5097
9ca2fe73
ML
5098#define VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
5099#define VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
5100#define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
5101 VLV_HDMIW_HDMIEDID_A, \
5102 VLV_HDMIW_HDMIEDID_B)
5103#define VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
5104#define VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
5105#define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \
5106 VLV_AUD_CNTL_ST_A, \
5107 VLV_AUD_CNTL_ST_B)
5108#define VLV_AUD_CNTL_ST2 (VLV_DISPLAY_BASE + 0x620C0)
5109
ae662d31
EA
5110/* These are the 4 32-bit write offset registers for each stream
5111 * output buffer. It determines the offset from the
5112 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
5113 */
5114#define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4)
5115
b6daa025 5116#define IBX_AUD_CONFIG_A 0xe2000
9b138a83
WX
5117#define IBX_AUD_CONFIG_B 0xe2100
5118#define IBX_AUD_CFG(pipe) _PIPE(pipe, \
5119 IBX_AUD_CONFIG_A, \
5120 IBX_AUD_CONFIG_B)
b6daa025 5121#define CPT_AUD_CONFIG_A 0xe5000
9b138a83
WX
5122#define CPT_AUD_CONFIG_B 0xe5100
5123#define CPT_AUD_CFG(pipe) _PIPE(pipe, \
5124 CPT_AUD_CONFIG_A, \
5125 CPT_AUD_CONFIG_B)
9ca2fe73
ML
5126#define VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
5127#define VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
5128#define VLV_AUD_CFG(pipe) _PIPE(pipe, \
5129 VLV_AUD_CONFIG_A, \
5130 VLV_AUD_CONFIG_B)
5131
b6daa025
WF
5132#define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
5133#define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
5134#define AUD_CONFIG_UPPER_N_SHIFT 20
5135#define AUD_CONFIG_UPPER_N_VALUE (0xff << 20)
5136#define AUD_CONFIG_LOWER_N_SHIFT 4
5137#define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4)
5138#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
1a91510d
JN
5139#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
5140#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
5141#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
5142#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
5143#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
5144#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
5145#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
5146#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
5147#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
5148#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
5149#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
b6daa025
WF
5150#define AUD_CONFIG_DISABLE_NCTS (1 << 3)
5151
9a78b6cc
WX
5152/* HSW Audio */
5153#define HSW_AUD_CONFIG_A 0x65000 /* Audio Configuration Transcoder A */
5154#define HSW_AUD_CONFIG_B 0x65100 /* Audio Configuration Transcoder B */
5155#define HSW_AUD_CFG(pipe) _PIPE(pipe, \
5156 HSW_AUD_CONFIG_A, \
5157 HSW_AUD_CONFIG_B)
5158
5159#define HSW_AUD_MISC_CTRL_A 0x65010 /* Audio Misc Control Convert 1 */
5160#define HSW_AUD_MISC_CTRL_B 0x65110 /* Audio Misc Control Convert 2 */
5161#define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \
5162 HSW_AUD_MISC_CTRL_A, \
5163 HSW_AUD_MISC_CTRL_B)
5164
5165#define HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 /* Audio DIP and ELD Control State Transcoder A */
5166#define HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 /* Audio DIP and ELD Control State Transcoder B */
5167#define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
5168 HSW_AUD_DIP_ELD_CTRL_ST_A, \
5169 HSW_AUD_DIP_ELD_CTRL_ST_B)
5170
5171/* Audio Digital Converter */
5172#define HSW_AUD_DIG_CNVT_1 0x65080 /* Audio Converter 1 */
5173#define HSW_AUD_DIG_CNVT_2 0x65180 /* Audio Converter 1 */
5174#define AUD_DIG_CNVT(pipe) _PIPE(pipe, \
5175 HSW_AUD_DIG_CNVT_1, \
5176 HSW_AUD_DIG_CNVT_2)
9b138a83 5177#define DIP_PORT_SEL_MASK 0x3
9a78b6cc
WX
5178
5179#define HSW_AUD_EDID_DATA_A 0x65050
5180#define HSW_AUD_EDID_DATA_B 0x65150
5181#define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
5182 HSW_AUD_EDID_DATA_A, \
5183 HSW_AUD_EDID_DATA_B)
5184
5185#define HSW_AUD_PIPE_CONV_CFG 0x6507c /* Audio pipe and converter configs */
5186#define HSW_AUD_PIN_ELD_CP_VLD 0x650c0 /* Audio ELD and CP Ready Status */
5187#define AUDIO_INACTIVE_C (1<<11)
5188#define AUDIO_INACTIVE_B (1<<7)
5189#define AUDIO_INACTIVE_A (1<<3)
5190#define AUDIO_OUTPUT_ENABLE_A (1<<2)
5191#define AUDIO_OUTPUT_ENABLE_B (1<<6)
5192#define AUDIO_OUTPUT_ENABLE_C (1<<10)
5193#define AUDIO_ELD_VALID_A (1<<0)
5194#define AUDIO_ELD_VALID_B (1<<4)
5195#define AUDIO_ELD_VALID_C (1<<8)
5196#define AUDIO_CP_READY_A (1<<1)
5197#define AUDIO_CP_READY_B (1<<5)
5198#define AUDIO_CP_READY_C (1<<9)
5199
9eb3a752 5200/* HSW Power Wells */
fa42e23c
PZ
5201#define HSW_PWR_WELL_BIOS 0x45400 /* CTL1 */
5202#define HSW_PWR_WELL_DRIVER 0x45404 /* CTL2 */
5203#define HSW_PWR_WELL_KVMR 0x45408 /* CTL3 */
5204#define HSW_PWR_WELL_DEBUG 0x4540C /* CTL4 */
6aedd1f5
PZ
5205#define HSW_PWR_WELL_ENABLE_REQUEST (1<<31)
5206#define HSW_PWR_WELL_STATE_ENABLED (1<<30)
5e49cea6 5207#define HSW_PWR_WELL_CTL5 0x45410
9eb3a752
ED
5208#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
5209#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
5e49cea6
PZ
5210#define HSW_PWR_WELL_FORCE_ON (1<<19)
5211#define HSW_PWR_WELL_CTL6 0x45414
9eb3a752 5212
e7e104c3 5213/* Per-pipe DDI Function Control */
ad80a810
PZ
5214#define TRANS_DDI_FUNC_CTL_A 0x60400
5215#define TRANS_DDI_FUNC_CTL_B 0x61400
5216#define TRANS_DDI_FUNC_CTL_C 0x62400
5217#define TRANS_DDI_FUNC_CTL_EDP 0x6F400
a57c774a
AK
5218#define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER2(tran, TRANS_DDI_FUNC_CTL_A)
5219
ad80a810 5220#define TRANS_DDI_FUNC_ENABLE (1<<31)
e7e104c3 5221/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
ad80a810
PZ
5222#define TRANS_DDI_PORT_MASK (7<<28)
5223#define TRANS_DDI_SELECT_PORT(x) ((x)<<28)
5224#define TRANS_DDI_PORT_NONE (0<<28)
5225#define TRANS_DDI_MODE_SELECT_MASK (7<<24)
5226#define TRANS_DDI_MODE_SELECT_HDMI (0<<24)
5227#define TRANS_DDI_MODE_SELECT_DVI (1<<24)
5228#define TRANS_DDI_MODE_SELECT_DP_SST (2<<24)
5229#define TRANS_DDI_MODE_SELECT_DP_MST (3<<24)
5230#define TRANS_DDI_MODE_SELECT_FDI (4<<24)
5231#define TRANS_DDI_BPC_MASK (7<<20)
5232#define TRANS_DDI_BPC_8 (0<<20)
5233#define TRANS_DDI_BPC_10 (1<<20)
5234#define TRANS_DDI_BPC_6 (2<<20)
5235#define TRANS_DDI_BPC_12 (3<<20)
5236#define TRANS_DDI_PVSYNC (1<<17)
5237#define TRANS_DDI_PHSYNC (1<<16)
5238#define TRANS_DDI_EDP_INPUT_MASK (7<<12)
5239#define TRANS_DDI_EDP_INPUT_A_ON (0<<12)
5240#define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12)
5241#define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12)
5242#define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12)
5243#define TRANS_DDI_BFI_ENABLE (1<<4)
e7e104c3 5244
0e87f667
ED
5245/* DisplayPort Transport Control */
5246#define DP_TP_CTL_A 0x64040
5247#define DP_TP_CTL_B 0x64140
5e49cea6
PZ
5248#define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B)
5249#define DP_TP_CTL_ENABLE (1<<31)
5250#define DP_TP_CTL_MODE_SST (0<<27)
5251#define DP_TP_CTL_MODE_MST (1<<27)
0e87f667 5252#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
5e49cea6 5253#define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
0e87f667
ED
5254#define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
5255#define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
5256#define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
d6c0d722
PZ
5257#define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8)
5258#define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8)
5e49cea6 5259#define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
d6c0d722 5260#define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7)
0e87f667 5261
e411b2c1
ED
5262/* DisplayPort Transport Status */
5263#define DP_TP_STATUS_A 0x64044
5264#define DP_TP_STATUS_B 0x64144
5e49cea6 5265#define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)
d6c0d722 5266#define DP_TP_STATUS_IDLE_DONE (1<<25)
e411b2c1
ED
5267#define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
5268
03f896a1
ED
5269/* DDI Buffer Control */
5270#define DDI_BUF_CTL_A 0x64000
5271#define DDI_BUF_CTL_B 0x64100
5e49cea6
PZ
5272#define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
5273#define DDI_BUF_CTL_ENABLE (1<<31)
8f93f4f1 5274/* Haswell */
03f896a1 5275#define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */
5e49cea6 5276#define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */
03f896a1 5277#define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */
5e49cea6 5278#define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */
03f896a1 5279#define DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */
5e49cea6 5280#define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */
03f896a1
ED
5281#define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */
5282#define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */
5e49cea6 5283#define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */
8f93f4f1
PZ
5284/* Broadwell */
5285#define DDI_BUF_EMP_400MV_0DB_BDW (0<<24) /* Sel0 */
5286#define DDI_BUF_EMP_400MV_3_5DB_BDW (1<<24) /* Sel1 */
5287#define DDI_BUF_EMP_400MV_6DB_BDW (2<<24) /* Sel2 */
5288#define DDI_BUF_EMP_600MV_0DB_BDW (3<<24) /* Sel3 */
5289#define DDI_BUF_EMP_600MV_3_5DB_BDW (4<<24) /* Sel4 */
5290#define DDI_BUF_EMP_600MV_6DB_BDW (5<<24) /* Sel5 */
5291#define DDI_BUF_EMP_800MV_0DB_BDW (6<<24) /* Sel6 */
5292#define DDI_BUF_EMP_800MV_3_5DB_BDW (7<<24) /* Sel7 */
5293#define DDI_BUF_EMP_1200MV_0DB_BDW (8<<24) /* Sel8 */
5e49cea6 5294#define DDI_BUF_EMP_MASK (0xf<<24)
876a8cdf 5295#define DDI_BUF_PORT_REVERSAL (1<<16)
5e49cea6 5296#define DDI_BUF_IS_IDLE (1<<7)
79935fca 5297#define DDI_A_4_LANES (1<<4)
17aa6be9 5298#define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
03f896a1
ED
5299#define DDI_INIT_DISPLAY_DETECTED (1<<0)
5300
bb879a44
ED
5301/* DDI Buffer Translations */
5302#define DDI_BUF_TRANS_A 0x64E00
5303#define DDI_BUF_TRANS_B 0x64E60
5e49cea6 5304#define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B)
bb879a44 5305
7501a4d8
ED
5306/* Sideband Interface (SBI) is programmed indirectly, via
5307 * SBI_ADDR, which contains the register offset; and SBI_DATA,
5308 * which contains the payload */
5e49cea6
PZ
5309#define SBI_ADDR 0xC6000
5310#define SBI_DATA 0xC6004
7501a4d8 5311#define SBI_CTL_STAT 0xC6008
988d6ee8
PZ
5312#define SBI_CTL_DEST_ICLK (0x0<<16)
5313#define SBI_CTL_DEST_MPHY (0x1<<16)
5314#define SBI_CTL_OP_IORD (0x2<<8)
5315#define SBI_CTL_OP_IOWR (0x3<<8)
7501a4d8
ED
5316#define SBI_CTL_OP_CRRD (0x6<<8)
5317#define SBI_CTL_OP_CRWR (0x7<<8)
5318#define SBI_RESPONSE_FAIL (0x1<<1)
5e49cea6
PZ
5319#define SBI_RESPONSE_SUCCESS (0x0<<1)
5320#define SBI_BUSY (0x1<<0)
5321#define SBI_READY (0x0<<0)
52f025ef 5322
ccf1c867 5323/* SBI offsets */
5e49cea6 5324#define SBI_SSCDIVINTPHASE6 0x0600
ccf1c867
ED
5325#define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1)
5326#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1)
5327#define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8)
5328#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8)
5e49cea6 5329#define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15)
ccf1c867 5330#define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0)
5e49cea6 5331#define SBI_SSCCTL 0x020c
ccf1c867 5332#define SBI_SSCCTL6 0x060C
dde86e2d 5333#define SBI_SSCCTL_PATHALT (1<<3)
5e49cea6 5334#define SBI_SSCCTL_DISABLE (1<<0)
ccf1c867
ED
5335#define SBI_SSCAUXDIV6 0x0610
5336#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4)
5e49cea6 5337#define SBI_DBUFF0 0x2a00
2fa86a1f
PZ
5338#define SBI_GEN0 0x1f00
5339#define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0)
ccf1c867 5340
52f025ef 5341/* LPT PIXCLK_GATE */
5e49cea6 5342#define PIXCLK_GATE 0xC6020
745ca3be
PZ
5343#define PIXCLK_GATE_UNGATE (1<<0)
5344#define PIXCLK_GATE_GATE (0<<0)
52f025ef 5345
e93ea06a 5346/* SPLL */
5e49cea6 5347#define SPLL_CTL 0x46020
e93ea06a 5348#define SPLL_PLL_ENABLE (1<<31)
39bc66c9
DL
5349#define SPLL_PLL_SSC (1<<28)
5350#define SPLL_PLL_NON_SSC (2<<28)
11578553
JB
5351#define SPLL_PLL_LCPLL (3<<28)
5352#define SPLL_PLL_REF_MASK (3<<28)
5e49cea6
PZ
5353#define SPLL_PLL_FREQ_810MHz (0<<26)
5354#define SPLL_PLL_FREQ_1350MHz (1<<26)
11578553
JB
5355#define SPLL_PLL_FREQ_2700MHz (2<<26)
5356#define SPLL_PLL_FREQ_MASK (3<<26)
e93ea06a 5357
4dffc404 5358/* WRPLL */
5e49cea6
PZ
5359#define WRPLL_CTL1 0x46040
5360#define WRPLL_CTL2 0x46060
5361#define WRPLL_PLL_ENABLE (1<<31)
5362#define WRPLL_PLL_SELECT_SSC (0x01<<28)
39bc66c9 5363#define WRPLL_PLL_SELECT_NON_SSC (0x02<<28)
4dffc404 5364#define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28)
ef4d084f 5365/* WRPLL divider programming */
5e49cea6 5366#define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
11578553 5367#define WRPLL_DIVIDER_REF_MASK (0xff)
5e49cea6 5368#define WRPLL_DIVIDER_POST(x) ((x)<<8)
11578553
JB
5369#define WRPLL_DIVIDER_POST_MASK (0x3f<<8)
5370#define WRPLL_DIVIDER_POST_SHIFT 8
5e49cea6 5371#define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
11578553
JB
5372#define WRPLL_DIVIDER_FB_SHIFT 16
5373#define WRPLL_DIVIDER_FB_MASK (0xff<<16)
4dffc404 5374
fec9181c
ED
5375/* Port clock selection */
5376#define PORT_CLK_SEL_A 0x46100
5377#define PORT_CLK_SEL_B 0x46104
5e49cea6 5378#define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B)
fec9181c
ED
5379#define PORT_CLK_SEL_LCPLL_2700 (0<<29)
5380#define PORT_CLK_SEL_LCPLL_1350 (1<<29)
5381#define PORT_CLK_SEL_LCPLL_810 (2<<29)
5e49cea6 5382#define PORT_CLK_SEL_SPLL (3<<29)
fec9181c
ED
5383#define PORT_CLK_SEL_WRPLL1 (4<<29)
5384#define PORT_CLK_SEL_WRPLL2 (5<<29)
6441ab5f 5385#define PORT_CLK_SEL_NONE (7<<29)
11578553 5386#define PORT_CLK_SEL_MASK (7<<29)
fec9181c 5387
bb523fc0
PZ
5388/* Transcoder clock selection */
5389#define TRANS_CLK_SEL_A 0x46140
5390#define TRANS_CLK_SEL_B 0x46144
5391#define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)
5392/* For each transcoder, we need to select the corresponding port clock */
5393#define TRANS_CLK_SEL_DISABLED (0x0<<29)
5394#define TRANS_CLK_SEL_PORT(x) ((x+1)<<29)
fec9181c 5395
a57c774a
AK
5396#define TRANSA_MSA_MISC 0x60410
5397#define TRANSB_MSA_MISC 0x61410
5398#define TRANSC_MSA_MISC 0x62410
5399#define TRANS_EDP_MSA_MISC 0x6f410
5400#define TRANS_MSA_MISC(tran) _TRANSCODER2(tran, TRANSA_MSA_MISC)
5401
c9809791
PZ
5402#define TRANS_MSA_SYNC_CLK (1<<0)
5403#define TRANS_MSA_6_BPC (0<<5)
5404#define TRANS_MSA_8_BPC (1<<5)
5405#define TRANS_MSA_10_BPC (2<<5)
5406#define TRANS_MSA_12_BPC (3<<5)
5407#define TRANS_MSA_16_BPC (4<<5)
dae84799 5408
90e8d31c 5409/* LCPLL Control */
5e49cea6 5410#define LCPLL_CTL 0x130040
90e8d31c
ED
5411#define LCPLL_PLL_DISABLE (1<<31)
5412#define LCPLL_PLL_LOCK (1<<30)
79f689aa
PZ
5413#define LCPLL_CLK_FREQ_MASK (3<<26)
5414#define LCPLL_CLK_FREQ_450 (0<<26)
e39bf98a
PZ
5415#define LCPLL_CLK_FREQ_54O_BDW (1<<26)
5416#define LCPLL_CLK_FREQ_337_5_BDW (2<<26)
5417#define LCPLL_CLK_FREQ_675_BDW (3<<26)
5e49cea6 5418#define LCPLL_CD_CLOCK_DISABLE (1<<25)
90e8d31c 5419#define LCPLL_CD2X_CLOCK_DISABLE (1<<23)
be256dc7 5420#define LCPLL_POWER_DOWN_ALLOW (1<<22)
79f689aa 5421#define LCPLL_CD_SOURCE_FCLK (1<<21)
be256dc7
PZ
5422#define LCPLL_CD_SOURCE_FCLK_DONE (1<<19)
5423
5424#define D_COMP (MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
5425#define D_COMP_RCOMP_IN_PROGRESS (1<<9)
5426#define D_COMP_COMP_FORCE (1<<8)
5427#define D_COMP_COMP_DISABLE (1<<0)
90e8d31c 5428
69e94b7e
ED
5429/* Pipe WM_LINETIME - watermark line time */
5430#define PIPE_WM_LINETIME_A 0x45270
5431#define PIPE_WM_LINETIME_B 0x45274
5e49cea6
PZ
5432#define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \
5433 PIPE_WM_LINETIME_B)
5434#define PIPE_WM_LINETIME_MASK (0x1ff)
5435#define PIPE_WM_LINETIME_TIME(x) ((x))
69e94b7e 5436#define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16)
5e49cea6 5437#define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16)
96d6e350
ED
5438
5439/* SFUSE_STRAP */
5e49cea6 5440#define SFUSE_STRAP 0xc2014
658ac4c6
DL
5441#define SFUSE_STRAP_FUSE_LOCK (1<<13)
5442#define SFUSE_STRAP_DISPLAY_DISABLED (1<<7)
96d6e350
ED
5443#define SFUSE_STRAP_DDIB_DETECTED (1<<2)
5444#define SFUSE_STRAP_DDIC_DETECTED (1<<1)
5445#define SFUSE_STRAP_DDID_DETECTED (1<<0)
5446
801bcfff
PZ
5447#define WM_MISC 0x45260
5448#define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
5449
1544d9d5
ED
5450#define WM_DBG 0x45280
5451#define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0)
5452#define WM_DBG_DISALLOW_MAXFIFO (1<<1)
5453#define WM_DBG_DISALLOW_SPRITE (1<<2)
5454
86d3efce
VS
5455/* pipe CSC */
5456#define _PIPE_A_CSC_COEFF_RY_GY 0x49010
5457#define _PIPE_A_CSC_COEFF_BY 0x49014
5458#define _PIPE_A_CSC_COEFF_RU_GU 0x49018
5459#define _PIPE_A_CSC_COEFF_BU 0x4901c
5460#define _PIPE_A_CSC_COEFF_RV_GV 0x49020
5461#define _PIPE_A_CSC_COEFF_BV 0x49024
5462#define _PIPE_A_CSC_MODE 0x49028
29a397ba
VS
5463#define CSC_BLACK_SCREEN_OFFSET (1 << 2)
5464#define CSC_POSITION_BEFORE_GAMMA (1 << 1)
5465#define CSC_MODE_YUV_TO_RGB (1 << 0)
86d3efce
VS
5466#define _PIPE_A_CSC_PREOFF_HI 0x49030
5467#define _PIPE_A_CSC_PREOFF_ME 0x49034
5468#define _PIPE_A_CSC_PREOFF_LO 0x49038
5469#define _PIPE_A_CSC_POSTOFF_HI 0x49040
5470#define _PIPE_A_CSC_POSTOFF_ME 0x49044
5471#define _PIPE_A_CSC_POSTOFF_LO 0x49048
5472
5473#define _PIPE_B_CSC_COEFF_RY_GY 0x49110
5474#define _PIPE_B_CSC_COEFF_BY 0x49114
5475#define _PIPE_B_CSC_COEFF_RU_GU 0x49118
5476#define _PIPE_B_CSC_COEFF_BU 0x4911c
5477#define _PIPE_B_CSC_COEFF_RV_GV 0x49120
5478#define _PIPE_B_CSC_COEFF_BV 0x49124
5479#define _PIPE_B_CSC_MODE 0x49128
5480#define _PIPE_B_CSC_PREOFF_HI 0x49130
5481#define _PIPE_B_CSC_PREOFF_ME 0x49134
5482#define _PIPE_B_CSC_PREOFF_LO 0x49138
5483#define _PIPE_B_CSC_POSTOFF_HI 0x49140
5484#define _PIPE_B_CSC_POSTOFF_ME 0x49144
5485#define _PIPE_B_CSC_POSTOFF_LO 0x49148
5486
86d3efce
VS
5487#define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
5488#define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
5489#define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
5490#define PIPE_CSC_COEFF_BU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
5491#define PIPE_CSC_COEFF_RV_GV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
5492#define PIPE_CSC_COEFF_BV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
5493#define PIPE_CSC_MODE(pipe) _PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
5494#define PIPE_CSC_PREOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
5495#define PIPE_CSC_PREOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
5496#define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
5497#define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
5498#define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
5499#define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
5500
3230bf14
JN
5501/* VLV MIPI registers */
5502
5503#define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
5504#define _MIPIB_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
5505#define MIPI_PORT_CTRL(pipe) _PIPE(pipe, _MIPIA_PORT_CTRL, _MIPIB_PORT_CTRL)
5506#define DPI_ENABLE (1 << 31) /* A + B */
5507#define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
5508#define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
5509#define DUAL_LINK_MODE_MASK (1 << 26)
5510#define DUAL_LINK_MODE_FRONT_BACK (0 << 26)
5511#define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26)
5512#define DITHERING_ENABLE (1 << 25) /* A + B */
5513#define FLOPPED_HSTX (1 << 23)
5514#define DE_INVERT (1 << 19) /* XXX */
5515#define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18
5516#define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18)
5517#define AFE_LATCHOUT (1 << 17)
5518#define LP_OUTPUT_HOLD (1 << 16)
5519#define MIPIB_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15
5520#define MIPIB_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15)
5521#define MIPIB_MIPI4DPHY_DELAY_COUNT_SHIFT 11
5522#define MIPIB_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11)
5523#define CSB_SHIFT 9
5524#define CSB_MASK (3 << 9)
5525#define CSB_20MHZ (0 << 9)
5526#define CSB_10MHZ (1 << 9)
5527#define CSB_40MHZ (2 << 9)
5528#define BANDGAP_MASK (1 << 8)
5529#define BANDGAP_PNW_CIRCUIT (0 << 8)
5530#define BANDGAP_LNC_CIRCUIT (1 << 8)
5531#define MIPIB_FLISDSI_DELAY_COUNT_LOW_SHIFT 5
5532#define MIPIB_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5)
5533#define TEARING_EFFECT_DELAY (1 << 4) /* A + B */
5534#define TEARING_EFFECT_SHIFT 2 /* A + B */
5535#define TEARING_EFFECT_MASK (3 << 2)
5536#define TEARING_EFFECT_OFF (0 << 2)
5537#define TEARING_EFFECT_DSI (1 << 2)
5538#define TEARING_EFFECT_GPIO (2 << 2)
5539#define LANE_CONFIGURATION_SHIFT 0
5540#define LANE_CONFIGURATION_MASK (3 << 0)
5541#define LANE_CONFIGURATION_4LANE (0 << 0)
5542#define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0)
5543#define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0)
5544
5545#define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
5546#define _MIPIB_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
5547#define MIPI_TEARING_CTRL(pipe) _PIPE(pipe, _MIPIA_TEARING_CTRL, _MIPIB_TEARING_CTRL)
5548#define TEARING_EFFECT_DELAY_SHIFT 0
5549#define TEARING_EFFECT_DELAY_MASK (0xffff << 0)
5550
5551/* XXX: all bits reserved */
5552#define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)
5553
5554/* MIPI DSI Controller and D-PHY registers */
5555
5556#define _MIPIA_DEVICE_READY (VLV_DISPLAY_BASE + 0xb000)
5557#define _MIPIB_DEVICE_READY (VLV_DISPLAY_BASE + 0xb800)
5558#define MIPI_DEVICE_READY(pipe) _PIPE(pipe, _MIPIA_DEVICE_READY, _MIPIB_DEVICE_READY)
5559#define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
5560#define ULPS_STATE_MASK (3 << 1)
5561#define ULPS_STATE_ENTER (2 << 1)
5562#define ULPS_STATE_EXIT (1 << 1)
5563#define ULPS_STATE_NORMAL_OPERATION (0 << 1)
5564#define DEVICE_READY (1 << 0)
5565
5566#define _MIPIA_INTR_STAT (VLV_DISPLAY_BASE + 0xb004)
5567#define _MIPIB_INTR_STAT (VLV_DISPLAY_BASE + 0xb804)
5568#define MIPI_INTR_STAT(pipe) _PIPE(pipe, _MIPIA_INTR_STAT, _MIPIB_INTR_STAT)
5569#define _MIPIA_INTR_EN (VLV_DISPLAY_BASE + 0xb008)
5570#define _MIPIB_INTR_EN (VLV_DISPLAY_BASE + 0xb808)
5571#define MIPI_INTR_EN(pipe) _PIPE(pipe, _MIPIA_INTR_EN, _MIPIB_INTR_EN)
5572#define TEARING_EFFECT (1 << 31)
5573#define SPL_PKT_SENT_INTERRUPT (1 << 30)
5574#define GEN_READ_DATA_AVAIL (1 << 29)
5575#define LP_GENERIC_WR_FIFO_FULL (1 << 28)
5576#define HS_GENERIC_WR_FIFO_FULL (1 << 27)
5577#define RX_PROT_VIOLATION (1 << 26)
5578#define RX_INVALID_TX_LENGTH (1 << 25)
5579#define ACK_WITH_NO_ERROR (1 << 24)
5580#define TURN_AROUND_ACK_TIMEOUT (1 << 23)
5581#define LP_RX_TIMEOUT (1 << 22)
5582#define HS_TX_TIMEOUT (1 << 21)
5583#define DPI_FIFO_UNDERRUN (1 << 20)
5584#define LOW_CONTENTION (1 << 19)
5585#define HIGH_CONTENTION (1 << 18)
5586#define TXDSI_VC_ID_INVALID (1 << 17)
5587#define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16)
5588#define TXCHECKSUM_ERROR (1 << 15)
5589#define TXECC_MULTIBIT_ERROR (1 << 14)
5590#define TXECC_SINGLE_BIT_ERROR (1 << 13)
5591#define TXFALSE_CONTROL_ERROR (1 << 12)
5592#define RXDSI_VC_ID_INVALID (1 << 11)
5593#define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10)
5594#define RXCHECKSUM_ERROR (1 << 9)
5595#define RXECC_MULTIBIT_ERROR (1 << 8)
5596#define RXECC_SINGLE_BIT_ERROR (1 << 7)
5597#define RXFALSE_CONTROL_ERROR (1 << 6)
5598#define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5)
5599#define RX_LP_TX_SYNC_ERROR (1 << 4)
5600#define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3)
5601#define RXEOT_SYNC_ERROR (1 << 2)
5602#define RXSOT_SYNC_ERROR (1 << 1)
5603#define RXSOT_ERROR (1 << 0)
5604
5605#define _MIPIA_DSI_FUNC_PRG (VLV_DISPLAY_BASE + 0xb00c)
5606#define _MIPIB_DSI_FUNC_PRG (VLV_DISPLAY_BASE + 0xb80c)
5607#define MIPI_DSI_FUNC_PRG(pipe) _PIPE(pipe, _MIPIA_DSI_FUNC_PRG, _MIPIB_DSI_FUNC_PRG)
5608#define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
5609#define CMD_MODE_NOT_SUPPORTED (0 << 13)
5610#define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13)
5611#define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13)
5612#define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13)
5613#define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13)
5614#define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13)
5615#define VID_MODE_FORMAT_MASK (0xf << 7)
5616#define VID_MODE_NOT_SUPPORTED (0 << 7)
5617#define VID_MODE_FORMAT_RGB565 (1 << 7)
5618#define VID_MODE_FORMAT_RGB666 (2 << 7)
5619#define VID_MODE_FORMAT_RGB666_LOOSE (3 << 7)
5620#define VID_MODE_FORMAT_RGB888 (4 << 7)
5621#define CMD_MODE_CHANNEL_NUMBER_SHIFT 5
5622#define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5)
5623#define VID_MODE_CHANNEL_NUMBER_SHIFT 3
5624#define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3)
5625#define DATA_LANES_PRG_REG_SHIFT 0
5626#define DATA_LANES_PRG_REG_MASK (7 << 0)
5627
5628#define _MIPIA_HS_TX_TIMEOUT (VLV_DISPLAY_BASE + 0xb010)
5629#define _MIPIB_HS_TX_TIMEOUT (VLV_DISPLAY_BASE + 0xb810)
5630#define MIPI_HS_TX_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_HS_TX_TIMEOUT, _MIPIB_HS_TX_TIMEOUT)
5631#define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
5632
5633#define _MIPIA_LP_RX_TIMEOUT (VLV_DISPLAY_BASE + 0xb014)
5634#define _MIPIB_LP_RX_TIMEOUT (VLV_DISPLAY_BASE + 0xb814)
5635#define MIPI_LP_RX_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_LP_RX_TIMEOUT, _MIPIB_LP_RX_TIMEOUT)
5636#define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
5637
5638#define _MIPIA_TURN_AROUND_TIMEOUT (VLV_DISPLAY_BASE + 0xb018)
5639#define _MIPIB_TURN_AROUND_TIMEOUT (VLV_DISPLAY_BASE + 0xb818)
5640#define MIPI_TURN_AROUND_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIB_TURN_AROUND_TIMEOUT)
5641#define TURN_AROUND_TIMEOUT_MASK 0x3f
5642
5643#define _MIPIA_DEVICE_RESET_TIMER (VLV_DISPLAY_BASE + 0xb01c)
5644#define _MIPIB_DEVICE_RESET_TIMER (VLV_DISPLAY_BASE + 0xb81c)
5645#define MIPI_DEVICE_RESET_TIMER(pipe) _PIPE(pipe, _MIPIA_DEVICE_RESET_TIMER, _MIPIB_DEVICE_RESET_TIMER)
5646#define DEVICE_RESET_TIMER_MASK 0xffff
5647
5648#define _MIPIA_DPI_RESOLUTION (VLV_DISPLAY_BASE + 0xb020)
5649#define _MIPIB_DPI_RESOLUTION (VLV_DISPLAY_BASE + 0xb820)
5650#define MIPI_DPI_RESOLUTION(pipe) _PIPE(pipe, _MIPIA_DPI_RESOLUTION, _MIPIB_DPI_RESOLUTION)
5651#define VERTICAL_ADDRESS_SHIFT 16
5652#define VERTICAL_ADDRESS_MASK (0xffff << 16)
5653#define HORIZONTAL_ADDRESS_SHIFT 0
5654#define HORIZONTAL_ADDRESS_MASK 0xffff
5655
5656#define _MIPIA_DBI_FIFO_THROTTLE (VLV_DISPLAY_BASE + 0xb024)
5657#define _MIPIB_DBI_FIFO_THROTTLE (VLV_DISPLAY_BASE + 0xb824)
5658#define MIPI_DBI_FIFO_THROTTLE(pipe) _PIPE(pipe, _MIPIA_DBI_FIFO_THROTTLE, _MIPIB_DBI_FIFO_THROTTLE)
5659#define DBI_FIFO_EMPTY_HALF (0 << 0)
5660#define DBI_FIFO_EMPTY_QUARTER (1 << 0)
5661#define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
5662
5663/* regs below are bits 15:0 */
5664#define _MIPIA_HSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb028)
5665#define _MIPIB_HSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb828)
5666#define MIPI_HSYNC_PADDING_COUNT(pipe) _PIPE(pipe, _MIPIA_HSYNC_PADDING_COUNT, _MIPIB_HSYNC_PADDING_COUNT)
5667
5668#define _MIPIA_HBP_COUNT (VLV_DISPLAY_BASE + 0xb02c)
5669#define _MIPIB_HBP_COUNT (VLV_DISPLAY_BASE + 0xb82c)
5670#define MIPI_HBP_COUNT(pipe) _PIPE(pipe, _MIPIA_HBP_COUNT, _MIPIB_HBP_COUNT)
5671
5672#define _MIPIA_HFP_COUNT (VLV_DISPLAY_BASE + 0xb030)
5673#define _MIPIB_HFP_COUNT (VLV_DISPLAY_BASE + 0xb830)
5674#define MIPI_HFP_COUNT(pipe) _PIPE(pipe, _MIPIA_HFP_COUNT, _MIPIB_HFP_COUNT)
5675
5676#define _MIPIA_HACTIVE_AREA_COUNT (VLV_DISPLAY_BASE + 0xb034)
5677#define _MIPIB_HACTIVE_AREA_COUNT (VLV_DISPLAY_BASE + 0xb834)
5678#define MIPI_HACTIVE_AREA_COUNT(pipe) _PIPE(pipe, _MIPIA_HACTIVE_AREA_COUNT, _MIPIB_HACTIVE_AREA_COUNT)
5679
5680#define _MIPIA_VSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb038)
5681#define _MIPIB_VSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb838)
5682#define MIPI_VSYNC_PADDING_COUNT(pipe) _PIPE(pipe, _MIPIA_VSYNC_PADDING_COUNT, _MIPIB_VSYNC_PADDING_COUNT)
5683
5684#define _MIPIA_VBP_COUNT (VLV_DISPLAY_BASE + 0xb03c)
5685#define _MIPIB_VBP_COUNT (VLV_DISPLAY_BASE + 0xb83c)
5686#define MIPI_VBP_COUNT(pipe) _PIPE(pipe, _MIPIA_VBP_COUNT, _MIPIB_VBP_COUNT)
5687
5688#define _MIPIA_VFP_COUNT (VLV_DISPLAY_BASE + 0xb040)
5689#define _MIPIB_VFP_COUNT (VLV_DISPLAY_BASE + 0xb840)
5690#define MIPI_VFP_COUNT(pipe) _PIPE(pipe, _MIPIA_VFP_COUNT, _MIPIB_VFP_COUNT)
5691
5692#define _MIPIA_HIGH_LOW_SWITCH_COUNT (VLV_DISPLAY_BASE + 0xb044)
5693#define _MIPIB_HIGH_LOW_SWITCH_COUNT (VLV_DISPLAY_BASE + 0xb844)
5694#define MIPI_HIGH_LOW_SWITCH_COUNT(pipe) _PIPE(pipe, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIB_HIGH_LOW_SWITCH_COUNT)
5695/* regs above are bits 15:0 */
5696
5697#define _MIPIA_DPI_CONTROL (VLV_DISPLAY_BASE + 0xb048)
5698#define _MIPIB_DPI_CONTROL (VLV_DISPLAY_BASE + 0xb848)
5699#define MIPI_DPI_CONTROL(pipe) _PIPE(pipe, _MIPIA_DPI_CONTROL, _MIPIB_DPI_CONTROL)
5700#define DPI_LP_MODE (1 << 6)
5701#define BACKLIGHT_OFF (1 << 5)
5702#define BACKLIGHT_ON (1 << 4)
5703#define COLOR_MODE_OFF (1 << 3)
5704#define COLOR_MODE_ON (1 << 2)
5705#define TURN_ON (1 << 1)
5706#define SHUTDOWN (1 << 0)
5707
5708#define _MIPIA_DPI_DATA (VLV_DISPLAY_BASE + 0xb04c)
5709#define _MIPIB_DPI_DATA (VLV_DISPLAY_BASE + 0xb84c)
5710#define MIPI_DPI_DATA(pipe) _PIPE(pipe, _MIPIA_DPI_DATA, _MIPIB_DPI_DATA)
5711#define COMMAND_BYTE_SHIFT 0
5712#define COMMAND_BYTE_MASK (0x3f << 0)
5713
5714#define _MIPIA_INIT_COUNT (VLV_DISPLAY_BASE + 0xb050)
5715#define _MIPIB_INIT_COUNT (VLV_DISPLAY_BASE + 0xb850)
5716#define MIPI_INIT_COUNT(pipe) _PIPE(pipe, _MIPIA_INIT_COUNT, _MIPIB_INIT_COUNT)
5717#define MASTER_INIT_TIMER_SHIFT 0
5718#define MASTER_INIT_TIMER_MASK (0xffff << 0)
5719
5720#define _MIPIA_MAX_RETURN_PKT_SIZE (VLV_DISPLAY_BASE + 0xb054)
5721#define _MIPIB_MAX_RETURN_PKT_SIZE (VLV_DISPLAY_BASE + 0xb854)
5722#define MIPI_MAX_RETURN_PKT_SIZE(pipe) _PIPE(pipe, _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIB_MAX_RETURN_PKT_SIZE)
5723#define MAX_RETURN_PKT_SIZE_SHIFT 0
5724#define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
5725
5726#define _MIPIA_VIDEO_MODE_FORMAT (VLV_DISPLAY_BASE + 0xb058)
5727#define _MIPIB_VIDEO_MODE_FORMAT (VLV_DISPLAY_BASE + 0xb858)
5728#define MIPI_VIDEO_MODE_FORMAT(pipe) _PIPE(pipe, _MIPIA_VIDEO_MODE_FORMAT, _MIPIB_VIDEO_MODE_FORMAT)
5729#define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
5730#define DISABLE_VIDEO_BTA (1 << 3)
5731#define IP_TG_CONFIG (1 << 2)
5732#define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0)
5733#define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
5734#define VIDEO_MODE_BURST (3 << 0)
5735
5736#define _MIPIA_EOT_DISABLE (VLV_DISPLAY_BASE + 0xb05c)
5737#define _MIPIB_EOT_DISABLE (VLV_DISPLAY_BASE + 0xb85c)
5738#define MIPI_EOT_DISABLE(pipe) _PIPE(pipe, _MIPIA_EOT_DISABLE, _MIPIB_EOT_DISABLE)
5739#define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7)
5740#define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6)
5741#define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5)
5742#define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4)
5743#define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
5744#define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2)
5745#define CLOCKSTOP (1 << 1)
5746#define EOT_DISABLE (1 << 0)
5747
5748#define _MIPIA_LP_BYTECLK (VLV_DISPLAY_BASE + 0xb060)
5749#define _MIPIB_LP_BYTECLK (VLV_DISPLAY_BASE + 0xb860)
5750#define MIPI_LP_BYTECLK(pipe) _PIPE(pipe, _MIPIA_LP_BYTECLK, _MIPIB_LP_BYTECLK)
5751#define LP_BYTECLK_SHIFT 0
5752#define LP_BYTECLK_MASK (0xffff << 0)
5753
5754/* bits 31:0 */
5755#define _MIPIA_LP_GEN_DATA (VLV_DISPLAY_BASE + 0xb064)
5756#define _MIPIB_LP_GEN_DATA (VLV_DISPLAY_BASE + 0xb864)
5757#define MIPI_LP_GEN_DATA(pipe) _PIPE(pipe, _MIPIA_LP_GEN_DATA, _MIPIB_LP_GEN_DATA)
5758
5759/* bits 31:0 */
5760#define _MIPIA_HS_GEN_DATA (VLV_DISPLAY_BASE + 0xb068)
5761#define _MIPIB_HS_GEN_DATA (VLV_DISPLAY_BASE + 0xb868)
5762#define MIPI_HS_GEN_DATA(pipe) _PIPE(pipe, _MIPIA_HS_GEN_DATA, _MIPIB_HS_GEN_DATA)
5763
5764#define _MIPIA_LP_GEN_CTRL (VLV_DISPLAY_BASE + 0xb06c)
5765#define _MIPIB_LP_GEN_CTRL (VLV_DISPLAY_BASE + 0xb86c)
5766#define MIPI_LP_GEN_CTRL(pipe) _PIPE(pipe, _MIPIA_LP_GEN_CTRL, _MIPIB_LP_GEN_CTRL)
5767#define _MIPIA_HS_GEN_CTRL (VLV_DISPLAY_BASE + 0xb070)
5768#define _MIPIB_HS_GEN_CTRL (VLV_DISPLAY_BASE + 0xb870)
5769#define MIPI_HS_GEN_CTRL(pipe) _PIPE(pipe, _MIPIA_HS_GEN_CTRL, _MIPIB_HS_GEN_CTRL)
5770#define LONG_PACKET_WORD_COUNT_SHIFT 8
5771#define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
5772#define SHORT_PACKET_PARAM_SHIFT 8
5773#define SHORT_PACKET_PARAM_MASK (0xffff << 8)
5774#define VIRTUAL_CHANNEL_SHIFT 6
5775#define VIRTUAL_CHANNEL_MASK (3 << 6)
5776#define DATA_TYPE_SHIFT 0
5777#define DATA_TYPE_MASK (3f << 0)
5778/* data type values, see include/video/mipi_display.h */
5779
5780#define _MIPIA_GEN_FIFO_STAT (VLV_DISPLAY_BASE + 0xb074)
5781#define _MIPIB_GEN_FIFO_STAT (VLV_DISPLAY_BASE + 0xb874)
5782#define MIPI_GEN_FIFO_STAT(pipe) _PIPE(pipe, _MIPIA_GEN_FIFO_STAT, _MIPIB_GEN_FIFO_STAT)
5783#define DPI_FIFO_EMPTY (1 << 28)
5784#define DBI_FIFO_EMPTY (1 << 27)
5785#define LP_CTRL_FIFO_EMPTY (1 << 26)
5786#define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
5787#define LP_CTRL_FIFO_FULL (1 << 24)
5788#define HS_CTRL_FIFO_EMPTY (1 << 18)
5789#define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
5790#define HS_CTRL_FIFO_FULL (1 << 16)
5791#define LP_DATA_FIFO_EMPTY (1 << 10)
5792#define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
5793#define LP_DATA_FIFO_FULL (1 << 8)
5794#define HS_DATA_FIFO_EMPTY (1 << 2)
5795#define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
5796#define HS_DATA_FIFO_FULL (1 << 0)
5797
5798#define _MIPIA_HS_LS_DBI_ENABLE (VLV_DISPLAY_BASE + 0xb078)
5799#define _MIPIB_HS_LS_DBI_ENABLE (VLV_DISPLAY_BASE + 0xb878)
5800#define MIPI_HS_LP_DBI_ENABLE(pipe) _PIPE(pipe, _MIPIA_HS_LS_DBI_ENABLE, _MIPIB_HS_LS_DBI_ENABLE)
5801#define DBI_HS_LP_MODE_MASK (1 << 0)
5802#define DBI_LP_MODE (1 << 0)
5803#define DBI_HS_MODE (0 << 0)
5804
5805#define _MIPIA_DPHY_PARAM (VLV_DISPLAY_BASE + 0xb080)
5806#define _MIPIB_DPHY_PARAM (VLV_DISPLAY_BASE + 0xb880)
5807#define MIPI_DPHY_PARAM(pipe) _PIPE(pipe, _MIPIA_DPHY_PARAM, _MIPIB_DPHY_PARAM)
5808#define EXIT_ZERO_COUNT_SHIFT 24
5809#define EXIT_ZERO_COUNT_MASK (0x3f << 24)
5810#define TRAIL_COUNT_SHIFT 16
5811#define TRAIL_COUNT_MASK (0x1f << 16)
5812#define CLK_ZERO_COUNT_SHIFT 8
5813#define CLK_ZERO_COUNT_MASK (0xff << 8)
5814#define PREPARE_COUNT_SHIFT 0
5815#define PREPARE_COUNT_MASK (0x3f << 0)
5816
5817/* bits 31:0 */
5818#define _MIPIA_DBI_BW_CTRL (VLV_DISPLAY_BASE + 0xb084)
5819#define _MIPIB_DBI_BW_CTRL (VLV_DISPLAY_BASE + 0xb884)
5820#define MIPI_DBI_BW_CTRL(pipe) _PIPE(pipe, _MIPIA_DBI_BW_CTRL, _MIPIB_DBI_BW_CTRL)
5821
5822#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (VLV_DISPLAY_BASE + 0xb088)
5823#define _MIPIB_CLK_LANE_SWITCH_TIME_CNT (VLV_DISPLAY_BASE + 0xb888)
5824#define MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe) _PIPE(pipe, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIB_CLK_LANE_SWITCH_TIME_CNT)
5825#define LP_HS_SSW_CNT_SHIFT 16
5826#define LP_HS_SSW_CNT_MASK (0xffff << 16)
5827#define HS_LP_PWR_SW_CNT_SHIFT 0
5828#define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
5829
5830#define _MIPIA_STOP_STATE_STALL (VLV_DISPLAY_BASE + 0xb08c)
5831#define _MIPIB_STOP_STATE_STALL (VLV_DISPLAY_BASE + 0xb88c)
5832#define MIPI_STOP_STATE_STALL(pipe) _PIPE(pipe, _MIPIA_STOP_STATE_STALL, _MIPIB_STOP_STATE_STALL)
5833#define STOP_STATE_STALL_COUNTER_SHIFT 0
5834#define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
5835
5836#define _MIPIA_INTR_STAT_REG_1 (VLV_DISPLAY_BASE + 0xb090)
5837#define _MIPIB_INTR_STAT_REG_1 (VLV_DISPLAY_BASE + 0xb890)
5838#define MIPI_INTR_STAT_REG_1(pipe) _PIPE(pipe, _MIPIA_INTR_STAT_REG_1, _MIPIB_INTR_STAT_REG_1)
5839#define _MIPIA_INTR_EN_REG_1 (VLV_DISPLAY_BASE + 0xb094)
5840#define _MIPIB_INTR_EN_REG_1 (VLV_DISPLAY_BASE + 0xb894)
5841#define MIPI_INTR_EN_REG_1(pipe) _PIPE(pipe, _MIPIA_INTR_EN_REG_1, _MIPIB_INTR_EN_REG_1)
5842#define RX_CONTENTION_DETECTED (1 << 0)
5843
5844/* XXX: only pipe A ?!? */
5845#define MIPIA_DBI_TYPEC_CTRL (VLV_DISPLAY_BASE + 0xb100)
5846#define DBI_TYPEC_ENABLE (1 << 31)
5847#define DBI_TYPEC_WIP (1 << 30)
5848#define DBI_TYPEC_OPTION_SHIFT 28
5849#define DBI_TYPEC_OPTION_MASK (3 << 28)
5850#define DBI_TYPEC_FREQ_SHIFT 24
5851#define DBI_TYPEC_FREQ_MASK (0xf << 24)
5852#define DBI_TYPEC_OVERRIDE (1 << 8)
5853#define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0
5854#define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0)
5855
5856
5857/* MIPI adapter registers */
5858
5859#define _MIPIA_CTRL (VLV_DISPLAY_BASE + 0xb104)
5860#define _MIPIB_CTRL (VLV_DISPLAY_BASE + 0xb904)
5861#define MIPI_CTRL(pipe) _PIPE(pipe, _MIPIA_CTRL, _MIPIB_CTRL)
5862#define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
5863#define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
5864#define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
5865#define ESCAPE_CLOCK_DIVIDER_2 (1 << 5)
5866#define ESCAPE_CLOCK_DIVIDER_4 (2 << 5)
5867#define READ_REQUEST_PRIORITY_SHIFT 3
5868#define READ_REQUEST_PRIORITY_MASK (3 << 3)
5869#define READ_REQUEST_PRIORITY_LOW (0 << 3)
5870#define READ_REQUEST_PRIORITY_HIGH (3 << 3)
5871#define RGB_FLIP_TO_BGR (1 << 2)
5872
5873#define _MIPIA_DATA_ADDRESS (VLV_DISPLAY_BASE + 0xb108)
5874#define _MIPIB_DATA_ADDRESS (VLV_DISPLAY_BASE + 0xb908)
5875#define MIPI_DATA_ADDRESS(pipe) _PIPE(pipe, _MIPIA_DATA_ADDRESS, _MIPIB_DATA_ADDRESS)
5876#define DATA_MEM_ADDRESS_SHIFT 5
5877#define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
5878#define DATA_VALID (1 << 0)
5879
5880#define _MIPIA_DATA_LENGTH (VLV_DISPLAY_BASE + 0xb10c)
5881#define _MIPIB_DATA_LENGTH (VLV_DISPLAY_BASE + 0xb90c)
5882#define MIPI_DATA_LENGTH(pipe) _PIPE(pipe, _MIPIA_DATA_LENGTH, _MIPIB_DATA_LENGTH)
5883#define DATA_LENGTH_SHIFT 0
5884#define DATA_LENGTH_MASK (0xfffff << 0)
5885
5886#define _MIPIA_COMMAND_ADDRESS (VLV_DISPLAY_BASE + 0xb110)
5887#define _MIPIB_COMMAND_ADDRESS (VLV_DISPLAY_BASE + 0xb910)
5888#define MIPI_COMMAND_ADDRESS(pipe) _PIPE(pipe, _MIPIA_COMMAND_ADDRESS, _MIPIB_COMMAND_ADDRESS)
5889#define COMMAND_MEM_ADDRESS_SHIFT 5
5890#define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
5891#define AUTO_PWG_ENABLE (1 << 2)
5892#define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
5893#define COMMAND_VALID (1 << 0)
5894
5895#define _MIPIA_COMMAND_LENGTH (VLV_DISPLAY_BASE + 0xb114)
5896#define _MIPIB_COMMAND_LENGTH (VLV_DISPLAY_BASE + 0xb914)
5897#define MIPI_COMMAND_LENGTH(pipe) _PIPE(pipe, _MIPIA_COMMAND_LENGTH, _MIPIB_COMMAND_LENGTH)
5898#define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */
5899#define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
5900
5901#define _MIPIA_READ_DATA_RETURN0 (VLV_DISPLAY_BASE + 0xb118)
5902#define _MIPIB_READ_DATA_RETURN0 (VLV_DISPLAY_BASE + 0xb918)
5903#define MIPI_READ_DATA_RETURN(pipe, n) \
5904 (_PIPE(pipe, _MIPIA_READ_DATA_RETURN0, _MIPIB_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
5905
5906#define _MIPIA_READ_DATA_VALID (VLV_DISPLAY_BASE + 0xb138)
5907#define _MIPIB_READ_DATA_VALID (VLV_DISPLAY_BASE + 0xb938)
5908#define MIPI_READ_DATA_VALID(pipe) _PIPE(pipe, _MIPIA_READ_DATA_VALID, _MIPIB_READ_DATA_VALID)
5909#define READ_DATA_VALID(n) (1 << (n))
5910
a57c774a 5911/* For UMS only (deprecated): */
5c969aa7
DL
5912#define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
5913#define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
5914#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
5915#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
5916#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
5917#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
a57c774a 5918
585fb111 5919#endif /* _I915_REG_H_ */