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585fb111 JB |
1 | /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
2 | * All Rights Reserved. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the | |
6 | * "Software"), to deal in the Software without restriction, including | |
7 | * without limitation the rights to use, copy, modify, merge, publish, | |
8 | * distribute, sub license, and/or sell copies of the Software, and to | |
9 | * permit persons to whom the Software is furnished to do so, subject to | |
10 | * the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the | |
13 | * next paragraph) shall be included in all copies or substantial portions | |
14 | * of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
19 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
20 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
21 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
22 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #ifndef _I915_REG_H_ | |
26 | #define _I915_REG_H_ | |
27 | ||
1aa920ea JN |
28 | /** |
29 | * DOC: The i915 register macro definition style guide | |
30 | * | |
31 | * Follow the style described here for new macros, and while changing existing | |
32 | * macros. Do **not** mass change existing definitions just to update the style. | |
33 | * | |
34 | * Layout | |
35 | * '''''' | |
36 | * | |
37 | * Keep helper macros near the top. For example, _PIPE() and friends. | |
38 | * | |
39 | * Prefix macros that generally should not be used outside of this file with | |
40 | * underscore '_'. For example, _PIPE() and friends, single instances of | |
41 | * registers that are defined solely for the use by function-like macros. | |
42 | * | |
43 | * Avoid using the underscore prefixed macros outside of this file. There are | |
44 | * exceptions, but keep them to a minimum. | |
45 | * | |
46 | * There are two basic types of register definitions: Single registers and | |
47 | * register groups. Register groups are registers which have two or more | |
48 | * instances, for example one per pipe, port, transcoder, etc. Register groups | |
49 | * should be defined using function-like macros. | |
50 | * | |
51 | * For single registers, define the register offset first, followed by register | |
52 | * contents. | |
53 | * | |
54 | * For register groups, define the register instance offsets first, prefixed | |
55 | * with underscore, followed by a function-like macro choosing the right | |
56 | * instance based on the parameter, followed by register contents. | |
57 | * | |
58 | * Define the register contents (i.e. bit and bit field macros) from most | |
59 | * significant to least significant bit. Indent the register content macros | |
60 | * using two extra spaces between ``#define`` and the macro name. | |
61 | * | |
62 | * For bit fields, define a ``_MASK`` and a ``_SHIFT`` macro. Define bit field | |
63 | * contents so that they are already shifted in place, and can be directly | |
64 | * OR'd. For convenience, function-like macros may be used to define bit fields, | |
65 | * but do note that the macros may be needed to read as well as write the | |
66 | * register contents. | |
67 | * | |
68 | * Define bits using ``(1 << N)`` instead of ``BIT(N)``. We may change this in | |
69 | * the future, but this is the prevailing style. Do **not** add ``_BIT`` suffix | |
70 | * to the name. | |
71 | * | |
72 | * Group the register and its contents together without blank lines, separate | |
73 | * from other registers and their contents with one blank line. | |
74 | * | |
75 | * Indent macro values from macro names using TABs. Align values vertically. Use | |
76 | * braces in macro values as needed to avoid unintended precedence after macro | |
77 | * substitution. Use spaces in macro values according to kernel coding | |
78 | * style. Use lower case in hexadecimal values. | |
79 | * | |
80 | * Naming | |
81 | * '''''' | |
82 | * | |
83 | * Try to name registers according to the specs. If the register name changes in | |
84 | * the specs from platform to another, stick to the original name. | |
85 | * | |
86 | * Try to re-use existing register macro definitions. Only add new macros for | |
87 | * new register offsets, or when the register contents have changed enough to | |
88 | * warrant a full redefinition. | |
89 | * | |
90 | * When a register macro changes for a new platform, prefix the new macro using | |
91 | * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The | |
92 | * prefix signifies the start platform/generation using the register. | |
93 | * | |
94 | * When a bit (field) macro changes or gets added for a new platform, while | |
95 | * retaining the existing register macro, add a platform acronym or generation | |
96 | * suffix to the name. For example, ``_SKL`` or ``_GEN8``. | |
97 | * | |
98 | * Examples | |
99 | * '''''''' | |
100 | * | |
101 | * (Note that the values in the example are indented using spaces instead of | |
102 | * TABs to avoid misalignment in generated documentation. Use TABs in the | |
103 | * definitions.):: | |
104 | * | |
105 | * #define _FOO_A 0xf000 | |
106 | * #define _FOO_B 0xf001 | |
107 | * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B) | |
108 | * #define FOO_ENABLE (1 << 31) | |
109 | * #define FOO_MODE_MASK (0xf << 16) | |
110 | * #define FOO_MODE_SHIFT 16 | |
111 | * #define FOO_MODE_BAR (0 << 16) | |
112 | * #define FOO_MODE_BAZ (1 << 16) | |
113 | * #define FOO_MODE_QUX_SNB (2 << 16) | |
114 | * | |
115 | * #define BAR _MMIO(0xb000) | |
116 | * #define GEN8_BAR _MMIO(0xb888) | |
117 | */ | |
118 | ||
f0f59a00 VS |
119 | typedef struct { |
120 | uint32_t reg; | |
121 | } i915_reg_t; | |
122 | ||
123 | #define _MMIO(r) ((const i915_reg_t){ .reg = (r) }) | |
124 | ||
125 | #define INVALID_MMIO_REG _MMIO(0) | |
126 | ||
127 | static inline uint32_t i915_mmio_reg_offset(i915_reg_t reg) | |
128 | { | |
129 | return reg.reg; | |
130 | } | |
131 | ||
132 | static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b) | |
133 | { | |
134 | return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b); | |
135 | } | |
136 | ||
137 | static inline bool i915_mmio_reg_valid(i915_reg_t reg) | |
138 | { | |
139 | return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG); | |
140 | } | |
141 | ||
e67005e5 JN |
142 | /* |
143 | * Given the first two numbers __a and __b of arbitrarily many evenly spaced | |
144 | * numbers, pick the 0-based __index'th value. | |
145 | * | |
146 | * Always prefer this over _PICK() if the numbers are evenly spaced. | |
147 | */ | |
148 | #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a))) | |
149 | ||
150 | /* | |
151 | * Given the arbitrary numbers in varargs, pick the 0-based __index'th number. | |
152 | * | |
153 | * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced. | |
154 | */ | |
ce64645d JN |
155 | #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index]) |
156 | ||
e67005e5 JN |
157 | /* |
158 | * Named helper wrappers around _PICK_EVEN() and _PICK(). | |
159 | */ | |
160 | #define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b) | |
f0f59a00 | 161 | #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) |
e67005e5 | 162 | #define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b) |
f0f59a00 | 163 | #define _MMIO_PLANE(plane, a, b) _MMIO_PIPE(plane, a, b) |
e67005e5 | 164 | #define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b) |
f0f59a00 | 165 | #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b)) |
e67005e5 | 166 | #define _PORT(port, a, b) _PICK_EVEN(port, a, b) |
f0f59a00 | 167 | #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b)) |
a1986f41 RV |
168 | #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) |
169 | #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) | |
e67005e5 | 170 | #define _PLL(pll, a, b) _PICK_EVEN(pll, a, b) |
a927c927 | 171 | #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) |
ce64645d | 172 | #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__) |
0a116ce8 | 173 | #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) |
2b139522 | 174 | |
5ee4a7a6 | 175 | #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value)) |
98533251 DL |
176 | #define _MASKED_FIELD(mask, value) ({ \ |
177 | if (__builtin_constant_p(mask)) \ | |
178 | BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \ | |
179 | if (__builtin_constant_p(value)) \ | |
180 | BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \ | |
181 | if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \ | |
182 | BUILD_BUG_ON_MSG((value) & ~(mask), \ | |
183 | "Incorrect value for mask"); \ | |
5ee4a7a6 | 184 | __MASKED_FIELD(mask, value); }) |
98533251 DL |
185 | #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) |
186 | #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0)) | |
187 | ||
237ae7c7 | 188 | /* Engine ID */ |
98533251 | 189 | |
237ae7c7 MW |
190 | #define RCS_HW 0 |
191 | #define VCS_HW 1 | |
192 | #define BCS_HW 2 | |
193 | #define VECS_HW 3 | |
194 | #define VCS2_HW 4 | |
022d3093 TU |
195 | #define VCS3_HW 6 |
196 | #define VCS4_HW 7 | |
197 | #define VECS2_HW 12 | |
6b26c86d | 198 | |
0908180b DCS |
199 | /* Engine class */ |
200 | ||
201 | #define RENDER_CLASS 0 | |
202 | #define VIDEO_DECODE_CLASS 1 | |
203 | #define VIDEO_ENHANCEMENT_CLASS 2 | |
204 | #define COPY_ENGINE_CLASS 3 | |
205 | #define OTHER_CLASS 4 | |
b46a33e2 TU |
206 | #define MAX_ENGINE_CLASS 4 |
207 | ||
d02b98b8 | 208 | #define OTHER_GTPM_INSTANCE 1 |
022d3093 | 209 | #define MAX_ENGINE_INSTANCE 3 |
0908180b | 210 | |
585fb111 JB |
211 | /* PCI config space */ |
212 | ||
e10fa551 JL |
213 | #define MCHBAR_I915 0x44 |
214 | #define MCHBAR_I965 0x48 | |
215 | #define MCHBAR_SIZE (4 * 4096) | |
216 | ||
217 | #define DEVEN 0x54 | |
218 | #define DEVEN_MCHBAR_EN (1 << 28) | |
219 | ||
40006c43 | 220 | /* BSM in include/drm/i915_drm.h */ |
e10fa551 | 221 | |
1b1d2716 VS |
222 | #define HPLLCC 0xc0 /* 85x only */ |
223 | #define GC_CLOCK_CONTROL_MASK (0x7 << 0) | |
585fb111 JB |
224 | #define GC_CLOCK_133_200 (0 << 0) |
225 | #define GC_CLOCK_100_200 (1 << 0) | |
226 | #define GC_CLOCK_100_133 (2 << 0) | |
1b1d2716 VS |
227 | #define GC_CLOCK_133_266 (3 << 0) |
228 | #define GC_CLOCK_133_200_2 (4 << 0) | |
229 | #define GC_CLOCK_133_266_2 (5 << 0) | |
230 | #define GC_CLOCK_166_266 (6 << 0) | |
231 | #define GC_CLOCK_166_250 (7 << 0) | |
232 | ||
e10fa551 JL |
233 | #define I915_GDRST 0xc0 /* PCI config register */ |
234 | #define GRDOM_FULL (0 << 2) | |
235 | #define GRDOM_RENDER (1 << 2) | |
236 | #define GRDOM_MEDIA (3 << 2) | |
237 | #define GRDOM_MASK (3 << 2) | |
238 | #define GRDOM_RESET_STATUS (1 << 1) | |
239 | #define GRDOM_RESET_ENABLE (1 << 0) | |
240 | ||
8fdded82 VS |
241 | /* BSpec only has register offset, PCI device and bit found empirically */ |
242 | #define I830_CLOCK_GATE 0xc8 /* device 0 */ | |
243 | #define I830_L2_CACHE_CLOCK_GATE_DISABLE (1 << 2) | |
244 | ||
e10fa551 JL |
245 | #define GCDGMBUS 0xcc |
246 | ||
f97108d1 | 247 | #define GCFGC2 0xda |
585fb111 JB |
248 | #define GCFGC 0xf0 /* 915+ only */ |
249 | #define GC_LOW_FREQUENCY_ENABLE (1 << 7) | |
250 | #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) | |
6248017a | 251 | #define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4) |
257a7ffc DV |
252 | #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4) |
253 | #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4) | |
254 | #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4) | |
255 | #define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4) | |
256 | #define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4) | |
257 | #define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4) | |
585fb111 | 258 | #define GC_DISPLAY_CLOCK_MASK (7 << 4) |
652c393a JB |
259 | #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) |
260 | #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) | |
261 | #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) | |
262 | #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) | |
263 | #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) | |
264 | #define I965_GC_RENDER_CLOCK_MASK (0xf << 0) | |
265 | #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) | |
266 | #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) | |
267 | #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) | |
268 | #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) | |
269 | #define I945_GC_RENDER_CLOCK_MASK (7 << 0) | |
270 | #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) | |
271 | #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) | |
272 | #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) | |
273 | #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) | |
274 | #define I915_GC_RENDER_CLOCK_MASK (7 << 0) | |
275 | #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) | |
276 | #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) | |
277 | #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) | |
7f1bdbcb | 278 | |
e10fa551 JL |
279 | #define ASLE 0xe4 |
280 | #define ASLS 0xfc | |
281 | ||
282 | #define SWSCI 0xe8 | |
283 | #define SWSCI_SCISEL (1 << 15) | |
284 | #define SWSCI_GSSCIE (1 << 0) | |
285 | ||
286 | #define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */ | |
eeccdcac | 287 | |
585fb111 | 288 | |
f0f59a00 | 289 | #define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4) |
5ee8ee86 PZ |
290 | #define ILK_GRDOM_FULL (0 << 1) |
291 | #define ILK_GRDOM_RENDER (1 << 1) | |
292 | #define ILK_GRDOM_MEDIA (3 << 1) | |
293 | #define ILK_GRDOM_MASK (3 << 1) | |
294 | #define ILK_GRDOM_RESET_ENABLE (1 << 0) | |
b3a3f03d | 295 | |
f0f59a00 | 296 | #define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */ |
07b7ddd9 | 297 | #define GEN6_MBC_SNPCR_SHIFT 21 |
5ee8ee86 PZ |
298 | #define GEN6_MBC_SNPCR_MASK (3 << 21) |
299 | #define GEN6_MBC_SNPCR_MAX (0 << 21) | |
300 | #define GEN6_MBC_SNPCR_MED (1 << 21) | |
301 | #define GEN6_MBC_SNPCR_LOW (2 << 21) | |
302 | #define GEN6_MBC_SNPCR_MIN (3 << 21) /* only 1/16th of the cache is shared */ | |
07b7ddd9 | 303 | |
f0f59a00 VS |
304 | #define VLV_G3DCTL _MMIO(0x9024) |
305 | #define VLV_GSCKGCTL _MMIO(0x9028) | |
9e72b46c | 306 | |
f0f59a00 | 307 | #define GEN6_MBCTL _MMIO(0x0907c) |
5eb719cd DV |
308 | #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) |
309 | #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) | |
310 | #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) | |
311 | #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) | |
312 | #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0) | |
313 | ||
f0f59a00 | 314 | #define GEN6_GDRST _MMIO(0x941c) |
cff458c2 EA |
315 | #define GEN6_GRDOM_FULL (1 << 0) |
316 | #define GEN6_GRDOM_RENDER (1 << 1) | |
317 | #define GEN6_GRDOM_MEDIA (1 << 2) | |
318 | #define GEN6_GRDOM_BLT (1 << 3) | |
ee4b6faf | 319 | #define GEN6_GRDOM_VECS (1 << 4) |
6b332fa2 | 320 | #define GEN9_GRDOM_GUC (1 << 5) |
ee4b6faf | 321 | #define GEN8_GRDOM_MEDIA2 (1 << 7) |
e34b0345 MT |
322 | /* GEN11 changed all bit defs except for FULL & RENDER */ |
323 | #define GEN11_GRDOM_FULL GEN6_GRDOM_FULL | |
324 | #define GEN11_GRDOM_RENDER GEN6_GRDOM_RENDER | |
325 | #define GEN11_GRDOM_BLT (1 << 2) | |
326 | #define GEN11_GRDOM_GUC (1 << 3) | |
327 | #define GEN11_GRDOM_MEDIA (1 << 5) | |
328 | #define GEN11_GRDOM_MEDIA2 (1 << 6) | |
329 | #define GEN11_GRDOM_MEDIA3 (1 << 7) | |
330 | #define GEN11_GRDOM_MEDIA4 (1 << 8) | |
331 | #define GEN11_GRDOM_VECS (1 << 13) | |
332 | #define GEN11_GRDOM_VECS2 (1 << 14) | |
cff458c2 | 333 | |
5ee8ee86 PZ |
334 | #define RING_PP_DIR_BASE(engine) _MMIO((engine)->mmio_base + 0x228) |
335 | #define RING_PP_DIR_BASE_READ(engine) _MMIO((engine)->mmio_base + 0x518) | |
336 | #define RING_PP_DIR_DCLV(engine) _MMIO((engine)->mmio_base + 0x220) | |
5eb719cd DV |
337 | #define PP_DIR_DCLV_2G 0xffffffff |
338 | ||
5ee8ee86 PZ |
339 | #define GEN8_RING_PDP_UDW(engine, n) _MMIO((engine)->mmio_base + 0x270 + (n) * 8 + 4) |
340 | #define GEN8_RING_PDP_LDW(engine, n) _MMIO((engine)->mmio_base + 0x270 + (n) * 8) | |
94e409c1 | 341 | |
f0f59a00 | 342 | #define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8) |
0cea6502 JM |
343 | #define GEN8_RPCS_ENABLE (1 << 31) |
344 | #define GEN8_RPCS_S_CNT_ENABLE (1 << 18) | |
345 | #define GEN8_RPCS_S_CNT_SHIFT 15 | |
346 | #define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT) | |
347 | #define GEN8_RPCS_SS_CNT_ENABLE (1 << 11) | |
348 | #define GEN8_RPCS_SS_CNT_SHIFT 8 | |
349 | #define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT) | |
350 | #define GEN8_RPCS_EU_MAX_SHIFT 4 | |
351 | #define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT) | |
352 | #define GEN8_RPCS_EU_MIN_SHIFT 0 | |
353 | #define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT) | |
354 | ||
f89823c2 LL |
355 | #define WAIT_FOR_RC6_EXIT _MMIO(0x20CC) |
356 | /* HSW only */ | |
357 | #define HSW_SELECTIVE_READ_ADDRESSING_SHIFT 2 | |
358 | #define HSW_SELECTIVE_READ_ADDRESSING_MASK (0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT) | |
359 | #define HSW_SELECTIVE_WRITE_ADDRESS_SHIFT 4 | |
360 | #define HSW_SELECTIVE_WRITE_ADDRESS_MASK (0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT) | |
361 | /* HSW+ */ | |
362 | #define HSW_WAIT_FOR_RC6_EXIT_ENABLE (1 << 0) | |
363 | #define HSW_RCS_CONTEXT_ENABLE (1 << 7) | |
364 | #define HSW_RCS_INHIBIT (1 << 8) | |
365 | /* Gen8 */ | |
366 | #define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4 | |
367 | #define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT) | |
368 | #define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4 | |
369 | #define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT) | |
370 | #define GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE (1 << 6) | |
371 | #define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT 9 | |
372 | #define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT) | |
373 | #define GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT 11 | |
374 | #define GEN8_SELECTIVE_READ_SLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT) | |
375 | #define GEN8_SELECTIVE_READ_ADDRESSING_ENABLE (1 << 13) | |
376 | ||
f0f59a00 | 377 | #define GAM_ECOCHK _MMIO(0x4090) |
5ee8ee86 PZ |
378 | #define BDW_DISABLE_HDC_INVALIDATION (1 << 25) |
379 | #define ECOCHK_SNB_BIT (1 << 10) | |
380 | #define ECOCHK_DIS_TLB (1 << 8) | |
381 | #define HSW_ECOCHK_ARB_PRIO_SOL (1 << 6) | |
382 | #define ECOCHK_PPGTT_CACHE64B (0x3 << 3) | |
383 | #define ECOCHK_PPGTT_CACHE4B (0x0 << 3) | |
384 | #define ECOCHK_PPGTT_GFDT_IVB (0x1 << 4) | |
385 | #define ECOCHK_PPGTT_LLC_IVB (0x1 << 3) | |
386 | #define ECOCHK_PPGTT_UC_HSW (0x1 << 3) | |
387 | #define ECOCHK_PPGTT_WT_HSW (0x2 << 3) | |
388 | #define ECOCHK_PPGTT_WB_HSW (0x3 << 3) | |
5eb719cd | 389 | |
f0f59a00 | 390 | #define GAC_ECO_BITS _MMIO(0x14090) |
5ee8ee86 PZ |
391 | #define ECOBITS_SNB_BIT (1 << 13) |
392 | #define ECOBITS_PPGTT_CACHE64B (3 << 8) | |
393 | #define ECOBITS_PPGTT_CACHE4B (0 << 8) | |
48ecfa10 | 394 | |
f0f59a00 | 395 | #define GAB_CTL _MMIO(0x24000) |
5ee8ee86 | 396 | #define GAB_CTL_CONT_AFTER_PAGEFAULT (1 << 8) |
be901a5a | 397 | |
f0f59a00 | 398 | #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0) |
3774eb50 PZ |
399 | #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20) |
400 | #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18) | |
401 | #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4) | |
402 | #define GEN6_STOLEN_RESERVED_1M (0 << 4) | |
403 | #define GEN6_STOLEN_RESERVED_512K (1 << 4) | |
404 | #define GEN6_STOLEN_RESERVED_256K (2 << 4) | |
405 | #define GEN6_STOLEN_RESERVED_128K (3 << 4) | |
406 | #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5) | |
407 | #define GEN7_STOLEN_RESERVED_1M (0 << 5) | |
408 | #define GEN7_STOLEN_RESERVED_256K (1 << 5) | |
409 | #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7) | |
410 | #define GEN8_STOLEN_RESERVED_1M (0 << 7) | |
411 | #define GEN8_STOLEN_RESERVED_2M (1 << 7) | |
412 | #define GEN8_STOLEN_RESERVED_4M (2 << 7) | |
413 | #define GEN8_STOLEN_RESERVED_8M (3 << 7) | |
db7fb605 | 414 | #define GEN6_STOLEN_RESERVED_ENABLE (1 << 0) |
40bae736 | 415 | |
585fb111 JB |
416 | /* VGA stuff */ |
417 | ||
418 | #define VGA_ST01_MDA 0x3ba | |
419 | #define VGA_ST01_CGA 0x3da | |
420 | ||
f0f59a00 | 421 | #define _VGA_MSR_WRITE _MMIO(0x3c2) |
585fb111 JB |
422 | #define VGA_MSR_WRITE 0x3c2 |
423 | #define VGA_MSR_READ 0x3cc | |
5ee8ee86 PZ |
424 | #define VGA_MSR_MEM_EN (1 << 1) |
425 | #define VGA_MSR_CGA_MODE (1 << 0) | |
585fb111 | 426 | |
5434fd92 | 427 | #define VGA_SR_INDEX 0x3c4 |
f930ddd0 | 428 | #define SR01 1 |
5434fd92 | 429 | #define VGA_SR_DATA 0x3c5 |
585fb111 JB |
430 | |
431 | #define VGA_AR_INDEX 0x3c0 | |
5ee8ee86 | 432 | #define VGA_AR_VID_EN (1 << 5) |
585fb111 JB |
433 | #define VGA_AR_DATA_WRITE 0x3c0 |
434 | #define VGA_AR_DATA_READ 0x3c1 | |
435 | ||
436 | #define VGA_GR_INDEX 0x3ce | |
437 | #define VGA_GR_DATA 0x3cf | |
438 | /* GR05 */ | |
439 | #define VGA_GR_MEM_READ_MODE_SHIFT 3 | |
440 | #define VGA_GR_MEM_READ_MODE_PLANE 1 | |
441 | /* GR06 */ | |
442 | #define VGA_GR_MEM_MODE_MASK 0xc | |
443 | #define VGA_GR_MEM_MODE_SHIFT 2 | |
444 | #define VGA_GR_MEM_A0000_AFFFF 0 | |
445 | #define VGA_GR_MEM_A0000_BFFFF 1 | |
446 | #define VGA_GR_MEM_B0000_B7FFF 2 | |
447 | #define VGA_GR_MEM_B0000_BFFFF 3 | |
448 | ||
449 | #define VGA_DACMASK 0x3c6 | |
450 | #define VGA_DACRX 0x3c7 | |
451 | #define VGA_DACWX 0x3c8 | |
452 | #define VGA_DACDATA 0x3c9 | |
453 | ||
454 | #define VGA_CR_INDEX_MDA 0x3b4 | |
455 | #define VGA_CR_DATA_MDA 0x3b5 | |
456 | #define VGA_CR_INDEX_CGA 0x3d4 | |
457 | #define VGA_CR_DATA_CGA 0x3d5 | |
458 | ||
f0f59a00 VS |
459 | #define MI_PREDICATE_SRC0 _MMIO(0x2400) |
460 | #define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4) | |
461 | #define MI_PREDICATE_SRC1 _MMIO(0x2408) | |
462 | #define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4) | |
9435373e | 463 | |
f0f59a00 | 464 | #define MI_PREDICATE_RESULT_2 _MMIO(0x2214) |
5ee8ee86 PZ |
465 | #define LOWER_SLICE_ENABLED (1 << 0) |
466 | #define LOWER_SLICE_DISABLED (0 << 0) | |
9435373e | 467 | |
5947de9b BV |
468 | /* |
469 | * Registers used only by the command parser | |
470 | */ | |
f0f59a00 VS |
471 | #define BCS_SWCTRL _MMIO(0x22200) |
472 | ||
473 | #define GPGPU_THREADS_DISPATCHED _MMIO(0x2290) | |
474 | #define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4) | |
475 | #define HS_INVOCATION_COUNT _MMIO(0x2300) | |
476 | #define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4) | |
477 | #define DS_INVOCATION_COUNT _MMIO(0x2308) | |
478 | #define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4) | |
479 | #define IA_VERTICES_COUNT _MMIO(0x2310) | |
480 | #define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4) | |
481 | #define IA_PRIMITIVES_COUNT _MMIO(0x2318) | |
482 | #define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4) | |
483 | #define VS_INVOCATION_COUNT _MMIO(0x2320) | |
484 | #define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4) | |
485 | #define GS_INVOCATION_COUNT _MMIO(0x2328) | |
486 | #define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4) | |
487 | #define GS_PRIMITIVES_COUNT _MMIO(0x2330) | |
488 | #define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4) | |
489 | #define CL_INVOCATION_COUNT _MMIO(0x2338) | |
490 | #define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4) | |
491 | #define CL_PRIMITIVES_COUNT _MMIO(0x2340) | |
492 | #define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4) | |
493 | #define PS_INVOCATION_COUNT _MMIO(0x2348) | |
494 | #define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4) | |
495 | #define PS_DEPTH_COUNT _MMIO(0x2350) | |
496 | #define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4) | |
5947de9b BV |
497 | |
498 | /* There are the 4 64-bit counter registers, one for each stream output */ | |
f0f59a00 VS |
499 | #define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8) |
500 | #define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4) | |
5947de9b | 501 | |
f0f59a00 VS |
502 | #define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8) |
503 | #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4) | |
113a0476 | 504 | |
f0f59a00 VS |
505 | #define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420) |
506 | #define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430) | |
507 | #define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434) | |
508 | #define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438) | |
509 | #define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243C) | |
510 | #define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440) | |
113a0476 | 511 | |
f0f59a00 VS |
512 | #define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500) |
513 | #define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504) | |
514 | #define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508) | |
7b9748cb | 515 | |
1b85066b JJ |
516 | /* There are the 16 64-bit CS General Purpose Registers */ |
517 | #define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8) | |
518 | #define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4) | |
519 | ||
a941795a | 520 | #define GEN7_OACONTROL _MMIO(0x2360) |
d7965152 RB |
521 | #define GEN7_OACONTROL_CTX_MASK 0xFFFFF000 |
522 | #define GEN7_OACONTROL_TIMER_PERIOD_MASK 0x3F | |
523 | #define GEN7_OACONTROL_TIMER_PERIOD_SHIFT 6 | |
5ee8ee86 PZ |
524 | #define GEN7_OACONTROL_TIMER_ENABLE (1 << 5) |
525 | #define GEN7_OACONTROL_FORMAT_A13 (0 << 2) | |
526 | #define GEN7_OACONTROL_FORMAT_A29 (1 << 2) | |
527 | #define GEN7_OACONTROL_FORMAT_A13_B8_C8 (2 << 2) | |
528 | #define GEN7_OACONTROL_FORMAT_A29_B8_C8 (3 << 2) | |
529 | #define GEN7_OACONTROL_FORMAT_B4_C8 (4 << 2) | |
530 | #define GEN7_OACONTROL_FORMAT_A45_B8_C8 (5 << 2) | |
531 | #define GEN7_OACONTROL_FORMAT_B4_C8_A16 (6 << 2) | |
532 | #define GEN7_OACONTROL_FORMAT_C4_B8 (7 << 2) | |
d7965152 | 533 | #define GEN7_OACONTROL_FORMAT_SHIFT 2 |
5ee8ee86 PZ |
534 | #define GEN7_OACONTROL_PER_CTX_ENABLE (1 << 1) |
535 | #define GEN7_OACONTROL_ENABLE (1 << 0) | |
d7965152 RB |
536 | |
537 | #define GEN8_OACTXID _MMIO(0x2364) | |
538 | ||
19f81df2 | 539 | #define GEN8_OA_DEBUG _MMIO(0x2B04) |
5ee8ee86 PZ |
540 | #define GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5) |
541 | #define GEN9_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6) | |
542 | #define GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2) | |
543 | #define GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1) | |
19f81df2 | 544 | |
d7965152 | 545 | #define GEN8_OACONTROL _MMIO(0x2B00) |
5ee8ee86 PZ |
546 | #define GEN8_OA_REPORT_FORMAT_A12 (0 << 2) |
547 | #define GEN8_OA_REPORT_FORMAT_A12_B8_C8 (2 << 2) | |
548 | #define GEN8_OA_REPORT_FORMAT_A36_B8_C8 (5 << 2) | |
549 | #define GEN8_OA_REPORT_FORMAT_C4_B8 (7 << 2) | |
d7965152 | 550 | #define GEN8_OA_REPORT_FORMAT_SHIFT 2 |
5ee8ee86 PZ |
551 | #define GEN8_OA_SPECIFIC_CONTEXT_ENABLE (1 << 1) |
552 | #define GEN8_OA_COUNTER_ENABLE (1 << 0) | |
d7965152 RB |
553 | |
554 | #define GEN8_OACTXCONTROL _MMIO(0x2360) | |
555 | #define GEN8_OA_TIMER_PERIOD_MASK 0x3F | |
556 | #define GEN8_OA_TIMER_PERIOD_SHIFT 2 | |
5ee8ee86 PZ |
557 | #define GEN8_OA_TIMER_ENABLE (1 << 1) |
558 | #define GEN8_OA_COUNTER_RESUME (1 << 0) | |
d7965152 RB |
559 | |
560 | #define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */ | |
5ee8ee86 PZ |
561 | #define GEN7_OABUFFER_OVERRUN_DISABLE (1 << 3) |
562 | #define GEN7_OABUFFER_EDGE_TRIGGER (1 << 2) | |
563 | #define GEN7_OABUFFER_STOP_RESUME_ENABLE (1 << 1) | |
564 | #define GEN7_OABUFFER_RESUME (1 << 0) | |
d7965152 | 565 | |
19f81df2 | 566 | #define GEN8_OABUFFER_UDW _MMIO(0x23b4) |
d7965152 | 567 | #define GEN8_OABUFFER _MMIO(0x2b14) |
b82ed43d | 568 | #define GEN8_OABUFFER_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */ |
d7965152 RB |
569 | |
570 | #define GEN7_OASTATUS1 _MMIO(0x2364) | |
571 | #define GEN7_OASTATUS1_TAIL_MASK 0xffffffc0 | |
5ee8ee86 PZ |
572 | #define GEN7_OASTATUS1_COUNTER_OVERFLOW (1 << 2) |
573 | #define GEN7_OASTATUS1_OABUFFER_OVERFLOW (1 << 1) | |
574 | #define GEN7_OASTATUS1_REPORT_LOST (1 << 0) | |
d7965152 RB |
575 | |
576 | #define GEN7_OASTATUS2 _MMIO(0x2368) | |
b82ed43d LL |
577 | #define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0 |
578 | #define GEN7_OASTATUS2_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */ | |
d7965152 RB |
579 | |
580 | #define GEN8_OASTATUS _MMIO(0x2b08) | |
5ee8ee86 PZ |
581 | #define GEN8_OASTATUS_OVERRUN_STATUS (1 << 3) |
582 | #define GEN8_OASTATUS_COUNTER_OVERFLOW (1 << 2) | |
583 | #define GEN8_OASTATUS_OABUFFER_OVERFLOW (1 << 1) | |
584 | #define GEN8_OASTATUS_REPORT_LOST (1 << 0) | |
d7965152 RB |
585 | |
586 | #define GEN8_OAHEADPTR _MMIO(0x2B0C) | |
19f81df2 | 587 | #define GEN8_OAHEADPTR_MASK 0xffffffc0 |
d7965152 | 588 | #define GEN8_OATAILPTR _MMIO(0x2B10) |
19f81df2 | 589 | #define GEN8_OATAILPTR_MASK 0xffffffc0 |
d7965152 | 590 | |
5ee8ee86 PZ |
591 | #define OABUFFER_SIZE_128K (0 << 3) |
592 | #define OABUFFER_SIZE_256K (1 << 3) | |
593 | #define OABUFFER_SIZE_512K (2 << 3) | |
594 | #define OABUFFER_SIZE_1M (3 << 3) | |
595 | #define OABUFFER_SIZE_2M (4 << 3) | |
596 | #define OABUFFER_SIZE_4M (5 << 3) | |
597 | #define OABUFFER_SIZE_8M (6 << 3) | |
598 | #define OABUFFER_SIZE_16M (7 << 3) | |
d7965152 | 599 | |
19f81df2 RB |
600 | /* |
601 | * Flexible, Aggregate EU Counter Registers. | |
602 | * Note: these aren't contiguous | |
603 | */ | |
d7965152 | 604 | #define EU_PERF_CNTL0 _MMIO(0xe458) |
19f81df2 RB |
605 | #define EU_PERF_CNTL1 _MMIO(0xe558) |
606 | #define EU_PERF_CNTL2 _MMIO(0xe658) | |
607 | #define EU_PERF_CNTL3 _MMIO(0xe758) | |
608 | #define EU_PERF_CNTL4 _MMIO(0xe45c) | |
609 | #define EU_PERF_CNTL5 _MMIO(0xe55c) | |
610 | #define EU_PERF_CNTL6 _MMIO(0xe65c) | |
d7965152 | 611 | |
d7965152 RB |
612 | /* |
613 | * OA Boolean state | |
614 | */ | |
615 | ||
d7965152 RB |
616 | #define OASTARTTRIG1 _MMIO(0x2710) |
617 | #define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000 | |
618 | #define OASTARTTRIG1_THRESHOLD_MASK 0xffff | |
619 | ||
620 | #define OASTARTTRIG2 _MMIO(0x2714) | |
5ee8ee86 PZ |
621 | #define OASTARTTRIG2_INVERT_A_0 (1 << 0) |
622 | #define OASTARTTRIG2_INVERT_A_1 (1 << 1) | |
623 | #define OASTARTTRIG2_INVERT_A_2 (1 << 2) | |
624 | #define OASTARTTRIG2_INVERT_A_3 (1 << 3) | |
625 | #define OASTARTTRIG2_INVERT_A_4 (1 << 4) | |
626 | #define OASTARTTRIG2_INVERT_A_5 (1 << 5) | |
627 | #define OASTARTTRIG2_INVERT_A_6 (1 << 6) | |
628 | #define OASTARTTRIG2_INVERT_A_7 (1 << 7) | |
629 | #define OASTARTTRIG2_INVERT_A_8 (1 << 8) | |
630 | #define OASTARTTRIG2_INVERT_A_9 (1 << 9) | |
631 | #define OASTARTTRIG2_INVERT_A_10 (1 << 10) | |
632 | #define OASTARTTRIG2_INVERT_A_11 (1 << 11) | |
633 | #define OASTARTTRIG2_INVERT_A_12 (1 << 12) | |
634 | #define OASTARTTRIG2_INVERT_A_13 (1 << 13) | |
635 | #define OASTARTTRIG2_INVERT_A_14 (1 << 14) | |
636 | #define OASTARTTRIG2_INVERT_A_15 (1 << 15) | |
637 | #define OASTARTTRIG2_INVERT_B_0 (1 << 16) | |
638 | #define OASTARTTRIG2_INVERT_B_1 (1 << 17) | |
639 | #define OASTARTTRIG2_INVERT_B_2 (1 << 18) | |
640 | #define OASTARTTRIG2_INVERT_B_3 (1 << 19) | |
641 | #define OASTARTTRIG2_INVERT_C_0 (1 << 20) | |
642 | #define OASTARTTRIG2_INVERT_C_1 (1 << 21) | |
643 | #define OASTARTTRIG2_INVERT_D_0 (1 << 22) | |
644 | #define OASTARTTRIG2_THRESHOLD_ENABLE (1 << 23) | |
645 | #define OASTARTTRIG2_START_TRIG_FLAG_MBZ (1 << 24) | |
646 | #define OASTARTTRIG2_EVENT_SELECT_0 (1 << 28) | |
647 | #define OASTARTTRIG2_EVENT_SELECT_1 (1 << 29) | |
648 | #define OASTARTTRIG2_EVENT_SELECT_2 (1 << 30) | |
649 | #define OASTARTTRIG2_EVENT_SELECT_3 (1 << 31) | |
d7965152 RB |
650 | |
651 | #define OASTARTTRIG3 _MMIO(0x2718) | |
652 | #define OASTARTTRIG3_NOA_SELECT_MASK 0xf | |
653 | #define OASTARTTRIG3_NOA_SELECT_8_SHIFT 0 | |
654 | #define OASTARTTRIG3_NOA_SELECT_9_SHIFT 4 | |
655 | #define OASTARTTRIG3_NOA_SELECT_10_SHIFT 8 | |
656 | #define OASTARTTRIG3_NOA_SELECT_11_SHIFT 12 | |
657 | #define OASTARTTRIG3_NOA_SELECT_12_SHIFT 16 | |
658 | #define OASTARTTRIG3_NOA_SELECT_13_SHIFT 20 | |
659 | #define OASTARTTRIG3_NOA_SELECT_14_SHIFT 24 | |
660 | #define OASTARTTRIG3_NOA_SELECT_15_SHIFT 28 | |
661 | ||
662 | #define OASTARTTRIG4 _MMIO(0x271c) | |
663 | #define OASTARTTRIG4_NOA_SELECT_MASK 0xf | |
664 | #define OASTARTTRIG4_NOA_SELECT_0_SHIFT 0 | |
665 | #define OASTARTTRIG4_NOA_SELECT_1_SHIFT 4 | |
666 | #define OASTARTTRIG4_NOA_SELECT_2_SHIFT 8 | |
667 | #define OASTARTTRIG4_NOA_SELECT_3_SHIFT 12 | |
668 | #define OASTARTTRIG4_NOA_SELECT_4_SHIFT 16 | |
669 | #define OASTARTTRIG4_NOA_SELECT_5_SHIFT 20 | |
670 | #define OASTARTTRIG4_NOA_SELECT_6_SHIFT 24 | |
671 | #define OASTARTTRIG4_NOA_SELECT_7_SHIFT 28 | |
672 | ||
673 | #define OASTARTTRIG5 _MMIO(0x2720) | |
674 | #define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000 | |
675 | #define OASTARTTRIG5_THRESHOLD_MASK 0xffff | |
676 | ||
677 | #define OASTARTTRIG6 _MMIO(0x2724) | |
5ee8ee86 PZ |
678 | #define OASTARTTRIG6_INVERT_A_0 (1 << 0) |
679 | #define OASTARTTRIG6_INVERT_A_1 (1 << 1) | |
680 | #define OASTARTTRIG6_INVERT_A_2 (1 << 2) | |
681 | #define OASTARTTRIG6_INVERT_A_3 (1 << 3) | |
682 | #define OASTARTTRIG6_INVERT_A_4 (1 << 4) | |
683 | #define OASTARTTRIG6_INVERT_A_5 (1 << 5) | |
684 | #define OASTARTTRIG6_INVERT_A_6 (1 << 6) | |
685 | #define OASTARTTRIG6_INVERT_A_7 (1 << 7) | |
686 | #define OASTARTTRIG6_INVERT_A_8 (1 << 8) | |
687 | #define OASTARTTRIG6_INVERT_A_9 (1 << 9) | |
688 | #define OASTARTTRIG6_INVERT_A_10 (1 << 10) | |
689 | #define OASTARTTRIG6_INVERT_A_11 (1 << 11) | |
690 | #define OASTARTTRIG6_INVERT_A_12 (1 << 12) | |
691 | #define OASTARTTRIG6_INVERT_A_13 (1 << 13) | |
692 | #define OASTARTTRIG6_INVERT_A_14 (1 << 14) | |
693 | #define OASTARTTRIG6_INVERT_A_15 (1 << 15) | |
694 | #define OASTARTTRIG6_INVERT_B_0 (1 << 16) | |
695 | #define OASTARTTRIG6_INVERT_B_1 (1 << 17) | |
696 | #define OASTARTTRIG6_INVERT_B_2 (1 << 18) | |
697 | #define OASTARTTRIG6_INVERT_B_3 (1 << 19) | |
698 | #define OASTARTTRIG6_INVERT_C_0 (1 << 20) | |
699 | #define OASTARTTRIG6_INVERT_C_1 (1 << 21) | |
700 | #define OASTARTTRIG6_INVERT_D_0 (1 << 22) | |
701 | #define OASTARTTRIG6_THRESHOLD_ENABLE (1 << 23) | |
702 | #define OASTARTTRIG6_START_TRIG_FLAG_MBZ (1 << 24) | |
703 | #define OASTARTTRIG6_EVENT_SELECT_4 (1 << 28) | |
704 | #define OASTARTTRIG6_EVENT_SELECT_5 (1 << 29) | |
705 | #define OASTARTTRIG6_EVENT_SELECT_6 (1 << 30) | |
706 | #define OASTARTTRIG6_EVENT_SELECT_7 (1 << 31) | |
d7965152 RB |
707 | |
708 | #define OASTARTTRIG7 _MMIO(0x2728) | |
709 | #define OASTARTTRIG7_NOA_SELECT_MASK 0xf | |
710 | #define OASTARTTRIG7_NOA_SELECT_8_SHIFT 0 | |
711 | #define OASTARTTRIG7_NOA_SELECT_9_SHIFT 4 | |
712 | #define OASTARTTRIG7_NOA_SELECT_10_SHIFT 8 | |
713 | #define OASTARTTRIG7_NOA_SELECT_11_SHIFT 12 | |
714 | #define OASTARTTRIG7_NOA_SELECT_12_SHIFT 16 | |
715 | #define OASTARTTRIG7_NOA_SELECT_13_SHIFT 20 | |
716 | #define OASTARTTRIG7_NOA_SELECT_14_SHIFT 24 | |
717 | #define OASTARTTRIG7_NOA_SELECT_15_SHIFT 28 | |
718 | ||
719 | #define OASTARTTRIG8 _MMIO(0x272c) | |
720 | #define OASTARTTRIG8_NOA_SELECT_MASK 0xf | |
721 | #define OASTARTTRIG8_NOA_SELECT_0_SHIFT 0 | |
722 | #define OASTARTTRIG8_NOA_SELECT_1_SHIFT 4 | |
723 | #define OASTARTTRIG8_NOA_SELECT_2_SHIFT 8 | |
724 | #define OASTARTTRIG8_NOA_SELECT_3_SHIFT 12 | |
725 | #define OASTARTTRIG8_NOA_SELECT_4_SHIFT 16 | |
726 | #define OASTARTTRIG8_NOA_SELECT_5_SHIFT 20 | |
727 | #define OASTARTTRIG8_NOA_SELECT_6_SHIFT 24 | |
728 | #define OASTARTTRIG8_NOA_SELECT_7_SHIFT 28 | |
729 | ||
7853d92e LL |
730 | #define OAREPORTTRIG1 _MMIO(0x2740) |
731 | #define OAREPORTTRIG1_THRESHOLD_MASK 0xffff | |
732 | #define OAREPORTTRIG1_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */ | |
733 | ||
734 | #define OAREPORTTRIG2 _MMIO(0x2744) | |
5ee8ee86 PZ |
735 | #define OAREPORTTRIG2_INVERT_A_0 (1 << 0) |
736 | #define OAREPORTTRIG2_INVERT_A_1 (1 << 1) | |
737 | #define OAREPORTTRIG2_INVERT_A_2 (1 << 2) | |
738 | #define OAREPORTTRIG2_INVERT_A_3 (1 << 3) | |
739 | #define OAREPORTTRIG2_INVERT_A_4 (1 << 4) | |
740 | #define OAREPORTTRIG2_INVERT_A_5 (1 << 5) | |
741 | #define OAREPORTTRIG2_INVERT_A_6 (1 << 6) | |
742 | #define OAREPORTTRIG2_INVERT_A_7 (1 << 7) | |
743 | #define OAREPORTTRIG2_INVERT_A_8 (1 << 8) | |
744 | #define OAREPORTTRIG2_INVERT_A_9 (1 << 9) | |
745 | #define OAREPORTTRIG2_INVERT_A_10 (1 << 10) | |
746 | #define OAREPORTTRIG2_INVERT_A_11 (1 << 11) | |
747 | #define OAREPORTTRIG2_INVERT_A_12 (1 << 12) | |
748 | #define OAREPORTTRIG2_INVERT_A_13 (1 << 13) | |
749 | #define OAREPORTTRIG2_INVERT_A_14 (1 << 14) | |
750 | #define OAREPORTTRIG2_INVERT_A_15 (1 << 15) | |
751 | #define OAREPORTTRIG2_INVERT_B_0 (1 << 16) | |
752 | #define OAREPORTTRIG2_INVERT_B_1 (1 << 17) | |
753 | #define OAREPORTTRIG2_INVERT_B_2 (1 << 18) | |
754 | #define OAREPORTTRIG2_INVERT_B_3 (1 << 19) | |
755 | #define OAREPORTTRIG2_INVERT_C_0 (1 << 20) | |
756 | #define OAREPORTTRIG2_INVERT_C_1 (1 << 21) | |
757 | #define OAREPORTTRIG2_INVERT_D_0 (1 << 22) | |
758 | #define OAREPORTTRIG2_THRESHOLD_ENABLE (1 << 23) | |
759 | #define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1 << 31) | |
7853d92e LL |
760 | |
761 | #define OAREPORTTRIG3 _MMIO(0x2748) | |
762 | #define OAREPORTTRIG3_NOA_SELECT_MASK 0xf | |
763 | #define OAREPORTTRIG3_NOA_SELECT_8_SHIFT 0 | |
764 | #define OAREPORTTRIG3_NOA_SELECT_9_SHIFT 4 | |
765 | #define OAREPORTTRIG3_NOA_SELECT_10_SHIFT 8 | |
766 | #define OAREPORTTRIG3_NOA_SELECT_11_SHIFT 12 | |
767 | #define OAREPORTTRIG3_NOA_SELECT_12_SHIFT 16 | |
768 | #define OAREPORTTRIG3_NOA_SELECT_13_SHIFT 20 | |
769 | #define OAREPORTTRIG3_NOA_SELECT_14_SHIFT 24 | |
770 | #define OAREPORTTRIG3_NOA_SELECT_15_SHIFT 28 | |
771 | ||
772 | #define OAREPORTTRIG4 _MMIO(0x274c) | |
773 | #define OAREPORTTRIG4_NOA_SELECT_MASK 0xf | |
774 | #define OAREPORTTRIG4_NOA_SELECT_0_SHIFT 0 | |
775 | #define OAREPORTTRIG4_NOA_SELECT_1_SHIFT 4 | |
776 | #define OAREPORTTRIG4_NOA_SELECT_2_SHIFT 8 | |
777 | #define OAREPORTTRIG4_NOA_SELECT_3_SHIFT 12 | |
778 | #define OAREPORTTRIG4_NOA_SELECT_4_SHIFT 16 | |
779 | #define OAREPORTTRIG4_NOA_SELECT_5_SHIFT 20 | |
780 | #define OAREPORTTRIG4_NOA_SELECT_6_SHIFT 24 | |
781 | #define OAREPORTTRIG4_NOA_SELECT_7_SHIFT 28 | |
782 | ||
783 | #define OAREPORTTRIG5 _MMIO(0x2750) | |
784 | #define OAREPORTTRIG5_THRESHOLD_MASK 0xffff | |
785 | #define OAREPORTTRIG5_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */ | |
786 | ||
787 | #define OAREPORTTRIG6 _MMIO(0x2754) | |
5ee8ee86 PZ |
788 | #define OAREPORTTRIG6_INVERT_A_0 (1 << 0) |
789 | #define OAREPORTTRIG6_INVERT_A_1 (1 << 1) | |
790 | #define OAREPORTTRIG6_INVERT_A_2 (1 << 2) | |
791 | #define OAREPORTTRIG6_INVERT_A_3 (1 << 3) | |
792 | #define OAREPORTTRIG6_INVERT_A_4 (1 << 4) | |
793 | #define OAREPORTTRIG6_INVERT_A_5 (1 << 5) | |
794 | #define OAREPORTTRIG6_INVERT_A_6 (1 << 6) | |
795 | #define OAREPORTTRIG6_INVERT_A_7 (1 << 7) | |
796 | #define OAREPORTTRIG6_INVERT_A_8 (1 << 8) | |
797 | #define OAREPORTTRIG6_INVERT_A_9 (1 << 9) | |
798 | #define OAREPORTTRIG6_INVERT_A_10 (1 << 10) | |
799 | #define OAREPORTTRIG6_INVERT_A_11 (1 << 11) | |
800 | #define OAREPORTTRIG6_INVERT_A_12 (1 << 12) | |
801 | #define OAREPORTTRIG6_INVERT_A_13 (1 << 13) | |
802 | #define OAREPORTTRIG6_INVERT_A_14 (1 << 14) | |
803 | #define OAREPORTTRIG6_INVERT_A_15 (1 << 15) | |
804 | #define OAREPORTTRIG6_INVERT_B_0 (1 << 16) | |
805 | #define OAREPORTTRIG6_INVERT_B_1 (1 << 17) | |
806 | #define OAREPORTTRIG6_INVERT_B_2 (1 << 18) | |
807 | #define OAREPORTTRIG6_INVERT_B_3 (1 << 19) | |
808 | #define OAREPORTTRIG6_INVERT_C_0 (1 << 20) | |
809 | #define OAREPORTTRIG6_INVERT_C_1 (1 << 21) | |
810 | #define OAREPORTTRIG6_INVERT_D_0 (1 << 22) | |
811 | #define OAREPORTTRIG6_THRESHOLD_ENABLE (1 << 23) | |
812 | #define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1 << 31) | |
7853d92e LL |
813 | |
814 | #define OAREPORTTRIG7 _MMIO(0x2758) | |
815 | #define OAREPORTTRIG7_NOA_SELECT_MASK 0xf | |
816 | #define OAREPORTTRIG7_NOA_SELECT_8_SHIFT 0 | |
817 | #define OAREPORTTRIG7_NOA_SELECT_9_SHIFT 4 | |
818 | #define OAREPORTTRIG7_NOA_SELECT_10_SHIFT 8 | |
819 | #define OAREPORTTRIG7_NOA_SELECT_11_SHIFT 12 | |
820 | #define OAREPORTTRIG7_NOA_SELECT_12_SHIFT 16 | |
821 | #define OAREPORTTRIG7_NOA_SELECT_13_SHIFT 20 | |
822 | #define OAREPORTTRIG7_NOA_SELECT_14_SHIFT 24 | |
823 | #define OAREPORTTRIG7_NOA_SELECT_15_SHIFT 28 | |
824 | ||
825 | #define OAREPORTTRIG8 _MMIO(0x275c) | |
826 | #define OAREPORTTRIG8_NOA_SELECT_MASK 0xf | |
827 | #define OAREPORTTRIG8_NOA_SELECT_0_SHIFT 0 | |
828 | #define OAREPORTTRIG8_NOA_SELECT_1_SHIFT 4 | |
829 | #define OAREPORTTRIG8_NOA_SELECT_2_SHIFT 8 | |
830 | #define OAREPORTTRIG8_NOA_SELECT_3_SHIFT 12 | |
831 | #define OAREPORTTRIG8_NOA_SELECT_4_SHIFT 16 | |
832 | #define OAREPORTTRIG8_NOA_SELECT_5_SHIFT 20 | |
833 | #define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24 | |
834 | #define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28 | |
835 | ||
d7965152 RB |
836 | /* CECX_0 */ |
837 | #define OACEC_COMPARE_LESS_OR_EQUAL 6 | |
838 | #define OACEC_COMPARE_NOT_EQUAL 5 | |
839 | #define OACEC_COMPARE_LESS_THAN 4 | |
840 | #define OACEC_COMPARE_GREATER_OR_EQUAL 3 | |
841 | #define OACEC_COMPARE_EQUAL 2 | |
842 | #define OACEC_COMPARE_GREATER_THAN 1 | |
843 | #define OACEC_COMPARE_ANY_EQUAL 0 | |
844 | ||
845 | #define OACEC_COMPARE_VALUE_MASK 0xffff | |
846 | #define OACEC_COMPARE_VALUE_SHIFT 3 | |
847 | ||
5ee8ee86 PZ |
848 | #define OACEC_SELECT_NOA (0 << 19) |
849 | #define OACEC_SELECT_PREV (1 << 19) | |
850 | #define OACEC_SELECT_BOOLEAN (2 << 19) | |
d7965152 RB |
851 | |
852 | /* CECX_1 */ | |
853 | #define OACEC_MASK_MASK 0xffff | |
854 | #define OACEC_CONSIDERATIONS_MASK 0xffff | |
855 | #define OACEC_CONSIDERATIONS_SHIFT 16 | |
856 | ||
857 | #define OACEC0_0 _MMIO(0x2770) | |
858 | #define OACEC0_1 _MMIO(0x2774) | |
859 | #define OACEC1_0 _MMIO(0x2778) | |
860 | #define OACEC1_1 _MMIO(0x277c) | |
861 | #define OACEC2_0 _MMIO(0x2780) | |
862 | #define OACEC2_1 _MMIO(0x2784) | |
863 | #define OACEC3_0 _MMIO(0x2788) | |
864 | #define OACEC3_1 _MMIO(0x278c) | |
865 | #define OACEC4_0 _MMIO(0x2790) | |
866 | #define OACEC4_1 _MMIO(0x2794) | |
867 | #define OACEC5_0 _MMIO(0x2798) | |
868 | #define OACEC5_1 _MMIO(0x279c) | |
869 | #define OACEC6_0 _MMIO(0x27a0) | |
870 | #define OACEC6_1 _MMIO(0x27a4) | |
871 | #define OACEC7_0 _MMIO(0x27a8) | |
872 | #define OACEC7_1 _MMIO(0x27ac) | |
873 | ||
f89823c2 LL |
874 | /* OA perf counters */ |
875 | #define OA_PERFCNT1_LO _MMIO(0x91B8) | |
876 | #define OA_PERFCNT1_HI _MMIO(0x91BC) | |
877 | #define OA_PERFCNT2_LO _MMIO(0x91C0) | |
878 | #define OA_PERFCNT2_HI _MMIO(0x91C4) | |
95690a02 LL |
879 | #define OA_PERFCNT3_LO _MMIO(0x91C8) |
880 | #define OA_PERFCNT3_HI _MMIO(0x91CC) | |
881 | #define OA_PERFCNT4_LO _MMIO(0x91D8) | |
882 | #define OA_PERFCNT4_HI _MMIO(0x91DC) | |
f89823c2 LL |
883 | |
884 | #define OA_PERFMATRIX_LO _MMIO(0x91C8) | |
885 | #define OA_PERFMATRIX_HI _MMIO(0x91CC) | |
886 | ||
887 | /* RPM unit config (Gen8+) */ | |
888 | #define RPM_CONFIG0 _MMIO(0x0D00) | |
dab91783 LL |
889 | #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3 |
890 | #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT) | |
891 | #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 0 | |
892 | #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 1 | |
d775a7b1 PZ |
893 | #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3 |
894 | #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT) | |
895 | #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0 | |
896 | #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1 | |
897 | #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2 | |
898 | #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3 | |
dab91783 LL |
899 | #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1 |
900 | #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT) | |
901 | ||
f89823c2 | 902 | #define RPM_CONFIG1 _MMIO(0x0D04) |
95690a02 | 903 | #define GEN10_GT_NOA_ENABLE (1 << 9) |
f89823c2 | 904 | |
dab91783 LL |
905 | /* GPM unit config (Gen9+) */ |
906 | #define CTC_MODE _MMIO(0xA26C) | |
907 | #define CTC_SOURCE_PARAMETER_MASK 1 | |
908 | #define CTC_SOURCE_CRYSTAL_CLOCK 0 | |
909 | #define CTC_SOURCE_DIVIDE_LOGIC 1 | |
910 | #define CTC_SHIFT_PARAMETER_SHIFT 1 | |
911 | #define CTC_SHIFT_PARAMETER_MASK (0x3 << CTC_SHIFT_PARAMETER_SHIFT) | |
912 | ||
5888576b LL |
913 | /* RCP unit config (Gen8+) */ |
914 | #define RCP_CONFIG _MMIO(0x0D08) | |
f89823c2 | 915 | |
a54b19f1 LL |
916 | /* NOA (HSW) */ |
917 | #define HSW_MBVID2_NOA0 _MMIO(0x9E80) | |
918 | #define HSW_MBVID2_NOA1 _MMIO(0x9E84) | |
919 | #define HSW_MBVID2_NOA2 _MMIO(0x9E88) | |
920 | #define HSW_MBVID2_NOA3 _MMIO(0x9E8C) | |
921 | #define HSW_MBVID2_NOA4 _MMIO(0x9E90) | |
922 | #define HSW_MBVID2_NOA5 _MMIO(0x9E94) | |
923 | #define HSW_MBVID2_NOA6 _MMIO(0x9E98) | |
924 | #define HSW_MBVID2_NOA7 _MMIO(0x9E9C) | |
925 | #define HSW_MBVID2_NOA8 _MMIO(0x9EA0) | |
926 | #define HSW_MBVID2_NOA9 _MMIO(0x9EA4) | |
927 | ||
928 | #define HSW_MBVID2_MISR0 _MMIO(0x9EC0) | |
929 | ||
f89823c2 LL |
930 | /* NOA (Gen8+) */ |
931 | #define NOA_CONFIG(i) _MMIO(0x0D0C + (i) * 4) | |
932 | ||
933 | #define MICRO_BP0_0 _MMIO(0x9800) | |
934 | #define MICRO_BP0_2 _MMIO(0x9804) | |
935 | #define MICRO_BP0_1 _MMIO(0x9808) | |
936 | ||
937 | #define MICRO_BP1_0 _MMIO(0x980C) | |
938 | #define MICRO_BP1_2 _MMIO(0x9810) | |
939 | #define MICRO_BP1_1 _MMIO(0x9814) | |
940 | ||
941 | #define MICRO_BP2_0 _MMIO(0x9818) | |
942 | #define MICRO_BP2_2 _MMIO(0x981C) | |
943 | #define MICRO_BP2_1 _MMIO(0x9820) | |
944 | ||
945 | #define MICRO_BP3_0 _MMIO(0x9824) | |
946 | #define MICRO_BP3_2 _MMIO(0x9828) | |
947 | #define MICRO_BP3_1 _MMIO(0x982C) | |
948 | ||
949 | #define MICRO_BP_TRIGGER _MMIO(0x9830) | |
950 | #define MICRO_BP3_COUNT_STATUS01 _MMIO(0x9834) | |
951 | #define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838) | |
952 | #define MICRO_BP_FIRED_ARMED _MMIO(0x983C) | |
953 | ||
954 | #define GDT_CHICKEN_BITS _MMIO(0x9840) | |
955 | #define GT_NOA_ENABLE 0x00000080 | |
956 | ||
957 | #define NOA_DATA _MMIO(0x986C) | |
958 | #define NOA_WRITE _MMIO(0x9888) | |
180b813c | 959 | |
220375aa BV |
960 | #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 |
961 | #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 | |
f0f59a00 | 962 | #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL) |
220375aa | 963 | |
dc96e9b8 CW |
964 | /* |
965 | * Reset registers | |
966 | */ | |
f0f59a00 | 967 | #define DEBUG_RESET_I830 _MMIO(0x6070) |
5ee8ee86 PZ |
968 | #define DEBUG_RESET_FULL (1 << 7) |
969 | #define DEBUG_RESET_RENDER (1 << 8) | |
970 | #define DEBUG_RESET_DISPLAY (1 << 9) | |
dc96e9b8 | 971 | |
57f350b6 | 972 | /* |
5a09ae9f JN |
973 | * IOSF sideband |
974 | */ | |
f0f59a00 | 975 | #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100) |
5a09ae9f JN |
976 | #define IOSF_DEVFN_SHIFT 24 |
977 | #define IOSF_OPCODE_SHIFT 16 | |
978 | #define IOSF_PORT_SHIFT 8 | |
979 | #define IOSF_BYTE_ENABLES_SHIFT 4 | |
980 | #define IOSF_BAR_SHIFT 1 | |
5ee8ee86 | 981 | #define IOSF_SB_BUSY (1 << 0) |
4688d45f JN |
982 | #define IOSF_PORT_BUNIT 0x03 |
983 | #define IOSF_PORT_PUNIT 0x04 | |
5a09ae9f JN |
984 | #define IOSF_PORT_NC 0x11 |
985 | #define IOSF_PORT_DPIO 0x12 | |
e9f882a3 JN |
986 | #define IOSF_PORT_GPIO_NC 0x13 |
987 | #define IOSF_PORT_CCK 0x14 | |
4688d45f JN |
988 | #define IOSF_PORT_DPIO_2 0x1a |
989 | #define IOSF_PORT_FLISDSI 0x1b | |
dfb19ed2 D |
990 | #define IOSF_PORT_GPIO_SC 0x48 |
991 | #define IOSF_PORT_GPIO_SUS 0xa8 | |
4688d45f | 992 | #define IOSF_PORT_CCU 0xa9 |
7071af97 JN |
993 | #define CHV_IOSF_PORT_GPIO_N 0x13 |
994 | #define CHV_IOSF_PORT_GPIO_SE 0x48 | |
995 | #define CHV_IOSF_PORT_GPIO_E 0xa8 | |
996 | #define CHV_IOSF_PORT_GPIO_SW 0xb2 | |
f0f59a00 VS |
997 | #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104) |
998 | #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108) | |
5a09ae9f | 999 | |
30a970c6 JB |
1000 | /* See configdb bunit SB addr map */ |
1001 | #define BUNIT_REG_BISOC 0x11 | |
1002 | ||
30a970c6 | 1003 | #define PUNIT_REG_DSPFREQ 0x36 |
383c5a6a VS |
1004 | #define DSPFREQSTAT_SHIFT_CHV 24 |
1005 | #define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV) | |
1006 | #define DSPFREQGUAR_SHIFT_CHV 8 | |
1007 | #define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV) | |
30a970c6 JB |
1008 | #define DSPFREQSTAT_SHIFT 30 |
1009 | #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT) | |
1010 | #define DSPFREQGUAR_SHIFT 14 | |
1011 | #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT) | |
cfb41411 VS |
1012 | #define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */ |
1013 | #define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */ | |
1014 | #define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */ | |
26972b0a VS |
1015 | #define _DP_SSC(val, pipe) ((val) << (2 * (pipe))) |
1016 | #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe)) | |
1017 | #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe)) | |
1018 | #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe)) | |
1019 | #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe)) | |
1020 | #define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe)) | |
1021 | #define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16)) | |
1022 | #define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe)) | |
1023 | #define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe)) | |
1024 | #define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe)) | |
1025 | #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe)) | |
1026 | #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe)) | |
a30180a5 | 1027 | |
c3fdb9d8 | 1028 | /* |
438b8dc4 ID |
1029 | * i915_power_well_id: |
1030 | * | |
1031 | * Platform specific IDs used to look up power wells and - except for custom | |
1032 | * power wells - to define request/status register flag bit positions. As such | |
1033 | * the set of IDs on a given platform must be unique and except for custom | |
1034 | * power wells their value must stay fixed. | |
1035 | */ | |
1036 | enum i915_power_well_id { | |
120b56a2 ID |
1037 | /* |
1038 | * I830 | |
1039 | * - custom power well | |
1040 | */ | |
1041 | I830_DISP_PW_PIPES = 0, | |
1042 | ||
438b8dc4 ID |
1043 | /* |
1044 | * VLV/CHV | |
1045 | * - PUNIT_REG_PWRGT_CTRL (bit: id*2), | |
1046 | * PUNIT_REG_PWRGT_STATUS (bit: id*2) (PUNIT HAS v0.8) | |
1047 | */ | |
a30180a5 ID |
1048 | PUNIT_POWER_WELL_RENDER = 0, |
1049 | PUNIT_POWER_WELL_MEDIA = 1, | |
1050 | PUNIT_POWER_WELL_DISP2D = 3, | |
1051 | PUNIT_POWER_WELL_DPIO_CMN_BC = 5, | |
1052 | PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6, | |
1053 | PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7, | |
1054 | PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8, | |
1055 | PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9, | |
1056 | PUNIT_POWER_WELL_DPIO_RX0 = 10, | |
1057 | PUNIT_POWER_WELL_DPIO_RX1 = 11, | |
5d6f7ea7 | 1058 | PUNIT_POWER_WELL_DPIO_CMN_D = 12, |
f49193cd ID |
1059 | /* - custom power well */ |
1060 | CHV_DISP_PW_PIPE_A, /* 13 */ | |
a30180a5 | 1061 | |
fb9248e2 ID |
1062 | /* |
1063 | * HSW/BDW | |
67ca07e7 | 1064 | * - _HSW_PWR_WELL_CTL1-4 (status bit: id*2, req bit: id*2+1) |
fb9248e2 ID |
1065 | */ |
1066 | HSW_DISP_PW_GLOBAL = 15, | |
1067 | ||
438b8dc4 ID |
1068 | /* |
1069 | * GEN9+ | |
67ca07e7 | 1070 | * - _HSW_PWR_WELL_CTL1-4 (status bit: id*2, req bit: id*2+1) |
438b8dc4 ID |
1071 | */ |
1072 | SKL_DISP_PW_MISC_IO = 0, | |
94dd5138 | 1073 | SKL_DISP_PW_DDI_A_E, |
0d03926d | 1074 | GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E, |
8bcd3dd4 | 1075 | CNL_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E, |
94dd5138 S |
1076 | SKL_DISP_PW_DDI_B, |
1077 | SKL_DISP_PW_DDI_C, | |
1078 | SKL_DISP_PW_DDI_D, | |
9787e835 | 1079 | CNL_DISP_PW_DDI_F = 6, |
0d03926d ACO |
1080 | |
1081 | GLK_DISP_PW_AUX_A = 8, | |
1082 | GLK_DISP_PW_AUX_B, | |
1083 | GLK_DISP_PW_AUX_C, | |
8bcd3dd4 VS |
1084 | CNL_DISP_PW_AUX_A = GLK_DISP_PW_AUX_A, |
1085 | CNL_DISP_PW_AUX_B = GLK_DISP_PW_AUX_B, | |
1086 | CNL_DISP_PW_AUX_C = GLK_DISP_PW_AUX_C, | |
1087 | CNL_DISP_PW_AUX_D, | |
a324fcac | 1088 | CNL_DISP_PW_AUX_F, |
0d03926d | 1089 | |
94dd5138 S |
1090 | SKL_DISP_PW_1 = 14, |
1091 | SKL_DISP_PW_2, | |
56fcfd63 | 1092 | |
438b8dc4 | 1093 | /* - custom power wells */ |
9c8d0b8e ID |
1094 | BXT_DPIO_CMN_A, |
1095 | BXT_DPIO_CMN_BC, | |
67ca07e7 ID |
1096 | GLK_DPIO_CMN_C, /* 18 */ |
1097 | ||
1098 | /* | |
1099 | * GEN11+ | |
1100 | * - _HSW_PWR_WELL_CTL1-4 | |
1101 | * (status bit: (id&15)*2, req bit:(id&15)*2+1) | |
1102 | */ | |
1103 | ICL_DISP_PW_1 = 0, | |
1104 | ICL_DISP_PW_2, | |
1105 | ICL_DISP_PW_3, | |
1106 | ICL_DISP_PW_4, | |
1107 | ||
1108 | /* | |
1109 | * - _HSW_PWR_WELL_CTL_AUX1/2/4 | |
1110 | * (status bit: (id&15)*2, req bit:(id&15)*2+1) | |
1111 | */ | |
1112 | ICL_DISP_PW_AUX_A = 16, | |
1113 | ICL_DISP_PW_AUX_B, | |
1114 | ICL_DISP_PW_AUX_C, | |
1115 | ICL_DISP_PW_AUX_D, | |
1116 | ICL_DISP_PW_AUX_E, | |
1117 | ICL_DISP_PW_AUX_F, | |
1118 | ||
1119 | ICL_DISP_PW_AUX_TBT1 = 24, | |
1120 | ICL_DISP_PW_AUX_TBT2, | |
1121 | ICL_DISP_PW_AUX_TBT3, | |
1122 | ICL_DISP_PW_AUX_TBT4, | |
1123 | ||
1124 | /* | |
1125 | * - _HSW_PWR_WELL_CTL_DDI1/2/4 | |
1126 | * (status bit: (id&15)*2, req bit:(id&15)*2+1) | |
1127 | */ | |
1128 | ICL_DISP_PW_DDI_A = 32, | |
1129 | ICL_DISP_PW_DDI_B, | |
1130 | ICL_DISP_PW_DDI_C, | |
1131 | ICL_DISP_PW_DDI_D, | |
1132 | ICL_DISP_PW_DDI_E, | |
1133 | ICL_DISP_PW_DDI_F, /* 37 */ | |
438b8dc4 ID |
1134 | |
1135 | /* | |
1136 | * Multiple platforms. | |
1137 | * Must start following the highest ID of any platform. | |
1138 | * - custom power wells | |
1139 | */ | |
67ca07e7 ID |
1140 | SKL_DISP_PW_DC_OFF = 38, |
1141 | I915_DISP_PW_ALWAYS_ON, | |
94dd5138 S |
1142 | }; |
1143 | ||
02f4c9e0 CML |
1144 | #define PUNIT_REG_PWRGT_CTRL 0x60 |
1145 | #define PUNIT_REG_PWRGT_STATUS 0x61 | |
a30180a5 ID |
1146 | #define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2)) |
1147 | #define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2)) | |
1148 | #define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2)) | |
1149 | #define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2)) | |
1150 | #define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2)) | |
02f4c9e0 | 1151 | |
5a09ae9f JN |
1152 | #define PUNIT_REG_GPU_LFM 0xd3 |
1153 | #define PUNIT_REG_GPU_FREQ_REQ 0xd4 | |
1154 | #define PUNIT_REG_GPU_FREQ_STS 0xd8 | |
5ee8ee86 PZ |
1155 | #define GPLLENABLE (1 << 4) |
1156 | #define GENFREQSTATUS (1 << 0) | |
5a09ae9f | 1157 | #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc |
31685c25 | 1158 | #define PUNIT_REG_CZ_TIMESTAMP 0xce |
5a09ae9f JN |
1159 | |
1160 | #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */ | |
1161 | #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */ | |
1162 | ||
095acd5f D |
1163 | #define FB_GFX_FMAX_AT_VMAX_FUSE 0x136 |
1164 | #define FB_GFX_FREQ_FUSE_MASK 0xff | |
1165 | #define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24 | |
1166 | #define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16 | |
1167 | #define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8 | |
1168 | ||
1169 | #define FB_GFX_FMIN_AT_VMIN_FUSE 0x137 | |
1170 | #define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8 | |
1171 | ||
fc1ac8de VS |
1172 | #define PUNIT_REG_DDR_SETUP2 0x139 |
1173 | #define FORCE_DDR_FREQ_REQ_ACK (1 << 8) | |
1174 | #define FORCE_DDR_LOW_FREQ (1 << 1) | |
1175 | #define FORCE_DDR_HIGH_FREQ (1 << 0) | |
1176 | ||
2b6b3a09 D |
1177 | #define PUNIT_GPU_STATUS_REG 0xdb |
1178 | #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16 | |
1179 | #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff | |
1180 | #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8 | |
1181 | #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff | |
1182 | ||
1183 | #define PUNIT_GPU_DUTYCYCLE_REG 0xdf | |
1184 | #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8 | |
1185 | #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff | |
1186 | ||
5a09ae9f JN |
1187 | #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c |
1188 | #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3 | |
1189 | #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8 | |
1190 | #define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11 | |
1191 | #define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800 | |
1192 | #define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34 | |
1193 | #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007 | |
1194 | #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30 | |
1195 | #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 | |
1196 | #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 | |
1197 | ||
af7187b7 PZ |
1198 | #define VLV_TURBO_SOC_OVERRIDE 0x04 |
1199 | #define VLV_OVERRIDE_EN 1 | |
1200 | #define VLV_SOC_TDP_EN (1 << 1) | |
1201 | #define VLV_BIAS_CPU_125_SOC_875 (6 << 2) | |
1202 | #define CHV_BIAS_CPU_50_SOC_50 (3 << 2) | |
3ef62342 | 1203 | |
be4fc046 | 1204 | /* vlv2 north clock has */ |
24eb2d59 CML |
1205 | #define CCK_FUSE_REG 0x8 |
1206 | #define CCK_FUSE_HPLL_FREQ_MASK 0x3 | |
be4fc046 | 1207 | #define CCK_REG_DSI_PLL_FUSE 0x44 |
1208 | #define CCK_REG_DSI_PLL_CONTROL 0x48 | |
1209 | #define DSI_PLL_VCO_EN (1 << 31) | |
1210 | #define DSI_PLL_LDO_GATE (1 << 30) | |
1211 | #define DSI_PLL_P1_POST_DIV_SHIFT 17 | |
1212 | #define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17) | |
1213 | #define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13) | |
1214 | #define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12) | |
1215 | #define DSI_PLL_MUX_MASK (3 << 9) | |
1216 | #define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10) | |
1217 | #define DSI_PLL_MUX_DSI0_CCK (1 << 10) | |
1218 | #define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9) | |
1219 | #define DSI_PLL_MUX_DSI1_CCK (1 << 9) | |
1220 | #define DSI_PLL_CLK_GATE_MASK (0xf << 5) | |
1221 | #define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8) | |
1222 | #define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7) | |
1223 | #define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6) | |
1224 | #define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5) | |
1225 | #define DSI_PLL_LOCK (1 << 0) | |
1226 | #define CCK_REG_DSI_PLL_DIVIDER 0x4c | |
1227 | #define DSI_PLL_LFSR (1 << 31) | |
1228 | #define DSI_PLL_FRACTION_EN (1 << 30) | |
1229 | #define DSI_PLL_FRAC_COUNTER_SHIFT 27 | |
1230 | #define DSI_PLL_FRAC_COUNTER_MASK (7 << 27) | |
1231 | #define DSI_PLL_USYNC_CNT_SHIFT 18 | |
1232 | #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18) | |
1233 | #define DSI_PLL_N1_DIV_SHIFT 16 | |
1234 | #define DSI_PLL_N1_DIV_MASK (3 << 16) | |
1235 | #define DSI_PLL_M1_DIV_SHIFT 0 | |
1236 | #define DSI_PLL_M1_DIV_MASK (0x1ff << 0) | |
bfa7df01 | 1237 | #define CCK_CZ_CLOCK_CONTROL 0x62 |
c30fec65 | 1238 | #define CCK_GPLL_CLOCK_CONTROL 0x67 |
30a970c6 | 1239 | #define CCK_DISPLAY_CLOCK_CONTROL 0x6b |
35d38d1f | 1240 | #define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c |
87d5d259 VK |
1241 | #define CCK_TRUNK_FORCE_ON (1 << 17) |
1242 | #define CCK_TRUNK_FORCE_OFF (1 << 16) | |
1243 | #define CCK_FREQUENCY_STATUS (0x1f << 8) | |
1244 | #define CCK_FREQUENCY_STATUS_SHIFT 8 | |
1245 | #define CCK_FREQUENCY_VALUES (0x1f << 0) | |
be4fc046 | 1246 | |
f38861b8 | 1247 | /* DPIO registers */ |
5a09ae9f | 1248 | #define DPIO_DEVFN 0 |
5a09ae9f | 1249 | |
f0f59a00 | 1250 | #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110) |
5ee8ee86 PZ |
1251 | #define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */ |
1252 | #define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */ | |
1253 | #define DPIO_SFR_BYPASS (1 << 1) | |
1254 | #define DPIO_CMNRST (1 << 0) | |
57f350b6 | 1255 | |
e4607fcf CML |
1256 | #define DPIO_PHY(pipe) ((pipe) >> 1) |
1257 | #define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy]) | |
1258 | ||
598fac6b DV |
1259 | /* |
1260 | * Per pipe/PLL DPIO regs | |
1261 | */ | |
ab3c759a | 1262 | #define _VLV_PLL_DW3_CH0 0x800c |
57f350b6 | 1263 | #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ |
598fac6b DV |
1264 | #define DPIO_POST_DIV_DAC 0 |
1265 | #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ | |
1266 | #define DPIO_POST_DIV_LVDS1 2 | |
1267 | #define DPIO_POST_DIV_LVDS2 3 | |
57f350b6 JB |
1268 | #define DPIO_K_SHIFT (24) /* 4 bits */ |
1269 | #define DPIO_P1_SHIFT (21) /* 3 bits */ | |
1270 | #define DPIO_P2_SHIFT (16) /* 5 bits */ | |
1271 | #define DPIO_N_SHIFT (12) /* 4 bits */ | |
5ee8ee86 | 1272 | #define DPIO_ENABLE_CALIBRATION (1 << 11) |
57f350b6 JB |
1273 | #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ |
1274 | #define DPIO_M2DIV_MASK 0xff | |
ab3c759a CML |
1275 | #define _VLV_PLL_DW3_CH1 0x802c |
1276 | #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1) | |
57f350b6 | 1277 | |
ab3c759a | 1278 | #define _VLV_PLL_DW5_CH0 0x8014 |
57f350b6 JB |
1279 | #define DPIO_REFSEL_OVERRIDE 27 |
1280 | #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ | |
1281 | #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ | |
1282 | #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ | |
b56747aa | 1283 | #define DPIO_PLL_REFCLK_SEL_MASK 3 |
57f350b6 JB |
1284 | #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ |
1285 | #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ | |
ab3c759a CML |
1286 | #define _VLV_PLL_DW5_CH1 0x8034 |
1287 | #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1) | |
57f350b6 | 1288 | |
ab3c759a CML |
1289 | #define _VLV_PLL_DW7_CH0 0x801c |
1290 | #define _VLV_PLL_DW7_CH1 0x803c | |
1291 | #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1) | |
57f350b6 | 1292 | |
ab3c759a CML |
1293 | #define _VLV_PLL_DW8_CH0 0x8040 |
1294 | #define _VLV_PLL_DW8_CH1 0x8060 | |
1295 | #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1) | |
598fac6b | 1296 | |
ab3c759a CML |
1297 | #define VLV_PLL_DW9_BCAST 0xc044 |
1298 | #define _VLV_PLL_DW9_CH0 0x8044 | |
1299 | #define _VLV_PLL_DW9_CH1 0x8064 | |
1300 | #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1) | |
598fac6b | 1301 | |
ab3c759a CML |
1302 | #define _VLV_PLL_DW10_CH0 0x8048 |
1303 | #define _VLV_PLL_DW10_CH1 0x8068 | |
1304 | #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) | |
598fac6b | 1305 | |
ab3c759a CML |
1306 | #define _VLV_PLL_DW11_CH0 0x804c |
1307 | #define _VLV_PLL_DW11_CH1 0x806c | |
1308 | #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1) | |
57f350b6 | 1309 | |
ab3c759a CML |
1310 | /* Spec for ref block start counts at DW10 */ |
1311 | #define VLV_REF_DW13 0x80ac | |
598fac6b | 1312 | |
ab3c759a | 1313 | #define VLV_CMN_DW0 0x8100 |
dc96e9b8 | 1314 | |
598fac6b DV |
1315 | /* |
1316 | * Per DDI channel DPIO regs | |
1317 | */ | |
1318 | ||
ab3c759a CML |
1319 | #define _VLV_PCS_DW0_CH0 0x8200 |
1320 | #define _VLV_PCS_DW0_CH1 0x8400 | |
5ee8ee86 PZ |
1321 | #define DPIO_PCS_TX_LANE2_RESET (1 << 16) |
1322 | #define DPIO_PCS_TX_LANE1_RESET (1 << 7) | |
1323 | #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4) | |
1324 | #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3) | |
ab3c759a | 1325 | #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1) |
598fac6b | 1326 | |
97fd4d5c VS |
1327 | #define _VLV_PCS01_DW0_CH0 0x200 |
1328 | #define _VLV_PCS23_DW0_CH0 0x400 | |
1329 | #define _VLV_PCS01_DW0_CH1 0x2600 | |
1330 | #define _VLV_PCS23_DW0_CH1 0x2800 | |
1331 | #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1) | |
1332 | #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1) | |
1333 | ||
ab3c759a CML |
1334 | #define _VLV_PCS_DW1_CH0 0x8204 |
1335 | #define _VLV_PCS_DW1_CH1 0x8404 | |
5ee8ee86 PZ |
1336 | #define CHV_PCS_REQ_SOFTRESET_EN (1 << 23) |
1337 | #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22) | |
1338 | #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21) | |
598fac6b | 1339 | #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) |
5ee8ee86 | 1340 | #define DPIO_PCS_CLK_SOFT_RESET (1 << 5) |
ab3c759a CML |
1341 | #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1) |
1342 | ||
97fd4d5c VS |
1343 | #define _VLV_PCS01_DW1_CH0 0x204 |
1344 | #define _VLV_PCS23_DW1_CH0 0x404 | |
1345 | #define _VLV_PCS01_DW1_CH1 0x2604 | |
1346 | #define _VLV_PCS23_DW1_CH1 0x2804 | |
1347 | #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1) | |
1348 | #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1) | |
1349 | ||
ab3c759a CML |
1350 | #define _VLV_PCS_DW8_CH0 0x8220 |
1351 | #define _VLV_PCS_DW8_CH1 0x8420 | |
9197c88b VS |
1352 | #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20) |
1353 | #define CHV_PCS_USEDCLKCHANNEL (1 << 21) | |
ab3c759a CML |
1354 | #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1) |
1355 | ||
1356 | #define _VLV_PCS01_DW8_CH0 0x0220 | |
1357 | #define _VLV_PCS23_DW8_CH0 0x0420 | |
1358 | #define _VLV_PCS01_DW8_CH1 0x2620 | |
1359 | #define _VLV_PCS23_DW8_CH1 0x2820 | |
1360 | #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1) | |
1361 | #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1) | |
1362 | ||
1363 | #define _VLV_PCS_DW9_CH0 0x8224 | |
1364 | #define _VLV_PCS_DW9_CH1 0x8424 | |
5ee8ee86 PZ |
1365 | #define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13) |
1366 | #define DPIO_PCS_TX2MARGIN_000 (0 << 13) | |
1367 | #define DPIO_PCS_TX2MARGIN_101 (1 << 13) | |
1368 | #define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10) | |
1369 | #define DPIO_PCS_TX1MARGIN_000 (0 << 10) | |
1370 | #define DPIO_PCS_TX1MARGIN_101 (1 << 10) | |
ab3c759a CML |
1371 | #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1) |
1372 | ||
a02ef3c7 VS |
1373 | #define _VLV_PCS01_DW9_CH0 0x224 |
1374 | #define _VLV_PCS23_DW9_CH0 0x424 | |
1375 | #define _VLV_PCS01_DW9_CH1 0x2624 | |
1376 | #define _VLV_PCS23_DW9_CH1 0x2824 | |
1377 | #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1) | |
1378 | #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1) | |
1379 | ||
9d556c99 CML |
1380 | #define _CHV_PCS_DW10_CH0 0x8228 |
1381 | #define _CHV_PCS_DW10_CH1 0x8428 | |
5ee8ee86 PZ |
1382 | #define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30) |
1383 | #define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31) | |
1384 | #define DPIO_PCS_TX2DEEMP_MASK (0xf << 24) | |
1385 | #define DPIO_PCS_TX2DEEMP_9P5 (0 << 24) | |
1386 | #define DPIO_PCS_TX2DEEMP_6P0 (2 << 24) | |
1387 | #define DPIO_PCS_TX1DEEMP_MASK (0xf << 16) | |
1388 | #define DPIO_PCS_TX1DEEMP_9P5 (0 << 16) | |
1389 | #define DPIO_PCS_TX1DEEMP_6P0 (2 << 16) | |
9d556c99 CML |
1390 | #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1) |
1391 | ||
1966e59e VS |
1392 | #define _VLV_PCS01_DW10_CH0 0x0228 |
1393 | #define _VLV_PCS23_DW10_CH0 0x0428 | |
1394 | #define _VLV_PCS01_DW10_CH1 0x2628 | |
1395 | #define _VLV_PCS23_DW10_CH1 0x2828 | |
1396 | #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1) | |
1397 | #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1) | |
1398 | ||
ab3c759a CML |
1399 | #define _VLV_PCS_DW11_CH0 0x822c |
1400 | #define _VLV_PCS_DW11_CH1 0x842c | |
5ee8ee86 PZ |
1401 | #define DPIO_TX2_STAGGER_MASK(x) ((x) << 24) |
1402 | #define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3) | |
1403 | #define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1) | |
1404 | #define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0) | |
ab3c759a CML |
1405 | #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1) |
1406 | ||
570e2a74 VS |
1407 | #define _VLV_PCS01_DW11_CH0 0x022c |
1408 | #define _VLV_PCS23_DW11_CH0 0x042c | |
1409 | #define _VLV_PCS01_DW11_CH1 0x262c | |
1410 | #define _VLV_PCS23_DW11_CH1 0x282c | |
142d2eca VS |
1411 | #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1) |
1412 | #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1) | |
570e2a74 | 1413 | |
2e523e98 VS |
1414 | #define _VLV_PCS01_DW12_CH0 0x0230 |
1415 | #define _VLV_PCS23_DW12_CH0 0x0430 | |
1416 | #define _VLV_PCS01_DW12_CH1 0x2630 | |
1417 | #define _VLV_PCS23_DW12_CH1 0x2830 | |
1418 | #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1) | |
1419 | #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1) | |
1420 | ||
ab3c759a CML |
1421 | #define _VLV_PCS_DW12_CH0 0x8230 |
1422 | #define _VLV_PCS_DW12_CH1 0x8430 | |
5ee8ee86 PZ |
1423 | #define DPIO_TX2_STAGGER_MULT(x) ((x) << 20) |
1424 | #define DPIO_TX1_STAGGER_MULT(x) ((x) << 16) | |
1425 | #define DPIO_TX1_STAGGER_MASK(x) ((x) << 8) | |
1426 | #define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6) | |
1427 | #define DPIO_LANESTAGGER_STRAP(x) ((x) << 0) | |
ab3c759a CML |
1428 | #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1) |
1429 | ||
1430 | #define _VLV_PCS_DW14_CH0 0x8238 | |
1431 | #define _VLV_PCS_DW14_CH1 0x8438 | |
1432 | #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1) | |
1433 | ||
1434 | #define _VLV_PCS_DW23_CH0 0x825c | |
1435 | #define _VLV_PCS_DW23_CH1 0x845c | |
1436 | #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1) | |
1437 | ||
1438 | #define _VLV_TX_DW2_CH0 0x8288 | |
1439 | #define _VLV_TX_DW2_CH1 0x8488 | |
1fb44505 VS |
1440 | #define DPIO_SWING_MARGIN000_SHIFT 16 |
1441 | #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT) | |
9d556c99 | 1442 | #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 |
ab3c759a CML |
1443 | #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) |
1444 | ||
1445 | #define _VLV_TX_DW3_CH0 0x828c | |
1446 | #define _VLV_TX_DW3_CH1 0x848c | |
9d556c99 | 1447 | /* The following bit for CHV phy */ |
5ee8ee86 | 1448 | #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27) |
1fb44505 VS |
1449 | #define DPIO_SWING_MARGIN101_SHIFT 16 |
1450 | #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT) | |
ab3c759a CML |
1451 | #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) |
1452 | ||
1453 | #define _VLV_TX_DW4_CH0 0x8290 | |
1454 | #define _VLV_TX_DW4_CH1 0x8490 | |
9d556c99 CML |
1455 | #define DPIO_SWING_DEEMPH9P5_SHIFT 24 |
1456 | #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) | |
1fb44505 VS |
1457 | #define DPIO_SWING_DEEMPH6P0_SHIFT 16 |
1458 | #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT) | |
ab3c759a CML |
1459 | #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) |
1460 | ||
1461 | #define _VLV_TX3_DW4_CH0 0x690 | |
1462 | #define _VLV_TX3_DW4_CH1 0x2a90 | |
1463 | #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1) | |
1464 | ||
1465 | #define _VLV_TX_DW5_CH0 0x8294 | |
1466 | #define _VLV_TX_DW5_CH1 0x8494 | |
5ee8ee86 | 1467 | #define DPIO_TX_OCALINIT_EN (1 << 31) |
ab3c759a CML |
1468 | #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1) |
1469 | ||
1470 | #define _VLV_TX_DW11_CH0 0x82ac | |
1471 | #define _VLV_TX_DW11_CH1 0x84ac | |
1472 | #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1) | |
1473 | ||
1474 | #define _VLV_TX_DW14_CH0 0x82b8 | |
1475 | #define _VLV_TX_DW14_CH1 0x84b8 | |
1476 | #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1) | |
b56747aa | 1477 | |
9d556c99 CML |
1478 | /* CHV dpPhy registers */ |
1479 | #define _CHV_PLL_DW0_CH0 0x8000 | |
1480 | #define _CHV_PLL_DW0_CH1 0x8180 | |
1481 | #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1) | |
1482 | ||
1483 | #define _CHV_PLL_DW1_CH0 0x8004 | |
1484 | #define _CHV_PLL_DW1_CH1 0x8184 | |
1485 | #define DPIO_CHV_N_DIV_SHIFT 8 | |
1486 | #define DPIO_CHV_M1_DIV_BY_2 (0 << 0) | |
1487 | #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1) | |
1488 | ||
1489 | #define _CHV_PLL_DW2_CH0 0x8008 | |
1490 | #define _CHV_PLL_DW2_CH1 0x8188 | |
1491 | #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1) | |
1492 | ||
1493 | #define _CHV_PLL_DW3_CH0 0x800c | |
1494 | #define _CHV_PLL_DW3_CH1 0x818c | |
1495 | #define DPIO_CHV_FRAC_DIV_EN (1 << 16) | |
1496 | #define DPIO_CHV_FIRST_MOD (0 << 8) | |
1497 | #define DPIO_CHV_SECOND_MOD (1 << 8) | |
1498 | #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0 | |
a945ce7e | 1499 | #define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0) |
9d556c99 CML |
1500 | #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1) |
1501 | ||
1502 | #define _CHV_PLL_DW6_CH0 0x8018 | |
1503 | #define _CHV_PLL_DW6_CH1 0x8198 | |
1504 | #define DPIO_CHV_GAIN_CTRL_SHIFT 16 | |
1505 | #define DPIO_CHV_INT_COEFF_SHIFT 8 | |
1506 | #define DPIO_CHV_PROP_COEFF_SHIFT 0 | |
1507 | #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1) | |
1508 | ||
d3eee4ba VP |
1509 | #define _CHV_PLL_DW8_CH0 0x8020 |
1510 | #define _CHV_PLL_DW8_CH1 0x81A0 | |
9cbe40c1 VP |
1511 | #define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0 |
1512 | #define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0) | |
d3eee4ba VP |
1513 | #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1) |
1514 | ||
1515 | #define _CHV_PLL_DW9_CH0 0x8024 | |
1516 | #define _CHV_PLL_DW9_CH1 0x81A4 | |
1517 | #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */ | |
de3a0fde | 1518 | #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1) |
d3eee4ba VP |
1519 | #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */ |
1520 | #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1) | |
1521 | ||
6669e39f VS |
1522 | #define _CHV_CMN_DW0_CH0 0x8100 |
1523 | #define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19 | |
1524 | #define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18 | |
1525 | #define DPIO_ALLDL_POWERDOWN (1 << 1) | |
1526 | #define DPIO_ANYDL_POWERDOWN (1 << 0) | |
1527 | ||
b9e5ac3c VS |
1528 | #define _CHV_CMN_DW5_CH0 0x8114 |
1529 | #define CHV_BUFRIGHTENA1_DISABLE (0 << 20) | |
1530 | #define CHV_BUFRIGHTENA1_NORMAL (1 << 20) | |
1531 | #define CHV_BUFRIGHTENA1_FORCE (3 << 20) | |
1532 | #define CHV_BUFRIGHTENA1_MASK (3 << 20) | |
1533 | #define CHV_BUFLEFTENA1_DISABLE (0 << 22) | |
1534 | #define CHV_BUFLEFTENA1_NORMAL (1 << 22) | |
1535 | #define CHV_BUFLEFTENA1_FORCE (3 << 22) | |
1536 | #define CHV_BUFLEFTENA1_MASK (3 << 22) | |
1537 | ||
9d556c99 CML |
1538 | #define _CHV_CMN_DW13_CH0 0x8134 |
1539 | #define _CHV_CMN_DW0_CH1 0x8080 | |
1540 | #define DPIO_CHV_S1_DIV_SHIFT 21 | |
1541 | #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */ | |
1542 | #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */ | |
1543 | #define DPIO_CHV_K_DIV_SHIFT 4 | |
1544 | #define DPIO_PLL_FREQLOCK (1 << 1) | |
1545 | #define DPIO_PLL_LOCK (1 << 0) | |
1546 | #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1) | |
1547 | ||
1548 | #define _CHV_CMN_DW14_CH0 0x8138 | |
1549 | #define _CHV_CMN_DW1_CH1 0x8084 | |
1550 | #define DPIO_AFC_RECAL (1 << 14) | |
1551 | #define DPIO_DCLKP_EN (1 << 13) | |
b9e5ac3c VS |
1552 | #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */ |
1553 | #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */ | |
1554 | #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */ | |
1555 | #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */ | |
1556 | #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */ | |
1557 | #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */ | |
1558 | #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */ | |
1559 | #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */ | |
9d556c99 CML |
1560 | #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1) |
1561 | ||
9197c88b VS |
1562 | #define _CHV_CMN_DW19_CH0 0x814c |
1563 | #define _CHV_CMN_DW6_CH1 0x8098 | |
6669e39f VS |
1564 | #define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */ |
1565 | #define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */ | |
e0fce78f | 1566 | #define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */ |
9197c88b | 1567 | #define CHV_CMN_USEDCLKCHANNEL (1 << 13) |
e0fce78f | 1568 | |
9197c88b VS |
1569 | #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1) |
1570 | ||
e0fce78f VS |
1571 | #define CHV_CMN_DW28 0x8170 |
1572 | #define DPIO_CL1POWERDOWNEN (1 << 23) | |
1573 | #define DPIO_DYNPWRDOWNEN_CH0 (1 << 22) | |
ee279218 VS |
1574 | #define DPIO_SUS_CLK_CONFIG_ON (0 << 0) |
1575 | #define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0) | |
1576 | #define DPIO_SUS_CLK_CONFIG_GATE (2 << 0) | |
1577 | #define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0) | |
e0fce78f | 1578 | |
9d556c99 | 1579 | #define CHV_CMN_DW30 0x8178 |
3e288786 | 1580 | #define DPIO_CL2_LDOFUSE_PWRENB (1 << 6) |
9d556c99 CML |
1581 | #define DPIO_LRC_BYPASS (1 << 3) |
1582 | ||
1583 | #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ | |
1584 | (lane) * 0x200 + (offset)) | |
1585 | ||
f72df8db VS |
1586 | #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) |
1587 | #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) | |
1588 | #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) | |
1589 | #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c) | |
1590 | #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90) | |
1591 | #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94) | |
1592 | #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98) | |
1593 | #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c) | |
1594 | #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0) | |
1595 | #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4) | |
1596 | #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8) | |
9d556c99 CML |
1597 | #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac) |
1598 | #define DPIO_FRC_LATENCY_SHFIT 8 | |
1599 | #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) | |
1600 | #define DPIO_UPAR_SHIFT 30 | |
5c6706e5 VK |
1601 | |
1602 | /* BXT PHY registers */ | |
ed37892e ACO |
1603 | #define _BXT_PHY0_BASE 0x6C000 |
1604 | #define _BXT_PHY1_BASE 0x162000 | |
0a116ce8 ACO |
1605 | #define _BXT_PHY2_BASE 0x163000 |
1606 | #define BXT_PHY_BASE(phy) _PHY3((phy), _BXT_PHY0_BASE, \ | |
1607 | _BXT_PHY1_BASE, \ | |
1608 | _BXT_PHY2_BASE) | |
ed37892e ACO |
1609 | |
1610 | #define _BXT_PHY(phy, reg) \ | |
1611 | _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg)) | |
1612 | ||
1613 | #define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \ | |
1614 | (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \ | |
1615 | (reg_ch1) - _BXT_PHY0_BASE)) | |
1616 | #define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \ | |
1617 | _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)) | |
5c6706e5 | 1618 | |
f0f59a00 | 1619 | #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090) |
1881a423 | 1620 | #define MIPIO_RST_CTRL (1 << 2) |
5c6706e5 | 1621 | |
e93da0a0 ID |
1622 | #define _BXT_PHY_CTL_DDI_A 0x64C00 |
1623 | #define _BXT_PHY_CTL_DDI_B 0x64C10 | |
1624 | #define _BXT_PHY_CTL_DDI_C 0x64C20 | |
1625 | #define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10) | |
1626 | #define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9) | |
1627 | #define BXT_PHY_LANE_ENABLED (1 << 8) | |
1628 | #define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \ | |
1629 | _BXT_PHY_CTL_DDI_B) | |
1630 | ||
5c6706e5 VK |
1631 | #define _PHY_CTL_FAMILY_EDP 0x64C80 |
1632 | #define _PHY_CTL_FAMILY_DDI 0x64C90 | |
0a116ce8 | 1633 | #define _PHY_CTL_FAMILY_DDI_C 0x64CA0 |
5c6706e5 | 1634 | #define COMMON_RESET_DIS (1 << 31) |
0a116ce8 ACO |
1635 | #define BXT_PHY_CTL_FAMILY(phy) _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \ |
1636 | _PHY_CTL_FAMILY_EDP, \ | |
1637 | _PHY_CTL_FAMILY_DDI_C) | |
5c6706e5 | 1638 | |
dfb82408 S |
1639 | /* BXT PHY PLL registers */ |
1640 | #define _PORT_PLL_A 0x46074 | |
1641 | #define _PORT_PLL_B 0x46078 | |
1642 | #define _PORT_PLL_C 0x4607c | |
1643 | #define PORT_PLL_ENABLE (1 << 31) | |
1644 | #define PORT_PLL_LOCK (1 << 30) | |
1645 | #define PORT_PLL_REF_SEL (1 << 27) | |
f7044dd9 MC |
1646 | #define PORT_PLL_POWER_ENABLE (1 << 26) |
1647 | #define PORT_PLL_POWER_STATE (1 << 25) | |
f0f59a00 | 1648 | #define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B) |
dfb82408 S |
1649 | |
1650 | #define _PORT_PLL_EBB_0_A 0x162034 | |
1651 | #define _PORT_PLL_EBB_0_B 0x6C034 | |
1652 | #define _PORT_PLL_EBB_0_C 0x6C340 | |
aa610dcb ID |
1653 | #define PORT_PLL_P1_SHIFT 13 |
1654 | #define PORT_PLL_P1_MASK (0x07 << PORT_PLL_P1_SHIFT) | |
1655 | #define PORT_PLL_P1(x) ((x) << PORT_PLL_P1_SHIFT) | |
1656 | #define PORT_PLL_P2_SHIFT 8 | |
1657 | #define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT) | |
1658 | #define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT) | |
ed37892e ACO |
1659 | #define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
1660 | _PORT_PLL_EBB_0_B, \ | |
1661 | _PORT_PLL_EBB_0_C) | |
dfb82408 S |
1662 | |
1663 | #define _PORT_PLL_EBB_4_A 0x162038 | |
1664 | #define _PORT_PLL_EBB_4_B 0x6C038 | |
1665 | #define _PORT_PLL_EBB_4_C 0x6C344 | |
1666 | #define PORT_PLL_10BIT_CLK_ENABLE (1 << 13) | |
1667 | #define PORT_PLL_RECALIBRATE (1 << 14) | |
ed37892e ACO |
1668 | #define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
1669 | _PORT_PLL_EBB_4_B, \ | |
1670 | _PORT_PLL_EBB_4_C) | |
dfb82408 S |
1671 | |
1672 | #define _PORT_PLL_0_A 0x162100 | |
1673 | #define _PORT_PLL_0_B 0x6C100 | |
1674 | #define _PORT_PLL_0_C 0x6C380 | |
1675 | /* PORT_PLL_0_A */ | |
1676 | #define PORT_PLL_M2_MASK 0xFF | |
1677 | /* PORT_PLL_1_A */ | |
aa610dcb ID |
1678 | #define PORT_PLL_N_SHIFT 8 |
1679 | #define PORT_PLL_N_MASK (0x0F << PORT_PLL_N_SHIFT) | |
1680 | #define PORT_PLL_N(x) ((x) << PORT_PLL_N_SHIFT) | |
dfb82408 S |
1681 | /* PORT_PLL_2_A */ |
1682 | #define PORT_PLL_M2_FRAC_MASK 0x3FFFFF | |
1683 | /* PORT_PLL_3_A */ | |
1684 | #define PORT_PLL_M2_FRAC_ENABLE (1 << 16) | |
1685 | /* PORT_PLL_6_A */ | |
1686 | #define PORT_PLL_PROP_COEFF_MASK 0xF | |
1687 | #define PORT_PLL_INT_COEFF_MASK (0x1F << 8) | |
1688 | #define PORT_PLL_INT_COEFF(x) ((x) << 8) | |
1689 | #define PORT_PLL_GAIN_CTL_MASK (0x07 << 16) | |
1690 | #define PORT_PLL_GAIN_CTL(x) ((x) << 16) | |
1691 | /* PORT_PLL_8_A */ | |
1692 | #define PORT_PLL_TARGET_CNT_MASK 0x3FF | |
b6dc71f3 | 1693 | /* PORT_PLL_9_A */ |
05712c15 ID |
1694 | #define PORT_PLL_LOCK_THRESHOLD_SHIFT 1 |
1695 | #define PORT_PLL_LOCK_THRESHOLD_MASK (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT) | |
b6dc71f3 | 1696 | /* PORT_PLL_10_A */ |
5ee8ee86 | 1697 | #define PORT_PLL_DCO_AMP_OVR_EN_H (1 << 27) |
e6292556 | 1698 | #define PORT_PLL_DCO_AMP_DEFAULT 15 |
b6dc71f3 | 1699 | #define PORT_PLL_DCO_AMP_MASK 0x3c00 |
5ee8ee86 | 1700 | #define PORT_PLL_DCO_AMP(x) ((x) << 10) |
ed37892e ACO |
1701 | #define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \ |
1702 | _PORT_PLL_0_B, \ | |
1703 | _PORT_PLL_0_C) | |
1704 | #define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \ | |
1705 | (idx) * 4) | |
dfb82408 | 1706 | |
5c6706e5 VK |
1707 | /* BXT PHY common lane registers */ |
1708 | #define _PORT_CL1CM_DW0_A 0x162000 | |
1709 | #define _PORT_CL1CM_DW0_BC 0x6C000 | |
1710 | #define PHY_POWER_GOOD (1 << 16) | |
b61e7996 | 1711 | #define PHY_RESERVED (1 << 7) |
ed37892e | 1712 | #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC) |
5c6706e5 | 1713 | |
d8d4a512 VS |
1714 | #define CNL_PORT_CL1CM_DW5 _MMIO(0x162014) |
1715 | #define CL_POWER_DOWN_ENABLE (1 << 4) | |
cf54ca8b | 1716 | #define SUS_CLOCK_CONFIG (3 << 0) |
d8d4a512 | 1717 | |
ad186f3f PZ |
1718 | #define _ICL_PORT_CL_DW5_A 0x162014 |
1719 | #define _ICL_PORT_CL_DW5_B 0x6C014 | |
1720 | #define ICL_PORT_CL_DW5(port) _MMIO_PORT(port, _ICL_PORT_CL_DW5_A, \ | |
1721 | _ICL_PORT_CL_DW5_B) | |
1722 | ||
166869b3 MC |
1723 | #define _CNL_PORT_CL_DW10_A 0x162028 |
1724 | #define _ICL_PORT_CL_DW10_B 0x6c028 | |
1725 | #define ICL_PORT_CL_DW10(port) _MMIO_PORT(port, \ | |
1726 | _CNL_PORT_CL_DW10_A, \ | |
1727 | _ICL_PORT_CL_DW10_B) | |
1728 | #define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25) | |
1729 | #define PG_SEQ_DELAY_OVERRIDE_SHIFT 25 | |
1730 | #define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24) | |
1731 | #define PWR_UP_ALL_LANES (0x0 << 4) | |
1732 | #define PWR_DOWN_LN_3_2_1 (0xe << 4) | |
1733 | #define PWR_DOWN_LN_3_2 (0xc << 4) | |
1734 | #define PWR_DOWN_LN_3 (0x8 << 4) | |
1735 | #define PWR_DOWN_LN_2_1_0 (0x7 << 4) | |
1736 | #define PWR_DOWN_LN_1_0 (0x3 << 4) | |
1737 | #define PWR_DOWN_LN_1 (0x2 << 4) | |
1738 | #define PWR_DOWN_LN_3_1 (0xa << 4) | |
1739 | #define PWR_DOWN_LN_3_1_0 (0xb << 4) | |
1740 | #define PWR_DOWN_LN_MASK (0xf << 4) | |
1741 | #define PWR_DOWN_LN_SHIFT 4 | |
1742 | ||
5c6706e5 VK |
1743 | #define _PORT_CL1CM_DW9_A 0x162024 |
1744 | #define _PORT_CL1CM_DW9_BC 0x6C024 | |
1745 | #define IREF0RC_OFFSET_SHIFT 8 | |
1746 | #define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT) | |
ed37892e | 1747 | #define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC) |
5c6706e5 VK |
1748 | |
1749 | #define _PORT_CL1CM_DW10_A 0x162028 | |
1750 | #define _PORT_CL1CM_DW10_BC 0x6C028 | |
1751 | #define IREF1RC_OFFSET_SHIFT 8 | |
1752 | #define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT) | |
ed37892e | 1753 | #define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC) |
5c6706e5 | 1754 | |
67ca07e7 ID |
1755 | #define _ICL_PORT_CL_DW12_A 0x162030 |
1756 | #define _ICL_PORT_CL_DW12_B 0x6C030 | |
1757 | #define ICL_LANE_ENABLE_AUX (1 << 0) | |
1758 | #define ICL_PORT_CL_DW12(port) _MMIO_PORT((port), \ | |
1759 | _ICL_PORT_CL_DW12_A, \ | |
1760 | _ICL_PORT_CL_DW12_B) | |
1761 | ||
5c6706e5 VK |
1762 | #define _PORT_CL1CM_DW28_A 0x162070 |
1763 | #define _PORT_CL1CM_DW28_BC 0x6C070 | |
1764 | #define OCL1_POWER_DOWN_EN (1 << 23) | |
1765 | #define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22) | |
1766 | #define SUS_CLK_CONFIG 0x3 | |
ed37892e | 1767 | #define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC) |
5c6706e5 VK |
1768 | |
1769 | #define _PORT_CL1CM_DW30_A 0x162078 | |
1770 | #define _PORT_CL1CM_DW30_BC 0x6C078 | |
1771 | #define OCL2_LDOFUSE_PWR_DIS (1 << 6) | |
ed37892e | 1772 | #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC) |
5c6706e5 | 1773 | |
04416108 RV |
1774 | #define _CNL_PORT_PCS_DW1_GRP_AE 0x162304 |
1775 | #define _CNL_PORT_PCS_DW1_GRP_B 0x162384 | |
1776 | #define _CNL_PORT_PCS_DW1_GRP_C 0x162B04 | |
1777 | #define _CNL_PORT_PCS_DW1_GRP_D 0x162B84 | |
1778 | #define _CNL_PORT_PCS_DW1_GRP_F 0x162A04 | |
1779 | #define _CNL_PORT_PCS_DW1_LN0_AE 0x162404 | |
1780 | #define _CNL_PORT_PCS_DW1_LN0_B 0x162604 | |
1781 | #define _CNL_PORT_PCS_DW1_LN0_C 0x162C04 | |
1782 | #define _CNL_PORT_PCS_DW1_LN0_D 0x162E04 | |
1783 | #define _CNL_PORT_PCS_DW1_LN0_F 0x162804 | |
da9cb11f | 1784 | #define CNL_PORT_PCS_DW1_GRP(port) _MMIO(_PICK(port, \ |
04416108 RV |
1785 | _CNL_PORT_PCS_DW1_GRP_AE, \ |
1786 | _CNL_PORT_PCS_DW1_GRP_B, \ | |
1787 | _CNL_PORT_PCS_DW1_GRP_C, \ | |
1788 | _CNL_PORT_PCS_DW1_GRP_D, \ | |
1789 | _CNL_PORT_PCS_DW1_GRP_AE, \ | |
da9cb11f MK |
1790 | _CNL_PORT_PCS_DW1_GRP_F)) |
1791 | ||
1792 | #define CNL_PORT_PCS_DW1_LN0(port) _MMIO(_PICK(port, \ | |
04416108 RV |
1793 | _CNL_PORT_PCS_DW1_LN0_AE, \ |
1794 | _CNL_PORT_PCS_DW1_LN0_B, \ | |
1795 | _CNL_PORT_PCS_DW1_LN0_C, \ | |
1796 | _CNL_PORT_PCS_DW1_LN0_D, \ | |
1797 | _CNL_PORT_PCS_DW1_LN0_AE, \ | |
da9cb11f | 1798 | _CNL_PORT_PCS_DW1_LN0_F)) |
d61d1b3b | 1799 | |
5bb975de MN |
1800 | #define _ICL_PORT_PCS_DW1_GRP_A 0x162604 |
1801 | #define _ICL_PORT_PCS_DW1_GRP_B 0x6C604 | |
1802 | #define _ICL_PORT_PCS_DW1_LN0_A 0x162804 | |
1803 | #define _ICL_PORT_PCS_DW1_LN0_B 0x6C804 | |
d61d1b3b MC |
1804 | #define _ICL_PORT_PCS_DW1_AUX_A 0x162304 |
1805 | #define _ICL_PORT_PCS_DW1_AUX_B 0x6c304 | |
5bb975de MN |
1806 | #define ICL_PORT_PCS_DW1_GRP(port) _MMIO_PORT(port,\ |
1807 | _ICL_PORT_PCS_DW1_GRP_A, \ | |
1808 | _ICL_PORT_PCS_DW1_GRP_B) | |
1809 | #define ICL_PORT_PCS_DW1_LN0(port) _MMIO_PORT(port, \ | |
1810 | _ICL_PORT_PCS_DW1_LN0_A, \ | |
1811 | _ICL_PORT_PCS_DW1_LN0_B) | |
d61d1b3b MC |
1812 | #define ICL_PORT_PCS_DW1_AUX(port) _MMIO_PORT(port, \ |
1813 | _ICL_PORT_PCS_DW1_AUX_A, \ | |
1814 | _ICL_PORT_PCS_DW1_AUX_B) | |
04416108 RV |
1815 | #define COMMON_KEEPER_EN (1 << 26) |
1816 | ||
4635b573 MK |
1817 | /* CNL Port TX registers */ |
1818 | #define _CNL_PORT_TX_AE_GRP_OFFSET 0x162340 | |
1819 | #define _CNL_PORT_TX_B_GRP_OFFSET 0x1623C0 | |
1820 | #define _CNL_PORT_TX_C_GRP_OFFSET 0x162B40 | |
1821 | #define _CNL_PORT_TX_D_GRP_OFFSET 0x162BC0 | |
1822 | #define _CNL_PORT_TX_F_GRP_OFFSET 0x162A40 | |
1823 | #define _CNL_PORT_TX_AE_LN0_OFFSET 0x162440 | |
1824 | #define _CNL_PORT_TX_B_LN0_OFFSET 0x162640 | |
1825 | #define _CNL_PORT_TX_C_LN0_OFFSET 0x162C40 | |
1826 | #define _CNL_PORT_TX_D_LN0_OFFSET 0x162E40 | |
1827 | #define _CNL_PORT_TX_F_LN0_OFFSET 0x162840 | |
1828 | #define _CNL_PORT_TX_DW_GRP(port, dw) (_PICK((port), \ | |
1829 | _CNL_PORT_TX_AE_GRP_OFFSET, \ | |
1830 | _CNL_PORT_TX_B_GRP_OFFSET, \ | |
1831 | _CNL_PORT_TX_B_GRP_OFFSET, \ | |
1832 | _CNL_PORT_TX_D_GRP_OFFSET, \ | |
1833 | _CNL_PORT_TX_AE_GRP_OFFSET, \ | |
1834 | _CNL_PORT_TX_F_GRP_OFFSET) + \ | |
5ee8ee86 | 1835 | 4 * (dw)) |
4635b573 MK |
1836 | #define _CNL_PORT_TX_DW_LN0(port, dw) (_PICK((port), \ |
1837 | _CNL_PORT_TX_AE_LN0_OFFSET, \ | |
1838 | _CNL_PORT_TX_B_LN0_OFFSET, \ | |
1839 | _CNL_PORT_TX_B_LN0_OFFSET, \ | |
1840 | _CNL_PORT_TX_D_LN0_OFFSET, \ | |
1841 | _CNL_PORT_TX_AE_LN0_OFFSET, \ | |
1842 | _CNL_PORT_TX_F_LN0_OFFSET) + \ | |
5ee8ee86 | 1843 | 4 * (dw)) |
4635b573 MK |
1844 | |
1845 | #define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 2)) | |
1846 | #define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 2)) | |
5bb975de MN |
1847 | #define _ICL_PORT_TX_DW2_GRP_A 0x162688 |
1848 | #define _ICL_PORT_TX_DW2_GRP_B 0x6C688 | |
1849 | #define _ICL_PORT_TX_DW2_LN0_A 0x162888 | |
1850 | #define _ICL_PORT_TX_DW2_LN0_B 0x6C888 | |
d61d1b3b MC |
1851 | #define _ICL_PORT_TX_DW2_AUX_A 0x162388 |
1852 | #define _ICL_PORT_TX_DW2_AUX_B 0x6c388 | |
5bb975de MN |
1853 | #define ICL_PORT_TX_DW2_GRP(port) _MMIO_PORT(port, \ |
1854 | _ICL_PORT_TX_DW2_GRP_A, \ | |
1855 | _ICL_PORT_TX_DW2_GRP_B) | |
1856 | #define ICL_PORT_TX_DW2_LN0(port) _MMIO_PORT(port, \ | |
1857 | _ICL_PORT_TX_DW2_LN0_A, \ | |
1858 | _ICL_PORT_TX_DW2_LN0_B) | |
d61d1b3b MC |
1859 | #define ICL_PORT_TX_DW2_AUX(port) _MMIO_PORT(port, \ |
1860 | _ICL_PORT_TX_DW2_AUX_A, \ | |
1861 | _ICL_PORT_TX_DW2_AUX_B) | |
7487508e | 1862 | #define SWING_SEL_UPPER(x) (((x) >> 3) << 15) |
1f588aeb | 1863 | #define SWING_SEL_UPPER_MASK (1 << 15) |
7487508e | 1864 | #define SWING_SEL_LOWER(x) (((x) & 0x7) << 11) |
1f588aeb | 1865 | #define SWING_SEL_LOWER_MASK (0x7 << 11) |
d61d1b3b MC |
1866 | #define FRC_LATENCY_OPTIM_MASK (0x7 << 8) |
1867 | #define FRC_LATENCY_OPTIM_VAL(x) ((x) << 8) | |
04416108 | 1868 | #define RCOMP_SCALAR(x) ((x) << 0) |
1f588aeb | 1869 | #define RCOMP_SCALAR_MASK (0xFF << 0) |
04416108 | 1870 | |
04416108 RV |
1871 | #define _CNL_PORT_TX_DW4_LN0_AE 0x162450 |
1872 | #define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0 | |
4635b573 MK |
1873 | #define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 4)) |
1874 | #define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4)) | |
1875 | #define CNL_PORT_TX_DW4_LN(port, ln) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4) + \ | |
9e8789ec | 1876 | ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \ |
4635b573 | 1877 | _CNL_PORT_TX_DW4_LN0_AE))) |
5bb975de MN |
1878 | #define _ICL_PORT_TX_DW4_GRP_A 0x162690 |
1879 | #define _ICL_PORT_TX_DW4_GRP_B 0x6C690 | |
1880 | #define _ICL_PORT_TX_DW4_LN0_A 0x162890 | |
1881 | #define _ICL_PORT_TX_DW4_LN1_A 0x162990 | |
1882 | #define _ICL_PORT_TX_DW4_LN0_B 0x6C890 | |
d61d1b3b MC |
1883 | #define _ICL_PORT_TX_DW4_AUX_A 0x162390 |
1884 | #define _ICL_PORT_TX_DW4_AUX_B 0x6c390 | |
5bb975de MN |
1885 | #define ICL_PORT_TX_DW4_GRP(port) _MMIO_PORT(port, \ |
1886 | _ICL_PORT_TX_DW4_GRP_A, \ | |
1887 | _ICL_PORT_TX_DW4_GRP_B) | |
1888 | #define ICL_PORT_TX_DW4_LN(port, ln) _MMIO(_PORT(port, \ | |
1889 | _ICL_PORT_TX_DW4_LN0_A, \ | |
1890 | _ICL_PORT_TX_DW4_LN0_B) + \ | |
9e8789ec PZ |
1891 | ((ln) * (_ICL_PORT_TX_DW4_LN1_A - \ |
1892 | _ICL_PORT_TX_DW4_LN0_A))) | |
d61d1b3b MC |
1893 | #define ICL_PORT_TX_DW4_AUX(port) _MMIO_PORT(port, \ |
1894 | _ICL_PORT_TX_DW4_AUX_A, \ | |
1895 | _ICL_PORT_TX_DW4_AUX_B) | |
04416108 RV |
1896 | #define LOADGEN_SELECT (1 << 31) |
1897 | #define POST_CURSOR_1(x) ((x) << 12) | |
1f588aeb | 1898 | #define POST_CURSOR_1_MASK (0x3F << 12) |
04416108 | 1899 | #define POST_CURSOR_2(x) ((x) << 6) |
1f588aeb | 1900 | #define POST_CURSOR_2_MASK (0x3F << 6) |
04416108 | 1901 | #define CURSOR_COEFF(x) ((x) << 0) |
fcace3b9 | 1902 | #define CURSOR_COEFF_MASK (0x3F << 0) |
04416108 | 1903 | |
4635b573 MK |
1904 | #define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 5)) |
1905 | #define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 5)) | |
5bb975de MN |
1906 | #define _ICL_PORT_TX_DW5_GRP_A 0x162694 |
1907 | #define _ICL_PORT_TX_DW5_GRP_B 0x6C694 | |
1908 | #define _ICL_PORT_TX_DW5_LN0_A 0x162894 | |
1909 | #define _ICL_PORT_TX_DW5_LN0_B 0x6C894 | |
d61d1b3b MC |
1910 | #define _ICL_PORT_TX_DW5_AUX_A 0x162394 |
1911 | #define _ICL_PORT_TX_DW5_AUX_B 0x6c394 | |
5bb975de MN |
1912 | #define ICL_PORT_TX_DW5_GRP(port) _MMIO_PORT(port, \ |
1913 | _ICL_PORT_TX_DW5_GRP_A, \ | |
1914 | _ICL_PORT_TX_DW5_GRP_B) | |
1915 | #define ICL_PORT_TX_DW5_LN0(port) _MMIO_PORT(port, \ | |
1916 | _ICL_PORT_TX_DW5_LN0_A, \ | |
1917 | _ICL_PORT_TX_DW5_LN0_B) | |
d61d1b3b MC |
1918 | #define ICL_PORT_TX_DW5_AUX(port) _MMIO_PORT(port, \ |
1919 | _ICL_PORT_TX_DW5_AUX_A, \ | |
1920 | _ICL_PORT_TX_DW5_AUX_B) | |
04416108 | 1921 | #define TX_TRAINING_EN (1 << 31) |
5bb975de | 1922 | #define TAP2_DISABLE (1 << 30) |
04416108 RV |
1923 | #define TAP3_DISABLE (1 << 29) |
1924 | #define SCALING_MODE_SEL(x) ((x) << 18) | |
1f588aeb | 1925 | #define SCALING_MODE_SEL_MASK (0x7 << 18) |
04416108 | 1926 | #define RTERM_SELECT(x) ((x) << 3) |
1f588aeb | 1927 | #define RTERM_SELECT_MASK (0x7 << 3) |
04416108 | 1928 | |
4635b573 MK |
1929 | #define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7)) |
1930 | #define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7)) | |
04416108 | 1931 | #define N_SCALAR(x) ((x) << 24) |
1f588aeb | 1932 | #define N_SCALAR_MASK (0x7F << 24) |
04416108 | 1933 | |
c92f47b5 MN |
1934 | #define _ICL_MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \ |
1935 | _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1))) | |
1936 | ||
1937 | #define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C | |
1938 | #define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C | |
1939 | #define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C | |
1940 | #define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C | |
1941 | #define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C | |
1942 | #define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C | |
1943 | #define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C | |
1944 | #define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C | |
1945 | #define ICL_PORT_MG_TX1_LINK_PARAMS(port, ln) \ | |
1946 | _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT1, \ | |
1947 | _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT2, \ | |
1948 | _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT1) | |
1949 | ||
1950 | #define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC | |
1951 | #define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC | |
1952 | #define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC | |
1953 | #define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC | |
1954 | #define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC | |
1955 | #define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC | |
1956 | #define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC | |
1957 | #define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC | |
1958 | #define ICL_PORT_MG_TX2_LINK_PARAMS(port, ln) \ | |
1959 | _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT1, \ | |
1960 | _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT2, \ | |
1961 | _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT1) | |
1962 | #define CRI_USE_FS32 (1 << 5) | |
1963 | ||
1964 | #define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C | |
1965 | #define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C | |
1966 | #define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C | |
1967 | #define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C | |
1968 | #define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C | |
1969 | #define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C | |
1970 | #define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C | |
1971 | #define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C | |
1972 | #define ICL_PORT_MG_TX1_PISO_READLOAD(port, ln) \ | |
1973 | _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT1, \ | |
1974 | _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT2, \ | |
1975 | _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT1) | |
1976 | ||
1977 | #define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC | |
1978 | #define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC | |
1979 | #define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC | |
1980 | #define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC | |
1981 | #define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC | |
1982 | #define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC | |
1983 | #define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC | |
1984 | #define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC | |
1985 | #define ICL_PORT_MG_TX2_PISO_READLOAD(port, ln) \ | |
1986 | _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT1, \ | |
1987 | _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT2, \ | |
1988 | _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT1) | |
1989 | #define CRI_CALCINIT (1 << 1) | |
1990 | ||
1991 | #define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148 | |
1992 | #define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548 | |
1993 | #define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148 | |
1994 | #define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548 | |
1995 | #define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148 | |
1996 | #define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548 | |
1997 | #define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148 | |
1998 | #define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548 | |
1999 | #define ICL_PORT_MG_TX1_SWINGCTRL(port, ln) \ | |
2000 | _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT1, \ | |
2001 | _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT2, \ | |
2002 | _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT1) | |
2003 | ||
2004 | #define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8 | |
2005 | #define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8 | |
2006 | #define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8 | |
2007 | #define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8 | |
2008 | #define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8 | |
2009 | #define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8 | |
2010 | #define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8 | |
2011 | #define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8 | |
2012 | #define ICL_PORT_MG_TX2_SWINGCTRL(port, ln) \ | |
2013 | _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT1, \ | |
2014 | _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT2, \ | |
2015 | _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT1) | |
2016 | #define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0) | |
2017 | #define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0) | |
2018 | ||
2019 | #define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT1 0x168144 | |
2020 | #define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT1 0x168544 | |
2021 | #define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT2 0x169144 | |
2022 | #define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT2 0x169544 | |
2023 | #define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT3 0x16A144 | |
2024 | #define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT3 0x16A544 | |
2025 | #define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT4 0x16B144 | |
2026 | #define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT4 0x16B544 | |
2027 | #define ICL_PORT_MG_TX1_DRVCTRL(port, ln) \ | |
2028 | _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_DRVCTRL_TX1LN0_PORT1, \ | |
2029 | _ICL_MG_TX_DRVCTRL_TX1LN0_PORT2, \ | |
2030 | _ICL_MG_TX_DRVCTRL_TX1LN1_PORT1) | |
2031 | ||
2032 | #define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4 | |
2033 | #define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4 | |
2034 | #define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4 | |
2035 | #define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4 | |
2036 | #define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4 | |
2037 | #define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4 | |
2038 | #define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4 | |
2039 | #define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4 | |
2040 | #define ICL_PORT_MG_TX2_DRVCTRL(port, ln) \ | |
2041 | _ICL_MG_PHY_PORT_LN(port, ln, _ICL_MG_TX_DRVCTRL_TX2LN0_PORT1, \ | |
2042 | _ICL_MG_TX_DRVCTRL_TX2LN0_PORT2, \ | |
2043 | _ICL_MG_TX_DRVCTRL_TX2LN1_PORT1) | |
2044 | #define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24) | |
2045 | #define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24) | |
2046 | #define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22) | |
2047 | #define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16) | |
2048 | #define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16) | |
2049 | ||
842d4166 ACO |
2050 | /* The spec defines this only for BXT PHY0, but lets assume that this |
2051 | * would exist for PHY1 too if it had a second channel. | |
2052 | */ | |
2053 | #define _PORT_CL2CM_DW6_A 0x162358 | |
2054 | #define _PORT_CL2CM_DW6_BC 0x6C358 | |
ed37892e | 2055 | #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC) |
5c6706e5 VK |
2056 | #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28) |
2057 | ||
d8d4a512 VS |
2058 | #define CNL_PORT_COMP_DW0 _MMIO(0x162100) |
2059 | #define COMP_INIT (1 << 31) | |
2060 | #define CNL_PORT_COMP_DW1 _MMIO(0x162104) | |
2061 | #define CNL_PORT_COMP_DW3 _MMIO(0x16210c) | |
2062 | #define PROCESS_INFO_DOT_0 (0 << 26) | |
2063 | #define PROCESS_INFO_DOT_1 (1 << 26) | |
2064 | #define PROCESS_INFO_DOT_4 (2 << 26) | |
2065 | #define PROCESS_INFO_MASK (7 << 26) | |
2066 | #define PROCESS_INFO_SHIFT 26 | |
2067 | #define VOLTAGE_INFO_0_85V (0 << 24) | |
2068 | #define VOLTAGE_INFO_0_95V (1 << 24) | |
2069 | #define VOLTAGE_INFO_1_05V (2 << 24) | |
2070 | #define VOLTAGE_INFO_MASK (3 << 24) | |
2071 | #define VOLTAGE_INFO_SHIFT 24 | |
2072 | #define CNL_PORT_COMP_DW9 _MMIO(0x162124) | |
2073 | #define CNL_PORT_COMP_DW10 _MMIO(0x162128) | |
2074 | ||
62d4a5e1 PZ |
2075 | #define _ICL_PORT_COMP_DW0_A 0x162100 |
2076 | #define _ICL_PORT_COMP_DW0_B 0x6C100 | |
2077 | #define ICL_PORT_COMP_DW0(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW0_A, \ | |
2078 | _ICL_PORT_COMP_DW0_B) | |
2079 | #define _ICL_PORT_COMP_DW1_A 0x162104 | |
2080 | #define _ICL_PORT_COMP_DW1_B 0x6C104 | |
2081 | #define ICL_PORT_COMP_DW1(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW1_A, \ | |
2082 | _ICL_PORT_COMP_DW1_B) | |
2083 | #define _ICL_PORT_COMP_DW3_A 0x16210C | |
2084 | #define _ICL_PORT_COMP_DW3_B 0x6C10C | |
2085 | #define ICL_PORT_COMP_DW3(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW3_A, \ | |
2086 | _ICL_PORT_COMP_DW3_B) | |
2087 | #define _ICL_PORT_COMP_DW9_A 0x162124 | |
2088 | #define _ICL_PORT_COMP_DW9_B 0x6C124 | |
2089 | #define ICL_PORT_COMP_DW9(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW9_A, \ | |
2090 | _ICL_PORT_COMP_DW9_B) | |
2091 | #define _ICL_PORT_COMP_DW10_A 0x162128 | |
2092 | #define _ICL_PORT_COMP_DW10_B 0x6C128 | |
2093 | #define ICL_PORT_COMP_DW10(port) _MMIO_PORT(port, \ | |
2094 | _ICL_PORT_COMP_DW10_A, \ | |
2095 | _ICL_PORT_COMP_DW10_B) | |
2096 | ||
a2bc69a1 MN |
2097 | /* ICL PHY DFLEX registers */ |
2098 | #define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0) | |
2099 | #define DFLEXDPMLE1_DPMLETC_MASK(n) (0xf << (4 * (n))) | |
2100 | #define DFLEXDPMLE1_DPMLETC(n, x) ((x) << (4 * (n))) | |
2101 | ||
5c6706e5 VK |
2102 | /* BXT PHY Ref registers */ |
2103 | #define _PORT_REF_DW3_A 0x16218C | |
2104 | #define _PORT_REF_DW3_BC 0x6C18C | |
2105 | #define GRC_DONE (1 << 22) | |
ed37892e | 2106 | #define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC) |
5c6706e5 VK |
2107 | |
2108 | #define _PORT_REF_DW6_A 0x162198 | |
2109 | #define _PORT_REF_DW6_BC 0x6C198 | |
d1e082ff ID |
2110 | #define GRC_CODE_SHIFT 24 |
2111 | #define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT) | |
5c6706e5 | 2112 | #define GRC_CODE_FAST_SHIFT 16 |
d1e082ff | 2113 | #define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT) |
5c6706e5 VK |
2114 | #define GRC_CODE_SLOW_SHIFT 8 |
2115 | #define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT) | |
2116 | #define GRC_CODE_NOM_MASK 0xFF | |
ed37892e | 2117 | #define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC) |
5c6706e5 VK |
2118 | |
2119 | #define _PORT_REF_DW8_A 0x1621A0 | |
2120 | #define _PORT_REF_DW8_BC 0x6C1A0 | |
2121 | #define GRC_DIS (1 << 15) | |
2122 | #define GRC_RDY_OVRD (1 << 1) | |
ed37892e | 2123 | #define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC) |
5c6706e5 | 2124 | |
dfb82408 | 2125 | /* BXT PHY PCS registers */ |
96fb9f9b VK |
2126 | #define _PORT_PCS_DW10_LN01_A 0x162428 |
2127 | #define _PORT_PCS_DW10_LN01_B 0x6C428 | |
2128 | #define _PORT_PCS_DW10_LN01_C 0x6C828 | |
2129 | #define _PORT_PCS_DW10_GRP_A 0x162C28 | |
2130 | #define _PORT_PCS_DW10_GRP_B 0x6CC28 | |
2131 | #define _PORT_PCS_DW10_GRP_C 0x6CE28 | |
ed37892e ACO |
2132 | #define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
2133 | _PORT_PCS_DW10_LN01_B, \ | |
2134 | _PORT_PCS_DW10_LN01_C) | |
2135 | #define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ | |
2136 | _PORT_PCS_DW10_GRP_B, \ | |
2137 | _PORT_PCS_DW10_GRP_C) | |
2138 | ||
96fb9f9b VK |
2139 | #define TX2_SWING_CALC_INIT (1 << 31) |
2140 | #define TX1_SWING_CALC_INIT (1 << 30) | |
2141 | ||
dfb82408 S |
2142 | #define _PORT_PCS_DW12_LN01_A 0x162430 |
2143 | #define _PORT_PCS_DW12_LN01_B 0x6C430 | |
2144 | #define _PORT_PCS_DW12_LN01_C 0x6C830 | |
2145 | #define _PORT_PCS_DW12_LN23_A 0x162630 | |
2146 | #define _PORT_PCS_DW12_LN23_B 0x6C630 | |
2147 | #define _PORT_PCS_DW12_LN23_C 0x6CA30 | |
2148 | #define _PORT_PCS_DW12_GRP_A 0x162c30 | |
2149 | #define _PORT_PCS_DW12_GRP_B 0x6CC30 | |
2150 | #define _PORT_PCS_DW12_GRP_C 0x6CE30 | |
2151 | #define LANESTAGGER_STRAP_OVRD (1 << 6) | |
2152 | #define LANE_STAGGER_MASK 0x1F | |
ed37892e ACO |
2153 | #define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
2154 | _PORT_PCS_DW12_LN01_B, \ | |
2155 | _PORT_PCS_DW12_LN01_C) | |
2156 | #define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ | |
2157 | _PORT_PCS_DW12_LN23_B, \ | |
2158 | _PORT_PCS_DW12_LN23_C) | |
2159 | #define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ | |
2160 | _PORT_PCS_DW12_GRP_B, \ | |
2161 | _PORT_PCS_DW12_GRP_C) | |
dfb82408 | 2162 | |
5c6706e5 VK |
2163 | /* BXT PHY TX registers */ |
2164 | #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \ | |
2165 | ((lane) & 1) * 0x80) | |
2166 | ||
96fb9f9b VK |
2167 | #define _PORT_TX_DW2_LN0_A 0x162508 |
2168 | #define _PORT_TX_DW2_LN0_B 0x6C508 | |
2169 | #define _PORT_TX_DW2_LN0_C 0x6C908 | |
2170 | #define _PORT_TX_DW2_GRP_A 0x162D08 | |
2171 | #define _PORT_TX_DW2_GRP_B 0x6CD08 | |
2172 | #define _PORT_TX_DW2_GRP_C 0x6CF08 | |
ed37892e ACO |
2173 | #define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
2174 | _PORT_TX_DW2_LN0_B, \ | |
2175 | _PORT_TX_DW2_LN0_C) | |
2176 | #define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ | |
2177 | _PORT_TX_DW2_GRP_B, \ | |
2178 | _PORT_TX_DW2_GRP_C) | |
96fb9f9b VK |
2179 | #define MARGIN_000_SHIFT 16 |
2180 | #define MARGIN_000 (0xFF << MARGIN_000_SHIFT) | |
2181 | #define UNIQ_TRANS_SCALE_SHIFT 8 | |
2182 | #define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT) | |
2183 | ||
2184 | #define _PORT_TX_DW3_LN0_A 0x16250C | |
2185 | #define _PORT_TX_DW3_LN0_B 0x6C50C | |
2186 | #define _PORT_TX_DW3_LN0_C 0x6C90C | |
2187 | #define _PORT_TX_DW3_GRP_A 0x162D0C | |
2188 | #define _PORT_TX_DW3_GRP_B 0x6CD0C | |
2189 | #define _PORT_TX_DW3_GRP_C 0x6CF0C | |
ed37892e ACO |
2190 | #define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
2191 | _PORT_TX_DW3_LN0_B, \ | |
2192 | _PORT_TX_DW3_LN0_C) | |
2193 | #define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ | |
2194 | _PORT_TX_DW3_GRP_B, \ | |
2195 | _PORT_TX_DW3_GRP_C) | |
9c58a049 SJ |
2196 | #define SCALE_DCOMP_METHOD (1 << 26) |
2197 | #define UNIQUE_TRANGE_EN_METHOD (1 << 27) | |
96fb9f9b VK |
2198 | |
2199 | #define _PORT_TX_DW4_LN0_A 0x162510 | |
2200 | #define _PORT_TX_DW4_LN0_B 0x6C510 | |
2201 | #define _PORT_TX_DW4_LN0_C 0x6C910 | |
2202 | #define _PORT_TX_DW4_GRP_A 0x162D10 | |
2203 | #define _PORT_TX_DW4_GRP_B 0x6CD10 | |
2204 | #define _PORT_TX_DW4_GRP_C 0x6CF10 | |
ed37892e ACO |
2205 | #define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
2206 | _PORT_TX_DW4_LN0_B, \ | |
2207 | _PORT_TX_DW4_LN0_C) | |
2208 | #define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ | |
2209 | _PORT_TX_DW4_GRP_B, \ | |
2210 | _PORT_TX_DW4_GRP_C) | |
96fb9f9b VK |
2211 | #define DEEMPH_SHIFT 24 |
2212 | #define DE_EMPHASIS (0xFF << DEEMPH_SHIFT) | |
2213 | ||
51b3ee35 ACO |
2214 | #define _PORT_TX_DW5_LN0_A 0x162514 |
2215 | #define _PORT_TX_DW5_LN0_B 0x6C514 | |
2216 | #define _PORT_TX_DW5_LN0_C 0x6C914 | |
2217 | #define _PORT_TX_DW5_GRP_A 0x162D14 | |
2218 | #define _PORT_TX_DW5_GRP_B 0x6CD14 | |
2219 | #define _PORT_TX_DW5_GRP_C 0x6CF14 | |
2220 | #define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ | |
2221 | _PORT_TX_DW5_LN0_B, \ | |
2222 | _PORT_TX_DW5_LN0_C) | |
2223 | #define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ | |
2224 | _PORT_TX_DW5_GRP_B, \ | |
2225 | _PORT_TX_DW5_GRP_C) | |
2226 | #define DCC_DELAY_RANGE_1 (1 << 9) | |
2227 | #define DCC_DELAY_RANGE_2 (1 << 8) | |
2228 | ||
5c6706e5 VK |
2229 | #define _PORT_TX_DW14_LN0_A 0x162538 |
2230 | #define _PORT_TX_DW14_LN0_B 0x6C538 | |
2231 | #define _PORT_TX_DW14_LN0_C 0x6C938 | |
2232 | #define LATENCY_OPTIM_SHIFT 30 | |
2233 | #define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT) | |
ed37892e ACO |
2234 | #define BXT_PORT_TX_DW14_LN(phy, ch, lane) \ |
2235 | _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \ | |
2236 | _PORT_TX_DW14_LN0_C) + \ | |
2237 | _BXT_LANE_OFFSET(lane)) | |
5c6706e5 | 2238 | |
f8896f5d | 2239 | /* UAIMI scratch pad register 1 */ |
f0f59a00 | 2240 | #define UAIMI_SPR1 _MMIO(0x4F074) |
f8896f5d DW |
2241 | /* SKL VccIO mask */ |
2242 | #define SKL_VCCIO_MASK 0x1 | |
2243 | /* SKL balance leg register */ | |
f0f59a00 | 2244 | #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C) |
f8896f5d | 2245 | /* I_boost values */ |
5ee8ee86 PZ |
2246 | #define BALANCE_LEG_SHIFT(port) (8 + 3 * (port)) |
2247 | #define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port))) | |
f8896f5d DW |
2248 | /* Balance leg disable bits */ |
2249 | #define BALANCE_LEG_DISABLE_SHIFT 23 | |
a7d8dbc0 | 2250 | #define BALANCE_LEG_DISABLE(port) (1 << (23 + (port))) |
f8896f5d | 2251 | |
585fb111 | 2252 | /* |
de151cf6 | 2253 | * Fence registers |
eecf613a VS |
2254 | * [0-7] @ 0x2000 gen2,gen3 |
2255 | * [8-15] @ 0x3000 945,g33,pnv | |
2256 | * | |
2257 | * [0-15] @ 0x3000 gen4,gen5 | |
2258 | * | |
2259 | * [0-15] @ 0x100000 gen6,vlv,chv | |
2260 | * [0-31] @ 0x100000 gen7+ | |
585fb111 | 2261 | */ |
f0f59a00 | 2262 | #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4) |
de151cf6 JB |
2263 | #define I830_FENCE_START_MASK 0x07f80000 |
2264 | #define I830_FENCE_TILING_Y_SHIFT 12 | |
0f973f27 | 2265 | #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) |
de151cf6 | 2266 | #define I830_FENCE_PITCH_SHIFT 4 |
5ee8ee86 | 2267 | #define I830_FENCE_REG_VALID (1 << 0) |
c36a2a6d | 2268 | #define I915_FENCE_MAX_PITCH_VAL 4 |
e76a16de | 2269 | #define I830_FENCE_MAX_PITCH_VAL 6 |
5ee8ee86 | 2270 | #define I830_FENCE_MAX_SIZE_VAL (1 << 8) |
de151cf6 JB |
2271 | |
2272 | #define I915_FENCE_START_MASK 0x0ff00000 | |
0f973f27 | 2273 | #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) |
585fb111 | 2274 | |
f0f59a00 VS |
2275 | #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8) |
2276 | #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4) | |
de151cf6 JB |
2277 | #define I965_FENCE_PITCH_SHIFT 2 |
2278 | #define I965_FENCE_TILING_Y_SHIFT 1 | |
5ee8ee86 | 2279 | #define I965_FENCE_REG_VALID (1 << 0) |
8d7773a3 | 2280 | #define I965_FENCE_MAX_PITCH_VAL 0x0400 |
de151cf6 | 2281 | |
f0f59a00 VS |
2282 | #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8) |
2283 | #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4) | |
eecf613a | 2284 | #define GEN6_FENCE_PITCH_SHIFT 32 |
3a062478 | 2285 | #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 |
4e901fdc | 2286 | |
2b6b3a09 | 2287 | |
f691e2f4 | 2288 | /* control register for cpu gtt access */ |
f0f59a00 | 2289 | #define TILECTL _MMIO(0x101000) |
f691e2f4 | 2290 | #define TILECTL_SWZCTL (1 << 0) |
e3a29055 | 2291 | #define TILECTL_TLBPF (1 << 1) |
f691e2f4 DV |
2292 | #define TILECTL_TLB_PREFETCH_DIS (1 << 2) |
2293 | #define TILECTL_BACKSNOOP_DIS (1 << 3) | |
2294 | ||
de151cf6 JB |
2295 | /* |
2296 | * Instruction and interrupt control regs | |
2297 | */ | |
f0f59a00 | 2298 | #define PGTBL_CTL _MMIO(0x02020) |
f1e1c212 VS |
2299 | #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ |
2300 | #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ | |
f0f59a00 | 2301 | #define PGTBL_ER _MMIO(0x02024) |
5ee8ee86 PZ |
2302 | #define PRB0_BASE (0x2030 - 0x30) |
2303 | #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */ | |
2304 | #define PRB2_BASE (0x2050 - 0x30) /* gen3 */ | |
2305 | #define SRB0_BASE (0x2100 - 0x30) /* gen2 */ | |
2306 | #define SRB1_BASE (0x2110 - 0x30) /* gen2 */ | |
2307 | #define SRB2_BASE (0x2120 - 0x30) /* 830 */ | |
2308 | #define SRB3_BASE (0x2130 - 0x30) /* 830 */ | |
333e9fe9 DV |
2309 | #define RENDER_RING_BASE 0x02000 |
2310 | #define BSD_RING_BASE 0x04000 | |
2311 | #define GEN6_BSD_RING_BASE 0x12000 | |
845f74a7 | 2312 | #define GEN8_BSD2_RING_BASE 0x1c000 |
5f79e7c6 OM |
2313 | #define GEN11_BSD_RING_BASE 0x1c0000 |
2314 | #define GEN11_BSD2_RING_BASE 0x1c4000 | |
2315 | #define GEN11_BSD3_RING_BASE 0x1d0000 | |
2316 | #define GEN11_BSD4_RING_BASE 0x1d4000 | |
1950de14 | 2317 | #define VEBOX_RING_BASE 0x1a000 |
5f79e7c6 OM |
2318 | #define GEN11_VEBOX_RING_BASE 0x1c8000 |
2319 | #define GEN11_VEBOX2_RING_BASE 0x1d8000 | |
549f7365 | 2320 | #define BLT_RING_BASE 0x22000 |
5ee8ee86 PZ |
2321 | #define RING_TAIL(base) _MMIO((base) + 0x30) |
2322 | #define RING_HEAD(base) _MMIO((base) + 0x34) | |
2323 | #define RING_START(base) _MMIO((base) + 0x38) | |
2324 | #define RING_CTL(base) _MMIO((base) + 0x3c) | |
62ae14b1 | 2325 | #define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */ |
5ee8ee86 PZ |
2326 | #define RING_SYNC_0(base) _MMIO((base) + 0x40) |
2327 | #define RING_SYNC_1(base) _MMIO((base) + 0x44) | |
2328 | #define RING_SYNC_2(base) _MMIO((base) + 0x48) | |
1950de14 BW |
2329 | #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE)) |
2330 | #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE)) | |
2331 | #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE)) | |
2332 | #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE)) | |
2333 | #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE)) | |
2334 | #define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE)) | |
2335 | #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE)) | |
2336 | #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE)) | |
2337 | #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE)) | |
2338 | #define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE)) | |
2339 | #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE)) | |
2340 | #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE)) | |
f0f59a00 | 2341 | #define GEN6_NOSYNC INVALID_MMIO_REG |
5ee8ee86 PZ |
2342 | #define RING_PSMI_CTL(base) _MMIO((base) + 0x50) |
2343 | #define RING_MAX_IDLE(base) _MMIO((base) + 0x54) | |
2344 | #define RING_HWS_PGA(base) _MMIO((base) + 0x80) | |
2345 | #define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080) | |
2346 | #define RING_RESET_CTL(base) _MMIO((base) + 0xd0) | |
7fd2d269 MK |
2347 | #define RESET_CTL_REQUEST_RESET (1 << 0) |
2348 | #define RESET_CTL_READY_TO_RESET (1 << 1) | |
39e78234 | 2349 | #define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c) |
9e72b46c | 2350 | |
f0f59a00 | 2351 | #define HSW_GTT_CACHE_EN _MMIO(0x4024) |
6d50b065 | 2352 | #define GTT_CACHE_EN_ALL 0xF0007FFF |
f0f59a00 VS |
2353 | #define GEN7_WR_WATERMARK _MMIO(0x4028) |
2354 | #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C) | |
2355 | #define ARB_MODE _MMIO(0x4030) | |
5ee8ee86 PZ |
2356 | #define ARB_MODE_SWIZZLE_SNB (1 << 4) |
2357 | #define ARB_MODE_SWIZZLE_IVB (1 << 5) | |
f0f59a00 VS |
2358 | #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034) |
2359 | #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038) | |
9e72b46c | 2360 | /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ |
f0f59a00 | 2361 | #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4) |
9e72b46c | 2362 | #define GEN7_LRA_LIMITS_REG_NUM 13 |
f0f59a00 VS |
2363 | #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070) |
2364 | #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074) | |
9e72b46c | 2365 | |
f0f59a00 | 2366 | #define GAMTARBMODE _MMIO(0x04a08) |
5ee8ee86 PZ |
2367 | #define ARB_MODE_BWGTLB_DISABLE (1 << 9) |
2368 | #define ARB_MODE_SWIZZLE_BDW (1 << 1) | |
f0f59a00 | 2369 | #define RENDER_HWS_PGA_GEN7 _MMIO(0x04080) |
5ee8ee86 | 2370 | #define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100 * (engine)->hw_id) |
b03ec3d6 MT |
2371 | #define GEN8_RING_FAULT_REG _MMIO(0x4094) |
2372 | #define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7) | |
5ee8ee86 | 2373 | #define RING_FAULT_GTTSEL_MASK (1 << 11) |
68d97538 VS |
2374 | #define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff) |
2375 | #define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3) | |
5ee8ee86 | 2376 | #define RING_FAULT_VALID (1 << 0) |
f0f59a00 VS |
2377 | #define DONE_REG _MMIO(0x40b0) |
2378 | #define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0) | |
2379 | #define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4) | |
5ee8ee86 | 2380 | #define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index) * 4) |
f0f59a00 VS |
2381 | #define BSD_HWS_PGA_GEN7 _MMIO(0x04180) |
2382 | #define BLT_HWS_PGA_GEN7 _MMIO(0x04280) | |
2383 | #define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380) | |
5ee8ee86 PZ |
2384 | #define RING_ACTHD(base) _MMIO((base) + 0x74) |
2385 | #define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c) | |
2386 | #define RING_NOPID(base) _MMIO((base) + 0x94) | |
2387 | #define RING_IMR(base) _MMIO((base) + 0xa8) | |
2388 | #define RING_HWSTAM(base) _MMIO((base) + 0x98) | |
2389 | #define RING_TIMESTAMP(base) _MMIO((base) + 0x358) | |
2390 | #define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4) | |
585fb111 JB |
2391 | #define TAIL_ADDR 0x001FFFF8 |
2392 | #define HEAD_WRAP_COUNT 0xFFE00000 | |
2393 | #define HEAD_WRAP_ONE 0x00200000 | |
2394 | #define HEAD_ADDR 0x001FFFFC | |
2395 | #define RING_NR_PAGES 0x001FF000 | |
2396 | #define RING_REPORT_MASK 0x00000006 | |
2397 | #define RING_REPORT_64K 0x00000002 | |
2398 | #define RING_REPORT_128K 0x00000004 | |
2399 | #define RING_NO_REPORT 0x00000000 | |
2400 | #define RING_VALID_MASK 0x00000001 | |
2401 | #define RING_VALID 0x00000001 | |
2402 | #define RING_INVALID 0x00000000 | |
5ee8ee86 PZ |
2403 | #define RING_WAIT_I8XX (1 << 0) /* gen2, PRBx_HEAD */ |
2404 | #define RING_WAIT (1 << 11) /* gen3+, PRBx_CTL */ | |
2405 | #define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */ | |
9e72b46c | 2406 | |
5ee8ee86 | 2407 | #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4) |
33136b06 AS |
2408 | #define RING_MAX_NONPRIV_SLOTS 12 |
2409 | ||
f0f59a00 | 2410 | #define GEN7_TLB_RD_ADDR _MMIO(0x4700) |
9e72b46c | 2411 | |
4ba9c1f7 | 2412 | #define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0) |
5ee8ee86 | 2413 | #define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1 << 18) |
4ba9c1f7 | 2414 | |
9a6330cf MA |
2415 | #define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080) |
2416 | #define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF | |
2417 | ||
c0b730d5 | 2418 | #define GAMT_CHKN_BIT_REG _MMIO(0x4ab8) |
4ece66b1 OM |
2419 | #define GAMT_CHKN_DISABLE_L3_COH_PIPE (1 << 31) |
2420 | #define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1 << 28) | |
2421 | #define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1 << 24) | |
c0b730d5 | 2422 | |
8168bd48 | 2423 | #if 0 |
f0f59a00 VS |
2424 | #define PRB0_TAIL _MMIO(0x2030) |
2425 | #define PRB0_HEAD _MMIO(0x2034) | |
2426 | #define PRB0_START _MMIO(0x2038) | |
2427 | #define PRB0_CTL _MMIO(0x203c) | |
2428 | #define PRB1_TAIL _MMIO(0x2040) /* 915+ only */ | |
2429 | #define PRB1_HEAD _MMIO(0x2044) /* 915+ only */ | |
2430 | #define PRB1_START _MMIO(0x2048) /* 915+ only */ | |
2431 | #define PRB1_CTL _MMIO(0x204c) /* 915+ only */ | |
8168bd48 | 2432 | #endif |
f0f59a00 VS |
2433 | #define IPEIR_I965 _MMIO(0x2064) |
2434 | #define IPEHR_I965 _MMIO(0x2068) | |
2435 | #define GEN7_SC_INSTDONE _MMIO(0x7100) | |
2436 | #define GEN7_SAMPLER_INSTDONE _MMIO(0xe160) | |
2437 | #define GEN7_ROW_INSTDONE _MMIO(0xe164) | |
f9e61372 BW |
2438 | #define GEN8_MCR_SELECTOR _MMIO(0xfdc) |
2439 | #define GEN8_MCR_SLICE(slice) (((slice) & 3) << 26) | |
2440 | #define GEN8_MCR_SLICE_MASK GEN8_MCR_SLICE(3) | |
2441 | #define GEN8_MCR_SUBSLICE(subslice) (((subslice) & 3) << 24) | |
2442 | #define GEN8_MCR_SUBSLICE_MASK GEN8_MCR_SUBSLICE(3) | |
d3d57927 KG |
2443 | #define GEN11_MCR_SLICE(slice) (((slice) & 0xf) << 27) |
2444 | #define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf) | |
2445 | #define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24) | |
2446 | #define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7) | |
5ee8ee86 PZ |
2447 | #define RING_IPEIR(base) _MMIO((base) + 0x64) |
2448 | #define RING_IPEHR(base) _MMIO((base) + 0x68) | |
f1d54348 ID |
2449 | /* |
2450 | * On GEN4, only the render ring INSTDONE exists and has a different | |
2451 | * layout than the GEN7+ version. | |
bd93a50e | 2452 | * The GEN2 counterpart of this register is GEN2_INSTDONE. |
f1d54348 | 2453 | */ |
5ee8ee86 PZ |
2454 | #define RING_INSTDONE(base) _MMIO((base) + 0x6c) |
2455 | #define RING_INSTPS(base) _MMIO((base) + 0x70) | |
2456 | #define RING_DMA_FADD(base) _MMIO((base) + 0x78) | |
2457 | #define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) /* gen8+ */ | |
2458 | #define RING_INSTPM(base) _MMIO((base) + 0xc0) | |
2459 | #define RING_MI_MODE(base) _MMIO((base) + 0x9c) | |
f0f59a00 VS |
2460 | #define INSTPS _MMIO(0x2070) /* 965+ only */ |
2461 | #define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */ | |
2462 | #define ACTHD_I965 _MMIO(0x2074) | |
2463 | #define HWS_PGA _MMIO(0x2080) | |
585fb111 JB |
2464 | #define HWS_ADDRESS_MASK 0xfffff000 |
2465 | #define HWS_START_ADDRESS_SHIFT 4 | |
f0f59a00 | 2466 | #define PWRCTXA _MMIO(0x2088) /* 965GM+ only */ |
5ee8ee86 | 2467 | #define PWRCTX_EN (1 << 0) |
f0f59a00 VS |
2468 | #define IPEIR _MMIO(0x2088) |
2469 | #define IPEHR _MMIO(0x208c) | |
2470 | #define GEN2_INSTDONE _MMIO(0x2090) | |
2471 | #define NOPID _MMIO(0x2094) | |
2472 | #define HWSTAM _MMIO(0x2098) | |
2473 | #define DMA_FADD_I8XX _MMIO(0x20d0) | |
5ee8ee86 | 2474 | #define RING_BBSTATE(base) _MMIO((base) + 0x110) |
35dc3f97 | 2475 | #define RING_BB_PPGTT (1 << 5) |
5ee8ee86 PZ |
2476 | #define RING_SBBADDR(base) _MMIO((base) + 0x114) /* hsw+ */ |
2477 | #define RING_SBBSTATE(base) _MMIO((base) + 0x118) /* hsw+ */ | |
2478 | #define RING_SBBADDR_UDW(base) _MMIO((base) + 0x11c) /* gen8+ */ | |
2479 | #define RING_BBADDR(base) _MMIO((base) + 0x140) | |
2480 | #define RING_BBADDR_UDW(base) _MMIO((base) + 0x168) /* gen8+ */ | |
2481 | #define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+ */ | |
2482 | #define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */ | |
2483 | #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */ | |
2484 | #define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */ | |
f0f59a00 VS |
2485 | |
2486 | #define ERROR_GEN6 _MMIO(0x40a0) | |
2487 | #define GEN7_ERR_INT _MMIO(0x44040) | |
5ee8ee86 PZ |
2488 | #define ERR_INT_POISON (1 << 31) |
2489 | #define ERR_INT_MMIO_UNCLAIMED (1 << 13) | |
2490 | #define ERR_INT_PIPE_CRC_DONE_C (1 << 8) | |
2491 | #define ERR_INT_FIFO_UNDERRUN_C (1 << 6) | |
2492 | #define ERR_INT_PIPE_CRC_DONE_B (1 << 5) | |
2493 | #define ERR_INT_FIFO_UNDERRUN_B (1 << 3) | |
2494 | #define ERR_INT_PIPE_CRC_DONE_A (1 << 2) | |
2495 | #define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3)) | |
2496 | #define ERR_INT_FIFO_UNDERRUN_A (1 << 0) | |
2497 | #define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) | |
f406839f | 2498 | |
f0f59a00 VS |
2499 | #define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10) |
2500 | #define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14) | |
5a3f58df OM |
2501 | #define FAULT_VA_HIGH_BITS (0xf << 0) |
2502 | #define FAULT_GTT_SEL (1 << 4) | |
6c826f34 | 2503 | |
f0f59a00 | 2504 | #define FPGA_DBG _MMIO(0x42300) |
5ee8ee86 | 2505 | #define FPGA_DBG_RM_NOCLAIM (1 << 31) |
3f1e109a | 2506 | |
8ac3e1bb MK |
2507 | #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028) |
2508 | #define CLAIM_ER_CLR (1 << 31) | |
2509 | #define CLAIM_ER_OVERFLOW (1 << 16) | |
2510 | #define CLAIM_ER_CTR_MASK 0xffff | |
2511 | ||
f0f59a00 | 2512 | #define DERRMR _MMIO(0x44050) |
4e0bbc31 | 2513 | /* Note that HBLANK events are reserved on bdw+ */ |
5ee8ee86 PZ |
2514 | #define DERRMR_PIPEA_SCANLINE (1 << 0) |
2515 | #define DERRMR_PIPEA_PRI_FLIP_DONE (1 << 1) | |
2516 | #define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2) | |
2517 | #define DERRMR_PIPEA_VBLANK (1 << 3) | |
2518 | #define DERRMR_PIPEA_HBLANK (1 << 5) | |
af7187b7 | 2519 | #define DERRMR_PIPEB_SCANLINE (1 << 8) |
5ee8ee86 PZ |
2520 | #define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9) |
2521 | #define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10) | |
2522 | #define DERRMR_PIPEB_VBLANK (1 << 11) | |
2523 | #define DERRMR_PIPEB_HBLANK (1 << 13) | |
ffe74d75 | 2524 | /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */ |
5ee8ee86 PZ |
2525 | #define DERRMR_PIPEC_SCANLINE (1 << 14) |
2526 | #define DERRMR_PIPEC_PRI_FLIP_DONE (1 << 15) | |
2527 | #define DERRMR_PIPEC_SPR_FLIP_DONE (1 << 20) | |
2528 | #define DERRMR_PIPEC_VBLANK (1 << 21) | |
2529 | #define DERRMR_PIPEC_HBLANK (1 << 22) | |
ffe74d75 | 2530 | |
0f3b6849 | 2531 | |
de6e2eaf EA |
2532 | /* GM45+ chicken bits -- debug workaround bits that may be required |
2533 | * for various sorts of correct behavior. The top 16 bits of each are | |
2534 | * the enables for writing to the corresponding low bit. | |
2535 | */ | |
f0f59a00 | 2536 | #define _3D_CHICKEN _MMIO(0x2084) |
4283908e | 2537 | #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10) |
f0f59a00 | 2538 | #define _3D_CHICKEN2 _MMIO(0x208c) |
b77422f8 KG |
2539 | |
2540 | #define FF_SLICE_CHICKEN _MMIO(0x2088) | |
2541 | #define FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX (1 << 1) | |
2542 | ||
de6e2eaf EA |
2543 | /* Disables pipelining of read flushes past the SF-WIZ interface. |
2544 | * Required on all Ironlake steppings according to the B-Spec, but the | |
2545 | * particular danger of not doing so is not specified. | |
2546 | */ | |
2547 | # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) | |
f0f59a00 | 2548 | #define _3D_CHICKEN3 _MMIO(0x2090) |
b77422f8 | 2549 | #define _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX (1 << 12) |
87f8020e | 2550 | #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) |
1a25db65 | 2551 | #define _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE (1 << 5) |
26b6e44a | 2552 | #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) |
5ee8ee86 | 2553 | #define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x) << 1) /* gen8+ */ |
e927ecde | 2554 | #define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */ |
de6e2eaf | 2555 | |
f0f59a00 | 2556 | #define MI_MODE _MMIO(0x209c) |
71cf39b1 | 2557 | # define VS_TIMER_DISPATCH (1 << 6) |
fc74d8e0 | 2558 | # define MI_FLUSH_ENABLE (1 << 12) |
1c8c38c5 | 2559 | # define ASYNC_FLIP_PERF_DISABLE (1 << 14) |
e9fea574 | 2560 | # define MODE_IDLE (1 << 9) |
9991ae78 | 2561 | # define STOP_RING (1 << 8) |
71cf39b1 | 2562 | |
f0f59a00 VS |
2563 | #define GEN6_GT_MODE _MMIO(0x20d0) |
2564 | #define GEN7_GT_MODE _MMIO(0x7008) | |
8d85d272 VS |
2565 | #define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7)) |
2566 | #define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0) | |
2567 | #define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1) | |
2568 | #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0) | |
98533251 | 2569 | #define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1) |
6547fbdb | 2570 | #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5) |
68d97538 VS |
2571 | #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2)) |
2572 | #define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2)) | |
f8f2ac9a | 2573 | |
a8ab5ed5 TG |
2574 | /* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */ |
2575 | #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4) | |
2576 | #define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2) | |
2577 | ||
b1e429fe TG |
2578 | /* WaClearTdlStateAckDirtyBits */ |
2579 | #define GEN8_STATE_ACK _MMIO(0x20F0) | |
2580 | #define GEN9_STATE_ACK_SLICE1 _MMIO(0x20F8) | |
2581 | #define GEN9_STATE_ACK_SLICE2 _MMIO(0x2100) | |
2582 | #define GEN9_STATE_ACK_TDL0 (1 << 12) | |
2583 | #define GEN9_STATE_ACK_TDL1 (1 << 13) | |
2584 | #define GEN9_STATE_ACK_TDL2 (1 << 14) | |
2585 | #define GEN9_STATE_ACK_TDL3 (1 << 15) | |
2586 | #define GEN9_SUBSLICE_TDL_ACK_BITS \ | |
2587 | (GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \ | |
2588 | GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0) | |
2589 | ||
f0f59a00 VS |
2590 | #define GFX_MODE _MMIO(0x2520) |
2591 | #define GFX_MODE_GEN7 _MMIO(0x229c) | |
5ee8ee86 PZ |
2592 | #define RING_MODE_GEN7(engine) _MMIO((engine)->mmio_base + 0x29c) |
2593 | #define GFX_RUN_LIST_ENABLE (1 << 15) | |
2594 | #define GFX_INTERRUPT_STEERING (1 << 14) | |
2595 | #define GFX_TLB_INVALIDATE_EXPLICIT (1 << 13) | |
2596 | #define GFX_SURFACE_FAULT_ENABLE (1 << 12) | |
2597 | #define GFX_REPLAY_MODE (1 << 11) | |
2598 | #define GFX_PSMI_GRANULARITY (1 << 10) | |
2599 | #define GFX_PPGTT_ENABLE (1 << 9) | |
2600 | #define GEN8_GFX_PPGTT_48B (1 << 7) | |
2601 | ||
2602 | #define GFX_FORWARD_VBLANK_MASK (3 << 5) | |
2603 | #define GFX_FORWARD_VBLANK_NEVER (0 << 5) | |
2604 | #define GFX_FORWARD_VBLANK_ALWAYS (1 << 5) | |
2605 | #define GFX_FORWARD_VBLANK_COND (2 << 5) | |
2606 | ||
2607 | #define GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3) | |
225701fc | 2608 | |
a7e806de | 2609 | #define VLV_DISPLAY_BASE 0x180000 |
b6fdd0f2 | 2610 | #define VLV_MIPI_BASE VLV_DISPLAY_BASE |
c6c794a2 | 2611 | #define BXT_MIPI_BASE 0x60000 |
a7e806de | 2612 | |
f0f59a00 VS |
2613 | #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030) |
2614 | #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034) | |
2615 | #define SCPD0 _MMIO(0x209c) /* 915+ only */ | |
2616 | #define IER _MMIO(0x20a0) | |
2617 | #define IIR _MMIO(0x20a4) | |
2618 | #define IMR _MMIO(0x20a8) | |
2619 | #define ISR _MMIO(0x20ac) | |
2620 | #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060) | |
5ee8ee86 PZ |
2621 | #define GINT_DIS (1 << 22) |
2622 | #define GCFG_DIS (1 << 8) | |
f0f59a00 VS |
2623 | #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064) |
2624 | #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084) | |
2625 | #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0) | |
2626 | #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4) | |
2627 | #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8) | |
2628 | #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac) | |
2629 | #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120) | |
38807746 D |
2630 | #define VLV_PCBR_ADDR_SHIFT 12 |
2631 | ||
5ee8ee86 | 2632 | #define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */ |
f0f59a00 VS |
2633 | #define EIR _MMIO(0x20b0) |
2634 | #define EMR _MMIO(0x20b4) | |
2635 | #define ESR _MMIO(0x20b8) | |
5ee8ee86 PZ |
2636 | #define GM45_ERROR_PAGE_TABLE (1 << 5) |
2637 | #define GM45_ERROR_MEM_PRIV (1 << 4) | |
2638 | #define I915_ERROR_PAGE_TABLE (1 << 4) | |
2639 | #define GM45_ERROR_CP_PRIV (1 << 3) | |
2640 | #define I915_ERROR_MEMORY_REFRESH (1 << 1) | |
2641 | #define I915_ERROR_INSTRUCTION (1 << 0) | |
f0f59a00 | 2642 | #define INSTPM _MMIO(0x20c0) |
5ee8ee86 PZ |
2643 | #define INSTPM_SELF_EN (1 << 12) /* 915GM only */ |
2644 | #define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts | |
8692d00e CW |
2645 | will not assert AGPBUSY# and will only |
2646 | be delivered when out of C3. */ | |
5ee8ee86 PZ |
2647 | #define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */ |
2648 | #define INSTPM_TLB_INVALIDATE (1 << 9) | |
2649 | #define INSTPM_SYNC_FLUSH (1 << 5) | |
f0f59a00 VS |
2650 | #define ACTHD _MMIO(0x20c8) |
2651 | #define MEM_MODE _MMIO(0x20cc) | |
5ee8ee86 PZ |
2652 | #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */ |
2653 | #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */ | |
2654 | #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */ | |
f0f59a00 VS |
2655 | #define FW_BLC _MMIO(0x20d8) |
2656 | #define FW_BLC2 _MMIO(0x20dc) | |
2657 | #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */ | |
5ee8ee86 PZ |
2658 | #define FW_BLC_SELF_EN_MASK (1 << 31) |
2659 | #define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */ | |
2660 | #define FW_BLC_SELF_EN (1 << 15) /* 945 only */ | |
7662c8bd SL |
2661 | #define MM_BURST_LENGTH 0x00700000 |
2662 | #define MM_FIFO_WATERMARK 0x0001F000 | |
2663 | #define LM_BURST_LENGTH 0x00000700 | |
2664 | #define LM_FIFO_WATERMARK 0x0000001F | |
f0f59a00 | 2665 | #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */ |
45503ded | 2666 | |
78005497 MK |
2667 | #define MBUS_ABOX_CTL _MMIO(0x45038) |
2668 | #define MBUS_ABOX_BW_CREDIT_MASK (3 << 20) | |
2669 | #define MBUS_ABOX_BW_CREDIT(x) ((x) << 20) | |
2670 | #define MBUS_ABOX_B_CREDIT_MASK (0xF << 16) | |
2671 | #define MBUS_ABOX_B_CREDIT(x) ((x) << 16) | |
2672 | #define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8) | |
2673 | #define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8) | |
2674 | #define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0) | |
2675 | #define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0) | |
2676 | ||
2677 | #define _PIPEA_MBUS_DBOX_CTL 0x7003C | |
2678 | #define _PIPEB_MBUS_DBOX_CTL 0x7103C | |
2679 | #define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \ | |
2680 | _PIPEB_MBUS_DBOX_CTL) | |
2681 | #define MBUS_DBOX_BW_CREDIT_MASK (3 << 14) | |
2682 | #define MBUS_DBOX_BW_CREDIT(x) ((x) << 14) | |
2683 | #define MBUS_DBOX_B_CREDIT_MASK (0x1F << 8) | |
2684 | #define MBUS_DBOX_B_CREDIT(x) ((x) << 8) | |
2685 | #define MBUS_DBOX_A_CREDIT_MASK (0xF << 0) | |
2686 | #define MBUS_DBOX_A_CREDIT(x) ((x) << 0) | |
2687 | ||
2688 | #define MBUS_UBOX_CTL _MMIO(0x4503C) | |
2689 | #define MBUS_BBOX_CTL_S1 _MMIO(0x45040) | |
2690 | #define MBUS_BBOX_CTL_S2 _MMIO(0x45044) | |
2691 | ||
45503ded KP |
2692 | /* Make render/texture TLB fetches lower priorty than associated data |
2693 | * fetches. This is not turned on by default | |
2694 | */ | |
2695 | #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) | |
2696 | ||
2697 | /* Isoch request wait on GTT enable (Display A/B/C streams). | |
2698 | * Make isoch requests stall on the TLB update. May cause | |
2699 | * display underruns (test mode only) | |
2700 | */ | |
2701 | #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) | |
2702 | ||
2703 | /* Block grant count for isoch requests when block count is | |
2704 | * set to a finite value. | |
2705 | */ | |
2706 | #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) | |
2707 | #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ | |
2708 | #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ | |
2709 | #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ | |
2710 | #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ | |
2711 | ||
2712 | /* Enable render writes to complete in C2/C3/C4 power states. | |
2713 | * If this isn't enabled, render writes are prevented in low | |
2714 | * power states. That seems bad to me. | |
2715 | */ | |
2716 | #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) | |
2717 | ||
2718 | /* This acknowledges an async flip immediately instead | |
2719 | * of waiting for 2TLB fetches. | |
2720 | */ | |
2721 | #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) | |
2722 | ||
2723 | /* Enables non-sequential data reads through arbiter | |
2724 | */ | |
0206e353 | 2725 | #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) |
45503ded KP |
2726 | |
2727 | /* Disable FSB snooping of cacheable write cycles from binner/render | |
2728 | * command stream | |
2729 | */ | |
2730 | #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) | |
2731 | ||
2732 | /* Arbiter time slice for non-isoch streams */ | |
2733 | #define MI_ARB_TIME_SLICE_MASK (7 << 5) | |
2734 | #define MI_ARB_TIME_SLICE_1 (0 << 5) | |
2735 | #define MI_ARB_TIME_SLICE_2 (1 << 5) | |
2736 | #define MI_ARB_TIME_SLICE_4 (2 << 5) | |
2737 | #define MI_ARB_TIME_SLICE_6 (3 << 5) | |
2738 | #define MI_ARB_TIME_SLICE_8 (4 << 5) | |
2739 | #define MI_ARB_TIME_SLICE_10 (5 << 5) | |
2740 | #define MI_ARB_TIME_SLICE_14 (6 << 5) | |
2741 | #define MI_ARB_TIME_SLICE_16 (7 << 5) | |
2742 | ||
2743 | /* Low priority grace period page size */ | |
2744 | #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ | |
2745 | #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) | |
2746 | ||
2747 | /* Disable display A/B trickle feed */ | |
2748 | #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) | |
2749 | ||
2750 | /* Set display plane priority */ | |
2751 | #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ | |
2752 | #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ | |
2753 | ||
f0f59a00 | 2754 | #define MI_STATE _MMIO(0x20e4) /* gen2 only */ |
54e472ae VS |
2755 | #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */ |
2756 | #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */ | |
2757 | ||
f0f59a00 | 2758 | #define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */ |
5ee8ee86 PZ |
2759 | #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1 << 8) |
2760 | #define CM0_IZ_OPT_DISABLE (1 << 6) | |
2761 | #define CM0_ZR_OPT_DISABLE (1 << 5) | |
2762 | #define CM0_STC_EVICT_DISABLE_LRA_SNB (1 << 5) | |
2763 | #define CM0_DEPTH_EVICT_DISABLE (1 << 4) | |
2764 | #define CM0_COLOR_EVICT_DISABLE (1 << 3) | |
2765 | #define CM0_DEPTH_WRITE_DISABLE (1 << 1) | |
2766 | #define CM0_RC_OP_FLUSH_DISABLE (1 << 0) | |
f0f59a00 VS |
2767 | #define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */ |
2768 | #define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008) | |
5ee8ee86 | 2769 | #define GFX_FLSH_CNTL_EN (1 << 0) |
f0f59a00 | 2770 | #define ECOSKPD _MMIO(0x21d0) |
5ee8ee86 PZ |
2771 | #define ECO_GATING_CX_ONLY (1 << 3) |
2772 | #define ECO_FLIP_DONE (1 << 0) | |
585fb111 | 2773 | |
f0f59a00 | 2774 | #define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */ |
5ee8ee86 PZ |
2775 | #define RC_OP_FLUSH_ENABLE (1 << 0) |
2776 | #define HIZ_RAW_STALL_OPT_DISABLE (1 << 2) | |
f0f59a00 | 2777 | #define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */ |
5ee8ee86 PZ |
2778 | #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1 << 6) |
2779 | #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1 << 6) | |
2780 | #define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1) | |
fb046853 | 2781 | |
0bf059f3 OM |
2782 | #define GEN10_CACHE_MODE_SS _MMIO(0xe420) |
2783 | #define FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4) | |
2784 | ||
f0f59a00 | 2785 | #define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0) |
4efe0708 | 2786 | #define GEN6_BLITTER_LOCK_SHIFT 16 |
5ee8ee86 | 2787 | #define GEN6_BLITTER_FBC_NOTIFY (1 << 3) |
4efe0708 | 2788 | |
f0f59a00 | 2789 | #define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050) |
2c550183 | 2790 | #define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0) |
295e8bb7 | 2791 | #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12) |
5ee8ee86 | 2792 | #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1 << 10) |
295e8bb7 | 2793 | |
19f81df2 RB |
2794 | #define GEN6_RCS_PWR_FSM _MMIO(0x22ac) |
2795 | #define GEN9_RCS_FE_FSM2 _MMIO(0x22a4) | |
2796 | ||
693d11c3 | 2797 | /* Fuse readout registers for GT */ |
b8ec759e LL |
2798 | #define HSW_PAVP_FUSE1 _MMIO(0x911C) |
2799 | #define HSW_F1_EU_DIS_SHIFT 16 | |
2800 | #define HSW_F1_EU_DIS_MASK (0x3 << HSW_F1_EU_DIS_SHIFT) | |
2801 | #define HSW_F1_EU_DIS_10EUS 0 | |
2802 | #define HSW_F1_EU_DIS_8EUS 1 | |
2803 | #define HSW_F1_EU_DIS_6EUS 2 | |
2804 | ||
f0f59a00 | 2805 | #define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168) |
c93043ae JM |
2806 | #define CHV_FGT_DISABLE_SS0 (1 << 10) |
2807 | #define CHV_FGT_DISABLE_SS1 (1 << 11) | |
693d11c3 D |
2808 | #define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16 |
2809 | #define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT) | |
2810 | #define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20 | |
2811 | #define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT) | |
2812 | #define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24 | |
2813 | #define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT) | |
2814 | #define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28 | |
2815 | #define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT) | |
2816 | ||
f0f59a00 | 2817 | #define GEN8_FUSE2 _MMIO(0x9120) |
91bedd34 ŁD |
2818 | #define GEN8_F2_SS_DIS_SHIFT 21 |
2819 | #define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT) | |
3873218f JM |
2820 | #define GEN8_F2_S_ENA_SHIFT 25 |
2821 | #define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT) | |
2822 | ||
2823 | #define GEN9_F2_SS_DIS_SHIFT 20 | |
2824 | #define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT) | |
2825 | ||
4e9767bc BW |
2826 | #define GEN10_F2_S_ENA_SHIFT 22 |
2827 | #define GEN10_F2_S_ENA_MASK (0x3f << GEN10_F2_S_ENA_SHIFT) | |
2828 | #define GEN10_F2_SS_DIS_SHIFT 18 | |
2829 | #define GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT) | |
2830 | ||
fe864b76 YZ |
2831 | #define GEN10_MIRROR_FUSE3 _MMIO(0x9118) |
2832 | #define GEN10_L3BANK_PAIR_COUNT 4 | |
2833 | #define GEN10_L3BANK_MASK 0x0F | |
2834 | ||
f0f59a00 | 2835 | #define GEN8_EU_DISABLE0 _MMIO(0x9134) |
91bedd34 ŁD |
2836 | #define GEN8_EU_DIS0_S0_MASK 0xffffff |
2837 | #define GEN8_EU_DIS0_S1_SHIFT 24 | |
2838 | #define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT) | |
2839 | ||
f0f59a00 | 2840 | #define GEN8_EU_DISABLE1 _MMIO(0x9138) |
91bedd34 ŁD |
2841 | #define GEN8_EU_DIS1_S1_MASK 0xffff |
2842 | #define GEN8_EU_DIS1_S2_SHIFT 16 | |
2843 | #define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT) | |
2844 | ||
f0f59a00 | 2845 | #define GEN8_EU_DISABLE2 _MMIO(0x913c) |
91bedd34 ŁD |
2846 | #define GEN8_EU_DIS2_S2_MASK 0xff |
2847 | ||
5ee8ee86 | 2848 | #define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice) * 0x4) |
3873218f | 2849 | |
4e9767bc BW |
2850 | #define GEN10_EU_DISABLE3 _MMIO(0x9140) |
2851 | #define GEN10_EU_DIS_SS_MASK 0xff | |
2852 | ||
26376a7e OM |
2853 | #define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140) |
2854 | #define GEN11_GT_VDBOX_DISABLE_MASK 0xff | |
2855 | #define GEN11_GT_VEBOX_DISABLE_SHIFT 16 | |
2856 | #define GEN11_GT_VEBOX_DISABLE_MASK (0xff << GEN11_GT_VEBOX_DISABLE_SHIFT) | |
2857 | ||
8b5eb5e2 KG |
2858 | #define GEN11_EU_DISABLE _MMIO(0x9134) |
2859 | #define GEN11_EU_DIS_MASK 0xFF | |
2860 | ||
2861 | #define GEN11_GT_SLICE_ENABLE _MMIO(0x9138) | |
2862 | #define GEN11_GT_S_ENA_MASK 0xFF | |
2863 | ||
2864 | #define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C) | |
2865 | ||
f0f59a00 | 2866 | #define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050) |
12f55818 CW |
2867 | #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0) |
2868 | #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2) | |
2869 | #define GEN6_BSD_SLEEP_INDICATOR (1 << 3) | |
2870 | #define GEN6_BSD_GO_INDICATOR (1 << 4) | |
881f47b6 | 2871 | |
cc609d5d BW |
2872 | /* On modern GEN architectures interrupt control consists of two sets |
2873 | * of registers. The first set pertains to the ring generating the | |
2874 | * interrupt. The second control is for the functional block generating the | |
2875 | * interrupt. These are PM, GT, DE, etc. | |
2876 | * | |
2877 | * Luckily *knocks on wood* all the ring interrupt bits match up with the | |
2878 | * GT interrupt bits, so we don't need to duplicate the defines. | |
2879 | * | |
2880 | * These defines should cover us well from SNB->HSW with minor exceptions | |
2881 | * it can also work on ILK. | |
2882 | */ | |
2883 | #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) | |
2884 | #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) | |
2885 | #define GT_BLT_USER_INTERRUPT (1 << 22) | |
2886 | #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) | |
2887 | #define GT_BSD_USER_INTERRUPT (1 << 12) | |
35a85ac6 | 2888 | #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */ |
73d477f6 | 2889 | #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8) |
cc609d5d BW |
2890 | #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ |
2891 | #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) | |
2892 | #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3) | |
2893 | #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) | |
2894 | #define GT_RENDER_DEBUG_INTERRUPT (1 << 1) | |
2895 | #define GT_RENDER_USER_INTERRUPT (1 << 0) | |
2896 | ||
12638c57 BW |
2897 | #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ |
2898 | #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ | |
2899 | ||
772c2a51 | 2900 | #define GT_PARITY_ERROR(dev_priv) \ |
35a85ac6 | 2901 | (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \ |
772c2a51 | 2902 | (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)) |
35a85ac6 | 2903 | |
cc609d5d | 2904 | /* These are all the "old" interrupts */ |
5ee8ee86 PZ |
2905 | #define ILK_BSD_USER_INTERRUPT (1 << 5) |
2906 | ||
2907 | #define I915_PM_INTERRUPT (1 << 31) | |
2908 | #define I915_ISP_INTERRUPT (1 << 22) | |
2909 | #define I915_LPE_PIPE_B_INTERRUPT (1 << 21) | |
2910 | #define I915_LPE_PIPE_A_INTERRUPT (1 << 20) | |
2911 | #define I915_MIPIC_INTERRUPT (1 << 19) | |
2912 | #define I915_MIPIA_INTERRUPT (1 << 18) | |
2913 | #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18) | |
2914 | #define I915_DISPLAY_PORT_INTERRUPT (1 << 17) | |
2915 | #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16) | |
2916 | #define I915_MASTER_ERROR_INTERRUPT (1 << 15) | |
5ee8ee86 PZ |
2917 | #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14) |
2918 | #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */ | |
2919 | #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13) | |
2920 | #define I915_HWB_OOM_INTERRUPT (1 << 13) | |
2921 | #define I915_LPE_PIPE_C_INTERRUPT (1 << 12) | |
2922 | #define I915_SYNC_STATUS_INTERRUPT (1 << 12) | |
2923 | #define I915_MISC_INTERRUPT (1 << 11) | |
2924 | #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11) | |
2925 | #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10) | |
2926 | #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10) | |
2927 | #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9) | |
2928 | #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9) | |
2929 | #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8) | |
2930 | #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8) | |
2931 | #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7) | |
2932 | #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6) | |
2933 | #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5) | |
2934 | #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4) | |
2935 | #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3) | |
2936 | #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2) | |
2937 | #define I915_DEBUG_INTERRUPT (1 << 2) | |
2938 | #define I915_WINVALID_INTERRUPT (1 << 1) | |
2939 | #define I915_USER_INTERRUPT (1 << 1) | |
2940 | #define I915_ASLE_INTERRUPT (1 << 0) | |
2941 | #define I915_BSD_USER_INTERRUPT (1 << 25) | |
881f47b6 | 2942 | |
eef57324 JA |
2943 | #define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000) |
2944 | #define I915_HDMI_LPE_AUDIO_SIZE 0x1000 | |
2945 | ||
d5d8c3a1 | 2946 | /* DisplayPort Audio w/ LPE */ |
9db13e5f TI |
2947 | #define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38) |
2948 | #define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0) | |
2949 | ||
d5d8c3a1 PLB |
2950 | #define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20) |
2951 | #define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30) | |
2952 | #define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34) | |
2953 | #define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \ | |
2954 | _VLV_AUD_PORT_EN_B_DBG, \ | |
2955 | _VLV_AUD_PORT_EN_C_DBG, \ | |
2956 | _VLV_AUD_PORT_EN_D_DBG) | |
2957 | #define VLV_AMP_MUTE (1 << 1) | |
2958 | ||
f0f59a00 | 2959 | #define GEN6_BSD_RNCID _MMIO(0x12198) |
881f47b6 | 2960 | |
f0f59a00 | 2961 | #define GEN7_FF_THREAD_MODE _MMIO(0x20a0) |
a1e969e0 | 2962 | #define GEN7_FF_SCHED_MASK 0x0077070 |
ab57fff1 | 2963 | #define GEN8_FF_DS_REF_CNT_FFME (1 << 19) |
5ee8ee86 PZ |
2964 | #define GEN7_FF_TS_SCHED_HS1 (0x5 << 16) |
2965 | #define GEN7_FF_TS_SCHED_HS0 (0x3 << 16) | |
2966 | #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16) | |
2967 | #define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */ | |
41c0b3a8 | 2968 | #define GEN7_FF_VS_REF_CNT_FFME (1 << 15) |
5ee8ee86 PZ |
2969 | #define GEN7_FF_VS_SCHED_HS1 (0x5 << 12) |
2970 | #define GEN7_FF_VS_SCHED_HS0 (0x3 << 12) | |
2971 | #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */ | |
2972 | #define GEN7_FF_VS_SCHED_HW (0x0 << 12) | |
2973 | #define GEN7_FF_DS_SCHED_HS1 (0x5 << 4) | |
2974 | #define GEN7_FF_DS_SCHED_HS0 (0x3 << 4) | |
2975 | #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */ | |
2976 | #define GEN7_FF_DS_SCHED_HW (0x0 << 4) | |
a1e969e0 | 2977 | |
585fb111 JB |
2978 | /* |
2979 | * Framebuffer compression (915+ only) | |
2980 | */ | |
2981 | ||
f0f59a00 VS |
2982 | #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */ |
2983 | #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */ | |
2984 | #define FBC_CONTROL _MMIO(0x3208) | |
5ee8ee86 PZ |
2985 | #define FBC_CTL_EN (1 << 31) |
2986 | #define FBC_CTL_PERIODIC (1 << 30) | |
585fb111 | 2987 | #define FBC_CTL_INTERVAL_SHIFT (16) |
5ee8ee86 PZ |
2988 | #define FBC_CTL_UNCOMPRESSIBLE (1 << 14) |
2989 | #define FBC_CTL_C3_IDLE (1 << 13) | |
585fb111 | 2990 | #define FBC_CTL_STRIDE_SHIFT (5) |
82f34496 | 2991 | #define FBC_CTL_FENCENO_SHIFT (0) |
f0f59a00 | 2992 | #define FBC_COMMAND _MMIO(0x320c) |
5ee8ee86 | 2993 | #define FBC_CMD_COMPRESS (1 << 0) |
f0f59a00 | 2994 | #define FBC_STATUS _MMIO(0x3210) |
5ee8ee86 PZ |
2995 | #define FBC_STAT_COMPRESSING (1 << 31) |
2996 | #define FBC_STAT_COMPRESSED (1 << 30) | |
2997 | #define FBC_STAT_MODIFIED (1 << 29) | |
82f34496 | 2998 | #define FBC_STAT_CURRENT_LINE_SHIFT (0) |
f0f59a00 | 2999 | #define FBC_CONTROL2 _MMIO(0x3214) |
5ee8ee86 PZ |
3000 | #define FBC_CTL_FENCE_DBL (0 << 4) |
3001 | #define FBC_CTL_IDLE_IMM (0 << 2) | |
3002 | #define FBC_CTL_IDLE_FULL (1 << 2) | |
3003 | #define FBC_CTL_IDLE_LINE (2 << 2) | |
3004 | #define FBC_CTL_IDLE_DEBUG (3 << 2) | |
3005 | #define FBC_CTL_CPU_FENCE (1 << 1) | |
3006 | #define FBC_CTL_PLANE(plane) ((plane) << 0) | |
f0f59a00 VS |
3007 | #define FBC_FENCE_OFF _MMIO(0x3218) /* BSpec typo has 321Bh */ |
3008 | #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) | |
585fb111 JB |
3009 | |
3010 | #define FBC_LL_SIZE (1536) | |
3011 | ||
44fff99f | 3012 | #define FBC_LLC_READ_CTRL _MMIO(0x9044) |
5ee8ee86 | 3013 | #define FBC_LLC_FULLY_OPEN (1 << 30) |
44fff99f | 3014 | |
74dff282 | 3015 | /* Framebuffer compression for GM45+ */ |
f0f59a00 VS |
3016 | #define DPFC_CB_BASE _MMIO(0x3200) |
3017 | #define DPFC_CONTROL _MMIO(0x3208) | |
5ee8ee86 PZ |
3018 | #define DPFC_CTL_EN (1 << 31) |
3019 | #define DPFC_CTL_PLANE(plane) ((plane) << 30) | |
3020 | #define IVB_DPFC_CTL_PLANE(plane) ((plane) << 29) | |
3021 | #define DPFC_CTL_FENCE_EN (1 << 29) | |
3022 | #define IVB_DPFC_CTL_FENCE_EN (1 << 28) | |
3023 | #define DPFC_CTL_PERSISTENT_MODE (1 << 25) | |
3024 | #define DPFC_SR_EN (1 << 10) | |
3025 | #define DPFC_CTL_LIMIT_1X (0 << 6) | |
3026 | #define DPFC_CTL_LIMIT_2X (1 << 6) | |
3027 | #define DPFC_CTL_LIMIT_4X (2 << 6) | |
f0f59a00 | 3028 | #define DPFC_RECOMP_CTL _MMIO(0x320c) |
5ee8ee86 | 3029 | #define DPFC_RECOMP_STALL_EN (1 << 27) |
74dff282 JB |
3030 | #define DPFC_RECOMP_STALL_WM_SHIFT (16) |
3031 | #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) | |
3032 | #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) | |
3033 | #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) | |
f0f59a00 | 3034 | #define DPFC_STATUS _MMIO(0x3210) |
74dff282 JB |
3035 | #define DPFC_INVAL_SEG_SHIFT (16) |
3036 | #define DPFC_INVAL_SEG_MASK (0x07ff0000) | |
3037 | #define DPFC_COMP_SEG_SHIFT (0) | |
3fd5d1ec | 3038 | #define DPFC_COMP_SEG_MASK (0x000007ff) |
f0f59a00 VS |
3039 | #define DPFC_STATUS2 _MMIO(0x3214) |
3040 | #define DPFC_FENCE_YOFF _MMIO(0x3218) | |
3041 | #define DPFC_CHICKEN _MMIO(0x3224) | |
5ee8ee86 | 3042 | #define DPFC_HT_MODIFY (1 << 31) |
74dff282 | 3043 | |
b52eb4dc | 3044 | /* Framebuffer compression for Ironlake */ |
f0f59a00 VS |
3045 | #define ILK_DPFC_CB_BASE _MMIO(0x43200) |
3046 | #define ILK_DPFC_CONTROL _MMIO(0x43208) | |
5ee8ee86 | 3047 | #define FBC_CTL_FALSE_COLOR (1 << 10) |
b52eb4dc ZY |
3048 | /* The bit 28-8 is reserved */ |
3049 | #define DPFC_RESERVED (0x1FFFFF00) | |
f0f59a00 VS |
3050 | #define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c) |
3051 | #define ILK_DPFC_STATUS _MMIO(0x43210) | |
3fd5d1ec VS |
3052 | #define ILK_DPFC_COMP_SEG_MASK 0x7ff |
3053 | #define IVB_FBC_STATUS2 _MMIO(0x43214) | |
3054 | #define IVB_FBC_COMP_SEG_MASK 0x7ff | |
3055 | #define BDW_FBC_COMP_SEG_MASK 0xfff | |
f0f59a00 VS |
3056 | #define ILK_DPFC_FENCE_YOFF _MMIO(0x43218) |
3057 | #define ILK_DPFC_CHICKEN _MMIO(0x43224) | |
5ee8ee86 PZ |
3058 | #define ILK_DPFC_DISABLE_DUMMY0 (1 << 8) |
3059 | #define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1 << 23) | |
f0f59a00 | 3060 | #define ILK_FBC_RT_BASE _MMIO(0x2128) |
5ee8ee86 PZ |
3061 | #define ILK_FBC_RT_VALID (1 << 0) |
3062 | #define SNB_FBC_FRONT_BUFFER (1 << 1) | |
b52eb4dc | 3063 | |
f0f59a00 | 3064 | #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000) |
5ee8ee86 PZ |
3065 | #define ILK_FBCQ_DIS (1 << 22) |
3066 | #define ILK_PABSTRETCH_DIS (1 << 21) | |
1398261a | 3067 | |
b52eb4dc | 3068 | |
9c04f015 YL |
3069 | /* |
3070 | * Framebuffer compression for Sandybridge | |
3071 | * | |
3072 | * The following two registers are of type GTTMMADR | |
3073 | */ | |
f0f59a00 | 3074 | #define SNB_DPFC_CTL_SA _MMIO(0x100100) |
5ee8ee86 | 3075 | #define SNB_CPU_FENCE_ENABLE (1 << 29) |
f0f59a00 | 3076 | #define DPFC_CPU_FENCE_OFFSET _MMIO(0x100104) |
9c04f015 | 3077 | |
abe959c7 | 3078 | /* Framebuffer compression for Ivybridge */ |
f0f59a00 | 3079 | #define IVB_FBC_RT_BASE _MMIO(0x7020) |
abe959c7 | 3080 | |
f0f59a00 | 3081 | #define IPS_CTL _MMIO(0x43408) |
42db64ef | 3082 | #define IPS_ENABLE (1 << 31) |
9c04f015 | 3083 | |
f0f59a00 | 3084 | #define MSG_FBC_REND_STATE _MMIO(0x50380) |
5ee8ee86 PZ |
3085 | #define FBC_REND_NUKE (1 << 2) |
3086 | #define FBC_REND_CACHE_CLEAN (1 << 1) | |
fd3da6c9 | 3087 | |
585fb111 JB |
3088 | /* |
3089 | * GPIO regs | |
3090 | */ | |
f0f59a00 VS |
3091 | #define GPIOA _MMIO(0x5010) |
3092 | #define GPIOB _MMIO(0x5014) | |
3093 | #define GPIOC _MMIO(0x5018) | |
3094 | #define GPIOD _MMIO(0x501c) | |
3095 | #define GPIOE _MMIO(0x5020) | |
3096 | #define GPIOF _MMIO(0x5024) | |
3097 | #define GPIOG _MMIO(0x5028) | |
3098 | #define GPIOH _MMIO(0x502c) | |
af1f1b81 MK |
3099 | #define GPIOJ _MMIO(0x5034) |
3100 | #define GPIOK _MMIO(0x5038) | |
3101 | #define GPIOL _MMIO(0x503C) | |
3102 | #define GPIOM _MMIO(0x5040) | |
585fb111 JB |
3103 | # define GPIO_CLOCK_DIR_MASK (1 << 0) |
3104 | # define GPIO_CLOCK_DIR_IN (0 << 1) | |
3105 | # define GPIO_CLOCK_DIR_OUT (1 << 1) | |
3106 | # define GPIO_CLOCK_VAL_MASK (1 << 2) | |
3107 | # define GPIO_CLOCK_VAL_OUT (1 << 3) | |
3108 | # define GPIO_CLOCK_VAL_IN (1 << 4) | |
3109 | # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) | |
3110 | # define GPIO_DATA_DIR_MASK (1 << 8) | |
3111 | # define GPIO_DATA_DIR_IN (0 << 9) | |
3112 | # define GPIO_DATA_DIR_OUT (1 << 9) | |
3113 | # define GPIO_DATA_VAL_MASK (1 << 10) | |
3114 | # define GPIO_DATA_VAL_OUT (1 << 11) | |
3115 | # define GPIO_DATA_VAL_IN (1 << 12) | |
3116 | # define GPIO_DATA_PULLUP_DISABLE (1 << 13) | |
3117 | ||
f0f59a00 | 3118 | #define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */ |
5ee8ee86 PZ |
3119 | #define GMBUS_AKSV_SELECT (1 << 11) |
3120 | #define GMBUS_RATE_100KHZ (0 << 8) | |
3121 | #define GMBUS_RATE_50KHZ (1 << 8) | |
3122 | #define GMBUS_RATE_400KHZ (2 << 8) /* reserved on Pineview */ | |
3123 | #define GMBUS_RATE_1MHZ (3 << 8) /* reserved on Pineview */ | |
3124 | #define GMBUS_HOLD_EXT (1 << 7) /* 300ns hold time, rsvd on Pineview */ | |
988c7015 JN |
3125 | #define GMBUS_PIN_DISABLED 0 |
3126 | #define GMBUS_PIN_SSC 1 | |
3127 | #define GMBUS_PIN_VGADDC 2 | |
3128 | #define GMBUS_PIN_PANEL 3 | |
3129 | #define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */ | |
3130 | #define GMBUS_PIN_DPC 4 /* HDMIC */ | |
3131 | #define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */ | |
3132 | #define GMBUS_PIN_DPD 6 /* HDMID */ | |
3133 | #define GMBUS_PIN_RESERVED 7 /* 7 reserved */ | |
3d02352c | 3134 | #define GMBUS_PIN_1_BXT 1 /* BXT+ (atom) and CNP+ (big core) */ |
4c272834 JN |
3135 | #define GMBUS_PIN_2_BXT 2 |
3136 | #define GMBUS_PIN_3_BXT 3 | |
3d02352c | 3137 | #define GMBUS_PIN_4_CNP 4 |
5c749c52 AS |
3138 | #define GMBUS_PIN_9_TC1_ICP 9 |
3139 | #define GMBUS_PIN_10_TC2_ICP 10 | |
3140 | #define GMBUS_PIN_11_TC3_ICP 11 | |
3141 | #define GMBUS_PIN_12_TC4_ICP 12 | |
3142 | ||
3143 | #define GMBUS_NUM_PINS 13 /* including 0 */ | |
f0f59a00 | 3144 | #define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */ |
5ee8ee86 PZ |
3145 | #define GMBUS_SW_CLR_INT (1 << 31) |
3146 | #define GMBUS_SW_RDY (1 << 30) | |
3147 | #define GMBUS_ENT (1 << 29) /* enable timeout */ | |
3148 | #define GMBUS_CYCLE_NONE (0 << 25) | |
3149 | #define GMBUS_CYCLE_WAIT (1 << 25) | |
3150 | #define GMBUS_CYCLE_INDEX (2 << 25) | |
3151 | #define GMBUS_CYCLE_STOP (4 << 25) | |
f899fc64 | 3152 | #define GMBUS_BYTE_COUNT_SHIFT 16 |
9535c475 | 3153 | #define GMBUS_BYTE_COUNT_MAX 256U |
f899fc64 CW |
3154 | #define GMBUS_SLAVE_INDEX_SHIFT 8 |
3155 | #define GMBUS_SLAVE_ADDR_SHIFT 1 | |
5ee8ee86 PZ |
3156 | #define GMBUS_SLAVE_READ (1 << 0) |
3157 | #define GMBUS_SLAVE_WRITE (0 << 0) | |
f0f59a00 | 3158 | #define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */ |
5ee8ee86 PZ |
3159 | #define GMBUS_INUSE (1 << 15) |
3160 | #define GMBUS_HW_WAIT_PHASE (1 << 14) | |
3161 | #define GMBUS_STALL_TIMEOUT (1 << 13) | |
3162 | #define GMBUS_INT (1 << 12) | |
3163 | #define GMBUS_HW_RDY (1 << 11) | |
3164 | #define GMBUS_SATOER (1 << 10) | |
3165 | #define GMBUS_ACTIVE (1 << 9) | |
f0f59a00 VS |
3166 | #define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */ |
3167 | #define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */ | |
5ee8ee86 PZ |
3168 | #define GMBUS_SLAVE_TIMEOUT_EN (1 << 4) |
3169 | #define GMBUS_NAK_EN (1 << 3) | |
3170 | #define GMBUS_IDLE_EN (1 << 2) | |
3171 | #define GMBUS_HW_WAIT_EN (1 << 1) | |
3172 | #define GMBUS_HW_RDY_EN (1 << 0) | |
f0f59a00 | 3173 | #define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */ |
5ee8ee86 | 3174 | #define GMBUS_2BYTE_INDEX_EN (1 << 31) |
f0217c42 | 3175 | |
585fb111 JB |
3176 | /* |
3177 | * Clock control & power management | |
3178 | */ | |
2d401b17 VS |
3179 | #define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014) |
3180 | #define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018) | |
3181 | #define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030) | |
f0f59a00 | 3182 | #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) |
585fb111 | 3183 | |
f0f59a00 VS |
3184 | #define VGA0 _MMIO(0x6000) |
3185 | #define VGA1 _MMIO(0x6004) | |
3186 | #define VGA_PD _MMIO(0x6010) | |
585fb111 JB |
3187 | #define VGA0_PD_P2_DIV_4 (1 << 7) |
3188 | #define VGA0_PD_P1_DIV_2 (1 << 5) | |
3189 | #define VGA0_PD_P1_SHIFT 0 | |
3190 | #define VGA0_PD_P1_MASK (0x1f << 0) | |
3191 | #define VGA1_PD_P2_DIV_4 (1 << 15) | |
3192 | #define VGA1_PD_P1_DIV_2 (1 << 13) | |
3193 | #define VGA1_PD_P1_SHIFT 8 | |
3194 | #define VGA1_PD_P1_MASK (0x1f << 8) | |
585fb111 | 3195 | #define DPLL_VCO_ENABLE (1 << 31) |
4a33e48d DV |
3196 | #define DPLL_SDVO_HIGH_SPEED (1 << 30) |
3197 | #define DPLL_DVO_2X_MODE (1 << 30) | |
25eb05fc | 3198 | #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) |
585fb111 | 3199 | #define DPLL_SYNCLOCK_ENABLE (1 << 29) |
60bfe44f | 3200 | #define DPLL_REF_CLK_ENABLE_VLV (1 << 29) |
585fb111 JB |
3201 | #define DPLL_VGA_MODE_DIS (1 << 28) |
3202 | #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ | |
3203 | #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ | |
3204 | #define DPLL_MODE_MASK (3 << 26) | |
3205 | #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ | |
3206 | #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ | |
3207 | #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ | |
3208 | #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ | |
3209 | #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ | |
3210 | #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ | |
f2b115e6 | 3211 | #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ |
5ee8ee86 PZ |
3212 | #define DPLL_LOCK_VLV (1 << 15) |
3213 | #define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14) | |
3214 | #define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13) | |
3215 | #define DPLL_SSC_REF_CLK_CHV (1 << 13) | |
598fac6b DV |
3216 | #define DPLL_PORTC_READY_MASK (0xf << 4) |
3217 | #define DPLL_PORTB_READY_MASK (0xf) | |
585fb111 | 3218 | |
585fb111 | 3219 | #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 |
00fc31b7 CML |
3220 | |
3221 | /* Additional CHV pll/phy registers */ | |
f0f59a00 | 3222 | #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240) |
00fc31b7 | 3223 | #define DPLL_PORTD_READY_MASK (0xf) |
f0f59a00 | 3224 | #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100) |
5ee8ee86 | 3225 | #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27)) |
bc284542 VS |
3226 | #define PHY_LDO_DELAY_0NS 0x0 |
3227 | #define PHY_LDO_DELAY_200NS 0x1 | |
3228 | #define PHY_LDO_DELAY_600NS 0x2 | |
5ee8ee86 PZ |
3229 | #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23)) |
3230 | #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11)) | |
70722468 VS |
3231 | #define PHY_CH_SU_PSR 0x1 |
3232 | #define PHY_CH_DEEP_PSR 0x7 | |
5ee8ee86 | 3233 | #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2)) |
70722468 | 3234 | #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) |
f0f59a00 | 3235 | #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104) |
5ee8ee86 PZ |
3236 | #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30)) |
3237 | #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch)))) | |
3238 | #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline)))) | |
076ed3b2 | 3239 | |
585fb111 JB |
3240 | /* |
3241 | * The i830 generation, in LVDS mode, defines P1 as the bit number set within | |
3242 | * this field (only one bit may be set). | |
3243 | */ | |
3244 | #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 | |
3245 | #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 | |
f2b115e6 | 3246 | #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 |
585fb111 JB |
3247 | /* i830, required in DVO non-gang */ |
3248 | #define PLL_P2_DIVIDE_BY_4 (1 << 23) | |
3249 | #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ | |
3250 | #define PLL_REF_INPUT_DREFCLK (0 << 13) | |
3251 | #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ | |
3252 | #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ | |
3253 | #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) | |
3254 | #define PLL_REF_INPUT_MASK (3 << 13) | |
3255 | #define PLL_LOAD_PULSE_PHASE_SHIFT 9 | |
f2b115e6 | 3256 | /* Ironlake */ |
b9055052 ZW |
3257 | # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 |
3258 | # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) | |
5ee8ee86 | 3259 | # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9) |
b9055052 ZW |
3260 | # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 |
3261 | # define DPLL_FPA1_P1_POST_DIV_MASK 0xff | |
3262 | ||
585fb111 JB |
3263 | /* |
3264 | * Parallel to Serial Load Pulse phase selection. | |
3265 | * Selects the phase for the 10X DPLL clock for the PCIe | |
3266 | * digital display port. The range is 4 to 13; 10 or more | |
3267 | * is just a flip delay. The default is 6 | |
3268 | */ | |
3269 | #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) | |
3270 | #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) | |
3271 | /* | |
3272 | * SDVO multiplier for 945G/GM. Not used on 965. | |
3273 | */ | |
3274 | #define SDVO_MULTIPLIER_MASK 0x000000ff | |
3275 | #define SDVO_MULTIPLIER_SHIFT_HIRES 4 | |
3276 | #define SDVO_MULTIPLIER_SHIFT_VGA 0 | |
a57c774a | 3277 | |
2d401b17 VS |
3278 | #define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c) |
3279 | #define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020) | |
3280 | #define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c) | |
f0f59a00 | 3281 | #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) |
a57c774a | 3282 | |
585fb111 JB |
3283 | /* |
3284 | * UDI pixel divider, controlling how many pixels are stuffed into a packet. | |
3285 | * | |
3286 | * Value is pixels minus 1. Must be set to 1 pixel for SDVO. | |
3287 | */ | |
3288 | #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 | |
3289 | #define DPLL_MD_UDI_DIVIDER_SHIFT 24 | |
3290 | /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ | |
3291 | #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 | |
3292 | #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 | |
3293 | /* | |
3294 | * SDVO/UDI pixel multiplier. | |
3295 | * | |
3296 | * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus | |
3297 | * clock rate is 10 times the DPLL clock. At low resolution/refresh rate | |
3298 | * modes, the bus rate would be below the limits, so SDVO allows for stuffing | |
3299 | * dummy bytes in the datastream at an increased clock rate, with both sides of | |
3300 | * the link knowing how many bytes are fill. | |
3301 | * | |
3302 | * So, for a mode with a dotclock of 65Mhz, we would want to double the clock | |
3303 | * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be | |
3304 | * set to 130Mhz, and the SDVO multiplier set to 2x in this register and | |
3305 | * through an SDVO command. | |
3306 | * | |
3307 | * This register field has values of multiplication factor minus 1, with | |
3308 | * a maximum multiplier of 5 for SDVO. | |
3309 | */ | |
3310 | #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 | |
3311 | #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 | |
3312 | /* | |
3313 | * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. | |
3314 | * This best be set to the default value (3) or the CRT won't work. No, | |
3315 | * I don't entirely understand what this does... | |
3316 | */ | |
3317 | #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f | |
3318 | #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 | |
25eb05fc | 3319 | |
19ab4ed3 VS |
3320 | #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024) |
3321 | ||
f0f59a00 VS |
3322 | #define _FPA0 0x6040 |
3323 | #define _FPA1 0x6044 | |
3324 | #define _FPB0 0x6048 | |
3325 | #define _FPB1 0x604c | |
3326 | #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0) | |
3327 | #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1) | |
585fb111 | 3328 | #define FP_N_DIV_MASK 0x003f0000 |
f2b115e6 | 3329 | #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 |
585fb111 JB |
3330 | #define FP_N_DIV_SHIFT 16 |
3331 | #define FP_M1_DIV_MASK 0x00003f00 | |
3332 | #define FP_M1_DIV_SHIFT 8 | |
3333 | #define FP_M2_DIV_MASK 0x0000003f | |
f2b115e6 | 3334 | #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff |
585fb111 | 3335 | #define FP_M2_DIV_SHIFT 0 |
f0f59a00 | 3336 | #define DPLL_TEST _MMIO(0x606c) |
585fb111 JB |
3337 | #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) |
3338 | #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) | |
3339 | #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) | |
3340 | #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) | |
3341 | #define DPLLB_TEST_N_BYPASS (1 << 19) | |
3342 | #define DPLLB_TEST_M_BYPASS (1 << 18) | |
3343 | #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) | |
3344 | #define DPLLA_TEST_N_BYPASS (1 << 3) | |
3345 | #define DPLLA_TEST_M_BYPASS (1 << 2) | |
3346 | #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) | |
f0f59a00 | 3347 | #define D_STATE _MMIO(0x6104) |
5ee8ee86 PZ |
3348 | #define DSTATE_GFX_RESET_I830 (1 << 6) |
3349 | #define DSTATE_PLL_D3_OFF (1 << 3) | |
3350 | #define DSTATE_GFX_CLOCK_GATING (1 << 1) | |
3351 | #define DSTATE_DOT_CLOCK_GATING (1 << 0) | |
f0f59a00 | 3352 | #define DSPCLK_GATE_D _MMIO(dev_priv->info.display_mmio_offset + 0x6200) |
652c393a JB |
3353 | # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ |
3354 | # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ | |
3355 | # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ | |
3356 | # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ | |
3357 | # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ | |
3358 | # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ | |
3359 | # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ | |
ad8059cf | 3360 | # define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */ |
652c393a JB |
3361 | # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ |
3362 | # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ | |
3363 | # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ | |
3364 | # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ | |
3365 | # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ | |
3366 | # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ | |
3367 | # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ | |
3368 | # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ | |
3369 | # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ | |
3370 | # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ | |
3371 | # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ | |
3372 | # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ | |
3373 | # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) | |
3374 | # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) | |
3375 | # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) | |
3376 | # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) | |
3377 | # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ | |
3378 | # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ | |
3379 | # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ | |
3380 | # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) | |
3381 | # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) | |
646b4269 | 3382 | /* |
652c393a JB |
3383 | * This bit must be set on the 830 to prevent hangs when turning off the |
3384 | * overlay scaler. | |
3385 | */ | |
3386 | # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) | |
3387 | # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) | |
3388 | # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) | |
3389 | # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ | |
3390 | # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ | |
3391 | ||
f0f59a00 | 3392 | #define RENCLK_GATE_D1 _MMIO(0x6204) |
652c393a JB |
3393 | # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ |
3394 | # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ | |
3395 | # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) | |
3396 | # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) | |
3397 | # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) | |
3398 | # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) | |
3399 | # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) | |
3400 | # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) | |
3401 | # define MAG_CLOCK_GATE_DISABLE (1 << 5) | |
646b4269 | 3402 | /* This bit must be unset on 855,865 */ |
652c393a JB |
3403 | # define MECI_CLOCK_GATE_DISABLE (1 << 4) |
3404 | # define DCMP_CLOCK_GATE_DISABLE (1 << 3) | |
3405 | # define MEC_CLOCK_GATE_DISABLE (1 << 2) | |
3406 | # define MECO_CLOCK_GATE_DISABLE (1 << 1) | |
646b4269 | 3407 | /* This bit must be set on 855,865. */ |
652c393a JB |
3408 | # define SV_CLOCK_GATE_DISABLE (1 << 0) |
3409 | # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) | |
3410 | # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) | |
3411 | # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) | |
3412 | # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) | |
3413 | # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) | |
3414 | # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) | |
3415 | # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) | |
3416 | # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) | |
3417 | # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) | |
3418 | # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) | |
3419 | # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) | |
3420 | # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) | |
3421 | # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) | |
3422 | # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) | |
3423 | # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) | |
3424 | # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) | |
3425 | # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) | |
3426 | ||
3427 | # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) | |
646b4269 | 3428 | /* This bit must always be set on 965G/965GM */ |
652c393a JB |
3429 | # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) |
3430 | # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) | |
3431 | # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) | |
3432 | # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) | |
3433 | # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) | |
3434 | # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) | |
646b4269 | 3435 | /* This bit must always be set on 965G */ |
652c393a JB |
3436 | # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) |
3437 | # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) | |
3438 | # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) | |
3439 | # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) | |
3440 | # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) | |
3441 | # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) | |
3442 | # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) | |
3443 | # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) | |
3444 | # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) | |
3445 | # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) | |
3446 | # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) | |
3447 | # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) | |
3448 | # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) | |
3449 | # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) | |
3450 | # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) | |
3451 | # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) | |
3452 | # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) | |
3453 | # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) | |
3454 | # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) | |
3455 | ||
f0f59a00 | 3456 | #define RENCLK_GATE_D2 _MMIO(0x6208) |
652c393a JB |
3457 | #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) |
3458 | #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) | |
3459 | #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) | |
fa4f53c4 | 3460 | |
f0f59a00 | 3461 | #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */ |
fa4f53c4 VS |
3462 | #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4) |
3463 | ||
f0f59a00 VS |
3464 | #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */ |
3465 | #define DEUC _MMIO(0x6214) /* CRL only */ | |
585fb111 | 3466 | |
f0f59a00 | 3467 | #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500) |
5ee8ee86 | 3468 | #define FW_CSPWRDWNEN (1 << 15) |
ceb04246 | 3469 | |
f0f59a00 | 3470 | #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504) |
e0d8d59b | 3471 | |
f0f59a00 | 3472 | #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508) |
24eb2d59 CML |
3473 | #define CDCLK_FREQ_SHIFT 4 |
3474 | #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) | |
3475 | #define CZCLK_FREQ_MASK 0xf | |
1e69cd74 | 3476 | |
f0f59a00 | 3477 | #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C) |
1e69cd74 VS |
3478 | #define PFI_CREDIT_63 (9 << 28) /* chv only */ |
3479 | #define PFI_CREDIT_31 (8 << 28) /* chv only */ | |
3480 | #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */ | |
3481 | #define PFI_CREDIT_RESEND (1 << 27) | |
3482 | #define VGA_FAST_MODE_DISABLE (1 << 14) | |
3483 | ||
f0f59a00 | 3484 | #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510) |
24eb2d59 | 3485 | |
585fb111 JB |
3486 | /* |
3487 | * Palette regs | |
3488 | */ | |
a57c774a AK |
3489 | #define PALETTE_A_OFFSET 0xa000 |
3490 | #define PALETTE_B_OFFSET 0xa800 | |
84fd4f4e | 3491 | #define CHV_PALETTE_C_OFFSET 0xc000 |
f0f59a00 VS |
3492 | #define PALETTE(pipe, i) _MMIO(dev_priv->info.palette_offsets[pipe] + \ |
3493 | dev_priv->info.display_mmio_offset + (i) * 4) | |
585fb111 | 3494 | |
673a394b EA |
3495 | /* MCH MMIO space */ |
3496 | ||
3497 | /* | |
3498 | * MCHBAR mirror. | |
3499 | * | |
3500 | * This mirrors the MCHBAR MMIO space whose location is determined by | |
3501 | * device 0 function 0's pci config register 0x44 or 0x48 and matches it in | |
3502 | * every way. It is not accessible from the CP register read instructions. | |
3503 | * | |
515b2392 PZ |
3504 | * Starting from Haswell, you can't write registers using the MCHBAR mirror, |
3505 | * just read. | |
673a394b EA |
3506 | */ |
3507 | #define MCHBAR_MIRROR_BASE 0x10000 | |
3508 | ||
1398261a YL |
3509 | #define MCHBAR_MIRROR_BASE_SNB 0x140000 |
3510 | ||
f0f59a00 VS |
3511 | #define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34) |
3512 | #define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48) | |
7d316aec VS |
3513 | #define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16) |
3514 | #define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4) | |
db7fb605 | 3515 | #define G4X_STOLEN_RESERVED_ENABLE (1 << 0) |
7d316aec | 3516 | |
3ebecd07 | 3517 | /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */ |
f0f59a00 | 3518 | #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04) |
3ebecd07 | 3519 | |
646b4269 | 3520 | /* 915-945 and GM965 MCH register controlling DRAM channel access */ |
f0f59a00 | 3521 | #define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200) |
673a394b EA |
3522 | #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) |
3523 | #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) | |
3524 | #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) | |
3525 | #define DCC_ADDRESSING_MODE_MASK (3 << 0) | |
3526 | #define DCC_CHANNEL_XOR_DISABLE (1 << 10) | |
a7f014f2 | 3527 | #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) |
f0f59a00 | 3528 | #define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204) |
656bfa3a | 3529 | #define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20) |
673a394b | 3530 | |
646b4269 | 3531 | /* Pineview MCH register contains DDR3 setting */ |
f0f59a00 | 3532 | #define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8) |
95534263 LP |
3533 | #define CSHRDDR3CTL_DDR3 (1 << 2) |
3534 | ||
646b4269 | 3535 | /* 965 MCH register controlling DRAM channel configuration */ |
f0f59a00 VS |
3536 | #define C0DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x206) |
3537 | #define C1DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x606) | |
673a394b | 3538 | |
646b4269 | 3539 | /* snb MCH registers for reading the DRAM channel configuration */ |
f0f59a00 VS |
3540 | #define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004) |
3541 | #define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008) | |
3542 | #define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C) | |
f691e2f4 DV |
3543 | #define MAD_DIMM_ECC_MASK (0x3 << 24) |
3544 | #define MAD_DIMM_ECC_OFF (0x0 << 24) | |
3545 | #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) | |
3546 | #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) | |
3547 | #define MAD_DIMM_ECC_ON (0x3 << 24) | |
3548 | #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) | |
3549 | #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) | |
3550 | #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ | |
3551 | #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ | |
3552 | #define MAD_DIMM_B_DUAL_RANK (0x1 << 18) | |
3553 | #define MAD_DIMM_A_DUAL_RANK (0x1 << 17) | |
3554 | #define MAD_DIMM_A_SELECT (0x1 << 16) | |
3555 | /* DIMM sizes are in multiples of 256mb. */ | |
3556 | #define MAD_DIMM_B_SIZE_SHIFT 8 | |
3557 | #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) | |
3558 | #define MAD_DIMM_A_SIZE_SHIFT 0 | |
3559 | #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) | |
3560 | ||
646b4269 | 3561 | /* snb MCH registers for priority tuning */ |
f0f59a00 | 3562 | #define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10) |
1d7aaa0c DV |
3563 | #define MCH_SSKPD_WM0_MASK 0x3f |
3564 | #define MCH_SSKPD_WM0_VAL 0xc | |
f691e2f4 | 3565 | |
f0f59a00 | 3566 | #define MCH_SECP_NRG_STTS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x592c) |
ec013e7f | 3567 | |
b11248df | 3568 | /* Clocking configuration register */ |
f0f59a00 | 3569 | #define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00) |
7662c8bd | 3570 | #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */ |
b11248df KP |
3571 | #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ |
3572 | #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ | |
3573 | #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */ | |
3574 | #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ | |
6f38123e | 3575 | #define CLKCFG_FSB_1067_ALT (0 << 0) /* hrawclk 266 */ |
b11248df | 3576 | #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ |
6f38123e VS |
3577 | /* |
3578 | * Note that on at least on ELK the below value is reported for both | |
3579 | * 333 and 400 MHz BIOS FSB setting, but given that the gmch datasheet | |
3580 | * lists only 200/266/333 MHz FSB as supported let's decode it as 333 MHz. | |
3581 | */ | |
3582 | #define CLKCFG_FSB_1333_ALT (4 << 0) /* hrawclk 333 */ | |
b11248df | 3583 | #define CLKCFG_FSB_MASK (7 << 0) |
7662c8bd SL |
3584 | #define CLKCFG_MEM_533 (1 << 4) |
3585 | #define CLKCFG_MEM_667 (2 << 4) | |
3586 | #define CLKCFG_MEM_800 (3 << 4) | |
3587 | #define CLKCFG_MEM_MASK (7 << 4) | |
3588 | ||
f0f59a00 VS |
3589 | #define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38) |
3590 | #define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f) | |
34edce2f | 3591 | |
f0f59a00 | 3592 | #define TSC1 _MMIO(0x11001) |
5ee8ee86 | 3593 | #define TSE (1 << 0) |
f0f59a00 VS |
3594 | #define TR1 _MMIO(0x11006) |
3595 | #define TSFS _MMIO(0x11020) | |
7648fa99 JB |
3596 | #define TSFS_SLOPE_MASK 0x0000ff00 |
3597 | #define TSFS_SLOPE_SHIFT 8 | |
3598 | #define TSFS_INTR_MASK 0x000000ff | |
3599 | ||
f0f59a00 VS |
3600 | #define CRSTANDVID _MMIO(0x11100) |
3601 | #define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ | |
f97108d1 JB |
3602 | #define PXVFREQ_PX_MASK 0x7f000000 |
3603 | #define PXVFREQ_PX_SHIFT 24 | |
f0f59a00 VS |
3604 | #define VIDFREQ_BASE _MMIO(0x11110) |
3605 | #define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */ | |
3606 | #define VIDFREQ2 _MMIO(0x11114) | |
3607 | #define VIDFREQ3 _MMIO(0x11118) | |
3608 | #define VIDFREQ4 _MMIO(0x1111c) | |
f97108d1 JB |
3609 | #define VIDFREQ_P0_MASK 0x1f000000 |
3610 | #define VIDFREQ_P0_SHIFT 24 | |
3611 | #define VIDFREQ_P0_CSCLK_MASK 0x00f00000 | |
3612 | #define VIDFREQ_P0_CSCLK_SHIFT 20 | |
3613 | #define VIDFREQ_P0_CRCLK_MASK 0x000f0000 | |
3614 | #define VIDFREQ_P0_CRCLK_SHIFT 16 | |
3615 | #define VIDFREQ_P1_MASK 0x00001f00 | |
3616 | #define VIDFREQ_P1_SHIFT 8 | |
3617 | #define VIDFREQ_P1_CSCLK_MASK 0x000000f0 | |
3618 | #define VIDFREQ_P1_CSCLK_SHIFT 4 | |
3619 | #define VIDFREQ_P1_CRCLK_MASK 0x0000000f | |
f0f59a00 VS |
3620 | #define INTTOEXT_BASE_ILK _MMIO(0x11300) |
3621 | #define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */ | |
f97108d1 JB |
3622 | #define INTTOEXT_MAP3_SHIFT 24 |
3623 | #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) | |
3624 | #define INTTOEXT_MAP2_SHIFT 16 | |
3625 | #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) | |
3626 | #define INTTOEXT_MAP1_SHIFT 8 | |
3627 | #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) | |
3628 | #define INTTOEXT_MAP0_SHIFT 0 | |
3629 | #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) | |
f0f59a00 | 3630 | #define MEMSWCTL _MMIO(0x11170) /* Ironlake only */ |
f97108d1 JB |
3631 | #define MEMCTL_CMD_MASK 0xe000 |
3632 | #define MEMCTL_CMD_SHIFT 13 | |
3633 | #define MEMCTL_CMD_RCLK_OFF 0 | |
3634 | #define MEMCTL_CMD_RCLK_ON 1 | |
3635 | #define MEMCTL_CMD_CHFREQ 2 | |
3636 | #define MEMCTL_CMD_CHVID 3 | |
3637 | #define MEMCTL_CMD_VMMOFF 4 | |
3638 | #define MEMCTL_CMD_VMMON 5 | |
5ee8ee86 | 3639 | #define MEMCTL_CMD_STS (1 << 12) /* write 1 triggers command, clears |
f97108d1 JB |
3640 | when command complete */ |
3641 | #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ | |
3642 | #define MEMCTL_FREQ_SHIFT 8 | |
5ee8ee86 | 3643 | #define MEMCTL_SFCAVM (1 << 7) |
f97108d1 | 3644 | #define MEMCTL_TGT_VID_MASK 0x007f |
f0f59a00 VS |
3645 | #define MEMIHYST _MMIO(0x1117c) |
3646 | #define MEMINTREN _MMIO(0x11180) /* 16 bits */ | |
5ee8ee86 PZ |
3647 | #define MEMINT_RSEXIT_EN (1 << 8) |
3648 | #define MEMINT_CX_SUPR_EN (1 << 7) | |
3649 | #define MEMINT_CONT_BUSY_EN (1 << 6) | |
3650 | #define MEMINT_AVG_BUSY_EN (1 << 5) | |
3651 | #define MEMINT_EVAL_CHG_EN (1 << 4) | |
3652 | #define MEMINT_MON_IDLE_EN (1 << 3) | |
3653 | #define MEMINT_UP_EVAL_EN (1 << 2) | |
3654 | #define MEMINT_DOWN_EVAL_EN (1 << 1) | |
3655 | #define MEMINT_SW_CMD_EN (1 << 0) | |
f0f59a00 | 3656 | #define MEMINTRSTR _MMIO(0x11182) /* 16 bits */ |
f97108d1 JB |
3657 | #define MEM_RSEXIT_MASK 0xc000 |
3658 | #define MEM_RSEXIT_SHIFT 14 | |
3659 | #define MEM_CONT_BUSY_MASK 0x3000 | |
3660 | #define MEM_CONT_BUSY_SHIFT 12 | |
3661 | #define MEM_AVG_BUSY_MASK 0x0c00 | |
3662 | #define MEM_AVG_BUSY_SHIFT 10 | |
3663 | #define MEM_EVAL_CHG_MASK 0x0300 | |
3664 | #define MEM_EVAL_BUSY_SHIFT 8 | |
3665 | #define MEM_MON_IDLE_MASK 0x00c0 | |
3666 | #define MEM_MON_IDLE_SHIFT 6 | |
3667 | #define MEM_UP_EVAL_MASK 0x0030 | |
3668 | #define MEM_UP_EVAL_SHIFT 4 | |
3669 | #define MEM_DOWN_EVAL_MASK 0x000c | |
3670 | #define MEM_DOWN_EVAL_SHIFT 2 | |
3671 | #define MEM_SW_CMD_MASK 0x0003 | |
3672 | #define MEM_INT_STEER_GFX 0 | |
3673 | #define MEM_INT_STEER_CMR 1 | |
3674 | #define MEM_INT_STEER_SMI 2 | |
3675 | #define MEM_INT_STEER_SCI 3 | |
f0f59a00 | 3676 | #define MEMINTRSTS _MMIO(0x11184) |
5ee8ee86 PZ |
3677 | #define MEMINT_RSEXIT (1 << 7) |
3678 | #define MEMINT_CONT_BUSY (1 << 6) | |
3679 | #define MEMINT_AVG_BUSY (1 << 5) | |
3680 | #define MEMINT_EVAL_CHG (1 << 4) | |
3681 | #define MEMINT_MON_IDLE (1 << 3) | |
3682 | #define MEMINT_UP_EVAL (1 << 2) | |
3683 | #define MEMINT_DOWN_EVAL (1 << 1) | |
3684 | #define MEMINT_SW_CMD (1 << 0) | |
f0f59a00 | 3685 | #define MEMMODECTL _MMIO(0x11190) |
5ee8ee86 | 3686 | #define MEMMODE_BOOST_EN (1 << 31) |
f97108d1 JB |
3687 | #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ |
3688 | #define MEMMODE_BOOST_FREQ_SHIFT 24 | |
3689 | #define MEMMODE_IDLE_MODE_MASK 0x00030000 | |
3690 | #define MEMMODE_IDLE_MODE_SHIFT 16 | |
3691 | #define MEMMODE_IDLE_MODE_EVAL 0 | |
3692 | #define MEMMODE_IDLE_MODE_CONT 1 | |
5ee8ee86 PZ |
3693 | #define MEMMODE_HWIDLE_EN (1 << 15) |
3694 | #define MEMMODE_SWMODE_EN (1 << 14) | |
3695 | #define MEMMODE_RCLK_GATE (1 << 13) | |
3696 | #define MEMMODE_HW_UPDATE (1 << 12) | |
f97108d1 JB |
3697 | #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ |
3698 | #define MEMMODE_FSTART_SHIFT 8 | |
3699 | #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ | |
3700 | #define MEMMODE_FMAX_SHIFT 4 | |
3701 | #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ | |
f0f59a00 VS |
3702 | #define RCBMAXAVG _MMIO(0x1119c) |
3703 | #define MEMSWCTL2 _MMIO(0x1119e) /* Cantiga only */ | |
f97108d1 JB |
3704 | #define SWMEMCMD_RENDER_OFF (0 << 13) |
3705 | #define SWMEMCMD_RENDER_ON (1 << 13) | |
3706 | #define SWMEMCMD_SWFREQ (2 << 13) | |
3707 | #define SWMEMCMD_TARVID (3 << 13) | |
3708 | #define SWMEMCMD_VRM_OFF (4 << 13) | |
3709 | #define SWMEMCMD_VRM_ON (5 << 13) | |
5ee8ee86 PZ |
3710 | #define CMDSTS (1 << 12) |
3711 | #define SFCAVM (1 << 11) | |
f97108d1 JB |
3712 | #define SWFREQ_MASK 0x0380 /* P0-7 */ |
3713 | #define SWFREQ_SHIFT 7 | |
3714 | #define TARVID_MASK 0x001f | |
f0f59a00 VS |
3715 | #define MEMSTAT_CTG _MMIO(0x111a0) |
3716 | #define RCBMINAVG _MMIO(0x111a0) | |
3717 | #define RCUPEI _MMIO(0x111b0) | |
3718 | #define RCDNEI _MMIO(0x111b4) | |
3719 | #define RSTDBYCTL _MMIO(0x111b8) | |
5ee8ee86 PZ |
3720 | #define RS1EN (1 << 31) |
3721 | #define RS2EN (1 << 30) | |
3722 | #define RS3EN (1 << 29) | |
3723 | #define D3RS3EN (1 << 28) /* Display D3 imlies RS3 */ | |
3724 | #define SWPROMORSX (1 << 27) /* RSx promotion timers ignored */ | |
3725 | #define RCWAKERW (1 << 26) /* Resetwarn from PCH causes wakeup */ | |
3726 | #define DPRSLPVREN (1 << 25) /* Fast voltage ramp enable */ | |
3727 | #define GFXTGHYST (1 << 24) /* Hysteresis to allow trunk gating */ | |
3728 | #define RCX_SW_EXIT (1 << 23) /* Leave RSx and prevent re-entry */ | |
3729 | #define RSX_STATUS_MASK (7 << 20) | |
3730 | #define RSX_STATUS_ON (0 << 20) | |
3731 | #define RSX_STATUS_RC1 (1 << 20) | |
3732 | #define RSX_STATUS_RC1E (2 << 20) | |
3733 | #define RSX_STATUS_RS1 (3 << 20) | |
3734 | #define RSX_STATUS_RS2 (4 << 20) /* aka rc6 */ | |
3735 | #define RSX_STATUS_RSVD (5 << 20) /* deep rc6 unsupported on ilk */ | |
3736 | #define RSX_STATUS_RS3 (6 << 20) /* rs3 unsupported on ilk */ | |
3737 | #define RSX_STATUS_RSVD2 (7 << 20) | |
3738 | #define UWRCRSXE (1 << 19) /* wake counter limit prevents rsx */ | |
3739 | #define RSCRP (1 << 18) /* rs requests control on rs1/2 reqs */ | |
3740 | #define JRSC (1 << 17) /* rsx coupled to cpu c-state */ | |
3741 | #define RS2INC0 (1 << 16) /* allow rs2 in cpu c0 */ | |
3742 | #define RS1CONTSAV_MASK (3 << 14) | |
3743 | #define RS1CONTSAV_NO_RS1 (0 << 14) /* rs1 doesn't save/restore context */ | |
3744 | #define RS1CONTSAV_RSVD (1 << 14) | |
3745 | #define RS1CONTSAV_SAVE_RS1 (2 << 14) /* rs1 saves context */ | |
3746 | #define RS1CONTSAV_FULL_RS1 (3 << 14) /* rs1 saves and restores context */ | |
3747 | #define NORMSLEXLAT_MASK (3 << 12) | |
3748 | #define SLOW_RS123 (0 << 12) | |
3749 | #define SLOW_RS23 (1 << 12) | |
3750 | #define SLOW_RS3 (2 << 12) | |
3751 | #define NORMAL_RS123 (3 << 12) | |
3752 | #define RCMODE_TIMEOUT (1 << 11) /* 0 is eval interval method */ | |
3753 | #define IMPROMOEN (1 << 10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ | |
3754 | #define RCENTSYNC (1 << 9) /* rs coupled to cpu c-state (3/6/7) */ | |
3755 | #define STATELOCK (1 << 7) /* locked to rs_cstate if 0 */ | |
3756 | #define RS_CSTATE_MASK (3 << 4) | |
3757 | #define RS_CSTATE_C367_RS1 (0 << 4) | |
3758 | #define RS_CSTATE_C36_RS1_C7_RS2 (1 << 4) | |
3759 | #define RS_CSTATE_RSVD (2 << 4) | |
3760 | #define RS_CSTATE_C367_RS2 (3 << 4) | |
3761 | #define REDSAVES (1 << 3) /* no context save if was idle during rs0 */ | |
3762 | #define REDRESTORES (1 << 2) /* no restore if was idle during rs0 */ | |
f0f59a00 VS |
3763 | #define VIDCTL _MMIO(0x111c0) |
3764 | #define VIDSTS _MMIO(0x111c8) | |
3765 | #define VIDSTART _MMIO(0x111cc) /* 8 bits */ | |
3766 | #define MEMSTAT_ILK _MMIO(0x111f8) | |
f97108d1 JB |
3767 | #define MEMSTAT_VID_MASK 0x7f00 |
3768 | #define MEMSTAT_VID_SHIFT 8 | |
3769 | #define MEMSTAT_PSTATE_MASK 0x00f8 | |
3770 | #define MEMSTAT_PSTATE_SHIFT 3 | |
5ee8ee86 | 3771 | #define MEMSTAT_MON_ACTV (1 << 2) |
f97108d1 JB |
3772 | #define MEMSTAT_SRC_CTL_MASK 0x0003 |
3773 | #define MEMSTAT_SRC_CTL_CORE 0 | |
3774 | #define MEMSTAT_SRC_CTL_TRB 1 | |
3775 | #define MEMSTAT_SRC_CTL_THM 2 | |
3776 | #define MEMSTAT_SRC_CTL_STDBY 3 | |
f0f59a00 VS |
3777 | #define RCPREVBSYTUPAVG _MMIO(0x113b8) |
3778 | #define RCPREVBSYTDNAVG _MMIO(0x113bc) | |
3779 | #define PMMISC _MMIO(0x11214) | |
5ee8ee86 | 3780 | #define MCPPCE_EN (1 << 0) /* enable PM_MSG from PCH->MPC */ |
f0f59a00 VS |
3781 | #define SDEW _MMIO(0x1124c) |
3782 | #define CSIEW0 _MMIO(0x11250) | |
3783 | #define CSIEW1 _MMIO(0x11254) | |
3784 | #define CSIEW2 _MMIO(0x11258) | |
3785 | #define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */ | |
3786 | #define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */ | |
3787 | #define MCHAFE _MMIO(0x112c0) | |
3788 | #define CSIEC _MMIO(0x112e0) | |
3789 | #define DMIEC _MMIO(0x112e4) | |
3790 | #define DDREC _MMIO(0x112e8) | |
3791 | #define PEG0EC _MMIO(0x112ec) | |
3792 | #define PEG1EC _MMIO(0x112f0) | |
3793 | #define GFXEC _MMIO(0x112f4) | |
3794 | #define RPPREVBSYTUPAVG _MMIO(0x113b8) | |
3795 | #define RPPREVBSYTDNAVG _MMIO(0x113bc) | |
3796 | #define ECR _MMIO(0x11600) | |
5ee8ee86 PZ |
3797 | #define ECR_GPFE (1 << 31) |
3798 | #define ECR_IMONE (1 << 30) | |
7648fa99 | 3799 | #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ |
f0f59a00 VS |
3800 | #define OGW0 _MMIO(0x11608) |
3801 | #define OGW1 _MMIO(0x1160c) | |
3802 | #define EG0 _MMIO(0x11610) | |
3803 | #define EG1 _MMIO(0x11614) | |
3804 | #define EG2 _MMIO(0x11618) | |
3805 | #define EG3 _MMIO(0x1161c) | |
3806 | #define EG4 _MMIO(0x11620) | |
3807 | #define EG5 _MMIO(0x11624) | |
3808 | #define EG6 _MMIO(0x11628) | |
3809 | #define EG7 _MMIO(0x1162c) | |
3810 | #define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */ | |
3811 | #define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */ | |
3812 | #define LCFUSE02 _MMIO(0x116c0) | |
7648fa99 | 3813 | #define LCFUSE_HIV_MASK 0x000000ff |
f0f59a00 VS |
3814 | #define CSIPLL0 _MMIO(0x12c10) |
3815 | #define DDRMPLL1 _MMIO(0X12c20) | |
3816 | #define PEG_BAND_GAP_DATA _MMIO(0x14d68) | |
7d57382e | 3817 | |
f0f59a00 | 3818 | #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c) |
c4de7b0f | 3819 | #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7 |
c4de7b0f | 3820 | |
f0f59a00 VS |
3821 | #define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948) |
3822 | #define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070) | |
3823 | #define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994) | |
3824 | #define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998) | |
3825 | #define BXT_RP_STATE_CAP _MMIO(0x138170) | |
3b8d8d91 | 3826 | |
8a292d01 VS |
3827 | /* |
3828 | * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS | |
3829 | * 8300) freezing up around GPU hangs. Looks as if even | |
3830 | * scheduling/timer interrupts start misbehaving if the RPS | |
3831 | * EI/thresholds are "bad", leading to a very sluggish or even | |
3832 | * frozen machine. | |
3833 | */ | |
3834 | #define INTERVAL_1_28_US(us) roundup(((us) * 100) >> 7, 25) | |
de43ae9d | 3835 | #define INTERVAL_1_33_US(us) (((us) * 3) >> 2) |
26148bd3 | 3836 | #define INTERVAL_0_833_US(us) (((us) * 6) / 5) |
35ceabf3 | 3837 | #define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \ |
cc3f90f0 | 3838 | (IS_GEN9_LP(dev_priv) ? \ |
26148bd3 AG |
3839 | INTERVAL_0_833_US(us) : \ |
3840 | INTERVAL_1_33_US(us)) : \ | |
de43ae9d AG |
3841 | INTERVAL_1_28_US(us)) |
3842 | ||
52530cba AG |
3843 | #define INTERVAL_1_28_TO_US(interval) (((interval) << 7) / 100) |
3844 | #define INTERVAL_1_33_TO_US(interval) (((interval) << 2) / 3) | |
3845 | #define INTERVAL_0_833_TO_US(interval) (((interval) * 5) / 6) | |
35ceabf3 | 3846 | #define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \ |
cc3f90f0 | 3847 | (IS_GEN9_LP(dev_priv) ? \ |
52530cba AG |
3848 | INTERVAL_0_833_TO_US(interval) : \ |
3849 | INTERVAL_1_33_TO_US(interval)) : \ | |
3850 | INTERVAL_1_28_TO_US(interval)) | |
3851 | ||
aa40d6bb ZN |
3852 | /* |
3853 | * Logical Context regs | |
3854 | */ | |
ec62ed3e CW |
3855 | #define CCID _MMIO(0x2180) |
3856 | #define CCID_EN BIT(0) | |
3857 | #define CCID_EXTENDED_STATE_RESTORE BIT(2) | |
3858 | #define CCID_EXTENDED_STATE_SAVE BIT(3) | |
e8016055 VS |
3859 | /* |
3860 | * Notes on SNB/IVB/VLV context size: | |
3861 | * - Power context is saved elsewhere (LLC or stolen) | |
3862 | * - Ring/execlist context is saved on SNB, not on IVB | |
3863 | * - Extended context size already includes render context size | |
3864 | * - We always need to follow the extended context size. | |
3865 | * SNB BSpec has comments indicating that we should use the | |
3866 | * render context size instead if execlists are disabled, but | |
3867 | * based on empirical testing that's just nonsense. | |
3868 | * - Pipelined/VF state is saved on SNB/IVB respectively | |
3869 | * - GT1 size just indicates how much of render context | |
3870 | * doesn't need saving on GT1 | |
3871 | */ | |
f0f59a00 | 3872 | #define CXT_SIZE _MMIO(0x21a0) |
68d97538 VS |
3873 | #define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f) |
3874 | #define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f) | |
3875 | #define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f) | |
3876 | #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f) | |
3877 | #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f) | |
e8016055 | 3878 | #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \ |
fe1cc68f BW |
3879 | GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \ |
3880 | GEN6_CXT_PIPELINE_SIZE(cxt_reg)) | |
f0f59a00 | 3881 | #define GEN7_CXT_SIZE _MMIO(0x21a8) |
68d97538 VS |
3882 | #define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f) |
3883 | #define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7) | |
3884 | #define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f) | |
3885 | #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f) | |
3886 | #define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7) | |
3887 | #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f) | |
e8016055 | 3888 | #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \ |
4f91dd6f | 3889 | GEN7_CXT_VFSTATE_SIZE(ctx_reg)) |
8897644a | 3890 | |
c01fc532 ZW |
3891 | enum { |
3892 | INTEL_ADVANCED_CONTEXT = 0, | |
3893 | INTEL_LEGACY_32B_CONTEXT, | |
3894 | INTEL_ADVANCED_AD_CONTEXT, | |
3895 | INTEL_LEGACY_64B_CONTEXT | |
3896 | }; | |
3897 | ||
2355cf08 MK |
3898 | enum { |
3899 | FAULT_AND_HANG = 0, | |
3900 | FAULT_AND_HALT, /* Debug only */ | |
3901 | FAULT_AND_STREAM, | |
3902 | FAULT_AND_CONTINUE /* Unsupported */ | |
3903 | }; | |
3904 | ||
5ee8ee86 PZ |
3905 | #define GEN8_CTX_VALID (1 << 0) |
3906 | #define GEN8_CTX_FORCE_PD_RESTORE (1 << 1) | |
3907 | #define GEN8_CTX_FORCE_RESTORE (1 << 2) | |
3908 | #define GEN8_CTX_L3LLC_COHERENT (1 << 5) | |
3909 | #define GEN8_CTX_PRIVILEGE (1 << 8) | |
c01fc532 | 3910 | #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3 |
c01fc532 | 3911 | |
2355cf08 MK |
3912 | #define GEN8_CTX_ID_SHIFT 32 |
3913 | #define GEN8_CTX_ID_WIDTH 21 | |
ac52da6a DCS |
3914 | #define GEN11_SW_CTX_ID_SHIFT 37 |
3915 | #define GEN11_SW_CTX_ID_WIDTH 11 | |
3916 | #define GEN11_ENGINE_CLASS_SHIFT 61 | |
3917 | #define GEN11_ENGINE_CLASS_WIDTH 3 | |
3918 | #define GEN11_ENGINE_INSTANCE_SHIFT 48 | |
3919 | #define GEN11_ENGINE_INSTANCE_WIDTH 6 | |
c01fc532 | 3920 | |
f0f59a00 VS |
3921 | #define CHV_CLK_CTL1 _MMIO(0x101100) |
3922 | #define VLV_CLK_CTL2 _MMIO(0x101104) | |
e454a05d JB |
3923 | #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 |
3924 | ||
585fb111 JB |
3925 | /* |
3926 | * Overlay regs | |
3927 | */ | |
3928 | ||
f0f59a00 VS |
3929 | #define OVADD _MMIO(0x30000) |
3930 | #define DOVSTA _MMIO(0x30008) | |
5ee8ee86 | 3931 | #define OC_BUF (0x3 << 20) |
f0f59a00 VS |
3932 | #define OGAMC5 _MMIO(0x30010) |
3933 | #define OGAMC4 _MMIO(0x30014) | |
3934 | #define OGAMC3 _MMIO(0x30018) | |
3935 | #define OGAMC2 _MMIO(0x3001c) | |
3936 | #define OGAMC1 _MMIO(0x30020) | |
3937 | #define OGAMC0 _MMIO(0x30024) | |
585fb111 | 3938 | |
d965e7ac ID |
3939 | /* |
3940 | * GEN9 clock gating regs | |
3941 | */ | |
3942 | #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530) | |
df49ec82 | 3943 | #define DARBF_GATING_DIS (1 << 27) |
d965e7ac ID |
3944 | #define PWM2_GATING_DIS (1 << 14) |
3945 | #define PWM1_GATING_DIS (1 << 13) | |
3946 | ||
6481d5ed VS |
3947 | #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C) |
3948 | #define BXT_GMBUS_GATING_DIS (1 << 14) | |
3949 | ||
ed69cd40 ID |
3950 | #define _CLKGATE_DIS_PSL_A 0x46520 |
3951 | #define _CLKGATE_DIS_PSL_B 0x46524 | |
3952 | #define _CLKGATE_DIS_PSL_C 0x46528 | |
c4a4efa9 VS |
3953 | #define DUPS1_GATING_DIS (1 << 15) |
3954 | #define DUPS2_GATING_DIS (1 << 19) | |
3955 | #define DUPS3_GATING_DIS (1 << 23) | |
ed69cd40 ID |
3956 | #define DPF_GATING_DIS (1 << 10) |
3957 | #define DPF_RAM_GATING_DIS (1 << 9) | |
3958 | #define DPFR_GATING_DIS (1 << 8) | |
3959 | ||
3960 | #define CLKGATE_DIS_PSL(pipe) \ | |
3961 | _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B) | |
3962 | ||
90007bca RV |
3963 | /* |
3964 | * GEN10 clock gating regs | |
3965 | */ | |
3966 | #define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4) | |
3967 | #define SARBUNIT_CLKGATE_DIS (1 << 5) | |
0a60797a | 3968 | #define RCCUNIT_CLKGATE_DIS (1 << 7) |
0a437d49 | 3969 | #define MSCUNIT_CLKGATE_DIS (1 << 10) |
90007bca | 3970 | |
a4713c5a RV |
3971 | #define SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524) |
3972 | #define GWUNIT_CLKGATE_DIS (1 << 16) | |
3973 | ||
01ab0f92 RA |
3974 | #define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434) |
3975 | #define VFUNIT_CLKGATE_DIS (1 << 20) | |
3976 | ||
5ba700c7 OM |
3977 | #define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560) |
3978 | #define CGPSF_CLKGATE_DIS (1 << 3) | |
3979 | ||
585fb111 JB |
3980 | /* |
3981 | * Display engine regs | |
3982 | */ | |
3983 | ||
8bf1e9f1 | 3984 | /* Pipe A CRC regs */ |
a57c774a | 3985 | #define _PIPE_CRC_CTL_A 0x60050 |
8bf1e9f1 | 3986 | #define PIPE_CRC_ENABLE (1 << 31) |
b4437a41 | 3987 | /* ivb+ source selection */ |
8bf1e9f1 SH |
3988 | #define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29) |
3989 | #define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29) | |
3990 | #define PIPE_CRC_SOURCE_PF_IVB (2 << 29) | |
b4437a41 | 3991 | /* ilk+ source selection */ |
5a6b5c84 DV |
3992 | #define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28) |
3993 | #define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28) | |
3994 | #define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28) | |
3995 | /* embedded DP port on the north display block, reserved on ivb */ | |
3996 | #define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28) | |
3997 | #define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */ | |
b4437a41 DV |
3998 | /* vlv source selection */ |
3999 | #define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27) | |
4000 | #define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27) | |
4001 | #define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27) | |
4002 | /* with DP port the pipe source is invalid */ | |
4003 | #define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27) | |
4004 | #define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27) | |
4005 | #define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27) | |
4006 | /* gen3+ source selection */ | |
4007 | #define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28) | |
4008 | #define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28) | |
4009 | #define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28) | |
4010 | /* with DP/TV port the pipe source is invalid */ | |
4011 | #define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28) | |
4012 | #define PIPE_CRC_SOURCE_TV_PRE (4 << 28) | |
4013 | #define PIPE_CRC_SOURCE_TV_POST (5 << 28) | |
4014 | #define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28) | |
4015 | #define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28) | |
4016 | /* gen2 doesn't have source selection bits */ | |
52f843f6 | 4017 | #define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30) |
b4437a41 | 4018 | |
5a6b5c84 DV |
4019 | #define _PIPE_CRC_RES_1_A_IVB 0x60064 |
4020 | #define _PIPE_CRC_RES_2_A_IVB 0x60068 | |
4021 | #define _PIPE_CRC_RES_3_A_IVB 0x6006c | |
4022 | #define _PIPE_CRC_RES_4_A_IVB 0x60070 | |
4023 | #define _PIPE_CRC_RES_5_A_IVB 0x60074 | |
4024 | ||
a57c774a AK |
4025 | #define _PIPE_CRC_RES_RED_A 0x60060 |
4026 | #define _PIPE_CRC_RES_GREEN_A 0x60064 | |
4027 | #define _PIPE_CRC_RES_BLUE_A 0x60068 | |
4028 | #define _PIPE_CRC_RES_RES1_A_I915 0x6006c | |
4029 | #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 | |
8bf1e9f1 SH |
4030 | |
4031 | /* Pipe B CRC regs */ | |
5a6b5c84 DV |
4032 | #define _PIPE_CRC_RES_1_B_IVB 0x61064 |
4033 | #define _PIPE_CRC_RES_2_B_IVB 0x61068 | |
4034 | #define _PIPE_CRC_RES_3_B_IVB 0x6106c | |
4035 | #define _PIPE_CRC_RES_4_B_IVB 0x61070 | |
4036 | #define _PIPE_CRC_RES_5_B_IVB 0x61074 | |
8bf1e9f1 | 4037 | |
f0f59a00 VS |
4038 | #define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A) |
4039 | #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB) | |
4040 | #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB) | |
4041 | #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB) | |
4042 | #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB) | |
4043 | #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB) | |
4044 | ||
4045 | #define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A) | |
4046 | #define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A) | |
4047 | #define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A) | |
4048 | #define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915) | |
4049 | #define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X) | |
5a6b5c84 | 4050 | |
585fb111 | 4051 | /* Pipe A timing regs */ |
a57c774a AK |
4052 | #define _HTOTAL_A 0x60000 |
4053 | #define _HBLANK_A 0x60004 | |
4054 | #define _HSYNC_A 0x60008 | |
4055 | #define _VTOTAL_A 0x6000c | |
4056 | #define _VBLANK_A 0x60010 | |
4057 | #define _VSYNC_A 0x60014 | |
4058 | #define _PIPEASRC 0x6001c | |
4059 | #define _BCLRPAT_A 0x60020 | |
4060 | #define _VSYNCSHIFT_A 0x60028 | |
ebb69c95 | 4061 | #define _PIPE_MULT_A 0x6002c |
585fb111 JB |
4062 | |
4063 | /* Pipe B timing regs */ | |
a57c774a AK |
4064 | #define _HTOTAL_B 0x61000 |
4065 | #define _HBLANK_B 0x61004 | |
4066 | #define _HSYNC_B 0x61008 | |
4067 | #define _VTOTAL_B 0x6100c | |
4068 | #define _VBLANK_B 0x61010 | |
4069 | #define _VSYNC_B 0x61014 | |
4070 | #define _PIPEBSRC 0x6101c | |
4071 | #define _BCLRPAT_B 0x61020 | |
4072 | #define _VSYNCSHIFT_B 0x61028 | |
ebb69c95 | 4073 | #define _PIPE_MULT_B 0x6102c |
a57c774a AK |
4074 | |
4075 | #define TRANSCODER_A_OFFSET 0x60000 | |
4076 | #define TRANSCODER_B_OFFSET 0x61000 | |
4077 | #define TRANSCODER_C_OFFSET 0x62000 | |
84fd4f4e | 4078 | #define CHV_TRANSCODER_C_OFFSET 0x63000 |
a57c774a AK |
4079 | #define TRANSCODER_EDP_OFFSET 0x6f000 |
4080 | ||
f0f59a00 | 4081 | #define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \ |
5c969aa7 DL |
4082 | dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \ |
4083 | dev_priv->info.display_mmio_offset) | |
a57c774a | 4084 | |
f0f59a00 VS |
4085 | #define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A) |
4086 | #define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A) | |
4087 | #define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A) | |
4088 | #define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A) | |
4089 | #define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A) | |
4090 | #define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A) | |
4091 | #define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A) | |
4092 | #define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A) | |
4093 | #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC) | |
4094 | #define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A) | |
5eddb70b | 4095 | |
c8f7df58 RV |
4096 | /* VLV eDP PSR registers */ |
4097 | #define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090) | |
4098 | #define _PSRCTLB (VLV_DISPLAY_BASE + 0x61090) | |
5ee8ee86 PZ |
4099 | #define VLV_EDP_PSR_ENABLE (1 << 0) |
4100 | #define VLV_EDP_PSR_RESET (1 << 1) | |
4101 | #define VLV_EDP_PSR_MODE_MASK (7 << 2) | |
4102 | #define VLV_EDP_PSR_MODE_HW_TIMER (1 << 3) | |
4103 | #define VLV_EDP_PSR_MODE_SW_TIMER (1 << 2) | |
4104 | #define VLV_EDP_PSR_SINGLE_FRAME_UPDATE (1 << 7) | |
4105 | #define VLV_EDP_PSR_ACTIVE_ENTRY (1 << 8) | |
4106 | #define VLV_EDP_PSR_SRC_TRANSMITTER_STATE (1 << 9) | |
4107 | #define VLV_EDP_PSR_DBL_FRAME (1 << 10) | |
4108 | #define VLV_EDP_PSR_FRAME_COUNT_MASK (0xff << 16) | |
c8f7df58 | 4109 | #define VLV_EDP_PSR_IDLE_FRAME_SHIFT 16 |
f0f59a00 | 4110 | #define VLV_PSRCTL(pipe) _MMIO_PIPE(pipe, _PSRCTLA, _PSRCTLB) |
c8f7df58 RV |
4111 | |
4112 | #define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0) | |
4113 | #define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0) | |
5ee8ee86 PZ |
4114 | #define VLV_EDP_PSR_SDP_FREQ_MASK (3 << 30) |
4115 | #define VLV_EDP_PSR_SDP_FREQ_ONCE (1 << 31) | |
4116 | #define VLV_EDP_PSR_SDP_FREQ_EVFRAME (1 << 30) | |
f0f59a00 | 4117 | #define VLV_VSCSDP(pipe) _MMIO_PIPE(pipe, _VSCSDPA, _VSCSDPB) |
c8f7df58 RV |
4118 | |
4119 | #define _PSRSTATA (VLV_DISPLAY_BASE + 0x60094) | |
4120 | #define _PSRSTATB (VLV_DISPLAY_BASE + 0x61094) | |
5ee8ee86 | 4121 | #define VLV_EDP_PSR_LAST_STATE_MASK (7 << 3) |
c8f7df58 | 4122 | #define VLV_EDP_PSR_CURR_STATE_MASK 7 |
5ee8ee86 PZ |
4123 | #define VLV_EDP_PSR_DISABLED (0 << 0) |
4124 | #define VLV_EDP_PSR_INACTIVE (1 << 0) | |
4125 | #define VLV_EDP_PSR_IN_TRANS_TO_ACTIVE (2 << 0) | |
4126 | #define VLV_EDP_PSR_ACTIVE_NORFB_UP (3 << 0) | |
4127 | #define VLV_EDP_PSR_ACTIVE_SF_UPDATE (4 << 0) | |
4128 | #define VLV_EDP_PSR_EXIT (5 << 0) | |
4129 | #define VLV_EDP_PSR_IN_TRANS (1 << 7) | |
f0f59a00 | 4130 | #define VLV_PSRSTAT(pipe) _MMIO_PIPE(pipe, _PSRSTATA, _PSRSTATB) |
c8f7df58 | 4131 | |
ed8546ac | 4132 | /* HSW+ eDP PSR registers */ |
443a389f VS |
4133 | #define HSW_EDP_PSR_BASE 0x64800 |
4134 | #define BDW_EDP_PSR_BASE 0x6f800 | |
f0f59a00 | 4135 | #define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0) |
5ee8ee86 PZ |
4136 | #define EDP_PSR_ENABLE (1 << 31) |
4137 | #define BDW_PSR_SINGLE_FRAME (1 << 30) | |
4138 | #define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1 << 29) /* SW can't modify */ | |
4139 | #define EDP_PSR_LINK_STANDBY (1 << 27) | |
4140 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3 << 25) | |
4141 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0 << 25) | |
4142 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1 << 25) | |
4143 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2 << 25) | |
4144 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3 << 25) | |
2b28bb1b | 4145 | #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20 |
5ee8ee86 PZ |
4146 | #define EDP_PSR_SKIP_AUX_EXIT (1 << 12) |
4147 | #define EDP_PSR_TP1_TP2_SEL (0 << 11) | |
4148 | #define EDP_PSR_TP1_TP3_SEL (1 << 11) | |
00c8f194 | 4149 | #define EDP_PSR_CRC_ENABLE (1 << 10) /* BDW+ */ |
5ee8ee86 PZ |
4150 | #define EDP_PSR_TP2_TP3_TIME_500us (0 << 8) |
4151 | #define EDP_PSR_TP2_TP3_TIME_100us (1 << 8) | |
4152 | #define EDP_PSR_TP2_TP3_TIME_2500us (2 << 8) | |
4153 | #define EDP_PSR_TP2_TP3_TIME_0us (3 << 8) | |
4154 | #define EDP_PSR_TP1_TIME_500us (0 << 4) | |
4155 | #define EDP_PSR_TP1_TIME_100us (1 << 4) | |
4156 | #define EDP_PSR_TP1_TIME_2500us (2 << 4) | |
4157 | #define EDP_PSR_TP1_TIME_0us (3 << 4) | |
2b28bb1b RV |
4158 | #define EDP_PSR_IDLE_FRAME_SHIFT 0 |
4159 | ||
fc340442 DV |
4160 | /* Bspec claims those aren't shifted but stay at 0x64800 */ |
4161 | #define EDP_PSR_IMR _MMIO(0x64834) | |
4162 | #define EDP_PSR_IIR _MMIO(0x64838) | |
e04f7ece VS |
4163 | #define EDP_PSR_ERROR(trans) (1 << (((trans) * 8 + 10) & 31)) |
4164 | #define EDP_PSR_POST_EXIT(trans) (1 << (((trans) * 8 + 9) & 31)) | |
4165 | #define EDP_PSR_PRE_ENTRY(trans) (1 << (((trans) * 8 + 8) & 31)) | |
fc340442 | 4166 | |
f0f59a00 | 4167 | #define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10) |
d544e918 DP |
4168 | #define EDP_PSR_AUX_CTL_TIME_OUT_MASK (3 << 26) |
4169 | #define EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK (0x1f << 20) | |
4170 | #define EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK (0xf << 16) | |
4171 | #define EDP_PSR_AUX_CTL_ERROR_INTERRUPT (1 << 11) | |
4172 | #define EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK (0x7ff) | |
4173 | ||
f0f59a00 | 4174 | #define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */ |
2b28bb1b | 4175 | |
861023e0 | 4176 | #define EDP_PSR_STATUS _MMIO(dev_priv->psr_mmio_base + 0x40) |
5ee8ee86 | 4177 | #define EDP_PSR_STATUS_STATE_MASK (7 << 29) |
00b06296 | 4178 | #define EDP_PSR_STATUS_STATE_SHIFT 29 |
5ee8ee86 PZ |
4179 | #define EDP_PSR_STATUS_STATE_IDLE (0 << 29) |
4180 | #define EDP_PSR_STATUS_STATE_SRDONACK (1 << 29) | |
4181 | #define EDP_PSR_STATUS_STATE_SRDENT (2 << 29) | |
4182 | #define EDP_PSR_STATUS_STATE_BUFOFF (3 << 29) | |
4183 | #define EDP_PSR_STATUS_STATE_BUFON (4 << 29) | |
4184 | #define EDP_PSR_STATUS_STATE_AUXACK (5 << 29) | |
4185 | #define EDP_PSR_STATUS_STATE_SRDOFFACK (6 << 29) | |
4186 | #define EDP_PSR_STATUS_LINK_MASK (3 << 26) | |
4187 | #define EDP_PSR_STATUS_LINK_FULL_OFF (0 << 26) | |
4188 | #define EDP_PSR_STATUS_LINK_FULL_ON (1 << 26) | |
4189 | #define EDP_PSR_STATUS_LINK_STANDBY (2 << 26) | |
e91fd8c6 RV |
4190 | #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20 |
4191 | #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f | |
4192 | #define EDP_PSR_STATUS_COUNT_SHIFT 16 | |
4193 | #define EDP_PSR_STATUS_COUNT_MASK 0xf | |
5ee8ee86 PZ |
4194 | #define EDP_PSR_STATUS_AUX_ERROR (1 << 15) |
4195 | #define EDP_PSR_STATUS_AUX_SENDING (1 << 12) | |
4196 | #define EDP_PSR_STATUS_SENDING_IDLE (1 << 9) | |
4197 | #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1 << 8) | |
4198 | #define EDP_PSR_STATUS_SENDING_TP1 (1 << 4) | |
e91fd8c6 RV |
4199 | #define EDP_PSR_STATUS_IDLE_MASK 0xf |
4200 | ||
f0f59a00 | 4201 | #define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr_mmio_base + 0x44) |
e91fd8c6 | 4202 | #define EDP_PSR_PERF_CNT_MASK 0xffffff |
2b28bb1b | 4203 | |
62801bf6 | 4204 | #define EDP_PSR_DEBUG _MMIO(dev_priv->psr_mmio_base + 0x60) /* PSR_MASK on SKL+ */ |
5ee8ee86 PZ |
4205 | #define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1 << 28) |
4206 | #define EDP_PSR_DEBUG_MASK_LPSP (1 << 27) | |
4207 | #define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26) | |
4208 | #define EDP_PSR_DEBUG_MASK_HPD (1 << 25) | |
4209 | #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) | |
4210 | #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */ | |
2b28bb1b | 4211 | |
f0f59a00 | 4212 | #define EDP_PSR2_CTL _MMIO(0x6f900) |
5ee8ee86 PZ |
4213 | #define EDP_PSR2_ENABLE (1 << 31) |
4214 | #define EDP_SU_TRACK_ENABLE (1 << 30) | |
4215 | #define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */ | |
4216 | #define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and CNL+ */ | |
4217 | #define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20) | |
4218 | #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20) | |
4219 | #define EDP_PSR2_TP2_TIME_500us (0 << 8) | |
4220 | #define EDP_PSR2_TP2_TIME_100us (1 << 8) | |
4221 | #define EDP_PSR2_TP2_TIME_2500us (2 << 8) | |
4222 | #define EDP_PSR2_TP2_TIME_50us (3 << 8) | |
4223 | #define EDP_PSR2_TP2_TIME_MASK (3 << 8) | |
474d1ec4 | 4224 | #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 |
5ee8ee86 PZ |
4225 | #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4) |
4226 | #define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4) | |
fe36181b JRS |
4227 | #define EDP_PSR2_IDLE_FRAME_MASK 0xf |
4228 | #define EDP_PSR2_IDLE_FRAME_SHIFT 0 | |
474d1ec4 | 4229 | |
bc18b4df JRS |
4230 | #define _PSR_EVENT_TRANS_A 0x60848 |
4231 | #define _PSR_EVENT_TRANS_B 0x61848 | |
4232 | #define _PSR_EVENT_TRANS_C 0x62848 | |
4233 | #define _PSR_EVENT_TRANS_D 0x63848 | |
4234 | #define _PSR_EVENT_TRANS_EDP 0x6F848 | |
4235 | #define PSR_EVENT(trans) _MMIO_TRANS2(trans, _PSR_EVENT_TRANS_A) | |
4236 | #define PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17) | |
4237 | #define PSR_EVENT_PSR2_DISABLED (1 << 16) | |
4238 | #define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15) | |
4239 | #define PSR_EVENT_SU_CRC_FIFO_UNDERRUN (1 << 14) | |
4240 | #define PSR_EVENT_GRAPHICS_RESET (1 << 12) | |
4241 | #define PSR_EVENT_PCH_INTERRUPT (1 << 11) | |
4242 | #define PSR_EVENT_MEMORY_UP (1 << 10) | |
4243 | #define PSR_EVENT_FRONT_BUFFER_MODIFY (1 << 9) | |
4244 | #define PSR_EVENT_WD_TIMER_EXPIRE (1 << 8) | |
4245 | #define PSR_EVENT_PIPE_REGISTERS_UPDATE (1 << 6) | |
4246 | #define PSR_EVENT_REGISTER_UPDATE (1 << 5) | |
4247 | #define PSR_EVENT_HDCP_ENABLE (1 << 4) | |
4248 | #define PSR_EVENT_KVMR_SESSION_ENABLE (1 << 3) | |
4249 | #define PSR_EVENT_VBI_ENABLE (1 << 2) | |
4250 | #define PSR_EVENT_LPSP_MODE_EXIT (1 << 1) | |
4251 | #define PSR_EVENT_PSR_DISABLE (1 << 0) | |
4252 | ||
861023e0 | 4253 | #define EDP_PSR2_STATUS _MMIO(0x6f940) |
5ee8ee86 | 4254 | #define EDP_PSR2_STATUS_STATE_MASK (0xf << 28) |
6ba1f9e1 | 4255 | #define EDP_PSR2_STATUS_STATE_SHIFT 28 |
474d1ec4 | 4256 | |
585fb111 | 4257 | /* VGA port control */ |
f0f59a00 VS |
4258 | #define ADPA _MMIO(0x61100) |
4259 | #define PCH_ADPA _MMIO(0xe1100) | |
4260 | #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100) | |
ebc0fd88 | 4261 | |
5ee8ee86 | 4262 | #define ADPA_DAC_ENABLE (1 << 31) |
585fb111 | 4263 | #define ADPA_DAC_DISABLE 0 |
6102a8ee | 4264 | #define ADPA_PIPE_SEL_SHIFT 30 |
5ee8ee86 | 4265 | #define ADPA_PIPE_SEL_MASK (1 << 30) |
6102a8ee VS |
4266 | #define ADPA_PIPE_SEL(pipe) ((pipe) << 30) |
4267 | #define ADPA_PIPE_SEL_SHIFT_CPT 29 | |
5ee8ee86 | 4268 | #define ADPA_PIPE_SEL_MASK_CPT (3 << 29) |
6102a8ee | 4269 | #define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29) |
ebc0fd88 | 4270 | #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ |
5ee8ee86 PZ |
4271 | #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0 << 24) |
4272 | #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3 << 24) | |
4273 | #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24) | |
4274 | #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2 << 24) | |
4275 | #define ADPA_CRT_HOTPLUG_ENABLE (1 << 23) | |
4276 | #define ADPA_CRT_HOTPLUG_PERIOD_64 (0 << 22) | |
4277 | #define ADPA_CRT_HOTPLUG_PERIOD_128 (1 << 22) | |
4278 | #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0 << 21) | |
4279 | #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1 << 21) | |
4280 | #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0 << 20) | |
4281 | #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1 << 20) | |
4282 | #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0 << 18) | |
4283 | #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1 << 18) | |
4284 | #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2 << 18) | |
4285 | #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3 << 18) | |
4286 | #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0 << 17) | |
4287 | #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1 << 17) | |
4288 | #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16) | |
4289 | #define ADPA_USE_VGA_HVPOLARITY (1 << 15) | |
585fb111 | 4290 | #define ADPA_SETS_HVPOLARITY 0 |
5ee8ee86 | 4291 | #define ADPA_VSYNC_CNTL_DISABLE (1 << 10) |
585fb111 | 4292 | #define ADPA_VSYNC_CNTL_ENABLE 0 |
5ee8ee86 | 4293 | #define ADPA_HSYNC_CNTL_DISABLE (1 << 11) |
585fb111 | 4294 | #define ADPA_HSYNC_CNTL_ENABLE 0 |
5ee8ee86 | 4295 | #define ADPA_VSYNC_ACTIVE_HIGH (1 << 4) |
585fb111 | 4296 | #define ADPA_VSYNC_ACTIVE_LOW 0 |
5ee8ee86 | 4297 | #define ADPA_HSYNC_ACTIVE_HIGH (1 << 3) |
585fb111 | 4298 | #define ADPA_HSYNC_ACTIVE_LOW 0 |
5ee8ee86 PZ |
4299 | #define ADPA_DPMS_MASK (~(3 << 10)) |
4300 | #define ADPA_DPMS_ON (0 << 10) | |
4301 | #define ADPA_DPMS_SUSPEND (1 << 10) | |
4302 | #define ADPA_DPMS_STANDBY (2 << 10) | |
4303 | #define ADPA_DPMS_OFF (3 << 10) | |
585fb111 | 4304 | |
939fe4d7 | 4305 | |
585fb111 | 4306 | /* Hotplug control (945+ only) */ |
f0f59a00 | 4307 | #define PORT_HOTPLUG_EN _MMIO(dev_priv->info.display_mmio_offset + 0x61110) |
26739f12 DV |
4308 | #define PORTB_HOTPLUG_INT_EN (1 << 29) |
4309 | #define PORTC_HOTPLUG_INT_EN (1 << 28) | |
4310 | #define PORTD_HOTPLUG_INT_EN (1 << 27) | |
585fb111 JB |
4311 | #define SDVOB_HOTPLUG_INT_EN (1 << 26) |
4312 | #define SDVOC_HOTPLUG_INT_EN (1 << 25) | |
4313 | #define TV_HOTPLUG_INT_EN (1 << 18) | |
4314 | #define CRT_HOTPLUG_INT_EN (1 << 9) | |
e5868a31 EE |
4315 | #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \ |
4316 | PORTC_HOTPLUG_INT_EN | \ | |
4317 | PORTD_HOTPLUG_INT_EN | \ | |
4318 | SDVOC_HOTPLUG_INT_EN | \ | |
4319 | SDVOB_HOTPLUG_INT_EN | \ | |
4320 | CRT_HOTPLUG_INT_EN) | |
585fb111 | 4321 | #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) |
771cb081 ZY |
4322 | #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) |
4323 | /* must use period 64 on GM45 according to docs */ | |
4324 | #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) | |
4325 | #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) | |
4326 | #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) | |
4327 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) | |
4328 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) | |
4329 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) | |
4330 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) | |
4331 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) | |
4332 | #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) | |
4333 | #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) | |
4334 | #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) | |
4335 | #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) | |
585fb111 | 4336 | |
f0f59a00 | 4337 | #define PORT_HOTPLUG_STAT _MMIO(dev_priv->info.display_mmio_offset + 0x61114) |
0ce99f74 | 4338 | /* |
0780cd36 | 4339 | * HDMI/DP bits are g4x+ |
0ce99f74 DV |
4340 | * |
4341 | * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused. | |
4342 | * Please check the detailed lore in the commit message for for experimental | |
4343 | * evidence. | |
4344 | */ | |
0780cd36 VS |
4345 | /* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */ |
4346 | #define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29) | |
4347 | #define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28) | |
4348 | #define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27) | |
4349 | /* G4X/VLV/CHV DP/HDMI bits again match Bspec */ | |
4350 | #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27) | |
232a6ee9 | 4351 | #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) |
0780cd36 | 4352 | #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29) |
26739f12 | 4353 | #define PORTD_HOTPLUG_INT_STATUS (3 << 21) |
a211b497 DV |
4354 | #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) |
4355 | #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) | |
26739f12 | 4356 | #define PORTC_HOTPLUG_INT_STATUS (3 << 19) |
a211b497 DV |
4357 | #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19) |
4358 | #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19) | |
26739f12 | 4359 | #define PORTB_HOTPLUG_INT_STATUS (3 << 17) |
a211b497 DV |
4360 | #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17) |
4361 | #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17) | |
084b612e | 4362 | /* CRT/TV common between gen3+ */ |
585fb111 JB |
4363 | #define CRT_HOTPLUG_INT_STATUS (1 << 11) |
4364 | #define TV_HOTPLUG_INT_STATUS (1 << 10) | |
4365 | #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) | |
4366 | #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) | |
4367 | #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) | |
4368 | #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) | |
4aeebd74 DV |
4369 | #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) |
4370 | #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) | |
4371 | #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) | |
bfbdb420 ID |
4372 | #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4) |
4373 | ||
084b612e CW |
4374 | /* SDVO is different across gen3/4 */ |
4375 | #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) | |
4376 | #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) | |
4f7fd709 DV |
4377 | /* |
4378 | * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, | |
4379 | * since reality corrobates that they're the same as on gen3. But keep these | |
4380 | * bits here (and the comment!) to help any other lost wanderers back onto the | |
4381 | * right tracks. | |
4382 | */ | |
084b612e CW |
4383 | #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) |
4384 | #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) | |
4385 | #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) | |
4386 | #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) | |
e5868a31 EE |
4387 | #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \ |
4388 | SDVOB_HOTPLUG_INT_STATUS_G4X | \ | |
4389 | SDVOC_HOTPLUG_INT_STATUS_G4X | \ | |
4390 | PORTB_HOTPLUG_INT_STATUS | \ | |
4391 | PORTC_HOTPLUG_INT_STATUS | \ | |
4392 | PORTD_HOTPLUG_INT_STATUS) | |
e5868a31 EE |
4393 | |
4394 | #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \ | |
4395 | SDVOB_HOTPLUG_INT_STATUS_I915 | \ | |
4396 | SDVOC_HOTPLUG_INT_STATUS_I915 | \ | |
4397 | PORTB_HOTPLUG_INT_STATUS | \ | |
4398 | PORTC_HOTPLUG_INT_STATUS | \ | |
4399 | PORTD_HOTPLUG_INT_STATUS) | |
585fb111 | 4400 | |
c20cd312 PZ |
4401 | /* SDVO and HDMI port control. |
4402 | * The same register may be used for SDVO or HDMI */ | |
f0f59a00 VS |
4403 | #define _GEN3_SDVOB 0x61140 |
4404 | #define _GEN3_SDVOC 0x61160 | |
4405 | #define GEN3_SDVOB _MMIO(_GEN3_SDVOB) | |
4406 | #define GEN3_SDVOC _MMIO(_GEN3_SDVOC) | |
c20cd312 PZ |
4407 | #define GEN4_HDMIB GEN3_SDVOB |
4408 | #define GEN4_HDMIC GEN3_SDVOC | |
f0f59a00 VS |
4409 | #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140) |
4410 | #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160) | |
4411 | #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C) | |
4412 | #define PCH_SDVOB _MMIO(0xe1140) | |
c20cd312 | 4413 | #define PCH_HDMIB PCH_SDVOB |
f0f59a00 VS |
4414 | #define PCH_HDMIC _MMIO(0xe1150) |
4415 | #define PCH_HDMID _MMIO(0xe1160) | |
c20cd312 | 4416 | |
f0f59a00 | 4417 | #define PORT_DFT_I9XX _MMIO(0x61150) |
84093603 | 4418 | #define DC_BALANCE_RESET (1 << 25) |
f0f59a00 | 4419 | #define PORT_DFT2_G4X _MMIO(dev_priv->info.display_mmio_offset + 0x61154) |
84093603 | 4420 | #define DC_BALANCE_RESET_VLV (1 << 31) |
eb736679 VS |
4421 | #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0)) |
4422 | #define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */ | |
84093603 DV |
4423 | #define PIPE_B_SCRAMBLE_RESET (1 << 1) |
4424 | #define PIPE_A_SCRAMBLE_RESET (1 << 0) | |
4425 | ||
c20cd312 PZ |
4426 | /* Gen 3 SDVO bits: */ |
4427 | #define SDVO_ENABLE (1 << 31) | |
76203467 | 4428 | #define SDVO_PIPE_SEL_SHIFT 30 |
dc0fa718 | 4429 | #define SDVO_PIPE_SEL_MASK (1 << 30) |
76203467 | 4430 | #define SDVO_PIPE_SEL(pipe) ((pipe) << 30) |
c20cd312 PZ |
4431 | #define SDVO_STALL_SELECT (1 << 29) |
4432 | #define SDVO_INTERRUPT_ENABLE (1 << 26) | |
646b4269 | 4433 | /* |
585fb111 | 4434 | * 915G/GM SDVO pixel multiplier. |
585fb111 | 4435 | * Programmed value is multiplier - 1, up to 5x. |
585fb111 JB |
4436 | * \sa DPLL_MD_UDI_MULTIPLIER_MASK |
4437 | */ | |
c20cd312 | 4438 | #define SDVO_PORT_MULTIPLY_MASK (7 << 23) |
585fb111 | 4439 | #define SDVO_PORT_MULTIPLY_SHIFT 23 |
c20cd312 PZ |
4440 | #define SDVO_PHASE_SELECT_MASK (15 << 19) |
4441 | #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) | |
4442 | #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) | |
4443 | #define SDVOC_GANG_MODE (1 << 16) /* Port C only */ | |
4444 | #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */ | |
4445 | #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */ | |
4446 | #define SDVO_DETECTED (1 << 2) | |
585fb111 | 4447 | /* Bits to be preserved when writing */ |
c20cd312 PZ |
4448 | #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \ |
4449 | SDVO_INTERRUPT_ENABLE) | |
4450 | #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) | |
4451 | ||
4452 | /* Gen 4 SDVO/HDMI bits: */ | |
4f3a8bc7 | 4453 | #define SDVO_COLOR_FORMAT_8bpc (0 << 26) |
18442d08 | 4454 | #define SDVO_COLOR_FORMAT_MASK (7 << 26) |
c20cd312 PZ |
4455 | #define SDVO_ENCODING_SDVO (0 << 10) |
4456 | #define SDVO_ENCODING_HDMI (2 << 10) | |
dc0fa718 PZ |
4457 | #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ |
4458 | #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ | |
4f3a8bc7 | 4459 | #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */ |
c20cd312 PZ |
4460 | #define SDVO_AUDIO_ENABLE (1 << 6) |
4461 | /* VSYNC/HSYNC bits new with 965, default is to be set */ | |
4462 | #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) | |
4463 | #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) | |
4464 | ||
4465 | /* Gen 5 (IBX) SDVO/HDMI bits: */ | |
4f3a8bc7 | 4466 | #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */ |
c20cd312 PZ |
4467 | #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */ |
4468 | ||
4469 | /* Gen 6 (CPT) SDVO/HDMI bits: */ | |
76203467 | 4470 | #define SDVO_PIPE_SEL_SHIFT_CPT 29 |
dc0fa718 | 4471 | #define SDVO_PIPE_SEL_MASK_CPT (3 << 29) |
76203467 | 4472 | #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) |
c20cd312 | 4473 | |
44f37d1f | 4474 | /* CHV SDVO/HDMI bits: */ |
76203467 | 4475 | #define SDVO_PIPE_SEL_SHIFT_CHV 24 |
44f37d1f | 4476 | #define SDVO_PIPE_SEL_MASK_CHV (3 << 24) |
76203467 | 4477 | #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) |
44f37d1f | 4478 | |
585fb111 JB |
4479 | |
4480 | /* DVO port control */ | |
f0f59a00 VS |
4481 | #define _DVOA 0x61120 |
4482 | #define DVOA _MMIO(_DVOA) | |
4483 | #define _DVOB 0x61140 | |
4484 | #define DVOB _MMIO(_DVOB) | |
4485 | #define _DVOC 0x61160 | |
4486 | #define DVOC _MMIO(_DVOC) | |
585fb111 | 4487 | #define DVO_ENABLE (1 << 31) |
b45a2588 VS |
4488 | #define DVO_PIPE_SEL_SHIFT 30 |
4489 | #define DVO_PIPE_SEL_MASK (1 << 30) | |
4490 | #define DVO_PIPE_SEL(pipe) ((pipe) << 30) | |
585fb111 JB |
4491 | #define DVO_PIPE_STALL_UNUSED (0 << 28) |
4492 | #define DVO_PIPE_STALL (1 << 28) | |
4493 | #define DVO_PIPE_STALL_TV (2 << 28) | |
4494 | #define DVO_PIPE_STALL_MASK (3 << 28) | |
4495 | #define DVO_USE_VGA_SYNC (1 << 15) | |
4496 | #define DVO_DATA_ORDER_I740 (0 << 14) | |
4497 | #define DVO_DATA_ORDER_FP (1 << 14) | |
4498 | #define DVO_VSYNC_DISABLE (1 << 11) | |
4499 | #define DVO_HSYNC_DISABLE (1 << 10) | |
4500 | #define DVO_VSYNC_TRISTATE (1 << 9) | |
4501 | #define DVO_HSYNC_TRISTATE (1 << 8) | |
4502 | #define DVO_BORDER_ENABLE (1 << 7) | |
4503 | #define DVO_DATA_ORDER_GBRG (1 << 6) | |
4504 | #define DVO_DATA_ORDER_RGGB (0 << 6) | |
4505 | #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) | |
4506 | #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) | |
4507 | #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) | |
4508 | #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) | |
4509 | #define DVO_BLANK_ACTIVE_HIGH (1 << 2) | |
4510 | #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ | |
4511 | #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ | |
5ee8ee86 | 4512 | #define DVO_PRESERVE_MASK (0x7 << 24) |
f0f59a00 VS |
4513 | #define DVOA_SRCDIM _MMIO(0x61124) |
4514 | #define DVOB_SRCDIM _MMIO(0x61144) | |
4515 | #define DVOC_SRCDIM _MMIO(0x61164) | |
585fb111 JB |
4516 | #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 |
4517 | #define DVO_SRCDIM_VERTICAL_SHIFT 0 | |
4518 | ||
4519 | /* LVDS port control */ | |
f0f59a00 | 4520 | #define LVDS _MMIO(0x61180) |
585fb111 JB |
4521 | /* |
4522 | * Enables the LVDS port. This bit must be set before DPLLs are enabled, as | |
4523 | * the DPLL semantics change when the LVDS is assigned to that pipe. | |
4524 | */ | |
4525 | #define LVDS_PORT_EN (1 << 31) | |
4526 | /* Selects pipe B for LVDS data. Must be set on pre-965. */ | |
a44628b9 VS |
4527 | #define LVDS_PIPE_SEL_SHIFT 30 |
4528 | #define LVDS_PIPE_SEL_MASK (1 << 30) | |
4529 | #define LVDS_PIPE_SEL(pipe) ((pipe) << 30) | |
4530 | #define LVDS_PIPE_SEL_SHIFT_CPT 29 | |
4531 | #define LVDS_PIPE_SEL_MASK_CPT (3 << 29) | |
4532 | #define LVDS_PIPE_SEL_CPT(pipe) ((pipe) << 29) | |
898822ce ZY |
4533 | /* LVDS dithering flag on 965/g4x platform */ |
4534 | #define LVDS_ENABLE_DITHER (1 << 25) | |
aa9b500d BF |
4535 | /* LVDS sync polarity flags. Set to invert (i.e. negative) */ |
4536 | #define LVDS_VSYNC_POLARITY (1 << 21) | |
4537 | #define LVDS_HSYNC_POLARITY (1 << 20) | |
4538 | ||
a3e17eb8 ZY |
4539 | /* Enable border for unscaled (or aspect-scaled) display */ |
4540 | #define LVDS_BORDER_ENABLE (1 << 15) | |
585fb111 JB |
4541 | /* |
4542 | * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per | |
4543 | * pixel. | |
4544 | */ | |
4545 | #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) | |
4546 | #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) | |
4547 | #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) | |
4548 | /* | |
4549 | * Controls the A3 data pair, which contains the additional LSBs for 24 bit | |
4550 | * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be | |
4551 | * on. | |
4552 | */ | |
4553 | #define LVDS_A3_POWER_MASK (3 << 6) | |
4554 | #define LVDS_A3_POWER_DOWN (0 << 6) | |
4555 | #define LVDS_A3_POWER_UP (3 << 6) | |
4556 | /* | |
4557 | * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP | |
4558 | * is set. | |
4559 | */ | |
4560 | #define LVDS_CLKB_POWER_MASK (3 << 4) | |
4561 | #define LVDS_CLKB_POWER_DOWN (0 << 4) | |
4562 | #define LVDS_CLKB_POWER_UP (3 << 4) | |
4563 | /* | |
4564 | * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 | |
4565 | * setting for whether we are in dual-channel mode. The B3 pair will | |
4566 | * additionally only be powered up when LVDS_A3_POWER_UP is set. | |
4567 | */ | |
4568 | #define LVDS_B0B3_POWER_MASK (3 << 2) | |
4569 | #define LVDS_B0B3_POWER_DOWN (0 << 2) | |
4570 | #define LVDS_B0B3_POWER_UP (3 << 2) | |
4571 | ||
3c17fe4b | 4572 | /* Video Data Island Packet control */ |
f0f59a00 | 4573 | #define VIDEO_DIP_DATA _MMIO(0x61178) |
fd0753cf | 4574 | /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC |
adf00b26 PZ |
4575 | * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte |
4576 | * of the infoframe structure specified by CEA-861. */ | |
4577 | #define VIDEO_DIP_DATA_SIZE 32 | |
2b28bb1b | 4578 | #define VIDEO_DIP_VSC_DATA_SIZE 36 |
f0f59a00 | 4579 | #define VIDEO_DIP_CTL _MMIO(0x61170) |
2da8af54 | 4580 | /* Pre HSW: */ |
3c17fe4b | 4581 | #define VIDEO_DIP_ENABLE (1 << 31) |
822cdc52 | 4582 | #define VIDEO_DIP_PORT(port) ((port) << 29) |
3e6e6395 | 4583 | #define VIDEO_DIP_PORT_MASK (3 << 29) |
0dd87d20 | 4584 | #define VIDEO_DIP_ENABLE_GCP (1 << 25) |
3c17fe4b DH |
4585 | #define VIDEO_DIP_ENABLE_AVI (1 << 21) |
4586 | #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) | |
0dd87d20 | 4587 | #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) |
3c17fe4b DH |
4588 | #define VIDEO_DIP_ENABLE_SPD (8 << 21) |
4589 | #define VIDEO_DIP_SELECT_AVI (0 << 19) | |
4590 | #define VIDEO_DIP_SELECT_VENDOR (1 << 19) | |
4591 | #define VIDEO_DIP_SELECT_SPD (3 << 19) | |
45187ace | 4592 | #define VIDEO_DIP_SELECT_MASK (3 << 19) |
3c17fe4b DH |
4593 | #define VIDEO_DIP_FREQ_ONCE (0 << 16) |
4594 | #define VIDEO_DIP_FREQ_VSYNC (1 << 16) | |
4595 | #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) | |
60c5ea2d | 4596 | #define VIDEO_DIP_FREQ_MASK (3 << 16) |
2da8af54 | 4597 | /* HSW and later: */ |
0dd87d20 PZ |
4598 | #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) |
4599 | #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) | |
2da8af54 | 4600 | #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) |
0dd87d20 PZ |
4601 | #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) |
4602 | #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) | |
2da8af54 | 4603 | #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) |
3c17fe4b | 4604 | |
585fb111 | 4605 | /* Panel power sequencing */ |
44cb734c ID |
4606 | #define PPS_BASE 0x61200 |
4607 | #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE) | |
4608 | #define PCH_PPS_BASE 0xC7200 | |
4609 | ||
4610 | #define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \ | |
4611 | PPS_BASE + (reg) + \ | |
4612 | (pps_idx) * 0x100) | |
4613 | ||
4614 | #define _PP_STATUS 0x61200 | |
4615 | #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS) | |
4616 | #define PP_ON (1 << 31) | |
585fb111 JB |
4617 | /* |
4618 | * Indicates that all dependencies of the panel are on: | |
4619 | * | |
4620 | * - PLL enabled | |
4621 | * - pipe enabled | |
4622 | * - LVDS/DVOB/DVOC on | |
4623 | */ | |
44cb734c ID |
4624 | #define PP_READY (1 << 30) |
4625 | #define PP_SEQUENCE_NONE (0 << 28) | |
4626 | #define PP_SEQUENCE_POWER_UP (1 << 28) | |
4627 | #define PP_SEQUENCE_POWER_DOWN (2 << 28) | |
4628 | #define PP_SEQUENCE_MASK (3 << 28) | |
4629 | #define PP_SEQUENCE_SHIFT 28 | |
4630 | #define PP_CYCLE_DELAY_ACTIVE (1 << 27) | |
4631 | #define PP_SEQUENCE_STATE_MASK 0x0000000f | |
99ea7127 KP |
4632 | #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0) |
4633 | #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0) | |
4634 | #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0) | |
4635 | #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0) | |
4636 | #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0) | |
4637 | #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0) | |
4638 | #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0) | |
4639 | #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0) | |
4640 | #define PP_SEQUENCE_STATE_RESET (0xf << 0) | |
44cb734c ID |
4641 | |
4642 | #define _PP_CONTROL 0x61204 | |
4643 | #define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL) | |
4644 | #define PANEL_UNLOCK_REGS (0xabcd << 16) | |
4645 | #define PANEL_UNLOCK_MASK (0xffff << 16) | |
4646 | #define BXT_POWER_CYCLE_DELAY_MASK 0x1f0 | |
4647 | #define BXT_POWER_CYCLE_DELAY_SHIFT 4 | |
4648 | #define EDP_FORCE_VDD (1 << 3) | |
4649 | #define EDP_BLC_ENABLE (1 << 2) | |
4650 | #define PANEL_POWER_RESET (1 << 1) | |
4651 | #define PANEL_POWER_OFF (0 << 0) | |
4652 | #define PANEL_POWER_ON (1 << 0) | |
44cb734c ID |
4653 | |
4654 | #define _PP_ON_DELAYS 0x61208 | |
4655 | #define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS) | |
ed6143b8 | 4656 | #define PANEL_PORT_SELECT_SHIFT 30 |
44cb734c ID |
4657 | #define PANEL_PORT_SELECT_MASK (3 << 30) |
4658 | #define PANEL_PORT_SELECT_LVDS (0 << 30) | |
4659 | #define PANEL_PORT_SELECT_DPA (1 << 30) | |
4660 | #define PANEL_PORT_SELECT_DPC (2 << 30) | |
4661 | #define PANEL_PORT_SELECT_DPD (3 << 30) | |
4662 | #define PANEL_PORT_SELECT_VLV(port) ((port) << 30) | |
4663 | #define PANEL_POWER_UP_DELAY_MASK 0x1fff0000 | |
4664 | #define PANEL_POWER_UP_DELAY_SHIFT 16 | |
4665 | #define PANEL_LIGHT_ON_DELAY_MASK 0x1fff | |
4666 | #define PANEL_LIGHT_ON_DELAY_SHIFT 0 | |
4667 | ||
4668 | #define _PP_OFF_DELAYS 0x6120C | |
4669 | #define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS) | |
4670 | #define PANEL_POWER_DOWN_DELAY_MASK 0x1fff0000 | |
4671 | #define PANEL_POWER_DOWN_DELAY_SHIFT 16 | |
4672 | #define PANEL_LIGHT_OFF_DELAY_MASK 0x1fff | |
4673 | #define PANEL_LIGHT_OFF_DELAY_SHIFT 0 | |
4674 | ||
4675 | #define _PP_DIVISOR 0x61210 | |
4676 | #define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR) | |
4677 | #define PP_REFERENCE_DIVIDER_MASK 0xffffff00 | |
4678 | #define PP_REFERENCE_DIVIDER_SHIFT 8 | |
4679 | #define PANEL_POWER_CYCLE_DELAY_MASK 0x1f | |
4680 | #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 | |
585fb111 JB |
4681 | |
4682 | /* Panel fitting */ | |
f0f59a00 | 4683 | #define PFIT_CONTROL _MMIO(dev_priv->info.display_mmio_offset + 0x61230) |
585fb111 JB |
4684 | #define PFIT_ENABLE (1 << 31) |
4685 | #define PFIT_PIPE_MASK (3 << 29) | |
4686 | #define PFIT_PIPE_SHIFT 29 | |
4687 | #define VERT_INTERP_DISABLE (0 << 10) | |
4688 | #define VERT_INTERP_BILINEAR (1 << 10) | |
4689 | #define VERT_INTERP_MASK (3 << 10) | |
4690 | #define VERT_AUTO_SCALE (1 << 9) | |
4691 | #define HORIZ_INTERP_DISABLE (0 << 6) | |
4692 | #define HORIZ_INTERP_BILINEAR (1 << 6) | |
4693 | #define HORIZ_INTERP_MASK (3 << 6) | |
4694 | #define HORIZ_AUTO_SCALE (1 << 5) | |
4695 | #define PANEL_8TO6_DITHER_ENABLE (1 << 3) | |
3fbe18d6 ZY |
4696 | #define PFIT_FILTER_FUZZY (0 << 24) |
4697 | #define PFIT_SCALING_AUTO (0 << 26) | |
4698 | #define PFIT_SCALING_PROGRAMMED (1 << 26) | |
4699 | #define PFIT_SCALING_PILLAR (2 << 26) | |
4700 | #define PFIT_SCALING_LETTER (3 << 26) | |
f0f59a00 | 4701 | #define PFIT_PGM_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61234) |
3fbe18d6 ZY |
4702 | /* Pre-965 */ |
4703 | #define PFIT_VERT_SCALE_SHIFT 20 | |
4704 | #define PFIT_VERT_SCALE_MASK 0xfff00000 | |
4705 | #define PFIT_HORIZ_SCALE_SHIFT 4 | |
4706 | #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 | |
4707 | /* 965+ */ | |
4708 | #define PFIT_VERT_SCALE_SHIFT_965 16 | |
4709 | #define PFIT_VERT_SCALE_MASK_965 0x1fff0000 | |
4710 | #define PFIT_HORIZ_SCALE_SHIFT_965 0 | |
4711 | #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff | |
4712 | ||
f0f59a00 | 4713 | #define PFIT_AUTO_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61238) |
585fb111 | 4714 | |
5c969aa7 DL |
4715 | #define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250) |
4716 | #define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350) | |
f0f59a00 VS |
4717 | #define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \ |
4718 | _VLV_BLC_PWM_CTL2_B) | |
07bf139b | 4719 | |
5c969aa7 DL |
4720 | #define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254) |
4721 | #define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354) | |
f0f59a00 VS |
4722 | #define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \ |
4723 | _VLV_BLC_PWM_CTL_B) | |
07bf139b | 4724 | |
5c969aa7 DL |
4725 | #define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260) |
4726 | #define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360) | |
f0f59a00 VS |
4727 | #define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \ |
4728 | _VLV_BLC_HIST_CTL_B) | |
07bf139b | 4729 | |
585fb111 | 4730 | /* Backlight control */ |
f0f59a00 | 4731 | #define BLC_PWM_CTL2 _MMIO(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */ |
7cf41601 DV |
4732 | #define BLM_PWM_ENABLE (1 << 31) |
4733 | #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ | |
4734 | #define BLM_PIPE_SELECT (1 << 29) | |
4735 | #define BLM_PIPE_SELECT_IVB (3 << 29) | |
4736 | #define BLM_PIPE_A (0 << 29) | |
4737 | #define BLM_PIPE_B (1 << 29) | |
4738 | #define BLM_PIPE_C (2 << 29) /* ivb + */ | |
35ffda48 JN |
4739 | #define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */ |
4740 | #define BLM_TRANSCODER_B BLM_PIPE_B | |
4741 | #define BLM_TRANSCODER_C BLM_PIPE_C | |
4742 | #define BLM_TRANSCODER_EDP (3 << 29) | |
7cf41601 DV |
4743 | #define BLM_PIPE(pipe) ((pipe) << 29) |
4744 | #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */ | |
4745 | #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26) | |
4746 | #define BLM_PHASE_IN_ENABLE (1 << 25) | |
4747 | #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24) | |
4748 | #define BLM_PHASE_IN_TIME_BASE_SHIFT (16) | |
4749 | #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16) | |
4750 | #define BLM_PHASE_IN_COUNT_SHIFT (8) | |
4751 | #define BLM_PHASE_IN_COUNT_MASK (0xff << 8) | |
4752 | #define BLM_PHASE_IN_INCR_SHIFT (0) | |
4753 | #define BLM_PHASE_IN_INCR_MASK (0xff << 0) | |
f0f59a00 | 4754 | #define BLC_PWM_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61254) |
ba3820ad TI |
4755 | /* |
4756 | * This is the most significant 15 bits of the number of backlight cycles in a | |
4757 | * complete cycle of the modulated backlight control. | |
4758 | * | |
4759 | * The actual value is this field multiplied by two. | |
4760 | */ | |
7cf41601 DV |
4761 | #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) |
4762 | #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) | |
4763 | #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */ | |
585fb111 JB |
4764 | /* |
4765 | * This is the number of cycles out of the backlight modulation cycle for which | |
4766 | * the backlight is on. | |
4767 | * | |
4768 | * This field must be no greater than the number of cycles in the complete | |
4769 | * backlight modulation cycle. | |
4770 | */ | |
4771 | #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) | |
4772 | #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) | |
534b5a53 DV |
4773 | #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) |
4774 | #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ | |
585fb111 | 4775 | |
f0f59a00 | 4776 | #define BLC_HIST_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61260) |
2059ac3b | 4777 | #define BLM_HISTOGRAM_ENABLE (1 << 31) |
0eb96d6e | 4778 | |
7cf41601 DV |
4779 | /* New registers for PCH-split platforms. Safe where new bits show up, the |
4780 | * register layout machtes with gen4 BLC_PWM_CTL[12]. */ | |
f0f59a00 VS |
4781 | #define BLC_PWM_CPU_CTL2 _MMIO(0x48250) |
4782 | #define BLC_PWM_CPU_CTL _MMIO(0x48254) | |
7cf41601 | 4783 | |
f0f59a00 | 4784 | #define HSW_BLC_PWM2_CTL _MMIO(0x48350) |
be256dc7 | 4785 | |
7cf41601 DV |
4786 | /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is |
4787 | * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */ | |
f0f59a00 | 4788 | #define BLC_PWM_PCH_CTL1 _MMIO(0xc8250) |
4b4147c3 | 4789 | #define BLM_PCH_PWM_ENABLE (1 << 31) |
7cf41601 DV |
4790 | #define BLM_PCH_OVERRIDE_ENABLE (1 << 30) |
4791 | #define BLM_PCH_POLARITY (1 << 29) | |
f0f59a00 | 4792 | #define BLC_PWM_PCH_CTL2 _MMIO(0xc8254) |
7cf41601 | 4793 | |
f0f59a00 | 4794 | #define UTIL_PIN_CTL _MMIO(0x48400) |
be256dc7 PZ |
4795 | #define UTIL_PIN_ENABLE (1 << 31) |
4796 | ||
022e4e52 SK |
4797 | #define UTIL_PIN_PIPE(x) ((x) << 29) |
4798 | #define UTIL_PIN_PIPE_MASK (3 << 29) | |
4799 | #define UTIL_PIN_MODE_PWM (1 << 24) | |
4800 | #define UTIL_PIN_MODE_MASK (0xf << 24) | |
4801 | #define UTIL_PIN_POLARITY (1 << 22) | |
4802 | ||
0fb890c0 | 4803 | /* BXT backlight register definition. */ |
022e4e52 | 4804 | #define _BXT_BLC_PWM_CTL1 0xC8250 |
0fb890c0 VK |
4805 | #define BXT_BLC_PWM_ENABLE (1 << 31) |
4806 | #define BXT_BLC_PWM_POLARITY (1 << 29) | |
022e4e52 SK |
4807 | #define _BXT_BLC_PWM_FREQ1 0xC8254 |
4808 | #define _BXT_BLC_PWM_DUTY1 0xC8258 | |
4809 | ||
4810 | #define _BXT_BLC_PWM_CTL2 0xC8350 | |
4811 | #define _BXT_BLC_PWM_FREQ2 0xC8354 | |
4812 | #define _BXT_BLC_PWM_DUTY2 0xC8358 | |
4813 | ||
f0f59a00 | 4814 | #define BXT_BLC_PWM_CTL(controller) _MMIO_PIPE(controller, \ |
022e4e52 | 4815 | _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2) |
f0f59a00 | 4816 | #define BXT_BLC_PWM_FREQ(controller) _MMIO_PIPE(controller, \ |
022e4e52 | 4817 | _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2) |
f0f59a00 | 4818 | #define BXT_BLC_PWM_DUTY(controller) _MMIO_PIPE(controller, \ |
022e4e52 | 4819 | _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2) |
0fb890c0 | 4820 | |
f0f59a00 | 4821 | #define PCH_GTC_CTL _MMIO(0xe7000) |
be256dc7 PZ |
4822 | #define PCH_GTC_ENABLE (1 << 31) |
4823 | ||
585fb111 | 4824 | /* TV port control */ |
f0f59a00 | 4825 | #define TV_CTL _MMIO(0x68000) |
646b4269 | 4826 | /* Enables the TV encoder */ |
585fb111 | 4827 | # define TV_ENC_ENABLE (1 << 31) |
646b4269 | 4828 | /* Sources the TV encoder input from pipe B instead of A. */ |
4add0f6b VS |
4829 | # define TV_ENC_PIPE_SEL_SHIFT 30 |
4830 | # define TV_ENC_PIPE_SEL_MASK (1 << 30) | |
4831 | # define TV_ENC_PIPE_SEL(pipe) ((pipe) << 30) | |
646b4269 | 4832 | /* Outputs composite video (DAC A only) */ |
585fb111 | 4833 | # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) |
646b4269 | 4834 | /* Outputs SVideo video (DAC B/C) */ |
585fb111 | 4835 | # define TV_ENC_OUTPUT_SVIDEO (1 << 28) |
646b4269 | 4836 | /* Outputs Component video (DAC A/B/C) */ |
585fb111 | 4837 | # define TV_ENC_OUTPUT_COMPONENT (2 << 28) |
646b4269 | 4838 | /* Outputs Composite and SVideo (DAC A/B/C) */ |
585fb111 JB |
4839 | # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) |
4840 | # define TV_TRILEVEL_SYNC (1 << 21) | |
646b4269 | 4841 | /* Enables slow sync generation (945GM only) */ |
585fb111 | 4842 | # define TV_SLOW_SYNC (1 << 20) |
646b4269 | 4843 | /* Selects 4x oversampling for 480i and 576p */ |
585fb111 | 4844 | # define TV_OVERSAMPLE_4X (0 << 18) |
646b4269 | 4845 | /* Selects 2x oversampling for 720p and 1080i */ |
585fb111 | 4846 | # define TV_OVERSAMPLE_2X (1 << 18) |
646b4269 | 4847 | /* Selects no oversampling for 1080p */ |
585fb111 | 4848 | # define TV_OVERSAMPLE_NONE (2 << 18) |
646b4269 | 4849 | /* Selects 8x oversampling */ |
585fb111 | 4850 | # define TV_OVERSAMPLE_8X (3 << 18) |
646b4269 | 4851 | /* Selects progressive mode rather than interlaced */ |
585fb111 | 4852 | # define TV_PROGRESSIVE (1 << 17) |
646b4269 | 4853 | /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */ |
585fb111 | 4854 | # define TV_PAL_BURST (1 << 16) |
646b4269 | 4855 | /* Field for setting delay of Y compared to C */ |
585fb111 | 4856 | # define TV_YC_SKEW_MASK (7 << 12) |
646b4269 | 4857 | /* Enables a fix for 480p/576p standard definition modes on the 915GM only */ |
585fb111 | 4858 | # define TV_ENC_SDP_FIX (1 << 11) |
646b4269 | 4859 | /* |
585fb111 JB |
4860 | * Enables a fix for the 915GM only. |
4861 | * | |
4862 | * Not sure what it does. | |
4863 | */ | |
4864 | # define TV_ENC_C0_FIX (1 << 10) | |
646b4269 | 4865 | /* Bits that must be preserved by software */ |
d2d9f232 | 4866 | # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) |
585fb111 | 4867 | # define TV_FUSE_STATE_MASK (3 << 4) |
646b4269 | 4868 | /* Read-only state that reports all features enabled */ |
585fb111 | 4869 | # define TV_FUSE_STATE_ENABLED (0 << 4) |
646b4269 | 4870 | /* Read-only state that reports that Macrovision is disabled in hardware*/ |
585fb111 | 4871 | # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) |
646b4269 | 4872 | /* Read-only state that reports that TV-out is disabled in hardware. */ |
585fb111 | 4873 | # define TV_FUSE_STATE_DISABLED (2 << 4) |
646b4269 | 4874 | /* Normal operation */ |
585fb111 | 4875 | # define TV_TEST_MODE_NORMAL (0 << 0) |
646b4269 | 4876 | /* Encoder test pattern 1 - combo pattern */ |
585fb111 | 4877 | # define TV_TEST_MODE_PATTERN_1 (1 << 0) |
646b4269 | 4878 | /* Encoder test pattern 2 - full screen vertical 75% color bars */ |
585fb111 | 4879 | # define TV_TEST_MODE_PATTERN_2 (2 << 0) |
646b4269 | 4880 | /* Encoder test pattern 3 - full screen horizontal 75% color bars */ |
585fb111 | 4881 | # define TV_TEST_MODE_PATTERN_3 (3 << 0) |
646b4269 | 4882 | /* Encoder test pattern 4 - random noise */ |
585fb111 | 4883 | # define TV_TEST_MODE_PATTERN_4 (4 << 0) |
646b4269 | 4884 | /* Encoder test pattern 5 - linear color ramps */ |
585fb111 | 4885 | # define TV_TEST_MODE_PATTERN_5 (5 << 0) |
646b4269 | 4886 | /* |
585fb111 JB |
4887 | * This test mode forces the DACs to 50% of full output. |
4888 | * | |
4889 | * This is used for load detection in combination with TVDAC_SENSE_MASK | |
4890 | */ | |
4891 | # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) | |
4892 | # define TV_TEST_MODE_MASK (7 << 0) | |
4893 | ||
f0f59a00 | 4894 | #define TV_DAC _MMIO(0x68004) |
b8ed2a4f | 4895 | # define TV_DAC_SAVE 0x00ffff00 |
646b4269 | 4896 | /* |
585fb111 JB |
4897 | * Reports that DAC state change logic has reported change (RO). |
4898 | * | |
4899 | * This gets cleared when TV_DAC_STATE_EN is cleared | |
4900 | */ | |
4901 | # define TVDAC_STATE_CHG (1 << 31) | |
4902 | # define TVDAC_SENSE_MASK (7 << 28) | |
646b4269 | 4903 | /* Reports that DAC A voltage is above the detect threshold */ |
585fb111 | 4904 | # define TVDAC_A_SENSE (1 << 30) |
646b4269 | 4905 | /* Reports that DAC B voltage is above the detect threshold */ |
585fb111 | 4906 | # define TVDAC_B_SENSE (1 << 29) |
646b4269 | 4907 | /* Reports that DAC C voltage is above the detect threshold */ |
585fb111 | 4908 | # define TVDAC_C_SENSE (1 << 28) |
646b4269 | 4909 | /* |
585fb111 JB |
4910 | * Enables DAC state detection logic, for load-based TV detection. |
4911 | * | |
4912 | * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set | |
4913 | * to off, for load detection to work. | |
4914 | */ | |
4915 | # define TVDAC_STATE_CHG_EN (1 << 27) | |
646b4269 | 4916 | /* Sets the DAC A sense value to high */ |
585fb111 | 4917 | # define TVDAC_A_SENSE_CTL (1 << 26) |
646b4269 | 4918 | /* Sets the DAC B sense value to high */ |
585fb111 | 4919 | # define TVDAC_B_SENSE_CTL (1 << 25) |
646b4269 | 4920 | /* Sets the DAC C sense value to high */ |
585fb111 | 4921 | # define TVDAC_C_SENSE_CTL (1 << 24) |
646b4269 | 4922 | /* Overrides the ENC_ENABLE and DAC voltage levels */ |
585fb111 | 4923 | # define DAC_CTL_OVERRIDE (1 << 7) |
646b4269 | 4924 | /* Sets the slew rate. Must be preserved in software */ |
585fb111 JB |
4925 | # define ENC_TVDAC_SLEW_FAST (1 << 6) |
4926 | # define DAC_A_1_3_V (0 << 4) | |
4927 | # define DAC_A_1_1_V (1 << 4) | |
4928 | # define DAC_A_0_7_V (2 << 4) | |
cb66c692 | 4929 | # define DAC_A_MASK (3 << 4) |
585fb111 JB |
4930 | # define DAC_B_1_3_V (0 << 2) |
4931 | # define DAC_B_1_1_V (1 << 2) | |
4932 | # define DAC_B_0_7_V (2 << 2) | |
cb66c692 | 4933 | # define DAC_B_MASK (3 << 2) |
585fb111 JB |
4934 | # define DAC_C_1_3_V (0 << 0) |
4935 | # define DAC_C_1_1_V (1 << 0) | |
4936 | # define DAC_C_0_7_V (2 << 0) | |
cb66c692 | 4937 | # define DAC_C_MASK (3 << 0) |
585fb111 | 4938 | |
646b4269 | 4939 | /* |
585fb111 JB |
4940 | * CSC coefficients are stored in a floating point format with 9 bits of |
4941 | * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, | |
4942 | * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with | |
4943 | * -1 (0x3) being the only legal negative value. | |
4944 | */ | |
f0f59a00 | 4945 | #define TV_CSC_Y _MMIO(0x68010) |
585fb111 JB |
4946 | # define TV_RY_MASK 0x07ff0000 |
4947 | # define TV_RY_SHIFT 16 | |
4948 | # define TV_GY_MASK 0x00000fff | |
4949 | # define TV_GY_SHIFT 0 | |
4950 | ||
f0f59a00 | 4951 | #define TV_CSC_Y2 _MMIO(0x68014) |
585fb111 JB |
4952 | # define TV_BY_MASK 0x07ff0000 |
4953 | # define TV_BY_SHIFT 16 | |
646b4269 | 4954 | /* |
585fb111 JB |
4955 | * Y attenuation for component video. |
4956 | * | |
4957 | * Stored in 1.9 fixed point. | |
4958 | */ | |
4959 | # define TV_AY_MASK 0x000003ff | |
4960 | # define TV_AY_SHIFT 0 | |
4961 | ||
f0f59a00 | 4962 | #define TV_CSC_U _MMIO(0x68018) |
585fb111 JB |
4963 | # define TV_RU_MASK 0x07ff0000 |
4964 | # define TV_RU_SHIFT 16 | |
4965 | # define TV_GU_MASK 0x000007ff | |
4966 | # define TV_GU_SHIFT 0 | |
4967 | ||
f0f59a00 | 4968 | #define TV_CSC_U2 _MMIO(0x6801c) |
585fb111 JB |
4969 | # define TV_BU_MASK 0x07ff0000 |
4970 | # define TV_BU_SHIFT 16 | |
646b4269 | 4971 | /* |
585fb111 JB |
4972 | * U attenuation for component video. |
4973 | * | |
4974 | * Stored in 1.9 fixed point. | |
4975 | */ | |
4976 | # define TV_AU_MASK 0x000003ff | |
4977 | # define TV_AU_SHIFT 0 | |
4978 | ||
f0f59a00 | 4979 | #define TV_CSC_V _MMIO(0x68020) |
585fb111 JB |
4980 | # define TV_RV_MASK 0x0fff0000 |
4981 | # define TV_RV_SHIFT 16 | |
4982 | # define TV_GV_MASK 0x000007ff | |
4983 | # define TV_GV_SHIFT 0 | |
4984 | ||
f0f59a00 | 4985 | #define TV_CSC_V2 _MMIO(0x68024) |
585fb111 JB |
4986 | # define TV_BV_MASK 0x07ff0000 |
4987 | # define TV_BV_SHIFT 16 | |
646b4269 | 4988 | /* |
585fb111 JB |
4989 | * V attenuation for component video. |
4990 | * | |
4991 | * Stored in 1.9 fixed point. | |
4992 | */ | |
4993 | # define TV_AV_MASK 0x000007ff | |
4994 | # define TV_AV_SHIFT 0 | |
4995 | ||
f0f59a00 | 4996 | #define TV_CLR_KNOBS _MMIO(0x68028) |
646b4269 | 4997 | /* 2s-complement brightness adjustment */ |
585fb111 JB |
4998 | # define TV_BRIGHTNESS_MASK 0xff000000 |
4999 | # define TV_BRIGHTNESS_SHIFT 24 | |
646b4269 | 5000 | /* Contrast adjustment, as a 2.6 unsigned floating point number */ |
585fb111 JB |
5001 | # define TV_CONTRAST_MASK 0x00ff0000 |
5002 | # define TV_CONTRAST_SHIFT 16 | |
646b4269 | 5003 | /* Saturation adjustment, as a 2.6 unsigned floating point number */ |
585fb111 JB |
5004 | # define TV_SATURATION_MASK 0x0000ff00 |
5005 | # define TV_SATURATION_SHIFT 8 | |
646b4269 | 5006 | /* Hue adjustment, as an integer phase angle in degrees */ |
585fb111 JB |
5007 | # define TV_HUE_MASK 0x000000ff |
5008 | # define TV_HUE_SHIFT 0 | |
5009 | ||
f0f59a00 | 5010 | #define TV_CLR_LEVEL _MMIO(0x6802c) |
646b4269 | 5011 | /* Controls the DAC level for black */ |
585fb111 JB |
5012 | # define TV_BLACK_LEVEL_MASK 0x01ff0000 |
5013 | # define TV_BLACK_LEVEL_SHIFT 16 | |
646b4269 | 5014 | /* Controls the DAC level for blanking */ |
585fb111 JB |
5015 | # define TV_BLANK_LEVEL_MASK 0x000001ff |
5016 | # define TV_BLANK_LEVEL_SHIFT 0 | |
5017 | ||
f0f59a00 | 5018 | #define TV_H_CTL_1 _MMIO(0x68030) |
646b4269 | 5019 | /* Number of pixels in the hsync. */ |
585fb111 JB |
5020 | # define TV_HSYNC_END_MASK 0x1fff0000 |
5021 | # define TV_HSYNC_END_SHIFT 16 | |
646b4269 | 5022 | /* Total number of pixels minus one in the line (display and blanking). */ |
585fb111 JB |
5023 | # define TV_HTOTAL_MASK 0x00001fff |
5024 | # define TV_HTOTAL_SHIFT 0 | |
5025 | ||
f0f59a00 | 5026 | #define TV_H_CTL_2 _MMIO(0x68034) |
646b4269 | 5027 | /* Enables the colorburst (needed for non-component color) */ |
585fb111 | 5028 | # define TV_BURST_ENA (1 << 31) |
646b4269 | 5029 | /* Offset of the colorburst from the start of hsync, in pixels minus one. */ |
585fb111 JB |
5030 | # define TV_HBURST_START_SHIFT 16 |
5031 | # define TV_HBURST_START_MASK 0x1fff0000 | |
646b4269 | 5032 | /* Length of the colorburst */ |
585fb111 JB |
5033 | # define TV_HBURST_LEN_SHIFT 0 |
5034 | # define TV_HBURST_LEN_MASK 0x0001fff | |
5035 | ||
f0f59a00 | 5036 | #define TV_H_CTL_3 _MMIO(0x68038) |
646b4269 | 5037 | /* End of hblank, measured in pixels minus one from start of hsync */ |
585fb111 JB |
5038 | # define TV_HBLANK_END_SHIFT 16 |
5039 | # define TV_HBLANK_END_MASK 0x1fff0000 | |
646b4269 | 5040 | /* Start of hblank, measured in pixels minus one from start of hsync */ |
585fb111 JB |
5041 | # define TV_HBLANK_START_SHIFT 0 |
5042 | # define TV_HBLANK_START_MASK 0x0001fff | |
5043 | ||
f0f59a00 | 5044 | #define TV_V_CTL_1 _MMIO(0x6803c) |
646b4269 | 5045 | /* XXX */ |
585fb111 JB |
5046 | # define TV_NBR_END_SHIFT 16 |
5047 | # define TV_NBR_END_MASK 0x07ff0000 | |
646b4269 | 5048 | /* XXX */ |
585fb111 JB |
5049 | # define TV_VI_END_F1_SHIFT 8 |
5050 | # define TV_VI_END_F1_MASK 0x00003f00 | |
646b4269 | 5051 | /* XXX */ |
585fb111 JB |
5052 | # define TV_VI_END_F2_SHIFT 0 |
5053 | # define TV_VI_END_F2_MASK 0x0000003f | |
5054 | ||
f0f59a00 | 5055 | #define TV_V_CTL_2 _MMIO(0x68040) |
646b4269 | 5056 | /* Length of vsync, in half lines */ |
585fb111 JB |
5057 | # define TV_VSYNC_LEN_MASK 0x07ff0000 |
5058 | # define TV_VSYNC_LEN_SHIFT 16 | |
646b4269 | 5059 | /* Offset of the start of vsync in field 1, measured in one less than the |
585fb111 JB |
5060 | * number of half lines. |
5061 | */ | |
5062 | # define TV_VSYNC_START_F1_MASK 0x00007f00 | |
5063 | # define TV_VSYNC_START_F1_SHIFT 8 | |
646b4269 | 5064 | /* |
585fb111 JB |
5065 | * Offset of the start of vsync in field 2, measured in one less than the |
5066 | * number of half lines. | |
5067 | */ | |
5068 | # define TV_VSYNC_START_F2_MASK 0x0000007f | |
5069 | # define TV_VSYNC_START_F2_SHIFT 0 | |
5070 | ||
f0f59a00 | 5071 | #define TV_V_CTL_3 _MMIO(0x68044) |
646b4269 | 5072 | /* Enables generation of the equalization signal */ |
585fb111 | 5073 | # define TV_EQUAL_ENA (1 << 31) |
646b4269 | 5074 | /* Length of vsync, in half lines */ |
585fb111 JB |
5075 | # define TV_VEQ_LEN_MASK 0x007f0000 |
5076 | # define TV_VEQ_LEN_SHIFT 16 | |
646b4269 | 5077 | /* Offset of the start of equalization in field 1, measured in one less than |
585fb111 JB |
5078 | * the number of half lines. |
5079 | */ | |
5080 | # define TV_VEQ_START_F1_MASK 0x0007f00 | |
5081 | # define TV_VEQ_START_F1_SHIFT 8 | |
646b4269 | 5082 | /* |
585fb111 JB |
5083 | * Offset of the start of equalization in field 2, measured in one less than |
5084 | * the number of half lines. | |
5085 | */ | |
5086 | # define TV_VEQ_START_F2_MASK 0x000007f | |
5087 | # define TV_VEQ_START_F2_SHIFT 0 | |
5088 | ||
f0f59a00 | 5089 | #define TV_V_CTL_4 _MMIO(0x68048) |
646b4269 | 5090 | /* |
585fb111 JB |
5091 | * Offset to start of vertical colorburst, measured in one less than the |
5092 | * number of lines from vertical start. | |
5093 | */ | |
5094 | # define TV_VBURST_START_F1_MASK 0x003f0000 | |
5095 | # define TV_VBURST_START_F1_SHIFT 16 | |
646b4269 | 5096 | /* |
585fb111 JB |
5097 | * Offset to the end of vertical colorburst, measured in one less than the |
5098 | * number of lines from the start of NBR. | |
5099 | */ | |
5100 | # define TV_VBURST_END_F1_MASK 0x000000ff | |
5101 | # define TV_VBURST_END_F1_SHIFT 0 | |
5102 | ||
f0f59a00 | 5103 | #define TV_V_CTL_5 _MMIO(0x6804c) |
646b4269 | 5104 | /* |
585fb111 JB |
5105 | * Offset to start of vertical colorburst, measured in one less than the |
5106 | * number of lines from vertical start. | |
5107 | */ | |
5108 | # define TV_VBURST_START_F2_MASK 0x003f0000 | |
5109 | # define TV_VBURST_START_F2_SHIFT 16 | |
646b4269 | 5110 | /* |
585fb111 JB |
5111 | * Offset to the end of vertical colorburst, measured in one less than the |
5112 | * number of lines from the start of NBR. | |
5113 | */ | |
5114 | # define TV_VBURST_END_F2_MASK 0x000000ff | |
5115 | # define TV_VBURST_END_F2_SHIFT 0 | |
5116 | ||
f0f59a00 | 5117 | #define TV_V_CTL_6 _MMIO(0x68050) |
646b4269 | 5118 | /* |
585fb111 JB |
5119 | * Offset to start of vertical colorburst, measured in one less than the |
5120 | * number of lines from vertical start. | |
5121 | */ | |
5122 | # define TV_VBURST_START_F3_MASK 0x003f0000 | |
5123 | # define TV_VBURST_START_F3_SHIFT 16 | |
646b4269 | 5124 | /* |
585fb111 JB |
5125 | * Offset to the end of vertical colorburst, measured in one less than the |
5126 | * number of lines from the start of NBR. | |
5127 | */ | |
5128 | # define TV_VBURST_END_F3_MASK 0x000000ff | |
5129 | # define TV_VBURST_END_F3_SHIFT 0 | |
5130 | ||
f0f59a00 | 5131 | #define TV_V_CTL_7 _MMIO(0x68054) |
646b4269 | 5132 | /* |
585fb111 JB |
5133 | * Offset to start of vertical colorburst, measured in one less than the |
5134 | * number of lines from vertical start. | |
5135 | */ | |
5136 | # define TV_VBURST_START_F4_MASK 0x003f0000 | |
5137 | # define TV_VBURST_START_F4_SHIFT 16 | |
646b4269 | 5138 | /* |
585fb111 JB |
5139 | * Offset to the end of vertical colorburst, measured in one less than the |
5140 | * number of lines from the start of NBR. | |
5141 | */ | |
5142 | # define TV_VBURST_END_F4_MASK 0x000000ff | |
5143 | # define TV_VBURST_END_F4_SHIFT 0 | |
5144 | ||
f0f59a00 | 5145 | #define TV_SC_CTL_1 _MMIO(0x68060) |
646b4269 | 5146 | /* Turns on the first subcarrier phase generation DDA */ |
585fb111 | 5147 | # define TV_SC_DDA1_EN (1 << 31) |
646b4269 | 5148 | /* Turns on the first subcarrier phase generation DDA */ |
585fb111 | 5149 | # define TV_SC_DDA2_EN (1 << 30) |
646b4269 | 5150 | /* Turns on the first subcarrier phase generation DDA */ |
585fb111 | 5151 | # define TV_SC_DDA3_EN (1 << 29) |
646b4269 | 5152 | /* Sets the subcarrier DDA to reset frequency every other field */ |
585fb111 | 5153 | # define TV_SC_RESET_EVERY_2 (0 << 24) |
646b4269 | 5154 | /* Sets the subcarrier DDA to reset frequency every fourth field */ |
585fb111 | 5155 | # define TV_SC_RESET_EVERY_4 (1 << 24) |
646b4269 | 5156 | /* Sets the subcarrier DDA to reset frequency every eighth field */ |
585fb111 | 5157 | # define TV_SC_RESET_EVERY_8 (2 << 24) |
646b4269 | 5158 | /* Sets the subcarrier DDA to never reset the frequency */ |
585fb111 | 5159 | # define TV_SC_RESET_NEVER (3 << 24) |
646b4269 | 5160 | /* Sets the peak amplitude of the colorburst.*/ |
585fb111 JB |
5161 | # define TV_BURST_LEVEL_MASK 0x00ff0000 |
5162 | # define TV_BURST_LEVEL_SHIFT 16 | |
646b4269 | 5163 | /* Sets the increment of the first subcarrier phase generation DDA */ |
585fb111 JB |
5164 | # define TV_SCDDA1_INC_MASK 0x00000fff |
5165 | # define TV_SCDDA1_INC_SHIFT 0 | |
5166 | ||
f0f59a00 | 5167 | #define TV_SC_CTL_2 _MMIO(0x68064) |
646b4269 | 5168 | /* Sets the rollover for the second subcarrier phase generation DDA */ |
585fb111 JB |
5169 | # define TV_SCDDA2_SIZE_MASK 0x7fff0000 |
5170 | # define TV_SCDDA2_SIZE_SHIFT 16 | |
646b4269 | 5171 | /* Sets the increent of the second subcarrier phase generation DDA */ |
585fb111 JB |
5172 | # define TV_SCDDA2_INC_MASK 0x00007fff |
5173 | # define TV_SCDDA2_INC_SHIFT 0 | |
5174 | ||
f0f59a00 | 5175 | #define TV_SC_CTL_3 _MMIO(0x68068) |
646b4269 | 5176 | /* Sets the rollover for the third subcarrier phase generation DDA */ |
585fb111 JB |
5177 | # define TV_SCDDA3_SIZE_MASK 0x7fff0000 |
5178 | # define TV_SCDDA3_SIZE_SHIFT 16 | |
646b4269 | 5179 | /* Sets the increent of the third subcarrier phase generation DDA */ |
585fb111 JB |
5180 | # define TV_SCDDA3_INC_MASK 0x00007fff |
5181 | # define TV_SCDDA3_INC_SHIFT 0 | |
5182 | ||
f0f59a00 | 5183 | #define TV_WIN_POS _MMIO(0x68070) |
646b4269 | 5184 | /* X coordinate of the display from the start of horizontal active */ |
585fb111 JB |
5185 | # define TV_XPOS_MASK 0x1fff0000 |
5186 | # define TV_XPOS_SHIFT 16 | |
646b4269 | 5187 | /* Y coordinate of the display from the start of vertical active (NBR) */ |
585fb111 JB |
5188 | # define TV_YPOS_MASK 0x00000fff |
5189 | # define TV_YPOS_SHIFT 0 | |
5190 | ||
f0f59a00 | 5191 | #define TV_WIN_SIZE _MMIO(0x68074) |
646b4269 | 5192 | /* Horizontal size of the display window, measured in pixels*/ |
585fb111 JB |
5193 | # define TV_XSIZE_MASK 0x1fff0000 |
5194 | # define TV_XSIZE_SHIFT 16 | |
646b4269 | 5195 | /* |
585fb111 JB |
5196 | * Vertical size of the display window, measured in pixels. |
5197 | * | |
5198 | * Must be even for interlaced modes. | |
5199 | */ | |
5200 | # define TV_YSIZE_MASK 0x00000fff | |
5201 | # define TV_YSIZE_SHIFT 0 | |
5202 | ||
f0f59a00 | 5203 | #define TV_FILTER_CTL_1 _MMIO(0x68080) |
646b4269 | 5204 | /* |
585fb111 JB |
5205 | * Enables automatic scaling calculation. |
5206 | * | |
5207 | * If set, the rest of the registers are ignored, and the calculated values can | |
5208 | * be read back from the register. | |
5209 | */ | |
5210 | # define TV_AUTO_SCALE (1 << 31) | |
646b4269 | 5211 | /* |
585fb111 JB |
5212 | * Disables the vertical filter. |
5213 | * | |
5214 | * This is required on modes more than 1024 pixels wide */ | |
5215 | # define TV_V_FILTER_BYPASS (1 << 29) | |
646b4269 | 5216 | /* Enables adaptive vertical filtering */ |
585fb111 JB |
5217 | # define TV_VADAPT (1 << 28) |
5218 | # define TV_VADAPT_MODE_MASK (3 << 26) | |
646b4269 | 5219 | /* Selects the least adaptive vertical filtering mode */ |
585fb111 | 5220 | # define TV_VADAPT_MODE_LEAST (0 << 26) |
646b4269 | 5221 | /* Selects the moderately adaptive vertical filtering mode */ |
585fb111 | 5222 | # define TV_VADAPT_MODE_MODERATE (1 << 26) |
646b4269 | 5223 | /* Selects the most adaptive vertical filtering mode */ |
585fb111 | 5224 | # define TV_VADAPT_MODE_MOST (3 << 26) |
646b4269 | 5225 | /* |
585fb111 JB |
5226 | * Sets the horizontal scaling factor. |
5227 | * | |
5228 | * This should be the fractional part of the horizontal scaling factor divided | |
5229 | * by the oversampling rate. TV_HSCALE should be less than 1, and set to: | |
5230 | * | |
5231 | * (src width - 1) / ((oversample * dest width) - 1) | |
5232 | */ | |
5233 | # define TV_HSCALE_FRAC_MASK 0x00003fff | |
5234 | # define TV_HSCALE_FRAC_SHIFT 0 | |
5235 | ||
f0f59a00 | 5236 | #define TV_FILTER_CTL_2 _MMIO(0x68084) |
646b4269 | 5237 | /* |
585fb111 JB |
5238 | * Sets the integer part of the 3.15 fixed-point vertical scaling factor. |
5239 | * | |
5240 | * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) | |
5241 | */ | |
5242 | # define TV_VSCALE_INT_MASK 0x00038000 | |
5243 | # define TV_VSCALE_INT_SHIFT 15 | |
646b4269 | 5244 | /* |
585fb111 JB |
5245 | * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. |
5246 | * | |
5247 | * \sa TV_VSCALE_INT_MASK | |
5248 | */ | |
5249 | # define TV_VSCALE_FRAC_MASK 0x00007fff | |
5250 | # define TV_VSCALE_FRAC_SHIFT 0 | |
5251 | ||
f0f59a00 | 5252 | #define TV_FILTER_CTL_3 _MMIO(0x68088) |
646b4269 | 5253 | /* |
585fb111 JB |
5254 | * Sets the integer part of the 3.15 fixed-point vertical scaling factor. |
5255 | * | |
5256 | * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) | |
5257 | * | |
5258 | * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. | |
5259 | */ | |
5260 | # define TV_VSCALE_IP_INT_MASK 0x00038000 | |
5261 | # define TV_VSCALE_IP_INT_SHIFT 15 | |
646b4269 | 5262 | /* |
585fb111 JB |
5263 | * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. |
5264 | * | |
5265 | * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. | |
5266 | * | |
5267 | * \sa TV_VSCALE_IP_INT_MASK | |
5268 | */ | |
5269 | # define TV_VSCALE_IP_FRAC_MASK 0x00007fff | |
5270 | # define TV_VSCALE_IP_FRAC_SHIFT 0 | |
5271 | ||
f0f59a00 | 5272 | #define TV_CC_CONTROL _MMIO(0x68090) |
585fb111 | 5273 | # define TV_CC_ENABLE (1 << 31) |
646b4269 | 5274 | /* |
585fb111 JB |
5275 | * Specifies which field to send the CC data in. |
5276 | * | |
5277 | * CC data is usually sent in field 0. | |
5278 | */ | |
5279 | # define TV_CC_FID_MASK (1 << 27) | |
5280 | # define TV_CC_FID_SHIFT 27 | |
646b4269 | 5281 | /* Sets the horizontal position of the CC data. Usually 135. */ |
585fb111 JB |
5282 | # define TV_CC_HOFF_MASK 0x03ff0000 |
5283 | # define TV_CC_HOFF_SHIFT 16 | |
646b4269 | 5284 | /* Sets the vertical position of the CC data. Usually 21 */ |
585fb111 JB |
5285 | # define TV_CC_LINE_MASK 0x0000003f |
5286 | # define TV_CC_LINE_SHIFT 0 | |
5287 | ||
f0f59a00 | 5288 | #define TV_CC_DATA _MMIO(0x68094) |
585fb111 | 5289 | # define TV_CC_RDY (1 << 31) |
646b4269 | 5290 | /* Second word of CC data to be transmitted. */ |
585fb111 JB |
5291 | # define TV_CC_DATA_2_MASK 0x007f0000 |
5292 | # define TV_CC_DATA_2_SHIFT 16 | |
646b4269 | 5293 | /* First word of CC data to be transmitted. */ |
585fb111 JB |
5294 | # define TV_CC_DATA_1_MASK 0x0000007f |
5295 | # define TV_CC_DATA_1_SHIFT 0 | |
5296 | ||
f0f59a00 VS |
5297 | #define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */ |
5298 | #define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */ | |
5299 | #define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */ | |
5300 | #define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */ | |
585fb111 | 5301 | |
040d87f1 | 5302 | /* Display Port */ |
f0f59a00 VS |
5303 | #define DP_A _MMIO(0x64000) /* eDP */ |
5304 | #define DP_B _MMIO(0x64100) | |
5305 | #define DP_C _MMIO(0x64200) | |
5306 | #define DP_D _MMIO(0x64300) | |
040d87f1 | 5307 | |
f0f59a00 VS |
5308 | #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100) |
5309 | #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200) | |
5310 | #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300) | |
e66eb81d | 5311 | |
040d87f1 | 5312 | #define DP_PORT_EN (1 << 31) |
59b74c49 VS |
5313 | #define DP_PIPE_SEL_SHIFT 30 |
5314 | #define DP_PIPE_SEL_MASK (1 << 30) | |
5315 | #define DP_PIPE_SEL(pipe) ((pipe) << 30) | |
5316 | #define DP_PIPE_SEL_SHIFT_IVB 29 | |
5317 | #define DP_PIPE_SEL_MASK_IVB (3 << 29) | |
5318 | #define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29) | |
5319 | #define DP_PIPE_SEL_SHIFT_CHV 16 | |
5320 | #define DP_PIPE_SEL_MASK_CHV (3 << 16) | |
5321 | #define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16) | |
47a05eca | 5322 | |
040d87f1 KP |
5323 | /* Link training mode - select a suitable mode for each stage */ |
5324 | #define DP_LINK_TRAIN_PAT_1 (0 << 28) | |
5325 | #define DP_LINK_TRAIN_PAT_2 (1 << 28) | |
5326 | #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) | |
5327 | #define DP_LINK_TRAIN_OFF (3 << 28) | |
5328 | #define DP_LINK_TRAIN_MASK (3 << 28) | |
5329 | #define DP_LINK_TRAIN_SHIFT 28 | |
5330 | ||
8db9d77b ZW |
5331 | /* CPT Link training mode */ |
5332 | #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) | |
5333 | #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) | |
5334 | #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) | |
5335 | #define DP_LINK_TRAIN_OFF_CPT (3 << 8) | |
5336 | #define DP_LINK_TRAIN_MASK_CPT (7 << 8) | |
5337 | #define DP_LINK_TRAIN_SHIFT_CPT 8 | |
5338 | ||
040d87f1 KP |
5339 | /* Signal voltages. These are mostly controlled by the other end */ |
5340 | #define DP_VOLTAGE_0_4 (0 << 25) | |
5341 | #define DP_VOLTAGE_0_6 (1 << 25) | |
5342 | #define DP_VOLTAGE_0_8 (2 << 25) | |
5343 | #define DP_VOLTAGE_1_2 (3 << 25) | |
5344 | #define DP_VOLTAGE_MASK (7 << 25) | |
5345 | #define DP_VOLTAGE_SHIFT 25 | |
5346 | ||
5347 | /* Signal pre-emphasis levels, like voltages, the other end tells us what | |
5348 | * they want | |
5349 | */ | |
5350 | #define DP_PRE_EMPHASIS_0 (0 << 22) | |
5351 | #define DP_PRE_EMPHASIS_3_5 (1 << 22) | |
5352 | #define DP_PRE_EMPHASIS_6 (2 << 22) | |
5353 | #define DP_PRE_EMPHASIS_9_5 (3 << 22) | |
5354 | #define DP_PRE_EMPHASIS_MASK (7 << 22) | |
5355 | #define DP_PRE_EMPHASIS_SHIFT 22 | |
5356 | ||
5357 | /* How many wires to use. I guess 3 was too hard */ | |
17aa6be9 | 5358 | #define DP_PORT_WIDTH(width) (((width) - 1) << 19) |
040d87f1 | 5359 | #define DP_PORT_WIDTH_MASK (7 << 19) |
90a6b7b0 | 5360 | #define DP_PORT_WIDTH_SHIFT 19 |
040d87f1 KP |
5361 | |
5362 | /* Mystic DPCD version 1.1 special mode */ | |
5363 | #define DP_ENHANCED_FRAMING (1 << 18) | |
5364 | ||
32f9d658 ZW |
5365 | /* eDP */ |
5366 | #define DP_PLL_FREQ_270MHZ (0 << 16) | |
b377e0df | 5367 | #define DP_PLL_FREQ_162MHZ (1 << 16) |
32f9d658 ZW |
5368 | #define DP_PLL_FREQ_MASK (3 << 16) |
5369 | ||
646b4269 | 5370 | /* locked once port is enabled */ |
040d87f1 KP |
5371 | #define DP_PORT_REVERSAL (1 << 15) |
5372 | ||
32f9d658 ZW |
5373 | /* eDP */ |
5374 | #define DP_PLL_ENABLE (1 << 14) | |
5375 | ||
646b4269 | 5376 | /* sends the clock on lane 15 of the PEG for debug */ |
040d87f1 KP |
5377 | #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) |
5378 | ||
5379 | #define DP_SCRAMBLING_DISABLE (1 << 12) | |
f2b115e6 | 5380 | #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) |
040d87f1 | 5381 | |
646b4269 | 5382 | /* limit RGB values to avoid confusing TVs */ |
040d87f1 KP |
5383 | #define DP_COLOR_RANGE_16_235 (1 << 8) |
5384 | ||
646b4269 | 5385 | /* Turn on the audio link */ |
040d87f1 KP |
5386 | #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) |
5387 | ||
646b4269 | 5388 | /* vs and hs sync polarity */ |
040d87f1 KP |
5389 | #define DP_SYNC_VS_HIGH (1 << 4) |
5390 | #define DP_SYNC_HS_HIGH (1 << 3) | |
5391 | ||
646b4269 | 5392 | /* A fantasy */ |
040d87f1 KP |
5393 | #define DP_DETECTED (1 << 2) |
5394 | ||
646b4269 | 5395 | /* The aux channel provides a way to talk to the |
040d87f1 KP |
5396 | * signal sink for DDC etc. Max packet size supported |
5397 | * is 20 bytes in each direction, hence the 5 fixed | |
5398 | * data registers | |
5399 | */ | |
da00bdcf VS |
5400 | #define _DPA_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64010) |
5401 | #define _DPA_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64014) | |
5402 | #define _DPA_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64018) | |
5403 | #define _DPA_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6401c) | |
5404 | #define _DPA_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64020) | |
5405 | #define _DPA_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64024) | |
5406 | ||
5407 | #define _DPB_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64110) | |
5408 | #define _DPB_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64114) | |
5409 | #define _DPB_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64118) | |
5410 | #define _DPB_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6411c) | |
5411 | #define _DPB_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64120) | |
5412 | #define _DPB_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64124) | |
5413 | ||
5414 | #define _DPC_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64210) | |
5415 | #define _DPC_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64214) | |
5416 | #define _DPC_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64218) | |
5417 | #define _DPC_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6421c) | |
5418 | #define _DPC_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64220) | |
5419 | #define _DPC_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64224) | |
5420 | ||
5421 | #define _DPD_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64310) | |
5422 | #define _DPD_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64314) | |
5423 | #define _DPD_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64318) | |
5424 | #define _DPD_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6431c) | |
5425 | #define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320) | |
5426 | #define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324) | |
750a951f | 5427 | |
bb187e93 JA |
5428 | #define _DPE_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64410) |
5429 | #define _DPE_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64414) | |
5430 | #define _DPE_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64418) | |
5431 | #define _DPE_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6441c) | |
5432 | #define _DPE_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64420) | |
5433 | #define _DPE_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64424) | |
5434 | ||
a324fcac RV |
5435 | #define _DPF_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64510) |
5436 | #define _DPF_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64514) | |
5437 | #define _DPF_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64518) | |
5438 | #define _DPF_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6451c) | |
5439 | #define _DPF_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64520) | |
5440 | #define _DPF_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64524) | |
5441 | ||
bdabdb63 VS |
5442 | #define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL) |
5443 | #define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ | |
040d87f1 KP |
5444 | |
5445 | #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) | |
5446 | #define DP_AUX_CH_CTL_DONE (1 << 30) | |
5447 | #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) | |
5448 | #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) | |
5449 | #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) | |
5450 | #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) | |
5451 | #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) | |
6fa228ba | 5452 | #define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */ |
040d87f1 KP |
5453 | #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) |
5454 | #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) | |
5455 | #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) | |
5456 | #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 | |
5457 | #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) | |
5458 | #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 | |
5459 | #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) | |
5460 | #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) | |
5461 | #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) | |
5462 | #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) | |
5463 | #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) | |
5464 | #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) | |
5465 | #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 | |
e3d99845 SJ |
5466 | #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14) |
5467 | #define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13) | |
5468 | #define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12) | |
395b2913 | 5469 | #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5) |
e3d99845 | 5470 | #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5) |
b9ca5fad | 5471 | #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1) |
040d87f1 KP |
5472 | |
5473 | /* | |
5474 | * Computing GMCH M and N values for the Display Port link | |
5475 | * | |
5476 | * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes | |
5477 | * | |
5478 | * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) | |
5479 | * | |
5480 | * The GMCH value is used internally | |
5481 | * | |
5482 | * bytes_per_pixel is the number of bytes coming out of the plane, | |
5483 | * which is after the LUTs, so we want the bytes for our color format. | |
5484 | * For our current usage, this is always 3, one byte for R, G and B. | |
5485 | */ | |
e3b95f1e DV |
5486 | #define _PIPEA_DATA_M_G4X 0x70050 |
5487 | #define _PIPEB_DATA_M_G4X 0x71050 | |
040d87f1 KP |
5488 | |
5489 | /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ | |
5ee8ee86 | 5490 | #define TU_SIZE(x) (((x) - 1) << 25) /* default size 64 */ |
72419203 | 5491 | #define TU_SIZE_SHIFT 25 |
a65851af | 5492 | #define TU_SIZE_MASK (0x3f << 25) |
040d87f1 | 5493 | |
a65851af VS |
5494 | #define DATA_LINK_M_N_MASK (0xffffff) |
5495 | #define DATA_LINK_N_MAX (0x800000) | |
040d87f1 | 5496 | |
e3b95f1e DV |
5497 | #define _PIPEA_DATA_N_G4X 0x70054 |
5498 | #define _PIPEB_DATA_N_G4X 0x71054 | |
040d87f1 KP |
5499 | #define PIPE_GMCH_DATA_N_MASK (0xffffff) |
5500 | ||
5501 | /* | |
5502 | * Computing Link M and N values for the Display Port link | |
5503 | * | |
5504 | * Link M / N = pixel_clock / ls_clk | |
5505 | * | |
5506 | * (the DP spec calls pixel_clock the 'strm_clk') | |
5507 | * | |
5508 | * The Link value is transmitted in the Main Stream | |
5509 | * Attributes and VB-ID. | |
5510 | */ | |
5511 | ||
e3b95f1e DV |
5512 | #define _PIPEA_LINK_M_G4X 0x70060 |
5513 | #define _PIPEB_LINK_M_G4X 0x71060 | |
040d87f1 KP |
5514 | #define PIPEA_DP_LINK_M_MASK (0xffffff) |
5515 | ||
e3b95f1e DV |
5516 | #define _PIPEA_LINK_N_G4X 0x70064 |
5517 | #define _PIPEB_LINK_N_G4X 0x71064 | |
040d87f1 KP |
5518 | #define PIPEA_DP_LINK_N_MASK (0xffffff) |
5519 | ||
f0f59a00 VS |
5520 | #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X) |
5521 | #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X) | |
5522 | #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X) | |
5523 | #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X) | |
9db4a9c7 | 5524 | |
585fb111 JB |
5525 | /* Display & cursor control */ |
5526 | ||
5527 | /* Pipe A */ | |
a57c774a | 5528 | #define _PIPEADSL 0x70000 |
837ba00f PZ |
5529 | #define DSL_LINEMASK_GEN2 0x00000fff |
5530 | #define DSL_LINEMASK_GEN3 0x00001fff | |
a57c774a | 5531 | #define _PIPEACONF 0x70008 |
5ee8ee86 | 5532 | #define PIPECONF_ENABLE (1 << 31) |
5eddb70b | 5533 | #define PIPECONF_DISABLE 0 |
5ee8ee86 PZ |
5534 | #define PIPECONF_DOUBLE_WIDE (1 << 30) |
5535 | #define I965_PIPECONF_ACTIVE (1 << 30) | |
5536 | #define PIPECONF_DSI_PLL_LOCKED (1 << 29) /* vlv & pipe A only */ | |
5537 | #define PIPECONF_FRAME_START_DELAY_MASK (3 << 27) | |
5eddb70b CW |
5538 | #define PIPECONF_SINGLE_WIDE 0 |
5539 | #define PIPECONF_PIPE_UNLOCKED 0 | |
5ee8ee86 | 5540 | #define PIPECONF_PIPE_LOCKED (1 << 25) |
5eddb70b | 5541 | #define PIPECONF_PALETTE 0 |
5ee8ee86 PZ |
5542 | #define PIPECONF_GAMMA (1 << 24) |
5543 | #define PIPECONF_FORCE_BORDER (1 << 25) | |
59df7b17 | 5544 | #define PIPECONF_INTERLACE_MASK (7 << 21) |
ee2b0b38 | 5545 | #define PIPECONF_INTERLACE_MASK_HSW (3 << 21) |
d442ae18 DV |
5546 | /* Note that pre-gen3 does not support interlaced display directly. Panel |
5547 | * fitting must be disabled on pre-ilk for interlaced. */ | |
5548 | #define PIPECONF_PROGRESSIVE (0 << 21) | |
5549 | #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ | |
5550 | #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ | |
5551 | #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) | |
5552 | #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ | |
5553 | /* Ironlake and later have a complete new set of values for interlaced. PFIT | |
5554 | * means panel fitter required, PF means progressive fetch, DBL means power | |
5555 | * saving pixel doubling. */ | |
5556 | #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) | |
5557 | #define PIPECONF_INTERLACED_ILK (3 << 21) | |
5558 | #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ | |
5559 | #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ | |
1bd1bd80 | 5560 | #define PIPECONF_INTERLACE_MODE_MASK (7 << 21) |
439d7ac0 | 5561 | #define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20) |
5ee8ee86 | 5562 | #define PIPECONF_CXSR_DOWNCLOCK (1 << 16) |
6fa7aec1 | 5563 | #define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14) |
3685a8f3 | 5564 | #define PIPECONF_COLOR_RANGE_SELECT (1 << 13) |
dfd07d72 | 5565 | #define PIPECONF_BPC_MASK (0x7 << 5) |
5ee8ee86 PZ |
5566 | #define PIPECONF_8BPC (0 << 5) |
5567 | #define PIPECONF_10BPC (1 << 5) | |
5568 | #define PIPECONF_6BPC (2 << 5) | |
5569 | #define PIPECONF_12BPC (3 << 5) | |
5570 | #define PIPECONF_DITHER_EN (1 << 4) | |
4f0d1aff | 5571 | #define PIPECONF_DITHER_TYPE_MASK (0x0000000c) |
5ee8ee86 PZ |
5572 | #define PIPECONF_DITHER_TYPE_SP (0 << 2) |
5573 | #define PIPECONF_DITHER_TYPE_ST1 (1 << 2) | |
5574 | #define PIPECONF_DITHER_TYPE_ST2 (2 << 2) | |
5575 | #define PIPECONF_DITHER_TYPE_TEMP (3 << 2) | |
a57c774a | 5576 | #define _PIPEASTAT 0x70024 |
5ee8ee86 PZ |
5577 | #define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31) |
5578 | #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30) | |
5579 | #define PIPE_CRC_ERROR_ENABLE (1UL << 29) | |
5580 | #define PIPE_CRC_DONE_ENABLE (1UL << 28) | |
5581 | #define PERF_COUNTER2_INTERRUPT_EN (1UL << 27) | |
5582 | #define PIPE_GMBUS_EVENT_ENABLE (1UL << 27) | |
5583 | #define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26) | |
5584 | #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26) | |
5585 | #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25) | |
5586 | #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24) | |
5587 | #define PIPE_DPST_EVENT_ENABLE (1UL << 23) | |
5588 | #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22) | |
5589 | #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22) | |
5590 | #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21) | |
5591 | #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20) | |
5592 | #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19) | |
5593 | #define PERF_COUNTER_INTERRUPT_EN (1UL << 19) | |
5594 | #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */ | |
5595 | #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */ | |
5596 | #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17) | |
5597 | #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17) | |
5598 | #define PIPEA_HBLANK_INT_EN_VLV (1UL << 16) | |
5599 | #define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16) | |
5600 | #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15) | |
5601 | #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14) | |
5602 | #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13) | |
5603 | #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12) | |
5604 | #define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11) | |
5605 | #define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11) | |
5606 | #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10) | |
5607 | #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10) | |
5608 | #define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9) | |
5609 | #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8) | |
5610 | #define PIPE_DPST_EVENT_STATUS (1UL << 7) | |
5611 | #define PIPE_A_PSR_STATUS_VLV (1UL << 6) | |
5612 | #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6) | |
5613 | #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5) | |
5614 | #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4) | |
5615 | #define PIPE_B_PSR_STATUS_VLV (1UL << 3) | |
5616 | #define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3) | |
5617 | #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */ | |
5618 | #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */ | |
5619 | #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1) | |
5620 | #define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1) | |
5621 | #define PIPE_HBLANK_INT_STATUS (1UL << 0) | |
5622 | #define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0) | |
585fb111 | 5623 | |
755e9019 ID |
5624 | #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 |
5625 | #define PIPESTAT_INT_STATUS_MASK 0x0000ffff | |
5626 | ||
84fd4f4e RB |
5627 | #define PIPE_A_OFFSET 0x70000 |
5628 | #define PIPE_B_OFFSET 0x71000 | |
5629 | #define PIPE_C_OFFSET 0x72000 | |
5630 | #define CHV_PIPE_C_OFFSET 0x74000 | |
a57c774a AK |
5631 | /* |
5632 | * There's actually no pipe EDP. Some pipe registers have | |
5633 | * simply shifted from the pipe to the transcoder, while | |
5634 | * keeping their original offset. Thus we need PIPE_EDP_OFFSET | |
5635 | * to access such registers in transcoder EDP. | |
5636 | */ | |
5637 | #define PIPE_EDP_OFFSET 0x7f000 | |
5638 | ||
f0f59a00 | 5639 | #define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \ |
5c969aa7 DL |
5640 | dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \ |
5641 | dev_priv->info.display_mmio_offset) | |
a57c774a | 5642 | |
f0f59a00 VS |
5643 | #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF) |
5644 | #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL) | |
5645 | #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH) | |
5646 | #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL) | |
5647 | #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT) | |
5eddb70b | 5648 | |
756f85cf PZ |
5649 | #define _PIPE_MISC_A 0x70030 |
5650 | #define _PIPE_MISC_B 0x71030 | |
5ee8ee86 PZ |
5651 | #define PIPEMISC_YUV420_ENABLE (1 << 27) |
5652 | #define PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26) | |
5653 | #define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11) | |
5654 | #define PIPEMISC_DITHER_BPC_MASK (7 << 5) | |
5655 | #define PIPEMISC_DITHER_8_BPC (0 << 5) | |
5656 | #define PIPEMISC_DITHER_10_BPC (1 << 5) | |
5657 | #define PIPEMISC_DITHER_6_BPC (2 << 5) | |
5658 | #define PIPEMISC_DITHER_12_BPC (3 << 5) | |
5659 | #define PIPEMISC_DITHER_ENABLE (1 << 4) | |
5660 | #define PIPEMISC_DITHER_TYPE_MASK (3 << 2) | |
5661 | #define PIPEMISC_DITHER_TYPE_SP (0 << 2) | |
f0f59a00 | 5662 | #define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A) |
756f85cf | 5663 | |
f0f59a00 | 5664 | #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028) |
5ee8ee86 PZ |
5665 | #define PIPEB_LINE_COMPARE_INT_EN (1 << 29) |
5666 | #define PIPEB_HLINE_INT_EN (1 << 28) | |
5667 | #define PIPEB_VBLANK_INT_EN (1 << 27) | |
5668 | #define SPRITED_FLIP_DONE_INT_EN (1 << 26) | |
5669 | #define SPRITEC_FLIP_DONE_INT_EN (1 << 25) | |
5670 | #define PLANEB_FLIP_DONE_INT_EN (1 << 24) | |
5671 | #define PIPE_PSR_INT_EN (1 << 22) | |
5672 | #define PIPEA_LINE_COMPARE_INT_EN (1 << 21) | |
5673 | #define PIPEA_HLINE_INT_EN (1 << 20) | |
5674 | #define PIPEA_VBLANK_INT_EN (1 << 19) | |
5675 | #define SPRITEB_FLIP_DONE_INT_EN (1 << 18) | |
5676 | #define SPRITEA_FLIP_DONE_INT_EN (1 << 17) | |
5677 | #define PLANEA_FLIPDONE_INT_EN (1 << 16) | |
5678 | #define PIPEC_LINE_COMPARE_INT_EN (1 << 13) | |
5679 | #define PIPEC_HLINE_INT_EN (1 << 12) | |
5680 | #define PIPEC_VBLANK_INT_EN (1 << 11) | |
5681 | #define SPRITEF_FLIPDONE_INT_EN (1 << 10) | |
5682 | #define SPRITEE_FLIPDONE_INT_EN (1 << 9) | |
5683 | #define PLANEC_FLIPDONE_INT_EN (1 << 8) | |
c46ce4d7 | 5684 | |
f0f59a00 | 5685 | #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ |
5ee8ee86 PZ |
5686 | #define SPRITEF_INVALID_GTT_INT_EN (1 << 27) |
5687 | #define SPRITEE_INVALID_GTT_INT_EN (1 << 26) | |
5688 | #define PLANEC_INVALID_GTT_INT_EN (1 << 25) | |
5689 | #define CURSORC_INVALID_GTT_INT_EN (1 << 24) | |
5690 | #define CURSORB_INVALID_GTT_INT_EN (1 << 23) | |
5691 | #define CURSORA_INVALID_GTT_INT_EN (1 << 22) | |
5692 | #define SPRITED_INVALID_GTT_INT_EN (1 << 21) | |
5693 | #define SPRITEC_INVALID_GTT_INT_EN (1 << 20) | |
5694 | #define PLANEB_INVALID_GTT_INT_EN (1 << 19) | |
5695 | #define SPRITEB_INVALID_GTT_INT_EN (1 << 18) | |
5696 | #define SPRITEA_INVALID_GTT_INT_EN (1 << 17) | |
5697 | #define PLANEA_INVALID_GTT_INT_EN (1 << 16) | |
c46ce4d7 | 5698 | #define DPINVGTT_EN_MASK 0xff0000 |
bf67a6fd | 5699 | #define DPINVGTT_EN_MASK_CHV 0xfff0000 |
5ee8ee86 PZ |
5700 | #define SPRITEF_INVALID_GTT_STATUS (1 << 11) |
5701 | #define SPRITEE_INVALID_GTT_STATUS (1 << 10) | |
5702 | #define PLANEC_INVALID_GTT_STATUS (1 << 9) | |
5703 | #define CURSORC_INVALID_GTT_STATUS (1 << 8) | |
5704 | #define CURSORB_INVALID_GTT_STATUS (1 << 7) | |
5705 | #define CURSORA_INVALID_GTT_STATUS (1 << 6) | |
5706 | #define SPRITED_INVALID_GTT_STATUS (1 << 5) | |
5707 | #define SPRITEC_INVALID_GTT_STATUS (1 << 4) | |
5708 | #define PLANEB_INVALID_GTT_STATUS (1 << 3) | |
5709 | #define SPRITEB_INVALID_GTT_STATUS (1 << 2) | |
5710 | #define SPRITEA_INVALID_GTT_STATUS (1 << 1) | |
5711 | #define PLANEA_INVALID_GTT_STATUS (1 << 0) | |
c46ce4d7 | 5712 | #define DPINVGTT_STATUS_MASK 0xff |
bf67a6fd | 5713 | #define DPINVGTT_STATUS_MASK_CHV 0xfff |
c46ce4d7 | 5714 | |
f0f59a00 | 5715 | #define DSPARB _MMIO(dev_priv->info.display_mmio_offset + 0x70030) |
585fb111 JB |
5716 | #define DSPARB_CSTART_MASK (0x7f << 7) |
5717 | #define DSPARB_CSTART_SHIFT 7 | |
5718 | #define DSPARB_BSTART_MASK (0x7f) | |
5719 | #define DSPARB_BSTART_SHIFT 0 | |
7662c8bd SL |
5720 | #define DSPARB_BEND_SHIFT 9 /* on 855 */ |
5721 | #define DSPARB_AEND_SHIFT 0 | |
54f1b6e1 VS |
5722 | #define DSPARB_SPRITEA_SHIFT_VLV 0 |
5723 | #define DSPARB_SPRITEA_MASK_VLV (0xff << 0) | |
5724 | #define DSPARB_SPRITEB_SHIFT_VLV 8 | |
5725 | #define DSPARB_SPRITEB_MASK_VLV (0xff << 8) | |
5726 | #define DSPARB_SPRITEC_SHIFT_VLV 16 | |
5727 | #define DSPARB_SPRITEC_MASK_VLV (0xff << 16) | |
5728 | #define DSPARB_SPRITED_SHIFT_VLV 24 | |
5729 | #define DSPARB_SPRITED_MASK_VLV (0xff << 24) | |
f0f59a00 | 5730 | #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */ |
54f1b6e1 VS |
5731 | #define DSPARB_SPRITEA_HI_SHIFT_VLV 0 |
5732 | #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0) | |
5733 | #define DSPARB_SPRITEB_HI_SHIFT_VLV 4 | |
5734 | #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4) | |
5735 | #define DSPARB_SPRITEC_HI_SHIFT_VLV 8 | |
5736 | #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8) | |
5737 | #define DSPARB_SPRITED_HI_SHIFT_VLV 12 | |
5738 | #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12) | |
5739 | #define DSPARB_SPRITEE_HI_SHIFT_VLV 16 | |
5740 | #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16) | |
5741 | #define DSPARB_SPRITEF_HI_SHIFT_VLV 20 | |
5742 | #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20) | |
f0f59a00 | 5743 | #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */ |
54f1b6e1 VS |
5744 | #define DSPARB_SPRITEE_SHIFT_VLV 0 |
5745 | #define DSPARB_SPRITEE_MASK_VLV (0xff << 0) | |
5746 | #define DSPARB_SPRITEF_SHIFT_VLV 8 | |
5747 | #define DSPARB_SPRITEF_MASK_VLV (0xff << 8) | |
b5004720 | 5748 | |
0a560674 | 5749 | /* pnv/gen4/g4x/vlv/chv */ |
f0f59a00 | 5750 | #define DSPFW1 _MMIO(dev_priv->info.display_mmio_offset + 0x70034) |
0a560674 | 5751 | #define DSPFW_SR_SHIFT 23 |
5ee8ee86 | 5752 | #define DSPFW_SR_MASK (0x1ff << 23) |
0a560674 | 5753 | #define DSPFW_CURSORB_SHIFT 16 |
5ee8ee86 | 5754 | #define DSPFW_CURSORB_MASK (0x3f << 16) |
0a560674 | 5755 | #define DSPFW_PLANEB_SHIFT 8 |
5ee8ee86 PZ |
5756 | #define DSPFW_PLANEB_MASK (0x7f << 8) |
5757 | #define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */ | |
0a560674 | 5758 | #define DSPFW_PLANEA_SHIFT 0 |
5ee8ee86 PZ |
5759 | #define DSPFW_PLANEA_MASK (0x7f << 0) |
5760 | #define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */ | |
f0f59a00 | 5761 | #define DSPFW2 _MMIO(dev_priv->info.display_mmio_offset + 0x70038) |
5ee8ee86 | 5762 | #define DSPFW_FBC_SR_EN (1 << 31) /* g4x */ |
0a560674 | 5763 | #define DSPFW_FBC_SR_SHIFT 28 |
5ee8ee86 | 5764 | #define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */ |
0a560674 | 5765 | #define DSPFW_FBC_HPLL_SR_SHIFT 24 |
5ee8ee86 | 5766 | #define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */ |
0a560674 | 5767 | #define DSPFW_SPRITEB_SHIFT (16) |
5ee8ee86 PZ |
5768 | #define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */ |
5769 | #define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */ | |
0a560674 | 5770 | #define DSPFW_CURSORA_SHIFT 8 |
5ee8ee86 | 5771 | #define DSPFW_CURSORA_MASK (0x3f << 8) |
f4998963 | 5772 | #define DSPFW_PLANEC_OLD_SHIFT 0 |
5ee8ee86 | 5773 | #define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */ |
0a560674 | 5774 | #define DSPFW_SPRITEA_SHIFT 0 |
5ee8ee86 PZ |
5775 | #define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */ |
5776 | #define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */ | |
f0f59a00 | 5777 | #define DSPFW3 _MMIO(dev_priv->info.display_mmio_offset + 0x7003c) |
5ee8ee86 PZ |
5778 | #define DSPFW_HPLL_SR_EN (1 << 31) |
5779 | #define PINEVIEW_SELF_REFRESH_EN (1 << 30) | |
0a560674 | 5780 | #define DSPFW_CURSOR_SR_SHIFT 24 |
5ee8ee86 | 5781 | #define DSPFW_CURSOR_SR_MASK (0x3f << 24) |
d4294342 | 5782 | #define DSPFW_HPLL_CURSOR_SHIFT 16 |
5ee8ee86 | 5783 | #define DSPFW_HPLL_CURSOR_MASK (0x3f << 16) |
0a560674 | 5784 | #define DSPFW_HPLL_SR_SHIFT 0 |
5ee8ee86 | 5785 | #define DSPFW_HPLL_SR_MASK (0x1ff << 0) |
0a560674 VS |
5786 | |
5787 | /* vlv/chv */ | |
f0f59a00 | 5788 | #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070) |
0a560674 | 5789 | #define DSPFW_SPRITEB_WM1_SHIFT 16 |
5ee8ee86 | 5790 | #define DSPFW_SPRITEB_WM1_MASK (0xff << 16) |
0a560674 | 5791 | #define DSPFW_CURSORA_WM1_SHIFT 8 |
5ee8ee86 | 5792 | #define DSPFW_CURSORA_WM1_MASK (0x3f << 8) |
0a560674 | 5793 | #define DSPFW_SPRITEA_WM1_SHIFT 0 |
5ee8ee86 | 5794 | #define DSPFW_SPRITEA_WM1_MASK (0xff << 0) |
f0f59a00 | 5795 | #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074) |
0a560674 | 5796 | #define DSPFW_PLANEB_WM1_SHIFT 24 |
5ee8ee86 | 5797 | #define DSPFW_PLANEB_WM1_MASK (0xff << 24) |
0a560674 | 5798 | #define DSPFW_PLANEA_WM1_SHIFT 16 |
5ee8ee86 | 5799 | #define DSPFW_PLANEA_WM1_MASK (0xff << 16) |
0a560674 | 5800 | #define DSPFW_CURSORB_WM1_SHIFT 8 |
5ee8ee86 | 5801 | #define DSPFW_CURSORB_WM1_MASK (0x3f << 8) |
0a560674 | 5802 | #define DSPFW_CURSOR_SR_WM1_SHIFT 0 |
5ee8ee86 | 5803 | #define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0) |
f0f59a00 | 5804 | #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078) |
0a560674 | 5805 | #define DSPFW_SR_WM1_SHIFT 0 |
5ee8ee86 | 5806 | #define DSPFW_SR_WM1_MASK (0x1ff << 0) |
f0f59a00 VS |
5807 | #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c) |
5808 | #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */ | |
0a560674 | 5809 | #define DSPFW_SPRITED_WM1_SHIFT 24 |
5ee8ee86 | 5810 | #define DSPFW_SPRITED_WM1_MASK (0xff << 24) |
0a560674 | 5811 | #define DSPFW_SPRITED_SHIFT 16 |
5ee8ee86 | 5812 | #define DSPFW_SPRITED_MASK_VLV (0xff << 16) |
0a560674 | 5813 | #define DSPFW_SPRITEC_WM1_SHIFT 8 |
5ee8ee86 | 5814 | #define DSPFW_SPRITEC_WM1_MASK (0xff << 8) |
0a560674 | 5815 | #define DSPFW_SPRITEC_SHIFT 0 |
5ee8ee86 | 5816 | #define DSPFW_SPRITEC_MASK_VLV (0xff << 0) |
f0f59a00 | 5817 | #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8) |
0a560674 | 5818 | #define DSPFW_SPRITEF_WM1_SHIFT 24 |
5ee8ee86 | 5819 | #define DSPFW_SPRITEF_WM1_MASK (0xff << 24) |
0a560674 | 5820 | #define DSPFW_SPRITEF_SHIFT 16 |
5ee8ee86 | 5821 | #define DSPFW_SPRITEF_MASK_VLV (0xff << 16) |
0a560674 | 5822 | #define DSPFW_SPRITEE_WM1_SHIFT 8 |
5ee8ee86 | 5823 | #define DSPFW_SPRITEE_WM1_MASK (0xff << 8) |
0a560674 | 5824 | #define DSPFW_SPRITEE_SHIFT 0 |
5ee8ee86 | 5825 | #define DSPFW_SPRITEE_MASK_VLV (0xff << 0) |
f0f59a00 | 5826 | #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */ |
0a560674 | 5827 | #define DSPFW_PLANEC_WM1_SHIFT 24 |
5ee8ee86 | 5828 | #define DSPFW_PLANEC_WM1_MASK (0xff << 24) |
0a560674 | 5829 | #define DSPFW_PLANEC_SHIFT 16 |
5ee8ee86 | 5830 | #define DSPFW_PLANEC_MASK_VLV (0xff << 16) |
0a560674 | 5831 | #define DSPFW_CURSORC_WM1_SHIFT 8 |
5ee8ee86 | 5832 | #define DSPFW_CURSORC_WM1_MASK (0x3f << 16) |
0a560674 | 5833 | #define DSPFW_CURSORC_SHIFT 0 |
5ee8ee86 | 5834 | #define DSPFW_CURSORC_MASK (0x3f << 0) |
0a560674 VS |
5835 | |
5836 | /* vlv/chv high order bits */ | |
f0f59a00 | 5837 | #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064) |
0a560674 | 5838 | #define DSPFW_SR_HI_SHIFT 24 |
5ee8ee86 | 5839 | #define DSPFW_SR_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ |
0a560674 | 5840 | #define DSPFW_SPRITEF_HI_SHIFT 23 |
5ee8ee86 | 5841 | #define DSPFW_SPRITEF_HI_MASK (1 << 23) |
0a560674 | 5842 | #define DSPFW_SPRITEE_HI_SHIFT 22 |
5ee8ee86 | 5843 | #define DSPFW_SPRITEE_HI_MASK (1 << 22) |
0a560674 | 5844 | #define DSPFW_PLANEC_HI_SHIFT 21 |
5ee8ee86 | 5845 | #define DSPFW_PLANEC_HI_MASK (1 << 21) |
0a560674 | 5846 | #define DSPFW_SPRITED_HI_SHIFT 20 |
5ee8ee86 | 5847 | #define DSPFW_SPRITED_HI_MASK (1 << 20) |
0a560674 | 5848 | #define DSPFW_SPRITEC_HI_SHIFT 16 |
5ee8ee86 | 5849 | #define DSPFW_SPRITEC_HI_MASK (1 << 16) |
0a560674 | 5850 | #define DSPFW_PLANEB_HI_SHIFT 12 |
5ee8ee86 | 5851 | #define DSPFW_PLANEB_HI_MASK (1 << 12) |
0a560674 | 5852 | #define DSPFW_SPRITEB_HI_SHIFT 8 |
5ee8ee86 | 5853 | #define DSPFW_SPRITEB_HI_MASK (1 << 8) |
0a560674 | 5854 | #define DSPFW_SPRITEA_HI_SHIFT 4 |
5ee8ee86 | 5855 | #define DSPFW_SPRITEA_HI_MASK (1 << 4) |
0a560674 | 5856 | #define DSPFW_PLANEA_HI_SHIFT 0 |
5ee8ee86 | 5857 | #define DSPFW_PLANEA_HI_MASK (1 << 0) |
f0f59a00 | 5858 | #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068) |
0a560674 | 5859 | #define DSPFW_SR_WM1_HI_SHIFT 24 |
5ee8ee86 | 5860 | #define DSPFW_SR_WM1_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ |
0a560674 | 5861 | #define DSPFW_SPRITEF_WM1_HI_SHIFT 23 |
5ee8ee86 | 5862 | #define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23) |
0a560674 | 5863 | #define DSPFW_SPRITEE_WM1_HI_SHIFT 22 |
5ee8ee86 | 5864 | #define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22) |
0a560674 | 5865 | #define DSPFW_PLANEC_WM1_HI_SHIFT 21 |
5ee8ee86 | 5866 | #define DSPFW_PLANEC_WM1_HI_MASK (1 << 21) |
0a560674 | 5867 | #define DSPFW_SPRITED_WM1_HI_SHIFT 20 |
5ee8ee86 | 5868 | #define DSPFW_SPRITED_WM1_HI_MASK (1 << 20) |
0a560674 | 5869 | #define DSPFW_SPRITEC_WM1_HI_SHIFT 16 |
5ee8ee86 | 5870 | #define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16) |
0a560674 | 5871 | #define DSPFW_PLANEB_WM1_HI_SHIFT 12 |
5ee8ee86 | 5872 | #define DSPFW_PLANEB_WM1_HI_MASK (1 << 12) |
0a560674 | 5873 | #define DSPFW_SPRITEB_WM1_HI_SHIFT 8 |
5ee8ee86 | 5874 | #define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8) |
0a560674 | 5875 | #define DSPFW_SPRITEA_WM1_HI_SHIFT 4 |
5ee8ee86 | 5876 | #define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4) |
0a560674 | 5877 | #define DSPFW_PLANEA_WM1_HI_SHIFT 0 |
5ee8ee86 | 5878 | #define DSPFW_PLANEA_WM1_HI_MASK (1 << 0) |
7662c8bd | 5879 | |
12a3c055 | 5880 | /* drain latency register values*/ |
f0f59a00 | 5881 | #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe)) |
1abc4dc7 | 5882 | #define DDL_CURSOR_SHIFT 24 |
5ee8ee86 | 5883 | #define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite)) |
1abc4dc7 | 5884 | #define DDL_PLANE_SHIFT 0 |
5ee8ee86 PZ |
5885 | #define DDL_PRECISION_HIGH (1 << 7) |
5886 | #define DDL_PRECISION_LOW (0 << 7) | |
0948c265 | 5887 | #define DRAIN_LATENCY_MASK 0x7f |
12a3c055 | 5888 | |
f0f59a00 | 5889 | #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400) |
5ee8ee86 PZ |
5890 | #define CBR_PND_DEADLINE_DISABLE (1 << 31) |
5891 | #define CBR_PWM_CLOCK_MUX_SELECT (1 << 30) | |
c6beb13e | 5892 | |
c231775c | 5893 | #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450) |
5ee8ee86 | 5894 | #define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */ |
c231775c | 5895 | |
7662c8bd | 5896 | /* FIFO watermark sizes etc */ |
0e442c60 | 5897 | #define G4X_FIFO_LINE_SIZE 64 |
7662c8bd SL |
5898 | #define I915_FIFO_LINE_SIZE 64 |
5899 | #define I830_FIFO_LINE_SIZE 32 | |
0e442c60 | 5900 | |
ceb04246 | 5901 | #define VALLEYVIEW_FIFO_SIZE 255 |
0e442c60 | 5902 | #define G4X_FIFO_SIZE 127 |
1b07e04e ZY |
5903 | #define I965_FIFO_SIZE 512 |
5904 | #define I945_FIFO_SIZE 127 | |
7662c8bd | 5905 | #define I915_FIFO_SIZE 95 |
dff33cfc | 5906 | #define I855GM_FIFO_SIZE 127 /* In cachelines */ |
7662c8bd | 5907 | #define I830_FIFO_SIZE 95 |
0e442c60 | 5908 | |
ceb04246 | 5909 | #define VALLEYVIEW_MAX_WM 0xff |
0e442c60 | 5910 | #define G4X_MAX_WM 0x3f |
7662c8bd SL |
5911 | #define I915_MAX_WM 0x3f |
5912 | ||
f2b115e6 AJ |
5913 | #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ |
5914 | #define PINEVIEW_FIFO_LINE_SIZE 64 | |
5915 | #define PINEVIEW_MAX_WM 0x1ff | |
5916 | #define PINEVIEW_DFT_WM 0x3f | |
5917 | #define PINEVIEW_DFT_HPLLOFF_WM 0 | |
5918 | #define PINEVIEW_GUARD_WM 10 | |
5919 | #define PINEVIEW_CURSOR_FIFO 64 | |
5920 | #define PINEVIEW_CURSOR_MAX_WM 0x3f | |
5921 | #define PINEVIEW_CURSOR_DFT_WM 0 | |
5922 | #define PINEVIEW_CURSOR_GUARD_WM 5 | |
7662c8bd | 5923 | |
ceb04246 | 5924 | #define VALLEYVIEW_CURSOR_MAX_WM 64 |
4fe5e611 ZY |
5925 | #define I965_CURSOR_FIFO 64 |
5926 | #define I965_CURSOR_MAX_WM 32 | |
5927 | #define I965_CURSOR_DFT_WM 8 | |
7f8a8569 | 5928 | |
fae1267d | 5929 | /* Watermark register definitions for SKL */ |
086f8e84 VS |
5930 | #define _CUR_WM_A_0 0x70140 |
5931 | #define _CUR_WM_B_0 0x71140 | |
5932 | #define _PLANE_WM_1_A_0 0x70240 | |
5933 | #define _PLANE_WM_1_B_0 0x71240 | |
5934 | #define _PLANE_WM_2_A_0 0x70340 | |
5935 | #define _PLANE_WM_2_B_0 0x71340 | |
5936 | #define _PLANE_WM_TRANS_1_A_0 0x70268 | |
5937 | #define _PLANE_WM_TRANS_1_B_0 0x71268 | |
5938 | #define _PLANE_WM_TRANS_2_A_0 0x70368 | |
5939 | #define _PLANE_WM_TRANS_2_B_0 0x71368 | |
5940 | #define _CUR_WM_TRANS_A_0 0x70168 | |
5941 | #define _CUR_WM_TRANS_B_0 0x71168 | |
fae1267d PB |
5942 | #define PLANE_WM_EN (1 << 31) |
5943 | #define PLANE_WM_LINES_SHIFT 14 | |
5944 | #define PLANE_WM_LINES_MASK 0x1f | |
5945 | #define PLANE_WM_BLOCKS_MASK 0x3ff | |
5946 | ||
086f8e84 | 5947 | #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0) |
f0f59a00 VS |
5948 | #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level))) |
5949 | #define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0) | |
fae1267d | 5950 | |
086f8e84 VS |
5951 | #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0) |
5952 | #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0) | |
fae1267d PB |
5953 | #define _PLANE_WM_BASE(pipe, plane) \ |
5954 | _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe)) | |
5955 | #define PLANE_WM(pipe, plane, level) \ | |
f0f59a00 | 5956 | _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level))) |
fae1267d | 5957 | #define _PLANE_WM_TRANS_1(pipe) \ |
086f8e84 | 5958 | _PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0) |
fae1267d | 5959 | #define _PLANE_WM_TRANS_2(pipe) \ |
086f8e84 | 5960 | _PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0) |
fae1267d | 5961 | #define PLANE_WM_TRANS(pipe, plane) \ |
f0f59a00 | 5962 | _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))) |
fae1267d | 5963 | |
7f8a8569 | 5964 | /* define the Watermark register on Ironlake */ |
f0f59a00 | 5965 | #define WM0_PIPEA_ILK _MMIO(0x45100) |
5ee8ee86 | 5966 | #define WM0_PIPE_PLANE_MASK (0xffff << 16) |
7f8a8569 | 5967 | #define WM0_PIPE_PLANE_SHIFT 16 |
5ee8ee86 | 5968 | #define WM0_PIPE_SPRITE_MASK (0xff << 8) |
7f8a8569 | 5969 | #define WM0_PIPE_SPRITE_SHIFT 8 |
1996d624 | 5970 | #define WM0_PIPE_CURSOR_MASK (0xff) |
7f8a8569 | 5971 | |
f0f59a00 VS |
5972 | #define WM0_PIPEB_ILK _MMIO(0x45104) |
5973 | #define WM0_PIPEC_IVB _MMIO(0x45200) | |
5974 | #define WM1_LP_ILK _MMIO(0x45108) | |
5ee8ee86 | 5975 | #define WM1_LP_SR_EN (1 << 31) |
7f8a8569 | 5976 | #define WM1_LP_LATENCY_SHIFT 24 |
5ee8ee86 PZ |
5977 | #define WM1_LP_LATENCY_MASK (0x7f << 24) |
5978 | #define WM1_LP_FBC_MASK (0xf << 20) | |
4ed765f9 | 5979 | #define WM1_LP_FBC_SHIFT 20 |
416f4727 | 5980 | #define WM1_LP_FBC_SHIFT_BDW 19 |
5ee8ee86 | 5981 | #define WM1_LP_SR_MASK (0x7ff << 8) |
7f8a8569 | 5982 | #define WM1_LP_SR_SHIFT 8 |
1996d624 | 5983 | #define WM1_LP_CURSOR_MASK (0xff) |
f0f59a00 | 5984 | #define WM2_LP_ILK _MMIO(0x4510c) |
5ee8ee86 | 5985 | #define WM2_LP_EN (1 << 31) |
f0f59a00 | 5986 | #define WM3_LP_ILK _MMIO(0x45110) |
5ee8ee86 | 5987 | #define WM3_LP_EN (1 << 31) |
f0f59a00 VS |
5988 | #define WM1S_LP_ILK _MMIO(0x45120) |
5989 | #define WM2S_LP_IVB _MMIO(0x45124) | |
5990 | #define WM3S_LP_IVB _MMIO(0x45128) | |
5ee8ee86 | 5991 | #define WM1S_LP_EN (1 << 31) |
7f8a8569 | 5992 | |
cca32e9a PZ |
5993 | #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \ |
5994 | (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \ | |
5995 | ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur)) | |
5996 | ||
7f8a8569 | 5997 | /* Memory latency timer register */ |
f0f59a00 | 5998 | #define MLTR_ILK _MMIO(0x11222) |
b79d4990 JB |
5999 | #define MLTR_WM1_SHIFT 0 |
6000 | #define MLTR_WM2_SHIFT 8 | |
7f8a8569 ZW |
6001 | /* the unit of memory self-refresh latency time is 0.5us */ |
6002 | #define ILK_SRLT_MASK 0x3f | |
6003 | ||
1398261a YL |
6004 | |
6005 | /* the address where we get all kinds of latency value */ | |
f0f59a00 | 6006 | #define SSKPD _MMIO(0x5d10) |
1398261a YL |
6007 | #define SSKPD_WM_MASK 0x3f |
6008 | #define SSKPD_WM0_SHIFT 0 | |
6009 | #define SSKPD_WM1_SHIFT 8 | |
6010 | #define SSKPD_WM2_SHIFT 16 | |
6011 | #define SSKPD_WM3_SHIFT 24 | |
6012 | ||
585fb111 JB |
6013 | /* |
6014 | * The two pipe frame counter registers are not synchronized, so | |
6015 | * reading a stable value is somewhat tricky. The following code | |
6016 | * should work: | |
6017 | * | |
6018 | * do { | |
6019 | * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> | |
6020 | * PIPE_FRAME_HIGH_SHIFT; | |
6021 | * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> | |
6022 | * PIPE_FRAME_LOW_SHIFT); | |
6023 | * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> | |
6024 | * PIPE_FRAME_HIGH_SHIFT); | |
6025 | * } while (high1 != high2); | |
6026 | * frame = (high1 << 8) | low1; | |
6027 | */ | |
25a2e2d0 | 6028 | #define _PIPEAFRAMEHIGH 0x70040 |
585fb111 JB |
6029 | #define PIPE_FRAME_HIGH_MASK 0x0000ffff |
6030 | #define PIPE_FRAME_HIGH_SHIFT 0 | |
25a2e2d0 | 6031 | #define _PIPEAFRAMEPIXEL 0x70044 |
585fb111 JB |
6032 | #define PIPE_FRAME_LOW_MASK 0xff000000 |
6033 | #define PIPE_FRAME_LOW_SHIFT 24 | |
6034 | #define PIPE_PIXEL_MASK 0x00ffffff | |
6035 | #define PIPE_PIXEL_SHIFT 0 | |
9880b7a5 | 6036 | /* GM45+ just has to be different */ |
fd8f507c VS |
6037 | #define _PIPEA_FRMCOUNT_G4X 0x70040 |
6038 | #define _PIPEA_FLIPCOUNT_G4X 0x70044 | |
f0f59a00 VS |
6039 | #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X) |
6040 | #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X) | |
585fb111 JB |
6041 | |
6042 | /* Cursor A & B regs */ | |
5efb3e28 | 6043 | #define _CURACNTR 0x70080 |
14b60391 JB |
6044 | /* Old style CUR*CNTR flags (desktop 8xx) */ |
6045 | #define CURSOR_ENABLE 0x80000000 | |
6046 | #define CURSOR_GAMMA_ENABLE 0x40000000 | |
dc41c154 | 6047 | #define CURSOR_STRIDE_SHIFT 28 |
5ee8ee86 | 6048 | #define CURSOR_STRIDE(x) ((ffs(x) - 9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */ |
14b60391 JB |
6049 | #define CURSOR_FORMAT_SHIFT 24 |
6050 | #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) | |
6051 | #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) | |
6052 | #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) | |
6053 | #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) | |
6054 | #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) | |
6055 | #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) | |
6056 | /* New style CUR*CNTR flags */ | |
b99b9ec1 VS |
6057 | #define MCURSOR_MODE 0x27 |
6058 | #define MCURSOR_MODE_DISABLE 0x00 | |
6059 | #define MCURSOR_MODE_128_32B_AX 0x02 | |
6060 | #define MCURSOR_MODE_256_32B_AX 0x03 | |
6061 | #define MCURSOR_MODE_64_32B_AX 0x07 | |
6062 | #define MCURSOR_MODE_128_ARGB_AX ((1 << 5) | MCURSOR_MODE_128_32B_AX) | |
6063 | #define MCURSOR_MODE_256_ARGB_AX ((1 << 5) | MCURSOR_MODE_256_32B_AX) | |
6064 | #define MCURSOR_MODE_64_ARGB_AX ((1 << 5) | MCURSOR_MODE_64_32B_AX) | |
eade6c89 VS |
6065 | #define MCURSOR_PIPE_SELECT_MASK (0x3 << 28) |
6066 | #define MCURSOR_PIPE_SELECT_SHIFT 28 | |
d509e28b | 6067 | #define MCURSOR_PIPE_SELECT(pipe) ((pipe) << 28) |
585fb111 | 6068 | #define MCURSOR_GAMMA_ENABLE (1 << 26) |
5ee8ee86 PZ |
6069 | #define MCURSOR_PIPE_CSC_ENABLE (1 << 24) |
6070 | #define MCURSOR_ROTATE_180 (1 << 15) | |
b99b9ec1 | 6071 | #define MCURSOR_TRICKLE_FEED_DISABLE (1 << 14) |
5efb3e28 VS |
6072 | #define _CURABASE 0x70084 |
6073 | #define _CURAPOS 0x70088 | |
585fb111 JB |
6074 | #define CURSOR_POS_MASK 0x007FF |
6075 | #define CURSOR_POS_SIGN 0x8000 | |
6076 | #define CURSOR_X_SHIFT 0 | |
6077 | #define CURSOR_Y_SHIFT 16 | |
024faac7 VS |
6078 | #define CURSIZE _MMIO(0x700a0) /* 845/865 */ |
6079 | #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */ | |
6080 | #define CUR_FBC_CTL_EN (1 << 31) | |
a8ada068 | 6081 | #define _CURASURFLIVE 0x700ac /* g4x+ */ |
5efb3e28 VS |
6082 | #define _CURBCNTR 0x700c0 |
6083 | #define _CURBBASE 0x700c4 | |
6084 | #define _CURBPOS 0x700c8 | |
585fb111 | 6085 | |
65a21cd6 JB |
6086 | #define _CURBCNTR_IVB 0x71080 |
6087 | #define _CURBBASE_IVB 0x71084 | |
6088 | #define _CURBPOS_IVB 0x71088 | |
6089 | ||
f0f59a00 | 6090 | #define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \ |
5efb3e28 VS |
6091 | dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \ |
6092 | dev_priv->info.display_mmio_offset) | |
6093 | ||
6094 | #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR) | |
6095 | #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE) | |
6096 | #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS) | |
024faac7 | 6097 | #define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A) |
a8ada068 | 6098 | #define CURSURFLIVE(pipe) _CURSOR2(pipe, _CURASURFLIVE) |
c4a1d9e4 | 6099 | |
5efb3e28 VS |
6100 | #define CURSOR_A_OFFSET 0x70080 |
6101 | #define CURSOR_B_OFFSET 0x700c0 | |
6102 | #define CHV_CURSOR_C_OFFSET 0x700e0 | |
6103 | #define IVB_CURSOR_B_OFFSET 0x71080 | |
6104 | #define IVB_CURSOR_C_OFFSET 0x72080 | |
65a21cd6 | 6105 | |
585fb111 | 6106 | /* Display A control */ |
a57c774a | 6107 | #define _DSPACNTR 0x70180 |
5ee8ee86 | 6108 | #define DISPLAY_PLANE_ENABLE (1 << 31) |
585fb111 | 6109 | #define DISPLAY_PLANE_DISABLE 0 |
5ee8ee86 | 6110 | #define DISPPLANE_GAMMA_ENABLE (1 << 30) |
585fb111 | 6111 | #define DISPPLANE_GAMMA_DISABLE 0 |
5ee8ee86 PZ |
6112 | #define DISPPLANE_PIXFORMAT_MASK (0xf << 26) |
6113 | #define DISPPLANE_YUV422 (0x0 << 26) | |
6114 | #define DISPPLANE_8BPP (0x2 << 26) | |
6115 | #define DISPPLANE_BGRA555 (0x3 << 26) | |
6116 | #define DISPPLANE_BGRX555 (0x4 << 26) | |
6117 | #define DISPPLANE_BGRX565 (0x5 << 26) | |
6118 | #define DISPPLANE_BGRX888 (0x6 << 26) | |
6119 | #define DISPPLANE_BGRA888 (0x7 << 26) | |
6120 | #define DISPPLANE_RGBX101010 (0x8 << 26) | |
6121 | #define DISPPLANE_RGBA101010 (0x9 << 26) | |
6122 | #define DISPPLANE_BGRX101010 (0xa << 26) | |
6123 | #define DISPPLANE_RGBX161616 (0xc << 26) | |
6124 | #define DISPPLANE_RGBX888 (0xe << 26) | |
6125 | #define DISPPLANE_RGBA888 (0xf << 26) | |
6126 | #define DISPPLANE_STEREO_ENABLE (1 << 25) | |
585fb111 | 6127 | #define DISPPLANE_STEREO_DISABLE 0 |
5ee8ee86 | 6128 | #define DISPPLANE_PIPE_CSC_ENABLE (1 << 24) |
b24e7179 | 6129 | #define DISPPLANE_SEL_PIPE_SHIFT 24 |
5ee8ee86 PZ |
6130 | #define DISPPLANE_SEL_PIPE_MASK (3 << DISPPLANE_SEL_PIPE_SHIFT) |
6131 | #define DISPPLANE_SEL_PIPE(pipe) ((pipe) << DISPPLANE_SEL_PIPE_SHIFT) | |
6132 | #define DISPPLANE_SRC_KEY_ENABLE (1 << 22) | |
585fb111 | 6133 | #define DISPPLANE_SRC_KEY_DISABLE 0 |
5ee8ee86 | 6134 | #define DISPPLANE_LINE_DOUBLE (1 << 20) |
585fb111 JB |
6135 | #define DISPPLANE_NO_LINE_DOUBLE 0 |
6136 | #define DISPPLANE_STEREO_POLARITY_FIRST 0 | |
5ee8ee86 PZ |
6137 | #define DISPPLANE_STEREO_POLARITY_SECOND (1 << 18) |
6138 | #define DISPPLANE_ALPHA_PREMULTIPLY (1 << 16) /* CHV pipe B */ | |
6139 | #define DISPPLANE_ROTATE_180 (1 << 15) | |
6140 | #define DISPPLANE_TRICKLE_FEED_DISABLE (1 << 14) /* Ironlake */ | |
6141 | #define DISPPLANE_TILED (1 << 10) | |
6142 | #define DISPPLANE_MIRROR (1 << 8) /* CHV pipe B */ | |
a57c774a AK |
6143 | #define _DSPAADDR 0x70184 |
6144 | #define _DSPASTRIDE 0x70188 | |
6145 | #define _DSPAPOS 0x7018C /* reserved */ | |
6146 | #define _DSPASIZE 0x70190 | |
6147 | #define _DSPASURF 0x7019C /* 965+ only */ | |
6148 | #define _DSPATILEOFF 0x701A4 /* 965+ only */ | |
6149 | #define _DSPAOFFSET 0x701A4 /* HSW */ | |
6150 | #define _DSPASURFLIVE 0x701AC | |
6151 | ||
f0f59a00 VS |
6152 | #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR) |
6153 | #define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR) | |
6154 | #define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE) | |
6155 | #define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS) | |
6156 | #define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE) | |
6157 | #define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF) | |
6158 | #define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF) | |
6159 | #define DSPLINOFF(plane) DSPADDR(plane) | |
6160 | #define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET) | |
6161 | #define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE) | |
5eddb70b | 6162 | |
c14b0485 VS |
6163 | /* CHV pipe B blender and primary plane */ |
6164 | #define _CHV_BLEND_A 0x60a00 | |
5ee8ee86 PZ |
6165 | #define CHV_BLEND_LEGACY (0 << 30) |
6166 | #define CHV_BLEND_ANDROID (1 << 30) | |
6167 | #define CHV_BLEND_MPO (2 << 30) | |
6168 | #define CHV_BLEND_MASK (3 << 30) | |
c14b0485 VS |
6169 | #define _CHV_CANVAS_A 0x60a04 |
6170 | #define _PRIMPOS_A 0x60a08 | |
6171 | #define _PRIMSIZE_A 0x60a0c | |
6172 | #define _PRIMCNSTALPHA_A 0x60a10 | |
5ee8ee86 | 6173 | #define PRIM_CONST_ALPHA_ENABLE (1 << 31) |
c14b0485 | 6174 | |
f0f59a00 VS |
6175 | #define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A) |
6176 | #define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A) | |
6177 | #define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A) | |
6178 | #define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A) | |
6179 | #define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A) | |
c14b0485 | 6180 | |
446f2545 AR |
6181 | /* Display/Sprite base address macros */ |
6182 | #define DISP_BASEADDR_MASK (0xfffff000) | |
9e8789ec PZ |
6183 | #define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK) |
6184 | #define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK) | |
446f2545 | 6185 | |
85fa792b VS |
6186 | /* |
6187 | * VBIOS flags | |
6188 | * gen2: | |
6189 | * [00:06] alm,mgm | |
6190 | * [10:16] all | |
6191 | * [30:32] alm,mgm | |
6192 | * gen3+: | |
6193 | * [00:0f] all | |
6194 | * [10:1f] all | |
6195 | * [30:32] all | |
6196 | */ | |
f0f59a00 VS |
6197 | #define SWF0(i) _MMIO(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4) |
6198 | #define SWF1(i) _MMIO(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4) | |
6199 | #define SWF3(i) _MMIO(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4) | |
6200 | #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) | |
585fb111 JB |
6201 | |
6202 | /* Pipe B */ | |
5c969aa7 DL |
6203 | #define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000) |
6204 | #define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008) | |
6205 | #define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024) | |
25a2e2d0 VS |
6206 | #define _PIPEBFRAMEHIGH 0x71040 |
6207 | #define _PIPEBFRAMEPIXEL 0x71044 | |
fd8f507c VS |
6208 | #define _PIPEB_FRMCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71040) |
6209 | #define _PIPEB_FLIPCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71044) | |
9880b7a5 | 6210 | |
585fb111 JB |
6211 | |
6212 | /* Display B control */ | |
5c969aa7 | 6213 | #define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180) |
5ee8ee86 | 6214 | #define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15) |
585fb111 JB |
6215 | #define DISPPLANE_ALPHA_TRANS_DISABLE 0 |
6216 | #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 | |
6217 | #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) | |
5c969aa7 DL |
6218 | #define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184) |
6219 | #define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188) | |
6220 | #define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C) | |
6221 | #define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190) | |
6222 | #define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C) | |
6223 | #define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4) | |
6224 | #define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4) | |
6225 | #define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC) | |
585fb111 | 6226 | |
b840d907 JB |
6227 | /* Sprite A control */ |
6228 | #define _DVSACNTR 0x72180 | |
5ee8ee86 PZ |
6229 | #define DVS_ENABLE (1 << 31) |
6230 | #define DVS_GAMMA_ENABLE (1 << 30) | |
6231 | #define DVS_YUV_RANGE_CORRECTION_DISABLE (1 << 27) | |
6232 | #define DVS_PIXFORMAT_MASK (3 << 25) | |
6233 | #define DVS_FORMAT_YUV422 (0 << 25) | |
6234 | #define DVS_FORMAT_RGBX101010 (1 << 25) | |
6235 | #define DVS_FORMAT_RGBX888 (2 << 25) | |
6236 | #define DVS_FORMAT_RGBX161616 (3 << 25) | |
6237 | #define DVS_PIPE_CSC_ENABLE (1 << 24) | |
6238 | #define DVS_SOURCE_KEY (1 << 22) | |
6239 | #define DVS_RGB_ORDER_XBGR (1 << 20) | |
6240 | #define DVS_YUV_FORMAT_BT709 (1 << 18) | |
6241 | #define DVS_YUV_BYTE_ORDER_MASK (3 << 16) | |
6242 | #define DVS_YUV_ORDER_YUYV (0 << 16) | |
6243 | #define DVS_YUV_ORDER_UYVY (1 << 16) | |
6244 | #define DVS_YUV_ORDER_YVYU (2 << 16) | |
6245 | #define DVS_YUV_ORDER_VYUY (3 << 16) | |
6246 | #define DVS_ROTATE_180 (1 << 15) | |
6247 | #define DVS_DEST_KEY (1 << 2) | |
6248 | #define DVS_TRICKLE_FEED_DISABLE (1 << 14) | |
6249 | #define DVS_TILED (1 << 10) | |
b840d907 JB |
6250 | #define _DVSALINOFF 0x72184 |
6251 | #define _DVSASTRIDE 0x72188 | |
6252 | #define _DVSAPOS 0x7218c | |
6253 | #define _DVSASIZE 0x72190 | |
6254 | #define _DVSAKEYVAL 0x72194 | |
6255 | #define _DVSAKEYMSK 0x72198 | |
6256 | #define _DVSASURF 0x7219c | |
6257 | #define _DVSAKEYMAXVAL 0x721a0 | |
6258 | #define _DVSATILEOFF 0x721a4 | |
6259 | #define _DVSASURFLIVE 0x721ac | |
6260 | #define _DVSASCALE 0x72204 | |
5ee8ee86 PZ |
6261 | #define DVS_SCALE_ENABLE (1 << 31) |
6262 | #define DVS_FILTER_MASK (3 << 29) | |
6263 | #define DVS_FILTER_MEDIUM (0 << 29) | |
6264 | #define DVS_FILTER_ENHANCING (1 << 29) | |
6265 | #define DVS_FILTER_SOFTENING (2 << 29) | |
6266 | #define DVS_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */ | |
6267 | #define DVS_VERTICAL_OFFSET_ENABLE (1 << 27) | |
b840d907 JB |
6268 | #define _DVSAGAMC 0x72300 |
6269 | ||
6270 | #define _DVSBCNTR 0x73180 | |
6271 | #define _DVSBLINOFF 0x73184 | |
6272 | #define _DVSBSTRIDE 0x73188 | |
6273 | #define _DVSBPOS 0x7318c | |
6274 | #define _DVSBSIZE 0x73190 | |
6275 | #define _DVSBKEYVAL 0x73194 | |
6276 | #define _DVSBKEYMSK 0x73198 | |
6277 | #define _DVSBSURF 0x7319c | |
6278 | #define _DVSBKEYMAXVAL 0x731a0 | |
6279 | #define _DVSBTILEOFF 0x731a4 | |
6280 | #define _DVSBSURFLIVE 0x731ac | |
6281 | #define _DVSBSCALE 0x73204 | |
6282 | #define _DVSBGAMC 0x73300 | |
6283 | ||
f0f59a00 VS |
6284 | #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) |
6285 | #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) | |
6286 | #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) | |
6287 | #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS) | |
6288 | #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF) | |
6289 | #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) | |
6290 | #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE) | |
6291 | #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE) | |
6292 | #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) | |
6293 | #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) | |
6294 | #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) | |
6295 | #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) | |
b840d907 JB |
6296 | |
6297 | #define _SPRA_CTL 0x70280 | |
5ee8ee86 PZ |
6298 | #define SPRITE_ENABLE (1 << 31) |
6299 | #define SPRITE_GAMMA_ENABLE (1 << 30) | |
6300 | #define SPRITE_YUV_RANGE_CORRECTION_DISABLE (1 << 28) | |
6301 | #define SPRITE_PIXFORMAT_MASK (7 << 25) | |
6302 | #define SPRITE_FORMAT_YUV422 (0 << 25) | |
6303 | #define SPRITE_FORMAT_RGBX101010 (1 << 25) | |
6304 | #define SPRITE_FORMAT_RGBX888 (2 << 25) | |
6305 | #define SPRITE_FORMAT_RGBX161616 (3 << 25) | |
6306 | #define SPRITE_FORMAT_YUV444 (4 << 25) | |
6307 | #define SPRITE_FORMAT_XR_BGR101010 (5 << 25) /* Extended range */ | |
6308 | #define SPRITE_PIPE_CSC_ENABLE (1 << 24) | |
6309 | #define SPRITE_SOURCE_KEY (1 << 22) | |
6310 | #define SPRITE_RGB_ORDER_RGBX (1 << 20) /* only for 888 and 161616 */ | |
6311 | #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1 << 19) | |
6312 | #define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18) /* 0 is BT601 */ | |
6313 | #define SPRITE_YUV_BYTE_ORDER_MASK (3 << 16) | |
6314 | #define SPRITE_YUV_ORDER_YUYV (0 << 16) | |
6315 | #define SPRITE_YUV_ORDER_UYVY (1 << 16) | |
6316 | #define SPRITE_YUV_ORDER_YVYU (2 << 16) | |
6317 | #define SPRITE_YUV_ORDER_VYUY (3 << 16) | |
6318 | #define SPRITE_ROTATE_180 (1 << 15) | |
6319 | #define SPRITE_TRICKLE_FEED_DISABLE (1 << 14) | |
6320 | #define SPRITE_INT_GAMMA_ENABLE (1 << 13) | |
6321 | #define SPRITE_TILED (1 << 10) | |
6322 | #define SPRITE_DEST_KEY (1 << 2) | |
b840d907 JB |
6323 | #define _SPRA_LINOFF 0x70284 |
6324 | #define _SPRA_STRIDE 0x70288 | |
6325 | #define _SPRA_POS 0x7028c | |
6326 | #define _SPRA_SIZE 0x70290 | |
6327 | #define _SPRA_KEYVAL 0x70294 | |
6328 | #define _SPRA_KEYMSK 0x70298 | |
6329 | #define _SPRA_SURF 0x7029c | |
6330 | #define _SPRA_KEYMAX 0x702a0 | |
6331 | #define _SPRA_TILEOFF 0x702a4 | |
c54173a8 | 6332 | #define _SPRA_OFFSET 0x702a4 |
32ae46bf | 6333 | #define _SPRA_SURFLIVE 0x702ac |
b840d907 | 6334 | #define _SPRA_SCALE 0x70304 |
5ee8ee86 PZ |
6335 | #define SPRITE_SCALE_ENABLE (1 << 31) |
6336 | #define SPRITE_FILTER_MASK (3 << 29) | |
6337 | #define SPRITE_FILTER_MEDIUM (0 << 29) | |
6338 | #define SPRITE_FILTER_ENHANCING (1 << 29) | |
6339 | #define SPRITE_FILTER_SOFTENING (2 << 29) | |
6340 | #define SPRITE_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */ | |
6341 | #define SPRITE_VERTICAL_OFFSET_ENABLE (1 << 27) | |
b840d907 JB |
6342 | #define _SPRA_GAMC 0x70400 |
6343 | ||
6344 | #define _SPRB_CTL 0x71280 | |
6345 | #define _SPRB_LINOFF 0x71284 | |
6346 | #define _SPRB_STRIDE 0x71288 | |
6347 | #define _SPRB_POS 0x7128c | |
6348 | #define _SPRB_SIZE 0x71290 | |
6349 | #define _SPRB_KEYVAL 0x71294 | |
6350 | #define _SPRB_KEYMSK 0x71298 | |
6351 | #define _SPRB_SURF 0x7129c | |
6352 | #define _SPRB_KEYMAX 0x712a0 | |
6353 | #define _SPRB_TILEOFF 0x712a4 | |
c54173a8 | 6354 | #define _SPRB_OFFSET 0x712a4 |
32ae46bf | 6355 | #define _SPRB_SURFLIVE 0x712ac |
b840d907 JB |
6356 | #define _SPRB_SCALE 0x71304 |
6357 | #define _SPRB_GAMC 0x71400 | |
6358 | ||
f0f59a00 VS |
6359 | #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL) |
6360 | #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) | |
6361 | #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) | |
6362 | #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS) | |
6363 | #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) | |
6364 | #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) | |
6365 | #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) | |
6366 | #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF) | |
6367 | #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) | |
6368 | #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) | |
6369 | #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) | |
6370 | #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) | |
6371 | #define SPRGAMC(pipe) _MMIO_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) | |
6372 | #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) | |
b840d907 | 6373 | |
921c3b67 | 6374 | #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) |
5ee8ee86 PZ |
6375 | #define SP_ENABLE (1 << 31) |
6376 | #define SP_GAMMA_ENABLE (1 << 30) | |
6377 | #define SP_PIXFORMAT_MASK (0xf << 26) | |
6378 | #define SP_FORMAT_YUV422 (0 << 26) | |
6379 | #define SP_FORMAT_BGR565 (5 << 26) | |
6380 | #define SP_FORMAT_BGRX8888 (6 << 26) | |
6381 | #define SP_FORMAT_BGRA8888 (7 << 26) | |
6382 | #define SP_FORMAT_RGBX1010102 (8 << 26) | |
6383 | #define SP_FORMAT_RGBA1010102 (9 << 26) | |
6384 | #define SP_FORMAT_RGBX8888 (0xe << 26) | |
6385 | #define SP_FORMAT_RGBA8888 (0xf << 26) | |
6386 | #define SP_ALPHA_PREMULTIPLY (1 << 23) /* CHV pipe B */ | |
6387 | #define SP_SOURCE_KEY (1 << 22) | |
6388 | #define SP_YUV_FORMAT_BT709 (1 << 18) | |
6389 | #define SP_YUV_BYTE_ORDER_MASK (3 << 16) | |
6390 | #define SP_YUV_ORDER_YUYV (0 << 16) | |
6391 | #define SP_YUV_ORDER_UYVY (1 << 16) | |
6392 | #define SP_YUV_ORDER_YVYU (2 << 16) | |
6393 | #define SP_YUV_ORDER_VYUY (3 << 16) | |
6394 | #define SP_ROTATE_180 (1 << 15) | |
6395 | #define SP_TILED (1 << 10) | |
6396 | #define SP_MIRROR (1 << 8) /* CHV pipe B */ | |
921c3b67 VS |
6397 | #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) |
6398 | #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) | |
6399 | #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) | |
6400 | #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) | |
6401 | #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194) | |
6402 | #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) | |
6403 | #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) | |
6404 | #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) | |
6405 | #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) | |
6406 | #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) | |
5ee8ee86 | 6407 | #define SP_CONST_ALPHA_ENABLE (1 << 31) |
5deae919 VS |
6408 | #define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0) |
6409 | #define SP_CONTRAST(x) ((x) << 18) /* u3.6 */ | |
6410 | #define SP_BRIGHTNESS(x) ((x) & 0xff) /* s8 */ | |
6411 | #define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4) | |
6412 | #define SP_SH_SIN(x) (((x) & 0x7ff) << 16) /* s4.7 */ | |
6413 | #define SP_SH_COS(x) (x) /* u3.7 */ | |
921c3b67 VS |
6414 | #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4) |
6415 | ||
6416 | #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) | |
6417 | #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) | |
6418 | #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) | |
6419 | #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) | |
6420 | #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) | |
6421 | #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) | |
6422 | #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) | |
6423 | #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) | |
6424 | #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) | |
6425 | #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) | |
6426 | #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) | |
5deae919 VS |
6427 | #define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0) |
6428 | #define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4) | |
921c3b67 | 6429 | #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4) |
7f1f3851 | 6430 | |
83c04a62 VS |
6431 | #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \ |
6432 | _MMIO_PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b)) | |
6433 | ||
6434 | #define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR) | |
6435 | #define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF) | |
6436 | #define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE) | |
6437 | #define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS) | |
6438 | #define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE) | |
6439 | #define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL) | |
6440 | #define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK) | |
6441 | #define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF) | |
6442 | #define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL) | |
6443 | #define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF) | |
6444 | #define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA) | |
5deae919 VS |
6445 | #define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0) |
6446 | #define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1) | |
83c04a62 | 6447 | #define SPGAMC(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) |
7f1f3851 | 6448 | |
6ca2aeb2 VS |
6449 | /* |
6450 | * CHV pipe B sprite CSC | |
6451 | * | |
6452 | * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff| | |
6453 | * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff| | |
6454 | * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff| | |
6455 | */ | |
83c04a62 VS |
6456 | #define _MMIO_CHV_SPCSC(plane_id, reg) \ |
6457 | _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg)) | |
6458 | ||
6459 | #define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900) | |
6460 | #define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904) | |
6461 | #define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908) | |
6ca2aeb2 VS |
6462 | #define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */ |
6463 | #define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */ | |
6464 | ||
83c04a62 VS |
6465 | #define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c) |
6466 | #define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910) | |
6467 | #define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914) | |
6468 | #define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918) | |
6469 | #define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c) | |
6ca2aeb2 VS |
6470 | #define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */ |
6471 | #define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */ | |
6472 | ||
83c04a62 VS |
6473 | #define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920) |
6474 | #define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924) | |
6475 | #define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928) | |
6ca2aeb2 VS |
6476 | #define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */ |
6477 | #define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */ | |
6478 | ||
83c04a62 VS |
6479 | #define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c) |
6480 | #define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930) | |
6481 | #define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934) | |
6ca2aeb2 VS |
6482 | #define SPCSC_OMAX(x) ((x) << 16) /* u10 */ |
6483 | #define SPCSC_OMIN(x) ((x) << 0) /* u10 */ | |
6484 | ||
70d21f0e DL |
6485 | /* Skylake plane registers */ |
6486 | ||
6487 | #define _PLANE_CTL_1_A 0x70180 | |
6488 | #define _PLANE_CTL_2_A 0x70280 | |
6489 | #define _PLANE_CTL_3_A 0x70380 | |
6490 | #define PLANE_CTL_ENABLE (1 << 31) | |
4036c78c | 6491 | #define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-GLK */ |
c8624ede | 6492 | #define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE (1 << 28) |
b5972776 JA |
6493 | /* |
6494 | * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition | |
6495 | * expanded to include bit 23 as well. However, the shift-24 based values | |
6496 | * correctly map to the same formats in ICL, as long as bit 23 is set to 0 | |
6497 | */ | |
70d21f0e | 6498 | #define PLANE_CTL_FORMAT_MASK (0xf << 24) |
5ee8ee86 PZ |
6499 | #define PLANE_CTL_FORMAT_YUV422 (0 << 24) |
6500 | #define PLANE_CTL_FORMAT_NV12 (1 << 24) | |
6501 | #define PLANE_CTL_FORMAT_XRGB_2101010 (2 << 24) | |
6502 | #define PLANE_CTL_FORMAT_XRGB_8888 (4 << 24) | |
6503 | #define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24) | |
6504 | #define PLANE_CTL_FORMAT_AYUV (8 << 24) | |
6505 | #define PLANE_CTL_FORMAT_INDEXED (12 << 24) | |
6506 | #define PLANE_CTL_FORMAT_RGB_565 (14 << 24) | |
b5972776 | 6507 | #define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23) |
4036c78c | 6508 | #define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) /* Pre-GLK */ |
dc2a41b4 | 6509 | #define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21) |
5ee8ee86 PZ |
6510 | #define PLANE_CTL_KEY_ENABLE_SOURCE (1 << 21) |
6511 | #define PLANE_CTL_KEY_ENABLE_DESTINATION (2 << 21) | |
70d21f0e DL |
6512 | #define PLANE_CTL_ORDER_BGRX (0 << 20) |
6513 | #define PLANE_CTL_ORDER_RGBX (1 << 20) | |
b0f5c0ba | 6514 | #define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18) |
70d21f0e | 6515 | #define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16) |
5ee8ee86 PZ |
6516 | #define PLANE_CTL_YUV422_YUYV (0 << 16) |
6517 | #define PLANE_CTL_YUV422_UYVY (1 << 16) | |
6518 | #define PLANE_CTL_YUV422_YVYU (2 << 16) | |
6519 | #define PLANE_CTL_YUV422_VYUY (3 << 16) | |
70d21f0e DL |
6520 | #define PLANE_CTL_DECOMPRESSION_ENABLE (1 << 15) |
6521 | #define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14) | |
4036c78c | 6522 | #define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /* Pre-GLK */ |
70d21f0e | 6523 | #define PLANE_CTL_TILED_MASK (0x7 << 10) |
5ee8ee86 PZ |
6524 | #define PLANE_CTL_TILED_LINEAR (0 << 10) |
6525 | #define PLANE_CTL_TILED_X (1 << 10) | |
6526 | #define PLANE_CTL_TILED_Y (4 << 10) | |
6527 | #define PLANE_CTL_TILED_YF (5 << 10) | |
6528 | #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8) | |
4036c78c | 6529 | #define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */ |
5ee8ee86 PZ |
6530 | #define PLANE_CTL_ALPHA_DISABLE (0 << 4) |
6531 | #define PLANE_CTL_ALPHA_SW_PREMULTIPLY (2 << 4) | |
6532 | #define PLANE_CTL_ALPHA_HW_PREMULTIPLY (3 << 4) | |
1447dde0 SJ |
6533 | #define PLANE_CTL_ROTATE_MASK 0x3 |
6534 | #define PLANE_CTL_ROTATE_0 0x0 | |
3b7a5119 | 6535 | #define PLANE_CTL_ROTATE_90 0x1 |
1447dde0 | 6536 | #define PLANE_CTL_ROTATE_180 0x2 |
3b7a5119 | 6537 | #define PLANE_CTL_ROTATE_270 0x3 |
70d21f0e DL |
6538 | #define _PLANE_STRIDE_1_A 0x70188 |
6539 | #define _PLANE_STRIDE_2_A 0x70288 | |
6540 | #define _PLANE_STRIDE_3_A 0x70388 | |
6541 | #define _PLANE_POS_1_A 0x7018c | |
6542 | #define _PLANE_POS_2_A 0x7028c | |
6543 | #define _PLANE_POS_3_A 0x7038c | |
6544 | #define _PLANE_SIZE_1_A 0x70190 | |
6545 | #define _PLANE_SIZE_2_A 0x70290 | |
6546 | #define _PLANE_SIZE_3_A 0x70390 | |
6547 | #define _PLANE_SURF_1_A 0x7019c | |
6548 | #define _PLANE_SURF_2_A 0x7029c | |
6549 | #define _PLANE_SURF_3_A 0x7039c | |
6550 | #define _PLANE_OFFSET_1_A 0x701a4 | |
6551 | #define _PLANE_OFFSET_2_A 0x702a4 | |
6552 | #define _PLANE_OFFSET_3_A 0x703a4 | |
dc2a41b4 DL |
6553 | #define _PLANE_KEYVAL_1_A 0x70194 |
6554 | #define _PLANE_KEYVAL_2_A 0x70294 | |
6555 | #define _PLANE_KEYMSK_1_A 0x70198 | |
6556 | #define _PLANE_KEYMSK_2_A 0x70298 | |
6557 | #define _PLANE_KEYMAX_1_A 0x701a0 | |
6558 | #define _PLANE_KEYMAX_2_A 0x702a0 | |
2e2adb05 VS |
6559 | #define _PLANE_AUX_DIST_1_A 0x701c0 |
6560 | #define _PLANE_AUX_DIST_2_A 0x702c0 | |
6561 | #define _PLANE_AUX_OFFSET_1_A 0x701c4 | |
6562 | #define _PLANE_AUX_OFFSET_2_A 0x702c4 | |
47f9ea8b ACO |
6563 | #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */ |
6564 | #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */ | |
6565 | #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ | |
077ef1f0 | 6566 | #define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */ |
c8624ede | 6567 | #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28) |
077ef1f0 | 6568 | #define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */ |
38f24f21 VS |
6569 | #define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17) |
6570 | #define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 (1 << 17) | |
6571 | #define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 (2 << 17) | |
6572 | #define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 (3 << 17) | |
6573 | #define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17) | |
47f9ea8b | 6574 | #define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13) |
4036c78c JA |
6575 | #define PLANE_COLOR_ALPHA_MASK (0x3 << 4) |
6576 | #define PLANE_COLOR_ALPHA_DISABLE (0 << 4) | |
6577 | #define PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4) | |
6578 | #define PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4) | |
8211bd5b DL |
6579 | #define _PLANE_BUF_CFG_1_A 0x7027c |
6580 | #define _PLANE_BUF_CFG_2_A 0x7037c | |
2cd601c6 CK |
6581 | #define _PLANE_NV12_BUF_CFG_1_A 0x70278 |
6582 | #define _PLANE_NV12_BUF_CFG_2_A 0x70378 | |
70d21f0e | 6583 | |
47f9ea8b | 6584 | |
70d21f0e DL |
6585 | #define _PLANE_CTL_1_B 0x71180 |
6586 | #define _PLANE_CTL_2_B 0x71280 | |
6587 | #define _PLANE_CTL_3_B 0x71380 | |
6588 | #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) | |
6589 | #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) | |
6590 | #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B) | |
6591 | #define PLANE_CTL(pipe, plane) \ | |
f0f59a00 | 6592 | _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) |
70d21f0e DL |
6593 | |
6594 | #define _PLANE_STRIDE_1_B 0x71188 | |
6595 | #define _PLANE_STRIDE_2_B 0x71288 | |
6596 | #define _PLANE_STRIDE_3_B 0x71388 | |
6597 | #define _PLANE_STRIDE_1(pipe) \ | |
6598 | _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) | |
6599 | #define _PLANE_STRIDE_2(pipe) \ | |
6600 | _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) | |
6601 | #define _PLANE_STRIDE_3(pipe) \ | |
6602 | _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B) | |
6603 | #define PLANE_STRIDE(pipe, plane) \ | |
f0f59a00 | 6604 | _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) |
70d21f0e DL |
6605 | |
6606 | #define _PLANE_POS_1_B 0x7118c | |
6607 | #define _PLANE_POS_2_B 0x7128c | |
6608 | #define _PLANE_POS_3_B 0x7138c | |
6609 | #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) | |
6610 | #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) | |
6611 | #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B) | |
6612 | #define PLANE_POS(pipe, plane) \ | |
f0f59a00 | 6613 | _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) |
70d21f0e DL |
6614 | |
6615 | #define _PLANE_SIZE_1_B 0x71190 | |
6616 | #define _PLANE_SIZE_2_B 0x71290 | |
6617 | #define _PLANE_SIZE_3_B 0x71390 | |
6618 | #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) | |
6619 | #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) | |
6620 | #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B) | |
6621 | #define PLANE_SIZE(pipe, plane) \ | |
f0f59a00 | 6622 | _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) |
70d21f0e DL |
6623 | |
6624 | #define _PLANE_SURF_1_B 0x7119c | |
6625 | #define _PLANE_SURF_2_B 0x7129c | |
6626 | #define _PLANE_SURF_3_B 0x7139c | |
6627 | #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) | |
6628 | #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) | |
6629 | #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) | |
6630 | #define PLANE_SURF(pipe, plane) \ | |
f0f59a00 | 6631 | _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) |
70d21f0e DL |
6632 | |
6633 | #define _PLANE_OFFSET_1_B 0x711a4 | |
6634 | #define _PLANE_OFFSET_2_B 0x712a4 | |
6635 | #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B) | |
6636 | #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) | |
6637 | #define PLANE_OFFSET(pipe, plane) \ | |
f0f59a00 | 6638 | _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe)) |
70d21f0e | 6639 | |
dc2a41b4 DL |
6640 | #define _PLANE_KEYVAL_1_B 0x71194 |
6641 | #define _PLANE_KEYVAL_2_B 0x71294 | |
6642 | #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B) | |
6643 | #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) | |
6644 | #define PLANE_KEYVAL(pipe, plane) \ | |
f0f59a00 | 6645 | _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) |
dc2a41b4 DL |
6646 | |
6647 | #define _PLANE_KEYMSK_1_B 0x71198 | |
6648 | #define _PLANE_KEYMSK_2_B 0x71298 | |
6649 | #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B) | |
6650 | #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) | |
6651 | #define PLANE_KEYMSK(pipe, plane) \ | |
f0f59a00 | 6652 | _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe)) |
dc2a41b4 DL |
6653 | |
6654 | #define _PLANE_KEYMAX_1_B 0x711a0 | |
6655 | #define _PLANE_KEYMAX_2_B 0x712a0 | |
6656 | #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B) | |
6657 | #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) | |
6658 | #define PLANE_KEYMAX(pipe, plane) \ | |
f0f59a00 | 6659 | _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe)) |
dc2a41b4 | 6660 | |
8211bd5b DL |
6661 | #define _PLANE_BUF_CFG_1_B 0x7127c |
6662 | #define _PLANE_BUF_CFG_2_B 0x7137c | |
37cde11b MK |
6663 | #define SKL_DDB_ENTRY_MASK 0x3FF |
6664 | #define ICL_DDB_ENTRY_MASK 0x7FF | |
6665 | #define DDB_ENTRY_END_SHIFT 16 | |
8211bd5b DL |
6666 | #define _PLANE_BUF_CFG_1(pipe) \ |
6667 | _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B) | |
6668 | #define _PLANE_BUF_CFG_2(pipe) \ | |
6669 | _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) | |
6670 | #define PLANE_BUF_CFG(pipe, plane) \ | |
f0f59a00 | 6671 | _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe)) |
8211bd5b | 6672 | |
2cd601c6 CK |
6673 | #define _PLANE_NV12_BUF_CFG_1_B 0x71278 |
6674 | #define _PLANE_NV12_BUF_CFG_2_B 0x71378 | |
6675 | #define _PLANE_NV12_BUF_CFG_1(pipe) \ | |
6676 | _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B) | |
6677 | #define _PLANE_NV12_BUF_CFG_2(pipe) \ | |
6678 | _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B) | |
6679 | #define PLANE_NV12_BUF_CFG(pipe, plane) \ | |
f0f59a00 | 6680 | _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe)) |
2cd601c6 | 6681 | |
2e2adb05 VS |
6682 | #define _PLANE_AUX_DIST_1_B 0x711c0 |
6683 | #define _PLANE_AUX_DIST_2_B 0x712c0 | |
6684 | #define _PLANE_AUX_DIST_1(pipe) \ | |
6685 | _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B) | |
6686 | #define _PLANE_AUX_DIST_2(pipe) \ | |
6687 | _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B) | |
6688 | #define PLANE_AUX_DIST(pipe, plane) \ | |
6689 | _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe)) | |
6690 | ||
6691 | #define _PLANE_AUX_OFFSET_1_B 0x711c4 | |
6692 | #define _PLANE_AUX_OFFSET_2_B 0x712c4 | |
6693 | #define _PLANE_AUX_OFFSET_1(pipe) \ | |
6694 | _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B) | |
6695 | #define _PLANE_AUX_OFFSET_2(pipe) \ | |
6696 | _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B) | |
6697 | #define PLANE_AUX_OFFSET(pipe, plane) \ | |
6698 | _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe)) | |
6699 | ||
47f9ea8b ACO |
6700 | #define _PLANE_COLOR_CTL_1_B 0x711CC |
6701 | #define _PLANE_COLOR_CTL_2_B 0x712CC | |
6702 | #define _PLANE_COLOR_CTL_3_B 0x713CC | |
6703 | #define _PLANE_COLOR_CTL_1(pipe) \ | |
6704 | _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B) | |
6705 | #define _PLANE_COLOR_CTL_2(pipe) \ | |
6706 | _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B) | |
6707 | #define PLANE_COLOR_CTL(pipe, plane) \ | |
6708 | _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe)) | |
6709 | ||
6710 | #/* SKL new cursor registers */ | |
8211bd5b DL |
6711 | #define _CUR_BUF_CFG_A 0x7017c |
6712 | #define _CUR_BUF_CFG_B 0x7117c | |
f0f59a00 | 6713 | #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) |
8211bd5b | 6714 | |
585fb111 | 6715 | /* VBIOS regs */ |
f0f59a00 | 6716 | #define VGACNTRL _MMIO(0x71400) |
585fb111 JB |
6717 | # define VGA_DISP_DISABLE (1 << 31) |
6718 | # define VGA_2X_MODE (1 << 30) | |
6719 | # define VGA_PIPE_B_SELECT (1 << 29) | |
6720 | ||
f0f59a00 | 6721 | #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400) |
766aa1c4 | 6722 | |
f2b115e6 | 6723 | /* Ironlake */ |
b9055052 | 6724 | |
f0f59a00 | 6725 | #define CPU_VGACNTRL _MMIO(0x41000) |
b9055052 | 6726 | |
f0f59a00 | 6727 | #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030) |
40bfd7a3 VS |
6728 | #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) |
6729 | #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */ | |
6730 | #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */ | |
6731 | #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */ | |
6732 | #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */ | |
6733 | #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */ | |
6734 | #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0) | |
6735 | #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0) | |
6736 | #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0) | |
6737 | #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0) | |
b9055052 ZW |
6738 | |
6739 | /* refresh rate hardware control */ | |
f0f59a00 | 6740 | #define RR_HW_CTL _MMIO(0x45300) |
b9055052 ZW |
6741 | #define RR_HW_LOW_POWER_FRAMES_MASK 0xff |
6742 | #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 | |
6743 | ||
f0f59a00 | 6744 | #define FDI_PLL_BIOS_0 _MMIO(0x46000) |
021357ac | 6745 | #define FDI_PLL_FB_CLOCK_MASK 0xff |
f0f59a00 VS |
6746 | #define FDI_PLL_BIOS_1 _MMIO(0x46004) |
6747 | #define FDI_PLL_BIOS_2 _MMIO(0x46008) | |
6748 | #define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c) | |
6749 | #define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010) | |
6750 | #define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014) | |
b9055052 | 6751 | |
f0f59a00 | 6752 | #define PCH_3DCGDIS0 _MMIO(0x46020) |
8956c8bb EA |
6753 | # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) |
6754 | # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) | |
6755 | ||
f0f59a00 | 6756 | #define PCH_3DCGDIS1 _MMIO(0x46024) |
06f37751 EA |
6757 | # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) |
6758 | ||
f0f59a00 | 6759 | #define FDI_PLL_FREQ_CTL _MMIO(0x46030) |
5ee8ee86 | 6760 | #define FDI_PLL_FREQ_CHANGE_REQUEST (1 << 24) |
b9055052 ZW |
6761 | #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 |
6762 | #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff | |
6763 | ||
6764 | ||
a57c774a | 6765 | #define _PIPEA_DATA_M1 0x60030 |
5eddb70b | 6766 | #define PIPE_DATA_M1_OFFSET 0 |
a57c774a | 6767 | #define _PIPEA_DATA_N1 0x60034 |
5eddb70b | 6768 | #define PIPE_DATA_N1_OFFSET 0 |
b9055052 | 6769 | |
a57c774a | 6770 | #define _PIPEA_DATA_M2 0x60038 |
5eddb70b | 6771 | #define PIPE_DATA_M2_OFFSET 0 |
a57c774a | 6772 | #define _PIPEA_DATA_N2 0x6003c |
5eddb70b | 6773 | #define PIPE_DATA_N2_OFFSET 0 |
b9055052 | 6774 | |
a57c774a | 6775 | #define _PIPEA_LINK_M1 0x60040 |
5eddb70b | 6776 | #define PIPE_LINK_M1_OFFSET 0 |
a57c774a | 6777 | #define _PIPEA_LINK_N1 0x60044 |
5eddb70b | 6778 | #define PIPE_LINK_N1_OFFSET 0 |
b9055052 | 6779 | |
a57c774a | 6780 | #define _PIPEA_LINK_M2 0x60048 |
5eddb70b | 6781 | #define PIPE_LINK_M2_OFFSET 0 |
a57c774a | 6782 | #define _PIPEA_LINK_N2 0x6004c |
5eddb70b | 6783 | #define PIPE_LINK_N2_OFFSET 0 |
b9055052 ZW |
6784 | |
6785 | /* PIPEB timing regs are same start from 0x61000 */ | |
6786 | ||
a57c774a AK |
6787 | #define _PIPEB_DATA_M1 0x61030 |
6788 | #define _PIPEB_DATA_N1 0x61034 | |
6789 | #define _PIPEB_DATA_M2 0x61038 | |
6790 | #define _PIPEB_DATA_N2 0x6103c | |
6791 | #define _PIPEB_LINK_M1 0x61040 | |
6792 | #define _PIPEB_LINK_N1 0x61044 | |
6793 | #define _PIPEB_LINK_M2 0x61048 | |
6794 | #define _PIPEB_LINK_N2 0x6104c | |
6795 | ||
f0f59a00 VS |
6796 | #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1) |
6797 | #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1) | |
6798 | #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2) | |
6799 | #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2) | |
6800 | #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1) | |
6801 | #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1) | |
6802 | #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2) | |
6803 | #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2) | |
b9055052 ZW |
6804 | |
6805 | /* CPU panel fitter */ | |
9db4a9c7 JB |
6806 | /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ |
6807 | #define _PFA_CTL_1 0x68080 | |
6808 | #define _PFB_CTL_1 0x68880 | |
5ee8ee86 PZ |
6809 | #define PF_ENABLE (1 << 31) |
6810 | #define PF_PIPE_SEL_MASK_IVB (3 << 29) | |
6811 | #define PF_PIPE_SEL_IVB(pipe) ((pipe) << 29) | |
6812 | #define PF_FILTER_MASK (3 << 23) | |
6813 | #define PF_FILTER_PROGRAMMED (0 << 23) | |
6814 | #define PF_FILTER_MED_3x3 (1 << 23) | |
6815 | #define PF_FILTER_EDGE_ENHANCE (2 << 23) | |
6816 | #define PF_FILTER_EDGE_SOFTEN (3 << 23) | |
9db4a9c7 JB |
6817 | #define _PFA_WIN_SZ 0x68074 |
6818 | #define _PFB_WIN_SZ 0x68874 | |
6819 | #define _PFA_WIN_POS 0x68070 | |
6820 | #define _PFB_WIN_POS 0x68870 | |
6821 | #define _PFA_VSCALE 0x68084 | |
6822 | #define _PFB_VSCALE 0x68884 | |
6823 | #define _PFA_HSCALE 0x68090 | |
6824 | #define _PFB_HSCALE 0x68890 | |
6825 | ||
f0f59a00 VS |
6826 | #define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) |
6827 | #define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) | |
6828 | #define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) | |
6829 | #define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) | |
6830 | #define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) | |
b9055052 | 6831 | |
bd2e244f JB |
6832 | #define _PSA_CTL 0x68180 |
6833 | #define _PSB_CTL 0x68980 | |
5ee8ee86 | 6834 | #define PS_ENABLE (1 << 31) |
bd2e244f JB |
6835 | #define _PSA_WIN_SZ 0x68174 |
6836 | #define _PSB_WIN_SZ 0x68974 | |
6837 | #define _PSA_WIN_POS 0x68170 | |
6838 | #define _PSB_WIN_POS 0x68970 | |
6839 | ||
f0f59a00 VS |
6840 | #define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL) |
6841 | #define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ) | |
6842 | #define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS) | |
bd2e244f | 6843 | |
1c9a2d4a CK |
6844 | /* |
6845 | * Skylake scalers | |
6846 | */ | |
6847 | #define _PS_1A_CTRL 0x68180 | |
6848 | #define _PS_2A_CTRL 0x68280 | |
6849 | #define _PS_1B_CTRL 0x68980 | |
6850 | #define _PS_2B_CTRL 0x68A80 | |
6851 | #define _PS_1C_CTRL 0x69180 | |
6852 | #define PS_SCALER_EN (1 << 31) | |
6853 | #define PS_SCALER_MODE_MASK (3 << 28) | |
6854 | #define PS_SCALER_MODE_DYN (0 << 28) | |
6855 | #define PS_SCALER_MODE_HQ (1 << 28) | |
e6e1948c CK |
6856 | #define SKL_PS_SCALER_MODE_NV12 (2 << 28) |
6857 | #define PS_SCALER_MODE_PLANAR (1 << 29) | |
1c9a2d4a | 6858 | #define PS_PLANE_SEL_MASK (7 << 25) |
68d97538 | 6859 | #define PS_PLANE_SEL(plane) (((plane) + 1) << 25) |
1c9a2d4a CK |
6860 | #define PS_FILTER_MASK (3 << 23) |
6861 | #define PS_FILTER_MEDIUM (0 << 23) | |
6862 | #define PS_FILTER_EDGE_ENHANCE (2 << 23) | |
6863 | #define PS_FILTER_BILINEAR (3 << 23) | |
6864 | #define PS_VERT3TAP (1 << 21) | |
6865 | #define PS_VERT_INT_INVERT_FIELD1 (0 << 20) | |
6866 | #define PS_VERT_INT_INVERT_FIELD0 (1 << 20) | |
6867 | #define PS_PWRUP_PROGRESS (1 << 17) | |
6868 | #define PS_V_FILTER_BYPASS (1 << 8) | |
6869 | #define PS_VADAPT_EN (1 << 7) | |
6870 | #define PS_VADAPT_MODE_MASK (3 << 5) | |
6871 | #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5) | |
6872 | #define PS_VADAPT_MODE_MOD_ADAPT (1 << 5) | |
6873 | #define PS_VADAPT_MODE_MOST_ADAPT (3 << 5) | |
6874 | ||
6875 | #define _PS_PWR_GATE_1A 0x68160 | |
6876 | #define _PS_PWR_GATE_2A 0x68260 | |
6877 | #define _PS_PWR_GATE_1B 0x68960 | |
6878 | #define _PS_PWR_GATE_2B 0x68A60 | |
6879 | #define _PS_PWR_GATE_1C 0x69160 | |
6880 | #define PS_PWR_GATE_DIS_OVERRIDE (1 << 31) | |
6881 | #define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3) | |
6882 | #define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3) | |
6883 | #define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3) | |
6884 | #define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3) | |
6885 | #define PS_PWR_GATE_SLPEN_8 0 | |
6886 | #define PS_PWR_GATE_SLPEN_16 1 | |
6887 | #define PS_PWR_GATE_SLPEN_24 2 | |
6888 | #define PS_PWR_GATE_SLPEN_32 3 | |
6889 | ||
6890 | #define _PS_WIN_POS_1A 0x68170 | |
6891 | #define _PS_WIN_POS_2A 0x68270 | |
6892 | #define _PS_WIN_POS_1B 0x68970 | |
6893 | #define _PS_WIN_POS_2B 0x68A70 | |
6894 | #define _PS_WIN_POS_1C 0x69170 | |
6895 | ||
6896 | #define _PS_WIN_SZ_1A 0x68174 | |
6897 | #define _PS_WIN_SZ_2A 0x68274 | |
6898 | #define _PS_WIN_SZ_1B 0x68974 | |
6899 | #define _PS_WIN_SZ_2B 0x68A74 | |
6900 | #define _PS_WIN_SZ_1C 0x69174 | |
6901 | ||
6902 | #define _PS_VSCALE_1A 0x68184 | |
6903 | #define _PS_VSCALE_2A 0x68284 | |
6904 | #define _PS_VSCALE_1B 0x68984 | |
6905 | #define _PS_VSCALE_2B 0x68A84 | |
6906 | #define _PS_VSCALE_1C 0x69184 | |
6907 | ||
6908 | #define _PS_HSCALE_1A 0x68190 | |
6909 | #define _PS_HSCALE_2A 0x68290 | |
6910 | #define _PS_HSCALE_1B 0x68990 | |
6911 | #define _PS_HSCALE_2B 0x68A90 | |
6912 | #define _PS_HSCALE_1C 0x69190 | |
6913 | ||
6914 | #define _PS_VPHASE_1A 0x68188 | |
6915 | #define _PS_VPHASE_2A 0x68288 | |
6916 | #define _PS_VPHASE_1B 0x68988 | |
6917 | #define _PS_VPHASE_2B 0x68A88 | |
6918 | #define _PS_VPHASE_1C 0x69188 | |
0a59952b VS |
6919 | #define PS_Y_PHASE(x) ((x) << 16) |
6920 | #define PS_UV_RGB_PHASE(x) ((x) << 0) | |
6921 | #define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */ | |
6922 | #define PS_PHASE_TRIP (1 << 0) | |
1c9a2d4a CK |
6923 | |
6924 | #define _PS_HPHASE_1A 0x68194 | |
6925 | #define _PS_HPHASE_2A 0x68294 | |
6926 | #define _PS_HPHASE_1B 0x68994 | |
6927 | #define _PS_HPHASE_2B 0x68A94 | |
6928 | #define _PS_HPHASE_1C 0x69194 | |
6929 | ||
6930 | #define _PS_ECC_STAT_1A 0x681D0 | |
6931 | #define _PS_ECC_STAT_2A 0x682D0 | |
6932 | #define _PS_ECC_STAT_1B 0x689D0 | |
6933 | #define _PS_ECC_STAT_2B 0x68AD0 | |
6934 | #define _PS_ECC_STAT_1C 0x691D0 | |
6935 | ||
e67005e5 | 6936 | #define _ID(id, a, b) _PICK_EVEN(id, a, b) |
f0f59a00 | 6937 | #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \ |
1c9a2d4a CK |
6938 | _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \ |
6939 | _ID(id, _PS_1B_CTRL, _PS_2B_CTRL)) | |
f0f59a00 | 6940 | #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \ |
1c9a2d4a CK |
6941 | _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \ |
6942 | _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B)) | |
f0f59a00 | 6943 | #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \ |
1c9a2d4a CK |
6944 | _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \ |
6945 | _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B)) | |
f0f59a00 | 6946 | #define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \ |
1c9a2d4a CK |
6947 | _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \ |
6948 | _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B)) | |
f0f59a00 | 6949 | #define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \ |
1c9a2d4a CK |
6950 | _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \ |
6951 | _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B)) | |
f0f59a00 | 6952 | #define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \ |
1c9a2d4a CK |
6953 | _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \ |
6954 | _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B)) | |
f0f59a00 | 6955 | #define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \ |
1c9a2d4a CK |
6956 | _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \ |
6957 | _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B)) | |
f0f59a00 | 6958 | #define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \ |
1c9a2d4a CK |
6959 | _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \ |
6960 | _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B)) | |
f0f59a00 | 6961 | #define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \ |
1c9a2d4a | 6962 | _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \ |
9bca5d0c | 6963 | _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)) |
1c9a2d4a | 6964 | |
b9055052 | 6965 | /* legacy palette */ |
9db4a9c7 JB |
6966 | #define _LGC_PALETTE_A 0x4a000 |
6967 | #define _LGC_PALETTE_B 0x4a800 | |
f0f59a00 | 6968 | #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4) |
b9055052 | 6969 | |
42db64ef PZ |
6970 | #define _GAMMA_MODE_A 0x4a480 |
6971 | #define _GAMMA_MODE_B 0x4ac80 | |
f0f59a00 | 6972 | #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) |
42db64ef | 6973 | #define GAMMA_MODE_MODE_MASK (3 << 0) |
3eff4faa DV |
6974 | #define GAMMA_MODE_MODE_8BIT (0 << 0) |
6975 | #define GAMMA_MODE_MODE_10BIT (1 << 0) | |
6976 | #define GAMMA_MODE_MODE_12BIT (2 << 0) | |
42db64ef PZ |
6977 | #define GAMMA_MODE_MODE_SPLIT (3 << 0) |
6978 | ||
8337206d | 6979 | /* DMC/CSR */ |
f0f59a00 | 6980 | #define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4) |
6fb403de MK |
6981 | #define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0 |
6982 | #define CSR_HTP_ADDR_SKL 0x00500034 | |
f0f59a00 VS |
6983 | #define CSR_SSP_BASE _MMIO(0x8F074) |
6984 | #define CSR_HTP_SKL _MMIO(0x8F004) | |
6985 | #define CSR_LAST_WRITE _MMIO(0x8F034) | |
6fb403de MK |
6986 | #define CSR_LAST_WRITE_VALUE 0xc003b400 |
6987 | /* MMIO address range for CSR program (0x80000 - 0x82FFF) */ | |
6988 | #define CSR_MMIO_START_RANGE 0x80000 | |
6989 | #define CSR_MMIO_END_RANGE 0x8FFFF | |
f0f59a00 VS |
6990 | #define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030) |
6991 | #define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C) | |
6992 | #define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038) | |
8337206d | 6993 | |
b9055052 ZW |
6994 | /* interrupts */ |
6995 | #define DE_MASTER_IRQ_CONTROL (1 << 31) | |
6996 | #define DE_SPRITEB_FLIP_DONE (1 << 29) | |
6997 | #define DE_SPRITEA_FLIP_DONE (1 << 28) | |
6998 | #define DE_PLANEB_FLIP_DONE (1 << 27) | |
6999 | #define DE_PLANEA_FLIP_DONE (1 << 26) | |
40da17c2 | 7000 | #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane))) |
b9055052 ZW |
7001 | #define DE_PCU_EVENT (1 << 25) |
7002 | #define DE_GTT_FAULT (1 << 24) | |
7003 | #define DE_POISON (1 << 23) | |
7004 | #define DE_PERFORM_COUNTER (1 << 22) | |
7005 | #define DE_PCH_EVENT (1 << 21) | |
7006 | #define DE_AUX_CHANNEL_A (1 << 20) | |
7007 | #define DE_DP_A_HOTPLUG (1 << 19) | |
7008 | #define DE_GSE (1 << 18) | |
7009 | #define DE_PIPEB_VBLANK (1 << 15) | |
7010 | #define DE_PIPEB_EVEN_FIELD (1 << 14) | |
7011 | #define DE_PIPEB_ODD_FIELD (1 << 13) | |
7012 | #define DE_PIPEB_LINE_COMPARE (1 << 12) | |
7013 | #define DE_PIPEB_VSYNC (1 << 11) | |
5b3a856b | 7014 | #define DE_PIPEB_CRC_DONE (1 << 10) |
b9055052 ZW |
7015 | #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) |
7016 | #define DE_PIPEA_VBLANK (1 << 7) | |
5ee8ee86 | 7017 | #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe))) |
b9055052 ZW |
7018 | #define DE_PIPEA_EVEN_FIELD (1 << 6) |
7019 | #define DE_PIPEA_ODD_FIELD (1 << 5) | |
7020 | #define DE_PIPEA_LINE_COMPARE (1 << 4) | |
7021 | #define DE_PIPEA_VSYNC (1 << 3) | |
5b3a856b | 7022 | #define DE_PIPEA_CRC_DONE (1 << 2) |
5ee8ee86 | 7023 | #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe))) |
b9055052 | 7024 | #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) |
5ee8ee86 | 7025 | #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe))) |
b9055052 | 7026 | |
b1f14ad0 | 7027 | /* More Ivybridge lolz */ |
5ee8ee86 PZ |
7028 | #define DE_ERR_INT_IVB (1 << 30) |
7029 | #define DE_GSE_IVB (1 << 29) | |
7030 | #define DE_PCH_EVENT_IVB (1 << 28) | |
7031 | #define DE_DP_A_HOTPLUG_IVB (1 << 27) | |
7032 | #define DE_AUX_CHANNEL_A_IVB (1 << 26) | |
7033 | #define DE_EDP_PSR_INT_HSW (1 << 19) | |
7034 | #define DE_SPRITEC_FLIP_DONE_IVB (1 << 14) | |
7035 | #define DE_PLANEC_FLIP_DONE_IVB (1 << 13) | |
7036 | #define DE_PIPEC_VBLANK_IVB (1 << 10) | |
7037 | #define DE_SPRITEB_FLIP_DONE_IVB (1 << 9) | |
7038 | #define DE_PLANEB_FLIP_DONE_IVB (1 << 8) | |
7039 | #define DE_PIPEB_VBLANK_IVB (1 << 5) | |
7040 | #define DE_SPRITEA_FLIP_DONE_IVB (1 << 4) | |
7041 | #define DE_PLANEA_FLIP_DONE_IVB (1 << 3) | |
7042 | #define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane))) | |
7043 | #define DE_PIPEA_VBLANK_IVB (1 << 0) | |
68d97538 | 7044 | #define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5)) |
b518421f | 7045 | |
f0f59a00 | 7046 | #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */ |
5ee8ee86 | 7047 | #define MASTER_INTERRUPT_ENABLE (1 << 31) |
7eea1ddf | 7048 | |
f0f59a00 VS |
7049 | #define DEISR _MMIO(0x44000) |
7050 | #define DEIMR _MMIO(0x44004) | |
7051 | #define DEIIR _MMIO(0x44008) | |
7052 | #define DEIER _MMIO(0x4400c) | |
b9055052 | 7053 | |
f0f59a00 VS |
7054 | #define GTISR _MMIO(0x44010) |
7055 | #define GTIMR _MMIO(0x44014) | |
7056 | #define GTIIR _MMIO(0x44018) | |
7057 | #define GTIER _MMIO(0x4401c) | |
b9055052 | 7058 | |
f0f59a00 | 7059 | #define GEN8_MASTER_IRQ _MMIO(0x44200) |
5ee8ee86 PZ |
7060 | #define GEN8_MASTER_IRQ_CONTROL (1 << 31) |
7061 | #define GEN8_PCU_IRQ (1 << 30) | |
7062 | #define GEN8_DE_PCH_IRQ (1 << 23) | |
7063 | #define GEN8_DE_MISC_IRQ (1 << 22) | |
7064 | #define GEN8_DE_PORT_IRQ (1 << 20) | |
7065 | #define GEN8_DE_PIPE_C_IRQ (1 << 18) | |
7066 | #define GEN8_DE_PIPE_B_IRQ (1 << 17) | |
7067 | #define GEN8_DE_PIPE_A_IRQ (1 << 16) | |
7068 | #define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe))) | |
7069 | #define GEN8_GT_VECS_IRQ (1 << 6) | |
7070 | #define GEN8_GT_GUC_IRQ (1 << 5) | |
7071 | #define GEN8_GT_PM_IRQ (1 << 4) | |
7072 | #define GEN8_GT_VCS2_IRQ (1 << 3) | |
7073 | #define GEN8_GT_VCS1_IRQ (1 << 2) | |
7074 | #define GEN8_GT_BCS_IRQ (1 << 1) | |
7075 | #define GEN8_GT_RCS_IRQ (1 << 0) | |
abd58f01 | 7076 | |
f0f59a00 VS |
7077 | #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which))) |
7078 | #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which))) | |
7079 | #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which))) | |
7080 | #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which))) | |
abd58f01 | 7081 | |
5ee8ee86 PZ |
7082 | #define GEN9_GUC_TO_HOST_INT_EVENT (1 << 31) |
7083 | #define GEN9_GUC_EXEC_ERROR_EVENT (1 << 30) | |
7084 | #define GEN9_GUC_DISPLAY_EVENT (1 << 29) | |
7085 | #define GEN9_GUC_SEMA_SIGNAL_EVENT (1 << 28) | |
7086 | #define GEN9_GUC_IOMMU_MSG_EVENT (1 << 27) | |
7087 | #define GEN9_GUC_DB_RING_EVENT (1 << 26) | |
7088 | #define GEN9_GUC_DMA_DONE_EVENT (1 << 25) | |
7089 | #define GEN9_GUC_FATAL_ERROR_EVENT (1 << 24) | |
7090 | #define GEN9_GUC_NOTIFICATION_EVENT (1 << 23) | |
26705e20 | 7091 | |
abd58f01 | 7092 | #define GEN8_RCS_IRQ_SHIFT 0 |
4df001d3 | 7093 | #define GEN8_BCS_IRQ_SHIFT 16 |
abd58f01 | 7094 | #define GEN8_VCS1_IRQ_SHIFT 0 |
4df001d3 | 7095 | #define GEN8_VCS2_IRQ_SHIFT 16 |
abd58f01 | 7096 | #define GEN8_VECS_IRQ_SHIFT 0 |
4df001d3 | 7097 | #define GEN8_WD_IRQ_SHIFT 16 |
abd58f01 | 7098 | |
f0f59a00 VS |
7099 | #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe))) |
7100 | #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe))) | |
7101 | #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe))) | |
7102 | #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe))) | |
38d83c96 | 7103 | #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31) |
abd58f01 BW |
7104 | #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29) |
7105 | #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28) | |
7106 | #define GEN8_PIPE_CURSOR_FAULT (1 << 10) | |
7107 | #define GEN8_PIPE_SPRITE_FAULT (1 << 9) | |
7108 | #define GEN8_PIPE_PRIMARY_FAULT (1 << 8) | |
7109 | #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5) | |
d0e1f1cb | 7110 | #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4) |
abd58f01 BW |
7111 | #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) |
7112 | #define GEN8_PIPE_VSYNC (1 << 1) | |
7113 | #define GEN8_PIPE_VBLANK (1 << 0) | |
770de83d | 7114 | #define GEN9_PIPE_CURSOR_FAULT (1 << 11) |
b21249c9 | 7115 | #define GEN9_PIPE_PLANE4_FAULT (1 << 10) |
770de83d DL |
7116 | #define GEN9_PIPE_PLANE3_FAULT (1 << 9) |
7117 | #define GEN9_PIPE_PLANE2_FAULT (1 << 8) | |
7118 | #define GEN9_PIPE_PLANE1_FAULT (1 << 7) | |
b21249c9 | 7119 | #define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6) |
770de83d DL |
7120 | #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5) |
7121 | #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4) | |
7122 | #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3) | |
68d97538 | 7123 | #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p))) |
30100f2b DV |
7124 | #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ |
7125 | (GEN8_PIPE_CURSOR_FAULT | \ | |
7126 | GEN8_PIPE_SPRITE_FAULT | \ | |
7127 | GEN8_PIPE_PRIMARY_FAULT) | |
770de83d DL |
7128 | #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \ |
7129 | (GEN9_PIPE_CURSOR_FAULT | \ | |
b21249c9 | 7130 | GEN9_PIPE_PLANE4_FAULT | \ |
770de83d DL |
7131 | GEN9_PIPE_PLANE3_FAULT | \ |
7132 | GEN9_PIPE_PLANE2_FAULT | \ | |
7133 | GEN9_PIPE_PLANE1_FAULT) | |
abd58f01 | 7134 | |
f0f59a00 VS |
7135 | #define GEN8_DE_PORT_ISR _MMIO(0x44440) |
7136 | #define GEN8_DE_PORT_IMR _MMIO(0x44444) | |
7137 | #define GEN8_DE_PORT_IIR _MMIO(0x44448) | |
7138 | #define GEN8_DE_PORT_IER _MMIO(0x4444c) | |
bb187e93 | 7139 | #define ICL_AUX_CHANNEL_E (1 << 29) |
a324fcac | 7140 | #define CNL_AUX_CHANNEL_F (1 << 28) |
88e04703 JB |
7141 | #define GEN9_AUX_CHANNEL_D (1 << 27) |
7142 | #define GEN9_AUX_CHANNEL_C (1 << 26) | |
7143 | #define GEN9_AUX_CHANNEL_B (1 << 25) | |
e0a20ad7 SS |
7144 | #define BXT_DE_PORT_HP_DDIC (1 << 5) |
7145 | #define BXT_DE_PORT_HP_DDIB (1 << 4) | |
7146 | #define BXT_DE_PORT_HP_DDIA (1 << 3) | |
7147 | #define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDIA | \ | |
7148 | BXT_DE_PORT_HP_DDIB | \ | |
7149 | BXT_DE_PORT_HP_DDIC) | |
7150 | #define GEN8_PORT_DP_A_HOTPLUG (1 << 3) | |
9e63743e | 7151 | #define BXT_DE_PORT_GMBUS (1 << 1) |
6d766f02 | 7152 | #define GEN8_AUX_CHANNEL_A (1 << 0) |
abd58f01 | 7153 | |
f0f59a00 VS |
7154 | #define GEN8_DE_MISC_ISR _MMIO(0x44460) |
7155 | #define GEN8_DE_MISC_IMR _MMIO(0x44464) | |
7156 | #define GEN8_DE_MISC_IIR _MMIO(0x44468) | |
7157 | #define GEN8_DE_MISC_IER _MMIO(0x4446c) | |
abd58f01 | 7158 | #define GEN8_DE_MISC_GSE (1 << 27) |
e04f7ece | 7159 | #define GEN8_DE_EDP_PSR (1 << 19) |
abd58f01 | 7160 | |
f0f59a00 VS |
7161 | #define GEN8_PCU_ISR _MMIO(0x444e0) |
7162 | #define GEN8_PCU_IMR _MMIO(0x444e4) | |
7163 | #define GEN8_PCU_IIR _MMIO(0x444e8) | |
7164 | #define GEN8_PCU_IER _MMIO(0x444ec) | |
abd58f01 | 7165 | |
df0d28c1 DP |
7166 | #define GEN11_GU_MISC_ISR _MMIO(0x444f0) |
7167 | #define GEN11_GU_MISC_IMR _MMIO(0x444f4) | |
7168 | #define GEN11_GU_MISC_IIR _MMIO(0x444f8) | |
7169 | #define GEN11_GU_MISC_IER _MMIO(0x444fc) | |
7170 | #define GEN11_GU_MISC_GSE (1 << 27) | |
7171 | ||
a6358dda TU |
7172 | #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010) |
7173 | #define GEN11_MASTER_IRQ (1 << 31) | |
7174 | #define GEN11_PCU_IRQ (1 << 30) | |
df0d28c1 | 7175 | #define GEN11_GU_MISC_IRQ (1 << 29) |
a6358dda TU |
7176 | #define GEN11_DISPLAY_IRQ (1 << 16) |
7177 | #define GEN11_GT_DW_IRQ(x) (1 << (x)) | |
7178 | #define GEN11_GT_DW1_IRQ (1 << 1) | |
7179 | #define GEN11_GT_DW0_IRQ (1 << 0) | |
7180 | ||
7181 | #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200) | |
7182 | #define GEN11_DISPLAY_IRQ_ENABLE (1 << 31) | |
7183 | #define GEN11_AUDIO_CODEC_IRQ (1 << 24) | |
7184 | #define GEN11_DE_PCH_IRQ (1 << 23) | |
7185 | #define GEN11_DE_MISC_IRQ (1 << 22) | |
121e758e | 7186 | #define GEN11_DE_HPD_IRQ (1 << 21) |
a6358dda TU |
7187 | #define GEN11_DE_PORT_IRQ (1 << 20) |
7188 | #define GEN11_DE_PIPE_C (1 << 18) | |
7189 | #define GEN11_DE_PIPE_B (1 << 17) | |
7190 | #define GEN11_DE_PIPE_A (1 << 16) | |
7191 | ||
121e758e DP |
7192 | #define GEN11_DE_HPD_ISR _MMIO(0x44470) |
7193 | #define GEN11_DE_HPD_IMR _MMIO(0x44474) | |
7194 | #define GEN11_DE_HPD_IIR _MMIO(0x44478) | |
7195 | #define GEN11_DE_HPD_IER _MMIO(0x4447c) | |
7196 | #define GEN11_TC4_HOTPLUG (1 << 19) | |
7197 | #define GEN11_TC3_HOTPLUG (1 << 18) | |
7198 | #define GEN11_TC2_HOTPLUG (1 << 17) | |
7199 | #define GEN11_TC1_HOTPLUG (1 << 16) | |
7200 | #define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC4_HOTPLUG | \ | |
7201 | GEN11_TC3_HOTPLUG | \ | |
7202 | GEN11_TC2_HOTPLUG | \ | |
7203 | GEN11_TC1_HOTPLUG) | |
b796b971 DP |
7204 | #define GEN11_TBT4_HOTPLUG (1 << 3) |
7205 | #define GEN11_TBT3_HOTPLUG (1 << 2) | |
7206 | #define GEN11_TBT2_HOTPLUG (1 << 1) | |
7207 | #define GEN11_TBT1_HOTPLUG (1 << 0) | |
7208 | #define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT4_HOTPLUG | \ | |
7209 | GEN11_TBT3_HOTPLUG | \ | |
7210 | GEN11_TBT2_HOTPLUG | \ | |
7211 | GEN11_TBT1_HOTPLUG) | |
7212 | ||
7213 | #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030) | |
121e758e DP |
7214 | #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038) |
7215 | #define GEN11_HOTPLUG_CTL_ENABLE(tc_port) (8 << (tc_port) * 4) | |
7216 | #define GEN11_HOTPLUG_CTL_LONG_DETECT(tc_port) (2 << (tc_port) * 4) | |
7217 | #define GEN11_HOTPLUG_CTL_SHORT_DETECT(tc_port) (1 << (tc_port) * 4) | |
7218 | #define GEN11_HOTPLUG_CTL_NO_DETECT(tc_port) (0 << (tc_port) * 4) | |
7219 | ||
a6358dda TU |
7220 | #define GEN11_GT_INTR_DW0 _MMIO(0x190018) |
7221 | #define GEN11_CSME (31) | |
7222 | #define GEN11_GUNIT (28) | |
7223 | #define GEN11_GUC (25) | |
7224 | #define GEN11_WDPERF (20) | |
7225 | #define GEN11_KCR (19) | |
7226 | #define GEN11_GTPM (16) | |
7227 | #define GEN11_BCS (15) | |
7228 | #define GEN11_RCS0 (0) | |
7229 | ||
7230 | #define GEN11_GT_INTR_DW1 _MMIO(0x19001c) | |
7231 | #define GEN11_VECS(x) (31 - (x)) | |
7232 | #define GEN11_VCS(x) (x) | |
7233 | ||
9e8789ec | 7234 | #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4)) |
a6358dda TU |
7235 | |
7236 | #define GEN11_INTR_IDENTITY_REG0 _MMIO(0x190060) | |
7237 | #define GEN11_INTR_IDENTITY_REG1 _MMIO(0x190064) | |
7238 | #define GEN11_INTR_DATA_VALID (1 << 31) | |
f744dbc2 MK |
7239 | #define GEN11_INTR_ENGINE_CLASS(x) (((x) & GENMASK(18, 16)) >> 16) |
7240 | #define GEN11_INTR_ENGINE_INSTANCE(x) (((x) & GENMASK(25, 20)) >> 20) | |
7241 | #define GEN11_INTR_ENGINE_INTR(x) ((x) & 0xffff) | |
a6358dda | 7242 | |
9e8789ec | 7243 | #define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4)) |
a6358dda TU |
7244 | |
7245 | #define GEN11_IIR_REG0_SELECTOR _MMIO(0x190070) | |
7246 | #define GEN11_IIR_REG1_SELECTOR _MMIO(0x190074) | |
7247 | ||
9e8789ec | 7248 | #define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4)) |
a6358dda TU |
7249 | |
7250 | #define GEN11_RENDER_COPY_INTR_ENABLE _MMIO(0x190030) | |
7251 | #define GEN11_VCS_VECS_INTR_ENABLE _MMIO(0x190034) | |
7252 | #define GEN11_GUC_SG_INTR_ENABLE _MMIO(0x190038) | |
7253 | #define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c) | |
7254 | #define GEN11_CRYPTO_RSVD_INTR_ENABLE _MMIO(0x190040) | |
7255 | #define GEN11_GUNIT_CSME_INTR_ENABLE _MMIO(0x190044) | |
7256 | ||
7257 | #define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090) | |
7258 | #define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0) | |
7259 | #define GEN11_VCS0_VCS1_INTR_MASK _MMIO(0x1900a8) | |
7260 | #define GEN11_VCS2_VCS3_INTR_MASK _MMIO(0x1900ac) | |
7261 | #define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0) | |
7262 | #define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8) | |
7263 | #define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec) | |
7264 | #define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0) | |
7265 | #define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4) | |
7266 | ||
f0f59a00 | 7267 | #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004) |
67e92af0 EA |
7268 | /* Required on all Ironlake and Sandybridge according to the B-Spec. */ |
7269 | #define ILK_ELPIN_409_SELECT (1 << 25) | |
5ee8ee86 PZ |
7270 | #define ILK_DPARB_GATE (1 << 22) |
7271 | #define ILK_VSDPFD_FULL (1 << 21) | |
f0f59a00 | 7272 | #define FUSE_STRAP _MMIO(0x42014) |
e3589908 DL |
7273 | #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31) |
7274 | #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30) | |
7275 | #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29) | |
8c448cad | 7276 | #define IVB_PIPE_C_DISABLE (1 << 28) |
e3589908 DL |
7277 | #define ILK_HDCP_DISABLE (1 << 25) |
7278 | #define ILK_eDP_A_DISABLE (1 << 24) | |
7279 | #define HSW_CDCLK_LIMIT (1 << 24) | |
7280 | #define ILK_DESKTOP (1 << 23) | |
231e54f6 | 7281 | |
f0f59a00 | 7282 | #define ILK_DSPCLK_GATE_D _MMIO(0x42020) |
231e54f6 DL |
7283 | #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) |
7284 | #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) | |
7285 | #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) | |
7286 | #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7) | |
7287 | #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5) | |
7f8a8569 | 7288 | |
f0f59a00 | 7289 | #define IVB_CHICKEN3 _MMIO(0x4200c) |
116ac8d2 EA |
7290 | # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) |
7291 | # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) | |
7292 | ||
f0f59a00 | 7293 | #define CHICKEN_PAR1_1 _MMIO(0x42080) |
93564044 | 7294 | #define SKL_DE_COMPRESSED_HASH_MODE (1 << 15) |
fe4ab3ce | 7295 | #define DPA_MASK_VBLANK_SRD (1 << 15) |
90a88643 | 7296 | #define FORCE_ARB_IDLE_PLANES (1 << 14) |
dc00b6a0 | 7297 | #define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) |
90a88643 | 7298 | |
17e0adf0 MK |
7299 | #define CHICKEN_PAR2_1 _MMIO(0x42090) |
7300 | #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14) | |
7301 | ||
f4f4b59b | 7302 | #define CHICKEN_MISC_2 _MMIO(0x42084) |
746a5173 | 7303 | #define CNL_COMP_PWR_DOWN (1 << 23) |
f4f4b59b | 7304 | #define GLK_CL2_PWR_DOWN (1 << 12) |
746a5173 PZ |
7305 | #define GLK_CL1_PWR_DOWN (1 << 11) |
7306 | #define GLK_CL0_PWR_DOWN (1 << 10) | |
d8d4a512 | 7307 | |
5654a162 PP |
7308 | #define CHICKEN_MISC_4 _MMIO(0x4208c) |
7309 | #define FBC_STRIDE_OVERRIDE (1 << 13) | |
7310 | #define FBC_STRIDE_MASK 0x1FFF | |
7311 | ||
fe4ab3ce BW |
7312 | #define _CHICKEN_PIPESL_1_A 0x420b0 |
7313 | #define _CHICKEN_PIPESL_1_B 0x420b4 | |
8f670bb1 VS |
7314 | #define HSW_FBCQ_DIS (1 << 22) |
7315 | #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0) | |
f0f59a00 | 7316 | #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) |
fe4ab3ce | 7317 | |
d86f0482 NV |
7318 | #define CHICKEN_TRANS_A 0x420c0 |
7319 | #define CHICKEN_TRANS_B 0x420c4 | |
7320 | #define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B) | |
5ee8ee86 PZ |
7321 | #define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and CNL+ */ |
7322 | #define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19) | |
7323 | #define DDI_TRAINING_OVERRIDE_VALUE (1 << 18) | |
7324 | #define DDIE_TRAINING_OVERRIDE_ENABLE (1 << 17) /* CHICKEN_TRANS_A only */ | |
7325 | #define DDIE_TRAINING_OVERRIDE_VALUE (1 << 16) /* CHICKEN_TRANS_A only */ | |
7326 | #define PSR2_ADD_VERTICAL_LINE_COUNT (1 << 15) | |
7327 | #define PSR2_VSC_ENABLE_PROG_HEADER (1 << 12) | |
d86f0482 | 7328 | |
f0f59a00 | 7329 | #define DISP_ARB_CTL _MMIO(0x45000) |
5ee8ee86 PZ |
7330 | #define DISP_FBC_MEMORY_WAKE (1 << 31) |
7331 | #define DISP_TILE_SURFACE_SWIZZLING (1 << 13) | |
7332 | #define DISP_FBC_WM_DIS (1 << 15) | |
f0f59a00 | 7333 | #define DISP_ARB_CTL2 _MMIO(0x45004) |
5ee8ee86 PZ |
7334 | #define DISP_DATA_PARTITION_5_6 (1 << 6) |
7335 | #define DISP_IPC_ENABLE (1 << 3) | |
f0f59a00 | 7336 | #define DBUF_CTL _MMIO(0x45008) |
746edf8f MK |
7337 | #define DBUF_CTL_S1 _MMIO(0x45008) |
7338 | #define DBUF_CTL_S2 _MMIO(0x44FE8) | |
5ee8ee86 PZ |
7339 | #define DBUF_POWER_REQUEST (1 << 31) |
7340 | #define DBUF_POWER_STATE (1 << 30) | |
f0f59a00 | 7341 | #define GEN7_MSG_CTL _MMIO(0x45010) |
5ee8ee86 PZ |
7342 | #define WAIT_FOR_PCH_RESET_ACK (1 << 1) |
7343 | #define WAIT_FOR_PCH_FLR_ACK (1 << 0) | |
f0f59a00 | 7344 | #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) |
5ee8ee86 | 7345 | #define RESET_PCH_HANDSHAKE_ENABLE (1 << 4) |
553bd149 | 7346 | |
590e8ff0 | 7347 | #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) |
ad186f3f PZ |
7348 | #define SKL_SELECT_ALTERNATE_DC_EXIT (1 << 30) |
7349 | #define MASK_WAKEMEM (1 << 13) | |
7350 | #define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7) | |
590e8ff0 | 7351 | |
f0f59a00 | 7352 | #define SKL_DFSM _MMIO(0x51000) |
a9419e84 DL |
7353 | #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23) |
7354 | #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23) | |
7355 | #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23) | |
7356 | #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23) | |
7357 | #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23) | |
bf4f2fb0 PJ |
7358 | #define SKL_DFSM_PIPE_A_DISABLE (1 << 30) |
7359 | #define SKL_DFSM_PIPE_B_DISABLE (1 << 21) | |
7360 | #define SKL_DFSM_PIPE_C_DISABLE (1 << 28) | |
a9419e84 | 7361 | |
186a277e PZ |
7362 | #define SKL_DSSM _MMIO(0x51004) |
7363 | #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31) | |
7364 | #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29) | |
7365 | #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29) | |
7366 | #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29) | |
7367 | #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29) | |
945f2672 | 7368 | |
a78536e7 | 7369 | #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0) |
5ee8ee86 | 7370 | #define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1 << 14) |
a78536e7 | 7371 | |
f0f59a00 | 7372 | #define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4) |
5ee8ee86 PZ |
7373 | #define GEN9_TSG_BARRIER_ACK_DISABLE (1 << 8) |
7374 | #define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE (1 << 10) | |
2caa3b26 | 7375 | |
2c8580e4 | 7376 | #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec) |
6bb62855 | 7377 | #define GEN9_CTX_PREEMPT_REG _MMIO(0x2248) |
e0f3fa09 | 7378 | #define GEN8_CS_CHICKEN1 _MMIO(0x2580) |
5ee8ee86 | 7379 | #define GEN9_PREEMPT_3D_OBJECT_LEVEL (1 << 0) |
5152defe MW |
7380 | #define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1)) |
7381 | #define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 0) | |
7382 | #define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 1) | |
7383 | #define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0) | |
7384 | #define GEN9_PREEMPT_GPGPU_LEVEL_MASK GEN9_PREEMPT_GPGPU_LEVEL(1, 1) | |
e0f3fa09 | 7385 | |
e4e0c058 | 7386 | /* GEN7 chicken */ |
f0f59a00 | 7387 | #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010) |
b1f88820 OM |
7388 | #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1 << 10) | (1 << 26)) |
7389 | #define GEN9_RHWO_OPTIMIZATION_DISABLE (1 << 14) | |
7390 | ||
7391 | #define COMMON_SLICE_CHICKEN2 _MMIO(0x7014) | |
7392 | #define GEN9_PBE_COMPRESSED_HASH_SELECTION (1 << 13) | |
7393 | #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1 << 12) | |
7394 | #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1 << 8) | |
7395 | #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1 << 0) | |
7396 | ||
7397 | #define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304) | |
7398 | #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC (1 << 11) | |
d71de14d | 7399 | |
f0f59a00 | 7400 | #define HIZ_CHICKEN _MMIO(0x7018) |
5ee8ee86 PZ |
7401 | # define CHV_HZ_8X8_MODE_IN_1X (1 << 15) |
7402 | # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1 << 3) | |
d60de81d | 7403 | |
f0f59a00 | 7404 | #define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308) |
5ee8ee86 | 7405 | #define DISABLE_PIXEL_MASK_CAMMING (1 << 14) |
183c6dac | 7406 | |
ab062639 | 7407 | #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c) |
f63c7b48 | 7408 | #define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11) |
ab062639 | 7409 | |
f0f59a00 | 7410 | #define GEN7_L3SQCREG1 _MMIO(0xB010) |
031994ee VS |
7411 | #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 |
7412 | ||
f0f59a00 | 7413 | #define GEN8_L3SQCREG1 _MMIO(0xB100) |
450174fe ID |
7414 | /* |
7415 | * Note that on CHV the following has an off-by-one error wrt. to BSpec. | |
7416 | * Using the formula in BSpec leads to a hang, while the formula here works | |
7417 | * fine and matches the formulas for all other platforms. A BSpec change | |
7418 | * request has been filed to clarify this. | |
7419 | */ | |
36579cb6 ID |
7420 | #define L3_GENERAL_PRIO_CREDITS(x) (((x) >> 1) << 19) |
7421 | #define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14) | |
930a784d | 7422 | #define L3_PRIO_CREDITS_MASK ((0x1f << 19) | (0x1f << 14)) |
51ce4db1 | 7423 | |
f0f59a00 | 7424 | #define GEN7_L3CNTLREG1 _MMIO(0xB01C) |
1af8452f | 7425 | #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C |
5ee8ee86 | 7426 | #define GEN7_L3AGDIS (1 << 19) |
f0f59a00 VS |
7427 | #define GEN7_L3CNTLREG2 _MMIO(0xB020) |
7428 | #define GEN7_L3CNTLREG3 _MMIO(0xB024) | |
e4e0c058 | 7429 | |
f0f59a00 | 7430 | #define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xB030) |
5215eef3 OM |
7431 | #define GEN7_WA_L3_CHICKEN_MODE 0x20000000 |
7432 | #define GEN10_L3_CHICKEN_MODE_REGISTER _MMIO(0xB114) | |
7433 | #define GEN11_I2M_WRITE_DISABLE (1 << 28) | |
e4e0c058 | 7434 | |
f0f59a00 | 7435 | #define GEN7_L3SQCREG4 _MMIO(0xb034) |
5ee8ee86 | 7436 | #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1 << 27) |
61939d97 | 7437 | |
f0f59a00 | 7438 | #define GEN8_L3SQCREG4 _MMIO(0xb118) |
5246ae4b OM |
7439 | #define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6) |
7440 | #define GEN8_LQSC_RO_PERF_DIS (1 << 27) | |
7441 | #define GEN8_LQSC_FLUSH_COHERENT_LINES (1 << 21) | |
8bc0ccf6 | 7442 | |
63801f21 | 7443 | /* GEN8 chicken */ |
f0f59a00 | 7444 | #define HDC_CHICKEN0 _MMIO(0x7300) |
acfb5554 | 7445 | #define CNL_HDC_CHICKEN0 _MMIO(0xE5F0) |
cc38cae7 | 7446 | #define ICL_HDC_MODE _MMIO(0xE5F4) |
5ee8ee86 PZ |
7447 | #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1 << 15) |
7448 | #define HDC_FENCE_DEST_SLM_DISABLE (1 << 14) | |
7449 | #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1 << 11) | |
7450 | #define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1 << 5) | |
7451 | #define HDC_FORCE_NON_COHERENT (1 << 4) | |
7452 | #define HDC_BARRIER_PERFORMANCE_DISABLE (1 << 10) | |
63801f21 | 7453 | |
3669ab61 AS |
7454 | #define GEN8_HDC_CHICKEN1 _MMIO(0x7304) |
7455 | ||
38a39a7b | 7456 | /* GEN9 chicken */ |
f0f59a00 | 7457 | #define SLICE_ECO_CHICKEN0 _MMIO(0x7308) |
38a39a7b BW |
7458 | #define PIXEL_MASK_CAMMING_DISABLE (1 << 14) |
7459 | ||
0c79f9cb MT |
7460 | #define GEN9_WM_CHICKEN3 _MMIO(0x5588) |
7461 | #define GEN9_FACTOR_IN_CLR_VAL_HIZ (1 << 9) | |
7462 | ||
db099c8f | 7463 | /* WaCatErrorRejectionIssue */ |
f0f59a00 | 7464 | #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030) |
5ee8ee86 | 7465 | #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1 << 11) |
db099c8f | 7466 | |
f0f59a00 | 7467 | #define HSW_SCRATCH1 _MMIO(0xb038) |
5ee8ee86 | 7468 | #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1 << 27) |
f3fc4884 | 7469 | |
f0f59a00 | 7470 | #define BDW_SCRATCH1 _MMIO(0xb11c) |
5ee8ee86 | 7471 | #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1 << 2) |
77719d28 | 7472 | |
e16a3750 VK |
7473 | /*GEN11 chicken */ |
7474 | #define _PIPEA_CHICKEN 0x70038 | |
7475 | #define _PIPEB_CHICKEN 0x71038 | |
7476 | #define _PIPEC_CHICKEN 0x72038 | |
7477 | #define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7) | |
7478 | #define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\ | |
7479 | _PIPEB_CHICKEN) | |
7480 | ||
b9055052 ZW |
7481 | /* PCH */ |
7482 | ||
23e81d69 | 7483 | /* south display engine interrupt: IBX */ |
776ad806 JB |
7484 | #define SDE_AUDIO_POWER_D (1 << 27) |
7485 | #define SDE_AUDIO_POWER_C (1 << 26) | |
7486 | #define SDE_AUDIO_POWER_B (1 << 25) | |
7487 | #define SDE_AUDIO_POWER_SHIFT (25) | |
7488 | #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) | |
7489 | #define SDE_GMBUS (1 << 24) | |
7490 | #define SDE_AUDIO_HDCP_TRANSB (1 << 23) | |
7491 | #define SDE_AUDIO_HDCP_TRANSA (1 << 22) | |
7492 | #define SDE_AUDIO_HDCP_MASK (3 << 22) | |
7493 | #define SDE_AUDIO_TRANSB (1 << 21) | |
7494 | #define SDE_AUDIO_TRANSA (1 << 20) | |
7495 | #define SDE_AUDIO_TRANS_MASK (3 << 20) | |
7496 | #define SDE_POISON (1 << 19) | |
7497 | /* 18 reserved */ | |
7498 | #define SDE_FDI_RXB (1 << 17) | |
7499 | #define SDE_FDI_RXA (1 << 16) | |
7500 | #define SDE_FDI_MASK (3 << 16) | |
7501 | #define SDE_AUXD (1 << 15) | |
7502 | #define SDE_AUXC (1 << 14) | |
7503 | #define SDE_AUXB (1 << 13) | |
7504 | #define SDE_AUX_MASK (7 << 13) | |
7505 | /* 12 reserved */ | |
b9055052 ZW |
7506 | #define SDE_CRT_HOTPLUG (1 << 11) |
7507 | #define SDE_PORTD_HOTPLUG (1 << 10) | |
7508 | #define SDE_PORTC_HOTPLUG (1 << 9) | |
7509 | #define SDE_PORTB_HOTPLUG (1 << 8) | |
7510 | #define SDE_SDVOB_HOTPLUG (1 << 6) | |
e5868a31 EE |
7511 | #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \ |
7512 | SDE_SDVOB_HOTPLUG | \ | |
7513 | SDE_PORTB_HOTPLUG | \ | |
7514 | SDE_PORTC_HOTPLUG | \ | |
7515 | SDE_PORTD_HOTPLUG) | |
776ad806 JB |
7516 | #define SDE_TRANSB_CRC_DONE (1 << 5) |
7517 | #define SDE_TRANSB_CRC_ERR (1 << 4) | |
7518 | #define SDE_TRANSB_FIFO_UNDER (1 << 3) | |
7519 | #define SDE_TRANSA_CRC_DONE (1 << 2) | |
7520 | #define SDE_TRANSA_CRC_ERR (1 << 1) | |
7521 | #define SDE_TRANSA_FIFO_UNDER (1 << 0) | |
7522 | #define SDE_TRANS_MASK (0x3f) | |
23e81d69 | 7523 | |
31604222 | 7524 | /* south display engine interrupt: CPT - CNP */ |
23e81d69 AJ |
7525 | #define SDE_AUDIO_POWER_D_CPT (1 << 31) |
7526 | #define SDE_AUDIO_POWER_C_CPT (1 << 30) | |
7527 | #define SDE_AUDIO_POWER_B_CPT (1 << 29) | |
7528 | #define SDE_AUDIO_POWER_SHIFT_CPT 29 | |
7529 | #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) | |
7530 | #define SDE_AUXD_CPT (1 << 27) | |
7531 | #define SDE_AUXC_CPT (1 << 26) | |
7532 | #define SDE_AUXB_CPT (1 << 25) | |
7533 | #define SDE_AUX_MASK_CPT (7 << 25) | |
26951caf | 7534 | #define SDE_PORTE_HOTPLUG_SPT (1 << 25) |
74c0b395 | 7535 | #define SDE_PORTA_HOTPLUG_SPT (1 << 24) |
8db9d77b ZW |
7536 | #define SDE_PORTD_HOTPLUG_CPT (1 << 23) |
7537 | #define SDE_PORTC_HOTPLUG_CPT (1 << 22) | |
7538 | #define SDE_PORTB_HOTPLUG_CPT (1 << 21) | |
23e81d69 | 7539 | #define SDE_CRT_HOTPLUG_CPT (1 << 19) |
73c352a2 | 7540 | #define SDE_SDVOB_HOTPLUG_CPT (1 << 18) |
2d7b8366 | 7541 | #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ |
73c352a2 | 7542 | SDE_SDVOB_HOTPLUG_CPT | \ |
2d7b8366 YL |
7543 | SDE_PORTD_HOTPLUG_CPT | \ |
7544 | SDE_PORTC_HOTPLUG_CPT | \ | |
7545 | SDE_PORTB_HOTPLUG_CPT) | |
26951caf XZ |
7546 | #define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \ |
7547 | SDE_PORTD_HOTPLUG_CPT | \ | |
7548 | SDE_PORTC_HOTPLUG_CPT | \ | |
74c0b395 VS |
7549 | SDE_PORTB_HOTPLUG_CPT | \ |
7550 | SDE_PORTA_HOTPLUG_SPT) | |
23e81d69 | 7551 | #define SDE_GMBUS_CPT (1 << 17) |
8664281b | 7552 | #define SDE_ERROR_CPT (1 << 16) |
23e81d69 AJ |
7553 | #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) |
7554 | #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) | |
7555 | #define SDE_FDI_RXC_CPT (1 << 8) | |
7556 | #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) | |
7557 | #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) | |
7558 | #define SDE_FDI_RXB_CPT (1 << 4) | |
7559 | #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) | |
7560 | #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) | |
7561 | #define SDE_FDI_RXA_CPT (1 << 0) | |
7562 | #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ | |
7563 | SDE_AUDIO_CP_REQ_B_CPT | \ | |
7564 | SDE_AUDIO_CP_REQ_A_CPT) | |
7565 | #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ | |
7566 | SDE_AUDIO_CP_CHG_B_CPT | \ | |
7567 | SDE_AUDIO_CP_CHG_A_CPT) | |
7568 | #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ | |
7569 | SDE_FDI_RXB_CPT | \ | |
7570 | SDE_FDI_RXA_CPT) | |
b9055052 | 7571 | |
31604222 AS |
7572 | /* south display engine interrupt: ICP */ |
7573 | #define SDE_TC4_HOTPLUG_ICP (1 << 27) | |
7574 | #define SDE_TC3_HOTPLUG_ICP (1 << 26) | |
7575 | #define SDE_TC2_HOTPLUG_ICP (1 << 25) | |
7576 | #define SDE_TC1_HOTPLUG_ICP (1 << 24) | |
7577 | #define SDE_GMBUS_ICP (1 << 23) | |
7578 | #define SDE_DDIB_HOTPLUG_ICP (1 << 17) | |
7579 | #define SDE_DDIA_HOTPLUG_ICP (1 << 16) | |
7580 | #define SDE_DDI_MASK_ICP (SDE_DDIB_HOTPLUG_ICP | \ | |
7581 | SDE_DDIA_HOTPLUG_ICP) | |
7582 | #define SDE_TC_MASK_ICP (SDE_TC4_HOTPLUG_ICP | \ | |
7583 | SDE_TC3_HOTPLUG_ICP | \ | |
7584 | SDE_TC2_HOTPLUG_ICP | \ | |
7585 | SDE_TC1_HOTPLUG_ICP) | |
7586 | ||
f0f59a00 VS |
7587 | #define SDEISR _MMIO(0xc4000) |
7588 | #define SDEIMR _MMIO(0xc4004) | |
7589 | #define SDEIIR _MMIO(0xc4008) | |
7590 | #define SDEIER _MMIO(0xc400c) | |
b9055052 | 7591 | |
f0f59a00 | 7592 | #define SERR_INT _MMIO(0xc4040) |
5ee8ee86 PZ |
7593 | #define SERR_INT_POISON (1 << 31) |
7594 | #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) | |
8664281b | 7595 | |
b9055052 | 7596 | /* digital port hotplug */ |
f0f59a00 | 7597 | #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */ |
195baa06 | 7598 | #define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */ |
d252bf68 | 7599 | #define BXT_DDIA_HPD_INVERT (1 << 27) |
195baa06 VS |
7600 | #define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */ |
7601 | #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */ | |
7602 | #define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */ | |
7603 | #define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */ | |
40bfd7a3 VS |
7604 | #define PORTD_HOTPLUG_ENABLE (1 << 20) |
7605 | #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */ | |
7606 | #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */ | |
7607 | #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */ | |
7608 | #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */ | |
7609 | #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */ | |
7610 | #define PORTD_HOTPLUG_STATUS_MASK (3 << 16) | |
b696519e DL |
7611 | #define PORTD_HOTPLUG_NO_DETECT (0 << 16) |
7612 | #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) | |
7613 | #define PORTD_HOTPLUG_LONG_DETECT (2 << 16) | |
40bfd7a3 | 7614 | #define PORTC_HOTPLUG_ENABLE (1 << 12) |
d252bf68 | 7615 | #define BXT_DDIC_HPD_INVERT (1 << 11) |
40bfd7a3 VS |
7616 | #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */ |
7617 | #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */ | |
7618 | #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */ | |
7619 | #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */ | |
7620 | #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */ | |
7621 | #define PORTC_HOTPLUG_STATUS_MASK (3 << 8) | |
b696519e DL |
7622 | #define PORTC_HOTPLUG_NO_DETECT (0 << 8) |
7623 | #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) | |
7624 | #define PORTC_HOTPLUG_LONG_DETECT (2 << 8) | |
40bfd7a3 | 7625 | #define PORTB_HOTPLUG_ENABLE (1 << 4) |
d252bf68 | 7626 | #define BXT_DDIB_HPD_INVERT (1 << 3) |
40bfd7a3 VS |
7627 | #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */ |
7628 | #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */ | |
7629 | #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */ | |
7630 | #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */ | |
7631 | #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */ | |
7632 | #define PORTB_HOTPLUG_STATUS_MASK (3 << 0) | |
b696519e DL |
7633 | #define PORTB_HOTPLUG_NO_DETECT (0 << 0) |
7634 | #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) | |
7635 | #define PORTB_HOTPLUG_LONG_DETECT (2 << 0) | |
d252bf68 SS |
7636 | #define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \ |
7637 | BXT_DDIB_HPD_INVERT | \ | |
7638 | BXT_DDIC_HPD_INVERT) | |
b9055052 | 7639 | |
f0f59a00 | 7640 | #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */ |
40bfd7a3 VS |
7641 | #define PORTE_HOTPLUG_ENABLE (1 << 4) |
7642 | #define PORTE_HOTPLUG_STATUS_MASK (3 << 0) | |
26951caf XZ |
7643 | #define PORTE_HOTPLUG_NO_DETECT (0 << 0) |
7644 | #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0) | |
7645 | #define PORTE_HOTPLUG_LONG_DETECT (2 << 0) | |
b9055052 | 7646 | |
31604222 AS |
7647 | /* This register is a reuse of PCH_PORT_HOTPLUG register. The |
7648 | * functionality covered in PCH_PORT_HOTPLUG is split into | |
7649 | * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC. | |
7650 | */ | |
7651 | ||
7652 | #define SHOTPLUG_CTL_DDI _MMIO(0xc4030) | |
7653 | #define ICP_DDIB_HPD_ENABLE (1 << 7) | |
7654 | #define ICP_DDIB_HPD_STATUS_MASK (3 << 4) | |
7655 | #define ICP_DDIB_HPD_NO_DETECT (0 << 4) | |
7656 | #define ICP_DDIB_HPD_SHORT_DETECT (1 << 4) | |
7657 | #define ICP_DDIB_HPD_LONG_DETECT (2 << 4) | |
7658 | #define ICP_DDIB_HPD_SHORT_LONG_DETECT (3 << 4) | |
7659 | #define ICP_DDIA_HPD_ENABLE (1 << 3) | |
7660 | #define ICP_DDIA_HPD_STATUS_MASK (3 << 0) | |
7661 | #define ICP_DDIA_HPD_NO_DETECT (0 << 0) | |
7662 | #define ICP_DDIA_HPD_SHORT_DETECT (1 << 0) | |
7663 | #define ICP_DDIA_HPD_LONG_DETECT (2 << 0) | |
7664 | #define ICP_DDIA_HPD_SHORT_LONG_DETECT (3 << 0) | |
7665 | ||
7666 | #define SHOTPLUG_CTL_TC _MMIO(0xc4034) | |
7667 | #define ICP_TC_HPD_ENABLE(tc_port) (8 << (tc_port) * 4) | |
7668 | #define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4) | |
7669 | #define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4) | |
7670 | ||
f0f59a00 VS |
7671 | #define PCH_GPIOA _MMIO(0xc5010) |
7672 | #define PCH_GPIOB _MMIO(0xc5014) | |
7673 | #define PCH_GPIOC _MMIO(0xc5018) | |
7674 | #define PCH_GPIOD _MMIO(0xc501c) | |
7675 | #define PCH_GPIOE _MMIO(0xc5020) | |
7676 | #define PCH_GPIOF _MMIO(0xc5024) | |
b9055052 | 7677 | |
f0f59a00 VS |
7678 | #define PCH_GMBUS0 _MMIO(0xc5100) |
7679 | #define PCH_GMBUS1 _MMIO(0xc5104) | |
7680 | #define PCH_GMBUS2 _MMIO(0xc5108) | |
7681 | #define PCH_GMBUS3 _MMIO(0xc510c) | |
7682 | #define PCH_GMBUS4 _MMIO(0xc5110) | |
7683 | #define PCH_GMBUS5 _MMIO(0xc5120) | |
f0217c42 | 7684 | |
9db4a9c7 JB |
7685 | #define _PCH_DPLL_A 0xc6014 |
7686 | #define _PCH_DPLL_B 0xc6018 | |
9e8789ec | 7687 | #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) |
b9055052 | 7688 | |
9db4a9c7 | 7689 | #define _PCH_FPA0 0xc6040 |
5ee8ee86 | 7690 | #define FP_CB_TUNE (0x3 << 22) |
9db4a9c7 JB |
7691 | #define _PCH_FPA1 0xc6044 |
7692 | #define _PCH_FPB0 0xc6048 | |
7693 | #define _PCH_FPB1 0xc604c | |
9e8789ec PZ |
7694 | #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0) |
7695 | #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1) | |
b9055052 | 7696 | |
f0f59a00 | 7697 | #define PCH_DPLL_TEST _MMIO(0xc606c) |
b9055052 | 7698 | |
f0f59a00 | 7699 | #define PCH_DREF_CONTROL _MMIO(0xC6200) |
b9055052 | 7700 | #define DREF_CONTROL_MASK 0x7fc3 |
5ee8ee86 PZ |
7701 | #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13) |
7702 | #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13) | |
7703 | #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13) | |
7704 | #define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13) | |
7705 | #define DREF_SSC_SOURCE_DISABLE (0 << 11) | |
7706 | #define DREF_SSC_SOURCE_ENABLE (2 << 11) | |
7707 | #define DREF_SSC_SOURCE_MASK (3 << 11) | |
7708 | #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9) | |
7709 | #define DREF_NONSPREAD_CK505_ENABLE (1 << 9) | |
7710 | #define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9) | |
7711 | #define DREF_NONSPREAD_SOURCE_MASK (3 << 9) | |
7712 | #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7) | |
7713 | #define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7) | |
7714 | #define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7) | |
7715 | #define DREF_SSC4_DOWNSPREAD (0 << 6) | |
7716 | #define DREF_SSC4_CENTERSPREAD (1 << 6) | |
7717 | #define DREF_SSC1_DISABLE (0 << 1) | |
7718 | #define DREF_SSC1_ENABLE (1 << 1) | |
b9055052 ZW |
7719 | #define DREF_SSC4_DISABLE (0) |
7720 | #define DREF_SSC4_ENABLE (1) | |
7721 | ||
f0f59a00 | 7722 | #define PCH_RAWCLK_FREQ _MMIO(0xc6204) |
b9055052 | 7723 | #define FDL_TP1_TIMER_SHIFT 12 |
5ee8ee86 | 7724 | #define FDL_TP1_TIMER_MASK (3 << 12) |
b9055052 | 7725 | #define FDL_TP2_TIMER_SHIFT 10 |
5ee8ee86 | 7726 | #define FDL_TP2_TIMER_MASK (3 << 10) |
b9055052 | 7727 | #define RAWCLK_FREQ_MASK 0x3ff |
9d81a997 RV |
7728 | #define CNP_RAWCLK_DIV_MASK (0x3ff << 16) |
7729 | #define CNP_RAWCLK_DIV(div) ((div) << 16) | |
7730 | #define CNP_RAWCLK_FRAC_MASK (0xf << 26) | |
7731 | #define CNP_RAWCLK_FRAC(frac) ((frac) << 26) | |
4ef99abd AS |
7732 | #define ICP_RAWCLK_DEN(den) ((den) << 26) |
7733 | #define ICP_RAWCLK_NUM(num) ((num) << 11) | |
b9055052 | 7734 | |
f0f59a00 | 7735 | #define PCH_DPLL_TMR_CFG _MMIO(0xc6208) |
b9055052 | 7736 | |
f0f59a00 VS |
7737 | #define PCH_SSC4_PARMS _MMIO(0xc6210) |
7738 | #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214) | |
b9055052 | 7739 | |
f0f59a00 | 7740 | #define PCH_DPLL_SEL _MMIO(0xc7000) |
68d97538 | 7741 | #define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4)) |
11887397 | 7742 | #define TRANS_DPLLA_SEL(pipe) 0 |
68d97538 | 7743 | #define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3)) |
8db9d77b | 7744 | |
b9055052 ZW |
7745 | /* transcoder */ |
7746 | ||
275f01b2 DV |
7747 | #define _PCH_TRANS_HTOTAL_A 0xe0000 |
7748 | #define TRANS_HTOTAL_SHIFT 16 | |
7749 | #define TRANS_HACTIVE_SHIFT 0 | |
7750 | #define _PCH_TRANS_HBLANK_A 0xe0004 | |
7751 | #define TRANS_HBLANK_END_SHIFT 16 | |
7752 | #define TRANS_HBLANK_START_SHIFT 0 | |
7753 | #define _PCH_TRANS_HSYNC_A 0xe0008 | |
7754 | #define TRANS_HSYNC_END_SHIFT 16 | |
7755 | #define TRANS_HSYNC_START_SHIFT 0 | |
7756 | #define _PCH_TRANS_VTOTAL_A 0xe000c | |
7757 | #define TRANS_VTOTAL_SHIFT 16 | |
7758 | #define TRANS_VACTIVE_SHIFT 0 | |
7759 | #define _PCH_TRANS_VBLANK_A 0xe0010 | |
7760 | #define TRANS_VBLANK_END_SHIFT 16 | |
7761 | #define TRANS_VBLANK_START_SHIFT 0 | |
7762 | #define _PCH_TRANS_VSYNC_A 0xe0014 | |
af7187b7 | 7763 | #define TRANS_VSYNC_END_SHIFT 16 |
275f01b2 DV |
7764 | #define TRANS_VSYNC_START_SHIFT 0 |
7765 | #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028 | |
b9055052 | 7766 | |
e3b95f1e DV |
7767 | #define _PCH_TRANSA_DATA_M1 0xe0030 |
7768 | #define _PCH_TRANSA_DATA_N1 0xe0034 | |
7769 | #define _PCH_TRANSA_DATA_M2 0xe0038 | |
7770 | #define _PCH_TRANSA_DATA_N2 0xe003c | |
7771 | #define _PCH_TRANSA_LINK_M1 0xe0040 | |
7772 | #define _PCH_TRANSA_LINK_N1 0xe0044 | |
7773 | #define _PCH_TRANSA_LINK_M2 0xe0048 | |
7774 | #define _PCH_TRANSA_LINK_N2 0xe004c | |
9db4a9c7 | 7775 | |
2dcbc34d | 7776 | /* Per-transcoder DIP controls (PCH) */ |
b055c8f3 JB |
7777 | #define _VIDEO_DIP_CTL_A 0xe0200 |
7778 | #define _VIDEO_DIP_DATA_A 0xe0208 | |
7779 | #define _VIDEO_DIP_GCP_A 0xe0210 | |
6d67415f VS |
7780 | #define GCP_COLOR_INDICATION (1 << 2) |
7781 | #define GCP_DEFAULT_PHASE_ENABLE (1 << 1) | |
7782 | #define GCP_AV_MUTE (1 << 0) | |
b055c8f3 JB |
7783 | |
7784 | #define _VIDEO_DIP_CTL_B 0xe1200 | |
7785 | #define _VIDEO_DIP_DATA_B 0xe1208 | |
7786 | #define _VIDEO_DIP_GCP_B 0xe1210 | |
7787 | ||
f0f59a00 VS |
7788 | #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) |
7789 | #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) | |
7790 | #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) | |
b055c8f3 | 7791 | |
2dcbc34d | 7792 | /* Per-transcoder DIP controls (VLV) */ |
086f8e84 VS |
7793 | #define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200) |
7794 | #define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208) | |
7795 | #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210) | |
90b107c8 | 7796 | |
086f8e84 VS |
7797 | #define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170) |
7798 | #define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174) | |
7799 | #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178) | |
90b107c8 | 7800 | |
086f8e84 VS |
7801 | #define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0) |
7802 | #define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4) | |
7803 | #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8) | |
2dcbc34d | 7804 | |
90b107c8 | 7805 | #define VLV_TVIDEO_DIP_CTL(pipe) \ |
f0f59a00 | 7806 | _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \ |
086f8e84 | 7807 | _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C) |
90b107c8 | 7808 | #define VLV_TVIDEO_DIP_DATA(pipe) \ |
f0f59a00 | 7809 | _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \ |
086f8e84 | 7810 | _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C) |
90b107c8 | 7811 | #define VLV_TVIDEO_DIP_GCP(pipe) \ |
f0f59a00 | 7812 | _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \ |
086f8e84 | 7813 | _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C) |
90b107c8 | 7814 | |
8c5f5f7c | 7815 | /* Haswell DIP controls */ |
f0f59a00 | 7816 | |
086f8e84 VS |
7817 | #define _HSW_VIDEO_DIP_CTL_A 0x60200 |
7818 | #define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220 | |
7819 | #define _HSW_VIDEO_DIP_VS_DATA_A 0x60260 | |
7820 | #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 | |
7821 | #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 | |
7822 | #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320 | |
7823 | #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240 | |
7824 | #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280 | |
7825 | #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 | |
7826 | #define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300 | |
7827 | #define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344 | |
7828 | #define _HSW_VIDEO_DIP_GCP_A 0x60210 | |
7829 | ||
7830 | #define _HSW_VIDEO_DIP_CTL_B 0x61200 | |
7831 | #define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220 | |
7832 | #define _HSW_VIDEO_DIP_VS_DATA_B 0x61260 | |
7833 | #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 | |
7834 | #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 | |
7835 | #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320 | |
7836 | #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240 | |
7837 | #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280 | |
7838 | #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 | |
7839 | #define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300 | |
7840 | #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344 | |
7841 | #define _HSW_VIDEO_DIP_GCP_B 0x61210 | |
8c5f5f7c | 7842 | |
f0f59a00 VS |
7843 | #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A) |
7844 | #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4) | |
7845 | #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4) | |
7846 | #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) | |
7847 | #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A) | |
7848 | #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) | |
7849 | ||
7850 | #define _HSW_STEREO_3D_CTL_A 0x70020 | |
5ee8ee86 | 7851 | #define S3D_ENABLE (1 << 31) |
f0f59a00 VS |
7852 | #define _HSW_STEREO_3D_CTL_B 0x71020 |
7853 | ||
7854 | #define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A) | |
3f51e471 | 7855 | |
275f01b2 DV |
7856 | #define _PCH_TRANS_HTOTAL_B 0xe1000 |
7857 | #define _PCH_TRANS_HBLANK_B 0xe1004 | |
7858 | #define _PCH_TRANS_HSYNC_B 0xe1008 | |
7859 | #define _PCH_TRANS_VTOTAL_B 0xe100c | |
7860 | #define _PCH_TRANS_VBLANK_B 0xe1010 | |
7861 | #define _PCH_TRANS_VSYNC_B 0xe1014 | |
f0f59a00 | 7862 | #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 |
275f01b2 | 7863 | |
f0f59a00 VS |
7864 | #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) |
7865 | #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) | |
7866 | #define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B) | |
7867 | #define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B) | |
7868 | #define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B) | |
7869 | #define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B) | |
7870 | #define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B) | |
9db4a9c7 | 7871 | |
e3b95f1e DV |
7872 | #define _PCH_TRANSB_DATA_M1 0xe1030 |
7873 | #define _PCH_TRANSB_DATA_N1 0xe1034 | |
7874 | #define _PCH_TRANSB_DATA_M2 0xe1038 | |
7875 | #define _PCH_TRANSB_DATA_N2 0xe103c | |
7876 | #define _PCH_TRANSB_LINK_M1 0xe1040 | |
7877 | #define _PCH_TRANSB_LINK_N1 0xe1044 | |
7878 | #define _PCH_TRANSB_LINK_M2 0xe1048 | |
7879 | #define _PCH_TRANSB_LINK_N2 0xe104c | |
7880 | ||
f0f59a00 VS |
7881 | #define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1) |
7882 | #define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1) | |
7883 | #define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2) | |
7884 | #define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2) | |
7885 | #define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1) | |
7886 | #define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1) | |
7887 | #define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2) | |
7888 | #define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2) | |
9db4a9c7 | 7889 | |
ab9412ba DV |
7890 | #define _PCH_TRANSACONF 0xf0008 |
7891 | #define _PCH_TRANSBCONF 0xf1008 | |
f0f59a00 VS |
7892 | #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF) |
7893 | #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */ | |
5ee8ee86 PZ |
7894 | #define TRANS_DISABLE (0 << 31) |
7895 | #define TRANS_ENABLE (1 << 31) | |
7896 | #define TRANS_STATE_MASK (1 << 30) | |
7897 | #define TRANS_STATE_DISABLE (0 << 30) | |
7898 | #define TRANS_STATE_ENABLE (1 << 30) | |
7899 | #define TRANS_FSYNC_DELAY_HB1 (0 << 27) | |
7900 | #define TRANS_FSYNC_DELAY_HB2 (1 << 27) | |
7901 | #define TRANS_FSYNC_DELAY_HB3 (2 << 27) | |
7902 | #define TRANS_FSYNC_DELAY_HB4 (3 << 27) | |
7903 | #define TRANS_INTERLACE_MASK (7 << 21) | |
7904 | #define TRANS_PROGRESSIVE (0 << 21) | |
7905 | #define TRANS_INTERLACED (3 << 21) | |
7906 | #define TRANS_LEGACY_INTERLACED_ILK (2 << 21) | |
7907 | #define TRANS_8BPC (0 << 5) | |
7908 | #define TRANS_10BPC (1 << 5) | |
7909 | #define TRANS_6BPC (2 << 5) | |
7910 | #define TRANS_12BPC (3 << 5) | |
b9055052 | 7911 | |
ce40141f DV |
7912 | #define _TRANSA_CHICKEN1 0xf0060 |
7913 | #define _TRANSB_CHICKEN1 0xf1060 | |
f0f59a00 | 7914 | #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) |
5ee8ee86 PZ |
7915 | #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1 << 10) |
7916 | #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1 << 4) | |
3bcf603f JB |
7917 | #define _TRANSA_CHICKEN2 0xf0064 |
7918 | #define _TRANSB_CHICKEN2 0xf1064 | |
f0f59a00 | 7919 | #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) |
5ee8ee86 PZ |
7920 | #define TRANS_CHICKEN2_TIMING_OVERRIDE (1 << 31) |
7921 | #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1 << 29) | |
7922 | #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3 << 27) | |
7923 | #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1 << 26) | |
7924 | #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1 << 25) | |
3bcf603f | 7925 | |
f0f59a00 | 7926 | #define SOUTH_CHICKEN1 _MMIO(0xc2000) |
291427f5 JB |
7927 | #define FDIA_PHASE_SYNC_SHIFT_OVR 19 |
7928 | #define FDIA_PHASE_SYNC_SHIFT_EN 18 | |
5ee8ee86 PZ |
7929 | #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) |
7930 | #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) | |
01a415fd | 7931 | #define FDI_BC_BIFURCATION_SELECT (1 << 12) |
3b92e263 RV |
7932 | #define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8) |
7933 | #define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8) | |
5ee8ee86 | 7934 | #define SPT_PWM_GRANULARITY (1 << 0) |
f0f59a00 | 7935 | #define SOUTH_CHICKEN2 _MMIO(0xc2004) |
5ee8ee86 PZ |
7936 | #define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13) |
7937 | #define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12) | |
7938 | #define LPT_PWM_GRANULARITY (1 << 5) | |
7939 | #define DPLS_EDP_PPS_FIX_DIS (1 << 0) | |
645c62a5 | 7940 | |
f0f59a00 VS |
7941 | #define _FDI_RXA_CHICKEN 0xc200c |
7942 | #define _FDI_RXB_CHICKEN 0xc2010 | |
5ee8ee86 PZ |
7943 | #define FDI_RX_PHASE_SYNC_POINTER_OVR (1 << 1) |
7944 | #define FDI_RX_PHASE_SYNC_POINTER_EN (1 << 0) | |
f0f59a00 | 7945 | #define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) |
b9055052 | 7946 | |
f0f59a00 | 7947 | #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020) |
5ee8ee86 PZ |
7948 | #define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31) |
7949 | #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30) | |
7950 | #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29) | |
7951 | #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14) | |
7952 | #define CNP_PWM_CGE_GATING_DISABLE (1 << 13) | |
7953 | #define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12) | |
382b0936 | 7954 | |
b9055052 | 7955 | /* CPU: FDI_TX */ |
f0f59a00 VS |
7956 | #define _FDI_TXA_CTL 0x60100 |
7957 | #define _FDI_TXB_CTL 0x61100 | |
7958 | #define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) | |
5ee8ee86 PZ |
7959 | #define FDI_TX_DISABLE (0 << 31) |
7960 | #define FDI_TX_ENABLE (1 << 31) | |
7961 | #define FDI_LINK_TRAIN_PATTERN_1 (0 << 28) | |
7962 | #define FDI_LINK_TRAIN_PATTERN_2 (1 << 28) | |
7963 | #define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28) | |
7964 | #define FDI_LINK_TRAIN_NONE (3 << 28) | |
7965 | #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25) | |
7966 | #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25) | |
7967 | #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25) | |
7968 | #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25) | |
7969 | #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22) | |
7970 | #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22) | |
7971 | #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22) | |
7972 | #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22) | |
8db9d77b ZW |
7973 | /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. |
7974 | SNB has different settings. */ | |
7975 | /* SNB A-stepping */ | |
5ee8ee86 PZ |
7976 | #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) |
7977 | #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) | |
7978 | #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) | |
7979 | #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22) | |
8db9d77b | 7980 | /* SNB B-stepping */ |
5ee8ee86 PZ |
7981 | #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0 << 22) |
7982 | #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22) | |
7983 | #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22) | |
7984 | #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22) | |
7985 | #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22) | |
627eb5a3 DV |
7986 | #define FDI_DP_PORT_WIDTH_SHIFT 19 |
7987 | #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT) | |
7988 | #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT) | |
5ee8ee86 | 7989 | #define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18) |
f2b115e6 | 7990 | /* Ironlake: hardwired to 1 */ |
5ee8ee86 | 7991 | #define FDI_TX_PLL_ENABLE (1 << 14) |
357555c0 JB |
7992 | |
7993 | /* Ivybridge has different bits for lolz */ | |
5ee8ee86 PZ |
7994 | #define FDI_LINK_TRAIN_PATTERN_1_IVB (0 << 8) |
7995 | #define FDI_LINK_TRAIN_PATTERN_2_IVB (1 << 8) | |
7996 | #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2 << 8) | |
7997 | #define FDI_LINK_TRAIN_NONE_IVB (3 << 8) | |
357555c0 | 7998 | |
b9055052 | 7999 | /* both Tx and Rx */ |
5ee8ee86 PZ |
8000 | #define FDI_COMPOSITE_SYNC (1 << 11) |
8001 | #define FDI_LINK_TRAIN_AUTO (1 << 10) | |
8002 | #define FDI_SCRAMBLING_ENABLE (0 << 7) | |
8003 | #define FDI_SCRAMBLING_DISABLE (1 << 7) | |
b9055052 ZW |
8004 | |
8005 | /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ | |
9db4a9c7 JB |
8006 | #define _FDI_RXA_CTL 0xf000c |
8007 | #define _FDI_RXB_CTL 0xf100c | |
f0f59a00 | 8008 | #define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) |
5ee8ee86 | 8009 | #define FDI_RX_ENABLE (1 << 31) |
b9055052 | 8010 | /* train, dp width same as FDI_TX */ |
5ee8ee86 PZ |
8011 | #define FDI_FS_ERRC_ENABLE (1 << 27) |
8012 | #define FDI_FE_ERRC_ENABLE (1 << 26) | |
8013 | #define FDI_RX_POLARITY_REVERSED_LPT (1 << 16) | |
8014 | #define FDI_8BPC (0 << 16) | |
8015 | #define FDI_10BPC (1 << 16) | |
8016 | #define FDI_6BPC (2 << 16) | |
8017 | #define FDI_12BPC (3 << 16) | |
8018 | #define FDI_RX_LINK_REVERSAL_OVERRIDE (1 << 15) | |
8019 | #define FDI_DMI_LINK_REVERSE_MASK (1 << 14) | |
8020 | #define FDI_RX_PLL_ENABLE (1 << 13) | |
8021 | #define FDI_FS_ERR_CORRECT_ENABLE (1 << 11) | |
8022 | #define FDI_FE_ERR_CORRECT_ENABLE (1 << 10) | |
8023 | #define FDI_FS_ERR_REPORT_ENABLE (1 << 9) | |
8024 | #define FDI_FE_ERR_REPORT_ENABLE (1 << 8) | |
8025 | #define FDI_RX_ENHANCE_FRAME_ENABLE (1 << 6) | |
8026 | #define FDI_PCDCLK (1 << 4) | |
8db9d77b | 8027 | /* CPT */ |
5ee8ee86 PZ |
8028 | #define FDI_AUTO_TRAINING (1 << 10) |
8029 | #define FDI_LINK_TRAIN_PATTERN_1_CPT (0 << 8) | |
8030 | #define FDI_LINK_TRAIN_PATTERN_2_CPT (1 << 8) | |
8031 | #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2 << 8) | |
8032 | #define FDI_LINK_TRAIN_NORMAL_CPT (3 << 8) | |
8033 | #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3 << 8) | |
b9055052 | 8034 | |
04945641 PZ |
8035 | #define _FDI_RXA_MISC 0xf0010 |
8036 | #define _FDI_RXB_MISC 0xf1010 | |
5ee8ee86 PZ |
8037 | #define FDI_RX_PWRDN_LANE1_MASK (3 << 26) |
8038 | #define FDI_RX_PWRDN_LANE1_VAL(x) ((x) << 26) | |
8039 | #define FDI_RX_PWRDN_LANE0_MASK (3 << 24) | |
8040 | #define FDI_RX_PWRDN_LANE0_VAL(x) ((x) << 24) | |
8041 | #define FDI_RX_TP1_TO_TP2_48 (2 << 20) | |
8042 | #define FDI_RX_TP1_TO_TP2_64 (3 << 20) | |
8043 | #define FDI_RX_FDI_DELAY_90 (0x90 << 0) | |
f0f59a00 | 8044 | #define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) |
04945641 | 8045 | |
f0f59a00 VS |
8046 | #define _FDI_RXA_TUSIZE1 0xf0030 |
8047 | #define _FDI_RXA_TUSIZE2 0xf0038 | |
8048 | #define _FDI_RXB_TUSIZE1 0xf1030 | |
8049 | #define _FDI_RXB_TUSIZE2 0xf1038 | |
8050 | #define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) | |
8051 | #define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) | |
b9055052 ZW |
8052 | |
8053 | /* FDI_RX interrupt register format */ | |
5ee8ee86 PZ |
8054 | #define FDI_RX_INTER_LANE_ALIGN (1 << 10) |
8055 | #define FDI_RX_SYMBOL_LOCK (1 << 9) /* train 2 */ | |
8056 | #define FDI_RX_BIT_LOCK (1 << 8) /* train 1 */ | |
8057 | #define FDI_RX_TRAIN_PATTERN_2_FAIL (1 << 7) | |
8058 | #define FDI_RX_FS_CODE_ERR (1 << 6) | |
8059 | #define FDI_RX_FE_CODE_ERR (1 << 5) | |
8060 | #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1 << 4) | |
8061 | #define FDI_RX_HDCP_LINK_FAIL (1 << 3) | |
8062 | #define FDI_RX_PIXEL_FIFO_OVERFLOW (1 << 2) | |
8063 | #define FDI_RX_CROSS_CLOCK_OVERFLOW (1 << 1) | |
8064 | #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1 << 0) | |
b9055052 | 8065 | |
f0f59a00 VS |
8066 | #define _FDI_RXA_IIR 0xf0014 |
8067 | #define _FDI_RXA_IMR 0xf0018 | |
8068 | #define _FDI_RXB_IIR 0xf1014 | |
8069 | #define _FDI_RXB_IMR 0xf1018 | |
8070 | #define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) | |
8071 | #define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) | |
b9055052 | 8072 | |
f0f59a00 VS |
8073 | #define FDI_PLL_CTL_1 _MMIO(0xfe000) |
8074 | #define FDI_PLL_CTL_2 _MMIO(0xfe004) | |
b9055052 | 8075 | |
f0f59a00 | 8076 | #define PCH_LVDS _MMIO(0xe1180) |
b9055052 ZW |
8077 | #define LVDS_DETECTED (1 << 1) |
8078 | ||
f0f59a00 VS |
8079 | #define _PCH_DP_B 0xe4100 |
8080 | #define PCH_DP_B _MMIO(_PCH_DP_B) | |
750a951f VS |
8081 | #define _PCH_DPB_AUX_CH_CTL 0xe4110 |
8082 | #define _PCH_DPB_AUX_CH_DATA1 0xe4114 | |
8083 | #define _PCH_DPB_AUX_CH_DATA2 0xe4118 | |
8084 | #define _PCH_DPB_AUX_CH_DATA3 0xe411c | |
8085 | #define _PCH_DPB_AUX_CH_DATA4 0xe4120 | |
8086 | #define _PCH_DPB_AUX_CH_DATA5 0xe4124 | |
5eb08b69 | 8087 | |
f0f59a00 VS |
8088 | #define _PCH_DP_C 0xe4200 |
8089 | #define PCH_DP_C _MMIO(_PCH_DP_C) | |
750a951f VS |
8090 | #define _PCH_DPC_AUX_CH_CTL 0xe4210 |
8091 | #define _PCH_DPC_AUX_CH_DATA1 0xe4214 | |
8092 | #define _PCH_DPC_AUX_CH_DATA2 0xe4218 | |
8093 | #define _PCH_DPC_AUX_CH_DATA3 0xe421c | |
8094 | #define _PCH_DPC_AUX_CH_DATA4 0xe4220 | |
8095 | #define _PCH_DPC_AUX_CH_DATA5 0xe4224 | |
5eb08b69 | 8096 | |
f0f59a00 VS |
8097 | #define _PCH_DP_D 0xe4300 |
8098 | #define PCH_DP_D _MMIO(_PCH_DP_D) | |
750a951f VS |
8099 | #define _PCH_DPD_AUX_CH_CTL 0xe4310 |
8100 | #define _PCH_DPD_AUX_CH_DATA1 0xe4314 | |
8101 | #define _PCH_DPD_AUX_CH_DATA2 0xe4318 | |
8102 | #define _PCH_DPD_AUX_CH_DATA3 0xe431c | |
8103 | #define _PCH_DPD_AUX_CH_DATA4 0xe4320 | |
8104 | #define _PCH_DPD_AUX_CH_DATA5 0xe4324 | |
8105 | ||
bdabdb63 VS |
8106 | #define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL) |
8107 | #define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ | |
5eb08b69 | 8108 | |
8db9d77b | 8109 | /* CPT */ |
086f8e84 VS |
8110 | #define _TRANS_DP_CTL_A 0xe0300 |
8111 | #define _TRANS_DP_CTL_B 0xe1300 | |
8112 | #define _TRANS_DP_CTL_C 0xe2300 | |
f0f59a00 | 8113 | #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B) |
5ee8ee86 | 8114 | #define TRANS_DP_OUTPUT_ENABLE (1 << 31) |
f67dc6d8 VS |
8115 | #define TRANS_DP_PORT_SEL_MASK (3 << 29) |
8116 | #define TRANS_DP_PORT_SEL_NONE (3 << 29) | |
8117 | #define TRANS_DP_PORT_SEL(port) (((port) - PORT_B) << 29) | |
5ee8ee86 PZ |
8118 | #define TRANS_DP_AUDIO_ONLY (1 << 26) |
8119 | #define TRANS_DP_ENH_FRAMING (1 << 18) | |
8120 | #define TRANS_DP_8BPC (0 << 9) | |
8121 | #define TRANS_DP_10BPC (1 << 9) | |
8122 | #define TRANS_DP_6BPC (2 << 9) | |
8123 | #define TRANS_DP_12BPC (3 << 9) | |
8124 | #define TRANS_DP_BPC_MASK (3 << 9) | |
8125 | #define TRANS_DP_VSYNC_ACTIVE_HIGH (1 << 4) | |
8db9d77b | 8126 | #define TRANS_DP_VSYNC_ACTIVE_LOW 0 |
5ee8ee86 | 8127 | #define TRANS_DP_HSYNC_ACTIVE_HIGH (1 << 3) |
8db9d77b | 8128 | #define TRANS_DP_HSYNC_ACTIVE_LOW 0 |
5ee8ee86 | 8129 | #define TRANS_DP_SYNC_MASK (3 << 3) |
8db9d77b ZW |
8130 | |
8131 | /* SNB eDP training params */ | |
8132 | /* SNB A-stepping */ | |
5ee8ee86 PZ |
8133 | #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) |
8134 | #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) | |
8135 | #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) | |
8136 | #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22) | |
8db9d77b | 8137 | /* SNB B-stepping */ |
5ee8ee86 PZ |
8138 | #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22) |
8139 | #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22) | |
8140 | #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22) | |
8141 | #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22) | |
8142 | #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22) | |
8143 | #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22) | |
8db9d77b | 8144 | |
1a2eb460 | 8145 | /* IVB */ |
5ee8ee86 PZ |
8146 | #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22) |
8147 | #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22) | |
8148 | #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22) | |
8149 | #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22) | |
8150 | #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22) | |
8151 | #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22) | |
8152 | #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22) | |
1a2eb460 KP |
8153 | |
8154 | /* legacy values */ | |
5ee8ee86 PZ |
8155 | #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22) |
8156 | #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22) | |
8157 | #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22) | |
8158 | #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22) | |
8159 | #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22) | |
1a2eb460 | 8160 | |
5ee8ee86 | 8161 | #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22) |
1a2eb460 | 8162 | |
f0f59a00 | 8163 | #define VLV_PMWGICZ _MMIO(0x1300a4) |
9e72b46c | 8164 | |
274008e8 SAK |
8165 | #define RC6_LOCATION _MMIO(0xD40) |
8166 | #define RC6_CTX_IN_DRAM (1 << 0) | |
8167 | #define RC6_CTX_BASE _MMIO(0xD48) | |
8168 | #define RC6_CTX_BASE_MASK 0xFFFFFFF0 | |
8169 | #define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054) | |
8170 | #define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054) | |
8171 | #define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054) | |
8172 | #define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054) | |
8173 | #define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054) | |
8174 | #define IDLE_TIME_MASK 0xFFFFF | |
f0f59a00 VS |
8175 | #define FORCEWAKE _MMIO(0xA18C) |
8176 | #define FORCEWAKE_VLV _MMIO(0x1300b0) | |
8177 | #define FORCEWAKE_ACK_VLV _MMIO(0x1300b4) | |
8178 | #define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8) | |
8179 | #define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc) | |
8180 | #define FORCEWAKE_ACK_HSW _MMIO(0x130044) | |
8181 | #define FORCEWAKE_ACK _MMIO(0x130090) | |
8182 | #define VLV_GTLC_WAKE_CTRL _MMIO(0x130090) | |
981a5aea ID |
8183 | #define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25) |
8184 | #define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24) | |
8185 | #define VLV_GTLC_ALLOWWAKEREQ (1 << 0) | |
8186 | ||
f0f59a00 | 8187 | #define VLV_GTLC_PW_STATUS _MMIO(0x130094) |
981a5aea ID |
8188 | #define VLV_GTLC_ALLOWWAKEACK (1 << 0) |
8189 | #define VLV_GTLC_ALLOWWAKEERR (1 << 1) | |
8190 | #define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5) | |
8191 | #define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7) | |
f0f59a00 VS |
8192 | #define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */ |
8193 | #define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270) | |
a89a70a8 DCS |
8194 | #define FORCEWAKE_MEDIA_VDBOX_GEN11(n) _MMIO(0xa540 + (n) * 4) |
8195 | #define FORCEWAKE_MEDIA_VEBOX_GEN11(n) _MMIO(0xa560 + (n) * 4) | |
f0f59a00 VS |
8196 | #define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278) |
8197 | #define FORCEWAKE_BLITTER_GEN9 _MMIO(0xa188) | |
8198 | #define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0x0D88) | |
a89a70a8 DCS |
8199 | #define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) _MMIO(0x0D50 + (n) * 4) |
8200 | #define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) _MMIO(0x0D70 + (n) * 4) | |
f0f59a00 VS |
8201 | #define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84) |
8202 | #define FORCEWAKE_ACK_BLITTER_GEN9 _MMIO(0x130044) | |
71306303 MK |
8203 | #define FORCEWAKE_KERNEL BIT(0) |
8204 | #define FORCEWAKE_USER BIT(1) | |
8205 | #define FORCEWAKE_KERNEL_FALLBACK BIT(15) | |
f0f59a00 VS |
8206 | #define FORCEWAKE_MT_ACK _MMIO(0x130040) |
8207 | #define ECOBUS _MMIO(0xa180) | |
5ee8ee86 | 8208 | #define FORCEWAKE_MT_ENABLE (1 << 5) |
f0f59a00 | 8209 | #define VLV_SPAREG2H _MMIO(0xA194) |
f2dd7578 AG |
8210 | #define GEN9_PWRGT_DOMAIN_STATUS _MMIO(0xA2A0) |
8211 | #define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0) | |
8212 | #define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1) | |
8fd26859 | 8213 | |
f0f59a00 | 8214 | #define GTFIFODBG _MMIO(0x120000) |
297b32ec VS |
8215 | #define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20) |
8216 | #define GT_FIFO_FREE_ENTRIES_CHV (0x7f << 13) | |
5ee8ee86 PZ |
8217 | #define GT_FIFO_SBDROPERR (1 << 6) |
8218 | #define GT_FIFO_BLOBDROPERR (1 << 5) | |
8219 | #define GT_FIFO_SB_READ_ABORTERR (1 << 4) | |
8220 | #define GT_FIFO_DROPERR (1 << 3) | |
8221 | #define GT_FIFO_OVFERR (1 << 2) | |
8222 | #define GT_FIFO_IAWRERR (1 << 1) | |
8223 | #define GT_FIFO_IARDERR (1 << 0) | |
dd202c6d | 8224 | |
f0f59a00 | 8225 | #define GTFIFOCTL _MMIO(0x120008) |
46520e2b | 8226 | #define GT_FIFO_FREE_ENTRIES_MASK 0x7f |
95736720 | 8227 | #define GT_FIFO_NUM_RESERVED_ENTRIES 20 |
a04f90a3 D |
8228 | #define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12) |
8229 | #define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11) | |
91355834 | 8230 | |
f0f59a00 | 8231 | #define HSW_IDICR _MMIO(0x9008) |
05e21cc4 | 8232 | #define IDIHASHMSK(x) (((x) & 0x3f) << 16) |
3accaf7e | 8233 | #define HSW_EDRAM_CAP _MMIO(0x120010) |
2db59d53 | 8234 | #define EDRAM_ENABLED 0x1 |
c02e85a0 MK |
8235 | #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf) |
8236 | #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7) | |
8237 | #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3) | |
05e21cc4 | 8238 | |
f0f59a00 | 8239 | #define GEN6_UCGCTL1 _MMIO(0x9400) |
8aeb7f62 | 8240 | # define GEN6_GAMUNIT_CLOCK_GATE_DISABLE (1 << 22) |
e4443e45 | 8241 | # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16) |
80e829fa | 8242 | # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) |
de4a8bd1 | 8243 | # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) |
80e829fa | 8244 | |
f0f59a00 | 8245 | #define GEN6_UCGCTL2 _MMIO(0x9404) |
f9fc42f4 | 8246 | # define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31) |
0f846f81 | 8247 | # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30) |
6edaa7fc | 8248 | # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22) |
eae66b50 | 8249 | # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) |
406478dc | 8250 | # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) |
9ca1d10d | 8251 | # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) |
406478dc | 8252 | |
f0f59a00 | 8253 | #define GEN6_UCGCTL3 _MMIO(0x9408) |
d7965152 | 8254 | # define GEN6_OACSUNIT_CLOCK_GATE_DISABLE (1 << 20) |
9e72b46c | 8255 | |
f0f59a00 | 8256 | #define GEN7_UCGCTL4 _MMIO(0x940c) |
5ee8ee86 PZ |
8257 | #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1 << 25) |
8258 | #define GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE (1 << 14) | |
e3f33d46 | 8259 | |
f0f59a00 VS |
8260 | #define GEN6_RCGCTL1 _MMIO(0x9410) |
8261 | #define GEN6_RCGCTL2 _MMIO(0x9414) | |
8262 | #define GEN6_RSTCTL _MMIO(0x9420) | |
9e72b46c | 8263 | |
f0f59a00 | 8264 | #define GEN8_UCGCTL6 _MMIO(0x9430) |
5ee8ee86 PZ |
8265 | #define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1 << 24) |
8266 | #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1 << 14) | |
8267 | #define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1 << 28) | |
4f1ca9e9 | 8268 | |
f0f59a00 VS |
8269 | #define GEN6_GFXPAUSE _MMIO(0xA000) |
8270 | #define GEN6_RPNSWREQ _MMIO(0xA008) | |
5ee8ee86 PZ |
8271 | #define GEN6_TURBO_DISABLE (1 << 31) |
8272 | #define GEN6_FREQUENCY(x) ((x) << 25) | |
8273 | #define HSW_FREQUENCY(x) ((x) << 24) | |
8274 | #define GEN9_FREQUENCY(x) ((x) << 23) | |
8275 | #define GEN6_OFFSET(x) ((x) << 19) | |
8276 | #define GEN6_AGGRESSIVE_TURBO (0 << 15) | |
f0f59a00 VS |
8277 | #define GEN6_RC_VIDEO_FREQ _MMIO(0xA00C) |
8278 | #define GEN6_RC_CONTROL _MMIO(0xA090) | |
5ee8ee86 PZ |
8279 | #define GEN6_RC_CTL_RC6pp_ENABLE (1 << 16) |
8280 | #define GEN6_RC_CTL_RC6p_ENABLE (1 << 17) | |
8281 | #define GEN6_RC_CTL_RC6_ENABLE (1 << 18) | |
8282 | #define GEN6_RC_CTL_RC1e_ENABLE (1 << 20) | |
8283 | #define GEN6_RC_CTL_RC7_ENABLE (1 << 22) | |
8284 | #define VLV_RC_CTL_CTX_RST_PARALLEL (1 << 24) | |
8285 | #define GEN7_RC_CTL_TO_MODE (1 << 28) | |
8286 | #define GEN6_RC_CTL_EI_MODE(x) ((x) << 27) | |
8287 | #define GEN6_RC_CTL_HW_ENABLE (1 << 31) | |
f0f59a00 VS |
8288 | #define GEN6_RP_DOWN_TIMEOUT _MMIO(0xA010) |
8289 | #define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xA014) | |
8290 | #define GEN6_RPSTAT1 _MMIO(0xA01C) | |
ccab5c82 | 8291 | #define GEN6_CAGF_SHIFT 8 |
f82855d3 | 8292 | #define HSW_CAGF_SHIFT 7 |
de43ae9d | 8293 | #define GEN9_CAGF_SHIFT 23 |
ccab5c82 | 8294 | #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) |
f82855d3 | 8295 | #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT) |
de43ae9d | 8296 | #define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT) |
f0f59a00 | 8297 | #define GEN6_RP_CONTROL _MMIO(0xA024) |
5ee8ee86 PZ |
8298 | #define GEN6_RP_MEDIA_TURBO (1 << 11) |
8299 | #define GEN6_RP_MEDIA_MODE_MASK (3 << 9) | |
8300 | #define GEN6_RP_MEDIA_HW_TURBO_MODE (3 << 9) | |
8301 | #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2 << 9) | |
8302 | #define GEN6_RP_MEDIA_HW_MODE (1 << 9) | |
8303 | #define GEN6_RP_MEDIA_SW_MODE (0 << 9) | |
8304 | #define GEN6_RP_MEDIA_IS_GFX (1 << 8) | |
8305 | #define GEN6_RP_ENABLE (1 << 7) | |
8306 | #define GEN6_RP_UP_IDLE_MIN (0x1 << 3) | |
8307 | #define GEN6_RP_UP_BUSY_AVG (0x2 << 3) | |
8308 | #define GEN6_RP_UP_BUSY_CONT (0x4 << 3) | |
8309 | #define GEN6_RP_DOWN_IDLE_AVG (0x2 << 0) | |
8310 | #define GEN6_RP_DOWN_IDLE_CONT (0x1 << 0) | |
f0f59a00 VS |
8311 | #define GEN6_RP_UP_THRESHOLD _MMIO(0xA02C) |
8312 | #define GEN6_RP_DOWN_THRESHOLD _MMIO(0xA030) | |
8313 | #define GEN6_RP_CUR_UP_EI _MMIO(0xA050) | |
7466c291 CW |
8314 | #define GEN6_RP_EI_MASK 0xffffff |
8315 | #define GEN6_CURICONT_MASK GEN6_RP_EI_MASK | |
f0f59a00 | 8316 | #define GEN6_RP_CUR_UP _MMIO(0xA054) |
7466c291 | 8317 | #define GEN6_CURBSYTAVG_MASK GEN6_RP_EI_MASK |
f0f59a00 VS |
8318 | #define GEN6_RP_PREV_UP _MMIO(0xA058) |
8319 | #define GEN6_RP_CUR_DOWN_EI _MMIO(0xA05C) | |
7466c291 | 8320 | #define GEN6_CURIAVG_MASK GEN6_RP_EI_MASK |
f0f59a00 VS |
8321 | #define GEN6_RP_CUR_DOWN _MMIO(0xA060) |
8322 | #define GEN6_RP_PREV_DOWN _MMIO(0xA064) | |
8323 | #define GEN6_RP_UP_EI _MMIO(0xA068) | |
8324 | #define GEN6_RP_DOWN_EI _MMIO(0xA06C) | |
8325 | #define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xA070) | |
8326 | #define GEN6_RPDEUHWTC _MMIO(0xA080) | |
8327 | #define GEN6_RPDEUC _MMIO(0xA084) | |
8328 | #define GEN6_RPDEUCSW _MMIO(0xA088) | |
8329 | #define GEN6_RC_STATE _MMIO(0xA094) | |
fc619841 ID |
8330 | #define RC_SW_TARGET_STATE_SHIFT 16 |
8331 | #define RC_SW_TARGET_STATE_MASK (7 << RC_SW_TARGET_STATE_SHIFT) | |
f0f59a00 VS |
8332 | #define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098) |
8333 | #define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C) | |
8334 | #define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0) | |
0aab201b | 8335 | #define GEN10_MEDIA_WAKE_RATE_LIMIT _MMIO(0xA0A0) |
f0f59a00 VS |
8336 | #define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8) |
8337 | #define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC) | |
8338 | #define GEN6_RC_SLEEP _MMIO(0xA0B0) | |
8339 | #define GEN6_RCUBMABDTMR _MMIO(0xA0B0) | |
8340 | #define GEN6_RC1e_THRESHOLD _MMIO(0xA0B4) | |
8341 | #define GEN6_RC6_THRESHOLD _MMIO(0xA0B8) | |
8342 | #define GEN6_RC6p_THRESHOLD _MMIO(0xA0BC) | |
8343 | #define VLV_RCEDATA _MMIO(0xA0BC) | |
8344 | #define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0) | |
8345 | #define GEN6_PMINTRMSK _MMIO(0xA168) | |
5ee8ee86 PZ |
8346 | #define GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC (1 << 31) |
8347 | #define ARAT_EXPIRED_INTRMSK (1 << 9) | |
fc619841 | 8348 | #define GEN8_MISC_CTRL0 _MMIO(0xA180) |
f0f59a00 VS |
8349 | #define VLV_PWRDWNUPCTL _MMIO(0xA294) |
8350 | #define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4) | |
8351 | #define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8) | |
8352 | #define GEN9_PG_ENABLE _MMIO(0xA210) | |
5ee8ee86 PZ |
8353 | #define GEN9_RENDER_PG_ENABLE (1 << 0) |
8354 | #define GEN9_MEDIA_PG_ENABLE (1 << 1) | |
fc619841 ID |
8355 | #define GEN8_PUSHBUS_CONTROL _MMIO(0xA248) |
8356 | #define GEN8_PUSHBUS_ENABLE _MMIO(0xA250) | |
8357 | #define GEN8_PUSHBUS_SHIFT _MMIO(0xA25C) | |
8fd26859 | 8358 | |
f0f59a00 | 8359 | #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C) |
a9da9bce GS |
8360 | #define PIXEL_OVERLAP_CNT_MASK (3 << 30) |
8361 | #define PIXEL_OVERLAP_CNT_SHIFT 30 | |
8362 | ||
f0f59a00 VS |
8363 | #define GEN6_PMISR _MMIO(0x44020) |
8364 | #define GEN6_PMIMR _MMIO(0x44024) /* rps_lock */ | |
8365 | #define GEN6_PMIIR _MMIO(0x44028) | |
8366 | #define GEN6_PMIER _MMIO(0x4402C) | |
5ee8ee86 PZ |
8367 | #define GEN6_PM_MBOX_EVENT (1 << 25) |
8368 | #define GEN6_PM_THERMAL_EVENT (1 << 24) | |
8369 | #define GEN6_PM_RP_DOWN_TIMEOUT (1 << 6) | |
8370 | #define GEN6_PM_RP_UP_THRESHOLD (1 << 5) | |
8371 | #define GEN6_PM_RP_DOWN_THRESHOLD (1 << 4) | |
8372 | #define GEN6_PM_RP_UP_EI_EXPIRED (1 << 2) | |
8373 | #define GEN6_PM_RP_DOWN_EI_EXPIRED (1 << 1) | |
4848405c | 8374 | #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \ |
4912d041 BW |
8375 | GEN6_PM_RP_DOWN_THRESHOLD | \ |
8376 | GEN6_PM_RP_DOWN_TIMEOUT) | |
8fd26859 | 8377 | |
f0f59a00 | 8378 | #define GEN7_GT_SCRATCH(i) _MMIO(0x4F100 + (i) * 4) |
9e72b46c ID |
8379 | #define GEN7_GT_SCRATCH_REG_NUM 8 |
8380 | ||
f0f59a00 | 8381 | #define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098) |
5ee8ee86 PZ |
8382 | #define VLV_GFX_CLK_STATUS_BIT (1 << 3) |
8383 | #define VLV_GFX_CLK_FORCE_ON_BIT (1 << 2) | |
76c3552f | 8384 | |
f0f59a00 VS |
8385 | #define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104) |
8386 | #define VLV_COUNTER_CONTROL _MMIO(0x138104) | |
5ee8ee86 PZ |
8387 | #define VLV_COUNT_RANGE_HIGH (1 << 15) |
8388 | #define VLV_MEDIA_RC0_COUNT_EN (1 << 5) | |
8389 | #define VLV_RENDER_RC0_COUNT_EN (1 << 4) | |
8390 | #define VLV_MEDIA_RC6_COUNT_EN (1 << 1) | |
8391 | #define VLV_RENDER_RC6_COUNT_EN (1 << 0) | |
f0f59a00 VS |
8392 | #define GEN6_GT_GFX_RC6 _MMIO(0x138108) |
8393 | #define VLV_GT_RENDER_RC6 _MMIO(0x138108) | |
8394 | #define VLV_GT_MEDIA_RC6 _MMIO(0x13810C) | |
9cc19be5 | 8395 | |
f0f59a00 VS |
8396 | #define GEN6_GT_GFX_RC6p _MMIO(0x13810C) |
8397 | #define GEN6_GT_GFX_RC6pp _MMIO(0x138110) | |
8398 | #define VLV_RENDER_C0_COUNT _MMIO(0x138118) | |
8399 | #define VLV_MEDIA_C0_COUNT _MMIO(0x13811C) | |
cce66a28 | 8400 | |
f0f59a00 | 8401 | #define GEN6_PCODE_MAILBOX _MMIO(0x138124) |
5ee8ee86 | 8402 | #define GEN6_PCODE_READY (1 << 31) |
87660502 L |
8403 | #define GEN6_PCODE_ERROR_MASK 0xFF |
8404 | #define GEN6_PCODE_SUCCESS 0x0 | |
8405 | #define GEN6_PCODE_ILLEGAL_CMD 0x1 | |
8406 | #define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2 | |
8407 | #define GEN6_PCODE_TIMEOUT 0x3 | |
8408 | #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF | |
8409 | #define GEN7_PCODE_TIMEOUT 0x2 | |
8410 | #define GEN7_PCODE_ILLEGAL_DATA 0x3 | |
8411 | #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10 | |
3e8ddd9e VS |
8412 | #define GEN6_PCODE_WRITE_RC6VIDS 0x4 |
8413 | #define GEN6_PCODE_READ_RC6VIDS 0x5 | |
9043ae02 DL |
8414 | #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) |
8415 | #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) | |
b432e5cf | 8416 | #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18 |
57520bc5 DL |
8417 | #define GEN9_PCODE_READ_MEM_LATENCY 0x6 |
8418 | #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF | |
8419 | #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8 | |
8420 | #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16 | |
8421 | #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24 | |
ee5e5e7a | 8422 | #define SKL_PCODE_LOAD_HDCP_KEYS 0x5 |
5d96d8af DL |
8423 | #define SKL_PCODE_CDCLK_CONTROL 0x7 |
8424 | #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3 | |
8425 | #define SKL_CDCLK_READY_FOR_CHANGE 0x1 | |
9043ae02 DL |
8426 | #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 |
8427 | #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 | |
8428 | #define GEN6_READ_OC_PARAMS 0xc | |
515b2392 PZ |
8429 | #define GEN6_PCODE_READ_D_COMP 0x10 |
8430 | #define GEN6_PCODE_WRITE_D_COMP 0x11 | |
f8437dd1 | 8431 | #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 |
2a114cc1 | 8432 | #define DISPLAY_IPS_CONTROL 0x19 |
61843f0e VS |
8433 | /* See also IPS_CTL */ |
8434 | #define IPS_PCODE_CONTROL (1 << 30) | |
3e8ddd9e | 8435 | #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A |
656d1b89 L |
8436 | #define GEN9_PCODE_SAGV_CONTROL 0x21 |
8437 | #define GEN9_SAGV_DISABLE 0x0 | |
8438 | #define GEN9_SAGV_IS_DISABLED 0x1 | |
8439 | #define GEN9_SAGV_ENABLE 0x3 | |
f0f59a00 | 8440 | #define GEN6_PCODE_DATA _MMIO(0x138128) |
23b2f8bb | 8441 | #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 |
3ebecd07 | 8442 | #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 |
f0f59a00 | 8443 | #define GEN6_PCODE_DATA1 _MMIO(0x13812C) |
8fd26859 | 8444 | |
f0f59a00 | 8445 | #define GEN6_GT_CORE_STATUS _MMIO(0x138060) |
5ee8ee86 | 8446 | #define GEN6_CORE_CPD_STATE_MASK (7 << 4) |
4d85529d BW |
8447 | #define GEN6_RCn_MASK 7 |
8448 | #define GEN6_RC0 0 | |
8449 | #define GEN6_RC3 2 | |
8450 | #define GEN6_RC6 3 | |
8451 | #define GEN6_RC7 4 | |
8452 | ||
f0f59a00 | 8453 | #define GEN8_GT_SLICE_INFO _MMIO(0x138064) |
91bedd34 ŁD |
8454 | #define GEN8_LSLICESTAT_MASK 0x7 |
8455 | ||
f0f59a00 VS |
8456 | #define CHV_POWER_SS0_SIG1 _MMIO(0xa720) |
8457 | #define CHV_POWER_SS1_SIG1 _MMIO(0xa728) | |
5ee8ee86 PZ |
8458 | #define CHV_SS_PG_ENABLE (1 << 1) |
8459 | #define CHV_EU08_PG_ENABLE (1 << 9) | |
8460 | #define CHV_EU19_PG_ENABLE (1 << 17) | |
8461 | #define CHV_EU210_PG_ENABLE (1 << 25) | |
5575f03a | 8462 | |
f0f59a00 VS |
8463 | #define CHV_POWER_SS0_SIG2 _MMIO(0xa724) |
8464 | #define CHV_POWER_SS1_SIG2 _MMIO(0xa72c) | |
5ee8ee86 | 8465 | #define CHV_EU311_PG_ENABLE (1 << 1) |
5575f03a | 8466 | |
5ee8ee86 | 8467 | #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4) |
f8c3dcf9 RV |
8468 | #define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \ |
8469 | ((slice) % 3) * 0x4) | |
7f992aba | 8470 | #define GEN9_PGCTL_SLICE_ACK (1 << 0) |
5ee8ee86 | 8471 | #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice) * 2)) |
f8c3dcf9 | 8472 | #define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F) |
7f992aba | 8473 | |
5ee8ee86 | 8474 | #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8) |
f8c3dcf9 RV |
8475 | #define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \ |
8476 | ((slice) % 3) * 0x8) | |
5ee8ee86 | 8477 | #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8) |
f8c3dcf9 RV |
8478 | #define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \ |
8479 | ((slice) % 3) * 0x8) | |
7f992aba JM |
8480 | #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0) |
8481 | #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2) | |
8482 | #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4) | |
8483 | #define GEN9_PGCTL_SSA_EU311_ACK (1 << 6) | |
8484 | #define GEN9_PGCTL_SSB_EU08_ACK (1 << 8) | |
8485 | #define GEN9_PGCTL_SSB_EU19_ACK (1 << 10) | |
8486 | #define GEN9_PGCTL_SSB_EU210_ACK (1 << 12) | |
8487 | #define GEN9_PGCTL_SSB_EU311_ACK (1 << 14) | |
8488 | ||
f0f59a00 | 8489 | #define GEN7_MISCCPCTL _MMIO(0x9424) |
5ee8ee86 PZ |
8490 | #define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0) |
8491 | #define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2) | |
8492 | #define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1 << 4) | |
8493 | #define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1 << 6) | |
e3689190 | 8494 | |
5bcebe76 OM |
8495 | #define GEN8_GARBCNTL _MMIO(0xB004) |
8496 | #define GEN9_GAPS_TSV_CREDIT_DISABLE (1 << 7) | |
8497 | #define GEN11_ARBITRATION_PRIO_ORDER_MASK (0x3f << 22) | |
d41bab68 OM |
8498 | #define GEN11_HASH_CTRL_EXCL_MASK (0x7f << 0) |
8499 | #define GEN11_HASH_CTRL_EXCL_BIT0 (1 << 0) | |
8500 | ||
8501 | #define GEN11_GLBLINVL _MMIO(0xB404) | |
8502 | #define GEN11_BANK_HASH_ADDR_EXCL_MASK (0x7f << 5) | |
8503 | #define GEN11_BANK_HASH_ADDR_EXCL_BIT0 (1 << 5) | |
245d9667 | 8504 | |
d65dc3e4 OM |
8505 | #define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550) |
8506 | #define DFR_DISABLE (1 << 9) | |
8507 | ||
f4a35714 OM |
8508 | #define GEN11_GACB_PERF_CTRL _MMIO(0x4B80) |
8509 | #define GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0) | |
8510 | #define GEN11_HASH_CTRL_BIT0 (1 << 0) | |
8511 | #define GEN11_HASH_CTRL_BIT4 (1 << 12) | |
8512 | ||
6b967dc3 OM |
8513 | #define GEN11_LSN_UNSLCVC _MMIO(0xB43C) |
8514 | #define GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC (1 << 9) | |
8515 | #define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC (1 << 7) | |
8516 | ||
908ae051 OM |
8517 | #define GAMW_ECO_DEV_RW_IA_REG _MMIO(0x4080) |
8518 | #define GAMW_ECO_DEV_CTX_RELOAD_DISABLE (1 << 7) | |
8519 | ||
e3689190 | 8520 | /* IVYBRIDGE DPF */ |
f0f59a00 | 8521 | #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */ |
5ee8ee86 PZ |
8522 | #define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14) |
8523 | #define GEN7_PARITY_ERROR_VALID (1 << 13) | |
8524 | #define GEN7_L3CDERRST1_BANK_MASK (3 << 11) | |
8525 | #define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8) | |
e3689190 | 8526 | #define GEN7_PARITY_ERROR_ROW(reg) \ |
9e8789ec | 8527 | (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14) |
e3689190 | 8528 | #define GEN7_PARITY_ERROR_BANK(reg) \ |
9e8789ec | 8529 | (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11) |
e3689190 | 8530 | #define GEN7_PARITY_ERROR_SUBBANK(reg) \ |
9e8789ec | 8531 | (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) |
5ee8ee86 | 8532 | #define GEN7_L3CDERRST1_ENABLE (1 << 7) |
e3689190 | 8533 | |
f0f59a00 | 8534 | #define GEN7_L3LOG(slice, i) _MMIO(0xB070 + (slice) * 0x200 + (i) * 4) |
b9524a1e BW |
8535 | #define GEN7_L3LOG_SIZE 0x80 |
8536 | ||
f0f59a00 VS |
8537 | #define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */ |
8538 | #define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100) | |
5ee8ee86 PZ |
8539 | #define GEN7_MAX_PS_THREAD_DEP (8 << 12) |
8540 | #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1 << 10) | |
8541 | #define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1 << 4) | |
8542 | #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1 << 3) | |
12f3382b | 8543 | |
f0f59a00 | 8544 | #define GEN9_HALF_SLICE_CHICKEN5 _MMIO(0xe188) |
5ee8ee86 PZ |
8545 | #define GEN9_DG_MIRROR_FIX_ENABLE (1 << 5) |
8546 | #define GEN9_CCS_TLB_PREFETCH_ENABLE (1 << 3) | |
3ca5da43 | 8547 | |
f0f59a00 | 8548 | #define GEN8_ROW_CHICKEN _MMIO(0xe4f0) |
5ee8ee86 PZ |
8549 | #define FLOW_CONTROL_ENABLE (1 << 15) |
8550 | #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1 << 8) | |
8551 | #define STALL_DOP_GATING_DISABLE (1 << 5) | |
8552 | #define THROTTLE_12_5 (7 << 2) | |
8553 | #define DISABLE_EARLY_EOT (1 << 1) | |
c8966e10 | 8554 | |
f0f59a00 VS |
8555 | #define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4) |
8556 | #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4) | |
3c7ab278 OM |
8557 | #define DOP_CLOCK_GATING_DISABLE (1 << 0) |
8558 | #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8) | |
8559 | #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1) | |
8ab43976 | 8560 | |
f0f59a00 | 8561 | #define HSW_ROW_CHICKEN3 _MMIO(0xe49c) |
f3fc4884 FJ |
8562 | #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) |
8563 | ||
f0f59a00 | 8564 | #define HALF_SLICE_CHICKEN2 _MMIO(0xe180) |
5ee8ee86 | 8565 | #define GEN8_ST_PO_DISABLE (1 << 13) |
6b6d5626 | 8566 | |
f0f59a00 | 8567 | #define HALF_SLICE_CHICKEN3 _MMIO(0xe184) |
5ee8ee86 PZ |
8568 | #define HSW_SAMPLE_C_PERFORMANCE (1 << 9) |
8569 | #define GEN8_CENTROID_PIXEL_OPT_DIS (1 << 8) | |
8570 | #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1 << 5) | |
8571 | #define CNL_FAST_ANISO_L1_BANKING_FIX (1 << 4) | |
8572 | #define GEN8_SAMPLER_POWER_BYPASS_DIS (1 << 1) | |
fd392b60 | 8573 | |
f0f59a00 | 8574 | #define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194) |
5ee8ee86 PZ |
8575 | #define GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR (1 << 8) |
8576 | #define GEN9_ENABLE_YV12_BUGFIX (1 << 4) | |
8577 | #define GEN9_ENABLE_GPGPU_PREEMPTION (1 << 2) | |
cac23df4 | 8578 | |
c46f111f | 8579 | /* Audio */ |
f0f59a00 | 8580 | #define G4X_AUD_VID_DID _MMIO(dev_priv->info.display_mmio_offset + 0x62020) |
c46f111f JN |
8581 | #define INTEL_AUDIO_DEVCL 0x808629FB |
8582 | #define INTEL_AUDIO_DEVBLC 0x80862801 | |
8583 | #define INTEL_AUDIO_DEVCTG 0x80862802 | |
e0dac65e | 8584 | |
f0f59a00 | 8585 | #define G4X_AUD_CNTL_ST _MMIO(0x620B4) |
c46f111f JN |
8586 | #define G4X_ELDV_DEVCL_DEVBLC (1 << 13) |
8587 | #define G4X_ELDV_DEVCTG (1 << 14) | |
8588 | #define G4X_ELD_ADDR_MASK (0xf << 5) | |
8589 | #define G4X_ELD_ACK (1 << 4) | |
f0f59a00 | 8590 | #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C) |
e0dac65e | 8591 | |
c46f111f JN |
8592 | #define _IBX_HDMIW_HDMIEDID_A 0xE2050 |
8593 | #define _IBX_HDMIW_HDMIEDID_B 0xE2150 | |
f0f59a00 VS |
8594 | #define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \ |
8595 | _IBX_HDMIW_HDMIEDID_B) | |
c46f111f JN |
8596 | #define _IBX_AUD_CNTL_ST_A 0xE20B4 |
8597 | #define _IBX_AUD_CNTL_ST_B 0xE21B4 | |
f0f59a00 VS |
8598 | #define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \ |
8599 | _IBX_AUD_CNTL_ST_B) | |
c46f111f JN |
8600 | #define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10) |
8601 | #define IBX_ELD_ADDRESS_MASK (0x1f << 5) | |
8602 | #define IBX_ELD_ACK (1 << 4) | |
f0f59a00 | 8603 | #define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0) |
82910ac6 JN |
8604 | #define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4)) |
8605 | #define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4)) | |
1202b4c6 | 8606 | |
c46f111f JN |
8607 | #define _CPT_HDMIW_HDMIEDID_A 0xE5050 |
8608 | #define _CPT_HDMIW_HDMIEDID_B 0xE5150 | |
f0f59a00 | 8609 | #define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B) |
c46f111f JN |
8610 | #define _CPT_AUD_CNTL_ST_A 0xE50B4 |
8611 | #define _CPT_AUD_CNTL_ST_B 0xE51B4 | |
f0f59a00 VS |
8612 | #define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B) |
8613 | #define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0) | |
e0dac65e | 8614 | |
c46f111f JN |
8615 | #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050) |
8616 | #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150) | |
f0f59a00 | 8617 | #define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B) |
c46f111f JN |
8618 | #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4) |
8619 | #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4) | |
f0f59a00 VS |
8620 | #define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B) |
8621 | #define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0) | |
9ca2fe73 | 8622 | |
ae662d31 EA |
8623 | /* These are the 4 32-bit write offset registers for each stream |
8624 | * output buffer. It determines the offset from the | |
8625 | * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. | |
8626 | */ | |
f0f59a00 | 8627 | #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4) |
ae662d31 | 8628 | |
c46f111f JN |
8629 | #define _IBX_AUD_CONFIG_A 0xe2000 |
8630 | #define _IBX_AUD_CONFIG_B 0xe2100 | |
f0f59a00 | 8631 | #define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B) |
c46f111f JN |
8632 | #define _CPT_AUD_CONFIG_A 0xe5000 |
8633 | #define _CPT_AUD_CONFIG_B 0xe5100 | |
f0f59a00 | 8634 | #define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B) |
c46f111f JN |
8635 | #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000) |
8636 | #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100) | |
f0f59a00 | 8637 | #define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B) |
9ca2fe73 | 8638 | |
b6daa025 WF |
8639 | #define AUD_CONFIG_N_VALUE_INDEX (1 << 29) |
8640 | #define AUD_CONFIG_N_PROG_ENABLE (1 << 28) | |
8641 | #define AUD_CONFIG_UPPER_N_SHIFT 20 | |
c46f111f | 8642 | #define AUD_CONFIG_UPPER_N_MASK (0xff << 20) |
b6daa025 | 8643 | #define AUD_CONFIG_LOWER_N_SHIFT 4 |
c46f111f | 8644 | #define AUD_CONFIG_LOWER_N_MASK (0xfff << 4) |
2561389a JN |
8645 | #define AUD_CONFIG_N_MASK (AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK) |
8646 | #define AUD_CONFIG_N(n) \ | |
8647 | (((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) | \ | |
8648 | (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT)) | |
b6daa025 | 8649 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 |
1a91510d JN |
8650 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16) |
8651 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16) | |
8652 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16) | |
8653 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16) | |
8654 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16) | |
8655 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16) | |
8656 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16) | |
8657 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16) | |
8658 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16) | |
8659 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16) | |
8660 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16) | |
b6daa025 WF |
8661 | #define AUD_CONFIG_DISABLE_NCTS (1 << 3) |
8662 | ||
9a78b6cc | 8663 | /* HSW Audio */ |
c46f111f JN |
8664 | #define _HSW_AUD_CONFIG_A 0x65000 |
8665 | #define _HSW_AUD_CONFIG_B 0x65100 | |
f0f59a00 | 8666 | #define HSW_AUD_CFG(pipe) _MMIO_PIPE(pipe, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B) |
c46f111f JN |
8667 | |
8668 | #define _HSW_AUD_MISC_CTRL_A 0x65010 | |
8669 | #define _HSW_AUD_MISC_CTRL_B 0x65110 | |
f0f59a00 | 8670 | #define HSW_AUD_MISC_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B) |
c46f111f | 8671 | |
6014ac12 LY |
8672 | #define _HSW_AUD_M_CTS_ENABLE_A 0x65028 |
8673 | #define _HSW_AUD_M_CTS_ENABLE_B 0x65128 | |
8674 | #define HSW_AUD_M_CTS_ENABLE(pipe) _MMIO_PIPE(pipe, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B) | |
8675 | #define AUD_M_CTS_M_VALUE_INDEX (1 << 21) | |
8676 | #define AUD_M_CTS_M_PROG_ENABLE (1 << 20) | |
8677 | #define AUD_CONFIG_M_MASK 0xfffff | |
8678 | ||
c46f111f JN |
8679 | #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 |
8680 | #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 | |
f0f59a00 | 8681 | #define HSW_AUD_DIP_ELD_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B) |
9a78b6cc WX |
8682 | |
8683 | /* Audio Digital Converter */ | |
c46f111f JN |
8684 | #define _HSW_AUD_DIG_CNVT_1 0x65080 |
8685 | #define _HSW_AUD_DIG_CNVT_2 0x65180 | |
f0f59a00 | 8686 | #define AUD_DIG_CNVT(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2) |
c46f111f JN |
8687 | #define DIP_PORT_SEL_MASK 0x3 |
8688 | ||
8689 | #define _HSW_AUD_EDID_DATA_A 0x65050 | |
8690 | #define _HSW_AUD_EDID_DATA_B 0x65150 | |
f0f59a00 | 8691 | #define HSW_AUD_EDID_DATA(pipe) _MMIO_PIPE(pipe, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B) |
c46f111f | 8692 | |
f0f59a00 VS |
8693 | #define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c) |
8694 | #define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0) | |
82910ac6 JN |
8695 | #define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4)) |
8696 | #define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4)) | |
8697 | #define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4)) | |
8698 | #define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4)) | |
9a78b6cc | 8699 | |
f0f59a00 | 8700 | #define HSW_AUD_CHICKENBIT _MMIO(0x65f10) |
632f3ab9 LH |
8701 | #define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15) |
8702 | ||
9eb3a752 | 8703 | /* HSW Power Wells */ |
9c3a16c8 ID |
8704 | #define _HSW_PWR_WELL_CTL1 0x45400 |
8705 | #define _HSW_PWR_WELL_CTL2 0x45404 | |
8706 | #define _HSW_PWR_WELL_CTL3 0x45408 | |
8707 | #define _HSW_PWR_WELL_CTL4 0x4540C | |
8708 | ||
67ca07e7 ID |
8709 | #define _ICL_PWR_WELL_CTL_AUX1 0x45440 |
8710 | #define _ICL_PWR_WELL_CTL_AUX2 0x45444 | |
8711 | #define _ICL_PWR_WELL_CTL_AUX4 0x4544C | |
8712 | ||
8713 | #define _ICL_PWR_WELL_CTL_DDI1 0x45450 | |
8714 | #define _ICL_PWR_WELL_CTL_DDI2 0x45454 | |
8715 | #define _ICL_PWR_WELL_CTL_DDI4 0x4545C | |
8716 | ||
9c3a16c8 ID |
8717 | /* |
8718 | * Each power well control register contains up to 16 (request, status) HW | |
8719 | * flag tuples. The register index and HW flag shift is determined by the | |
8720 | * power well ID (see i915_power_well_id). There are 4 possible sources of | |
8721 | * power well requests each source having its own set of control registers: | |
8722 | * BIOS, DRIVER, KVMR, DEBUG. | |
8723 | */ | |
8724 | #define _HSW_PW_REG_IDX(pw) ((pw) >> 4) | |
8725 | #define _HSW_PW_SHIFT(pw) (((pw) & 0xf) * 2) | |
9c3a16c8 | 8726 | #define HSW_PWR_WELL_CTL_BIOS(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \ |
67ca07e7 ID |
8727 | _HSW_PWR_WELL_CTL1, \ |
8728 | _ICL_PWR_WELL_CTL_AUX1, \ | |
8729 | _ICL_PWR_WELL_CTL_DDI1)) | |
9c3a16c8 | 8730 | #define HSW_PWR_WELL_CTL_DRIVER(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \ |
67ca07e7 ID |
8731 | _HSW_PWR_WELL_CTL2, \ |
8732 | _ICL_PWR_WELL_CTL_AUX2, \ | |
8733 | _ICL_PWR_WELL_CTL_DDI2)) | |
8734 | /* KVMR doesn't have a reg for AUX or DDI power well control */ | |
9c3a16c8 ID |
8735 | #define HSW_PWR_WELL_CTL_KVMR _MMIO(_HSW_PWR_WELL_CTL3) |
8736 | #define HSW_PWR_WELL_CTL_DEBUG(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \ | |
67ca07e7 ID |
8737 | _HSW_PWR_WELL_CTL4, \ |
8738 | _ICL_PWR_WELL_CTL_AUX4, \ | |
8739 | _ICL_PWR_WELL_CTL_DDI4)) | |
9c3a16c8 | 8740 | |
1af474fe ID |
8741 | #define HSW_PWR_WELL_CTL_REQ(pw) (1 << (_HSW_PW_SHIFT(pw) + 1)) |
8742 | #define HSW_PWR_WELL_CTL_STATE(pw) (1 << _HSW_PW_SHIFT(pw)) | |
f0f59a00 | 8743 | #define HSW_PWR_WELL_CTL5 _MMIO(0x45410) |
5ee8ee86 PZ |
8744 | #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31) |
8745 | #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20) | |
8746 | #define HSW_PWR_WELL_FORCE_ON (1 << 19) | |
f0f59a00 | 8747 | #define HSW_PWR_WELL_CTL6 _MMIO(0x45414) |
9eb3a752 | 8748 | |
94dd5138 | 8749 | /* SKL Fuse Status */ |
b2891eb2 ID |
8750 | enum skl_power_gate { |
8751 | SKL_PG0, | |
8752 | SKL_PG1, | |
8753 | SKL_PG2, | |
8754 | }; | |
8755 | ||
f0f59a00 | 8756 | #define SKL_FUSE_STATUS _MMIO(0x42000) |
5ee8ee86 | 8757 | #define SKL_FUSE_DOWNLOAD_STATUS (1 << 31) |
b2891eb2 ID |
8758 | /* PG0 (HW control->no power well ID), PG1..PG2 (SKL_DISP_PW1..SKL_DISP_PW2) */ |
8759 | #define SKL_PW_TO_PG(pw) ((pw) - SKL_DISP_PW_1 + SKL_PG1) | |
67ca07e7 ID |
8760 | /* PG0 (HW control->no power well ID), PG1..PG4 (ICL_DISP_PW1..ICL_DISP_PW4) */ |
8761 | #define ICL_PW_TO_PG(pw) ((pw) - ICL_DISP_PW_1 + SKL_PG1) | |
b2891eb2 | 8762 | #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg))) |
94dd5138 | 8763 | |
c559c2a0 | 8764 | #define _CNL_AUX_REG_IDX(pw) ((pw) - 9) |
ddd39e4b LDM |
8765 | #define _CNL_AUX_ANAOVRD1_B 0x162250 |
8766 | #define _CNL_AUX_ANAOVRD1_C 0x162210 | |
8767 | #define _CNL_AUX_ANAOVRD1_D 0x1622D0 | |
b1ae6a8b | 8768 | #define _CNL_AUX_ANAOVRD1_F 0x162A90 |
ddd39e4b LDM |
8769 | #define CNL_AUX_ANAOVRD1(pw) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw), \ |
8770 | _CNL_AUX_ANAOVRD1_B, \ | |
8771 | _CNL_AUX_ANAOVRD1_C, \ | |
b1ae6a8b RV |
8772 | _CNL_AUX_ANAOVRD1_D, \ |
8773 | _CNL_AUX_ANAOVRD1_F)) | |
5ee8ee86 PZ |
8774 | #define CNL_AUX_ANAOVRD1_ENABLE (1 << 16) |
8775 | #define CNL_AUX_ANAOVRD1_LDO_BYPASS (1 << 23) | |
ddd39e4b | 8776 | |
ee5e5e7a | 8777 | /* HDCP Key Registers */ |
2834d9df | 8778 | #define HDCP_KEY_CONF _MMIO(0x66c00) |
ee5e5e7a SP |
8779 | #define HDCP_AKSV_SEND_TRIGGER BIT(31) |
8780 | #define HDCP_CLEAR_KEYS_TRIGGER BIT(30) | |
fdddd08c | 8781 | #define HDCP_KEY_LOAD_TRIGGER BIT(8) |
2834d9df R |
8782 | #define HDCP_KEY_STATUS _MMIO(0x66c04) |
8783 | #define HDCP_FUSE_IN_PROGRESS BIT(7) | |
ee5e5e7a | 8784 | #define HDCP_FUSE_ERROR BIT(6) |
2834d9df R |
8785 | #define HDCP_FUSE_DONE BIT(5) |
8786 | #define HDCP_KEY_LOAD_STATUS BIT(1) | |
ee5e5e7a | 8787 | #define HDCP_KEY_LOAD_DONE BIT(0) |
2834d9df R |
8788 | #define HDCP_AKSV_LO _MMIO(0x66c10) |
8789 | #define HDCP_AKSV_HI _MMIO(0x66c14) | |
ee5e5e7a SP |
8790 | |
8791 | /* HDCP Repeater Registers */ | |
2834d9df R |
8792 | #define HDCP_REP_CTL _MMIO(0x66d00) |
8793 | #define HDCP_DDIB_REP_PRESENT BIT(30) | |
8794 | #define HDCP_DDIA_REP_PRESENT BIT(29) | |
8795 | #define HDCP_DDIC_REP_PRESENT BIT(28) | |
8796 | #define HDCP_DDID_REP_PRESENT BIT(27) | |
8797 | #define HDCP_DDIF_REP_PRESENT BIT(26) | |
8798 | #define HDCP_DDIE_REP_PRESENT BIT(25) | |
ee5e5e7a SP |
8799 | #define HDCP_DDIB_SHA1_M0 (1 << 20) |
8800 | #define HDCP_DDIA_SHA1_M0 (2 << 20) | |
8801 | #define HDCP_DDIC_SHA1_M0 (3 << 20) | |
8802 | #define HDCP_DDID_SHA1_M0 (4 << 20) | |
8803 | #define HDCP_DDIF_SHA1_M0 (5 << 20) | |
8804 | #define HDCP_DDIE_SHA1_M0 (6 << 20) /* Bspec says 5? */ | |
2834d9df | 8805 | #define HDCP_SHA1_BUSY BIT(16) |
ee5e5e7a SP |
8806 | #define HDCP_SHA1_READY BIT(17) |
8807 | #define HDCP_SHA1_COMPLETE BIT(18) | |
8808 | #define HDCP_SHA1_V_MATCH BIT(19) | |
8809 | #define HDCP_SHA1_TEXT_32 (1 << 1) | |
8810 | #define HDCP_SHA1_COMPLETE_HASH (2 << 1) | |
8811 | #define HDCP_SHA1_TEXT_24 (4 << 1) | |
8812 | #define HDCP_SHA1_TEXT_16 (5 << 1) | |
8813 | #define HDCP_SHA1_TEXT_8 (6 << 1) | |
8814 | #define HDCP_SHA1_TEXT_0 (7 << 1) | |
8815 | #define HDCP_SHA_V_PRIME_H0 _MMIO(0x66d04) | |
8816 | #define HDCP_SHA_V_PRIME_H1 _MMIO(0x66d08) | |
8817 | #define HDCP_SHA_V_PRIME_H2 _MMIO(0x66d0C) | |
8818 | #define HDCP_SHA_V_PRIME_H3 _MMIO(0x66d10) | |
8819 | #define HDCP_SHA_V_PRIME_H4 _MMIO(0x66d14) | |
9e8789ec | 8820 | #define HDCP_SHA_V_PRIME(h) _MMIO((0x66d04 + (h) * 4)) |
2834d9df | 8821 | #define HDCP_SHA_TEXT _MMIO(0x66d18) |
ee5e5e7a SP |
8822 | |
8823 | /* HDCP Auth Registers */ | |
8824 | #define _PORTA_HDCP_AUTHENC 0x66800 | |
8825 | #define _PORTB_HDCP_AUTHENC 0x66500 | |
8826 | #define _PORTC_HDCP_AUTHENC 0x66600 | |
8827 | #define _PORTD_HDCP_AUTHENC 0x66700 | |
8828 | #define _PORTE_HDCP_AUTHENC 0x66A00 | |
8829 | #define _PORTF_HDCP_AUTHENC 0x66900 | |
8830 | #define _PORT_HDCP_AUTHENC(port, x) _MMIO(_PICK(port, \ | |
8831 | _PORTA_HDCP_AUTHENC, \ | |
8832 | _PORTB_HDCP_AUTHENC, \ | |
8833 | _PORTC_HDCP_AUTHENC, \ | |
8834 | _PORTD_HDCP_AUTHENC, \ | |
8835 | _PORTE_HDCP_AUTHENC, \ | |
9e8789ec | 8836 | _PORTF_HDCP_AUTHENC) + (x)) |
2834d9df R |
8837 | #define PORT_HDCP_CONF(port) _PORT_HDCP_AUTHENC(port, 0x0) |
8838 | #define HDCP_CONF_CAPTURE_AN BIT(0) | |
8839 | #define HDCP_CONF_AUTH_AND_ENC (BIT(1) | BIT(0)) | |
8840 | #define PORT_HDCP_ANINIT(port) _PORT_HDCP_AUTHENC(port, 0x4) | |
8841 | #define PORT_HDCP_ANLO(port) _PORT_HDCP_AUTHENC(port, 0x8) | |
8842 | #define PORT_HDCP_ANHI(port) _PORT_HDCP_AUTHENC(port, 0xC) | |
8843 | #define PORT_HDCP_BKSVLO(port) _PORT_HDCP_AUTHENC(port, 0x10) | |
8844 | #define PORT_HDCP_BKSVHI(port) _PORT_HDCP_AUTHENC(port, 0x14) | |
8845 | #define PORT_HDCP_RPRIME(port) _PORT_HDCP_AUTHENC(port, 0x18) | |
8846 | #define PORT_HDCP_STATUS(port) _PORT_HDCP_AUTHENC(port, 0x1C) | |
ee5e5e7a SP |
8847 | #define HDCP_STATUS_STREAM_A_ENC BIT(31) |
8848 | #define HDCP_STATUS_STREAM_B_ENC BIT(30) | |
8849 | #define HDCP_STATUS_STREAM_C_ENC BIT(29) | |
8850 | #define HDCP_STATUS_STREAM_D_ENC BIT(28) | |
8851 | #define HDCP_STATUS_AUTH BIT(21) | |
8852 | #define HDCP_STATUS_ENC BIT(20) | |
2834d9df R |
8853 | #define HDCP_STATUS_RI_MATCH BIT(19) |
8854 | #define HDCP_STATUS_R0_READY BIT(18) | |
8855 | #define HDCP_STATUS_AN_READY BIT(17) | |
ee5e5e7a | 8856 | #define HDCP_STATUS_CIPHER BIT(16) |
9e8789ec | 8857 | #define HDCP_STATUS_FRAME_CNT(x) (((x) >> 8) & 0xff) |
ee5e5e7a | 8858 | |
e7e104c3 | 8859 | /* Per-pipe DDI Function Control */ |
086f8e84 VS |
8860 | #define _TRANS_DDI_FUNC_CTL_A 0x60400 |
8861 | #define _TRANS_DDI_FUNC_CTL_B 0x61400 | |
8862 | #define _TRANS_DDI_FUNC_CTL_C 0x62400 | |
8863 | #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400 | |
f0f59a00 | 8864 | #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A) |
a57c774a | 8865 | |
5ee8ee86 | 8866 | #define TRANS_DDI_FUNC_ENABLE (1 << 31) |
e7e104c3 | 8867 | /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ |
5ee8ee86 | 8868 | #define TRANS_DDI_PORT_MASK (7 << 28) |
26804afd | 8869 | #define TRANS_DDI_PORT_SHIFT 28 |
5ee8ee86 PZ |
8870 | #define TRANS_DDI_SELECT_PORT(x) ((x) << 28) |
8871 | #define TRANS_DDI_PORT_NONE (0 << 28) | |
8872 | #define TRANS_DDI_MODE_SELECT_MASK (7 << 24) | |
8873 | #define TRANS_DDI_MODE_SELECT_HDMI (0 << 24) | |
8874 | #define TRANS_DDI_MODE_SELECT_DVI (1 << 24) | |
8875 | #define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24) | |
8876 | #define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24) | |
8877 | #define TRANS_DDI_MODE_SELECT_FDI (4 << 24) | |
8878 | #define TRANS_DDI_BPC_MASK (7 << 20) | |
8879 | #define TRANS_DDI_BPC_8 (0 << 20) | |
8880 | #define TRANS_DDI_BPC_10 (1 << 20) | |
8881 | #define TRANS_DDI_BPC_6 (2 << 20) | |
8882 | #define TRANS_DDI_BPC_12 (3 << 20) | |
8883 | #define TRANS_DDI_PVSYNC (1 << 17) | |
8884 | #define TRANS_DDI_PHSYNC (1 << 16) | |
8885 | #define TRANS_DDI_EDP_INPUT_MASK (7 << 12) | |
8886 | #define TRANS_DDI_EDP_INPUT_A_ON (0 << 12) | |
8887 | #define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12) | |
8888 | #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12) | |
8889 | #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12) | |
8890 | #define TRANS_DDI_HDCP_SIGNALLING (1 << 9) | |
8891 | #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8) | |
8892 | #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7) | |
8893 | #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6) | |
8894 | #define TRANS_DDI_BFI_ENABLE (1 << 4) | |
8895 | #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4) | |
8896 | #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0) | |
15953637 SS |
8897 | #define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \ |
8898 | | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \ | |
8899 | | TRANS_DDI_HDMI_SCRAMBLING) | |
e7e104c3 | 8900 | |
0e87f667 | 8901 | /* DisplayPort Transport Control */ |
086f8e84 VS |
8902 | #define _DP_TP_CTL_A 0x64040 |
8903 | #define _DP_TP_CTL_B 0x64140 | |
f0f59a00 | 8904 | #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) |
5ee8ee86 PZ |
8905 | #define DP_TP_CTL_ENABLE (1 << 31) |
8906 | #define DP_TP_CTL_MODE_SST (0 << 27) | |
8907 | #define DP_TP_CTL_MODE_MST (1 << 27) | |
8908 | #define DP_TP_CTL_FORCE_ACT (1 << 25) | |
8909 | #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18) | |
8910 | #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15) | |
8911 | #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8) | |
8912 | #define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8) | |
8913 | #define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8) | |
8914 | #define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8) | |
8915 | #define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8) | |
8916 | #define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8) | |
8917 | #define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8) | |
8918 | #define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7) | |
0e87f667 | 8919 | |
e411b2c1 | 8920 | /* DisplayPort Transport Status */ |
086f8e84 VS |
8921 | #define _DP_TP_STATUS_A 0x64044 |
8922 | #define _DP_TP_STATUS_B 0x64144 | |
f0f59a00 | 8923 | #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B) |
5ee8ee86 PZ |
8924 | #define DP_TP_STATUS_IDLE_DONE (1 << 25) |
8925 | #define DP_TP_STATUS_ACT_SENT (1 << 24) | |
8926 | #define DP_TP_STATUS_MODE_STATUS_MST (1 << 23) | |
8927 | #define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12) | |
01b887c3 DA |
8928 | #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8) |
8929 | #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4) | |
8930 | #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0) | |
e411b2c1 | 8931 | |
03f896a1 | 8932 | /* DDI Buffer Control */ |
086f8e84 VS |
8933 | #define _DDI_BUF_CTL_A 0x64000 |
8934 | #define _DDI_BUF_CTL_B 0x64100 | |
f0f59a00 | 8935 | #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) |
5ee8ee86 | 8936 | #define DDI_BUF_CTL_ENABLE (1 << 31) |
c5fe6a06 | 8937 | #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) |
5ee8ee86 PZ |
8938 | #define DDI_BUF_EMP_MASK (0xf << 24) |
8939 | #define DDI_BUF_PORT_REVERSAL (1 << 16) | |
8940 | #define DDI_BUF_IS_IDLE (1 << 7) | |
8941 | #define DDI_A_4_LANES (1 << 4) | |
17aa6be9 | 8942 | #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) |
90a6b7b0 VS |
8943 | #define DDI_PORT_WIDTH_MASK (7 << 1) |
8944 | #define DDI_PORT_WIDTH_SHIFT 1 | |
5ee8ee86 | 8945 | #define DDI_INIT_DISPLAY_DETECTED (1 << 0) |
03f896a1 | 8946 | |
bb879a44 | 8947 | /* DDI Buffer Translations */ |
086f8e84 VS |
8948 | #define _DDI_BUF_TRANS_A 0x64E00 |
8949 | #define _DDI_BUF_TRANS_B 0x64E60 | |
f0f59a00 | 8950 | #define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8) |
c110ae6c | 8951 | #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31) |
f0f59a00 | 8952 | #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4) |
bb879a44 | 8953 | |
7501a4d8 ED |
8954 | /* Sideband Interface (SBI) is programmed indirectly, via |
8955 | * SBI_ADDR, which contains the register offset; and SBI_DATA, | |
8956 | * which contains the payload */ | |
f0f59a00 VS |
8957 | #define SBI_ADDR _MMIO(0xC6000) |
8958 | #define SBI_DATA _MMIO(0xC6004) | |
8959 | #define SBI_CTL_STAT _MMIO(0xC6008) | |
5ee8ee86 PZ |
8960 | #define SBI_CTL_DEST_ICLK (0x0 << 16) |
8961 | #define SBI_CTL_DEST_MPHY (0x1 << 16) | |
8962 | #define SBI_CTL_OP_IORD (0x2 << 8) | |
8963 | #define SBI_CTL_OP_IOWR (0x3 << 8) | |
8964 | #define SBI_CTL_OP_CRRD (0x6 << 8) | |
8965 | #define SBI_CTL_OP_CRWR (0x7 << 8) | |
8966 | #define SBI_RESPONSE_FAIL (0x1 << 1) | |
8967 | #define SBI_RESPONSE_SUCCESS (0x0 << 1) | |
8968 | #define SBI_BUSY (0x1 << 0) | |
8969 | #define SBI_READY (0x0 << 0) | |
52f025ef | 8970 | |
ccf1c867 | 8971 | /* SBI offsets */ |
f7be2c21 | 8972 | #define SBI_SSCDIVINTPHASE 0x0200 |
5e49cea6 | 8973 | #define SBI_SSCDIVINTPHASE6 0x0600 |
8802e5b6 | 8974 | #define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1 |
5ee8ee86 PZ |
8975 | #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1) |
8976 | #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1) | |
8802e5b6 | 8977 | #define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8 |
5ee8ee86 PZ |
8978 | #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8) |
8979 | #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8) | |
8980 | #define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15) | |
8981 | #define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0) | |
f7be2c21 | 8982 | #define SBI_SSCDITHPHASE 0x0204 |
5e49cea6 | 8983 | #define SBI_SSCCTL 0x020c |
ccf1c867 | 8984 | #define SBI_SSCCTL6 0x060C |
5ee8ee86 PZ |
8985 | #define SBI_SSCCTL_PATHALT (1 << 3) |
8986 | #define SBI_SSCCTL_DISABLE (1 << 0) | |
ccf1c867 | 8987 | #define SBI_SSCAUXDIV6 0x0610 |
8802e5b6 | 8988 | #define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4 |
5ee8ee86 PZ |
8989 | #define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4) |
8990 | #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4) | |
5e49cea6 | 8991 | #define SBI_DBUFF0 0x2a00 |
2fa86a1f | 8992 | #define SBI_GEN0 0x1f00 |
5ee8ee86 | 8993 | #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0) |
ccf1c867 | 8994 | |
52f025ef | 8995 | /* LPT PIXCLK_GATE */ |
f0f59a00 | 8996 | #define PIXCLK_GATE _MMIO(0xC6020) |
5ee8ee86 PZ |
8997 | #define PIXCLK_GATE_UNGATE (1 << 0) |
8998 | #define PIXCLK_GATE_GATE (0 << 0) | |
52f025ef | 8999 | |
e93ea06a | 9000 | /* SPLL */ |
f0f59a00 | 9001 | #define SPLL_CTL _MMIO(0x46020) |
5ee8ee86 PZ |
9002 | #define SPLL_PLL_ENABLE (1 << 31) |
9003 | #define SPLL_PLL_SSC (1 << 28) | |
9004 | #define SPLL_PLL_NON_SSC (2 << 28) | |
9005 | #define SPLL_PLL_LCPLL (3 << 28) | |
9006 | #define SPLL_PLL_REF_MASK (3 << 28) | |
9007 | #define SPLL_PLL_FREQ_810MHz (0 << 26) | |
9008 | #define SPLL_PLL_FREQ_1350MHz (1 << 26) | |
9009 | #define SPLL_PLL_FREQ_2700MHz (2 << 26) | |
9010 | #define SPLL_PLL_FREQ_MASK (3 << 26) | |
e93ea06a | 9011 | |
4dffc404 | 9012 | /* WRPLL */ |
086f8e84 VS |
9013 | #define _WRPLL_CTL1 0x46040 |
9014 | #define _WRPLL_CTL2 0x46060 | |
f0f59a00 | 9015 | #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2) |
5ee8ee86 PZ |
9016 | #define WRPLL_PLL_ENABLE (1 << 31) |
9017 | #define WRPLL_PLL_SSC (1 << 28) | |
9018 | #define WRPLL_PLL_NON_SSC (2 << 28) | |
9019 | #define WRPLL_PLL_LCPLL (3 << 28) | |
9020 | #define WRPLL_PLL_REF_MASK (3 << 28) | |
ef4d084f | 9021 | /* WRPLL divider programming */ |
5ee8ee86 | 9022 | #define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0) |
11578553 | 9023 | #define WRPLL_DIVIDER_REF_MASK (0xff) |
5ee8ee86 PZ |
9024 | #define WRPLL_DIVIDER_POST(x) ((x) << 8) |
9025 | #define WRPLL_DIVIDER_POST_MASK (0x3f << 8) | |
11578553 | 9026 | #define WRPLL_DIVIDER_POST_SHIFT 8 |
5ee8ee86 | 9027 | #define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16) |
11578553 | 9028 | #define WRPLL_DIVIDER_FB_SHIFT 16 |
5ee8ee86 | 9029 | #define WRPLL_DIVIDER_FB_MASK (0xff << 16) |
4dffc404 | 9030 | |
fec9181c | 9031 | /* Port clock selection */ |
086f8e84 VS |
9032 | #define _PORT_CLK_SEL_A 0x46100 |
9033 | #define _PORT_CLK_SEL_B 0x46104 | |
f0f59a00 | 9034 | #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B) |
5ee8ee86 PZ |
9035 | #define PORT_CLK_SEL_LCPLL_2700 (0 << 29) |
9036 | #define PORT_CLK_SEL_LCPLL_1350 (1 << 29) | |
9037 | #define PORT_CLK_SEL_LCPLL_810 (2 << 29) | |
9038 | #define PORT_CLK_SEL_SPLL (3 << 29) | |
9039 | #define PORT_CLK_SEL_WRPLL(pll) (((pll) + 4) << 29) | |
9040 | #define PORT_CLK_SEL_WRPLL1 (4 << 29) | |
9041 | #define PORT_CLK_SEL_WRPLL2 (5 << 29) | |
9042 | #define PORT_CLK_SEL_NONE (7 << 29) | |
9043 | #define PORT_CLK_SEL_MASK (7 << 29) | |
fec9181c | 9044 | |
78b60ce7 PZ |
9045 | /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */ |
9046 | #define DDI_CLK_SEL(port) PORT_CLK_SEL(port) | |
9047 | #define DDI_CLK_SEL_NONE (0x0 << 28) | |
9048 | #define DDI_CLK_SEL_MG (0x8 << 28) | |
1fa11ee2 PZ |
9049 | #define DDI_CLK_SEL_TBT_162 (0xC << 28) |
9050 | #define DDI_CLK_SEL_TBT_270 (0xD << 28) | |
9051 | #define DDI_CLK_SEL_TBT_540 (0xE << 28) | |
9052 | #define DDI_CLK_SEL_TBT_810 (0xF << 28) | |
78b60ce7 PZ |
9053 | #define DDI_CLK_SEL_MASK (0xF << 28) |
9054 | ||
bb523fc0 | 9055 | /* Transcoder clock selection */ |
086f8e84 VS |
9056 | #define _TRANS_CLK_SEL_A 0x46140 |
9057 | #define _TRANS_CLK_SEL_B 0x46144 | |
f0f59a00 | 9058 | #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B) |
bb523fc0 | 9059 | /* For each transcoder, we need to select the corresponding port clock */ |
5ee8ee86 PZ |
9060 | #define TRANS_CLK_SEL_DISABLED (0x0 << 29) |
9061 | #define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29) | |
fec9181c | 9062 | |
7f1052a8 VS |
9063 | #define CDCLK_FREQ _MMIO(0x46200) |
9064 | ||
086f8e84 VS |
9065 | #define _TRANSA_MSA_MISC 0x60410 |
9066 | #define _TRANSB_MSA_MISC 0x61410 | |
9067 | #define _TRANSC_MSA_MISC 0x62410 | |
9068 | #define _TRANS_EDP_MSA_MISC 0x6f410 | |
f0f59a00 | 9069 | #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC) |
a57c774a | 9070 | |
5ee8ee86 PZ |
9071 | #define TRANS_MSA_SYNC_CLK (1 << 0) |
9072 | #define TRANS_MSA_6_BPC (0 << 5) | |
9073 | #define TRANS_MSA_8_BPC (1 << 5) | |
9074 | #define TRANS_MSA_10_BPC (2 << 5) | |
9075 | #define TRANS_MSA_12_BPC (3 << 5) | |
9076 | #define TRANS_MSA_16_BPC (4 << 5) | |
dae84799 | 9077 | |
90e8d31c | 9078 | /* LCPLL Control */ |
f0f59a00 | 9079 | #define LCPLL_CTL _MMIO(0x130040) |
5ee8ee86 PZ |
9080 | #define LCPLL_PLL_DISABLE (1 << 31) |
9081 | #define LCPLL_PLL_LOCK (1 << 30) | |
9082 | #define LCPLL_CLK_FREQ_MASK (3 << 26) | |
9083 | #define LCPLL_CLK_FREQ_450 (0 << 26) | |
9084 | #define LCPLL_CLK_FREQ_54O_BDW (1 << 26) | |
9085 | #define LCPLL_CLK_FREQ_337_5_BDW (2 << 26) | |
9086 | #define LCPLL_CLK_FREQ_675_BDW (3 << 26) | |
9087 | #define LCPLL_CD_CLOCK_DISABLE (1 << 25) | |
9088 | #define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24) | |
9089 | #define LCPLL_CD2X_CLOCK_DISABLE (1 << 23) | |
9090 | #define LCPLL_POWER_DOWN_ALLOW (1 << 22) | |
9091 | #define LCPLL_CD_SOURCE_FCLK (1 << 21) | |
9092 | #define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19) | |
be256dc7 | 9093 | |
326ac39b S |
9094 | /* |
9095 | * SKL Clocks | |
9096 | */ | |
9097 | ||
9098 | /* CDCLK_CTL */ | |
f0f59a00 | 9099 | #define CDCLK_CTL _MMIO(0x46000) |
186a277e PZ |
9100 | #define CDCLK_FREQ_SEL_MASK (3 << 26) |
9101 | #define CDCLK_FREQ_450_432 (0 << 26) | |
9102 | #define CDCLK_FREQ_540 (1 << 26) | |
9103 | #define CDCLK_FREQ_337_308 (2 << 26) | |
9104 | #define CDCLK_FREQ_675_617 (3 << 26) | |
9105 | #define BXT_CDCLK_CD2X_DIV_SEL_MASK (3 << 22) | |
9106 | #define BXT_CDCLK_CD2X_DIV_SEL_1 (0 << 22) | |
9107 | #define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1 << 22) | |
9108 | #define BXT_CDCLK_CD2X_DIV_SEL_2 (2 << 22) | |
9109 | #define BXT_CDCLK_CD2X_DIV_SEL_4 (3 << 22) | |
9110 | #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20) | |
9111 | #define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19) | |
7fe62757 | 9112 | #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3) |
186a277e PZ |
9113 | #define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19) |
9114 | #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16) | |
7fe62757 | 9115 | #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) |
f8437dd1 | 9116 | |
326ac39b | 9117 | /* LCPLL_CTL */ |
f0f59a00 VS |
9118 | #define LCPLL1_CTL _MMIO(0x46010) |
9119 | #define LCPLL2_CTL _MMIO(0x46014) | |
5ee8ee86 | 9120 | #define LCPLL_PLL_ENABLE (1 << 31) |
326ac39b S |
9121 | |
9122 | /* DPLL control1 */ | |
f0f59a00 | 9123 | #define DPLL_CTRL1 _MMIO(0x6C058) |
5ee8ee86 PZ |
9124 | #define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5)) |
9125 | #define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4)) | |
9126 | #define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1)) | |
9127 | #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1) | |
9128 | #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1)) | |
9129 | #define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6)) | |
71cd8423 DL |
9130 | #define DPLL_CTRL1_LINK_RATE_2700 0 |
9131 | #define DPLL_CTRL1_LINK_RATE_1350 1 | |
9132 | #define DPLL_CTRL1_LINK_RATE_810 2 | |
9133 | #define DPLL_CTRL1_LINK_RATE_1620 3 | |
9134 | #define DPLL_CTRL1_LINK_RATE_1080 4 | |
9135 | #define DPLL_CTRL1_LINK_RATE_2160 5 | |
326ac39b S |
9136 | |
9137 | /* DPLL control2 */ | |
f0f59a00 | 9138 | #define DPLL_CTRL2 _MMIO(0x6C05C) |
5ee8ee86 PZ |
9139 | #define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15)) |
9140 | #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1)) | |
9141 | #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1) | |
9142 | #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1)) | |
9143 | #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3)) | |
326ac39b S |
9144 | |
9145 | /* DPLL Status */ | |
f0f59a00 | 9146 | #define DPLL_STATUS _MMIO(0x6C060) |
5ee8ee86 | 9147 | #define DPLL_LOCK(id) (1 << ((id) * 8)) |
326ac39b S |
9148 | |
9149 | /* DPLL cfg */ | |
086f8e84 VS |
9150 | #define _DPLL1_CFGCR1 0x6C040 |
9151 | #define _DPLL2_CFGCR1 0x6C048 | |
9152 | #define _DPLL3_CFGCR1 0x6C050 | |
5ee8ee86 PZ |
9153 | #define DPLL_CFGCR1_FREQ_ENABLE (1 << 31) |
9154 | #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9) | |
9155 | #define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9) | |
326ac39b S |
9156 | #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) |
9157 | ||
086f8e84 VS |
9158 | #define _DPLL1_CFGCR2 0x6C044 |
9159 | #define _DPLL2_CFGCR2 0x6C04C | |
9160 | #define _DPLL3_CFGCR2 0x6C054 | |
5ee8ee86 PZ |
9161 | #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8) |
9162 | #define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8) | |
9163 | #define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7) | |
9164 | #define DPLL_CFGCR2_KDIV_MASK (3 << 5) | |
9165 | #define DPLL_CFGCR2_KDIV(x) ((x) << 5) | |
9166 | #define DPLL_CFGCR2_KDIV_5 (0 << 5) | |
9167 | #define DPLL_CFGCR2_KDIV_2 (1 << 5) | |
9168 | #define DPLL_CFGCR2_KDIV_3 (2 << 5) | |
9169 | #define DPLL_CFGCR2_KDIV_1 (3 << 5) | |
9170 | #define DPLL_CFGCR2_PDIV_MASK (7 << 2) | |
9171 | #define DPLL_CFGCR2_PDIV(x) ((x) << 2) | |
9172 | #define DPLL_CFGCR2_PDIV_1 (0 << 2) | |
9173 | #define DPLL_CFGCR2_PDIV_2 (1 << 2) | |
9174 | #define DPLL_CFGCR2_PDIV_3 (2 << 2) | |
9175 | #define DPLL_CFGCR2_PDIV_7 (4 << 2) | |
326ac39b S |
9176 | #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) |
9177 | ||
da3b891b | 9178 | #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1) |
f0f59a00 | 9179 | #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2) |
540e732c | 9180 | |
555e38d2 RV |
9181 | /* |
9182 | * CNL Clocks | |
9183 | */ | |
9184 | #define DPCLKA_CFGCR0 _MMIO(0x6C200) | |
78b60ce7 | 9185 | #define DPCLKA_CFGCR0_ICL _MMIO(0x164280) |
376faf8a | 9186 | #define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \ |
5ee8ee86 | 9187 | (port) + 10)) |
376faf8a | 9188 | #define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \ |
5ee8ee86 | 9189 | (port) * 2) |
376faf8a RV |
9190 | #define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)) |
9191 | #define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)) | |
555e38d2 | 9192 | |
a927c927 RV |
9193 | /* CNL PLL */ |
9194 | #define DPLL0_ENABLE 0x46010 | |
9195 | #define DPLL1_ENABLE 0x46014 | |
9196 | #define PLL_ENABLE (1 << 31) | |
9197 | #define PLL_LOCK (1 << 30) | |
9198 | #define PLL_POWER_ENABLE (1 << 27) | |
9199 | #define PLL_POWER_STATE (1 << 26) | |
9200 | #define CNL_DPLL_ENABLE(pll) _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE) | |
9201 | ||
1fa11ee2 PZ |
9202 | #define TBT_PLL_ENABLE _MMIO(0x46020) |
9203 | ||
78b60ce7 PZ |
9204 | #define _MG_PLL1_ENABLE 0x46030 |
9205 | #define _MG_PLL2_ENABLE 0x46034 | |
9206 | #define _MG_PLL3_ENABLE 0x46038 | |
9207 | #define _MG_PLL4_ENABLE 0x4603C | |
9208 | /* Bits are the same as DPLL0_ENABLE */ | |
9209 | #define MG_PLL_ENABLE(port) _MMIO_PORT((port) - PORT_C, _MG_PLL1_ENABLE, \ | |
9210 | _MG_PLL2_ENABLE) | |
9211 | ||
9212 | #define _MG_REFCLKIN_CTL_PORT1 0x16892C | |
9213 | #define _MG_REFCLKIN_CTL_PORT2 0x16992C | |
9214 | #define _MG_REFCLKIN_CTL_PORT3 0x16A92C | |
9215 | #define _MG_REFCLKIN_CTL_PORT4 0x16B92C | |
9216 | #define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x) << 8) | |
bd99ce08 | 9217 | #define MG_REFCLKIN_CTL_OD_2_MUX_MASK (0x7 << 8) |
78b60ce7 PZ |
9218 | #define MG_REFCLKIN_CTL(port) _MMIO_PORT((port) - PORT_C, \ |
9219 | _MG_REFCLKIN_CTL_PORT1, \ | |
9220 | _MG_REFCLKIN_CTL_PORT2) | |
9221 | ||
9222 | #define _MG_CLKTOP2_CORECLKCTL1_PORT1 0x1688D8 | |
9223 | #define _MG_CLKTOP2_CORECLKCTL1_PORT2 0x1698D8 | |
9224 | #define _MG_CLKTOP2_CORECLKCTL1_PORT3 0x16A8D8 | |
9225 | #define _MG_CLKTOP2_CORECLKCTL1_PORT4 0x16B8D8 | |
9226 | #define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x) ((x) << 16) | |
bd99ce08 | 9227 | #define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK (0xff << 16) |
78b60ce7 | 9228 | #define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8) |
bd99ce08 | 9229 | #define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK (0xff << 8) |
78b60ce7 PZ |
9230 | #define MG_CLKTOP2_CORECLKCTL1(port) _MMIO_PORT((port) - PORT_C, \ |
9231 | _MG_CLKTOP2_CORECLKCTL1_PORT1, \ | |
9232 | _MG_CLKTOP2_CORECLKCTL1_PORT2) | |
9233 | ||
9234 | #define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4 | |
9235 | #define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4 | |
9236 | #define _MG_CLKTOP2_HSCLKCTL_PORT3 0x16A8D4 | |
9237 | #define _MG_CLKTOP2_HSCLKCTL_PORT4 0x16B8D4 | |
9238 | #define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x) ((x) << 16) | |
bd99ce08 | 9239 | #define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK (0x1 << 16) |
78b60ce7 | 9240 | #define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14) |
bd99ce08 | 9241 | #define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK (0x3 << 14) |
78b60ce7 | 9242 | #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO(x) ((x) << 12) |
bd99ce08 | 9243 | #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK (0x3 << 12) |
78b60ce7 | 9244 | #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8) |
bd99ce08 | 9245 | #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8) |
78b60ce7 PZ |
9246 | #define MG_CLKTOP2_HSCLKCTL(port) _MMIO_PORT((port) - PORT_C, \ |
9247 | _MG_CLKTOP2_HSCLKCTL_PORT1, \ | |
9248 | _MG_CLKTOP2_HSCLKCTL_PORT2) | |
9249 | ||
9250 | #define _MG_PLL_DIV0_PORT1 0x168A00 | |
9251 | #define _MG_PLL_DIV0_PORT2 0x169A00 | |
9252 | #define _MG_PLL_DIV0_PORT3 0x16AA00 | |
9253 | #define _MG_PLL_DIV0_PORT4 0x16BA00 | |
9254 | #define MG_PLL_DIV0_FRACNEN_H (1 << 30) | |
9255 | #define MG_PLL_DIV0_FBDIV_FRAC(x) ((x) << 8) | |
9256 | #define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0) | |
9257 | #define MG_PLL_DIV0(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_DIV0_PORT1, \ | |
9258 | _MG_PLL_DIV0_PORT2) | |
9259 | ||
9260 | #define _MG_PLL_DIV1_PORT1 0x168A04 | |
9261 | #define _MG_PLL_DIV1_PORT2 0x169A04 | |
9262 | #define _MG_PLL_DIV1_PORT3 0x16AA04 | |
9263 | #define _MG_PLL_DIV1_PORT4 0x16BA04 | |
9264 | #define MG_PLL_DIV1_IREF_NDIVRATIO(x) ((x) << 16) | |
9265 | #define MG_PLL_DIV1_DITHER_DIV_1 (0 << 12) | |
9266 | #define MG_PLL_DIV1_DITHER_DIV_2 (1 << 12) | |
9267 | #define MG_PLL_DIV1_DITHER_DIV_4 (2 << 12) | |
9268 | #define MG_PLL_DIV1_DITHER_DIV_8 (3 << 12) | |
9269 | #define MG_PLL_DIV1_NDIVRATIO(x) ((x) << 4) | |
9270 | #define MG_PLL_DIV1_FBPREDIV(x) ((x) << 0) | |
9271 | #define MG_PLL_DIV1(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_DIV1_PORT1, \ | |
9272 | _MG_PLL_DIV1_PORT2) | |
9273 | ||
9274 | #define _MG_PLL_LF_PORT1 0x168A08 | |
9275 | #define _MG_PLL_LF_PORT2 0x169A08 | |
9276 | #define _MG_PLL_LF_PORT3 0x16AA08 | |
9277 | #define _MG_PLL_LF_PORT4 0x16BA08 | |
9278 | #define MG_PLL_LF_TDCTARGETCNT(x) ((x) << 24) | |
9279 | #define MG_PLL_LF_AFCCNTSEL_256 (0 << 20) | |
9280 | #define MG_PLL_LF_AFCCNTSEL_512 (1 << 20) | |
9281 | #define MG_PLL_LF_GAINCTRL(x) ((x) << 16) | |
9282 | #define MG_PLL_LF_INT_COEFF(x) ((x) << 8) | |
9283 | #define MG_PLL_LF_PROP_COEFF(x) ((x) << 0) | |
9284 | #define MG_PLL_LF(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_LF_PORT1, \ | |
9285 | _MG_PLL_LF_PORT2) | |
9286 | ||
9287 | #define _MG_PLL_FRAC_LOCK_PORT1 0x168A0C | |
9288 | #define _MG_PLL_FRAC_LOCK_PORT2 0x169A0C | |
9289 | #define _MG_PLL_FRAC_LOCK_PORT3 0x16AA0C | |
9290 | #define _MG_PLL_FRAC_LOCK_PORT4 0x16BA0C | |
9291 | #define MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 (1 << 18) | |
9292 | #define MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 (1 << 16) | |
9293 | #define MG_PLL_FRAC_LOCK_LOCKTHRESH(x) ((x) << 11) | |
9294 | #define MG_PLL_FRAC_LOCK_DCODITHEREN (1 << 10) | |
9295 | #define MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN (1 << 8) | |
9296 | #define MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x) ((x) << 0) | |
9297 | #define MG_PLL_FRAC_LOCK(port) _MMIO_PORT((port) - PORT_C, \ | |
9298 | _MG_PLL_FRAC_LOCK_PORT1, \ | |
9299 | _MG_PLL_FRAC_LOCK_PORT2) | |
9300 | ||
9301 | #define _MG_PLL_SSC_PORT1 0x168A10 | |
9302 | #define _MG_PLL_SSC_PORT2 0x169A10 | |
9303 | #define _MG_PLL_SSC_PORT3 0x16AA10 | |
9304 | #define _MG_PLL_SSC_PORT4 0x16BA10 | |
9305 | #define MG_PLL_SSC_EN (1 << 28) | |
9306 | #define MG_PLL_SSC_TYPE(x) ((x) << 26) | |
9307 | #define MG_PLL_SSC_STEPLENGTH(x) ((x) << 16) | |
9308 | #define MG_PLL_SSC_STEPNUM(x) ((x) << 10) | |
9309 | #define MG_PLL_SSC_FLLEN (1 << 9) | |
9310 | #define MG_PLL_SSC_STEPSIZE(x) ((x) << 0) | |
9311 | #define MG_PLL_SSC(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_SSC_PORT1, \ | |
9312 | _MG_PLL_SSC_PORT2) | |
9313 | ||
9314 | #define _MG_PLL_BIAS_PORT1 0x168A14 | |
9315 | #define _MG_PLL_BIAS_PORT2 0x169A14 | |
9316 | #define _MG_PLL_BIAS_PORT3 0x16AA14 | |
9317 | #define _MG_PLL_BIAS_PORT4 0x16BA14 | |
9318 | #define MG_PLL_BIAS_BIAS_GB_SEL(x) ((x) << 30) | |
bd99ce08 | 9319 | #define MG_PLL_BIAS_BIAS_GB_SEL_MASK (0x3 << 30) |
78b60ce7 | 9320 | #define MG_PLL_BIAS_INIT_DCOAMP(x) ((x) << 24) |
bd99ce08 | 9321 | #define MG_PLL_BIAS_INIT_DCOAMP_MASK (0x3f << 24) |
78b60ce7 | 9322 | #define MG_PLL_BIAS_BIAS_BONUS(x) ((x) << 16) |
bd99ce08 | 9323 | #define MG_PLL_BIAS_BIAS_BONUS_MASK (0xff << 16) |
78b60ce7 PZ |
9324 | #define MG_PLL_BIAS_BIASCAL_EN (1 << 15) |
9325 | #define MG_PLL_BIAS_CTRIM(x) ((x) << 8) | |
bd99ce08 | 9326 | #define MG_PLL_BIAS_CTRIM_MASK (0x1f << 8) |
78b60ce7 | 9327 | #define MG_PLL_BIAS_VREF_RDAC(x) ((x) << 5) |
bd99ce08 | 9328 | #define MG_PLL_BIAS_VREF_RDAC_MASK (0x7 << 5) |
78b60ce7 | 9329 | #define MG_PLL_BIAS_IREFTRIM(x) ((x) << 0) |
bd99ce08 | 9330 | #define MG_PLL_BIAS_IREFTRIM_MASK (0x1f << 0) |
78b60ce7 PZ |
9331 | #define MG_PLL_BIAS(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_BIAS_PORT1, \ |
9332 | _MG_PLL_BIAS_PORT2) | |
9333 | ||
9334 | #define _MG_PLL_TDC_COLDST_BIAS_PORT1 0x168A18 | |
9335 | #define _MG_PLL_TDC_COLDST_BIAS_PORT2 0x169A18 | |
9336 | #define _MG_PLL_TDC_COLDST_BIAS_PORT3 0x16AA18 | |
9337 | #define _MG_PLL_TDC_COLDST_BIAS_PORT4 0x16BA18 | |
9338 | #define MG_PLL_TDC_COLDST_IREFINT_EN (1 << 27) | |
9339 | #define MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x) ((x) << 17) | |
9340 | #define MG_PLL_TDC_COLDST_COLDSTART (1 << 16) | |
9341 | #define MG_PLL_TDC_TDCOVCCORR_EN (1 << 2) | |
9342 | #define MG_PLL_TDC_TDCSEL(x) ((x) << 0) | |
9343 | #define MG_PLL_TDC_COLDST_BIAS(port) _MMIO_PORT((port) - PORT_C, \ | |
9344 | _MG_PLL_TDC_COLDST_BIAS_PORT1, \ | |
9345 | _MG_PLL_TDC_COLDST_BIAS_PORT2) | |
9346 | ||
a927c927 RV |
9347 | #define _CNL_DPLL0_CFGCR0 0x6C000 |
9348 | #define _CNL_DPLL1_CFGCR0 0x6C080 | |
9349 | #define DPLL_CFGCR0_HDMI_MODE (1 << 30) | |
9350 | #define DPLL_CFGCR0_SSC_ENABLE (1 << 29) | |
78b60ce7 | 9351 | #define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25) |
a927c927 RV |
9352 | #define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25) |
9353 | #define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25) | |
9354 | #define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25) | |
9355 | #define DPLL_CFGCR0_LINK_RATE_810 (2 << 25) | |
9356 | #define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25) | |
9357 | #define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25) | |
9358 | #define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25) | |
9359 | #define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25) | |
9360 | #define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25) | |
9361 | #define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10) | |
442aa277 | 9362 | #define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10) |
a927c927 RV |
9363 | #define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10) |
9364 | #define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff) | |
9365 | #define CNL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0) | |
9366 | ||
9367 | #define _CNL_DPLL0_CFGCR1 0x6C004 | |
9368 | #define _CNL_DPLL1_CFGCR1 0x6C084 | |
9369 | #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10) | |
a9701a89 | 9370 | #define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10) |
a927c927 | 9371 | #define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10) |
51c83cfa | 9372 | #define DPLL_CFGCR1_QDIV_MODE_SHIFT (9) |
a927c927 RV |
9373 | #define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9) |
9374 | #define DPLL_CFGCR1_KDIV_MASK (7 << 6) | |
51c83cfa | 9375 | #define DPLL_CFGCR1_KDIV_SHIFT (6) |
a927c927 RV |
9376 | #define DPLL_CFGCR1_KDIV(x) ((x) << 6) |
9377 | #define DPLL_CFGCR1_KDIV_1 (1 << 6) | |
9378 | #define DPLL_CFGCR1_KDIV_2 (2 << 6) | |
9379 | #define DPLL_CFGCR1_KDIV_4 (4 << 6) | |
9380 | #define DPLL_CFGCR1_PDIV_MASK (0xf << 2) | |
51c83cfa | 9381 | #define DPLL_CFGCR1_PDIV_SHIFT (2) |
a927c927 RV |
9382 | #define DPLL_CFGCR1_PDIV(x) ((x) << 2) |
9383 | #define DPLL_CFGCR1_PDIV_2 (1 << 2) | |
9384 | #define DPLL_CFGCR1_PDIV_3 (2 << 2) | |
9385 | #define DPLL_CFGCR1_PDIV_5 (4 << 2) | |
9386 | #define DPLL_CFGCR1_PDIV_7 (8 << 2) | |
9387 | #define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0) | |
78b60ce7 | 9388 | #define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0) |
a927c927 RV |
9389 | #define CNL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1) |
9390 | ||
78b60ce7 PZ |
9391 | #define _ICL_DPLL0_CFGCR0 0x164000 |
9392 | #define _ICL_DPLL1_CFGCR0 0x164080 | |
9393 | #define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \ | |
9394 | _ICL_DPLL1_CFGCR0) | |
9395 | ||
9396 | #define _ICL_DPLL0_CFGCR1 0x164004 | |
9397 | #define _ICL_DPLL1_CFGCR1 0x164084 | |
9398 | #define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \ | |
9399 | _ICL_DPLL1_CFGCR1) | |
9400 | ||
f8437dd1 | 9401 | /* BXT display engine PLL */ |
f0f59a00 | 9402 | #define BXT_DE_PLL_CTL _MMIO(0x6d000) |
f8437dd1 VK |
9403 | #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */ |
9404 | #define BXT_DE_PLL_RATIO_MASK 0xff | |
9405 | ||
f0f59a00 | 9406 | #define BXT_DE_PLL_ENABLE _MMIO(0x46070) |
f8437dd1 VK |
9407 | #define BXT_DE_PLL_PLL_ENABLE (1 << 31) |
9408 | #define BXT_DE_PLL_LOCK (1 << 30) | |
945f2672 VS |
9409 | #define CNL_CDCLK_PLL_RATIO(x) (x) |
9410 | #define CNL_CDCLK_PLL_RATIO_MASK 0xff | |
f8437dd1 | 9411 | |
664326f8 | 9412 | /* GEN9 DC */ |
f0f59a00 | 9413 | #define DC_STATE_EN _MMIO(0x45504) |
13ae3a0d | 9414 | #define DC_STATE_DISABLE 0 |
5ee8ee86 PZ |
9415 | #define DC_STATE_EN_UPTO_DC5 (1 << 0) |
9416 | #define DC_STATE_EN_DC9 (1 << 3) | |
9417 | #define DC_STATE_EN_UPTO_DC6 (2 << 0) | |
6b457d31 SK |
9418 | #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3 |
9419 | ||
f0f59a00 | 9420 | #define DC_STATE_DEBUG _MMIO(0x45520) |
5ee8ee86 PZ |
9421 | #define DC_STATE_DEBUG_MASK_CORES (1 << 0) |
9422 | #define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1) | |
6b457d31 | 9423 | |
9ccd5aeb PZ |
9424 | /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, |
9425 | * since on HSW we can't write to it using I915_WRITE. */ | |
f0f59a00 VS |
9426 | #define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C) |
9427 | #define D_COMP_BDW _MMIO(0x138144) | |
5ee8ee86 PZ |
9428 | #define D_COMP_RCOMP_IN_PROGRESS (1 << 9) |
9429 | #define D_COMP_COMP_FORCE (1 << 8) | |
9430 | #define D_COMP_COMP_DISABLE (1 << 0) | |
90e8d31c | 9431 | |
69e94b7e | 9432 | /* Pipe WM_LINETIME - watermark line time */ |
086f8e84 VS |
9433 | #define _PIPE_WM_LINETIME_A 0x45270 |
9434 | #define _PIPE_WM_LINETIME_B 0x45274 | |
f0f59a00 | 9435 | #define PIPE_WM_LINETIME(pipe) _MMIO_PIPE(pipe, _PIPE_WM_LINETIME_A, _PIPE_WM_LINETIME_B) |
5e49cea6 PZ |
9436 | #define PIPE_WM_LINETIME_MASK (0x1ff) |
9437 | #define PIPE_WM_LINETIME_TIME(x) ((x)) | |
5ee8ee86 PZ |
9438 | #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff << 16) |
9439 | #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x) << 16) | |
96d6e350 ED |
9440 | |
9441 | /* SFUSE_STRAP */ | |
f0f59a00 | 9442 | #define SFUSE_STRAP _MMIO(0xc2014) |
5ee8ee86 PZ |
9443 | #define SFUSE_STRAP_FUSE_LOCK (1 << 13) |
9444 | #define SFUSE_STRAP_RAW_FREQUENCY (1 << 8) | |
9445 | #define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7) | |
9446 | #define SFUSE_STRAP_CRT_DISABLED (1 << 6) | |
9447 | #define SFUSE_STRAP_DDIF_DETECTED (1 << 3) | |
9448 | #define SFUSE_STRAP_DDIB_DETECTED (1 << 2) | |
9449 | #define SFUSE_STRAP_DDIC_DETECTED (1 << 1) | |
9450 | #define SFUSE_STRAP_DDID_DETECTED (1 << 0) | |
96d6e350 | 9451 | |
f0f59a00 | 9452 | #define WM_MISC _MMIO(0x45260) |
801bcfff PZ |
9453 | #define WM_MISC_DATA_PARTITION_5_6 (1 << 0) |
9454 | ||
f0f59a00 | 9455 | #define WM_DBG _MMIO(0x45280) |
5ee8ee86 PZ |
9456 | #define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0) |
9457 | #define WM_DBG_DISALLOW_MAXFIFO (1 << 1) | |
9458 | #define WM_DBG_DISALLOW_SPRITE (1 << 2) | |
1544d9d5 | 9459 | |
86d3efce VS |
9460 | /* pipe CSC */ |
9461 | #define _PIPE_A_CSC_COEFF_RY_GY 0x49010 | |
9462 | #define _PIPE_A_CSC_COEFF_BY 0x49014 | |
9463 | #define _PIPE_A_CSC_COEFF_RU_GU 0x49018 | |
9464 | #define _PIPE_A_CSC_COEFF_BU 0x4901c | |
9465 | #define _PIPE_A_CSC_COEFF_RV_GV 0x49020 | |
9466 | #define _PIPE_A_CSC_COEFF_BV 0x49024 | |
9467 | #define _PIPE_A_CSC_MODE 0x49028 | |
29a397ba VS |
9468 | #define CSC_BLACK_SCREEN_OFFSET (1 << 2) |
9469 | #define CSC_POSITION_BEFORE_GAMMA (1 << 1) | |
9470 | #define CSC_MODE_YUV_TO_RGB (1 << 0) | |
86d3efce VS |
9471 | #define _PIPE_A_CSC_PREOFF_HI 0x49030 |
9472 | #define _PIPE_A_CSC_PREOFF_ME 0x49034 | |
9473 | #define _PIPE_A_CSC_PREOFF_LO 0x49038 | |
9474 | #define _PIPE_A_CSC_POSTOFF_HI 0x49040 | |
9475 | #define _PIPE_A_CSC_POSTOFF_ME 0x49044 | |
9476 | #define _PIPE_A_CSC_POSTOFF_LO 0x49048 | |
9477 | ||
9478 | #define _PIPE_B_CSC_COEFF_RY_GY 0x49110 | |
9479 | #define _PIPE_B_CSC_COEFF_BY 0x49114 | |
9480 | #define _PIPE_B_CSC_COEFF_RU_GU 0x49118 | |
9481 | #define _PIPE_B_CSC_COEFF_BU 0x4911c | |
9482 | #define _PIPE_B_CSC_COEFF_RV_GV 0x49120 | |
9483 | #define _PIPE_B_CSC_COEFF_BV 0x49124 | |
9484 | #define _PIPE_B_CSC_MODE 0x49128 | |
9485 | #define _PIPE_B_CSC_PREOFF_HI 0x49130 | |
9486 | #define _PIPE_B_CSC_PREOFF_ME 0x49134 | |
9487 | #define _PIPE_B_CSC_PREOFF_LO 0x49138 | |
9488 | #define _PIPE_B_CSC_POSTOFF_HI 0x49140 | |
9489 | #define _PIPE_B_CSC_POSTOFF_ME 0x49144 | |
9490 | #define _PIPE_B_CSC_POSTOFF_LO 0x49148 | |
9491 | ||
f0f59a00 VS |
9492 | #define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY) |
9493 | #define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY) | |
9494 | #define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU) | |
9495 | #define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU) | |
9496 | #define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV) | |
9497 | #define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV) | |
9498 | #define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE) | |
9499 | #define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI) | |
9500 | #define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME) | |
9501 | #define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO) | |
9502 | #define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI) | |
9503 | #define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) | |
9504 | #define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) | |
86d3efce | 9505 | |
82cf435b LL |
9506 | /* pipe degamma/gamma LUTs on IVB+ */ |
9507 | #define _PAL_PREC_INDEX_A 0x4A400 | |
9508 | #define _PAL_PREC_INDEX_B 0x4AC00 | |
9509 | #define _PAL_PREC_INDEX_C 0x4B400 | |
9510 | #define PAL_PREC_10_12_BIT (0 << 31) | |
9511 | #define PAL_PREC_SPLIT_MODE (1 << 31) | |
9512 | #define PAL_PREC_AUTO_INCREMENT (1 << 15) | |
2fcb2066 | 9513 | #define PAL_PREC_INDEX_VALUE_MASK (0x3ff << 0) |
82cf435b LL |
9514 | #define _PAL_PREC_DATA_A 0x4A404 |
9515 | #define _PAL_PREC_DATA_B 0x4AC04 | |
9516 | #define _PAL_PREC_DATA_C 0x4B404 | |
9517 | #define _PAL_PREC_GC_MAX_A 0x4A410 | |
9518 | #define _PAL_PREC_GC_MAX_B 0x4AC10 | |
9519 | #define _PAL_PREC_GC_MAX_C 0x4B410 | |
9520 | #define _PAL_PREC_EXT_GC_MAX_A 0x4A420 | |
9521 | #define _PAL_PREC_EXT_GC_MAX_B 0x4AC20 | |
9522 | #define _PAL_PREC_EXT_GC_MAX_C 0x4B420 | |
9751bafc ACO |
9523 | #define _PAL_PREC_EXT2_GC_MAX_A 0x4A430 |
9524 | #define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30 | |
9525 | #define _PAL_PREC_EXT2_GC_MAX_C 0x4B430 | |
82cf435b LL |
9526 | |
9527 | #define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B) | |
9528 | #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B) | |
9529 | #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4) | |
9530 | #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4) | |
9531 | ||
9751bafc ACO |
9532 | #define _PRE_CSC_GAMC_INDEX_A 0x4A484 |
9533 | #define _PRE_CSC_GAMC_INDEX_B 0x4AC84 | |
9534 | #define _PRE_CSC_GAMC_INDEX_C 0x4B484 | |
9535 | #define PRE_CSC_GAMC_AUTO_INCREMENT (1 << 10) | |
9536 | #define _PRE_CSC_GAMC_DATA_A 0x4A488 | |
9537 | #define _PRE_CSC_GAMC_DATA_B 0x4AC88 | |
9538 | #define _PRE_CSC_GAMC_DATA_C 0x4B488 | |
9539 | ||
9540 | #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B) | |
9541 | #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B) | |
9542 | ||
29dc3739 LL |
9543 | /* pipe CSC & degamma/gamma LUTs on CHV */ |
9544 | #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) | |
9545 | #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904) | |
9546 | #define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908) | |
9547 | #define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C) | |
9548 | #define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910) | |
9549 | #define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000) | |
9550 | #define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000) | |
9551 | #define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00) | |
9552 | #define CGM_PIPE_MODE_GAMMA (1 << 2) | |
9553 | #define CGM_PIPE_MODE_CSC (1 << 1) | |
9554 | #define CGM_PIPE_MODE_DEGAMMA (1 << 0) | |
9555 | ||
9556 | #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900) | |
9557 | #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904) | |
9558 | #define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908) | |
9559 | #define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C) | |
9560 | #define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910) | |
9561 | #define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000) | |
9562 | #define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000) | |
9563 | #define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00) | |
9564 | ||
9565 | #define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01) | |
9566 | #define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23) | |
9567 | #define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45) | |
9568 | #define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67) | |
9569 | #define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8) | |
9570 | #define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4) | |
9571 | #define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4) | |
9572 | #define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE) | |
9573 | ||
e7d7cad0 JN |
9574 | /* MIPI DSI registers */ |
9575 | ||
0ad4dc88 | 9576 | #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */ |
f0f59a00 | 9577 | #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c)) |
3230bf14 | 9578 | |
bcc65700 D |
9579 | #define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004) |
9580 | #define GLK_TX_ESC_CLK_DIV1_MASK 0x3FF | |
9581 | #define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008) | |
9582 | #define GLK_TX_ESC_CLK_DIV2_MASK 0x3FF | |
9583 | ||
27efd256 MC |
9584 | #define _ICL_DSI_ESC_CLK_DIV0 0x6b090 |
9585 | #define _ICL_DSI_ESC_CLK_DIV1 0x6b890 | |
9586 | #define ICL_DSI_ESC_CLK_DIV(port) _MMIO_PORT((port), \ | |
9587 | _ICL_DSI_ESC_CLK_DIV0, \ | |
9588 | _ICL_DSI_ESC_CLK_DIV1) | |
9589 | #define _ICL_DPHY_ESC_CLK_DIV0 0x162190 | |
9590 | #define _ICL_DPHY_ESC_CLK_DIV1 0x6C190 | |
9591 | #define ICL_DPHY_ESC_CLK_DIV(port) _MMIO_PORT((port), \ | |
9592 | _ICL_DPHY_ESC_CLK_DIV0, \ | |
9593 | _ICL_DPHY_ESC_CLK_DIV1) | |
9594 | #define ICL_BYTE_CLK_PER_ESC_CLK_MASK (0x1f << 16) | |
9595 | #define ICL_BYTE_CLK_PER_ESC_CLK_SHIFT 16 | |
9596 | #define ICL_ESC_CLK_DIV_MASK 0x1ff | |
9597 | #define ICL_ESC_CLK_DIV_SHIFT 0 | |
fcfe0bdc | 9598 | #define DSI_MAX_ESC_CLK 20000 /* in KHz */ |
27efd256 | 9599 | |
aec0246f US |
9600 | /* Gen4+ Timestamp and Pipe Frame time stamp registers */ |
9601 | #define GEN4_TIMESTAMP _MMIO(0x2358) | |
9602 | #define ILK_TIMESTAMP_HI _MMIO(0x70070) | |
9603 | #define IVB_TIMESTAMP_CTR _MMIO(0x44070) | |
9604 | ||
dab91783 LL |
9605 | #define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074) |
9606 | #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0 | |
9607 | #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff | |
9608 | #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12 | |
9609 | #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12) | |
9610 | ||
aec0246f US |
9611 | #define _PIPE_FRMTMSTMP_A 0x70048 |
9612 | #define PIPE_FRMTMSTMP(pipe) \ | |
9613 | _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A) | |
9614 | ||
11b8e4f5 SS |
9615 | /* BXT MIPI clock controls */ |
9616 | #define BXT_MAX_VAR_OUTPUT_KHZ 39500 | |
9617 | ||
f0f59a00 | 9618 | #define BXT_MIPI_CLOCK_CTL _MMIO(0x46090) |
11b8e4f5 SS |
9619 | #define BXT_MIPI1_DIV_SHIFT 26 |
9620 | #define BXT_MIPI2_DIV_SHIFT 10 | |
9621 | #define BXT_MIPI_DIV_SHIFT(port) \ | |
9622 | _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \ | |
9623 | BXT_MIPI2_DIV_SHIFT) | |
782d25ca | 9624 | |
11b8e4f5 | 9625 | /* TX control divider to select actual TX clock output from (8x/var) */ |
782d25ca D |
9626 | #define BXT_MIPI1_TX_ESCLK_SHIFT 26 |
9627 | #define BXT_MIPI2_TX_ESCLK_SHIFT 10 | |
11b8e4f5 SS |
9628 | #define BXT_MIPI_TX_ESCLK_SHIFT(port) \ |
9629 | _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \ | |
9630 | BXT_MIPI2_TX_ESCLK_SHIFT) | |
782d25ca D |
9631 | #define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (0x3F << 26) |
9632 | #define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (0x3F << 10) | |
11b8e4f5 SS |
9633 | #define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \ |
9634 | _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \ | |
782d25ca D |
9635 | BXT_MIPI2_TX_ESCLK_FIXDIV_MASK) |
9636 | #define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \ | |
9e8789ec | 9637 | (((val) & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port)) |
782d25ca D |
9638 | /* RX upper control divider to select actual RX clock output from 8x */ |
9639 | #define BXT_MIPI1_RX_ESCLK_UPPER_SHIFT 21 | |
9640 | #define BXT_MIPI2_RX_ESCLK_UPPER_SHIFT 5 | |
9641 | #define BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port) \ | |
9642 | _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \ | |
9643 | BXT_MIPI2_RX_ESCLK_UPPER_SHIFT) | |
9644 | #define BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 21) | |
9645 | #define BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 5) | |
9646 | #define BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port) \ | |
9647 | _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \ | |
9648 | BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK) | |
9649 | #define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \ | |
9e8789ec | 9650 | (((val) & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port)) |
782d25ca D |
9651 | /* 8/3X divider to select the actual 8/3X clock output from 8x */ |
9652 | #define BXT_MIPI1_8X_BY3_SHIFT 19 | |
9653 | #define BXT_MIPI2_8X_BY3_SHIFT 3 | |
9654 | #define BXT_MIPI_8X_BY3_SHIFT(port) \ | |
9655 | _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \ | |
9656 | BXT_MIPI2_8X_BY3_SHIFT) | |
9657 | #define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19) | |
9658 | #define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3) | |
9659 | #define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \ | |
9660 | _MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \ | |
9661 | BXT_MIPI2_8X_BY3_DIVIDER_MASK) | |
9662 | #define BXT_MIPI_8X_BY3_DIVIDER(port, val) \ | |
9e8789ec | 9663 | (((val) & 3) << BXT_MIPI_8X_BY3_SHIFT(port)) |
782d25ca D |
9664 | /* RX lower control divider to select actual RX clock output from 8x */ |
9665 | #define BXT_MIPI1_RX_ESCLK_LOWER_SHIFT 16 | |
9666 | #define BXT_MIPI2_RX_ESCLK_LOWER_SHIFT 0 | |
9667 | #define BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port) \ | |
9668 | _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \ | |
9669 | BXT_MIPI2_RX_ESCLK_LOWER_SHIFT) | |
9670 | #define BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 16) | |
9671 | #define BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 0) | |
9672 | #define BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port) \ | |
9673 | _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \ | |
9674 | BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK) | |
9675 | #define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \ | |
9e8789ec | 9676 | (((val) & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port)) |
782d25ca D |
9677 | |
9678 | #define RX_DIVIDER_BIT_1_2 0x3 | |
9679 | #define RX_DIVIDER_BIT_3_4 0xC | |
11b8e4f5 | 9680 | |
d2e08c0f SS |
9681 | /* BXT MIPI mode configure */ |
9682 | #define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8 | |
9683 | #define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8 | |
f0f59a00 | 9684 | #define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \ |
d2e08c0f SS |
9685 | _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE) |
9686 | ||
9687 | #define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC | |
9688 | #define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC | |
f0f59a00 | 9689 | #define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \ |
d2e08c0f SS |
9690 | _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE) |
9691 | ||
9692 | #define _BXT_MIPIA_TRANS_VTOTAL 0x6B100 | |
9693 | #define _BXT_MIPIC_TRANS_VTOTAL 0x6B900 | |
f0f59a00 | 9694 | #define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \ |
d2e08c0f SS |
9695 | _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL) |
9696 | ||
f0f59a00 | 9697 | #define BXT_DSI_PLL_CTL _MMIO(0x161000) |
cfe01a5e SS |
9698 | #define BXT_DSI_PLL_PVD_RATIO_SHIFT 16 |
9699 | #define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT) | |
9700 | #define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT) | |
f340c2ff | 9701 | #define BXT_DSIC_16X_BY1 (0 << 10) |
cfe01a5e SS |
9702 | #define BXT_DSIC_16X_BY2 (1 << 10) |
9703 | #define BXT_DSIC_16X_BY3 (2 << 10) | |
9704 | #define BXT_DSIC_16X_BY4 (3 << 10) | |
db18b6a6 | 9705 | #define BXT_DSIC_16X_MASK (3 << 10) |
f340c2ff | 9706 | #define BXT_DSIA_16X_BY1 (0 << 8) |
cfe01a5e SS |
9707 | #define BXT_DSIA_16X_BY2 (1 << 8) |
9708 | #define BXT_DSIA_16X_BY3 (2 << 8) | |
9709 | #define BXT_DSIA_16X_BY4 (3 << 8) | |
db18b6a6 | 9710 | #define BXT_DSIA_16X_MASK (3 << 8) |
cfe01a5e SS |
9711 | #define BXT_DSI_FREQ_SEL_SHIFT 8 |
9712 | #define BXT_DSI_FREQ_SEL_MASK (0xF << BXT_DSI_FREQ_SEL_SHIFT) | |
9713 | ||
9714 | #define BXT_DSI_PLL_RATIO_MAX 0x7D | |
9715 | #define BXT_DSI_PLL_RATIO_MIN 0x22 | |
f340c2ff D |
9716 | #define GLK_DSI_PLL_RATIO_MAX 0x6F |
9717 | #define GLK_DSI_PLL_RATIO_MIN 0x22 | |
cfe01a5e | 9718 | #define BXT_DSI_PLL_RATIO_MASK 0xFF |
61ad9928 | 9719 | #define BXT_REF_CLOCK_KHZ 19200 |
cfe01a5e | 9720 | |
f0f59a00 | 9721 | #define BXT_DSI_PLL_ENABLE _MMIO(0x46080) |
cfe01a5e SS |
9722 | #define BXT_DSI_PLL_DO_ENABLE (1 << 31) |
9723 | #define BXT_DSI_PLL_LOCKED (1 << 30) | |
9724 | ||
3230bf14 | 9725 | #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) |
e7d7cad0 | 9726 | #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) |
f0f59a00 | 9727 | #define MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) |
37ab0810 SS |
9728 | |
9729 | /* BXT port control */ | |
9730 | #define _BXT_MIPIA_PORT_CTRL 0x6B0C0 | |
9731 | #define _BXT_MIPIC_PORT_CTRL 0x6B8C0 | |
f0f59a00 | 9732 | #define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL) |
37ab0810 | 9733 | |
21652f3b MC |
9734 | /* ICL DSI MODE control */ |
9735 | #define _ICL_DSI_IO_MODECTL_0 0x6B094 | |
9736 | #define _ICL_DSI_IO_MODECTL_1 0x6B894 | |
9737 | #define ICL_DSI_IO_MODECTL(port) _MMIO_PORT(port, \ | |
9738 | _ICL_DSI_IO_MODECTL_0, \ | |
9739 | _ICL_DSI_IO_MODECTL_1) | |
9740 | #define COMBO_PHY_MODE_DSI (1 << 0) | |
9741 | ||
1881a423 US |
9742 | #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020) |
9743 | #define STAP_SELECT (1 << 0) | |
9744 | ||
9745 | #define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054) | |
9746 | #define HS_IO_CTRL_SELECT (1 << 0) | |
9747 | ||
e7d7cad0 | 9748 | #define DPI_ENABLE (1 << 31) /* A + C */ |
3230bf14 JN |
9749 | #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 |
9750 | #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27) | |
369602d3 | 9751 | #define DUAL_LINK_MODE_SHIFT 26 |
3230bf14 JN |
9752 | #define DUAL_LINK_MODE_MASK (1 << 26) |
9753 | #define DUAL_LINK_MODE_FRONT_BACK (0 << 26) | |
9754 | #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26) | |
e7d7cad0 | 9755 | #define DITHERING_ENABLE (1 << 25) /* A + C */ |
3230bf14 JN |
9756 | #define FLOPPED_HSTX (1 << 23) |
9757 | #define DE_INVERT (1 << 19) /* XXX */ | |
9758 | #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18 | |
9759 | #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18) | |
9760 | #define AFE_LATCHOUT (1 << 17) | |
9761 | #define LP_OUTPUT_HOLD (1 << 16) | |
e7d7cad0 JN |
9762 | #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15 |
9763 | #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15) | |
9764 | #define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11 | |
9765 | #define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11) | |
3230bf14 JN |
9766 | #define CSB_SHIFT 9 |
9767 | #define CSB_MASK (3 << 9) | |
9768 | #define CSB_20MHZ (0 << 9) | |
9769 | #define CSB_10MHZ (1 << 9) | |
9770 | #define CSB_40MHZ (2 << 9) | |
9771 | #define BANDGAP_MASK (1 << 8) | |
9772 | #define BANDGAP_PNW_CIRCUIT (0 << 8) | |
9773 | #define BANDGAP_LNC_CIRCUIT (1 << 8) | |
e7d7cad0 JN |
9774 | #define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5 |
9775 | #define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5) | |
9776 | #define TEARING_EFFECT_DELAY (1 << 4) /* A + C */ | |
9777 | #define TEARING_EFFECT_SHIFT 2 /* A + C */ | |
3230bf14 JN |
9778 | #define TEARING_EFFECT_MASK (3 << 2) |
9779 | #define TEARING_EFFECT_OFF (0 << 2) | |
9780 | #define TEARING_EFFECT_DSI (1 << 2) | |
9781 | #define TEARING_EFFECT_GPIO (2 << 2) | |
9782 | #define LANE_CONFIGURATION_SHIFT 0 | |
9783 | #define LANE_CONFIGURATION_MASK (3 << 0) | |
9784 | #define LANE_CONFIGURATION_4LANE (0 << 0) | |
9785 | #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0) | |
9786 | #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0) | |
9787 | ||
9788 | #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) | |
e7d7cad0 | 9789 | #define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) |
f0f59a00 | 9790 | #define MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) |
3230bf14 JN |
9791 | #define TEARING_EFFECT_DELAY_SHIFT 0 |
9792 | #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) | |
9793 | ||
9794 | /* XXX: all bits reserved */ | |
4ad83e94 | 9795 | #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0) |
3230bf14 JN |
9796 | |
9797 | /* MIPI DSI Controller and D-PHY registers */ | |
9798 | ||
4ad83e94 | 9799 | #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000) |
e7d7cad0 | 9800 | #define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800) |
f0f59a00 | 9801 | #define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY) |
3230bf14 JN |
9802 | #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ |
9803 | #define ULPS_STATE_MASK (3 << 1) | |
9804 | #define ULPS_STATE_ENTER (2 << 1) | |
9805 | #define ULPS_STATE_EXIT (1 << 1) | |
9806 | #define ULPS_STATE_NORMAL_OPERATION (0 << 1) | |
9807 | #define DEVICE_READY (1 << 0) | |
9808 | ||
4ad83e94 | 9809 | #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004) |
e7d7cad0 | 9810 | #define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804) |
f0f59a00 | 9811 | #define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT) |
4ad83e94 | 9812 | #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008) |
e7d7cad0 | 9813 | #define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808) |
f0f59a00 | 9814 | #define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN) |
3230bf14 JN |
9815 | #define TEARING_EFFECT (1 << 31) |
9816 | #define SPL_PKT_SENT_INTERRUPT (1 << 30) | |
9817 | #define GEN_READ_DATA_AVAIL (1 << 29) | |
9818 | #define LP_GENERIC_WR_FIFO_FULL (1 << 28) | |
9819 | #define HS_GENERIC_WR_FIFO_FULL (1 << 27) | |
9820 | #define RX_PROT_VIOLATION (1 << 26) | |
9821 | #define RX_INVALID_TX_LENGTH (1 << 25) | |
9822 | #define ACK_WITH_NO_ERROR (1 << 24) | |
9823 | #define TURN_AROUND_ACK_TIMEOUT (1 << 23) | |
9824 | #define LP_RX_TIMEOUT (1 << 22) | |
9825 | #define HS_TX_TIMEOUT (1 << 21) | |
9826 | #define DPI_FIFO_UNDERRUN (1 << 20) | |
9827 | #define LOW_CONTENTION (1 << 19) | |
9828 | #define HIGH_CONTENTION (1 << 18) | |
9829 | #define TXDSI_VC_ID_INVALID (1 << 17) | |
9830 | #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16) | |
9831 | #define TXCHECKSUM_ERROR (1 << 15) | |
9832 | #define TXECC_MULTIBIT_ERROR (1 << 14) | |
9833 | #define TXECC_SINGLE_BIT_ERROR (1 << 13) | |
9834 | #define TXFALSE_CONTROL_ERROR (1 << 12) | |
9835 | #define RXDSI_VC_ID_INVALID (1 << 11) | |
9836 | #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10) | |
9837 | #define RXCHECKSUM_ERROR (1 << 9) | |
9838 | #define RXECC_MULTIBIT_ERROR (1 << 8) | |
9839 | #define RXECC_SINGLE_BIT_ERROR (1 << 7) | |
9840 | #define RXFALSE_CONTROL_ERROR (1 << 6) | |
9841 | #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5) | |
9842 | #define RX_LP_TX_SYNC_ERROR (1 << 4) | |
9843 | #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3) | |
9844 | #define RXEOT_SYNC_ERROR (1 << 2) | |
9845 | #define RXSOT_SYNC_ERROR (1 << 1) | |
9846 | #define RXSOT_ERROR (1 << 0) | |
9847 | ||
4ad83e94 | 9848 | #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c) |
e7d7cad0 | 9849 | #define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c) |
f0f59a00 | 9850 | #define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG) |
3230bf14 JN |
9851 | #define CMD_MODE_DATA_WIDTH_MASK (7 << 13) |
9852 | #define CMD_MODE_NOT_SUPPORTED (0 << 13) | |
9853 | #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) | |
9854 | #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13) | |
9855 | #define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13) | |
9856 | #define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13) | |
9857 | #define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13) | |
9858 | #define VID_MODE_FORMAT_MASK (0xf << 7) | |
9859 | #define VID_MODE_NOT_SUPPORTED (0 << 7) | |
9860 | #define VID_MODE_FORMAT_RGB565 (1 << 7) | |
42c151e6 JN |
9861 | #define VID_MODE_FORMAT_RGB666_PACKED (2 << 7) |
9862 | #define VID_MODE_FORMAT_RGB666 (3 << 7) | |
3230bf14 JN |
9863 | #define VID_MODE_FORMAT_RGB888 (4 << 7) |
9864 | #define CMD_MODE_CHANNEL_NUMBER_SHIFT 5 | |
9865 | #define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5) | |
9866 | #define VID_MODE_CHANNEL_NUMBER_SHIFT 3 | |
9867 | #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3) | |
9868 | #define DATA_LANES_PRG_REG_SHIFT 0 | |
9869 | #define DATA_LANES_PRG_REG_MASK (7 << 0) | |
9870 | ||
4ad83e94 | 9871 | #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010) |
e7d7cad0 | 9872 | #define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810) |
f0f59a00 | 9873 | #define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT) |
3230bf14 JN |
9874 | #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff |
9875 | ||
4ad83e94 | 9876 | #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014) |
e7d7cad0 | 9877 | #define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814) |
f0f59a00 | 9878 | #define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT) |
3230bf14 JN |
9879 | #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff |
9880 | ||
4ad83e94 | 9881 | #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018) |
e7d7cad0 | 9882 | #define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818) |
f0f59a00 | 9883 | #define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT) |
3230bf14 JN |
9884 | #define TURN_AROUND_TIMEOUT_MASK 0x3f |
9885 | ||
4ad83e94 | 9886 | #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c) |
e7d7cad0 | 9887 | #define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c) |
f0f59a00 | 9888 | #define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER) |
3230bf14 JN |
9889 | #define DEVICE_RESET_TIMER_MASK 0xffff |
9890 | ||
4ad83e94 | 9891 | #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020) |
e7d7cad0 | 9892 | #define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820) |
f0f59a00 | 9893 | #define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION) |
3230bf14 JN |
9894 | #define VERTICAL_ADDRESS_SHIFT 16 |
9895 | #define VERTICAL_ADDRESS_MASK (0xffff << 16) | |
9896 | #define HORIZONTAL_ADDRESS_SHIFT 0 | |
9897 | #define HORIZONTAL_ADDRESS_MASK 0xffff | |
9898 | ||
4ad83e94 | 9899 | #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024) |
e7d7cad0 | 9900 | #define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824) |
f0f59a00 | 9901 | #define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE) |
3230bf14 JN |
9902 | #define DBI_FIFO_EMPTY_HALF (0 << 0) |
9903 | #define DBI_FIFO_EMPTY_QUARTER (1 << 0) | |
9904 | #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) | |
9905 | ||
9906 | /* regs below are bits 15:0 */ | |
4ad83e94 | 9907 | #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028) |
e7d7cad0 | 9908 | #define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828) |
f0f59a00 | 9909 | #define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT) |
3230bf14 | 9910 | |
4ad83e94 | 9911 | #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c) |
e7d7cad0 | 9912 | #define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c) |
f0f59a00 | 9913 | #define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT) |
3230bf14 | 9914 | |
4ad83e94 | 9915 | #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030) |
e7d7cad0 | 9916 | #define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830) |
f0f59a00 | 9917 | #define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT) |
3230bf14 | 9918 | |
4ad83e94 | 9919 | #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034) |
e7d7cad0 | 9920 | #define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834) |
f0f59a00 | 9921 | #define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT) |
3230bf14 | 9922 | |
4ad83e94 | 9923 | #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038) |
e7d7cad0 | 9924 | #define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838) |
f0f59a00 | 9925 | #define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT) |
3230bf14 | 9926 | |
4ad83e94 | 9927 | #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c) |
e7d7cad0 | 9928 | #define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c) |
f0f59a00 | 9929 | #define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT) |
3230bf14 | 9930 | |
4ad83e94 | 9931 | #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040) |
e7d7cad0 | 9932 | #define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840) |
f0f59a00 | 9933 | #define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT) |
3230bf14 | 9934 | |
4ad83e94 | 9935 | #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044) |
e7d7cad0 | 9936 | #define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844) |
f0f59a00 | 9937 | #define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT) |
4ad83e94 | 9938 | |
3230bf14 JN |
9939 | /* regs above are bits 15:0 */ |
9940 | ||
4ad83e94 | 9941 | #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048) |
e7d7cad0 | 9942 | #define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848) |
f0f59a00 | 9943 | #define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL) |
3230bf14 JN |
9944 | #define DPI_LP_MODE (1 << 6) |
9945 | #define BACKLIGHT_OFF (1 << 5) | |
9946 | #define BACKLIGHT_ON (1 << 4) | |
9947 | #define COLOR_MODE_OFF (1 << 3) | |
9948 | #define COLOR_MODE_ON (1 << 2) | |
9949 | #define TURN_ON (1 << 1) | |
9950 | #define SHUTDOWN (1 << 0) | |
9951 | ||
4ad83e94 | 9952 | #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c) |
e7d7cad0 | 9953 | #define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c) |
f0f59a00 | 9954 | #define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA) |
3230bf14 JN |
9955 | #define COMMAND_BYTE_SHIFT 0 |
9956 | #define COMMAND_BYTE_MASK (0x3f << 0) | |
9957 | ||
4ad83e94 | 9958 | #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050) |
e7d7cad0 | 9959 | #define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850) |
f0f59a00 | 9960 | #define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT) |
3230bf14 JN |
9961 | #define MASTER_INIT_TIMER_SHIFT 0 |
9962 | #define MASTER_INIT_TIMER_MASK (0xffff << 0) | |
9963 | ||
4ad83e94 | 9964 | #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054) |
e7d7cad0 | 9965 | #define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854) |
f0f59a00 | 9966 | #define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \ |
e7d7cad0 | 9967 | _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE) |
3230bf14 JN |
9968 | #define MAX_RETURN_PKT_SIZE_SHIFT 0 |
9969 | #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) | |
9970 | ||
4ad83e94 | 9971 | #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058) |
e7d7cad0 | 9972 | #define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858) |
f0f59a00 | 9973 | #define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT) |
3230bf14 JN |
9974 | #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) |
9975 | #define DISABLE_VIDEO_BTA (1 << 3) | |
9976 | #define IP_TG_CONFIG (1 << 2) | |
9977 | #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0) | |
9978 | #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0) | |
9979 | #define VIDEO_MODE_BURST (3 << 0) | |
9980 | ||
4ad83e94 | 9981 | #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c) |
e7d7cad0 | 9982 | #define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c) |
f0f59a00 | 9983 | #define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE) |
f90e8c36 JN |
9984 | #define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9) |
9985 | #define BXT_DPHY_DEFEATURE_EN (1 << 8) | |
3230bf14 JN |
9986 | #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) |
9987 | #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6) | |
9988 | #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5) | |
9989 | #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4) | |
9990 | #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3) | |
9991 | #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2) | |
9992 | #define CLOCKSTOP (1 << 1) | |
9993 | #define EOT_DISABLE (1 << 0) | |
9994 | ||
4ad83e94 | 9995 | #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060) |
e7d7cad0 | 9996 | #define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860) |
f0f59a00 | 9997 | #define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK) |
3230bf14 JN |
9998 | #define LP_BYTECLK_SHIFT 0 |
9999 | #define LP_BYTECLK_MASK (0xffff << 0) | |
10000 | ||
b426f985 D |
10001 | #define _MIPIA_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb0a4) |
10002 | #define _MIPIC_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb8a4) | |
10003 | #define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT) | |
10004 | ||
10005 | #define _MIPIA_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb098) | |
10006 | #define _MIPIC_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb898) | |
10007 | #define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING) | |
10008 | ||
3230bf14 | 10009 | /* bits 31:0 */ |
4ad83e94 | 10010 | #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064) |
e7d7cad0 | 10011 | #define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864) |
f0f59a00 | 10012 | #define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA) |
3230bf14 JN |
10013 | |
10014 | /* bits 31:0 */ | |
4ad83e94 | 10015 | #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068) |
e7d7cad0 | 10016 | #define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868) |
f0f59a00 | 10017 | #define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA) |
3230bf14 | 10018 | |
4ad83e94 | 10019 | #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c) |
e7d7cad0 | 10020 | #define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c) |
f0f59a00 | 10021 | #define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL) |
4ad83e94 | 10022 | #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070) |
e7d7cad0 | 10023 | #define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870) |
f0f59a00 | 10024 | #define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL) |
3230bf14 JN |
10025 | #define LONG_PACKET_WORD_COUNT_SHIFT 8 |
10026 | #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) | |
10027 | #define SHORT_PACKET_PARAM_SHIFT 8 | |
10028 | #define SHORT_PACKET_PARAM_MASK (0xffff << 8) | |
10029 | #define VIRTUAL_CHANNEL_SHIFT 6 | |
10030 | #define VIRTUAL_CHANNEL_MASK (3 << 6) | |
10031 | #define DATA_TYPE_SHIFT 0 | |
395b2913 | 10032 | #define DATA_TYPE_MASK (0x3f << 0) |
3230bf14 JN |
10033 | /* data type values, see include/video/mipi_display.h */ |
10034 | ||
4ad83e94 | 10035 | #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074) |
e7d7cad0 | 10036 | #define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874) |
f0f59a00 | 10037 | #define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT) |
3230bf14 JN |
10038 | #define DPI_FIFO_EMPTY (1 << 28) |
10039 | #define DBI_FIFO_EMPTY (1 << 27) | |
10040 | #define LP_CTRL_FIFO_EMPTY (1 << 26) | |
10041 | #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25) | |
10042 | #define LP_CTRL_FIFO_FULL (1 << 24) | |
10043 | #define HS_CTRL_FIFO_EMPTY (1 << 18) | |
10044 | #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17) | |
10045 | #define HS_CTRL_FIFO_FULL (1 << 16) | |
10046 | #define LP_DATA_FIFO_EMPTY (1 << 10) | |
10047 | #define LP_DATA_FIFO_HALF_EMPTY (1 << 9) | |
10048 | #define LP_DATA_FIFO_FULL (1 << 8) | |
10049 | #define HS_DATA_FIFO_EMPTY (1 << 2) | |
10050 | #define HS_DATA_FIFO_HALF_EMPTY (1 << 1) | |
10051 | #define HS_DATA_FIFO_FULL (1 << 0) | |
10052 | ||
4ad83e94 | 10053 | #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078) |
e7d7cad0 | 10054 | #define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878) |
f0f59a00 | 10055 | #define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE) |
3230bf14 JN |
10056 | #define DBI_HS_LP_MODE_MASK (1 << 0) |
10057 | #define DBI_LP_MODE (1 << 0) | |
10058 | #define DBI_HS_MODE (0 << 0) | |
10059 | ||
4ad83e94 | 10060 | #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080) |
e7d7cad0 | 10061 | #define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880) |
f0f59a00 | 10062 | #define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM) |
3230bf14 JN |
10063 | #define EXIT_ZERO_COUNT_SHIFT 24 |
10064 | #define EXIT_ZERO_COUNT_MASK (0x3f << 24) | |
10065 | #define TRAIL_COUNT_SHIFT 16 | |
10066 | #define TRAIL_COUNT_MASK (0x1f << 16) | |
10067 | #define CLK_ZERO_COUNT_SHIFT 8 | |
10068 | #define CLK_ZERO_COUNT_MASK (0xff << 8) | |
10069 | #define PREPARE_COUNT_SHIFT 0 | |
10070 | #define PREPARE_COUNT_MASK (0x3f << 0) | |
10071 | ||
10072 | /* bits 31:0 */ | |
4ad83e94 | 10073 | #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084) |
e7d7cad0 | 10074 | #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884) |
f0f59a00 VS |
10075 | #define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL) |
10076 | ||
10077 | #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb088) | |
10078 | #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb888) | |
10079 | #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT) | |
3230bf14 JN |
10080 | #define LP_HS_SSW_CNT_SHIFT 16 |
10081 | #define LP_HS_SSW_CNT_MASK (0xffff << 16) | |
10082 | #define HS_LP_PWR_SW_CNT_SHIFT 0 | |
10083 | #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) | |
10084 | ||
4ad83e94 | 10085 | #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c) |
e7d7cad0 | 10086 | #define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c) |
f0f59a00 | 10087 | #define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL) |
3230bf14 JN |
10088 | #define STOP_STATE_STALL_COUNTER_SHIFT 0 |
10089 | #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) | |
10090 | ||
4ad83e94 | 10091 | #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090) |
e7d7cad0 | 10092 | #define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890) |
f0f59a00 | 10093 | #define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1) |
4ad83e94 | 10094 | #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094) |
e7d7cad0 | 10095 | #define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894) |
f0f59a00 | 10096 | #define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1) |
3230bf14 JN |
10097 | #define RX_CONTENTION_DETECTED (1 << 0) |
10098 | ||
10099 | /* XXX: only pipe A ?!? */ | |
4ad83e94 | 10100 | #define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100) |
3230bf14 JN |
10101 | #define DBI_TYPEC_ENABLE (1 << 31) |
10102 | #define DBI_TYPEC_WIP (1 << 30) | |
10103 | #define DBI_TYPEC_OPTION_SHIFT 28 | |
10104 | #define DBI_TYPEC_OPTION_MASK (3 << 28) | |
10105 | #define DBI_TYPEC_FREQ_SHIFT 24 | |
10106 | #define DBI_TYPEC_FREQ_MASK (0xf << 24) | |
10107 | #define DBI_TYPEC_OVERRIDE (1 << 8) | |
10108 | #define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0 | |
10109 | #define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0) | |
10110 | ||
10111 | ||
10112 | /* MIPI adapter registers */ | |
10113 | ||
4ad83e94 | 10114 | #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104) |
e7d7cad0 | 10115 | #define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904) |
f0f59a00 | 10116 | #define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL) |
3230bf14 JN |
10117 | #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ |
10118 | #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) | |
10119 | #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5) | |
10120 | #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5) | |
10121 | #define ESCAPE_CLOCK_DIVIDER_4 (2 << 5) | |
10122 | #define READ_REQUEST_PRIORITY_SHIFT 3 | |
10123 | #define READ_REQUEST_PRIORITY_MASK (3 << 3) | |
10124 | #define READ_REQUEST_PRIORITY_LOW (0 << 3) | |
10125 | #define READ_REQUEST_PRIORITY_HIGH (3 << 3) | |
10126 | #define RGB_FLIP_TO_BGR (1 << 2) | |
10127 | ||
6b93e9c8 | 10128 | #define BXT_PIPE_SELECT_SHIFT 7 |
d2e08c0f | 10129 | #define BXT_PIPE_SELECT_MASK (7 << 7) |
56c48978 | 10130 | #define BXT_PIPE_SELECT(pipe) ((pipe) << 7) |
093d680a D |
10131 | #define GLK_PHY_STATUS_PORT_READY (1 << 31) /* RO */ |
10132 | #define GLK_ULPS_NOT_ACTIVE (1 << 30) /* RO */ | |
10133 | #define GLK_MIPIIO_RESET_RELEASED (1 << 28) | |
10134 | #define GLK_CLOCK_LANE_STOP_STATE (1 << 27) /* RO */ | |
10135 | #define GLK_DATA_LANE_STOP_STATE (1 << 26) /* RO */ | |
10136 | #define GLK_LP_WAKE (1 << 22) | |
10137 | #define GLK_LP11_LOW_PWR_MODE (1 << 21) | |
10138 | #define GLK_LP00_LOW_PWR_MODE (1 << 20) | |
10139 | #define GLK_FIREWALL_ENABLE (1 << 16) | |
10140 | #define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10) | |
10141 | #define BXT_PIXEL_OVERLAP_CNT_SHIFT 10 | |
10142 | #define BXT_DSC_ENABLE (1 << 3) | |
10143 | #define BXT_RGB_FLIP (1 << 2) | |
10144 | #define GLK_MIPIIO_PORT_POWERED (1 << 1) /* RO */ | |
10145 | #define GLK_MIPIIO_ENABLE (1 << 0) | |
d2e08c0f | 10146 | |
4ad83e94 | 10147 | #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108) |
e7d7cad0 | 10148 | #define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908) |
f0f59a00 | 10149 | #define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS) |
3230bf14 JN |
10150 | #define DATA_MEM_ADDRESS_SHIFT 5 |
10151 | #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) | |
10152 | #define DATA_VALID (1 << 0) | |
10153 | ||
4ad83e94 | 10154 | #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c) |
e7d7cad0 | 10155 | #define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c) |
f0f59a00 | 10156 | #define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH) |
3230bf14 JN |
10157 | #define DATA_LENGTH_SHIFT 0 |
10158 | #define DATA_LENGTH_MASK (0xfffff << 0) | |
10159 | ||
4ad83e94 | 10160 | #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110) |
e7d7cad0 | 10161 | #define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910) |
f0f59a00 | 10162 | #define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS) |
3230bf14 JN |
10163 | #define COMMAND_MEM_ADDRESS_SHIFT 5 |
10164 | #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) | |
10165 | #define AUTO_PWG_ENABLE (1 << 2) | |
10166 | #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1) | |
10167 | #define COMMAND_VALID (1 << 0) | |
10168 | ||
4ad83e94 | 10169 | #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114) |
e7d7cad0 | 10170 | #define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914) |
f0f59a00 | 10171 | #define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH) |
3230bf14 JN |
10172 | #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ |
10173 | #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) | |
10174 | ||
4ad83e94 | 10175 | #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118) |
e7d7cad0 | 10176 | #define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918) |
f0f59a00 | 10177 | #define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */ |
3230bf14 | 10178 | |
4ad83e94 | 10179 | #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138) |
e7d7cad0 | 10180 | #define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938) |
f0f59a00 | 10181 | #define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID) |
3230bf14 JN |
10182 | #define READ_DATA_VALID(n) (1 << (n)) |
10183 | ||
a57c774a | 10184 | /* For UMS only (deprecated): */ |
5c969aa7 DL |
10185 | #define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000) |
10186 | #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800) | |
a57c774a | 10187 | |
3bbaba0c | 10188 | /* MOCS (Memory Object Control State) registers */ |
f0f59a00 | 10189 | #define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */ |
3bbaba0c | 10190 | |
f0f59a00 VS |
10191 | #define GEN9_GFX_MOCS(i) _MMIO(0xc800 + (i) * 4) /* Graphics MOCS registers */ |
10192 | #define GEN9_MFX0_MOCS(i) _MMIO(0xc900 + (i) * 4) /* Media 0 MOCS registers */ | |
10193 | #define GEN9_MFX1_MOCS(i) _MMIO(0xca00 + (i) * 4) /* Media 1 MOCS registers */ | |
10194 | #define GEN9_VEBOX_MOCS(i) _MMIO(0xcb00 + (i) * 4) /* Video MOCS registers */ | |
10195 | #define GEN9_BLT_MOCS(i) _MMIO(0xcc00 + (i) * 4) /* Blitter MOCS registers */ | |
74ba22ea TL |
10196 | /* Media decoder 2 MOCS registers */ |
10197 | #define GEN11_MFX2_MOCS(i) _MMIO(0x10000 + (i) * 4) | |
3bbaba0c | 10198 | |
73f4e8a3 OM |
10199 | #define GEN10_SCRATCH_LNCF2 _MMIO(0xb0a0) |
10200 | #define PMFLUSHDONE_LNICRSDROP (1 << 20) | |
10201 | #define PMFLUSH_GAPL3UNBLOCK (1 << 21) | |
10202 | #define PMFLUSHDONE_LNEBLK (1 << 22) | |
10203 | ||
d5165ebd TG |
10204 | /* gamt regs */ |
10205 | #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4) | |
10206 | #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */ | |
10207 | #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for LRA1/2 */ | |
10208 | #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /* " " */ | |
10209 | #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /* " " */ | |
10210 | ||
93564044 VS |
10211 | #define MMCD_MISC_CTRL _MMIO(0x4ddc) /* skl+ */ |
10212 | #define MMCD_PCLA (1 << 31) | |
10213 | #define MMCD_HOTSPOT_EN (1 << 27) | |
10214 | ||
ad186f3f PZ |
10215 | #define _ICL_PHY_MISC_A 0x64C00 |
10216 | #define _ICL_PHY_MISC_B 0x64C04 | |
10217 | #define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, \ | |
10218 | _ICL_PHY_MISC_B) | |
10219 | #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23) | |
10220 | ||
585fb111 | 10221 | #endif /* _I915_REG_H_ */ |