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585fb111 JB |
1 | /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
2 | * All Rights Reserved. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the | |
6 | * "Software"), to deal in the Software without restriction, including | |
7 | * without limitation the rights to use, copy, modify, merge, publish, | |
8 | * distribute, sub license, and/or sell copies of the Software, and to | |
9 | * permit persons to whom the Software is furnished to do so, subject to | |
10 | * the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the | |
13 | * next paragraph) shall be included in all copies or substantial portions | |
14 | * of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
19 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
20 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
21 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
22 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #ifndef _I915_REG_H_ | |
26 | #define _I915_REG_H_ | |
27 | ||
5eddb70b | 28 | #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) |
a5c961d1 | 29 | #define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a))) |
5eddb70b | 30 | |
2b139522 ED |
31 | #define _PORT(port, a, b) ((a) + (port)*((b)-(a))) |
32 | ||
6b26c86d DV |
33 | #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a)) |
34 | #define _MASKED_BIT_DISABLE(a) ((a) << 16) | |
35 | ||
585fb111 JB |
36 | /* |
37 | * The Bridge device's PCI config space has information about the | |
38 | * fb aperture size and the amount of pre-reserved memory. | |
95375b7f DV |
39 | * This is all handled in the intel-gtt.ko module. i915.ko only |
40 | * cares about the vga bit for the vga rbiter. | |
585fb111 JB |
41 | */ |
42 | #define INTEL_GMCH_CTRL 0x52 | |
28d52043 | 43 | #define INTEL_GMCH_VGA_DISABLE (1 << 1) |
e76e9aeb BW |
44 | #define SNB_GMCH_CTRL 0x50 |
45 | #define SNB_GMCH_GGMS_SHIFT 8 /* GTT Graphics Memory Size */ | |
46 | #define SNB_GMCH_GGMS_MASK 0x3 | |
47 | #define SNB_GMCH_GMS_SHIFT 3 /* Graphics Mode Select */ | |
48 | #define SNB_GMCH_GMS_MASK 0x1f | |
03752f5b BW |
49 | #define IVB_GMCH_GMS_SHIFT 4 |
50 | #define IVB_GMCH_GMS_MASK 0xf | |
e76e9aeb | 51 | |
14bc490b | 52 | |
585fb111 JB |
53 | /* PCI config space */ |
54 | ||
55 | #define HPLLCC 0xc0 /* 855 only */ | |
652c393a | 56 | #define GC_CLOCK_CONTROL_MASK (0xf << 0) |
585fb111 JB |
57 | #define GC_CLOCK_133_200 (0 << 0) |
58 | #define GC_CLOCK_100_200 (1 << 0) | |
59 | #define GC_CLOCK_100_133 (2 << 0) | |
60 | #define GC_CLOCK_166_250 (3 << 0) | |
f97108d1 | 61 | #define GCFGC2 0xda |
585fb111 JB |
62 | #define GCFGC 0xf0 /* 915+ only */ |
63 | #define GC_LOW_FREQUENCY_ENABLE (1 << 7) | |
64 | #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) | |
65 | #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) | |
66 | #define GC_DISPLAY_CLOCK_MASK (7 << 4) | |
652c393a JB |
67 | #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) |
68 | #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) | |
69 | #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) | |
70 | #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) | |
71 | #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) | |
72 | #define I965_GC_RENDER_CLOCK_MASK (0xf << 0) | |
73 | #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) | |
74 | #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) | |
75 | #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) | |
76 | #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) | |
77 | #define I945_GC_RENDER_CLOCK_MASK (7 << 0) | |
78 | #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) | |
79 | #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) | |
80 | #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) | |
81 | #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) | |
82 | #define I915_GC_RENDER_CLOCK_MASK (7 << 0) | |
83 | #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) | |
84 | #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) | |
85 | #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) | |
585fb111 | 86 | #define LBB 0xf4 |
eeccdcac KG |
87 | |
88 | /* Graphics reset regs */ | |
0573ed4a KG |
89 | #define I965_GDRST 0xc0 /* PCI config register */ |
90 | #define ILK_GDSR 0x2ca4 /* MCHBAR offset */ | |
eeccdcac KG |
91 | #define GRDOM_FULL (0<<2) |
92 | #define GRDOM_RENDER (1<<2) | |
93 | #define GRDOM_MEDIA (3<<2) | |
5ccce180 | 94 | #define GRDOM_RESET_ENABLE (1<<0) |
585fb111 | 95 | |
07b7ddd9 JB |
96 | #define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */ |
97 | #define GEN6_MBC_SNPCR_SHIFT 21 | |
98 | #define GEN6_MBC_SNPCR_MASK (3<<21) | |
99 | #define GEN6_MBC_SNPCR_MAX (0<<21) | |
100 | #define GEN6_MBC_SNPCR_MED (1<<21) | |
101 | #define GEN6_MBC_SNPCR_LOW (2<<21) | |
102 | #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */ | |
103 | ||
5eb719cd DV |
104 | #define GEN6_MBCTL 0x0907c |
105 | #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) | |
106 | #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) | |
107 | #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) | |
108 | #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) | |
109 | #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0) | |
110 | ||
cff458c2 EA |
111 | #define GEN6_GDRST 0x941c |
112 | #define GEN6_GRDOM_FULL (1 << 0) | |
113 | #define GEN6_GRDOM_RENDER (1 << 1) | |
114 | #define GEN6_GRDOM_MEDIA (1 << 2) | |
115 | #define GEN6_GRDOM_BLT (1 << 3) | |
116 | ||
5eb719cd DV |
117 | #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228) |
118 | #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518) | |
119 | #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220) | |
120 | #define PP_DIR_DCLV_2G 0xffffffff | |
121 | ||
122 | #define GAM_ECOCHK 0x4090 | |
123 | #define ECOCHK_SNB_BIT (1<<10) | |
124 | #define ECOCHK_PPGTT_CACHE64B (0x3<<3) | |
125 | #define ECOCHK_PPGTT_CACHE4B (0x0<<3) | |
126 | ||
48ecfa10 DV |
127 | #define GAC_ECO_BITS 0x14090 |
128 | #define ECOBITS_PPGTT_CACHE64B (3<<8) | |
129 | #define ECOBITS_PPGTT_CACHE4B (0<<8) | |
130 | ||
be901a5a DV |
131 | #define GAB_CTL 0x24000 |
132 | #define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8) | |
133 | ||
585fb111 JB |
134 | /* VGA stuff */ |
135 | ||
136 | #define VGA_ST01_MDA 0x3ba | |
137 | #define VGA_ST01_CGA 0x3da | |
138 | ||
139 | #define VGA_MSR_WRITE 0x3c2 | |
140 | #define VGA_MSR_READ 0x3cc | |
141 | #define VGA_MSR_MEM_EN (1<<1) | |
142 | #define VGA_MSR_CGA_MODE (1<<0) | |
143 | ||
144 | #define VGA_SR_INDEX 0x3c4 | |
f930ddd0 | 145 | #define SR01 1 |
585fb111 JB |
146 | #define VGA_SR_DATA 0x3c5 |
147 | ||
148 | #define VGA_AR_INDEX 0x3c0 | |
149 | #define VGA_AR_VID_EN (1<<5) | |
150 | #define VGA_AR_DATA_WRITE 0x3c0 | |
151 | #define VGA_AR_DATA_READ 0x3c1 | |
152 | ||
153 | #define VGA_GR_INDEX 0x3ce | |
154 | #define VGA_GR_DATA 0x3cf | |
155 | /* GR05 */ | |
156 | #define VGA_GR_MEM_READ_MODE_SHIFT 3 | |
157 | #define VGA_GR_MEM_READ_MODE_PLANE 1 | |
158 | /* GR06 */ | |
159 | #define VGA_GR_MEM_MODE_MASK 0xc | |
160 | #define VGA_GR_MEM_MODE_SHIFT 2 | |
161 | #define VGA_GR_MEM_A0000_AFFFF 0 | |
162 | #define VGA_GR_MEM_A0000_BFFFF 1 | |
163 | #define VGA_GR_MEM_B0000_B7FFF 2 | |
164 | #define VGA_GR_MEM_B0000_BFFFF 3 | |
165 | ||
166 | #define VGA_DACMASK 0x3c6 | |
167 | #define VGA_DACRX 0x3c7 | |
168 | #define VGA_DACWX 0x3c8 | |
169 | #define VGA_DACDATA 0x3c9 | |
170 | ||
171 | #define VGA_CR_INDEX_MDA 0x3b4 | |
172 | #define VGA_CR_DATA_MDA 0x3b5 | |
173 | #define VGA_CR_INDEX_CGA 0x3d4 | |
174 | #define VGA_CR_DATA_CGA 0x3d5 | |
175 | ||
176 | /* | |
177 | * Memory interface instructions used by the kernel | |
178 | */ | |
179 | #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) | |
180 | ||
181 | #define MI_NOOP MI_INSTR(0, 0) | |
182 | #define MI_USER_INTERRUPT MI_INSTR(0x02, 0) | |
183 | #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) | |
02e792fb | 184 | #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) |
585fb111 JB |
185 | #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) |
186 | #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) | |
187 | #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) | |
188 | #define MI_FLUSH MI_INSTR(0x04, 0) | |
189 | #define MI_READ_FLUSH (1 << 0) | |
190 | #define MI_EXE_FLUSH (1 << 1) | |
191 | #define MI_NO_WRITE_FLUSH (1 << 2) | |
192 | #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ | |
193 | #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ | |
1cafd347 | 194 | #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ |
585fb111 | 195 | #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) |
88271da3 JB |
196 | #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) |
197 | #define MI_SUSPEND_FLUSH_EN (1<<0) | |
585fb111 | 198 | #define MI_REPORT_HEAD MI_INSTR(0x07, 0) |
0206e353 | 199 | #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0) |
02e792fb DV |
200 | #define MI_OVERLAY_CONTINUE (0x0<<21) |
201 | #define MI_OVERLAY_ON (0x1<<21) | |
202 | #define MI_OVERLAY_OFF (0x2<<21) | |
585fb111 | 203 | #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) |
6b95a207 | 204 | #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) |
1afe3e9d | 205 | #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) |
6b95a207 | 206 | #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) |
cb05d8de DV |
207 | /* IVB has funny definitions for which plane to flip. */ |
208 | #define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19) | |
209 | #define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19) | |
210 | #define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19) | |
211 | #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19) | |
212 | #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19) | |
213 | #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19) | |
e37ec39b BW |
214 | #define MI_ARB_ON_OFF MI_INSTR(0x08, 0) |
215 | #define MI_ARB_ENABLE (1<<0) | |
216 | #define MI_ARB_DISABLE (0<<0) | |
cb05d8de | 217 | |
aa40d6bb ZN |
218 | #define MI_SET_CONTEXT MI_INSTR(0x18, 0) |
219 | #define MI_MM_SPACE_GTT (1<<8) | |
220 | #define MI_MM_SPACE_PHYSICAL (0<<8) | |
221 | #define MI_SAVE_EXT_STATE_EN (1<<3) | |
222 | #define MI_RESTORE_EXT_STATE_EN (1<<2) | |
88271da3 | 223 | #define MI_FORCE_RESTORE (1<<1) |
aa40d6bb | 224 | #define MI_RESTORE_INHIBIT (1<<0) |
585fb111 JB |
225 | #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) |
226 | #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ | |
227 | #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) | |
228 | #define MI_STORE_DWORD_INDEX_SHIFT 2 | |
c6642782 DV |
229 | /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM: |
230 | * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw | |
231 | * simply ignores the register load under certain conditions. | |
232 | * - One can actually load arbitrary many arbitrary registers: Simply issue x | |
233 | * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! | |
234 | */ | |
235 | #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1) | |
71a77e07 | 236 | #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ |
9a289771 JB |
237 | #define MI_FLUSH_DW_STORE_INDEX (1<<21) |
238 | #define MI_INVALIDATE_TLB (1<<18) | |
239 | #define MI_FLUSH_DW_OP_STOREDW (1<<14) | |
240 | #define MI_INVALIDATE_BSD (1<<7) | |
241 | #define MI_FLUSH_DW_USE_GTT (1<<2) | |
242 | #define MI_FLUSH_DW_USE_PPGTT (0<<2) | |
585fb111 | 243 | #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) |
d7d4eedd CW |
244 | #define MI_BATCH_NON_SECURE (1) |
245 | /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */ | |
246 | #define MI_BATCH_NON_SECURE_I965 (1<<8) | |
247 | #define MI_BATCH_PPGTT_HSW (1<<8) | |
248 | #define MI_BATCH_NON_SECURE_HSW (1<<13) | |
585fb111 | 249 | #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) |
65f56876 | 250 | #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */ |
1ec14ad3 CW |
251 | #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */ |
252 | #define MI_SEMAPHORE_GLOBAL_GTT (1<<22) | |
253 | #define MI_SEMAPHORE_UPDATE (1<<21) | |
254 | #define MI_SEMAPHORE_COMPARE (1<<20) | |
255 | #define MI_SEMAPHORE_REGISTER (1<<18) | |
c8c99b0f BW |
256 | #define MI_SEMAPHORE_SYNC_RV (2<<16) |
257 | #define MI_SEMAPHORE_SYNC_RB (0<<16) | |
258 | #define MI_SEMAPHORE_SYNC_VR (0<<16) | |
259 | #define MI_SEMAPHORE_SYNC_VB (2<<16) | |
260 | #define MI_SEMAPHORE_SYNC_BR (2<<16) | |
261 | #define MI_SEMAPHORE_SYNC_BV (0<<16) | |
262 | #define MI_SEMAPHORE_SYNC_INVALID (1<<0) | |
585fb111 JB |
263 | /* |
264 | * 3D instructions used by the kernel | |
265 | */ | |
266 | #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) | |
267 | ||
268 | #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) | |
269 | #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) | |
270 | #define SC_UPDATE_SCISSOR (0x1<<1) | |
271 | #define SC_ENABLE_MASK (0x1<<0) | |
272 | #define SC_ENABLE (0x1<<0) | |
273 | #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) | |
274 | #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) | |
275 | #define SCI_YMIN_MASK (0xffff<<16) | |
276 | #define SCI_XMIN_MASK (0xffff<<0) | |
277 | #define SCI_YMAX_MASK (0xffff<<16) | |
278 | #define SCI_XMAX_MASK (0xffff<<0) | |
279 | #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) | |
280 | #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) | |
281 | #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) | |
282 | #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) | |
283 | #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) | |
284 | #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) | |
285 | #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) | |
286 | #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) | |
287 | #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) | |
288 | #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) | |
289 | #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) | |
290 | #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) | |
291 | #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) | |
292 | #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) | |
293 | #define BLT_DEPTH_8 (0<<24) | |
294 | #define BLT_DEPTH_16_565 (1<<24) | |
295 | #define BLT_DEPTH_16_1555 (2<<24) | |
296 | #define BLT_DEPTH_32 (3<<24) | |
297 | #define BLT_ROP_GXCOPY (0xcc<<16) | |
298 | #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ | |
299 | #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ | |
300 | #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) | |
301 | #define ASYNC_FLIP (1<<22) | |
302 | #define DISPLAY_PLANE_A (0<<20) | |
303 | #define DISPLAY_PLANE_B (1<<20) | |
fcbc34e4 | 304 | #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2)) |
8d315287 | 305 | #define PIPE_CONTROL_CS_STALL (1<<20) |
cc0f6398 | 306 | #define PIPE_CONTROL_TLB_INVALIDATE (1<<18) |
9d971b37 KG |
307 | #define PIPE_CONTROL_QW_WRITE (1<<14) |
308 | #define PIPE_CONTROL_DEPTH_STALL (1<<13) | |
309 | #define PIPE_CONTROL_WRITE_FLUSH (1<<12) | |
8d315287 | 310 | #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ |
9d971b37 KG |
311 | #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ |
312 | #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ | |
313 | #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) | |
314 | #define PIPE_CONTROL_NOTIFY (1<<8) | |
8d315287 JB |
315 | #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) |
316 | #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) | |
317 | #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) | |
9d971b37 | 318 | #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) |
8d315287 | 319 | #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) |
e552eb70 | 320 | #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ |
585fb111 | 321 | |
dc96e9b8 CW |
322 | |
323 | /* | |
324 | * Reset registers | |
325 | */ | |
326 | #define DEBUG_RESET_I830 0x6070 | |
327 | #define DEBUG_RESET_FULL (1<<7) | |
328 | #define DEBUG_RESET_RENDER (1<<8) | |
329 | #define DEBUG_RESET_DISPLAY (1<<9) | |
330 | ||
57f350b6 JB |
331 | /* |
332 | * DPIO - a special bus for various display related registers to hide behind: | |
333 | * 0x800c: m1, m2, n, p1, p2, k dividers | |
334 | * 0x8014: REF and SFR select | |
335 | * 0x8014: N divider, VCO select | |
336 | * 0x801c/3c: core clock bits | |
337 | * 0x8048/68: low pass filter coefficients | |
338 | * 0x8100: fast clock controls | |
54d9d493 VS |
339 | * |
340 | * DPIO is VLV only. | |
57f350b6 | 341 | */ |
54d9d493 | 342 | #define DPIO_PKT (VLV_DISPLAY_BASE + 0x2100) |
57f350b6 JB |
343 | #define DPIO_RID (0<<24) |
344 | #define DPIO_OP_WRITE (1<<16) | |
345 | #define DPIO_OP_READ (0<<16) | |
346 | #define DPIO_PORTID (0x12<<8) | |
347 | #define DPIO_BYTE (0xf<<4) | |
348 | #define DPIO_BUSY (1<<0) /* status only */ | |
54d9d493 VS |
349 | #define DPIO_DATA (VLV_DISPLAY_BASE + 0x2104) |
350 | #define DPIO_REG (VLV_DISPLAY_BASE + 0x2108) | |
351 | #define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110) | |
57f350b6 JB |
352 | #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */ |
353 | #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */ | |
354 | #define DPIO_SFR_BYPASS (1<<1) | |
355 | #define DPIO_RESET (1<<0) | |
356 | ||
357 | #define _DPIO_DIV_A 0x800c | |
358 | #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ | |
359 | #define DPIO_K_SHIFT (24) /* 4 bits */ | |
360 | #define DPIO_P1_SHIFT (21) /* 3 bits */ | |
361 | #define DPIO_P2_SHIFT (16) /* 5 bits */ | |
362 | #define DPIO_N_SHIFT (12) /* 4 bits */ | |
363 | #define DPIO_ENABLE_CALIBRATION (1<<11) | |
364 | #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ | |
365 | #define DPIO_M2DIV_MASK 0xff | |
366 | #define _DPIO_DIV_B 0x802c | |
367 | #define DPIO_DIV(pipe) _PIPE(pipe, _DPIO_DIV_A, _DPIO_DIV_B) | |
368 | ||
369 | #define _DPIO_REFSFR_A 0x8014 | |
370 | #define DPIO_REFSEL_OVERRIDE 27 | |
371 | #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ | |
372 | #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ | |
373 | #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ | |
b56747aa | 374 | #define DPIO_PLL_REFCLK_SEL_MASK 3 |
57f350b6 JB |
375 | #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ |
376 | #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ | |
377 | #define _DPIO_REFSFR_B 0x8034 | |
378 | #define DPIO_REFSFR(pipe) _PIPE(pipe, _DPIO_REFSFR_A, _DPIO_REFSFR_B) | |
379 | ||
380 | #define _DPIO_CORE_CLK_A 0x801c | |
381 | #define _DPIO_CORE_CLK_B 0x803c | |
382 | #define DPIO_CORE_CLK(pipe) _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B) | |
383 | ||
384 | #define _DPIO_LFP_COEFF_A 0x8048 | |
385 | #define _DPIO_LFP_COEFF_B 0x8068 | |
386 | #define DPIO_LFP_COEFF(pipe) _PIPE(pipe, _DPIO_LFP_COEFF_A, _DPIO_LFP_COEFF_B) | |
387 | ||
388 | #define DPIO_FASTCLK_DISABLE 0x8100 | |
dc96e9b8 | 389 | |
2a8f64ca VP |
390 | #define DPIO_DATA_CHANNEL1 0x8220 |
391 | #define DPIO_DATA_CHANNEL2 0x8420 | |
b56747aa | 392 | |
585fb111 | 393 | /* |
de151cf6 | 394 | * Fence registers |
585fb111 | 395 | */ |
de151cf6 | 396 | #define FENCE_REG_830_0 0x2000 |
dc529a4f | 397 | #define FENCE_REG_945_8 0x3000 |
de151cf6 JB |
398 | #define I830_FENCE_START_MASK 0x07f80000 |
399 | #define I830_FENCE_TILING_Y_SHIFT 12 | |
0f973f27 | 400 | #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) |
de151cf6 JB |
401 | #define I830_FENCE_PITCH_SHIFT 4 |
402 | #define I830_FENCE_REG_VALID (1<<0) | |
c36a2a6d | 403 | #define I915_FENCE_MAX_PITCH_VAL 4 |
e76a16de | 404 | #define I830_FENCE_MAX_PITCH_VAL 6 |
8d7773a3 | 405 | #define I830_FENCE_MAX_SIZE_VAL (1<<8) |
de151cf6 JB |
406 | |
407 | #define I915_FENCE_START_MASK 0x0ff00000 | |
0f973f27 | 408 | #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) |
585fb111 | 409 | |
de151cf6 JB |
410 | #define FENCE_REG_965_0 0x03000 |
411 | #define I965_FENCE_PITCH_SHIFT 2 | |
412 | #define I965_FENCE_TILING_Y_SHIFT 1 | |
413 | #define I965_FENCE_REG_VALID (1<<0) | |
8d7773a3 | 414 | #define I965_FENCE_MAX_PITCH_VAL 0x0400 |
de151cf6 | 415 | |
4e901fdc EA |
416 | #define FENCE_REG_SANDYBRIDGE_0 0x100000 |
417 | #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 | |
418 | ||
f691e2f4 DV |
419 | /* control register for cpu gtt access */ |
420 | #define TILECTL 0x101000 | |
421 | #define TILECTL_SWZCTL (1 << 0) | |
422 | #define TILECTL_TLB_PREFETCH_DIS (1 << 2) | |
423 | #define TILECTL_BACKSNOOP_DIS (1 << 3) | |
424 | ||
de151cf6 JB |
425 | /* |
426 | * Instruction and interrupt control regs | |
427 | */ | |
63eeaf38 | 428 | #define PGTBL_ER 0x02024 |
333e9fe9 DV |
429 | #define RENDER_RING_BASE 0x02000 |
430 | #define BSD_RING_BASE 0x04000 | |
431 | #define GEN6_BSD_RING_BASE 0x12000 | |
549f7365 | 432 | #define BLT_RING_BASE 0x22000 |
3d281d8c DV |
433 | #define RING_TAIL(base) ((base)+0x30) |
434 | #define RING_HEAD(base) ((base)+0x34) | |
435 | #define RING_START(base) ((base)+0x38) | |
436 | #define RING_CTL(base) ((base)+0x3c) | |
1ec14ad3 CW |
437 | #define RING_SYNC_0(base) ((base)+0x40) |
438 | #define RING_SYNC_1(base) ((base)+0x44) | |
c8c99b0f BW |
439 | #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE)) |
440 | #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE)) | |
441 | #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE)) | |
442 | #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE)) | |
443 | #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE)) | |
444 | #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE)) | |
8fd26859 | 445 | #define RING_MAX_IDLE(base) ((base)+0x54) |
3d281d8c DV |
446 | #define RING_HWS_PGA(base) ((base)+0x80) |
447 | #define RING_HWS_PGA_GEN6(base) ((base)+0x2080) | |
f691e2f4 DV |
448 | #define ARB_MODE 0x04030 |
449 | #define ARB_MODE_SWIZZLE_SNB (1<<4) | |
450 | #define ARB_MODE_SWIZZLE_IVB (1<<5) | |
4593010b | 451 | #define RENDER_HWS_PGA_GEN7 (0x04080) |
33f3f518 DV |
452 | #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id) |
453 | #define DONE_REG 0x40b0 | |
4593010b EA |
454 | #define BSD_HWS_PGA_GEN7 (0x04180) |
455 | #define BLT_HWS_PGA_GEN7 (0x04280) | |
3d281d8c | 456 | #define RING_ACTHD(base) ((base)+0x74) |
1ec14ad3 | 457 | #define RING_NOPID(base) ((base)+0x94) |
0f46832f | 458 | #define RING_IMR(base) ((base)+0xa8) |
c0c7babc | 459 | #define RING_TIMESTAMP(base) ((base)+0x358) |
585fb111 JB |
460 | #define TAIL_ADDR 0x001FFFF8 |
461 | #define HEAD_WRAP_COUNT 0xFFE00000 | |
462 | #define HEAD_WRAP_ONE 0x00200000 | |
463 | #define HEAD_ADDR 0x001FFFFC | |
464 | #define RING_NR_PAGES 0x001FF000 | |
465 | #define RING_REPORT_MASK 0x00000006 | |
466 | #define RING_REPORT_64K 0x00000002 | |
467 | #define RING_REPORT_128K 0x00000004 | |
468 | #define RING_NO_REPORT 0x00000000 | |
469 | #define RING_VALID_MASK 0x00000001 | |
470 | #define RING_VALID 0x00000001 | |
471 | #define RING_INVALID 0x00000000 | |
4b60e5cb CW |
472 | #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ |
473 | #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ | |
1ec14ad3 | 474 | #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ |
8168bd48 CW |
475 | #if 0 |
476 | #define PRB0_TAIL 0x02030 | |
477 | #define PRB0_HEAD 0x02034 | |
478 | #define PRB0_START 0x02038 | |
479 | #define PRB0_CTL 0x0203c | |
585fb111 JB |
480 | #define PRB1_TAIL 0x02040 /* 915+ only */ |
481 | #define PRB1_HEAD 0x02044 /* 915+ only */ | |
482 | #define PRB1_START 0x02048 /* 915+ only */ | |
483 | #define PRB1_CTL 0x0204c /* 915+ only */ | |
8168bd48 | 484 | #endif |
63eeaf38 JB |
485 | #define IPEIR_I965 0x02064 |
486 | #define IPEHR_I965 0x02068 | |
487 | #define INSTDONE_I965 0x0206c | |
d53bd484 BW |
488 | #define GEN7_INSTDONE_1 0x0206c |
489 | #define GEN7_SC_INSTDONE 0x07100 | |
490 | #define GEN7_SAMPLER_INSTDONE 0x0e160 | |
491 | #define GEN7_ROW_INSTDONE 0x0e164 | |
492 | #define I915_NUM_INSTDONE_REG 4 | |
d27b1e0e DV |
493 | #define RING_IPEIR(base) ((base)+0x64) |
494 | #define RING_IPEHR(base) ((base)+0x68) | |
495 | #define RING_INSTDONE(base) ((base)+0x6c) | |
c1cd90ed DV |
496 | #define RING_INSTPS(base) ((base)+0x70) |
497 | #define RING_DMA_FADD(base) ((base)+0x78) | |
498 | #define RING_INSTPM(base) ((base)+0xc0) | |
63eeaf38 JB |
499 | #define INSTPS 0x02070 /* 965+ only */ |
500 | #define INSTDONE1 0x0207c /* 965+ only */ | |
585fb111 JB |
501 | #define ACTHD_I965 0x02074 |
502 | #define HWS_PGA 0x02080 | |
503 | #define HWS_ADDRESS_MASK 0xfffff000 | |
504 | #define HWS_START_ADDRESS_SHIFT 4 | |
97f5ab66 JB |
505 | #define PWRCTXA 0x2088 /* 965GM+ only */ |
506 | #define PWRCTX_EN (1<<0) | |
585fb111 | 507 | #define IPEIR 0x02088 |
63eeaf38 JB |
508 | #define IPEHR 0x0208c |
509 | #define INSTDONE 0x02090 | |
585fb111 JB |
510 | #define NOPID 0x02094 |
511 | #define HWSTAM 0x02098 | |
9d2f41fa | 512 | #define DMA_FADD_I8XX 0x020d0 |
71cf39b1 | 513 | |
f406839f | 514 | #define ERROR_GEN6 0x040a0 |
71e172e8 | 515 | #define GEN7_ERR_INT 0x44040 |
b4c145c1 | 516 | #define ERR_INT_MMIO_UNCLAIMED (1<<13) |
f406839f | 517 | |
de6e2eaf EA |
518 | /* GM45+ chicken bits -- debug workaround bits that may be required |
519 | * for various sorts of correct behavior. The top 16 bits of each are | |
520 | * the enables for writing to the corresponding low bit. | |
521 | */ | |
522 | #define _3D_CHICKEN 0x02084 | |
4283908e | 523 | #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10) |
de6e2eaf EA |
524 | #define _3D_CHICKEN2 0x0208c |
525 | /* Disables pipelining of read flushes past the SF-WIZ interface. | |
526 | * Required on all Ironlake steppings according to the B-Spec, but the | |
527 | * particular danger of not doing so is not specified. | |
528 | */ | |
529 | # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) | |
530 | #define _3D_CHICKEN3 0x02090 | |
87f8020e | 531 | #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) |
26b6e44a | 532 | #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) |
de6e2eaf | 533 | |
71cf39b1 EA |
534 | #define MI_MODE 0x0209c |
535 | # define VS_TIMER_DISPATCH (1 << 6) | |
fc74d8e0 | 536 | # define MI_FLUSH_ENABLE (1 << 12) |
71cf39b1 | 537 | |
f8f2ac9a | 538 | #define GEN6_GT_MODE 0x20d0 |
6547fbdb DV |
539 | #define GEN6_GT_MODE_HI (1 << 9) |
540 | #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5) | |
f8f2ac9a | 541 | |
1ec14ad3 | 542 | #define GFX_MODE 0x02520 |
b095cd0a | 543 | #define GFX_MODE_GEN7 0x0229c |
5eb719cd | 544 | #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c) |
1ec14ad3 CW |
545 | #define GFX_RUN_LIST_ENABLE (1<<15) |
546 | #define GFX_TLB_INVALIDATE_ALWAYS (1<<13) | |
547 | #define GFX_SURFACE_FAULT_ENABLE (1<<12) | |
548 | #define GFX_REPLAY_MODE (1<<11) | |
549 | #define GFX_PSMI_GRANULARITY (1<<10) | |
550 | #define GFX_PPGTT_ENABLE (1<<9) | |
551 | ||
a7e806de DV |
552 | #define VLV_DISPLAY_BASE 0x180000 |
553 | ||
585fb111 JB |
554 | #define SCPD0 0x0209c /* 915+ only */ |
555 | #define IER 0x020a0 | |
556 | #define IIR 0x020a4 | |
557 | #define IMR 0x020a8 | |
558 | #define ISR 0x020ac | |
07ec7ec5 | 559 | #define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060) |
2d809570 | 560 | #define GCFG_DIS (1<<8) |
ff763010 VS |
561 | #define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084) |
562 | #define VLV_IER (VLV_DISPLAY_BASE + 0x20a0) | |
563 | #define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4) | |
564 | #define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8) | |
565 | #define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac) | |
585fb111 JB |
566 | #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) |
567 | #define I915_DISPLAY_PORT_INTERRUPT (1<<17) | |
568 | #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) | |
f97108d1 | 569 | #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ |
585fb111 JB |
570 | #define I915_HWB_OOM_INTERRUPT (1<<13) |
571 | #define I915_SYNC_STATUS_INTERRUPT (1<<12) | |
572 | #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) | |
573 | #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) | |
574 | #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) | |
575 | #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) | |
576 | #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) | |
577 | #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) | |
578 | #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) | |
579 | #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) | |
580 | #define I915_DEBUG_INTERRUPT (1<<2) | |
581 | #define I915_USER_INTERRUPT (1<<1) | |
582 | #define I915_ASLE_INTERRUPT (1<<0) | |
d1b851fc | 583 | #define I915_BSD_USER_INTERRUPT (1<<25) |
585fb111 JB |
584 | #define EIR 0x020b0 |
585 | #define EMR 0x020b4 | |
586 | #define ESR 0x020b8 | |
63eeaf38 JB |
587 | #define GM45_ERROR_PAGE_TABLE (1<<5) |
588 | #define GM45_ERROR_MEM_PRIV (1<<4) | |
589 | #define I915_ERROR_PAGE_TABLE (1<<4) | |
590 | #define GM45_ERROR_CP_PRIV (1<<3) | |
591 | #define I915_ERROR_MEMORY_REFRESH (1<<1) | |
592 | #define I915_ERROR_INSTRUCTION (1<<0) | |
585fb111 | 593 | #define INSTPM 0x020c0 |
ee980b80 | 594 | #define INSTPM_SELF_EN (1<<12) /* 915GM only */ |
8692d00e CW |
595 | #define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts |
596 | will not assert AGPBUSY# and will only | |
597 | be delivered when out of C3. */ | |
84f9f938 | 598 | #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ |
585fb111 JB |
599 | #define ACTHD 0x020c8 |
600 | #define FW_BLC 0x020d8 | |
8692d00e | 601 | #define FW_BLC2 0x020dc |
585fb111 | 602 | #define FW_BLC_SELF 0x020e0 /* 915+ only */ |
ee980b80 LP |
603 | #define FW_BLC_SELF_EN_MASK (1<<31) |
604 | #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ | |
605 | #define FW_BLC_SELF_EN (1<<15) /* 945 only */ | |
7662c8bd SL |
606 | #define MM_BURST_LENGTH 0x00700000 |
607 | #define MM_FIFO_WATERMARK 0x0001F000 | |
608 | #define LM_BURST_LENGTH 0x00000700 | |
609 | #define LM_FIFO_WATERMARK 0x0000001F | |
585fb111 | 610 | #define MI_ARB_STATE 0x020e4 /* 915+ only */ |
45503ded KP |
611 | |
612 | /* Make render/texture TLB fetches lower priorty than associated data | |
613 | * fetches. This is not turned on by default | |
614 | */ | |
615 | #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) | |
616 | ||
617 | /* Isoch request wait on GTT enable (Display A/B/C streams). | |
618 | * Make isoch requests stall on the TLB update. May cause | |
619 | * display underruns (test mode only) | |
620 | */ | |
621 | #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) | |
622 | ||
623 | /* Block grant count for isoch requests when block count is | |
624 | * set to a finite value. | |
625 | */ | |
626 | #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) | |
627 | #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ | |
628 | #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ | |
629 | #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ | |
630 | #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ | |
631 | ||
632 | /* Enable render writes to complete in C2/C3/C4 power states. | |
633 | * If this isn't enabled, render writes are prevented in low | |
634 | * power states. That seems bad to me. | |
635 | */ | |
636 | #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) | |
637 | ||
638 | /* This acknowledges an async flip immediately instead | |
639 | * of waiting for 2TLB fetches. | |
640 | */ | |
641 | #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) | |
642 | ||
643 | /* Enables non-sequential data reads through arbiter | |
644 | */ | |
0206e353 | 645 | #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) |
45503ded KP |
646 | |
647 | /* Disable FSB snooping of cacheable write cycles from binner/render | |
648 | * command stream | |
649 | */ | |
650 | #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) | |
651 | ||
652 | /* Arbiter time slice for non-isoch streams */ | |
653 | #define MI_ARB_TIME_SLICE_MASK (7 << 5) | |
654 | #define MI_ARB_TIME_SLICE_1 (0 << 5) | |
655 | #define MI_ARB_TIME_SLICE_2 (1 << 5) | |
656 | #define MI_ARB_TIME_SLICE_4 (2 << 5) | |
657 | #define MI_ARB_TIME_SLICE_6 (3 << 5) | |
658 | #define MI_ARB_TIME_SLICE_8 (4 << 5) | |
659 | #define MI_ARB_TIME_SLICE_10 (5 << 5) | |
660 | #define MI_ARB_TIME_SLICE_14 (6 << 5) | |
661 | #define MI_ARB_TIME_SLICE_16 (7 << 5) | |
662 | ||
663 | /* Low priority grace period page size */ | |
664 | #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ | |
665 | #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) | |
666 | ||
667 | /* Disable display A/B trickle feed */ | |
668 | #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) | |
669 | ||
670 | /* Set display plane priority */ | |
671 | #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ | |
672 | #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ | |
673 | ||
585fb111 | 674 | #define CACHE_MODE_0 0x02120 /* 915+ only */ |
4358a374 | 675 | #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8) |
585fb111 JB |
676 | #define CM0_IZ_OPT_DISABLE (1<<6) |
677 | #define CM0_ZR_OPT_DISABLE (1<<5) | |
009be664 | 678 | #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) |
585fb111 JB |
679 | #define CM0_DEPTH_EVICT_DISABLE (1<<4) |
680 | #define CM0_COLOR_EVICT_DISABLE (1<<3) | |
681 | #define CM0_DEPTH_WRITE_DISABLE (1<<1) | |
682 | #define CM0_RC_OP_FLUSH_DISABLE (1<<0) | |
9df30794 | 683 | #define BB_ADDR 0x02140 /* 8 bytes */ |
585fb111 | 684 | #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ |
0f9b91c7 BW |
685 | #define GFX_FLSH_CNTL_GEN6 0x101008 |
686 | #define GFX_FLSH_CNTL_EN (1<<0) | |
1afe3e9d JB |
687 | #define ECOSKPD 0x021d0 |
688 | #define ECO_GATING_CX_ONLY (1<<3) | |
689 | #define ECO_FLIP_DONE (1<<0) | |
585fb111 | 690 | |
fb046853 JB |
691 | #define CACHE_MODE_1 0x7004 /* IVB+ */ |
692 | #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) | |
693 | ||
e2a1e2f0 BW |
694 | /* GEN6 interrupt control |
695 | * Note that the per-ring interrupt bits do alias with the global interrupt bits | |
696 | * in GTIMR. */ | |
a1786bd2 ZW |
697 | #define GEN6_RENDER_HWSTAM 0x2098 |
698 | #define GEN6_RENDER_IMR 0x20a8 | |
699 | #define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8) | |
700 | #define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7) | |
7aa69d2e | 701 | #define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6) |
a1786bd2 ZW |
702 | #define GEN6_RENDER_L3_PARITY_ERROR (1 << 5) |
703 | #define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4) | |
704 | #define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3) | |
705 | #define GEN6_RENDER_SYNC_STATUS (1 << 2) | |
706 | #define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1) | |
707 | #define GEN6_RENDER_USER_INTERRUPT (1 << 0) | |
708 | ||
709 | #define GEN6_BLITTER_HWSTAM 0x22098 | |
710 | #define GEN6_BLITTER_IMR 0x220a8 | |
711 | #define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26) | |
712 | #define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25) | |
713 | #define GEN6_BLITTER_SYNC_STATUS (1 << 24) | |
714 | #define GEN6_BLITTER_USER_INTERRUPT (1 << 22) | |
881f47b6 | 715 | |
4efe0708 JB |
716 | #define GEN6_BLITTER_ECOSKPD 0x221d0 |
717 | #define GEN6_BLITTER_LOCK_SHIFT 16 | |
718 | #define GEN6_BLITTER_FBC_NOTIFY (1<<3) | |
719 | ||
881f47b6 | 720 | #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 |
12f55818 CW |
721 | #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0) |
722 | #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2) | |
723 | #define GEN6_BSD_SLEEP_INDICATOR (1 << 3) | |
724 | #define GEN6_BSD_GO_INDICATOR (1 << 4) | |
881f47b6 | 725 | |
ec6a890d | 726 | #define GEN6_BSD_HWSTAM 0x12098 |
881f47b6 | 727 | #define GEN6_BSD_IMR 0x120a8 |
1ec14ad3 | 728 | #define GEN6_BSD_USER_INTERRUPT (1 << 12) |
881f47b6 XH |
729 | |
730 | #define GEN6_BSD_RNCID 0x12198 | |
731 | ||
a1e969e0 BW |
732 | #define GEN7_FF_THREAD_MODE 0x20a0 |
733 | #define GEN7_FF_SCHED_MASK 0x0077070 | |
734 | #define GEN7_FF_TS_SCHED_HS1 (0x5<<16) | |
735 | #define GEN7_FF_TS_SCHED_HS0 (0x3<<16) | |
736 | #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16) | |
737 | #define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */ | |
738 | #define GEN7_FF_VS_SCHED_HS1 (0x5<<12) | |
739 | #define GEN7_FF_VS_SCHED_HS0 (0x3<<12) | |
740 | #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */ | |
741 | #define GEN7_FF_VS_SCHED_HW (0x0<<12) | |
742 | #define GEN7_FF_DS_SCHED_HS1 (0x5<<4) | |
743 | #define GEN7_FF_DS_SCHED_HS0 (0x3<<4) | |
744 | #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */ | |
745 | #define GEN7_FF_DS_SCHED_HW (0x0<<4) | |
746 | ||
585fb111 JB |
747 | /* |
748 | * Framebuffer compression (915+ only) | |
749 | */ | |
750 | ||
751 | #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ | |
752 | #define FBC_LL_BASE 0x03204 /* 4k page aligned */ | |
753 | #define FBC_CONTROL 0x03208 | |
754 | #define FBC_CTL_EN (1<<31) | |
755 | #define FBC_CTL_PERIODIC (1<<30) | |
756 | #define FBC_CTL_INTERVAL_SHIFT (16) | |
757 | #define FBC_CTL_UNCOMPRESSIBLE (1<<14) | |
49677901 | 758 | #define FBC_CTL_C3_IDLE (1<<13) |
585fb111 JB |
759 | #define FBC_CTL_STRIDE_SHIFT (5) |
760 | #define FBC_CTL_FENCENO (1<<0) | |
761 | #define FBC_COMMAND 0x0320c | |
762 | #define FBC_CMD_COMPRESS (1<<0) | |
763 | #define FBC_STATUS 0x03210 | |
764 | #define FBC_STAT_COMPRESSING (1<<31) | |
765 | #define FBC_STAT_COMPRESSED (1<<30) | |
766 | #define FBC_STAT_MODIFIED (1<<29) | |
767 | #define FBC_STAT_CURRENT_LINE (1<<0) | |
768 | #define FBC_CONTROL2 0x03214 | |
769 | #define FBC_CTL_FENCE_DBL (0<<4) | |
770 | #define FBC_CTL_IDLE_IMM (0<<2) | |
771 | #define FBC_CTL_IDLE_FULL (1<<2) | |
772 | #define FBC_CTL_IDLE_LINE (2<<2) | |
773 | #define FBC_CTL_IDLE_DEBUG (3<<2) | |
774 | #define FBC_CTL_CPU_FENCE (1<<1) | |
775 | #define FBC_CTL_PLANEA (0<<0) | |
776 | #define FBC_CTL_PLANEB (1<<0) | |
777 | #define FBC_FENCE_OFF 0x0321b | |
80824003 | 778 | #define FBC_TAG 0x03300 |
585fb111 JB |
779 | |
780 | #define FBC_LL_SIZE (1536) | |
781 | ||
74dff282 JB |
782 | /* Framebuffer compression for GM45+ */ |
783 | #define DPFC_CB_BASE 0x3200 | |
784 | #define DPFC_CONTROL 0x3208 | |
785 | #define DPFC_CTL_EN (1<<31) | |
786 | #define DPFC_CTL_PLANEA (0<<30) | |
787 | #define DPFC_CTL_PLANEB (1<<30) | |
788 | #define DPFC_CTL_FENCE_EN (1<<29) | |
9ce9d069 | 789 | #define DPFC_CTL_PERSISTENT_MODE (1<<25) |
74dff282 JB |
790 | #define DPFC_SR_EN (1<<10) |
791 | #define DPFC_CTL_LIMIT_1X (0<<6) | |
792 | #define DPFC_CTL_LIMIT_2X (1<<6) | |
793 | #define DPFC_CTL_LIMIT_4X (2<<6) | |
794 | #define DPFC_RECOMP_CTL 0x320c | |
795 | #define DPFC_RECOMP_STALL_EN (1<<27) | |
796 | #define DPFC_RECOMP_STALL_WM_SHIFT (16) | |
797 | #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) | |
798 | #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) | |
799 | #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) | |
800 | #define DPFC_STATUS 0x3210 | |
801 | #define DPFC_INVAL_SEG_SHIFT (16) | |
802 | #define DPFC_INVAL_SEG_MASK (0x07ff0000) | |
803 | #define DPFC_COMP_SEG_SHIFT (0) | |
804 | #define DPFC_COMP_SEG_MASK (0x000003ff) | |
805 | #define DPFC_STATUS2 0x3214 | |
806 | #define DPFC_FENCE_YOFF 0x3218 | |
807 | #define DPFC_CHICKEN 0x3224 | |
808 | #define DPFC_HT_MODIFY (1<<31) | |
809 | ||
b52eb4dc ZY |
810 | /* Framebuffer compression for Ironlake */ |
811 | #define ILK_DPFC_CB_BASE 0x43200 | |
812 | #define ILK_DPFC_CONTROL 0x43208 | |
813 | /* The bit 28-8 is reserved */ | |
814 | #define DPFC_RESERVED (0x1FFFFF00) | |
815 | #define ILK_DPFC_RECOMP_CTL 0x4320c | |
816 | #define ILK_DPFC_STATUS 0x43210 | |
817 | #define ILK_DPFC_FENCE_YOFF 0x43218 | |
818 | #define ILK_DPFC_CHICKEN 0x43224 | |
819 | #define ILK_FBC_RT_BASE 0x2128 | |
820 | #define ILK_FBC_RT_VALID (1<<0) | |
821 | ||
822 | #define ILK_DISPLAY_CHICKEN1 0x42000 | |
823 | #define ILK_FBCQ_DIS (1<<22) | |
0206e353 | 824 | #define ILK_PABSTRETCH_DIS (1<<21) |
1398261a | 825 | |
b52eb4dc | 826 | |
9c04f015 YL |
827 | /* |
828 | * Framebuffer compression for Sandybridge | |
829 | * | |
830 | * The following two registers are of type GTTMMADR | |
831 | */ | |
832 | #define SNB_DPFC_CTL_SA 0x100100 | |
833 | #define SNB_CPU_FENCE_ENABLE (1<<29) | |
834 | #define DPFC_CPU_FENCE_OFFSET 0x100104 | |
835 | ||
836 | ||
585fb111 JB |
837 | /* |
838 | * GPIO regs | |
839 | */ | |
840 | #define GPIOA 0x5010 | |
841 | #define GPIOB 0x5014 | |
842 | #define GPIOC 0x5018 | |
843 | #define GPIOD 0x501c | |
844 | #define GPIOE 0x5020 | |
845 | #define GPIOF 0x5024 | |
846 | #define GPIOG 0x5028 | |
847 | #define GPIOH 0x502c | |
848 | # define GPIO_CLOCK_DIR_MASK (1 << 0) | |
849 | # define GPIO_CLOCK_DIR_IN (0 << 1) | |
850 | # define GPIO_CLOCK_DIR_OUT (1 << 1) | |
851 | # define GPIO_CLOCK_VAL_MASK (1 << 2) | |
852 | # define GPIO_CLOCK_VAL_OUT (1 << 3) | |
853 | # define GPIO_CLOCK_VAL_IN (1 << 4) | |
854 | # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) | |
855 | # define GPIO_DATA_DIR_MASK (1 << 8) | |
856 | # define GPIO_DATA_DIR_IN (0 << 9) | |
857 | # define GPIO_DATA_DIR_OUT (1 << 9) | |
858 | # define GPIO_DATA_VAL_MASK (1 << 10) | |
859 | # define GPIO_DATA_VAL_OUT (1 << 11) | |
860 | # define GPIO_DATA_VAL_IN (1 << 12) | |
861 | # define GPIO_DATA_PULLUP_DISABLE (1 << 13) | |
862 | ||
f899fc64 CW |
863 | #define GMBUS0 0x5100 /* clock/port select */ |
864 | #define GMBUS_RATE_100KHZ (0<<8) | |
865 | #define GMBUS_RATE_50KHZ (1<<8) | |
866 | #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ | |
867 | #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ | |
868 | #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ | |
869 | #define GMBUS_PORT_DISABLED 0 | |
870 | #define GMBUS_PORT_SSC 1 | |
871 | #define GMBUS_PORT_VGADDC 2 | |
872 | #define GMBUS_PORT_PANEL 3 | |
873 | #define GMBUS_PORT_DPC 4 /* HDMIC */ | |
874 | #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ | |
e4fd17af DK |
875 | #define GMBUS_PORT_DPD 6 /* HDMID */ |
876 | #define GMBUS_PORT_RESERVED 7 /* 7 reserved */ | |
2ed06c93 | 877 | #define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1) |
f899fc64 CW |
878 | #define GMBUS1 0x5104 /* command/status */ |
879 | #define GMBUS_SW_CLR_INT (1<<31) | |
880 | #define GMBUS_SW_RDY (1<<30) | |
881 | #define GMBUS_ENT (1<<29) /* enable timeout */ | |
882 | #define GMBUS_CYCLE_NONE (0<<25) | |
883 | #define GMBUS_CYCLE_WAIT (1<<25) | |
884 | #define GMBUS_CYCLE_INDEX (2<<25) | |
885 | #define GMBUS_CYCLE_STOP (4<<25) | |
886 | #define GMBUS_BYTE_COUNT_SHIFT 16 | |
887 | #define GMBUS_SLAVE_INDEX_SHIFT 8 | |
888 | #define GMBUS_SLAVE_ADDR_SHIFT 1 | |
889 | #define GMBUS_SLAVE_READ (1<<0) | |
890 | #define GMBUS_SLAVE_WRITE (0<<0) | |
891 | #define GMBUS2 0x5108 /* status */ | |
892 | #define GMBUS_INUSE (1<<15) | |
893 | #define GMBUS_HW_WAIT_PHASE (1<<14) | |
894 | #define GMBUS_STALL_TIMEOUT (1<<13) | |
895 | #define GMBUS_INT (1<<12) | |
896 | #define GMBUS_HW_RDY (1<<11) | |
897 | #define GMBUS_SATOER (1<<10) | |
898 | #define GMBUS_ACTIVE (1<<9) | |
899 | #define GMBUS3 0x510c /* data buffer bytes 3-0 */ | |
900 | #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */ | |
901 | #define GMBUS_SLAVE_TIMEOUT_EN (1<<4) | |
902 | #define GMBUS_NAK_EN (1<<3) | |
903 | #define GMBUS_IDLE_EN (1<<2) | |
904 | #define GMBUS_HW_WAIT_EN (1<<1) | |
905 | #define GMBUS_HW_RDY_EN (1<<0) | |
906 | #define GMBUS5 0x5120 /* byte index */ | |
907 | #define GMBUS_2BYTE_INDEX_EN (1<<31) | |
f0217c42 | 908 | |
585fb111 JB |
909 | /* |
910 | * Clock control & power management | |
911 | */ | |
912 | ||
913 | #define VGA0 0x6000 | |
914 | #define VGA1 0x6004 | |
915 | #define VGA_PD 0x6010 | |
916 | #define VGA0_PD_P2_DIV_4 (1 << 7) | |
917 | #define VGA0_PD_P1_DIV_2 (1 << 5) | |
918 | #define VGA0_PD_P1_SHIFT 0 | |
919 | #define VGA0_PD_P1_MASK (0x1f << 0) | |
920 | #define VGA1_PD_P2_DIV_4 (1 << 15) | |
921 | #define VGA1_PD_P1_DIV_2 (1 << 13) | |
922 | #define VGA1_PD_P1_SHIFT 8 | |
923 | #define VGA1_PD_P1_MASK (0x1f << 8) | |
9db4a9c7 JB |
924 | #define _DPLL_A 0x06014 |
925 | #define _DPLL_B 0x06018 | |
926 | #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B) | |
585fb111 JB |
927 | #define DPLL_VCO_ENABLE (1 << 31) |
928 | #define DPLL_DVO_HIGH_SPEED (1 << 30) | |
25eb05fc | 929 | #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) |
585fb111 | 930 | #define DPLL_SYNCLOCK_ENABLE (1 << 29) |
25eb05fc | 931 | #define DPLL_REFA_CLK_ENABLE_VLV (1 << 29) |
585fb111 JB |
932 | #define DPLL_VGA_MODE_DIS (1 << 28) |
933 | #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ | |
934 | #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ | |
935 | #define DPLL_MODE_MASK (3 << 26) | |
936 | #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ | |
937 | #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ | |
938 | #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ | |
939 | #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ | |
940 | #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ | |
941 | #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ | |
f2b115e6 | 942 | #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ |
a0c4da24 | 943 | #define DPLL_LOCK_VLV (1<<15) |
25eb05fc | 944 | #define DPLL_INTEGRATED_CLOCK_VLV (1<<13) |
585fb111 | 945 | |
585fb111 JB |
946 | #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 |
947 | /* | |
948 | * The i830 generation, in LVDS mode, defines P1 as the bit number set within | |
949 | * this field (only one bit may be set). | |
950 | */ | |
951 | #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 | |
952 | #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 | |
f2b115e6 | 953 | #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 |
585fb111 JB |
954 | /* i830, required in DVO non-gang */ |
955 | #define PLL_P2_DIVIDE_BY_4 (1 << 23) | |
956 | #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ | |
957 | #define PLL_REF_INPUT_DREFCLK (0 << 13) | |
958 | #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ | |
959 | #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ | |
960 | #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) | |
961 | #define PLL_REF_INPUT_MASK (3 << 13) | |
962 | #define PLL_LOAD_PULSE_PHASE_SHIFT 9 | |
f2b115e6 | 963 | /* Ironlake */ |
b9055052 ZW |
964 | # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 |
965 | # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) | |
966 | # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) | |
967 | # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 | |
968 | # define DPLL_FPA1_P1_POST_DIV_MASK 0xff | |
969 | ||
585fb111 JB |
970 | /* |
971 | * Parallel to Serial Load Pulse phase selection. | |
972 | * Selects the phase for the 10X DPLL clock for the PCIe | |
973 | * digital display port. The range is 4 to 13; 10 or more | |
974 | * is just a flip delay. The default is 6 | |
975 | */ | |
976 | #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) | |
977 | #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) | |
978 | /* | |
979 | * SDVO multiplier for 945G/GM. Not used on 965. | |
980 | */ | |
981 | #define SDVO_MULTIPLIER_MASK 0x000000ff | |
982 | #define SDVO_MULTIPLIER_SHIFT_HIRES 4 | |
983 | #define SDVO_MULTIPLIER_SHIFT_VGA 0 | |
9db4a9c7 | 984 | #define _DPLL_A_MD 0x0601c /* 965+ only */ |
585fb111 JB |
985 | /* |
986 | * UDI pixel divider, controlling how many pixels are stuffed into a packet. | |
987 | * | |
988 | * Value is pixels minus 1. Must be set to 1 pixel for SDVO. | |
989 | */ | |
990 | #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 | |
991 | #define DPLL_MD_UDI_DIVIDER_SHIFT 24 | |
992 | /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ | |
993 | #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 | |
994 | #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 | |
995 | /* | |
996 | * SDVO/UDI pixel multiplier. | |
997 | * | |
998 | * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus | |
999 | * clock rate is 10 times the DPLL clock. At low resolution/refresh rate | |
1000 | * modes, the bus rate would be below the limits, so SDVO allows for stuffing | |
1001 | * dummy bytes in the datastream at an increased clock rate, with both sides of | |
1002 | * the link knowing how many bytes are fill. | |
1003 | * | |
1004 | * So, for a mode with a dotclock of 65Mhz, we would want to double the clock | |
1005 | * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be | |
1006 | * set to 130Mhz, and the SDVO multiplier set to 2x in this register and | |
1007 | * through an SDVO command. | |
1008 | * | |
1009 | * This register field has values of multiplication factor minus 1, with | |
1010 | * a maximum multiplier of 5 for SDVO. | |
1011 | */ | |
1012 | #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 | |
1013 | #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 | |
1014 | /* | |
1015 | * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. | |
1016 | * This best be set to the default value (3) or the CRT won't work. No, | |
1017 | * I don't entirely understand what this does... | |
1018 | */ | |
1019 | #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f | |
1020 | #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 | |
9db4a9c7 JB |
1021 | #define _DPLL_B_MD 0x06020 /* 965+ only */ |
1022 | #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD) | |
25eb05fc | 1023 | |
9db4a9c7 JB |
1024 | #define _FPA0 0x06040 |
1025 | #define _FPA1 0x06044 | |
1026 | #define _FPB0 0x06048 | |
1027 | #define _FPB1 0x0604c | |
1028 | #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0) | |
1029 | #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1) | |
585fb111 | 1030 | #define FP_N_DIV_MASK 0x003f0000 |
f2b115e6 | 1031 | #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 |
585fb111 JB |
1032 | #define FP_N_DIV_SHIFT 16 |
1033 | #define FP_M1_DIV_MASK 0x00003f00 | |
1034 | #define FP_M1_DIV_SHIFT 8 | |
1035 | #define FP_M2_DIV_MASK 0x0000003f | |
f2b115e6 | 1036 | #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff |
585fb111 JB |
1037 | #define FP_M2_DIV_SHIFT 0 |
1038 | #define DPLL_TEST 0x606c | |
1039 | #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) | |
1040 | #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) | |
1041 | #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) | |
1042 | #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) | |
1043 | #define DPLLB_TEST_N_BYPASS (1 << 19) | |
1044 | #define DPLLB_TEST_M_BYPASS (1 << 18) | |
1045 | #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) | |
1046 | #define DPLLA_TEST_N_BYPASS (1 << 3) | |
1047 | #define DPLLA_TEST_M_BYPASS (1 << 2) | |
1048 | #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) | |
1049 | #define D_STATE 0x6104 | |
dc96e9b8 | 1050 | #define DSTATE_GFX_RESET_I830 (1<<6) |
652c393a JB |
1051 | #define DSTATE_PLL_D3_OFF (1<<3) |
1052 | #define DSTATE_GFX_CLOCK_GATING (1<<1) | |
1053 | #define DSTATE_DOT_CLOCK_GATING (1<<0) | |
1054 | #define DSPCLK_GATE_D 0x6200 | |
1055 | # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ | |
1056 | # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ | |
1057 | # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ | |
1058 | # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ | |
1059 | # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ | |
1060 | # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ | |
1061 | # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ | |
1062 | # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ | |
1063 | # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ | |
1064 | # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ | |
1065 | # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ | |
1066 | # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ | |
1067 | # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ | |
1068 | # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ | |
1069 | # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ | |
1070 | # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ | |
1071 | # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ | |
1072 | # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ | |
1073 | # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ | |
1074 | # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) | |
1075 | # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) | |
1076 | # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) | |
1077 | # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) | |
1078 | # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ | |
1079 | # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ | |
1080 | # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ | |
1081 | # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) | |
1082 | # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) | |
1083 | /** | |
1084 | * This bit must be set on the 830 to prevent hangs when turning off the | |
1085 | * overlay scaler. | |
1086 | */ | |
1087 | # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) | |
1088 | # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) | |
1089 | # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) | |
1090 | # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ | |
1091 | # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ | |
1092 | ||
1093 | #define RENCLK_GATE_D1 0x6204 | |
1094 | # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ | |
1095 | # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ | |
1096 | # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) | |
1097 | # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) | |
1098 | # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) | |
1099 | # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) | |
1100 | # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) | |
1101 | # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) | |
1102 | # define MAG_CLOCK_GATE_DISABLE (1 << 5) | |
1103 | /** This bit must be unset on 855,865 */ | |
1104 | # define MECI_CLOCK_GATE_DISABLE (1 << 4) | |
1105 | # define DCMP_CLOCK_GATE_DISABLE (1 << 3) | |
1106 | # define MEC_CLOCK_GATE_DISABLE (1 << 2) | |
1107 | # define MECO_CLOCK_GATE_DISABLE (1 << 1) | |
1108 | /** This bit must be set on 855,865. */ | |
1109 | # define SV_CLOCK_GATE_DISABLE (1 << 0) | |
1110 | # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) | |
1111 | # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) | |
1112 | # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) | |
1113 | # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) | |
1114 | # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) | |
1115 | # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) | |
1116 | # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) | |
1117 | # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) | |
1118 | # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) | |
1119 | # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) | |
1120 | # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) | |
1121 | # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) | |
1122 | # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) | |
1123 | # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) | |
1124 | # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) | |
1125 | # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) | |
1126 | # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) | |
1127 | ||
1128 | # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) | |
1129 | /** This bit must always be set on 965G/965GM */ | |
1130 | # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) | |
1131 | # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) | |
1132 | # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) | |
1133 | # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) | |
1134 | # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) | |
1135 | # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) | |
1136 | /** This bit must always be set on 965G */ | |
1137 | # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) | |
1138 | # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) | |
1139 | # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) | |
1140 | # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) | |
1141 | # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) | |
1142 | # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) | |
1143 | # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) | |
1144 | # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) | |
1145 | # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) | |
1146 | # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) | |
1147 | # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) | |
1148 | # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) | |
1149 | # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) | |
1150 | # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) | |
1151 | # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) | |
1152 | # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) | |
1153 | # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) | |
1154 | # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) | |
1155 | # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) | |
1156 | ||
1157 | #define RENCLK_GATE_D2 0x6208 | |
1158 | #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) | |
1159 | #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) | |
1160 | #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) | |
1161 | #define RAMCLK_GATE_D 0x6210 /* CRL only */ | |
1162 | #define DEUC 0x6214 /* CRL only */ | |
585fb111 | 1163 | |
d88b2270 | 1164 | #define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500) |
ceb04246 JB |
1165 | #define FW_CSPWRDWNEN (1<<15) |
1166 | ||
585fb111 JB |
1167 | /* |
1168 | * Palette regs | |
1169 | */ | |
1170 | ||
4b059985 VS |
1171 | #define _PALETTE_A (dev_priv->info->display_mmio_offset + 0xa000) |
1172 | #define _PALETTE_B (dev_priv->info->display_mmio_offset + 0xa800) | |
9db4a9c7 | 1173 | #define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B) |
585fb111 | 1174 | |
673a394b EA |
1175 | /* MCH MMIO space */ |
1176 | ||
1177 | /* | |
1178 | * MCHBAR mirror. | |
1179 | * | |
1180 | * This mirrors the MCHBAR MMIO space whose location is determined by | |
1181 | * device 0 function 0's pci config register 0x44 or 0x48 and matches it in | |
1182 | * every way. It is not accessible from the CP register read instructions. | |
1183 | * | |
1184 | */ | |
1185 | #define MCHBAR_MIRROR_BASE 0x10000 | |
1186 | ||
1398261a YL |
1187 | #define MCHBAR_MIRROR_BASE_SNB 0x140000 |
1188 | ||
673a394b EA |
1189 | /** 915-945 and GM965 MCH register controlling DRAM channel access */ |
1190 | #define DCC 0x10200 | |
1191 | #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) | |
1192 | #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) | |
1193 | #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) | |
1194 | #define DCC_ADDRESSING_MODE_MASK (3 << 0) | |
1195 | #define DCC_CHANNEL_XOR_DISABLE (1 << 10) | |
a7f014f2 | 1196 | #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) |
673a394b | 1197 | |
95534263 LP |
1198 | /** Pineview MCH register contains DDR3 setting */ |
1199 | #define CSHRDDR3CTL 0x101a8 | |
1200 | #define CSHRDDR3CTL_DDR3 (1 << 2) | |
1201 | ||
673a394b EA |
1202 | /** 965 MCH register controlling DRAM channel configuration */ |
1203 | #define C0DRB3 0x10206 | |
1204 | #define C1DRB3 0x10606 | |
1205 | ||
f691e2f4 DV |
1206 | /** snb MCH registers for reading the DRAM channel configuration */ |
1207 | #define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004) | |
1208 | #define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008) | |
1209 | #define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C) | |
1210 | #define MAD_DIMM_ECC_MASK (0x3 << 24) | |
1211 | #define MAD_DIMM_ECC_OFF (0x0 << 24) | |
1212 | #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) | |
1213 | #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) | |
1214 | #define MAD_DIMM_ECC_ON (0x3 << 24) | |
1215 | #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) | |
1216 | #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) | |
1217 | #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ | |
1218 | #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ | |
1219 | #define MAD_DIMM_B_DUAL_RANK (0x1 << 18) | |
1220 | #define MAD_DIMM_A_DUAL_RANK (0x1 << 17) | |
1221 | #define MAD_DIMM_A_SELECT (0x1 << 16) | |
1222 | /* DIMM sizes are in multiples of 256mb. */ | |
1223 | #define MAD_DIMM_B_SIZE_SHIFT 8 | |
1224 | #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) | |
1225 | #define MAD_DIMM_A_SIZE_SHIFT 0 | |
1226 | #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) | |
1227 | ||
1228 | ||
b11248df KP |
1229 | /* Clocking configuration register */ |
1230 | #define CLKCFG 0x10c00 | |
7662c8bd | 1231 | #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */ |
b11248df KP |
1232 | #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ |
1233 | #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ | |
1234 | #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */ | |
1235 | #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ | |
1236 | #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ | |
7662c8bd | 1237 | /* Note, below two are guess */ |
b11248df | 1238 | #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */ |
7662c8bd | 1239 | #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */ |
b11248df | 1240 | #define CLKCFG_FSB_MASK (7 << 0) |
7662c8bd SL |
1241 | #define CLKCFG_MEM_533 (1 << 4) |
1242 | #define CLKCFG_MEM_667 (2 << 4) | |
1243 | #define CLKCFG_MEM_800 (3 << 4) | |
1244 | #define CLKCFG_MEM_MASK (7 << 4) | |
1245 | ||
ea056c14 JB |
1246 | #define TSC1 0x11001 |
1247 | #define TSE (1<<0) | |
7648fa99 JB |
1248 | #define TR1 0x11006 |
1249 | #define TSFS 0x11020 | |
1250 | #define TSFS_SLOPE_MASK 0x0000ff00 | |
1251 | #define TSFS_SLOPE_SHIFT 8 | |
1252 | #define TSFS_INTR_MASK 0x000000ff | |
1253 | ||
f97108d1 JB |
1254 | #define CRSTANDVID 0x11100 |
1255 | #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ | |
1256 | #define PXVFREQ_PX_MASK 0x7f000000 | |
1257 | #define PXVFREQ_PX_SHIFT 24 | |
1258 | #define VIDFREQ_BASE 0x11110 | |
1259 | #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */ | |
1260 | #define VIDFREQ2 0x11114 | |
1261 | #define VIDFREQ3 0x11118 | |
1262 | #define VIDFREQ4 0x1111c | |
1263 | #define VIDFREQ_P0_MASK 0x1f000000 | |
1264 | #define VIDFREQ_P0_SHIFT 24 | |
1265 | #define VIDFREQ_P0_CSCLK_MASK 0x00f00000 | |
1266 | #define VIDFREQ_P0_CSCLK_SHIFT 20 | |
1267 | #define VIDFREQ_P0_CRCLK_MASK 0x000f0000 | |
1268 | #define VIDFREQ_P0_CRCLK_SHIFT 16 | |
1269 | #define VIDFREQ_P1_MASK 0x00001f00 | |
1270 | #define VIDFREQ_P1_SHIFT 8 | |
1271 | #define VIDFREQ_P1_CSCLK_MASK 0x000000f0 | |
1272 | #define VIDFREQ_P1_CSCLK_SHIFT 4 | |
1273 | #define VIDFREQ_P1_CRCLK_MASK 0x0000000f | |
1274 | #define INTTOEXT_BASE_ILK 0x11300 | |
1275 | #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */ | |
1276 | #define INTTOEXT_MAP3_SHIFT 24 | |
1277 | #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) | |
1278 | #define INTTOEXT_MAP2_SHIFT 16 | |
1279 | #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) | |
1280 | #define INTTOEXT_MAP1_SHIFT 8 | |
1281 | #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) | |
1282 | #define INTTOEXT_MAP0_SHIFT 0 | |
1283 | #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) | |
1284 | #define MEMSWCTL 0x11170 /* Ironlake only */ | |
1285 | #define MEMCTL_CMD_MASK 0xe000 | |
1286 | #define MEMCTL_CMD_SHIFT 13 | |
1287 | #define MEMCTL_CMD_RCLK_OFF 0 | |
1288 | #define MEMCTL_CMD_RCLK_ON 1 | |
1289 | #define MEMCTL_CMD_CHFREQ 2 | |
1290 | #define MEMCTL_CMD_CHVID 3 | |
1291 | #define MEMCTL_CMD_VMMOFF 4 | |
1292 | #define MEMCTL_CMD_VMMON 5 | |
1293 | #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears | |
1294 | when command complete */ | |
1295 | #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ | |
1296 | #define MEMCTL_FREQ_SHIFT 8 | |
1297 | #define MEMCTL_SFCAVM (1<<7) | |
1298 | #define MEMCTL_TGT_VID_MASK 0x007f | |
1299 | #define MEMIHYST 0x1117c | |
1300 | #define MEMINTREN 0x11180 /* 16 bits */ | |
1301 | #define MEMINT_RSEXIT_EN (1<<8) | |
1302 | #define MEMINT_CX_SUPR_EN (1<<7) | |
1303 | #define MEMINT_CONT_BUSY_EN (1<<6) | |
1304 | #define MEMINT_AVG_BUSY_EN (1<<5) | |
1305 | #define MEMINT_EVAL_CHG_EN (1<<4) | |
1306 | #define MEMINT_MON_IDLE_EN (1<<3) | |
1307 | #define MEMINT_UP_EVAL_EN (1<<2) | |
1308 | #define MEMINT_DOWN_EVAL_EN (1<<1) | |
1309 | #define MEMINT_SW_CMD_EN (1<<0) | |
1310 | #define MEMINTRSTR 0x11182 /* 16 bits */ | |
1311 | #define MEM_RSEXIT_MASK 0xc000 | |
1312 | #define MEM_RSEXIT_SHIFT 14 | |
1313 | #define MEM_CONT_BUSY_MASK 0x3000 | |
1314 | #define MEM_CONT_BUSY_SHIFT 12 | |
1315 | #define MEM_AVG_BUSY_MASK 0x0c00 | |
1316 | #define MEM_AVG_BUSY_SHIFT 10 | |
1317 | #define MEM_EVAL_CHG_MASK 0x0300 | |
1318 | #define MEM_EVAL_BUSY_SHIFT 8 | |
1319 | #define MEM_MON_IDLE_MASK 0x00c0 | |
1320 | #define MEM_MON_IDLE_SHIFT 6 | |
1321 | #define MEM_UP_EVAL_MASK 0x0030 | |
1322 | #define MEM_UP_EVAL_SHIFT 4 | |
1323 | #define MEM_DOWN_EVAL_MASK 0x000c | |
1324 | #define MEM_DOWN_EVAL_SHIFT 2 | |
1325 | #define MEM_SW_CMD_MASK 0x0003 | |
1326 | #define MEM_INT_STEER_GFX 0 | |
1327 | #define MEM_INT_STEER_CMR 1 | |
1328 | #define MEM_INT_STEER_SMI 2 | |
1329 | #define MEM_INT_STEER_SCI 3 | |
1330 | #define MEMINTRSTS 0x11184 | |
1331 | #define MEMINT_RSEXIT (1<<7) | |
1332 | #define MEMINT_CONT_BUSY (1<<6) | |
1333 | #define MEMINT_AVG_BUSY (1<<5) | |
1334 | #define MEMINT_EVAL_CHG (1<<4) | |
1335 | #define MEMINT_MON_IDLE (1<<3) | |
1336 | #define MEMINT_UP_EVAL (1<<2) | |
1337 | #define MEMINT_DOWN_EVAL (1<<1) | |
1338 | #define MEMINT_SW_CMD (1<<0) | |
1339 | #define MEMMODECTL 0x11190 | |
1340 | #define MEMMODE_BOOST_EN (1<<31) | |
1341 | #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ | |
1342 | #define MEMMODE_BOOST_FREQ_SHIFT 24 | |
1343 | #define MEMMODE_IDLE_MODE_MASK 0x00030000 | |
1344 | #define MEMMODE_IDLE_MODE_SHIFT 16 | |
1345 | #define MEMMODE_IDLE_MODE_EVAL 0 | |
1346 | #define MEMMODE_IDLE_MODE_CONT 1 | |
1347 | #define MEMMODE_HWIDLE_EN (1<<15) | |
1348 | #define MEMMODE_SWMODE_EN (1<<14) | |
1349 | #define MEMMODE_RCLK_GATE (1<<13) | |
1350 | #define MEMMODE_HW_UPDATE (1<<12) | |
1351 | #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ | |
1352 | #define MEMMODE_FSTART_SHIFT 8 | |
1353 | #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ | |
1354 | #define MEMMODE_FMAX_SHIFT 4 | |
1355 | #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ | |
1356 | #define RCBMAXAVG 0x1119c | |
1357 | #define MEMSWCTL2 0x1119e /* Cantiga only */ | |
1358 | #define SWMEMCMD_RENDER_OFF (0 << 13) | |
1359 | #define SWMEMCMD_RENDER_ON (1 << 13) | |
1360 | #define SWMEMCMD_SWFREQ (2 << 13) | |
1361 | #define SWMEMCMD_TARVID (3 << 13) | |
1362 | #define SWMEMCMD_VRM_OFF (4 << 13) | |
1363 | #define SWMEMCMD_VRM_ON (5 << 13) | |
1364 | #define CMDSTS (1<<12) | |
1365 | #define SFCAVM (1<<11) | |
1366 | #define SWFREQ_MASK 0x0380 /* P0-7 */ | |
1367 | #define SWFREQ_SHIFT 7 | |
1368 | #define TARVID_MASK 0x001f | |
1369 | #define MEMSTAT_CTG 0x111a0 | |
1370 | #define RCBMINAVG 0x111a0 | |
1371 | #define RCUPEI 0x111b0 | |
1372 | #define RCDNEI 0x111b4 | |
88271da3 JB |
1373 | #define RSTDBYCTL 0x111b8 |
1374 | #define RS1EN (1<<31) | |
1375 | #define RS2EN (1<<30) | |
1376 | #define RS3EN (1<<29) | |
1377 | #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */ | |
1378 | #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */ | |
1379 | #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */ | |
1380 | #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */ | |
1381 | #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */ | |
1382 | #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */ | |
1383 | #define RSX_STATUS_MASK (7<<20) | |
1384 | #define RSX_STATUS_ON (0<<20) | |
1385 | #define RSX_STATUS_RC1 (1<<20) | |
1386 | #define RSX_STATUS_RC1E (2<<20) | |
1387 | #define RSX_STATUS_RS1 (3<<20) | |
1388 | #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */ | |
1389 | #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */ | |
1390 | #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */ | |
1391 | #define RSX_STATUS_RSVD2 (7<<20) | |
1392 | #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */ | |
1393 | #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */ | |
1394 | #define JRSC (1<<17) /* rsx coupled to cpu c-state */ | |
1395 | #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */ | |
1396 | #define RS1CONTSAV_MASK (3<<14) | |
1397 | #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */ | |
1398 | #define RS1CONTSAV_RSVD (1<<14) | |
1399 | #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */ | |
1400 | #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */ | |
1401 | #define NORMSLEXLAT_MASK (3<<12) | |
1402 | #define SLOW_RS123 (0<<12) | |
1403 | #define SLOW_RS23 (1<<12) | |
1404 | #define SLOW_RS3 (2<<12) | |
1405 | #define NORMAL_RS123 (3<<12) | |
1406 | #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */ | |
1407 | #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ | |
1408 | #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */ | |
1409 | #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */ | |
1410 | #define RS_CSTATE_MASK (3<<4) | |
1411 | #define RS_CSTATE_C367_RS1 (0<<4) | |
1412 | #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4) | |
1413 | #define RS_CSTATE_RSVD (2<<4) | |
1414 | #define RS_CSTATE_C367_RS2 (3<<4) | |
1415 | #define REDSAVES (1<<3) /* no context save if was idle during rs0 */ | |
1416 | #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */ | |
f97108d1 JB |
1417 | #define VIDCTL 0x111c0 |
1418 | #define VIDSTS 0x111c8 | |
1419 | #define VIDSTART 0x111cc /* 8 bits */ | |
1420 | #define MEMSTAT_ILK 0x111f8 | |
1421 | #define MEMSTAT_VID_MASK 0x7f00 | |
1422 | #define MEMSTAT_VID_SHIFT 8 | |
1423 | #define MEMSTAT_PSTATE_MASK 0x00f8 | |
1424 | #define MEMSTAT_PSTATE_SHIFT 3 | |
1425 | #define MEMSTAT_MON_ACTV (1<<2) | |
1426 | #define MEMSTAT_SRC_CTL_MASK 0x0003 | |
1427 | #define MEMSTAT_SRC_CTL_CORE 0 | |
1428 | #define MEMSTAT_SRC_CTL_TRB 1 | |
1429 | #define MEMSTAT_SRC_CTL_THM 2 | |
1430 | #define MEMSTAT_SRC_CTL_STDBY 3 | |
1431 | #define RCPREVBSYTUPAVG 0x113b8 | |
1432 | #define RCPREVBSYTDNAVG 0x113bc | |
ea056c14 JB |
1433 | #define PMMISC 0x11214 |
1434 | #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */ | |
7648fa99 JB |
1435 | #define SDEW 0x1124c |
1436 | #define CSIEW0 0x11250 | |
1437 | #define CSIEW1 0x11254 | |
1438 | #define CSIEW2 0x11258 | |
1439 | #define PEW 0x1125c | |
1440 | #define DEW 0x11270 | |
1441 | #define MCHAFE 0x112c0 | |
1442 | #define CSIEC 0x112e0 | |
1443 | #define DMIEC 0x112e4 | |
1444 | #define DDREC 0x112e8 | |
1445 | #define PEG0EC 0x112ec | |
1446 | #define PEG1EC 0x112f0 | |
1447 | #define GFXEC 0x112f4 | |
1448 | #define RPPREVBSYTUPAVG 0x113b8 | |
1449 | #define RPPREVBSYTDNAVG 0x113bc | |
1450 | #define ECR 0x11600 | |
1451 | #define ECR_GPFE (1<<31) | |
1452 | #define ECR_IMONE (1<<30) | |
1453 | #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ | |
1454 | #define OGW0 0x11608 | |
1455 | #define OGW1 0x1160c | |
1456 | #define EG0 0x11610 | |
1457 | #define EG1 0x11614 | |
1458 | #define EG2 0x11618 | |
1459 | #define EG3 0x1161c | |
1460 | #define EG4 0x11620 | |
1461 | #define EG5 0x11624 | |
1462 | #define EG6 0x11628 | |
1463 | #define EG7 0x1162c | |
1464 | #define PXW 0x11664 | |
1465 | #define PXWL 0x11680 | |
1466 | #define LCFUSE02 0x116c0 | |
1467 | #define LCFUSE_HIV_MASK 0x000000ff | |
1468 | #define CSIPLL0 0x12c10 | |
1469 | #define DDRMPLL1 0X12c20 | |
7d57382e EA |
1470 | #define PEG_BAND_GAP_DATA 0x14d68 |
1471 | ||
c4de7b0f CW |
1472 | #define GEN6_GT_THREAD_STATUS_REG 0x13805c |
1473 | #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7 | |
1474 | #define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16)) | |
1475 | ||
3b8d8d91 JB |
1476 | #define GEN6_GT_PERF_STATUS 0x145948 |
1477 | #define GEN6_RP_STATE_LIMITS 0x145994 | |
1478 | #define GEN6_RP_STATE_CAP 0x145998 | |
1479 | ||
aa40d6bb ZN |
1480 | /* |
1481 | * Logical Context regs | |
1482 | */ | |
1483 | #define CCID 0x2180 | |
1484 | #define CCID_EN (1<<0) | |
fe1cc68f BW |
1485 | #define CXT_SIZE 0x21a0 |
1486 | #define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f) | |
1487 | #define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f) | |
1488 | #define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f) | |
1489 | #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f) | |
1490 | #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f) | |
1491 | #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_POWER_SIZE(cxt_reg) + \ | |
1492 | GEN6_CXT_RING_SIZE(cxt_reg) + \ | |
1493 | GEN6_CXT_RENDER_SIZE(cxt_reg) + \ | |
1494 | GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \ | |
1495 | GEN6_CXT_PIPELINE_SIZE(cxt_reg)) | |
4f91dd6f | 1496 | #define GEN7_CXT_SIZE 0x21a8 |
6a4ea124 BW |
1497 | #define GEN7_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 25) & 0x7f) |
1498 | #define GEN7_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 22) & 0x7) | |
4f91dd6f BW |
1499 | #define GEN7_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f) |
1500 | #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f) | |
1501 | #define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7) | |
1502 | #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f) | |
6a4ea124 BW |
1503 | #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_POWER_SIZE(ctx_reg) + \ |
1504 | GEN7_CXT_RING_SIZE(ctx_reg) + \ | |
1505 | GEN7_CXT_RENDER_SIZE(ctx_reg) + \ | |
4f91dd6f BW |
1506 | GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \ |
1507 | GEN7_CXT_GT1_SIZE(ctx_reg) + \ | |
1508 | GEN7_CXT_VFSTATE_SIZE(ctx_reg)) | |
2e4291e0 BW |
1509 | #define HSW_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 26) & 0x3f) |
1510 | #define HSW_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 23) & 0x7) | |
1511 | #define HSW_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 15) & 0xff) | |
1512 | #define HSW_CXT_TOTAL_SIZE(ctx_reg) (HSW_CXT_POWER_SIZE(ctx_reg) + \ | |
1513 | HSW_CXT_RING_SIZE(ctx_reg) + \ | |
1514 | HSW_CXT_RENDER_SIZE(ctx_reg) + \ | |
1515 | GEN7_CXT_VFSTATE_SIZE(ctx_reg)) | |
1516 | ||
fe1cc68f | 1517 | |
585fb111 JB |
1518 | /* |
1519 | * Overlay regs | |
1520 | */ | |
1521 | ||
1522 | #define OVADD 0x30000 | |
1523 | #define DOVSTA 0x30008 | |
1524 | #define OC_BUF (0x3<<20) | |
1525 | #define OGAMC5 0x30010 | |
1526 | #define OGAMC4 0x30014 | |
1527 | #define OGAMC3 0x30018 | |
1528 | #define OGAMC2 0x3001c | |
1529 | #define OGAMC1 0x30020 | |
1530 | #define OGAMC0 0x30024 | |
1531 | ||
1532 | /* | |
1533 | * Display engine regs | |
1534 | */ | |
1535 | ||
1536 | /* Pipe A timing regs */ | |
4e8e7eb7 VS |
1537 | #define _HTOTAL_A (dev_priv->info->display_mmio_offset + 0x60000) |
1538 | #define _HBLANK_A (dev_priv->info->display_mmio_offset + 0x60004) | |
1539 | #define _HSYNC_A (dev_priv->info->display_mmio_offset + 0x60008) | |
1540 | #define _VTOTAL_A (dev_priv->info->display_mmio_offset + 0x6000c) | |
1541 | #define _VBLANK_A (dev_priv->info->display_mmio_offset + 0x60010) | |
1542 | #define _VSYNC_A (dev_priv->info->display_mmio_offset + 0x60014) | |
1543 | #define _PIPEASRC (dev_priv->info->display_mmio_offset + 0x6001c) | |
1544 | #define _BCLRPAT_A (dev_priv->info->display_mmio_offset + 0x60020) | |
1545 | #define _VSYNCSHIFT_A (dev_priv->info->display_mmio_offset + 0x60028) | |
585fb111 JB |
1546 | |
1547 | /* Pipe B timing regs */ | |
4e8e7eb7 VS |
1548 | #define _HTOTAL_B (dev_priv->info->display_mmio_offset + 0x61000) |
1549 | #define _HBLANK_B (dev_priv->info->display_mmio_offset + 0x61004) | |
1550 | #define _HSYNC_B (dev_priv->info->display_mmio_offset + 0x61008) | |
1551 | #define _VTOTAL_B (dev_priv->info->display_mmio_offset + 0x6100c) | |
1552 | #define _VBLANK_B (dev_priv->info->display_mmio_offset + 0x61010) | |
1553 | #define _VSYNC_B (dev_priv->info->display_mmio_offset + 0x61014) | |
1554 | #define _PIPEBSRC (dev_priv->info->display_mmio_offset + 0x6101c) | |
1555 | #define _BCLRPAT_B (dev_priv->info->display_mmio_offset + 0x61020) | |
1556 | #define _VSYNCSHIFT_B (dev_priv->info->display_mmio_offset + 0x61028) | |
0529a0d9 | 1557 | |
9db4a9c7 | 1558 | |
fe2b8f9d PZ |
1559 | #define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B) |
1560 | #define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B) | |
1561 | #define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B) | |
1562 | #define VTOTAL(trans) _TRANSCODER(trans, _VTOTAL_A, _VTOTAL_B) | |
1563 | #define VBLANK(trans) _TRANSCODER(trans, _VBLANK_A, _VBLANK_B) | |
1564 | #define VSYNC(trans) _TRANSCODER(trans, _VSYNC_A, _VSYNC_B) | |
9db4a9c7 | 1565 | #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B) |
fe2b8f9d | 1566 | #define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B) |
5eddb70b | 1567 | |
585fb111 JB |
1568 | /* VGA port control */ |
1569 | #define ADPA 0x61100 | |
ebc0fd88 | 1570 | #define PCH_ADPA 0xe1100 |
540a8950 | 1571 | #define VLV_ADPA (VLV_DISPLAY_BASE + ADPA) |
ebc0fd88 | 1572 | |
585fb111 JB |
1573 | #define ADPA_DAC_ENABLE (1<<31) |
1574 | #define ADPA_DAC_DISABLE 0 | |
1575 | #define ADPA_PIPE_SELECT_MASK (1<<30) | |
1576 | #define ADPA_PIPE_A_SELECT 0 | |
1577 | #define ADPA_PIPE_B_SELECT (1<<30) | |
1519b995 | 1578 | #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30) |
ebc0fd88 DV |
1579 | /* CPT uses bits 29:30 for pch transcoder select */ |
1580 | #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ | |
1581 | #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) | |
1582 | #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) | |
1583 | #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) | |
1584 | #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) | |
1585 | #define ADPA_CRT_HOTPLUG_ENABLE (1<<23) | |
1586 | #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) | |
1587 | #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) | |
1588 | #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) | |
1589 | #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) | |
1590 | #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) | |
1591 | #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) | |
1592 | #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) | |
1593 | #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) | |
1594 | #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) | |
1595 | #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) | |
1596 | #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) | |
1597 | #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) | |
1598 | #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) | |
585fb111 JB |
1599 | #define ADPA_USE_VGA_HVPOLARITY (1<<15) |
1600 | #define ADPA_SETS_HVPOLARITY 0 | |
1601 | #define ADPA_VSYNC_CNTL_DISABLE (1<<11) | |
1602 | #define ADPA_VSYNC_CNTL_ENABLE 0 | |
1603 | #define ADPA_HSYNC_CNTL_DISABLE (1<<10) | |
1604 | #define ADPA_HSYNC_CNTL_ENABLE 0 | |
1605 | #define ADPA_VSYNC_ACTIVE_HIGH (1<<4) | |
1606 | #define ADPA_VSYNC_ACTIVE_LOW 0 | |
1607 | #define ADPA_HSYNC_ACTIVE_HIGH (1<<3) | |
1608 | #define ADPA_HSYNC_ACTIVE_LOW 0 | |
1609 | #define ADPA_DPMS_MASK (~(3<<10)) | |
1610 | #define ADPA_DPMS_ON (0<<10) | |
1611 | #define ADPA_DPMS_SUSPEND (1<<10) | |
1612 | #define ADPA_DPMS_STANDBY (2<<10) | |
1613 | #define ADPA_DPMS_OFF (3<<10) | |
1614 | ||
939fe4d7 | 1615 | |
585fb111 | 1616 | /* Hotplug control (945+ only) */ |
67d62c57 | 1617 | #define PORT_HOTPLUG_EN (dev_priv->info->display_mmio_offset + 0x61110) |
7d57382e | 1618 | #define HDMIB_HOTPLUG_INT_EN (1 << 29) |
040d87f1 | 1619 | #define DPB_HOTPLUG_INT_EN (1 << 29) |
7d57382e | 1620 | #define HDMIC_HOTPLUG_INT_EN (1 << 28) |
040d87f1 | 1621 | #define DPC_HOTPLUG_INT_EN (1 << 28) |
7d57382e | 1622 | #define HDMID_HOTPLUG_INT_EN (1 << 27) |
040d87f1 | 1623 | #define DPD_HOTPLUG_INT_EN (1 << 27) |
585fb111 JB |
1624 | #define SDVOB_HOTPLUG_INT_EN (1 << 26) |
1625 | #define SDVOC_HOTPLUG_INT_EN (1 << 25) | |
1626 | #define TV_HOTPLUG_INT_EN (1 << 18) | |
1627 | #define CRT_HOTPLUG_INT_EN (1 << 9) | |
1628 | #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) | |
771cb081 ZY |
1629 | #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) |
1630 | /* must use period 64 on GM45 according to docs */ | |
1631 | #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) | |
1632 | #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) | |
1633 | #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) | |
1634 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) | |
1635 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) | |
1636 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) | |
1637 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) | |
1638 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) | |
1639 | #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) | |
1640 | #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) | |
1641 | #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) | |
1642 | #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) | |
585fb111 | 1643 | |
67d62c57 | 1644 | #define PORT_HOTPLUG_STAT (dev_priv->info->display_mmio_offset + 0x61114) |
10f76a38 CW |
1645 | /* HDMI/DP bits are gen4+ */ |
1646 | #define DPB_HOTPLUG_LIVE_STATUS (1 << 29) | |
1647 | #define DPC_HOTPLUG_LIVE_STATUS (1 << 28) | |
1648 | #define DPD_HOTPLUG_LIVE_STATUS (1 << 27) | |
1649 | #define DPD_HOTPLUG_INT_STATUS (3 << 21) | |
1650 | #define DPC_HOTPLUG_INT_STATUS (3 << 19) | |
1651 | #define DPB_HOTPLUG_INT_STATUS (3 << 17) | |
1652 | /* HDMI bits are shared with the DP bits */ | |
1653 | #define HDMIB_HOTPLUG_LIVE_STATUS (1 << 29) | |
1654 | #define HDMIC_HOTPLUG_LIVE_STATUS (1 << 28) | |
1655 | #define HDMID_HOTPLUG_LIVE_STATUS (1 << 27) | |
1656 | #define HDMID_HOTPLUG_INT_STATUS (3 << 21) | |
1657 | #define HDMIC_HOTPLUG_INT_STATUS (3 << 19) | |
1658 | #define HDMIB_HOTPLUG_INT_STATUS (3 << 17) | |
084b612e | 1659 | /* CRT/TV common between gen3+ */ |
585fb111 JB |
1660 | #define CRT_HOTPLUG_INT_STATUS (1 << 11) |
1661 | #define TV_HOTPLUG_INT_STATUS (1 << 10) | |
1662 | #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) | |
1663 | #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) | |
1664 | #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) | |
1665 | #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) | |
084b612e CW |
1666 | /* SDVO is different across gen3/4 */ |
1667 | #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) | |
1668 | #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) | |
1669 | #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) | |
1670 | #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) | |
1671 | #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) | |
1672 | #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) | |
585fb111 JB |
1673 | |
1674 | /* SDVO port control */ | |
1675 | #define SDVOB 0x61140 | |
1676 | #define SDVOC 0x61160 | |
1677 | #define SDVO_ENABLE (1 << 31) | |
1678 | #define SDVO_PIPE_B_SELECT (1 << 30) | |
1679 | #define SDVO_STALL_SELECT (1 << 29) | |
1680 | #define SDVO_INTERRUPT_ENABLE (1 << 26) | |
1681 | /** | |
1682 | * 915G/GM SDVO pixel multiplier. | |
1683 | * | |
1684 | * Programmed value is multiplier - 1, up to 5x. | |
1685 | * | |
1686 | * \sa DPLL_MD_UDI_MULTIPLIER_MASK | |
1687 | */ | |
1688 | #define SDVO_PORT_MULTIPLY_MASK (7 << 23) | |
1689 | #define SDVO_PORT_MULTIPLY_SHIFT 23 | |
1690 | #define SDVO_PHASE_SELECT_MASK (15 << 19) | |
1691 | #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) | |
1692 | #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) | |
1693 | #define SDVOC_GANG_MODE (1 << 16) | |
7d57382e EA |
1694 | #define SDVO_ENCODING_SDVO (0x0 << 10) |
1695 | #define SDVO_ENCODING_HDMI (0x2 << 10) | |
1696 | /** Requird for HDMI operation */ | |
1697 | #define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9) | |
e953fd7b | 1698 | #define SDVO_COLOR_RANGE_16_235 (1 << 8) |
585fb111 | 1699 | #define SDVO_BORDER_ENABLE (1 << 7) |
7d57382e EA |
1700 | #define SDVO_AUDIO_ENABLE (1 << 6) |
1701 | /** New with 965, default is to be set */ | |
1702 | #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) | |
1703 | /** New with 965, default is to be set */ | |
1704 | #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) | |
585fb111 JB |
1705 | #define SDVOB_PCIE_CONCURRENCY (1 << 3) |
1706 | #define SDVO_DETECTED (1 << 2) | |
1707 | /* Bits to be preserved when writing */ | |
1708 | #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26)) | |
1709 | #define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26)) | |
1710 | ||
1711 | /* DVO port control */ | |
1712 | #define DVOA 0x61120 | |
1713 | #define DVOB 0x61140 | |
1714 | #define DVOC 0x61160 | |
1715 | #define DVO_ENABLE (1 << 31) | |
1716 | #define DVO_PIPE_B_SELECT (1 << 30) | |
1717 | #define DVO_PIPE_STALL_UNUSED (0 << 28) | |
1718 | #define DVO_PIPE_STALL (1 << 28) | |
1719 | #define DVO_PIPE_STALL_TV (2 << 28) | |
1720 | #define DVO_PIPE_STALL_MASK (3 << 28) | |
1721 | #define DVO_USE_VGA_SYNC (1 << 15) | |
1722 | #define DVO_DATA_ORDER_I740 (0 << 14) | |
1723 | #define DVO_DATA_ORDER_FP (1 << 14) | |
1724 | #define DVO_VSYNC_DISABLE (1 << 11) | |
1725 | #define DVO_HSYNC_DISABLE (1 << 10) | |
1726 | #define DVO_VSYNC_TRISTATE (1 << 9) | |
1727 | #define DVO_HSYNC_TRISTATE (1 << 8) | |
1728 | #define DVO_BORDER_ENABLE (1 << 7) | |
1729 | #define DVO_DATA_ORDER_GBRG (1 << 6) | |
1730 | #define DVO_DATA_ORDER_RGGB (0 << 6) | |
1731 | #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) | |
1732 | #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) | |
1733 | #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) | |
1734 | #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) | |
1735 | #define DVO_BLANK_ACTIVE_HIGH (1 << 2) | |
1736 | #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ | |
1737 | #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ | |
1738 | #define DVO_PRESERVE_MASK (0x7<<24) | |
1739 | #define DVOA_SRCDIM 0x61124 | |
1740 | #define DVOB_SRCDIM 0x61144 | |
1741 | #define DVOC_SRCDIM 0x61164 | |
1742 | #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 | |
1743 | #define DVO_SRCDIM_VERTICAL_SHIFT 0 | |
1744 | ||
1745 | /* LVDS port control */ | |
1746 | #define LVDS 0x61180 | |
1747 | /* | |
1748 | * Enables the LVDS port. This bit must be set before DPLLs are enabled, as | |
1749 | * the DPLL semantics change when the LVDS is assigned to that pipe. | |
1750 | */ | |
1751 | #define LVDS_PORT_EN (1 << 31) | |
1752 | /* Selects pipe B for LVDS data. Must be set on pre-965. */ | |
1753 | #define LVDS_PIPEB_SELECT (1 << 30) | |
47a05eca | 1754 | #define LVDS_PIPE_MASK (1 << 30) |
1519b995 | 1755 | #define LVDS_PIPE(pipe) ((pipe) << 30) |
898822ce ZY |
1756 | /* LVDS dithering flag on 965/g4x platform */ |
1757 | #define LVDS_ENABLE_DITHER (1 << 25) | |
aa9b500d BF |
1758 | /* LVDS sync polarity flags. Set to invert (i.e. negative) */ |
1759 | #define LVDS_VSYNC_POLARITY (1 << 21) | |
1760 | #define LVDS_HSYNC_POLARITY (1 << 20) | |
1761 | ||
a3e17eb8 ZY |
1762 | /* Enable border for unscaled (or aspect-scaled) display */ |
1763 | #define LVDS_BORDER_ENABLE (1 << 15) | |
585fb111 JB |
1764 | /* |
1765 | * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per | |
1766 | * pixel. | |
1767 | */ | |
1768 | #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) | |
1769 | #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) | |
1770 | #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) | |
1771 | /* | |
1772 | * Controls the A3 data pair, which contains the additional LSBs for 24 bit | |
1773 | * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be | |
1774 | * on. | |
1775 | */ | |
1776 | #define LVDS_A3_POWER_MASK (3 << 6) | |
1777 | #define LVDS_A3_POWER_DOWN (0 << 6) | |
1778 | #define LVDS_A3_POWER_UP (3 << 6) | |
1779 | /* | |
1780 | * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP | |
1781 | * is set. | |
1782 | */ | |
1783 | #define LVDS_CLKB_POWER_MASK (3 << 4) | |
1784 | #define LVDS_CLKB_POWER_DOWN (0 << 4) | |
1785 | #define LVDS_CLKB_POWER_UP (3 << 4) | |
1786 | /* | |
1787 | * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 | |
1788 | * setting for whether we are in dual-channel mode. The B3 pair will | |
1789 | * additionally only be powered up when LVDS_A3_POWER_UP is set. | |
1790 | */ | |
1791 | #define LVDS_B0B3_POWER_MASK (3 << 2) | |
1792 | #define LVDS_B0B3_POWER_DOWN (0 << 2) | |
1793 | #define LVDS_B0B3_POWER_UP (3 << 2) | |
1794 | ||
3c17fe4b DH |
1795 | /* Video Data Island Packet control */ |
1796 | #define VIDEO_DIP_DATA 0x61178 | |
adf00b26 PZ |
1797 | /* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC |
1798 | * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte | |
1799 | * of the infoframe structure specified by CEA-861. */ | |
1800 | #define VIDEO_DIP_DATA_SIZE 32 | |
3c17fe4b | 1801 | #define VIDEO_DIP_CTL 0x61170 |
2da8af54 | 1802 | /* Pre HSW: */ |
3c17fe4b DH |
1803 | #define VIDEO_DIP_ENABLE (1 << 31) |
1804 | #define VIDEO_DIP_PORT_B (1 << 29) | |
1805 | #define VIDEO_DIP_PORT_C (2 << 29) | |
4e89ee17 | 1806 | #define VIDEO_DIP_PORT_D (3 << 29) |
3e6e6395 | 1807 | #define VIDEO_DIP_PORT_MASK (3 << 29) |
0dd87d20 | 1808 | #define VIDEO_DIP_ENABLE_GCP (1 << 25) |
3c17fe4b DH |
1809 | #define VIDEO_DIP_ENABLE_AVI (1 << 21) |
1810 | #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) | |
0dd87d20 | 1811 | #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) |
3c17fe4b DH |
1812 | #define VIDEO_DIP_ENABLE_SPD (8 << 21) |
1813 | #define VIDEO_DIP_SELECT_AVI (0 << 19) | |
1814 | #define VIDEO_DIP_SELECT_VENDOR (1 << 19) | |
1815 | #define VIDEO_DIP_SELECT_SPD (3 << 19) | |
45187ace | 1816 | #define VIDEO_DIP_SELECT_MASK (3 << 19) |
3c17fe4b DH |
1817 | #define VIDEO_DIP_FREQ_ONCE (0 << 16) |
1818 | #define VIDEO_DIP_FREQ_VSYNC (1 << 16) | |
1819 | #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) | |
60c5ea2d | 1820 | #define VIDEO_DIP_FREQ_MASK (3 << 16) |
2da8af54 | 1821 | /* HSW and later: */ |
0dd87d20 PZ |
1822 | #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) |
1823 | #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) | |
2da8af54 | 1824 | #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) |
0dd87d20 PZ |
1825 | #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) |
1826 | #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) | |
2da8af54 | 1827 | #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) |
3c17fe4b | 1828 | |
585fb111 JB |
1829 | /* Panel power sequencing */ |
1830 | #define PP_STATUS 0x61200 | |
1831 | #define PP_ON (1 << 31) | |
1832 | /* | |
1833 | * Indicates that all dependencies of the panel are on: | |
1834 | * | |
1835 | * - PLL enabled | |
1836 | * - pipe enabled | |
1837 | * - LVDS/DVOB/DVOC on | |
1838 | */ | |
1839 | #define PP_READY (1 << 30) | |
1840 | #define PP_SEQUENCE_NONE (0 << 28) | |
99ea7127 KP |
1841 | #define PP_SEQUENCE_POWER_UP (1 << 28) |
1842 | #define PP_SEQUENCE_POWER_DOWN (2 << 28) | |
1843 | #define PP_SEQUENCE_MASK (3 << 28) | |
1844 | #define PP_SEQUENCE_SHIFT 28 | |
01cb9ea6 | 1845 | #define PP_CYCLE_DELAY_ACTIVE (1 << 27) |
01cb9ea6 | 1846 | #define PP_SEQUENCE_STATE_MASK 0x0000000f |
99ea7127 KP |
1847 | #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0) |
1848 | #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0) | |
1849 | #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0) | |
1850 | #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0) | |
1851 | #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0) | |
1852 | #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0) | |
1853 | #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0) | |
1854 | #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0) | |
1855 | #define PP_SEQUENCE_STATE_RESET (0xf << 0) | |
585fb111 JB |
1856 | #define PP_CONTROL 0x61204 |
1857 | #define POWER_TARGET_ON (1 << 0) | |
1858 | #define PP_ON_DELAYS 0x61208 | |
1859 | #define PP_OFF_DELAYS 0x6120c | |
1860 | #define PP_DIVISOR 0x61210 | |
1861 | ||
1862 | /* Panel fitting */ | |
7e470abf | 1863 | #define PFIT_CONTROL (dev_priv->info->display_mmio_offset + 0x61230) |
585fb111 JB |
1864 | #define PFIT_ENABLE (1 << 31) |
1865 | #define PFIT_PIPE_MASK (3 << 29) | |
1866 | #define PFIT_PIPE_SHIFT 29 | |
1867 | #define VERT_INTERP_DISABLE (0 << 10) | |
1868 | #define VERT_INTERP_BILINEAR (1 << 10) | |
1869 | #define VERT_INTERP_MASK (3 << 10) | |
1870 | #define VERT_AUTO_SCALE (1 << 9) | |
1871 | #define HORIZ_INTERP_DISABLE (0 << 6) | |
1872 | #define HORIZ_INTERP_BILINEAR (1 << 6) | |
1873 | #define HORIZ_INTERP_MASK (3 << 6) | |
1874 | #define HORIZ_AUTO_SCALE (1 << 5) | |
1875 | #define PANEL_8TO6_DITHER_ENABLE (1 << 3) | |
3fbe18d6 ZY |
1876 | #define PFIT_FILTER_FUZZY (0 << 24) |
1877 | #define PFIT_SCALING_AUTO (0 << 26) | |
1878 | #define PFIT_SCALING_PROGRAMMED (1 << 26) | |
1879 | #define PFIT_SCALING_PILLAR (2 << 26) | |
1880 | #define PFIT_SCALING_LETTER (3 << 26) | |
7e470abf | 1881 | #define PFIT_PGM_RATIOS (dev_priv->info->display_mmio_offset + 0x61234) |
3fbe18d6 ZY |
1882 | /* Pre-965 */ |
1883 | #define PFIT_VERT_SCALE_SHIFT 20 | |
1884 | #define PFIT_VERT_SCALE_MASK 0xfff00000 | |
1885 | #define PFIT_HORIZ_SCALE_SHIFT 4 | |
1886 | #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 | |
1887 | /* 965+ */ | |
1888 | #define PFIT_VERT_SCALE_SHIFT_965 16 | |
1889 | #define PFIT_VERT_SCALE_MASK_965 0x1fff0000 | |
1890 | #define PFIT_HORIZ_SCALE_SHIFT_965 0 | |
1891 | #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff | |
1892 | ||
7e470abf | 1893 | #define PFIT_AUTO_RATIOS (dev_priv->info->display_mmio_offset + 0x61238) |
585fb111 JB |
1894 | |
1895 | /* Backlight control */ | |
585fb111 | 1896 | #define BLC_PWM_CTL2 0x61250 /* 965+ only */ |
7cf41601 DV |
1897 | #define BLM_PWM_ENABLE (1 << 31) |
1898 | #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ | |
1899 | #define BLM_PIPE_SELECT (1 << 29) | |
1900 | #define BLM_PIPE_SELECT_IVB (3 << 29) | |
1901 | #define BLM_PIPE_A (0 << 29) | |
1902 | #define BLM_PIPE_B (1 << 29) | |
1903 | #define BLM_PIPE_C (2 << 29) /* ivb + */ | |
1904 | #define BLM_PIPE(pipe) ((pipe) << 29) | |
1905 | #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */ | |
1906 | #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26) | |
1907 | #define BLM_PHASE_IN_ENABLE (1 << 25) | |
1908 | #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24) | |
1909 | #define BLM_PHASE_IN_TIME_BASE_SHIFT (16) | |
1910 | #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16) | |
1911 | #define BLM_PHASE_IN_COUNT_SHIFT (8) | |
1912 | #define BLM_PHASE_IN_COUNT_MASK (0xff << 8) | |
1913 | #define BLM_PHASE_IN_INCR_SHIFT (0) | |
1914 | #define BLM_PHASE_IN_INCR_MASK (0xff << 0) | |
1915 | #define BLC_PWM_CTL 0x61254 | |
ba3820ad TI |
1916 | /* |
1917 | * This is the most significant 15 bits of the number of backlight cycles in a | |
1918 | * complete cycle of the modulated backlight control. | |
1919 | * | |
1920 | * The actual value is this field multiplied by two. | |
1921 | */ | |
7cf41601 DV |
1922 | #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) |
1923 | #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) | |
1924 | #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */ | |
585fb111 JB |
1925 | /* |
1926 | * This is the number of cycles out of the backlight modulation cycle for which | |
1927 | * the backlight is on. | |
1928 | * | |
1929 | * This field must be no greater than the number of cycles in the complete | |
1930 | * backlight modulation cycle. | |
1931 | */ | |
1932 | #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) | |
1933 | #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) | |
534b5a53 DV |
1934 | #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) |
1935 | #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ | |
585fb111 | 1936 | |
0eb96d6e JB |
1937 | #define BLC_HIST_CTL 0x61260 |
1938 | ||
7cf41601 DV |
1939 | /* New registers for PCH-split platforms. Safe where new bits show up, the |
1940 | * register layout machtes with gen4 BLC_PWM_CTL[12]. */ | |
1941 | #define BLC_PWM_CPU_CTL2 0x48250 | |
1942 | #define BLC_PWM_CPU_CTL 0x48254 | |
1943 | ||
1944 | /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is | |
1945 | * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */ | |
1946 | #define BLC_PWM_PCH_CTL1 0xc8250 | |
4b4147c3 | 1947 | #define BLM_PCH_PWM_ENABLE (1 << 31) |
7cf41601 DV |
1948 | #define BLM_PCH_OVERRIDE_ENABLE (1 << 30) |
1949 | #define BLM_PCH_POLARITY (1 << 29) | |
1950 | #define BLC_PWM_PCH_CTL2 0xc8254 | |
1951 | ||
585fb111 JB |
1952 | /* TV port control */ |
1953 | #define TV_CTL 0x68000 | |
1954 | /** Enables the TV encoder */ | |
1955 | # define TV_ENC_ENABLE (1 << 31) | |
1956 | /** Sources the TV encoder input from pipe B instead of A. */ | |
1957 | # define TV_ENC_PIPEB_SELECT (1 << 30) | |
1958 | /** Outputs composite video (DAC A only) */ | |
1959 | # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) | |
1960 | /** Outputs SVideo video (DAC B/C) */ | |
1961 | # define TV_ENC_OUTPUT_SVIDEO (1 << 28) | |
1962 | /** Outputs Component video (DAC A/B/C) */ | |
1963 | # define TV_ENC_OUTPUT_COMPONENT (2 << 28) | |
1964 | /** Outputs Composite and SVideo (DAC A/B/C) */ | |
1965 | # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) | |
1966 | # define TV_TRILEVEL_SYNC (1 << 21) | |
1967 | /** Enables slow sync generation (945GM only) */ | |
1968 | # define TV_SLOW_SYNC (1 << 20) | |
1969 | /** Selects 4x oversampling for 480i and 576p */ | |
1970 | # define TV_OVERSAMPLE_4X (0 << 18) | |
1971 | /** Selects 2x oversampling for 720p and 1080i */ | |
1972 | # define TV_OVERSAMPLE_2X (1 << 18) | |
1973 | /** Selects no oversampling for 1080p */ | |
1974 | # define TV_OVERSAMPLE_NONE (2 << 18) | |
1975 | /** Selects 8x oversampling */ | |
1976 | # define TV_OVERSAMPLE_8X (3 << 18) | |
1977 | /** Selects progressive mode rather than interlaced */ | |
1978 | # define TV_PROGRESSIVE (1 << 17) | |
1979 | /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */ | |
1980 | # define TV_PAL_BURST (1 << 16) | |
1981 | /** Field for setting delay of Y compared to C */ | |
1982 | # define TV_YC_SKEW_MASK (7 << 12) | |
1983 | /** Enables a fix for 480p/576p standard definition modes on the 915GM only */ | |
1984 | # define TV_ENC_SDP_FIX (1 << 11) | |
1985 | /** | |
1986 | * Enables a fix for the 915GM only. | |
1987 | * | |
1988 | * Not sure what it does. | |
1989 | */ | |
1990 | # define TV_ENC_C0_FIX (1 << 10) | |
1991 | /** Bits that must be preserved by software */ | |
d2d9f232 | 1992 | # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) |
585fb111 JB |
1993 | # define TV_FUSE_STATE_MASK (3 << 4) |
1994 | /** Read-only state that reports all features enabled */ | |
1995 | # define TV_FUSE_STATE_ENABLED (0 << 4) | |
1996 | /** Read-only state that reports that Macrovision is disabled in hardware*/ | |
1997 | # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) | |
1998 | /** Read-only state that reports that TV-out is disabled in hardware. */ | |
1999 | # define TV_FUSE_STATE_DISABLED (2 << 4) | |
2000 | /** Normal operation */ | |
2001 | # define TV_TEST_MODE_NORMAL (0 << 0) | |
2002 | /** Encoder test pattern 1 - combo pattern */ | |
2003 | # define TV_TEST_MODE_PATTERN_1 (1 << 0) | |
2004 | /** Encoder test pattern 2 - full screen vertical 75% color bars */ | |
2005 | # define TV_TEST_MODE_PATTERN_2 (2 << 0) | |
2006 | /** Encoder test pattern 3 - full screen horizontal 75% color bars */ | |
2007 | # define TV_TEST_MODE_PATTERN_3 (3 << 0) | |
2008 | /** Encoder test pattern 4 - random noise */ | |
2009 | # define TV_TEST_MODE_PATTERN_4 (4 << 0) | |
2010 | /** Encoder test pattern 5 - linear color ramps */ | |
2011 | # define TV_TEST_MODE_PATTERN_5 (5 << 0) | |
2012 | /** | |
2013 | * This test mode forces the DACs to 50% of full output. | |
2014 | * | |
2015 | * This is used for load detection in combination with TVDAC_SENSE_MASK | |
2016 | */ | |
2017 | # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) | |
2018 | # define TV_TEST_MODE_MASK (7 << 0) | |
2019 | ||
2020 | #define TV_DAC 0x68004 | |
b8ed2a4f | 2021 | # define TV_DAC_SAVE 0x00ffff00 |
585fb111 JB |
2022 | /** |
2023 | * Reports that DAC state change logic has reported change (RO). | |
2024 | * | |
2025 | * This gets cleared when TV_DAC_STATE_EN is cleared | |
2026 | */ | |
2027 | # define TVDAC_STATE_CHG (1 << 31) | |
2028 | # define TVDAC_SENSE_MASK (7 << 28) | |
2029 | /** Reports that DAC A voltage is above the detect threshold */ | |
2030 | # define TVDAC_A_SENSE (1 << 30) | |
2031 | /** Reports that DAC B voltage is above the detect threshold */ | |
2032 | # define TVDAC_B_SENSE (1 << 29) | |
2033 | /** Reports that DAC C voltage is above the detect threshold */ | |
2034 | # define TVDAC_C_SENSE (1 << 28) | |
2035 | /** | |
2036 | * Enables DAC state detection logic, for load-based TV detection. | |
2037 | * | |
2038 | * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set | |
2039 | * to off, for load detection to work. | |
2040 | */ | |
2041 | # define TVDAC_STATE_CHG_EN (1 << 27) | |
2042 | /** Sets the DAC A sense value to high */ | |
2043 | # define TVDAC_A_SENSE_CTL (1 << 26) | |
2044 | /** Sets the DAC B sense value to high */ | |
2045 | # define TVDAC_B_SENSE_CTL (1 << 25) | |
2046 | /** Sets the DAC C sense value to high */ | |
2047 | # define TVDAC_C_SENSE_CTL (1 << 24) | |
2048 | /** Overrides the ENC_ENABLE and DAC voltage levels */ | |
2049 | # define DAC_CTL_OVERRIDE (1 << 7) | |
2050 | /** Sets the slew rate. Must be preserved in software */ | |
2051 | # define ENC_TVDAC_SLEW_FAST (1 << 6) | |
2052 | # define DAC_A_1_3_V (0 << 4) | |
2053 | # define DAC_A_1_1_V (1 << 4) | |
2054 | # define DAC_A_0_7_V (2 << 4) | |
cb66c692 | 2055 | # define DAC_A_MASK (3 << 4) |
585fb111 JB |
2056 | # define DAC_B_1_3_V (0 << 2) |
2057 | # define DAC_B_1_1_V (1 << 2) | |
2058 | # define DAC_B_0_7_V (2 << 2) | |
cb66c692 | 2059 | # define DAC_B_MASK (3 << 2) |
585fb111 JB |
2060 | # define DAC_C_1_3_V (0 << 0) |
2061 | # define DAC_C_1_1_V (1 << 0) | |
2062 | # define DAC_C_0_7_V (2 << 0) | |
cb66c692 | 2063 | # define DAC_C_MASK (3 << 0) |
585fb111 JB |
2064 | |
2065 | /** | |
2066 | * CSC coefficients are stored in a floating point format with 9 bits of | |
2067 | * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, | |
2068 | * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with | |
2069 | * -1 (0x3) being the only legal negative value. | |
2070 | */ | |
2071 | #define TV_CSC_Y 0x68010 | |
2072 | # define TV_RY_MASK 0x07ff0000 | |
2073 | # define TV_RY_SHIFT 16 | |
2074 | # define TV_GY_MASK 0x00000fff | |
2075 | # define TV_GY_SHIFT 0 | |
2076 | ||
2077 | #define TV_CSC_Y2 0x68014 | |
2078 | # define TV_BY_MASK 0x07ff0000 | |
2079 | # define TV_BY_SHIFT 16 | |
2080 | /** | |
2081 | * Y attenuation for component video. | |
2082 | * | |
2083 | * Stored in 1.9 fixed point. | |
2084 | */ | |
2085 | # define TV_AY_MASK 0x000003ff | |
2086 | # define TV_AY_SHIFT 0 | |
2087 | ||
2088 | #define TV_CSC_U 0x68018 | |
2089 | # define TV_RU_MASK 0x07ff0000 | |
2090 | # define TV_RU_SHIFT 16 | |
2091 | # define TV_GU_MASK 0x000007ff | |
2092 | # define TV_GU_SHIFT 0 | |
2093 | ||
2094 | #define TV_CSC_U2 0x6801c | |
2095 | # define TV_BU_MASK 0x07ff0000 | |
2096 | # define TV_BU_SHIFT 16 | |
2097 | /** | |
2098 | * U attenuation for component video. | |
2099 | * | |
2100 | * Stored in 1.9 fixed point. | |
2101 | */ | |
2102 | # define TV_AU_MASK 0x000003ff | |
2103 | # define TV_AU_SHIFT 0 | |
2104 | ||
2105 | #define TV_CSC_V 0x68020 | |
2106 | # define TV_RV_MASK 0x0fff0000 | |
2107 | # define TV_RV_SHIFT 16 | |
2108 | # define TV_GV_MASK 0x000007ff | |
2109 | # define TV_GV_SHIFT 0 | |
2110 | ||
2111 | #define TV_CSC_V2 0x68024 | |
2112 | # define TV_BV_MASK 0x07ff0000 | |
2113 | # define TV_BV_SHIFT 16 | |
2114 | /** | |
2115 | * V attenuation for component video. | |
2116 | * | |
2117 | * Stored in 1.9 fixed point. | |
2118 | */ | |
2119 | # define TV_AV_MASK 0x000007ff | |
2120 | # define TV_AV_SHIFT 0 | |
2121 | ||
2122 | #define TV_CLR_KNOBS 0x68028 | |
2123 | /** 2s-complement brightness adjustment */ | |
2124 | # define TV_BRIGHTNESS_MASK 0xff000000 | |
2125 | # define TV_BRIGHTNESS_SHIFT 24 | |
2126 | /** Contrast adjustment, as a 2.6 unsigned floating point number */ | |
2127 | # define TV_CONTRAST_MASK 0x00ff0000 | |
2128 | # define TV_CONTRAST_SHIFT 16 | |
2129 | /** Saturation adjustment, as a 2.6 unsigned floating point number */ | |
2130 | # define TV_SATURATION_MASK 0x0000ff00 | |
2131 | # define TV_SATURATION_SHIFT 8 | |
2132 | /** Hue adjustment, as an integer phase angle in degrees */ | |
2133 | # define TV_HUE_MASK 0x000000ff | |
2134 | # define TV_HUE_SHIFT 0 | |
2135 | ||
2136 | #define TV_CLR_LEVEL 0x6802c | |
2137 | /** Controls the DAC level for black */ | |
2138 | # define TV_BLACK_LEVEL_MASK 0x01ff0000 | |
2139 | # define TV_BLACK_LEVEL_SHIFT 16 | |
2140 | /** Controls the DAC level for blanking */ | |
2141 | # define TV_BLANK_LEVEL_MASK 0x000001ff | |
2142 | # define TV_BLANK_LEVEL_SHIFT 0 | |
2143 | ||
2144 | #define TV_H_CTL_1 0x68030 | |
2145 | /** Number of pixels in the hsync. */ | |
2146 | # define TV_HSYNC_END_MASK 0x1fff0000 | |
2147 | # define TV_HSYNC_END_SHIFT 16 | |
2148 | /** Total number of pixels minus one in the line (display and blanking). */ | |
2149 | # define TV_HTOTAL_MASK 0x00001fff | |
2150 | # define TV_HTOTAL_SHIFT 0 | |
2151 | ||
2152 | #define TV_H_CTL_2 0x68034 | |
2153 | /** Enables the colorburst (needed for non-component color) */ | |
2154 | # define TV_BURST_ENA (1 << 31) | |
2155 | /** Offset of the colorburst from the start of hsync, in pixels minus one. */ | |
2156 | # define TV_HBURST_START_SHIFT 16 | |
2157 | # define TV_HBURST_START_MASK 0x1fff0000 | |
2158 | /** Length of the colorburst */ | |
2159 | # define TV_HBURST_LEN_SHIFT 0 | |
2160 | # define TV_HBURST_LEN_MASK 0x0001fff | |
2161 | ||
2162 | #define TV_H_CTL_3 0x68038 | |
2163 | /** End of hblank, measured in pixels minus one from start of hsync */ | |
2164 | # define TV_HBLANK_END_SHIFT 16 | |
2165 | # define TV_HBLANK_END_MASK 0x1fff0000 | |
2166 | /** Start of hblank, measured in pixels minus one from start of hsync */ | |
2167 | # define TV_HBLANK_START_SHIFT 0 | |
2168 | # define TV_HBLANK_START_MASK 0x0001fff | |
2169 | ||
2170 | #define TV_V_CTL_1 0x6803c | |
2171 | /** XXX */ | |
2172 | # define TV_NBR_END_SHIFT 16 | |
2173 | # define TV_NBR_END_MASK 0x07ff0000 | |
2174 | /** XXX */ | |
2175 | # define TV_VI_END_F1_SHIFT 8 | |
2176 | # define TV_VI_END_F1_MASK 0x00003f00 | |
2177 | /** XXX */ | |
2178 | # define TV_VI_END_F2_SHIFT 0 | |
2179 | # define TV_VI_END_F2_MASK 0x0000003f | |
2180 | ||
2181 | #define TV_V_CTL_2 0x68040 | |
2182 | /** Length of vsync, in half lines */ | |
2183 | # define TV_VSYNC_LEN_MASK 0x07ff0000 | |
2184 | # define TV_VSYNC_LEN_SHIFT 16 | |
2185 | /** Offset of the start of vsync in field 1, measured in one less than the | |
2186 | * number of half lines. | |
2187 | */ | |
2188 | # define TV_VSYNC_START_F1_MASK 0x00007f00 | |
2189 | # define TV_VSYNC_START_F1_SHIFT 8 | |
2190 | /** | |
2191 | * Offset of the start of vsync in field 2, measured in one less than the | |
2192 | * number of half lines. | |
2193 | */ | |
2194 | # define TV_VSYNC_START_F2_MASK 0x0000007f | |
2195 | # define TV_VSYNC_START_F2_SHIFT 0 | |
2196 | ||
2197 | #define TV_V_CTL_3 0x68044 | |
2198 | /** Enables generation of the equalization signal */ | |
2199 | # define TV_EQUAL_ENA (1 << 31) | |
2200 | /** Length of vsync, in half lines */ | |
2201 | # define TV_VEQ_LEN_MASK 0x007f0000 | |
2202 | # define TV_VEQ_LEN_SHIFT 16 | |
2203 | /** Offset of the start of equalization in field 1, measured in one less than | |
2204 | * the number of half lines. | |
2205 | */ | |
2206 | # define TV_VEQ_START_F1_MASK 0x0007f00 | |
2207 | # define TV_VEQ_START_F1_SHIFT 8 | |
2208 | /** | |
2209 | * Offset of the start of equalization in field 2, measured in one less than | |
2210 | * the number of half lines. | |
2211 | */ | |
2212 | # define TV_VEQ_START_F2_MASK 0x000007f | |
2213 | # define TV_VEQ_START_F2_SHIFT 0 | |
2214 | ||
2215 | #define TV_V_CTL_4 0x68048 | |
2216 | /** | |
2217 | * Offset to start of vertical colorburst, measured in one less than the | |
2218 | * number of lines from vertical start. | |
2219 | */ | |
2220 | # define TV_VBURST_START_F1_MASK 0x003f0000 | |
2221 | # define TV_VBURST_START_F1_SHIFT 16 | |
2222 | /** | |
2223 | * Offset to the end of vertical colorburst, measured in one less than the | |
2224 | * number of lines from the start of NBR. | |
2225 | */ | |
2226 | # define TV_VBURST_END_F1_MASK 0x000000ff | |
2227 | # define TV_VBURST_END_F1_SHIFT 0 | |
2228 | ||
2229 | #define TV_V_CTL_5 0x6804c | |
2230 | /** | |
2231 | * Offset to start of vertical colorburst, measured in one less than the | |
2232 | * number of lines from vertical start. | |
2233 | */ | |
2234 | # define TV_VBURST_START_F2_MASK 0x003f0000 | |
2235 | # define TV_VBURST_START_F2_SHIFT 16 | |
2236 | /** | |
2237 | * Offset to the end of vertical colorburst, measured in one less than the | |
2238 | * number of lines from the start of NBR. | |
2239 | */ | |
2240 | # define TV_VBURST_END_F2_MASK 0x000000ff | |
2241 | # define TV_VBURST_END_F2_SHIFT 0 | |
2242 | ||
2243 | #define TV_V_CTL_6 0x68050 | |
2244 | /** | |
2245 | * Offset to start of vertical colorburst, measured in one less than the | |
2246 | * number of lines from vertical start. | |
2247 | */ | |
2248 | # define TV_VBURST_START_F3_MASK 0x003f0000 | |
2249 | # define TV_VBURST_START_F3_SHIFT 16 | |
2250 | /** | |
2251 | * Offset to the end of vertical colorburst, measured in one less than the | |
2252 | * number of lines from the start of NBR. | |
2253 | */ | |
2254 | # define TV_VBURST_END_F3_MASK 0x000000ff | |
2255 | # define TV_VBURST_END_F3_SHIFT 0 | |
2256 | ||
2257 | #define TV_V_CTL_7 0x68054 | |
2258 | /** | |
2259 | * Offset to start of vertical colorburst, measured in one less than the | |
2260 | * number of lines from vertical start. | |
2261 | */ | |
2262 | # define TV_VBURST_START_F4_MASK 0x003f0000 | |
2263 | # define TV_VBURST_START_F4_SHIFT 16 | |
2264 | /** | |
2265 | * Offset to the end of vertical colorburst, measured in one less than the | |
2266 | * number of lines from the start of NBR. | |
2267 | */ | |
2268 | # define TV_VBURST_END_F4_MASK 0x000000ff | |
2269 | # define TV_VBURST_END_F4_SHIFT 0 | |
2270 | ||
2271 | #define TV_SC_CTL_1 0x68060 | |
2272 | /** Turns on the first subcarrier phase generation DDA */ | |
2273 | # define TV_SC_DDA1_EN (1 << 31) | |
2274 | /** Turns on the first subcarrier phase generation DDA */ | |
2275 | # define TV_SC_DDA2_EN (1 << 30) | |
2276 | /** Turns on the first subcarrier phase generation DDA */ | |
2277 | # define TV_SC_DDA3_EN (1 << 29) | |
2278 | /** Sets the subcarrier DDA to reset frequency every other field */ | |
2279 | # define TV_SC_RESET_EVERY_2 (0 << 24) | |
2280 | /** Sets the subcarrier DDA to reset frequency every fourth field */ | |
2281 | # define TV_SC_RESET_EVERY_4 (1 << 24) | |
2282 | /** Sets the subcarrier DDA to reset frequency every eighth field */ | |
2283 | # define TV_SC_RESET_EVERY_8 (2 << 24) | |
2284 | /** Sets the subcarrier DDA to never reset the frequency */ | |
2285 | # define TV_SC_RESET_NEVER (3 << 24) | |
2286 | /** Sets the peak amplitude of the colorburst.*/ | |
2287 | # define TV_BURST_LEVEL_MASK 0x00ff0000 | |
2288 | # define TV_BURST_LEVEL_SHIFT 16 | |
2289 | /** Sets the increment of the first subcarrier phase generation DDA */ | |
2290 | # define TV_SCDDA1_INC_MASK 0x00000fff | |
2291 | # define TV_SCDDA1_INC_SHIFT 0 | |
2292 | ||
2293 | #define TV_SC_CTL_2 0x68064 | |
2294 | /** Sets the rollover for the second subcarrier phase generation DDA */ | |
2295 | # define TV_SCDDA2_SIZE_MASK 0x7fff0000 | |
2296 | # define TV_SCDDA2_SIZE_SHIFT 16 | |
2297 | /** Sets the increent of the second subcarrier phase generation DDA */ | |
2298 | # define TV_SCDDA2_INC_MASK 0x00007fff | |
2299 | # define TV_SCDDA2_INC_SHIFT 0 | |
2300 | ||
2301 | #define TV_SC_CTL_3 0x68068 | |
2302 | /** Sets the rollover for the third subcarrier phase generation DDA */ | |
2303 | # define TV_SCDDA3_SIZE_MASK 0x7fff0000 | |
2304 | # define TV_SCDDA3_SIZE_SHIFT 16 | |
2305 | /** Sets the increent of the third subcarrier phase generation DDA */ | |
2306 | # define TV_SCDDA3_INC_MASK 0x00007fff | |
2307 | # define TV_SCDDA3_INC_SHIFT 0 | |
2308 | ||
2309 | #define TV_WIN_POS 0x68070 | |
2310 | /** X coordinate of the display from the start of horizontal active */ | |
2311 | # define TV_XPOS_MASK 0x1fff0000 | |
2312 | # define TV_XPOS_SHIFT 16 | |
2313 | /** Y coordinate of the display from the start of vertical active (NBR) */ | |
2314 | # define TV_YPOS_MASK 0x00000fff | |
2315 | # define TV_YPOS_SHIFT 0 | |
2316 | ||
2317 | #define TV_WIN_SIZE 0x68074 | |
2318 | /** Horizontal size of the display window, measured in pixels*/ | |
2319 | # define TV_XSIZE_MASK 0x1fff0000 | |
2320 | # define TV_XSIZE_SHIFT 16 | |
2321 | /** | |
2322 | * Vertical size of the display window, measured in pixels. | |
2323 | * | |
2324 | * Must be even for interlaced modes. | |
2325 | */ | |
2326 | # define TV_YSIZE_MASK 0x00000fff | |
2327 | # define TV_YSIZE_SHIFT 0 | |
2328 | ||
2329 | #define TV_FILTER_CTL_1 0x68080 | |
2330 | /** | |
2331 | * Enables automatic scaling calculation. | |
2332 | * | |
2333 | * If set, the rest of the registers are ignored, and the calculated values can | |
2334 | * be read back from the register. | |
2335 | */ | |
2336 | # define TV_AUTO_SCALE (1 << 31) | |
2337 | /** | |
2338 | * Disables the vertical filter. | |
2339 | * | |
2340 | * This is required on modes more than 1024 pixels wide */ | |
2341 | # define TV_V_FILTER_BYPASS (1 << 29) | |
2342 | /** Enables adaptive vertical filtering */ | |
2343 | # define TV_VADAPT (1 << 28) | |
2344 | # define TV_VADAPT_MODE_MASK (3 << 26) | |
2345 | /** Selects the least adaptive vertical filtering mode */ | |
2346 | # define TV_VADAPT_MODE_LEAST (0 << 26) | |
2347 | /** Selects the moderately adaptive vertical filtering mode */ | |
2348 | # define TV_VADAPT_MODE_MODERATE (1 << 26) | |
2349 | /** Selects the most adaptive vertical filtering mode */ | |
2350 | # define TV_VADAPT_MODE_MOST (3 << 26) | |
2351 | /** | |
2352 | * Sets the horizontal scaling factor. | |
2353 | * | |
2354 | * This should be the fractional part of the horizontal scaling factor divided | |
2355 | * by the oversampling rate. TV_HSCALE should be less than 1, and set to: | |
2356 | * | |
2357 | * (src width - 1) / ((oversample * dest width) - 1) | |
2358 | */ | |
2359 | # define TV_HSCALE_FRAC_MASK 0x00003fff | |
2360 | # define TV_HSCALE_FRAC_SHIFT 0 | |
2361 | ||
2362 | #define TV_FILTER_CTL_2 0x68084 | |
2363 | /** | |
2364 | * Sets the integer part of the 3.15 fixed-point vertical scaling factor. | |
2365 | * | |
2366 | * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) | |
2367 | */ | |
2368 | # define TV_VSCALE_INT_MASK 0x00038000 | |
2369 | # define TV_VSCALE_INT_SHIFT 15 | |
2370 | /** | |
2371 | * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. | |
2372 | * | |
2373 | * \sa TV_VSCALE_INT_MASK | |
2374 | */ | |
2375 | # define TV_VSCALE_FRAC_MASK 0x00007fff | |
2376 | # define TV_VSCALE_FRAC_SHIFT 0 | |
2377 | ||
2378 | #define TV_FILTER_CTL_3 0x68088 | |
2379 | /** | |
2380 | * Sets the integer part of the 3.15 fixed-point vertical scaling factor. | |
2381 | * | |
2382 | * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) | |
2383 | * | |
2384 | * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. | |
2385 | */ | |
2386 | # define TV_VSCALE_IP_INT_MASK 0x00038000 | |
2387 | # define TV_VSCALE_IP_INT_SHIFT 15 | |
2388 | /** | |
2389 | * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. | |
2390 | * | |
2391 | * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. | |
2392 | * | |
2393 | * \sa TV_VSCALE_IP_INT_MASK | |
2394 | */ | |
2395 | # define TV_VSCALE_IP_FRAC_MASK 0x00007fff | |
2396 | # define TV_VSCALE_IP_FRAC_SHIFT 0 | |
2397 | ||
2398 | #define TV_CC_CONTROL 0x68090 | |
2399 | # define TV_CC_ENABLE (1 << 31) | |
2400 | /** | |
2401 | * Specifies which field to send the CC data in. | |
2402 | * | |
2403 | * CC data is usually sent in field 0. | |
2404 | */ | |
2405 | # define TV_CC_FID_MASK (1 << 27) | |
2406 | # define TV_CC_FID_SHIFT 27 | |
2407 | /** Sets the horizontal position of the CC data. Usually 135. */ | |
2408 | # define TV_CC_HOFF_MASK 0x03ff0000 | |
2409 | # define TV_CC_HOFF_SHIFT 16 | |
2410 | /** Sets the vertical position of the CC data. Usually 21 */ | |
2411 | # define TV_CC_LINE_MASK 0x0000003f | |
2412 | # define TV_CC_LINE_SHIFT 0 | |
2413 | ||
2414 | #define TV_CC_DATA 0x68094 | |
2415 | # define TV_CC_RDY (1 << 31) | |
2416 | /** Second word of CC data to be transmitted. */ | |
2417 | # define TV_CC_DATA_2_MASK 0x007f0000 | |
2418 | # define TV_CC_DATA_2_SHIFT 16 | |
2419 | /** First word of CC data to be transmitted. */ | |
2420 | # define TV_CC_DATA_1_MASK 0x0000007f | |
2421 | # define TV_CC_DATA_1_SHIFT 0 | |
2422 | ||
2423 | #define TV_H_LUMA_0 0x68100 | |
2424 | #define TV_H_LUMA_59 0x681ec | |
2425 | #define TV_H_CHROMA_0 0x68200 | |
2426 | #define TV_H_CHROMA_59 0x682ec | |
2427 | #define TV_V_LUMA_0 0x68300 | |
2428 | #define TV_V_LUMA_42 0x683a8 | |
2429 | #define TV_V_CHROMA_0 0x68400 | |
2430 | #define TV_V_CHROMA_42 0x684a8 | |
2431 | ||
040d87f1 | 2432 | /* Display Port */ |
32f9d658 | 2433 | #define DP_A 0x64000 /* eDP */ |
040d87f1 KP |
2434 | #define DP_B 0x64100 |
2435 | #define DP_C 0x64200 | |
2436 | #define DP_D 0x64300 | |
2437 | ||
2438 | #define DP_PORT_EN (1 << 31) | |
2439 | #define DP_PIPEB_SELECT (1 << 30) | |
47a05eca JB |
2440 | #define DP_PIPE_MASK (1 << 30) |
2441 | ||
040d87f1 KP |
2442 | /* Link training mode - select a suitable mode for each stage */ |
2443 | #define DP_LINK_TRAIN_PAT_1 (0 << 28) | |
2444 | #define DP_LINK_TRAIN_PAT_2 (1 << 28) | |
2445 | #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) | |
2446 | #define DP_LINK_TRAIN_OFF (3 << 28) | |
2447 | #define DP_LINK_TRAIN_MASK (3 << 28) | |
2448 | #define DP_LINK_TRAIN_SHIFT 28 | |
2449 | ||
8db9d77b ZW |
2450 | /* CPT Link training mode */ |
2451 | #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) | |
2452 | #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) | |
2453 | #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) | |
2454 | #define DP_LINK_TRAIN_OFF_CPT (3 << 8) | |
2455 | #define DP_LINK_TRAIN_MASK_CPT (7 << 8) | |
2456 | #define DP_LINK_TRAIN_SHIFT_CPT 8 | |
2457 | ||
040d87f1 KP |
2458 | /* Signal voltages. These are mostly controlled by the other end */ |
2459 | #define DP_VOLTAGE_0_4 (0 << 25) | |
2460 | #define DP_VOLTAGE_0_6 (1 << 25) | |
2461 | #define DP_VOLTAGE_0_8 (2 << 25) | |
2462 | #define DP_VOLTAGE_1_2 (3 << 25) | |
2463 | #define DP_VOLTAGE_MASK (7 << 25) | |
2464 | #define DP_VOLTAGE_SHIFT 25 | |
2465 | ||
2466 | /* Signal pre-emphasis levels, like voltages, the other end tells us what | |
2467 | * they want | |
2468 | */ | |
2469 | #define DP_PRE_EMPHASIS_0 (0 << 22) | |
2470 | #define DP_PRE_EMPHASIS_3_5 (1 << 22) | |
2471 | #define DP_PRE_EMPHASIS_6 (2 << 22) | |
2472 | #define DP_PRE_EMPHASIS_9_5 (3 << 22) | |
2473 | #define DP_PRE_EMPHASIS_MASK (7 << 22) | |
2474 | #define DP_PRE_EMPHASIS_SHIFT 22 | |
2475 | ||
2476 | /* How many wires to use. I guess 3 was too hard */ | |
2477 | #define DP_PORT_WIDTH_1 (0 << 19) | |
2478 | #define DP_PORT_WIDTH_2 (1 << 19) | |
2479 | #define DP_PORT_WIDTH_4 (3 << 19) | |
2480 | #define DP_PORT_WIDTH_MASK (7 << 19) | |
2481 | ||
2482 | /* Mystic DPCD version 1.1 special mode */ | |
2483 | #define DP_ENHANCED_FRAMING (1 << 18) | |
2484 | ||
32f9d658 ZW |
2485 | /* eDP */ |
2486 | #define DP_PLL_FREQ_270MHZ (0 << 16) | |
2487 | #define DP_PLL_FREQ_160MHZ (1 << 16) | |
2488 | #define DP_PLL_FREQ_MASK (3 << 16) | |
2489 | ||
040d87f1 KP |
2490 | /** locked once port is enabled */ |
2491 | #define DP_PORT_REVERSAL (1 << 15) | |
2492 | ||
32f9d658 ZW |
2493 | /* eDP */ |
2494 | #define DP_PLL_ENABLE (1 << 14) | |
2495 | ||
040d87f1 KP |
2496 | /** sends the clock on lane 15 of the PEG for debug */ |
2497 | #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) | |
2498 | ||
2499 | #define DP_SCRAMBLING_DISABLE (1 << 12) | |
f2b115e6 | 2500 | #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) |
040d87f1 KP |
2501 | |
2502 | /** limit RGB values to avoid confusing TVs */ | |
2503 | #define DP_COLOR_RANGE_16_235 (1 << 8) | |
2504 | ||
2505 | /** Turn on the audio link */ | |
2506 | #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) | |
2507 | ||
2508 | /** vs and hs sync polarity */ | |
2509 | #define DP_SYNC_VS_HIGH (1 << 4) | |
2510 | #define DP_SYNC_HS_HIGH (1 << 3) | |
2511 | ||
2512 | /** A fantasy */ | |
2513 | #define DP_DETECTED (1 << 2) | |
2514 | ||
2515 | /** The aux channel provides a way to talk to the | |
2516 | * signal sink for DDC etc. Max packet size supported | |
2517 | * is 20 bytes in each direction, hence the 5 fixed | |
2518 | * data registers | |
2519 | */ | |
32f9d658 ZW |
2520 | #define DPA_AUX_CH_CTL 0x64010 |
2521 | #define DPA_AUX_CH_DATA1 0x64014 | |
2522 | #define DPA_AUX_CH_DATA2 0x64018 | |
2523 | #define DPA_AUX_CH_DATA3 0x6401c | |
2524 | #define DPA_AUX_CH_DATA4 0x64020 | |
2525 | #define DPA_AUX_CH_DATA5 0x64024 | |
2526 | ||
040d87f1 KP |
2527 | #define DPB_AUX_CH_CTL 0x64110 |
2528 | #define DPB_AUX_CH_DATA1 0x64114 | |
2529 | #define DPB_AUX_CH_DATA2 0x64118 | |
2530 | #define DPB_AUX_CH_DATA3 0x6411c | |
2531 | #define DPB_AUX_CH_DATA4 0x64120 | |
2532 | #define DPB_AUX_CH_DATA5 0x64124 | |
2533 | ||
2534 | #define DPC_AUX_CH_CTL 0x64210 | |
2535 | #define DPC_AUX_CH_DATA1 0x64214 | |
2536 | #define DPC_AUX_CH_DATA2 0x64218 | |
2537 | #define DPC_AUX_CH_DATA3 0x6421c | |
2538 | #define DPC_AUX_CH_DATA4 0x64220 | |
2539 | #define DPC_AUX_CH_DATA5 0x64224 | |
2540 | ||
2541 | #define DPD_AUX_CH_CTL 0x64310 | |
2542 | #define DPD_AUX_CH_DATA1 0x64314 | |
2543 | #define DPD_AUX_CH_DATA2 0x64318 | |
2544 | #define DPD_AUX_CH_DATA3 0x6431c | |
2545 | #define DPD_AUX_CH_DATA4 0x64320 | |
2546 | #define DPD_AUX_CH_DATA5 0x64324 | |
2547 | ||
2548 | #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) | |
2549 | #define DP_AUX_CH_CTL_DONE (1 << 30) | |
2550 | #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) | |
2551 | #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) | |
2552 | #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) | |
2553 | #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) | |
2554 | #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) | |
2555 | #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) | |
2556 | #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) | |
2557 | #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) | |
2558 | #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) | |
2559 | #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 | |
2560 | #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) | |
2561 | #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 | |
2562 | #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) | |
2563 | #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) | |
2564 | #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) | |
2565 | #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) | |
2566 | #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) | |
2567 | #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) | |
2568 | #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 | |
2569 | ||
2570 | /* | |
2571 | * Computing GMCH M and N values for the Display Port link | |
2572 | * | |
2573 | * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes | |
2574 | * | |
2575 | * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) | |
2576 | * | |
2577 | * The GMCH value is used internally | |
2578 | * | |
2579 | * bytes_per_pixel is the number of bytes coming out of the plane, | |
2580 | * which is after the LUTs, so we want the bytes for our color format. | |
2581 | * For our current usage, this is always 3, one byte for R, G and B. | |
2582 | */ | |
9db4a9c7 JB |
2583 | #define _PIPEA_GMCH_DATA_M 0x70050 |
2584 | #define _PIPEB_GMCH_DATA_M 0x71050 | |
040d87f1 KP |
2585 | |
2586 | /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ | |
2587 | #define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25) | |
2588 | #define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25 | |
2589 | ||
2590 | #define PIPE_GMCH_DATA_M_MASK (0xffffff) | |
2591 | ||
9db4a9c7 JB |
2592 | #define _PIPEA_GMCH_DATA_N 0x70054 |
2593 | #define _PIPEB_GMCH_DATA_N 0x71054 | |
040d87f1 KP |
2594 | #define PIPE_GMCH_DATA_N_MASK (0xffffff) |
2595 | ||
2596 | /* | |
2597 | * Computing Link M and N values for the Display Port link | |
2598 | * | |
2599 | * Link M / N = pixel_clock / ls_clk | |
2600 | * | |
2601 | * (the DP spec calls pixel_clock the 'strm_clk') | |
2602 | * | |
2603 | * The Link value is transmitted in the Main Stream | |
2604 | * Attributes and VB-ID. | |
2605 | */ | |
2606 | ||
9db4a9c7 JB |
2607 | #define _PIPEA_DP_LINK_M 0x70060 |
2608 | #define _PIPEB_DP_LINK_M 0x71060 | |
040d87f1 KP |
2609 | #define PIPEA_DP_LINK_M_MASK (0xffffff) |
2610 | ||
9db4a9c7 JB |
2611 | #define _PIPEA_DP_LINK_N 0x70064 |
2612 | #define _PIPEB_DP_LINK_N 0x71064 | |
040d87f1 KP |
2613 | #define PIPEA_DP_LINK_N_MASK (0xffffff) |
2614 | ||
9db4a9c7 JB |
2615 | #define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M) |
2616 | #define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N) | |
2617 | #define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M) | |
2618 | #define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N) | |
2619 | ||
585fb111 JB |
2620 | /* Display & cursor control */ |
2621 | ||
2622 | /* Pipe A */ | |
0c3870ee | 2623 | #define _PIPEADSL (dev_priv->info->display_mmio_offset + 0x70000) |
837ba00f PZ |
2624 | #define DSL_LINEMASK_GEN2 0x00000fff |
2625 | #define DSL_LINEMASK_GEN3 0x00001fff | |
0c3870ee | 2626 | #define _PIPEACONF (dev_priv->info->display_mmio_offset + 0x70008) |
5eddb70b CW |
2627 | #define PIPECONF_ENABLE (1<<31) |
2628 | #define PIPECONF_DISABLE 0 | |
2629 | #define PIPECONF_DOUBLE_WIDE (1<<30) | |
585fb111 | 2630 | #define I965_PIPECONF_ACTIVE (1<<30) |
f47166d2 | 2631 | #define PIPECONF_FRAME_START_DELAY_MASK (3<<27) |
5eddb70b CW |
2632 | #define PIPECONF_SINGLE_WIDE 0 |
2633 | #define PIPECONF_PIPE_UNLOCKED 0 | |
2634 | #define PIPECONF_PIPE_LOCKED (1<<25) | |
2635 | #define PIPECONF_PALETTE 0 | |
2636 | #define PIPECONF_GAMMA (1<<24) | |
585fb111 | 2637 | #define PIPECONF_FORCE_BORDER (1<<25) |
59df7b17 | 2638 | #define PIPECONF_INTERLACE_MASK (7 << 21) |
ee2b0b38 | 2639 | #define PIPECONF_INTERLACE_MASK_HSW (3 << 21) |
d442ae18 DV |
2640 | /* Note that pre-gen3 does not support interlaced display directly. Panel |
2641 | * fitting must be disabled on pre-ilk for interlaced. */ | |
2642 | #define PIPECONF_PROGRESSIVE (0 << 21) | |
2643 | #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ | |
2644 | #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ | |
2645 | #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) | |
2646 | #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ | |
2647 | /* Ironlake and later have a complete new set of values for interlaced. PFIT | |
2648 | * means panel fitter required, PF means progressive fetch, DBL means power | |
2649 | * saving pixel doubling. */ | |
2650 | #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) | |
2651 | #define PIPECONF_INTERLACED_ILK (3 << 21) | |
2652 | #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ | |
2653 | #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ | |
652c393a | 2654 | #define PIPECONF_CXSR_DOWNCLOCK (1<<16) |
3685a8f3 | 2655 | #define PIPECONF_COLOR_RANGE_SELECT (1 << 13) |
dfd07d72 DV |
2656 | #define PIPECONF_BPC_MASK (0x7 << 5) |
2657 | #define PIPECONF_8BPC (0<<5) | |
2658 | #define PIPECONF_10BPC (1<<5) | |
2659 | #define PIPECONF_6BPC (2<<5) | |
2660 | #define PIPECONF_12BPC (3<<5) | |
4f0d1aff JB |
2661 | #define PIPECONF_DITHER_EN (1<<4) |
2662 | #define PIPECONF_DITHER_TYPE_MASK (0x0000000c) | |
2663 | #define PIPECONF_DITHER_TYPE_SP (0<<2) | |
2664 | #define PIPECONF_DITHER_TYPE_ST1 (1<<2) | |
2665 | #define PIPECONF_DITHER_TYPE_ST2 (2<<2) | |
2666 | #define PIPECONF_DITHER_TYPE_TEMP (3<<2) | |
0c3870ee | 2667 | #define _PIPEASTAT (dev_priv->info->display_mmio_offset + 0x70024) |
585fb111 | 2668 | #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) |
c46ce4d7 | 2669 | #define SPRITE1_FLIPDONE_INT_EN_VLV (1UL<<30) |
585fb111 JB |
2670 | #define PIPE_CRC_ERROR_ENABLE (1UL<<29) |
2671 | #define PIPE_CRC_DONE_ENABLE (1UL<<28) | |
2672 | #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) | |
c46ce4d7 | 2673 | #define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26) |
585fb111 JB |
2674 | #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) |
2675 | #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) | |
2676 | #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) | |
2677 | #define PIPE_DPST_EVENT_ENABLE (1UL<<23) | |
c70af1e4 | 2678 | #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22) |
585fb111 JB |
2679 | #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) |
2680 | #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) | |
2681 | #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) | |
2682 | #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ | |
2683 | #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ | |
2684 | #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) | |
c46ce4d7 | 2685 | #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16) |
585fb111 | 2686 | #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) |
c46ce4d7 | 2687 | #define SPRITE1_FLIPDONE_INT_STATUS_VLV (1UL<<15) |
c70af1e4 | 2688 | #define SPRITE0_FLIPDONE_INT_STATUS_VLV (1UL<<14) |
585fb111 JB |
2689 | #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) |
2690 | #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) | |
2691 | #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) | |
c46ce4d7 | 2692 | #define PLANE_FLIPDONE_INT_STATUS_VLV (1UL<<10) |
585fb111 JB |
2693 | #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) |
2694 | #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) | |
2695 | #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) | |
2696 | #define PIPE_DPST_EVENT_STATUS (1UL<<7) | |
2697 | #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) | |
2698 | #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) | |
2699 | #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) | |
2700 | #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ | |
2701 | #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ | |
2702 | #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) | |
2703 | #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) | |
2704 | ||
9db4a9c7 | 2705 | #define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC) |
702e7a56 | 2706 | #define PIPECONF(tran) _TRANSCODER(tran, _PIPEACONF, _PIPEBCONF) |
9db4a9c7 JB |
2707 | #define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL) |
2708 | #define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH) | |
2709 | #define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL) | |
2710 | #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT) | |
5eddb70b | 2711 | |
b41fbda1 | 2712 | #define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028) |
7983117f | 2713 | #define PIPEB_LINE_COMPARE_INT_EN (1<<29) |
c46ce4d7 JB |
2714 | #define PIPEB_HLINE_INT_EN (1<<28) |
2715 | #define PIPEB_VBLANK_INT_EN (1<<27) | |
2716 | #define SPRITED_FLIPDONE_INT_EN (1<<26) | |
2717 | #define SPRITEC_FLIPDONE_INT_EN (1<<25) | |
2718 | #define PLANEB_FLIPDONE_INT_EN (1<<24) | |
7983117f | 2719 | #define PIPEA_LINE_COMPARE_INT_EN (1<<21) |
c46ce4d7 JB |
2720 | #define PIPEA_HLINE_INT_EN (1<<20) |
2721 | #define PIPEA_VBLANK_INT_EN (1<<19) | |
2722 | #define SPRITEB_FLIPDONE_INT_EN (1<<18) | |
2723 | #define SPRITEA_FLIPDONE_INT_EN (1<<17) | |
2724 | #define PLANEA_FLIPDONE_INT_EN (1<<16) | |
2725 | ||
b41fbda1 | 2726 | #define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV only */ |
c46ce4d7 JB |
2727 | #define CURSORB_INVALID_GTT_INT_EN (1<<23) |
2728 | #define CURSORA_INVALID_GTT_INT_EN (1<<22) | |
2729 | #define SPRITED_INVALID_GTT_INT_EN (1<<21) | |
2730 | #define SPRITEC_INVALID_GTT_INT_EN (1<<20) | |
2731 | #define PLANEB_INVALID_GTT_INT_EN (1<<19) | |
2732 | #define SPRITEB_INVALID_GTT_INT_EN (1<<18) | |
2733 | #define SPRITEA_INVALID_GTT_INT_EN (1<<17) | |
2734 | #define PLANEA_INVALID_GTT_INT_EN (1<<16) | |
2735 | #define DPINVGTT_EN_MASK 0xff0000 | |
2736 | #define CURSORB_INVALID_GTT_STATUS (1<<7) | |
2737 | #define CURSORA_INVALID_GTT_STATUS (1<<6) | |
2738 | #define SPRITED_INVALID_GTT_STATUS (1<<5) | |
2739 | #define SPRITEC_INVALID_GTT_STATUS (1<<4) | |
2740 | #define PLANEB_INVALID_GTT_STATUS (1<<3) | |
2741 | #define SPRITEB_INVALID_GTT_STATUS (1<<2) | |
2742 | #define SPRITEA_INVALID_GTT_STATUS (1<<1) | |
2743 | #define PLANEA_INVALID_GTT_STATUS (1<<0) | |
2744 | #define DPINVGTT_STATUS_MASK 0xff | |
2745 | ||
585fb111 JB |
2746 | #define DSPARB 0x70030 |
2747 | #define DSPARB_CSTART_MASK (0x7f << 7) | |
2748 | #define DSPARB_CSTART_SHIFT 7 | |
2749 | #define DSPARB_BSTART_MASK (0x7f) | |
2750 | #define DSPARB_BSTART_SHIFT 0 | |
7662c8bd SL |
2751 | #define DSPARB_BEND_SHIFT 9 /* on 855 */ |
2752 | #define DSPARB_AEND_SHIFT 0 | |
2753 | ||
90f7da3f | 2754 | #define DSPFW1 (dev_priv->info->display_mmio_offset + 0x70034) |
0e442c60 | 2755 | #define DSPFW_SR_SHIFT 23 |
0206e353 | 2756 | #define DSPFW_SR_MASK (0x1ff<<23) |
0e442c60 | 2757 | #define DSPFW_CURSORB_SHIFT 16 |
d4294342 | 2758 | #define DSPFW_CURSORB_MASK (0x3f<<16) |
0e442c60 | 2759 | #define DSPFW_PLANEB_SHIFT 8 |
d4294342 ZY |
2760 | #define DSPFW_PLANEB_MASK (0x7f<<8) |
2761 | #define DSPFW_PLANEA_MASK (0x7f) | |
90f7da3f | 2762 | #define DSPFW2 (dev_priv->info->display_mmio_offset + 0x70038) |
0e442c60 | 2763 | #define DSPFW_CURSORA_MASK 0x00003f00 |
21bd770b | 2764 | #define DSPFW_CURSORA_SHIFT 8 |
d4294342 | 2765 | #define DSPFW_PLANEC_MASK (0x7f) |
90f7da3f | 2766 | #define DSPFW3 (dev_priv->info->display_mmio_offset + 0x7003c) |
0e442c60 JB |
2767 | #define DSPFW_HPLL_SR_EN (1<<31) |
2768 | #define DSPFW_CURSOR_SR_SHIFT 24 | |
f2b115e6 | 2769 | #define PINEVIEW_SELF_REFRESH_EN (1<<30) |
d4294342 ZY |
2770 | #define DSPFW_CURSOR_SR_MASK (0x3f<<24) |
2771 | #define DSPFW_HPLL_CURSOR_SHIFT 16 | |
2772 | #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) | |
2773 | #define DSPFW_HPLL_SR_MASK (0x1ff) | |
7662c8bd | 2774 | |
12a3c055 GB |
2775 | /* drain latency register values*/ |
2776 | #define DRAIN_LATENCY_PRECISION_32 32 | |
2777 | #define DRAIN_LATENCY_PRECISION_16 16 | |
8f6d8ee9 | 2778 | #define VLV_DDL1 (VLV_DISPLAY_BASE + 0x70050) |
12a3c055 GB |
2779 | #define DDL_CURSORA_PRECISION_32 (1<<31) |
2780 | #define DDL_CURSORA_PRECISION_16 (0<<31) | |
2781 | #define DDL_CURSORA_SHIFT 24 | |
2782 | #define DDL_PLANEA_PRECISION_32 (1<<7) | |
2783 | #define DDL_PLANEA_PRECISION_16 (0<<7) | |
8f6d8ee9 | 2784 | #define VLV_DDL2 (VLV_DISPLAY_BASE + 0x70054) |
12a3c055 GB |
2785 | #define DDL_CURSORB_PRECISION_32 (1<<31) |
2786 | #define DDL_CURSORB_PRECISION_16 (0<<31) | |
2787 | #define DDL_CURSORB_SHIFT 24 | |
2788 | #define DDL_PLANEB_PRECISION_32 (1<<7) | |
2789 | #define DDL_PLANEB_PRECISION_16 (0<<7) | |
2790 | ||
7662c8bd | 2791 | /* FIFO watermark sizes etc */ |
0e442c60 | 2792 | #define G4X_FIFO_LINE_SIZE 64 |
7662c8bd SL |
2793 | #define I915_FIFO_LINE_SIZE 64 |
2794 | #define I830_FIFO_LINE_SIZE 32 | |
0e442c60 | 2795 | |
ceb04246 | 2796 | #define VALLEYVIEW_FIFO_SIZE 255 |
0e442c60 | 2797 | #define G4X_FIFO_SIZE 127 |
1b07e04e ZY |
2798 | #define I965_FIFO_SIZE 512 |
2799 | #define I945_FIFO_SIZE 127 | |
7662c8bd | 2800 | #define I915_FIFO_SIZE 95 |
dff33cfc | 2801 | #define I855GM_FIFO_SIZE 127 /* In cachelines */ |
7662c8bd | 2802 | #define I830_FIFO_SIZE 95 |
0e442c60 | 2803 | |
ceb04246 | 2804 | #define VALLEYVIEW_MAX_WM 0xff |
0e442c60 | 2805 | #define G4X_MAX_WM 0x3f |
7662c8bd SL |
2806 | #define I915_MAX_WM 0x3f |
2807 | ||
f2b115e6 AJ |
2808 | #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ |
2809 | #define PINEVIEW_FIFO_LINE_SIZE 64 | |
2810 | #define PINEVIEW_MAX_WM 0x1ff | |
2811 | #define PINEVIEW_DFT_WM 0x3f | |
2812 | #define PINEVIEW_DFT_HPLLOFF_WM 0 | |
2813 | #define PINEVIEW_GUARD_WM 10 | |
2814 | #define PINEVIEW_CURSOR_FIFO 64 | |
2815 | #define PINEVIEW_CURSOR_MAX_WM 0x3f | |
2816 | #define PINEVIEW_CURSOR_DFT_WM 0 | |
2817 | #define PINEVIEW_CURSOR_GUARD_WM 5 | |
7662c8bd | 2818 | |
ceb04246 | 2819 | #define VALLEYVIEW_CURSOR_MAX_WM 64 |
4fe5e611 ZY |
2820 | #define I965_CURSOR_FIFO 64 |
2821 | #define I965_CURSOR_MAX_WM 32 | |
2822 | #define I965_CURSOR_DFT_WM 8 | |
7f8a8569 ZW |
2823 | |
2824 | /* define the Watermark register on Ironlake */ | |
2825 | #define WM0_PIPEA_ILK 0x45100 | |
2826 | #define WM0_PIPE_PLANE_MASK (0x7f<<16) | |
2827 | #define WM0_PIPE_PLANE_SHIFT 16 | |
2828 | #define WM0_PIPE_SPRITE_MASK (0x3f<<8) | |
2829 | #define WM0_PIPE_SPRITE_SHIFT 8 | |
2830 | #define WM0_PIPE_CURSOR_MASK (0x1f) | |
2831 | ||
2832 | #define WM0_PIPEB_ILK 0x45104 | |
d6c892df | 2833 | #define WM0_PIPEC_IVB 0x45200 |
7f8a8569 ZW |
2834 | #define WM1_LP_ILK 0x45108 |
2835 | #define WM1_LP_SR_EN (1<<31) | |
2836 | #define WM1_LP_LATENCY_SHIFT 24 | |
2837 | #define WM1_LP_LATENCY_MASK (0x7f<<24) | |
4ed765f9 CW |
2838 | #define WM1_LP_FBC_MASK (0xf<<20) |
2839 | #define WM1_LP_FBC_SHIFT 20 | |
7f8a8569 ZW |
2840 | #define WM1_LP_SR_MASK (0x1ff<<8) |
2841 | #define WM1_LP_SR_SHIFT 8 | |
2842 | #define WM1_LP_CURSOR_MASK (0x3f) | |
dd8849c8 JB |
2843 | #define WM2_LP_ILK 0x4510c |
2844 | #define WM2_LP_EN (1<<31) | |
2845 | #define WM3_LP_ILK 0x45110 | |
2846 | #define WM3_LP_EN (1<<31) | |
2847 | #define WM1S_LP_ILK 0x45120 | |
b840d907 JB |
2848 | #define WM2S_LP_IVB 0x45124 |
2849 | #define WM3S_LP_IVB 0x45128 | |
dd8849c8 | 2850 | #define WM1S_LP_EN (1<<31) |
7f8a8569 ZW |
2851 | |
2852 | /* Memory latency timer register */ | |
2853 | #define MLTR_ILK 0x11222 | |
b79d4990 JB |
2854 | #define MLTR_WM1_SHIFT 0 |
2855 | #define MLTR_WM2_SHIFT 8 | |
7f8a8569 ZW |
2856 | /* the unit of memory self-refresh latency time is 0.5us */ |
2857 | #define ILK_SRLT_MASK 0x3f | |
b79d4990 JB |
2858 | #define ILK_LATENCY(shift) (I915_READ(MLTR_ILK) >> (shift) & ILK_SRLT_MASK) |
2859 | #define ILK_READ_WM1_LATENCY() ILK_LATENCY(MLTR_WM1_SHIFT) | |
2860 | #define ILK_READ_WM2_LATENCY() ILK_LATENCY(MLTR_WM2_SHIFT) | |
7f8a8569 ZW |
2861 | |
2862 | /* define the fifo size on Ironlake */ | |
2863 | #define ILK_DISPLAY_FIFO 128 | |
2864 | #define ILK_DISPLAY_MAXWM 64 | |
2865 | #define ILK_DISPLAY_DFTWM 8 | |
c936f44d ZY |
2866 | #define ILK_CURSOR_FIFO 32 |
2867 | #define ILK_CURSOR_MAXWM 16 | |
2868 | #define ILK_CURSOR_DFTWM 8 | |
7f8a8569 ZW |
2869 | |
2870 | #define ILK_DISPLAY_SR_FIFO 512 | |
2871 | #define ILK_DISPLAY_MAX_SRWM 0x1ff | |
2872 | #define ILK_DISPLAY_DFT_SRWM 0x3f | |
2873 | #define ILK_CURSOR_SR_FIFO 64 | |
2874 | #define ILK_CURSOR_MAX_SRWM 0x3f | |
2875 | #define ILK_CURSOR_DFT_SRWM 8 | |
2876 | ||
2877 | #define ILK_FIFO_LINE_SIZE 64 | |
2878 | ||
1398261a YL |
2879 | /* define the WM info on Sandybridge */ |
2880 | #define SNB_DISPLAY_FIFO 128 | |
2881 | #define SNB_DISPLAY_MAXWM 0x7f /* bit 16:22 */ | |
2882 | #define SNB_DISPLAY_DFTWM 8 | |
2883 | #define SNB_CURSOR_FIFO 32 | |
2884 | #define SNB_CURSOR_MAXWM 0x1f /* bit 4:0 */ | |
2885 | #define SNB_CURSOR_DFTWM 8 | |
2886 | ||
2887 | #define SNB_DISPLAY_SR_FIFO 512 | |
2888 | #define SNB_DISPLAY_MAX_SRWM 0x1ff /* bit 16:8 */ | |
2889 | #define SNB_DISPLAY_DFT_SRWM 0x3f | |
2890 | #define SNB_CURSOR_SR_FIFO 64 | |
2891 | #define SNB_CURSOR_MAX_SRWM 0x3f /* bit 5:0 */ | |
2892 | #define SNB_CURSOR_DFT_SRWM 8 | |
2893 | ||
2894 | #define SNB_FBC_MAX_SRWM 0xf /* bit 23:20 */ | |
2895 | ||
2896 | #define SNB_FIFO_LINE_SIZE 64 | |
2897 | ||
2898 | ||
2899 | /* the address where we get all kinds of latency value */ | |
2900 | #define SSKPD 0x5d10 | |
2901 | #define SSKPD_WM_MASK 0x3f | |
2902 | #define SSKPD_WM0_SHIFT 0 | |
2903 | #define SSKPD_WM1_SHIFT 8 | |
2904 | #define SSKPD_WM2_SHIFT 16 | |
2905 | #define SSKPD_WM3_SHIFT 24 | |
2906 | ||
2907 | #define SNB_LATENCY(shift) (I915_READ(MCHBAR_MIRROR_BASE_SNB + SSKPD) >> (shift) & SSKPD_WM_MASK) | |
2908 | #define SNB_READ_WM0_LATENCY() SNB_LATENCY(SSKPD_WM0_SHIFT) | |
2909 | #define SNB_READ_WM1_LATENCY() SNB_LATENCY(SSKPD_WM1_SHIFT) | |
2910 | #define SNB_READ_WM2_LATENCY() SNB_LATENCY(SSKPD_WM2_SHIFT) | |
2911 | #define SNB_READ_WM3_LATENCY() SNB_LATENCY(SSKPD_WM3_SHIFT) | |
2912 | ||
585fb111 JB |
2913 | /* |
2914 | * The two pipe frame counter registers are not synchronized, so | |
2915 | * reading a stable value is somewhat tricky. The following code | |
2916 | * should work: | |
2917 | * | |
2918 | * do { | |
2919 | * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> | |
2920 | * PIPE_FRAME_HIGH_SHIFT; | |
2921 | * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> | |
2922 | * PIPE_FRAME_LOW_SHIFT); | |
2923 | * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> | |
2924 | * PIPE_FRAME_HIGH_SHIFT); | |
2925 | * } while (high1 != high2); | |
2926 | * frame = (high1 << 8) | low1; | |
2927 | */ | |
0c3870ee | 2928 | #define _PIPEAFRAMEHIGH (dev_priv->info->display_mmio_offset + 0x70040) |
585fb111 JB |
2929 | #define PIPE_FRAME_HIGH_MASK 0x0000ffff |
2930 | #define PIPE_FRAME_HIGH_SHIFT 0 | |
0c3870ee | 2931 | #define _PIPEAFRAMEPIXEL (dev_priv->info->display_mmio_offset + 0x70044) |
585fb111 JB |
2932 | #define PIPE_FRAME_LOW_MASK 0xff000000 |
2933 | #define PIPE_FRAME_LOW_SHIFT 24 | |
2934 | #define PIPE_PIXEL_MASK 0x00ffffff | |
2935 | #define PIPE_PIXEL_SHIFT 0 | |
9880b7a5 | 2936 | /* GM45+ just has to be different */ |
9db4a9c7 JB |
2937 | #define _PIPEA_FRMCOUNT_GM45 0x70040 |
2938 | #define _PIPEA_FLIPCOUNT_GM45 0x70044 | |
2939 | #define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45) | |
585fb111 JB |
2940 | |
2941 | /* Cursor A & B regs */ | |
9dc33f31 | 2942 | #define _CURACNTR (dev_priv->info->display_mmio_offset + 0x70080) |
14b60391 JB |
2943 | /* Old style CUR*CNTR flags (desktop 8xx) */ |
2944 | #define CURSOR_ENABLE 0x80000000 | |
2945 | #define CURSOR_GAMMA_ENABLE 0x40000000 | |
2946 | #define CURSOR_STRIDE_MASK 0x30000000 | |
2947 | #define CURSOR_FORMAT_SHIFT 24 | |
2948 | #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) | |
2949 | #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) | |
2950 | #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) | |
2951 | #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) | |
2952 | #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) | |
2953 | #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) | |
2954 | /* New style CUR*CNTR flags */ | |
2955 | #define CURSOR_MODE 0x27 | |
585fb111 JB |
2956 | #define CURSOR_MODE_DISABLE 0x00 |
2957 | #define CURSOR_MODE_64_32B_AX 0x07 | |
2958 | #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) | |
14b60391 JB |
2959 | #define MCURSOR_PIPE_SELECT (1 << 28) |
2960 | #define MCURSOR_PIPE_A 0x00 | |
2961 | #define MCURSOR_PIPE_B (1 << 28) | |
585fb111 | 2962 | #define MCURSOR_GAMMA_ENABLE (1 << 26) |
9dc33f31 VS |
2963 | #define _CURABASE (dev_priv->info->display_mmio_offset + 0x70084) |
2964 | #define _CURAPOS (dev_priv->info->display_mmio_offset + 0x70088) | |
585fb111 JB |
2965 | #define CURSOR_POS_MASK 0x007FF |
2966 | #define CURSOR_POS_SIGN 0x8000 | |
2967 | #define CURSOR_X_SHIFT 0 | |
2968 | #define CURSOR_Y_SHIFT 16 | |
14b60391 | 2969 | #define CURSIZE 0x700a0 |
9dc33f31 VS |
2970 | #define _CURBCNTR (dev_priv->info->display_mmio_offset + 0x700c0) |
2971 | #define _CURBBASE (dev_priv->info->display_mmio_offset + 0x700c4) | |
2972 | #define _CURBPOS (dev_priv->info->display_mmio_offset + 0x700c8) | |
585fb111 | 2973 | |
65a21cd6 JB |
2974 | #define _CURBCNTR_IVB 0x71080 |
2975 | #define _CURBBASE_IVB 0x71084 | |
2976 | #define _CURBPOS_IVB 0x71088 | |
2977 | ||
9db4a9c7 JB |
2978 | #define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR) |
2979 | #define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE) | |
2980 | #define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS) | |
c4a1d9e4 | 2981 | |
65a21cd6 JB |
2982 | #define CURCNTR_IVB(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR_IVB) |
2983 | #define CURBASE_IVB(pipe) _PIPE(pipe, _CURABASE, _CURBBASE_IVB) | |
2984 | #define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB) | |
2985 | ||
585fb111 | 2986 | /* Display A control */ |
895abf0c | 2987 | #define _DSPACNTR (dev_priv->info->display_mmio_offset + 0x70180) |
585fb111 JB |
2988 | #define DISPLAY_PLANE_ENABLE (1<<31) |
2989 | #define DISPLAY_PLANE_DISABLE 0 | |
2990 | #define DISPPLANE_GAMMA_ENABLE (1<<30) | |
2991 | #define DISPPLANE_GAMMA_DISABLE 0 | |
2992 | #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) | |
57779d06 | 2993 | #define DISPPLANE_YUV422 (0x0<<26) |
585fb111 | 2994 | #define DISPPLANE_8BPP (0x2<<26) |
57779d06 VS |
2995 | #define DISPPLANE_BGRA555 (0x3<<26) |
2996 | #define DISPPLANE_BGRX555 (0x4<<26) | |
2997 | #define DISPPLANE_BGRX565 (0x5<<26) | |
2998 | #define DISPPLANE_BGRX888 (0x6<<26) | |
2999 | #define DISPPLANE_BGRA888 (0x7<<26) | |
3000 | #define DISPPLANE_RGBX101010 (0x8<<26) | |
3001 | #define DISPPLANE_RGBA101010 (0x9<<26) | |
3002 | #define DISPPLANE_BGRX101010 (0xa<<26) | |
3003 | #define DISPPLANE_RGBX161616 (0xc<<26) | |
3004 | #define DISPPLANE_RGBX888 (0xe<<26) | |
3005 | #define DISPPLANE_RGBA888 (0xf<<26) | |
585fb111 JB |
3006 | #define DISPPLANE_STEREO_ENABLE (1<<25) |
3007 | #define DISPPLANE_STEREO_DISABLE 0 | |
b24e7179 JB |
3008 | #define DISPPLANE_SEL_PIPE_SHIFT 24 |
3009 | #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) | |
585fb111 | 3010 | #define DISPPLANE_SEL_PIPE_A 0 |
b24e7179 | 3011 | #define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT) |
585fb111 JB |
3012 | #define DISPPLANE_SRC_KEY_ENABLE (1<<22) |
3013 | #define DISPPLANE_SRC_KEY_DISABLE 0 | |
3014 | #define DISPPLANE_LINE_DOUBLE (1<<20) | |
3015 | #define DISPPLANE_NO_LINE_DOUBLE 0 | |
3016 | #define DISPPLANE_STEREO_POLARITY_FIRST 0 | |
3017 | #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) | |
f2b115e6 | 3018 | #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ |
f544847f | 3019 | #define DISPPLANE_TILED (1<<10) |
895abf0c VS |
3020 | #define _DSPAADDR (dev_priv->info->display_mmio_offset + 0x70184) |
3021 | #define _DSPASTRIDE (dev_priv->info->display_mmio_offset + 0x70188) | |
3022 | #define _DSPAPOS (dev_priv->info->display_mmio_offset + 0x7018C) /* reserved */ | |
3023 | #define _DSPASIZE (dev_priv->info->display_mmio_offset + 0x70190) | |
3024 | #define _DSPASURF (dev_priv->info->display_mmio_offset + 0x7019C) /* 965+ only */ | |
3025 | #define _DSPATILEOFF (dev_priv->info->display_mmio_offset + 0x701A4) /* 965+ only */ | |
3026 | #define _DSPAOFFSET (dev_priv->info->display_mmio_offset + 0x701A4) /* HSW */ | |
3027 | #define _DSPASURFLIVE (dev_priv->info->display_mmio_offset + 0x701AC) | |
9db4a9c7 JB |
3028 | |
3029 | #define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR) | |
3030 | #define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR) | |
3031 | #define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE) | |
3032 | #define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS) | |
3033 | #define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE) | |
3034 | #define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF) | |
3035 | #define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF) | |
e506a0c6 | 3036 | #define DSPLINOFF(plane) DSPADDR(plane) |
bc1c91eb | 3037 | #define DSPOFFSET(plane) _PIPE(plane, _DSPAOFFSET, _DSPBOFFSET) |
32ae46bf | 3038 | #define DSPSURFLIVE(plane) _PIPE(plane, _DSPASURFLIVE, _DSPBSURFLIVE) |
5eddb70b | 3039 | |
446f2545 AR |
3040 | /* Display/Sprite base address macros */ |
3041 | #define DISP_BASEADDR_MASK (0xfffff000) | |
3042 | #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK) | |
3043 | #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK) | |
3044 | #define I915_MODIFY_DISPBASE(reg, gfx_addr) \ | |
c2c75131 | 3045 | (I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg)))) |
446f2545 | 3046 | |
585fb111 JB |
3047 | /* VBIOS flags */ |
3048 | #define SWF00 0x71410 | |
3049 | #define SWF01 0x71414 | |
3050 | #define SWF02 0x71418 | |
3051 | #define SWF03 0x7141c | |
3052 | #define SWF04 0x71420 | |
3053 | #define SWF05 0x71424 | |
3054 | #define SWF06 0x71428 | |
3055 | #define SWF10 0x70410 | |
3056 | #define SWF11 0x70414 | |
3057 | #define SWF14 0x71420 | |
3058 | #define SWF30 0x72414 | |
3059 | #define SWF31 0x72418 | |
3060 | #define SWF32 0x7241c | |
3061 | ||
3062 | /* Pipe B */ | |
0c3870ee VS |
3063 | #define _PIPEBDSL (dev_priv->info->display_mmio_offset + 0x71000) |
3064 | #define _PIPEBCONF (dev_priv->info->display_mmio_offset + 0x71008) | |
3065 | #define _PIPEBSTAT (dev_priv->info->display_mmio_offset + 0x71024) | |
3066 | #define _PIPEBFRAMEHIGH (dev_priv->info->display_mmio_offset + 0x71040) | |
3067 | #define _PIPEBFRAMEPIXEL (dev_priv->info->display_mmio_offset + 0x71044) | |
9db4a9c7 JB |
3068 | #define _PIPEB_FRMCOUNT_GM45 0x71040 |
3069 | #define _PIPEB_FLIPCOUNT_GM45 0x71044 | |
9880b7a5 | 3070 | |
585fb111 JB |
3071 | |
3072 | /* Display B control */ | |
895abf0c | 3073 | #define _DSPBCNTR (dev_priv->info->display_mmio_offset + 0x71180) |
585fb111 JB |
3074 | #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) |
3075 | #define DISPPLANE_ALPHA_TRANS_DISABLE 0 | |
3076 | #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 | |
3077 | #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) | |
895abf0c VS |
3078 | #define _DSPBADDR (dev_priv->info->display_mmio_offset + 0x71184) |
3079 | #define _DSPBSTRIDE (dev_priv->info->display_mmio_offset + 0x71188) | |
3080 | #define _DSPBPOS (dev_priv->info->display_mmio_offset + 0x7118C) | |
3081 | #define _DSPBSIZE (dev_priv->info->display_mmio_offset + 0x71190) | |
3082 | #define _DSPBSURF (dev_priv->info->display_mmio_offset + 0x7119C) | |
3083 | #define _DSPBTILEOFF (dev_priv->info->display_mmio_offset + 0x711A4) | |
3084 | #define _DSPBOFFSET (dev_priv->info->display_mmio_offset + 0x711A4) | |
3085 | #define _DSPBSURFLIVE (dev_priv->info->display_mmio_offset + 0x711AC) | |
585fb111 | 3086 | |
b840d907 JB |
3087 | /* Sprite A control */ |
3088 | #define _DVSACNTR 0x72180 | |
3089 | #define DVS_ENABLE (1<<31) | |
3090 | #define DVS_GAMMA_ENABLE (1<<30) | |
3091 | #define DVS_PIXFORMAT_MASK (3<<25) | |
3092 | #define DVS_FORMAT_YUV422 (0<<25) | |
3093 | #define DVS_FORMAT_RGBX101010 (1<<25) | |
3094 | #define DVS_FORMAT_RGBX888 (2<<25) | |
3095 | #define DVS_FORMAT_RGBX161616 (3<<25) | |
3096 | #define DVS_SOURCE_KEY (1<<22) | |
ab2f9df1 | 3097 | #define DVS_RGB_ORDER_XBGR (1<<20) |
b840d907 JB |
3098 | #define DVS_YUV_BYTE_ORDER_MASK (3<<16) |
3099 | #define DVS_YUV_ORDER_YUYV (0<<16) | |
3100 | #define DVS_YUV_ORDER_UYVY (1<<16) | |
3101 | #define DVS_YUV_ORDER_YVYU (2<<16) | |
3102 | #define DVS_YUV_ORDER_VYUY (3<<16) | |
3103 | #define DVS_DEST_KEY (1<<2) | |
3104 | #define DVS_TRICKLE_FEED_DISABLE (1<<14) | |
3105 | #define DVS_TILED (1<<10) | |
3106 | #define _DVSALINOFF 0x72184 | |
3107 | #define _DVSASTRIDE 0x72188 | |
3108 | #define _DVSAPOS 0x7218c | |
3109 | #define _DVSASIZE 0x72190 | |
3110 | #define _DVSAKEYVAL 0x72194 | |
3111 | #define _DVSAKEYMSK 0x72198 | |
3112 | #define _DVSASURF 0x7219c | |
3113 | #define _DVSAKEYMAXVAL 0x721a0 | |
3114 | #define _DVSATILEOFF 0x721a4 | |
3115 | #define _DVSASURFLIVE 0x721ac | |
3116 | #define _DVSASCALE 0x72204 | |
3117 | #define DVS_SCALE_ENABLE (1<<31) | |
3118 | #define DVS_FILTER_MASK (3<<29) | |
3119 | #define DVS_FILTER_MEDIUM (0<<29) | |
3120 | #define DVS_FILTER_ENHANCING (1<<29) | |
3121 | #define DVS_FILTER_SOFTENING (2<<29) | |
3122 | #define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ | |
3123 | #define DVS_VERTICAL_OFFSET_ENABLE (1<<27) | |
3124 | #define _DVSAGAMC 0x72300 | |
3125 | ||
3126 | #define _DVSBCNTR 0x73180 | |
3127 | #define _DVSBLINOFF 0x73184 | |
3128 | #define _DVSBSTRIDE 0x73188 | |
3129 | #define _DVSBPOS 0x7318c | |
3130 | #define _DVSBSIZE 0x73190 | |
3131 | #define _DVSBKEYVAL 0x73194 | |
3132 | #define _DVSBKEYMSK 0x73198 | |
3133 | #define _DVSBSURF 0x7319c | |
3134 | #define _DVSBKEYMAXVAL 0x731a0 | |
3135 | #define _DVSBTILEOFF 0x731a4 | |
3136 | #define _DVSBSURFLIVE 0x731ac | |
3137 | #define _DVSBSCALE 0x73204 | |
3138 | #define _DVSBGAMC 0x73300 | |
3139 | ||
3140 | #define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR) | |
3141 | #define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) | |
3142 | #define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) | |
3143 | #define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS) | |
3144 | #define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF) | |
8ea30864 | 3145 | #define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) |
b840d907 JB |
3146 | #define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE) |
3147 | #define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE) | |
3148 | #define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) | |
8ea30864 JB |
3149 | #define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) |
3150 | #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) | |
32ae46bf | 3151 | #define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) |
b840d907 JB |
3152 | |
3153 | #define _SPRA_CTL 0x70280 | |
3154 | #define SPRITE_ENABLE (1<<31) | |
3155 | #define SPRITE_GAMMA_ENABLE (1<<30) | |
3156 | #define SPRITE_PIXFORMAT_MASK (7<<25) | |
3157 | #define SPRITE_FORMAT_YUV422 (0<<25) | |
3158 | #define SPRITE_FORMAT_RGBX101010 (1<<25) | |
3159 | #define SPRITE_FORMAT_RGBX888 (2<<25) | |
3160 | #define SPRITE_FORMAT_RGBX161616 (3<<25) | |
3161 | #define SPRITE_FORMAT_YUV444 (4<<25) | |
3162 | #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */ | |
3163 | #define SPRITE_CSC_ENABLE (1<<24) | |
3164 | #define SPRITE_SOURCE_KEY (1<<22) | |
3165 | #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */ | |
3166 | #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19) | |
3167 | #define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */ | |
3168 | #define SPRITE_YUV_BYTE_ORDER_MASK (3<<16) | |
3169 | #define SPRITE_YUV_ORDER_YUYV (0<<16) | |
3170 | #define SPRITE_YUV_ORDER_UYVY (1<<16) | |
3171 | #define SPRITE_YUV_ORDER_YVYU (2<<16) | |
3172 | #define SPRITE_YUV_ORDER_VYUY (3<<16) | |
3173 | #define SPRITE_TRICKLE_FEED_DISABLE (1<<14) | |
3174 | #define SPRITE_INT_GAMMA_ENABLE (1<<13) | |
3175 | #define SPRITE_TILED (1<<10) | |
3176 | #define SPRITE_DEST_KEY (1<<2) | |
3177 | #define _SPRA_LINOFF 0x70284 | |
3178 | #define _SPRA_STRIDE 0x70288 | |
3179 | #define _SPRA_POS 0x7028c | |
3180 | #define _SPRA_SIZE 0x70290 | |
3181 | #define _SPRA_KEYVAL 0x70294 | |
3182 | #define _SPRA_KEYMSK 0x70298 | |
3183 | #define _SPRA_SURF 0x7029c | |
3184 | #define _SPRA_KEYMAX 0x702a0 | |
3185 | #define _SPRA_TILEOFF 0x702a4 | |
c54173a8 | 3186 | #define _SPRA_OFFSET 0x702a4 |
32ae46bf | 3187 | #define _SPRA_SURFLIVE 0x702ac |
b840d907 JB |
3188 | #define _SPRA_SCALE 0x70304 |
3189 | #define SPRITE_SCALE_ENABLE (1<<31) | |
3190 | #define SPRITE_FILTER_MASK (3<<29) | |
3191 | #define SPRITE_FILTER_MEDIUM (0<<29) | |
3192 | #define SPRITE_FILTER_ENHANCING (1<<29) | |
3193 | #define SPRITE_FILTER_SOFTENING (2<<29) | |
3194 | #define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ | |
3195 | #define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27) | |
3196 | #define _SPRA_GAMC 0x70400 | |
3197 | ||
3198 | #define _SPRB_CTL 0x71280 | |
3199 | #define _SPRB_LINOFF 0x71284 | |
3200 | #define _SPRB_STRIDE 0x71288 | |
3201 | #define _SPRB_POS 0x7128c | |
3202 | #define _SPRB_SIZE 0x71290 | |
3203 | #define _SPRB_KEYVAL 0x71294 | |
3204 | #define _SPRB_KEYMSK 0x71298 | |
3205 | #define _SPRB_SURF 0x7129c | |
3206 | #define _SPRB_KEYMAX 0x712a0 | |
3207 | #define _SPRB_TILEOFF 0x712a4 | |
c54173a8 | 3208 | #define _SPRB_OFFSET 0x712a4 |
32ae46bf | 3209 | #define _SPRB_SURFLIVE 0x712ac |
b840d907 JB |
3210 | #define _SPRB_SCALE 0x71304 |
3211 | #define _SPRB_GAMC 0x71400 | |
3212 | ||
3213 | #define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL) | |
3214 | #define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) | |
3215 | #define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) | |
3216 | #define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS) | |
3217 | #define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) | |
3218 | #define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) | |
3219 | #define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) | |
3220 | #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF) | |
3221 | #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) | |
3222 | #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) | |
c54173a8 | 3223 | #define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) |
b840d907 JB |
3224 | #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) |
3225 | #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) | |
32ae46bf | 3226 | #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) |
b840d907 | 3227 | |
585fb111 JB |
3228 | /* VBIOS regs */ |
3229 | #define VGACNTRL 0x71400 | |
3230 | # define VGA_DISP_DISABLE (1 << 31) | |
3231 | # define VGA_2X_MODE (1 << 30) | |
3232 | # define VGA_PIPE_B_SELECT (1 << 29) | |
3233 | ||
f2b115e6 | 3234 | /* Ironlake */ |
b9055052 ZW |
3235 | |
3236 | #define CPU_VGACNTRL 0x41000 | |
3237 | ||
3238 | #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 | |
3239 | #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) | |
3240 | #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) | |
3241 | #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) | |
3242 | #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) | |
3243 | #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) | |
3244 | #define DIGITAL_PORTA_NO_DETECT (0 << 0) | |
3245 | #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) | |
3246 | #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0) | |
3247 | ||
3248 | /* refresh rate hardware control */ | |
3249 | #define RR_HW_CTL 0x45300 | |
3250 | #define RR_HW_LOW_POWER_FRAMES_MASK 0xff | |
3251 | #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 | |
3252 | ||
3253 | #define FDI_PLL_BIOS_0 0x46000 | |
021357ac | 3254 | #define FDI_PLL_FB_CLOCK_MASK 0xff |
b9055052 ZW |
3255 | #define FDI_PLL_BIOS_1 0x46004 |
3256 | #define FDI_PLL_BIOS_2 0x46008 | |
3257 | #define DISPLAY_PORT_PLL_BIOS_0 0x4600c | |
3258 | #define DISPLAY_PORT_PLL_BIOS_1 0x46010 | |
3259 | #define DISPLAY_PORT_PLL_BIOS_2 0x46014 | |
3260 | ||
8956c8bb EA |
3261 | #define PCH_3DCGDIS0 0x46020 |
3262 | # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) | |
3263 | # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) | |
3264 | ||
06f37751 EA |
3265 | #define PCH_3DCGDIS1 0x46024 |
3266 | # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) | |
3267 | ||
b9055052 ZW |
3268 | #define FDI_PLL_FREQ_CTL 0x46030 |
3269 | #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) | |
3270 | #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 | |
3271 | #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff | |
3272 | ||
3273 | ||
aab17139 | 3274 | #define _PIPEA_DATA_M1 (dev_priv->info->display_mmio_offset + 0x60030) |
b9055052 ZW |
3275 | #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ |
3276 | #define TU_SIZE_MASK 0x7e000000 | |
5eddb70b | 3277 | #define PIPE_DATA_M1_OFFSET 0 |
aab17139 | 3278 | #define _PIPEA_DATA_N1 (dev_priv->info->display_mmio_offset + 0x60034) |
5eddb70b | 3279 | #define PIPE_DATA_N1_OFFSET 0 |
b9055052 | 3280 | |
aab17139 | 3281 | #define _PIPEA_DATA_M2 (dev_priv->info->display_mmio_offset + 0x60038) |
5eddb70b | 3282 | #define PIPE_DATA_M2_OFFSET 0 |
aab17139 | 3283 | #define _PIPEA_DATA_N2 (dev_priv->info->display_mmio_offset + 0x6003c) |
5eddb70b | 3284 | #define PIPE_DATA_N2_OFFSET 0 |
b9055052 | 3285 | |
aab17139 | 3286 | #define _PIPEA_LINK_M1 (dev_priv->info->display_mmio_offset + 0x60040) |
5eddb70b | 3287 | #define PIPE_LINK_M1_OFFSET 0 |
aab17139 | 3288 | #define _PIPEA_LINK_N1 (dev_priv->info->display_mmio_offset + 0x60044) |
5eddb70b | 3289 | #define PIPE_LINK_N1_OFFSET 0 |
b9055052 | 3290 | |
aab17139 | 3291 | #define _PIPEA_LINK_M2 (dev_priv->info->display_mmio_offset + 0x60048) |
5eddb70b | 3292 | #define PIPE_LINK_M2_OFFSET 0 |
aab17139 | 3293 | #define _PIPEA_LINK_N2 (dev_priv->info->display_mmio_offset + 0x6004c) |
5eddb70b | 3294 | #define PIPE_LINK_N2_OFFSET 0 |
b9055052 ZW |
3295 | |
3296 | /* PIPEB timing regs are same start from 0x61000 */ | |
3297 | ||
aab17139 VS |
3298 | #define _PIPEB_DATA_M1 (dev_priv->info->display_mmio_offset + 0x61030) |
3299 | #define _PIPEB_DATA_N1 (dev_priv->info->display_mmio_offset + 0x61034) | |
b9055052 | 3300 | |
aab17139 VS |
3301 | #define _PIPEB_DATA_M2 (dev_priv->info->display_mmio_offset + 0x61038) |
3302 | #define _PIPEB_DATA_N2 (dev_priv->info->display_mmio_offset + 0x6103c) | |
b9055052 | 3303 | |
aab17139 VS |
3304 | #define _PIPEB_LINK_M1 (dev_priv->info->display_mmio_offset + 0x61040) |
3305 | #define _PIPEB_LINK_N1 (dev_priv->info->display_mmio_offset + 0x61044) | |
b9055052 | 3306 | |
aab17139 VS |
3307 | #define _PIPEB_LINK_M2 (dev_priv->info->display_mmio_offset + 0x61048) |
3308 | #define _PIPEB_LINK_N2 (dev_priv->info->display_mmio_offset + 0x6104c) | |
5eddb70b | 3309 | |
afe2fcf5 PZ |
3310 | #define PIPE_DATA_M1(tran) _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1) |
3311 | #define PIPE_DATA_N1(tran) _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1) | |
3312 | #define PIPE_DATA_M2(tran) _TRANSCODER(tran, _PIPEA_DATA_M2, _PIPEB_DATA_M2) | |
3313 | #define PIPE_DATA_N2(tran) _TRANSCODER(tran, _PIPEA_DATA_N2, _PIPEB_DATA_N2) | |
3314 | #define PIPE_LINK_M1(tran) _TRANSCODER(tran, _PIPEA_LINK_M1, _PIPEB_LINK_M1) | |
3315 | #define PIPE_LINK_N1(tran) _TRANSCODER(tran, _PIPEA_LINK_N1, _PIPEB_LINK_N1) | |
3316 | #define PIPE_LINK_M2(tran) _TRANSCODER(tran, _PIPEA_LINK_M2, _PIPEB_LINK_M2) | |
3317 | #define PIPE_LINK_N2(tran) _TRANSCODER(tran, _PIPEA_LINK_N2, _PIPEB_LINK_N2) | |
b9055052 ZW |
3318 | |
3319 | /* CPU panel fitter */ | |
9db4a9c7 JB |
3320 | /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ |
3321 | #define _PFA_CTL_1 0x68080 | |
3322 | #define _PFB_CTL_1 0x68880 | |
b9055052 | 3323 | #define PF_ENABLE (1<<31) |
13888d78 PZ |
3324 | #define PF_PIPE_SEL_MASK_IVB (3<<29) |
3325 | #define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29) | |
b1f60b70 ZW |
3326 | #define PF_FILTER_MASK (3<<23) |
3327 | #define PF_FILTER_PROGRAMMED (0<<23) | |
3328 | #define PF_FILTER_MED_3x3 (1<<23) | |
3329 | #define PF_FILTER_EDGE_ENHANCE (2<<23) | |
3330 | #define PF_FILTER_EDGE_SOFTEN (3<<23) | |
9db4a9c7 JB |
3331 | #define _PFA_WIN_SZ 0x68074 |
3332 | #define _PFB_WIN_SZ 0x68874 | |
3333 | #define _PFA_WIN_POS 0x68070 | |
3334 | #define _PFB_WIN_POS 0x68870 | |
3335 | #define _PFA_VSCALE 0x68084 | |
3336 | #define _PFB_VSCALE 0x68884 | |
3337 | #define _PFA_HSCALE 0x68090 | |
3338 | #define _PFB_HSCALE 0x68890 | |
3339 | ||
3340 | #define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) | |
3341 | #define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) | |
3342 | #define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) | |
3343 | #define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) | |
3344 | #define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) | |
b9055052 ZW |
3345 | |
3346 | /* legacy palette */ | |
9db4a9c7 JB |
3347 | #define _LGC_PALETTE_A 0x4a000 |
3348 | #define _LGC_PALETTE_B 0x4a800 | |
3349 | #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) | |
b9055052 ZW |
3350 | |
3351 | /* interrupts */ | |
3352 | #define DE_MASTER_IRQ_CONTROL (1 << 31) | |
3353 | #define DE_SPRITEB_FLIP_DONE (1 << 29) | |
3354 | #define DE_SPRITEA_FLIP_DONE (1 << 28) | |
3355 | #define DE_PLANEB_FLIP_DONE (1 << 27) | |
3356 | #define DE_PLANEA_FLIP_DONE (1 << 26) | |
3357 | #define DE_PCU_EVENT (1 << 25) | |
3358 | #define DE_GTT_FAULT (1 << 24) | |
3359 | #define DE_POISON (1 << 23) | |
3360 | #define DE_PERFORM_COUNTER (1 << 22) | |
3361 | #define DE_PCH_EVENT (1 << 21) | |
3362 | #define DE_AUX_CHANNEL_A (1 << 20) | |
3363 | #define DE_DP_A_HOTPLUG (1 << 19) | |
3364 | #define DE_GSE (1 << 18) | |
3365 | #define DE_PIPEB_VBLANK (1 << 15) | |
3366 | #define DE_PIPEB_EVEN_FIELD (1 << 14) | |
3367 | #define DE_PIPEB_ODD_FIELD (1 << 13) | |
3368 | #define DE_PIPEB_LINE_COMPARE (1 << 12) | |
3369 | #define DE_PIPEB_VSYNC (1 << 11) | |
3370 | #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) | |
3371 | #define DE_PIPEA_VBLANK (1 << 7) | |
3372 | #define DE_PIPEA_EVEN_FIELD (1 << 6) | |
3373 | #define DE_PIPEA_ODD_FIELD (1 << 5) | |
3374 | #define DE_PIPEA_LINE_COMPARE (1 << 4) | |
3375 | #define DE_PIPEA_VSYNC (1 << 3) | |
3376 | #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) | |
3377 | ||
b1f14ad0 JB |
3378 | /* More Ivybridge lolz */ |
3379 | #define DE_ERR_DEBUG_IVB (1<<30) | |
3380 | #define DE_GSE_IVB (1<<29) | |
3381 | #define DE_PCH_EVENT_IVB (1<<28) | |
3382 | #define DE_DP_A_HOTPLUG_IVB (1<<27) | |
3383 | #define DE_AUX_CHANNEL_A_IVB (1<<26) | |
b615b57a CW |
3384 | #define DE_SPRITEC_FLIP_DONE_IVB (1<<14) |
3385 | #define DE_PLANEC_FLIP_DONE_IVB (1<<13) | |
3386 | #define DE_PIPEC_VBLANK_IVB (1<<10) | |
b1f14ad0 | 3387 | #define DE_SPRITEB_FLIP_DONE_IVB (1<<9) |
b1f14ad0 | 3388 | #define DE_PLANEB_FLIP_DONE_IVB (1<<8) |
b1f14ad0 | 3389 | #define DE_PIPEB_VBLANK_IVB (1<<5) |
b615b57a CW |
3390 | #define DE_SPRITEA_FLIP_DONE_IVB (1<<4) |
3391 | #define DE_PLANEA_FLIP_DONE_IVB (1<<3) | |
b1f14ad0 JB |
3392 | #define DE_PIPEA_VBLANK_IVB (1<<0) |
3393 | ||
7eea1ddf JB |
3394 | #define VLV_MASTER_IER 0x4400c /* Gunit master IER */ |
3395 | #define MASTER_INTERRUPT_ENABLE (1<<31) | |
3396 | ||
b9055052 ZW |
3397 | #define DEISR 0x44000 |
3398 | #define DEIMR 0x44004 | |
3399 | #define DEIIR 0x44008 | |
3400 | #define DEIER 0x4400c | |
3401 | ||
e2a1e2f0 BW |
3402 | /* GT interrupt. |
3403 | * Note that for gen6+ the ring-specific interrupt bits do alias with the | |
3404 | * corresponding bits in the per-ring interrupt control registers. */ | |
7eea1ddf JB |
3405 | #define GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) |
3406 | #define GT_GEN6_BLT_CS_ERROR_INTERRUPT (1 << 25) | |
e2a1e2f0 | 3407 | #define GT_GEN6_BLT_USER_INTERRUPT (1 << 22) |
7eea1ddf JB |
3408 | #define GT_GEN6_BSD_CS_ERROR_INTERRUPT (1 << 15) |
3409 | #define GT_GEN6_BSD_USER_INTERRUPT (1 << 12) | |
e2a1e2f0 | 3410 | #define GT_BSD_USER_INTERRUPT (1 << 5) /* ilk only */ |
7eea1ddf JB |
3411 | #define GT_GEN7_L3_PARITY_ERROR_INTERRUPT (1 << 5) |
3412 | #define GT_PIPE_NOTIFY (1 << 4) | |
3413 | #define GT_RENDER_CS_ERROR_INTERRUPT (1 << 3) | |
3414 | #define GT_SYNC_STATUS (1 << 2) | |
3415 | #define GT_USER_INTERRUPT (1 << 0) | |
b9055052 ZW |
3416 | |
3417 | #define GTISR 0x44010 | |
3418 | #define GTIMR 0x44014 | |
3419 | #define GTIIR 0x44018 | |
3420 | #define GTIER 0x4401c | |
3421 | ||
7f8a8569 | 3422 | #define ILK_DISPLAY_CHICKEN2 0x42004 |
67e92af0 EA |
3423 | /* Required on all Ironlake and Sandybridge according to the B-Spec. */ |
3424 | #define ILK_ELPIN_409_SELECT (1 << 25) | |
7f8a8569 ZW |
3425 | #define ILK_DPARB_GATE (1<<22) |
3426 | #define ILK_VSDPFD_FULL (1<<21) | |
4d302442 CW |
3427 | #define ILK_DISPLAY_CHICKEN_FUSES 0x42014 |
3428 | #define ILK_INTERNAL_GRAPHICS_DISABLE (1<<31) | |
3429 | #define ILK_INTERNAL_DISPLAY_DISABLE (1<<30) | |
3430 | #define ILK_DISPLAY_DEBUG_DISABLE (1<<29) | |
3431 | #define ILK_HDCP_DISABLE (1<<25) | |
3432 | #define ILK_eDP_A_DISABLE (1<<24) | |
3433 | #define ILK_DESKTOP (1<<23) | |
231e54f6 DL |
3434 | |
3435 | #define ILK_DSPCLK_GATE_D 0x42020 | |
3436 | #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) | |
3437 | #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) | |
3438 | #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) | |
3439 | #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7) | |
3440 | #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5) | |
7f8a8569 | 3441 | |
116ac8d2 EA |
3442 | #define IVB_CHICKEN3 0x4200c |
3443 | # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) | |
3444 | # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) | |
3445 | ||
553bd149 ZW |
3446 | #define DISP_ARB_CTL 0x45000 |
3447 | #define DISP_TILE_SURFACE_SWIZZLING (1<<13) | |
7f8a8569 | 3448 | #define DISP_FBC_WM_DIS (1<<15) |
553bd149 | 3449 | |
e4e0c058 | 3450 | /* GEN7 chicken */ |
d71de14d KG |
3451 | #define GEN7_COMMON_SLICE_CHICKEN1 0x7010 |
3452 | # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) | |
3453 | ||
e4e0c058 ED |
3454 | #define GEN7_L3CNTLREG1 0xB01C |
3455 | #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C | |
d0cf5ead | 3456 | #define GEN7_L3AGDIS (1<<19) |
e4e0c058 ED |
3457 | |
3458 | #define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030 | |
3459 | #define GEN7_WA_L3_CHICKEN_MODE 0x20000000 | |
3460 | ||
61939d97 JB |
3461 | #define GEN7_L3SQCREG4 0xb034 |
3462 | #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27) | |
3463 | ||
db099c8f ED |
3464 | /* WaCatErrorRejectionIssue */ |
3465 | #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 | |
3466 | #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) | |
3467 | ||
79f689aa PZ |
3468 | #define HSW_FUSE_STRAP 0x42014 |
3469 | #define HSW_CDCLK_LIMIT (1 << 24) | |
3470 | ||
b9055052 ZW |
3471 | /* PCH */ |
3472 | ||
23e81d69 | 3473 | /* south display engine interrupt: IBX */ |
776ad806 JB |
3474 | #define SDE_AUDIO_POWER_D (1 << 27) |
3475 | #define SDE_AUDIO_POWER_C (1 << 26) | |
3476 | #define SDE_AUDIO_POWER_B (1 << 25) | |
3477 | #define SDE_AUDIO_POWER_SHIFT (25) | |
3478 | #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) | |
3479 | #define SDE_GMBUS (1 << 24) | |
3480 | #define SDE_AUDIO_HDCP_TRANSB (1 << 23) | |
3481 | #define SDE_AUDIO_HDCP_TRANSA (1 << 22) | |
3482 | #define SDE_AUDIO_HDCP_MASK (3 << 22) | |
3483 | #define SDE_AUDIO_TRANSB (1 << 21) | |
3484 | #define SDE_AUDIO_TRANSA (1 << 20) | |
3485 | #define SDE_AUDIO_TRANS_MASK (3 << 20) | |
3486 | #define SDE_POISON (1 << 19) | |
3487 | /* 18 reserved */ | |
3488 | #define SDE_FDI_RXB (1 << 17) | |
3489 | #define SDE_FDI_RXA (1 << 16) | |
3490 | #define SDE_FDI_MASK (3 << 16) | |
3491 | #define SDE_AUXD (1 << 15) | |
3492 | #define SDE_AUXC (1 << 14) | |
3493 | #define SDE_AUXB (1 << 13) | |
3494 | #define SDE_AUX_MASK (7 << 13) | |
3495 | /* 12 reserved */ | |
b9055052 ZW |
3496 | #define SDE_CRT_HOTPLUG (1 << 11) |
3497 | #define SDE_PORTD_HOTPLUG (1 << 10) | |
3498 | #define SDE_PORTC_HOTPLUG (1 << 9) | |
3499 | #define SDE_PORTB_HOTPLUG (1 << 8) | |
3500 | #define SDE_SDVOB_HOTPLUG (1 << 6) | |
c650156a | 3501 | #define SDE_HOTPLUG_MASK (0xf << 8) |
776ad806 JB |
3502 | #define SDE_TRANSB_CRC_DONE (1 << 5) |
3503 | #define SDE_TRANSB_CRC_ERR (1 << 4) | |
3504 | #define SDE_TRANSB_FIFO_UNDER (1 << 3) | |
3505 | #define SDE_TRANSA_CRC_DONE (1 << 2) | |
3506 | #define SDE_TRANSA_CRC_ERR (1 << 1) | |
3507 | #define SDE_TRANSA_FIFO_UNDER (1 << 0) | |
3508 | #define SDE_TRANS_MASK (0x3f) | |
23e81d69 AJ |
3509 | |
3510 | /* south display engine interrupt: CPT/PPT */ | |
3511 | #define SDE_AUDIO_POWER_D_CPT (1 << 31) | |
3512 | #define SDE_AUDIO_POWER_C_CPT (1 << 30) | |
3513 | #define SDE_AUDIO_POWER_B_CPT (1 << 29) | |
3514 | #define SDE_AUDIO_POWER_SHIFT_CPT 29 | |
3515 | #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) | |
3516 | #define SDE_AUXD_CPT (1 << 27) | |
3517 | #define SDE_AUXC_CPT (1 << 26) | |
3518 | #define SDE_AUXB_CPT (1 << 25) | |
3519 | #define SDE_AUX_MASK_CPT (7 << 25) | |
8db9d77b ZW |
3520 | #define SDE_PORTD_HOTPLUG_CPT (1 << 23) |
3521 | #define SDE_PORTC_HOTPLUG_CPT (1 << 22) | |
3522 | #define SDE_PORTB_HOTPLUG_CPT (1 << 21) | |
23e81d69 | 3523 | #define SDE_CRT_HOTPLUG_CPT (1 << 19) |
2d7b8366 YL |
3524 | #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ |
3525 | SDE_PORTD_HOTPLUG_CPT | \ | |
3526 | SDE_PORTC_HOTPLUG_CPT | \ | |
3527 | SDE_PORTB_HOTPLUG_CPT) | |
23e81d69 AJ |
3528 | #define SDE_GMBUS_CPT (1 << 17) |
3529 | #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) | |
3530 | #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) | |
3531 | #define SDE_FDI_RXC_CPT (1 << 8) | |
3532 | #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) | |
3533 | #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) | |
3534 | #define SDE_FDI_RXB_CPT (1 << 4) | |
3535 | #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) | |
3536 | #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) | |
3537 | #define SDE_FDI_RXA_CPT (1 << 0) | |
3538 | #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ | |
3539 | SDE_AUDIO_CP_REQ_B_CPT | \ | |
3540 | SDE_AUDIO_CP_REQ_A_CPT) | |
3541 | #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ | |
3542 | SDE_AUDIO_CP_CHG_B_CPT | \ | |
3543 | SDE_AUDIO_CP_CHG_A_CPT) | |
3544 | #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ | |
3545 | SDE_FDI_RXB_CPT | \ | |
3546 | SDE_FDI_RXA_CPT) | |
b9055052 ZW |
3547 | |
3548 | #define SDEISR 0xc4000 | |
3549 | #define SDEIMR 0xc4004 | |
3550 | #define SDEIIR 0xc4008 | |
3551 | #define SDEIER 0xc400c | |
3552 | ||
3553 | /* digital port hotplug */ | |
7fe0b973 | 3554 | #define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */ |
b9055052 ZW |
3555 | #define PORTD_HOTPLUG_ENABLE (1 << 20) |
3556 | #define PORTD_PULSE_DURATION_2ms (0) | |
3557 | #define PORTD_PULSE_DURATION_4_5ms (1 << 18) | |
3558 | #define PORTD_PULSE_DURATION_6ms (2 << 18) | |
3559 | #define PORTD_PULSE_DURATION_100ms (3 << 18) | |
7fe0b973 | 3560 | #define PORTD_PULSE_DURATION_MASK (3 << 18) |
b696519e DL |
3561 | #define PORTD_HOTPLUG_STATUS_MASK (0x3 << 16) |
3562 | #define PORTD_HOTPLUG_NO_DETECT (0 << 16) | |
3563 | #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) | |
3564 | #define PORTD_HOTPLUG_LONG_DETECT (2 << 16) | |
b9055052 ZW |
3565 | #define PORTC_HOTPLUG_ENABLE (1 << 12) |
3566 | #define PORTC_PULSE_DURATION_2ms (0) | |
3567 | #define PORTC_PULSE_DURATION_4_5ms (1 << 10) | |
3568 | #define PORTC_PULSE_DURATION_6ms (2 << 10) | |
3569 | #define PORTC_PULSE_DURATION_100ms (3 << 10) | |
7fe0b973 | 3570 | #define PORTC_PULSE_DURATION_MASK (3 << 10) |
b696519e DL |
3571 | #define PORTC_HOTPLUG_STATUS_MASK (0x3 << 8) |
3572 | #define PORTC_HOTPLUG_NO_DETECT (0 << 8) | |
3573 | #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) | |
3574 | #define PORTC_HOTPLUG_LONG_DETECT (2 << 8) | |
b9055052 ZW |
3575 | #define PORTB_HOTPLUG_ENABLE (1 << 4) |
3576 | #define PORTB_PULSE_DURATION_2ms (0) | |
3577 | #define PORTB_PULSE_DURATION_4_5ms (1 << 2) | |
3578 | #define PORTB_PULSE_DURATION_6ms (2 << 2) | |
3579 | #define PORTB_PULSE_DURATION_100ms (3 << 2) | |
7fe0b973 | 3580 | #define PORTB_PULSE_DURATION_MASK (3 << 2) |
b696519e DL |
3581 | #define PORTB_HOTPLUG_STATUS_MASK (0x3 << 0) |
3582 | #define PORTB_HOTPLUG_NO_DETECT (0 << 0) | |
3583 | #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) | |
3584 | #define PORTB_HOTPLUG_LONG_DETECT (2 << 0) | |
b9055052 ZW |
3585 | |
3586 | #define PCH_GPIOA 0xc5010 | |
3587 | #define PCH_GPIOB 0xc5014 | |
3588 | #define PCH_GPIOC 0xc5018 | |
3589 | #define PCH_GPIOD 0xc501c | |
3590 | #define PCH_GPIOE 0xc5020 | |
3591 | #define PCH_GPIOF 0xc5024 | |
3592 | ||
f0217c42 EA |
3593 | #define PCH_GMBUS0 0xc5100 |
3594 | #define PCH_GMBUS1 0xc5104 | |
3595 | #define PCH_GMBUS2 0xc5108 | |
3596 | #define PCH_GMBUS3 0xc510c | |
3597 | #define PCH_GMBUS4 0xc5110 | |
3598 | #define PCH_GMBUS5 0xc5120 | |
3599 | ||
9db4a9c7 JB |
3600 | #define _PCH_DPLL_A 0xc6014 |
3601 | #define _PCH_DPLL_B 0xc6018 | |
ee7b9f93 | 3602 | #define _PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) |
b9055052 | 3603 | |
9db4a9c7 | 3604 | #define _PCH_FPA0 0xc6040 |
c1858123 | 3605 | #define FP_CB_TUNE (0x3<<22) |
9db4a9c7 JB |
3606 | #define _PCH_FPA1 0xc6044 |
3607 | #define _PCH_FPB0 0xc6048 | |
3608 | #define _PCH_FPB1 0xc604c | |
ee7b9f93 JB |
3609 | #define _PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0) |
3610 | #define _PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1) | |
b9055052 ZW |
3611 | |
3612 | #define PCH_DPLL_TEST 0xc606c | |
3613 | ||
3614 | #define PCH_DREF_CONTROL 0xC6200 | |
3615 | #define DREF_CONTROL_MASK 0x7fc3 | |
3616 | #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) | |
3617 | #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) | |
3618 | #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) | |
3619 | #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) | |
3620 | #define DREF_SSC_SOURCE_DISABLE (0<<11) | |
3621 | #define DREF_SSC_SOURCE_ENABLE (2<<11) | |
c038e51e | 3622 | #define DREF_SSC_SOURCE_MASK (3<<11) |
b9055052 ZW |
3623 | #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) |
3624 | #define DREF_NONSPREAD_CK505_ENABLE (1<<9) | |
3625 | #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) | |
c038e51e | 3626 | #define DREF_NONSPREAD_SOURCE_MASK (3<<9) |
b9055052 ZW |
3627 | #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) |
3628 | #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) | |
92f2584a | 3629 | #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7) |
b9055052 ZW |
3630 | #define DREF_SSC4_DOWNSPREAD (0<<6) |
3631 | #define DREF_SSC4_CENTERSPREAD (1<<6) | |
3632 | #define DREF_SSC1_DISABLE (0<<1) | |
3633 | #define DREF_SSC1_ENABLE (1<<1) | |
3634 | #define DREF_SSC4_DISABLE (0) | |
3635 | #define DREF_SSC4_ENABLE (1) | |
3636 | ||
3637 | #define PCH_RAWCLK_FREQ 0xc6204 | |
3638 | #define FDL_TP1_TIMER_SHIFT 12 | |
3639 | #define FDL_TP1_TIMER_MASK (3<<12) | |
3640 | #define FDL_TP2_TIMER_SHIFT 10 | |
3641 | #define FDL_TP2_TIMER_MASK (3<<10) | |
3642 | #define RAWCLK_FREQ_MASK 0x3ff | |
3643 | ||
3644 | #define PCH_DPLL_TMR_CFG 0xc6208 | |
3645 | ||
3646 | #define PCH_SSC4_PARMS 0xc6210 | |
3647 | #define PCH_SSC4_AUX_PARMS 0xc6214 | |
3648 | ||
8db9d77b ZW |
3649 | #define PCH_DPLL_SEL 0xc7000 |
3650 | #define TRANSA_DPLL_ENABLE (1<<3) | |
3651 | #define TRANSA_DPLLB_SEL (1<<0) | |
3652 | #define TRANSA_DPLLA_SEL 0 | |
3653 | #define TRANSB_DPLL_ENABLE (1<<7) | |
3654 | #define TRANSB_DPLLB_SEL (1<<4) | |
3655 | #define TRANSB_DPLLA_SEL (0) | |
3656 | #define TRANSC_DPLL_ENABLE (1<<11) | |
3657 | #define TRANSC_DPLLB_SEL (1<<8) | |
3658 | #define TRANSC_DPLLA_SEL (0) | |
3659 | ||
b9055052 ZW |
3660 | /* transcoder */ |
3661 | ||
9db4a9c7 | 3662 | #define _TRANS_HTOTAL_A 0xe0000 |
b9055052 ZW |
3663 | #define TRANS_HTOTAL_SHIFT 16 |
3664 | #define TRANS_HACTIVE_SHIFT 0 | |
9db4a9c7 | 3665 | #define _TRANS_HBLANK_A 0xe0004 |
b9055052 ZW |
3666 | #define TRANS_HBLANK_END_SHIFT 16 |
3667 | #define TRANS_HBLANK_START_SHIFT 0 | |
9db4a9c7 | 3668 | #define _TRANS_HSYNC_A 0xe0008 |
b9055052 ZW |
3669 | #define TRANS_HSYNC_END_SHIFT 16 |
3670 | #define TRANS_HSYNC_START_SHIFT 0 | |
9db4a9c7 | 3671 | #define _TRANS_VTOTAL_A 0xe000c |
b9055052 ZW |
3672 | #define TRANS_VTOTAL_SHIFT 16 |
3673 | #define TRANS_VACTIVE_SHIFT 0 | |
9db4a9c7 | 3674 | #define _TRANS_VBLANK_A 0xe0010 |
b9055052 ZW |
3675 | #define TRANS_VBLANK_END_SHIFT 16 |
3676 | #define TRANS_VBLANK_START_SHIFT 0 | |
9db4a9c7 | 3677 | #define _TRANS_VSYNC_A 0xe0014 |
b9055052 ZW |
3678 | #define TRANS_VSYNC_END_SHIFT 16 |
3679 | #define TRANS_VSYNC_START_SHIFT 0 | |
0529a0d9 | 3680 | #define _TRANS_VSYNCSHIFT_A 0xe0028 |
b9055052 | 3681 | |
9db4a9c7 JB |
3682 | #define _TRANSA_DATA_M1 0xe0030 |
3683 | #define _TRANSA_DATA_N1 0xe0034 | |
3684 | #define _TRANSA_DATA_M2 0xe0038 | |
3685 | #define _TRANSA_DATA_N2 0xe003c | |
3686 | #define _TRANSA_DP_LINK_M1 0xe0040 | |
3687 | #define _TRANSA_DP_LINK_N1 0xe0044 | |
3688 | #define _TRANSA_DP_LINK_M2 0xe0048 | |
3689 | #define _TRANSA_DP_LINK_N2 0xe004c | |
3690 | ||
b055c8f3 JB |
3691 | /* Per-transcoder DIP controls */ |
3692 | ||
3693 | #define _VIDEO_DIP_CTL_A 0xe0200 | |
3694 | #define _VIDEO_DIP_DATA_A 0xe0208 | |
3695 | #define _VIDEO_DIP_GCP_A 0xe0210 | |
3696 | ||
3697 | #define _VIDEO_DIP_CTL_B 0xe1200 | |
3698 | #define _VIDEO_DIP_DATA_B 0xe1208 | |
3699 | #define _VIDEO_DIP_GCP_B 0xe1210 | |
3700 | ||
3701 | #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) | |
3702 | #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) | |
3703 | #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) | |
3704 | ||
b906487c VS |
3705 | #define VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200) |
3706 | #define VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208) | |
3707 | #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210) | |
90b107c8 | 3708 | |
b906487c VS |
3709 | #define VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170) |
3710 | #define VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174) | |
3711 | #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178) | |
90b107c8 SK |
3712 | |
3713 | #define VLV_TVIDEO_DIP_CTL(pipe) \ | |
3714 | _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B) | |
3715 | #define VLV_TVIDEO_DIP_DATA(pipe) \ | |
3716 | _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B) | |
3717 | #define VLV_TVIDEO_DIP_GCP(pipe) \ | |
3718 | _PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B) | |
3719 | ||
8c5f5f7c ED |
3720 | /* Haswell DIP controls */ |
3721 | #define HSW_VIDEO_DIP_CTL_A 0x60200 | |
3722 | #define HSW_VIDEO_DIP_AVI_DATA_A 0x60220 | |
3723 | #define HSW_VIDEO_DIP_VS_DATA_A 0x60260 | |
3724 | #define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 | |
3725 | #define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 | |
3726 | #define HSW_VIDEO_DIP_VSC_DATA_A 0x60320 | |
3727 | #define HSW_VIDEO_DIP_AVI_ECC_A 0x60240 | |
3728 | #define HSW_VIDEO_DIP_VS_ECC_A 0x60280 | |
3729 | #define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 | |
3730 | #define HSW_VIDEO_DIP_GMP_ECC_A 0x60300 | |
3731 | #define HSW_VIDEO_DIP_VSC_ECC_A 0x60344 | |
3732 | #define HSW_VIDEO_DIP_GCP_A 0x60210 | |
3733 | ||
3734 | #define HSW_VIDEO_DIP_CTL_B 0x61200 | |
3735 | #define HSW_VIDEO_DIP_AVI_DATA_B 0x61220 | |
3736 | #define HSW_VIDEO_DIP_VS_DATA_B 0x61260 | |
3737 | #define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 | |
3738 | #define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 | |
3739 | #define HSW_VIDEO_DIP_VSC_DATA_B 0x61320 | |
3740 | #define HSW_VIDEO_DIP_BVI_ECC_B 0x61240 | |
3741 | #define HSW_VIDEO_DIP_VS_ECC_B 0x61280 | |
3742 | #define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 | |
3743 | #define HSW_VIDEO_DIP_GMP_ECC_B 0x61300 | |
3744 | #define HSW_VIDEO_DIP_VSC_ECC_B 0x61344 | |
3745 | #define HSW_VIDEO_DIP_GCP_B 0x61210 | |
3746 | ||
3747 | #define HSW_TVIDEO_DIP_CTL(pipe) \ | |
3748 | _PIPE(pipe, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B) | |
3749 | #define HSW_TVIDEO_DIP_AVI_DATA(pipe) \ | |
3750 | _PIPE(pipe, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B) | |
3751 | #define HSW_TVIDEO_DIP_SPD_DATA(pipe) \ | |
3752 | _PIPE(pipe, HSW_VIDEO_DIP_SPD_DATA_A, HSW_VIDEO_DIP_SPD_DATA_B) | |
3753 | #define HSW_TVIDEO_DIP_GCP(pipe) \ | |
3754 | _PIPE(pipe, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B) | |
3755 | ||
9db4a9c7 JB |
3756 | #define _TRANS_HTOTAL_B 0xe1000 |
3757 | #define _TRANS_HBLANK_B 0xe1004 | |
3758 | #define _TRANS_HSYNC_B 0xe1008 | |
3759 | #define _TRANS_VTOTAL_B 0xe100c | |
3760 | #define _TRANS_VBLANK_B 0xe1010 | |
3761 | #define _TRANS_VSYNC_B 0xe1014 | |
0529a0d9 | 3762 | #define _TRANS_VSYNCSHIFT_B 0xe1028 |
9db4a9c7 JB |
3763 | |
3764 | #define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B) | |
3765 | #define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B) | |
3766 | #define TRANS_HSYNC(pipe) _PIPE(pipe, _TRANS_HSYNC_A, _TRANS_HSYNC_B) | |
3767 | #define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B) | |
3768 | #define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B) | |
3769 | #define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B) | |
0529a0d9 DV |
3770 | #define TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _TRANS_VSYNCSHIFT_A, \ |
3771 | _TRANS_VSYNCSHIFT_B) | |
9db4a9c7 JB |
3772 | |
3773 | #define _TRANSB_DATA_M1 0xe1030 | |
3774 | #define _TRANSB_DATA_N1 0xe1034 | |
3775 | #define _TRANSB_DATA_M2 0xe1038 | |
3776 | #define _TRANSB_DATA_N2 0xe103c | |
3777 | #define _TRANSB_DP_LINK_M1 0xe1040 | |
3778 | #define _TRANSB_DP_LINK_N1 0xe1044 | |
3779 | #define _TRANSB_DP_LINK_M2 0xe1048 | |
3780 | #define _TRANSB_DP_LINK_N2 0xe104c | |
3781 | ||
3782 | #define TRANSDATA_M1(pipe) _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1) | |
3783 | #define TRANSDATA_N1(pipe) _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1) | |
3784 | #define TRANSDATA_M2(pipe) _PIPE(pipe, _TRANSA_DATA_M2, _TRANSB_DATA_M2) | |
3785 | #define TRANSDATA_N2(pipe) _PIPE(pipe, _TRANSA_DATA_N2, _TRANSB_DATA_N2) | |
3786 | #define TRANSDPLINK_M1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M1, _TRANSB_DP_LINK_M1) | |
3787 | #define TRANSDPLINK_N1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N1, _TRANSB_DP_LINK_N1) | |
3788 | #define TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2) | |
3789 | #define TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2) | |
3790 | ||
3791 | #define _TRANSACONF 0xf0008 | |
3792 | #define _TRANSBCONF 0xf1008 | |
3793 | #define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF) | |
b9055052 ZW |
3794 | #define TRANS_DISABLE (0<<31) |
3795 | #define TRANS_ENABLE (1<<31) | |
3796 | #define TRANS_STATE_MASK (1<<30) | |
3797 | #define TRANS_STATE_DISABLE (0<<30) | |
3798 | #define TRANS_STATE_ENABLE (1<<30) | |
3799 | #define TRANS_FSYNC_DELAY_HB1 (0<<27) | |
3800 | #define TRANS_FSYNC_DELAY_HB2 (1<<27) | |
3801 | #define TRANS_FSYNC_DELAY_HB3 (2<<27) | |
3802 | #define TRANS_FSYNC_DELAY_HB4 (3<<27) | |
5f7f726d | 3803 | #define TRANS_INTERLACE_MASK (7<<21) |
b9055052 | 3804 | #define TRANS_PROGRESSIVE (0<<21) |
5f7f726d | 3805 | #define TRANS_INTERLACED (3<<21) |
7c26e5c6 | 3806 | #define TRANS_LEGACY_INTERLACED_ILK (2<<21) |
b9055052 ZW |
3807 | #define TRANS_8BPC (0<<5) |
3808 | #define TRANS_10BPC (1<<5) | |
3809 | #define TRANS_6BPC (2<<5) | |
3810 | #define TRANS_12BPC (3<<5) | |
3811 | ||
ce40141f DV |
3812 | #define _TRANSA_CHICKEN1 0xf0060 |
3813 | #define _TRANSB_CHICKEN1 0xf1060 | |
3814 | #define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) | |
3815 | #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4) | |
3bcf603f JB |
3816 | #define _TRANSA_CHICKEN2 0xf0064 |
3817 | #define _TRANSB_CHICKEN2 0xf1064 | |
3818 | #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) | |
23670b32 DV |
3819 | #define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31) |
3820 | ||
3bcf603f | 3821 | |
291427f5 JB |
3822 | #define SOUTH_CHICKEN1 0xc2000 |
3823 | #define FDIA_PHASE_SYNC_SHIFT_OVR 19 | |
3824 | #define FDIA_PHASE_SYNC_SHIFT_EN 18 | |
01a415fd DV |
3825 | #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) |
3826 | #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) | |
3827 | #define FDI_BC_BIFURCATION_SELECT (1 << 12) | |
645c62a5 | 3828 | #define SOUTH_CHICKEN2 0xc2004 |
dde86e2d PZ |
3829 | #define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13) |
3830 | #define FDI_MPHY_IOSFSB_RESET_CTL (1<<12) | |
3831 | #define DPLS_EDP_PPS_FIX_DIS (1<<0) | |
645c62a5 | 3832 | |
9db4a9c7 JB |
3833 | #define _FDI_RXA_CHICKEN 0xc200c |
3834 | #define _FDI_RXB_CHICKEN 0xc2010 | |
6f06ce18 JB |
3835 | #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1) |
3836 | #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0) | |
9db4a9c7 | 3837 | #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) |
b9055052 | 3838 | |
382b0936 JB |
3839 | #define SOUTH_DSPCLK_GATE_D 0xc2020 |
3840 | #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) | |
17a303ec | 3841 | #define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12) |
382b0936 | 3842 | |
b9055052 | 3843 | /* CPU: FDI_TX */ |
9db4a9c7 JB |
3844 | #define _FDI_TXA_CTL 0x60100 |
3845 | #define _FDI_TXB_CTL 0x61100 | |
3846 | #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) | |
b9055052 ZW |
3847 | #define FDI_TX_DISABLE (0<<31) |
3848 | #define FDI_TX_ENABLE (1<<31) | |
3849 | #define FDI_LINK_TRAIN_PATTERN_1 (0<<28) | |
3850 | #define FDI_LINK_TRAIN_PATTERN_2 (1<<28) | |
3851 | #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) | |
3852 | #define FDI_LINK_TRAIN_NONE (3<<28) | |
3853 | #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) | |
3854 | #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) | |
3855 | #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) | |
3856 | #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) | |
3857 | #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) | |
3858 | #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) | |
3859 | #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) | |
3860 | #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) | |
8db9d77b ZW |
3861 | /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. |
3862 | SNB has different settings. */ | |
3863 | /* SNB A-stepping */ | |
3864 | #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) | |
3865 | #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) | |
3866 | #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) | |
3867 | #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) | |
3868 | /* SNB B-stepping */ | |
3869 | #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22) | |
3870 | #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22) | |
3871 | #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) | |
3872 | #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) | |
3873 | #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22) | |
b9055052 ZW |
3874 | #define FDI_DP_PORT_WIDTH_X1 (0<<19) |
3875 | #define FDI_DP_PORT_WIDTH_X2 (1<<19) | |
3876 | #define FDI_DP_PORT_WIDTH_X3 (2<<19) | |
3877 | #define FDI_DP_PORT_WIDTH_X4 (3<<19) | |
3878 | #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) | |
f2b115e6 | 3879 | /* Ironlake: hardwired to 1 */ |
b9055052 | 3880 | #define FDI_TX_PLL_ENABLE (1<<14) |
357555c0 JB |
3881 | |
3882 | /* Ivybridge has different bits for lolz */ | |
3883 | #define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8) | |
3884 | #define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8) | |
3885 | #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8) | |
3886 | #define FDI_LINK_TRAIN_NONE_IVB (3<<8) | |
3887 | ||
b9055052 | 3888 | /* both Tx and Rx */ |
c4f9c4c2 | 3889 | #define FDI_COMPOSITE_SYNC (1<<11) |
357555c0 | 3890 | #define FDI_LINK_TRAIN_AUTO (1<<10) |
b9055052 ZW |
3891 | #define FDI_SCRAMBLING_ENABLE (0<<7) |
3892 | #define FDI_SCRAMBLING_DISABLE (1<<7) | |
3893 | ||
3894 | /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ | |
9db4a9c7 JB |
3895 | #define _FDI_RXA_CTL 0xf000c |
3896 | #define _FDI_RXB_CTL 0xf100c | |
3897 | #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) | |
b9055052 | 3898 | #define FDI_RX_ENABLE (1<<31) |
b9055052 | 3899 | /* train, dp width same as FDI_TX */ |
357555c0 JB |
3900 | #define FDI_FS_ERRC_ENABLE (1<<27) |
3901 | #define FDI_FE_ERRC_ENABLE (1<<26) | |
b9055052 | 3902 | #define FDI_DP_PORT_WIDTH_X8 (7<<19) |
68d18ad7 | 3903 | #define FDI_RX_POLARITY_REVERSED_LPT (1<<16) |
b9055052 ZW |
3904 | #define FDI_8BPC (0<<16) |
3905 | #define FDI_10BPC (1<<16) | |
3906 | #define FDI_6BPC (2<<16) | |
3907 | #define FDI_12BPC (3<<16) | |
3908 | #define FDI_LINK_REVERSE_OVERWRITE (1<<15) | |
3909 | #define FDI_DMI_LINK_REVERSE_MASK (1<<14) | |
3910 | #define FDI_RX_PLL_ENABLE (1<<13) | |
3911 | #define FDI_FS_ERR_CORRECT_ENABLE (1<<11) | |
3912 | #define FDI_FE_ERR_CORRECT_ENABLE (1<<10) | |
3913 | #define FDI_FS_ERR_REPORT_ENABLE (1<<9) | |
3914 | #define FDI_FE_ERR_REPORT_ENABLE (1<<8) | |
3915 | #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) | |
5eddb70b | 3916 | #define FDI_PCDCLK (1<<4) |
8db9d77b ZW |
3917 | /* CPT */ |
3918 | #define FDI_AUTO_TRAINING (1<<10) | |
3919 | #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) | |
3920 | #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8) | |
3921 | #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8) | |
3922 | #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) | |
3923 | #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) | |
dc04a61a ED |
3924 | /* LPT */ |
3925 | #define FDI_PORT_WIDTH_2X_LPT (1<<19) | |
3926 | #define FDI_PORT_WIDTH_1X_LPT (0<<19) | |
b9055052 | 3927 | |
04945641 PZ |
3928 | #define _FDI_RXA_MISC 0xf0010 |
3929 | #define _FDI_RXB_MISC 0xf1010 | |
3930 | #define FDI_RX_PWRDN_LANE1_MASK (3<<26) | |
3931 | #define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26) | |
3932 | #define FDI_RX_PWRDN_LANE0_MASK (3<<24) | |
3933 | #define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24) | |
3934 | #define FDI_RX_TP1_TO_TP2_48 (2<<20) | |
3935 | #define FDI_RX_TP1_TO_TP2_64 (3<<20) | |
3936 | #define FDI_RX_FDI_DELAY_90 (0x90<<0) | |
3937 | #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) | |
3938 | ||
9db4a9c7 JB |
3939 | #define _FDI_RXA_TUSIZE1 0xf0030 |
3940 | #define _FDI_RXA_TUSIZE2 0xf0038 | |
3941 | #define _FDI_RXB_TUSIZE1 0xf1030 | |
3942 | #define _FDI_RXB_TUSIZE2 0xf1038 | |
9db4a9c7 JB |
3943 | #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) |
3944 | #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) | |
b9055052 ZW |
3945 | |
3946 | /* FDI_RX interrupt register format */ | |
3947 | #define FDI_RX_INTER_LANE_ALIGN (1<<10) | |
3948 | #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ | |
3949 | #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ | |
3950 | #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) | |
3951 | #define FDI_RX_FS_CODE_ERR (1<<6) | |
3952 | #define FDI_RX_FE_CODE_ERR (1<<5) | |
3953 | #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) | |
3954 | #define FDI_RX_HDCP_LINK_FAIL (1<<3) | |
3955 | #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) | |
3956 | #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) | |
3957 | #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) | |
3958 | ||
9db4a9c7 JB |
3959 | #define _FDI_RXA_IIR 0xf0014 |
3960 | #define _FDI_RXA_IMR 0xf0018 | |
3961 | #define _FDI_RXB_IIR 0xf1014 | |
3962 | #define _FDI_RXB_IMR 0xf1018 | |
3963 | #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) | |
3964 | #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) | |
b9055052 ZW |
3965 | |
3966 | #define FDI_PLL_CTL_1 0xfe000 | |
3967 | #define FDI_PLL_CTL_2 0xfe004 | |
3968 | ||
b9055052 ZW |
3969 | /* or SDVOB */ |
3970 | #define HDMIB 0xe1140 | |
3971 | #define PORT_ENABLE (1 << 31) | |
3573c410 PZ |
3972 | #define TRANSCODER(pipe) ((pipe) << 30) |
3973 | #define TRANSCODER_CPT(pipe) ((pipe) << 29) | |
3974 | #define TRANSCODER_MASK (1 << 30) | |
3975 | #define TRANSCODER_MASK_CPT (3 << 29) | |
b9055052 ZW |
3976 | #define COLOR_FORMAT_8bpc (0) |
3977 | #define COLOR_FORMAT_12bpc (3 << 26) | |
3978 | #define SDVOB_HOTPLUG_ENABLE (1 << 23) | |
3979 | #define SDVO_ENCODING (0) | |
3980 | #define TMDS_ENCODING (2 << 10) | |
3981 | #define NULL_PACKET_VSYNC_ENABLE (1 << 9) | |
467b200d ZW |
3982 | /* CPT */ |
3983 | #define HDMI_MODE_SELECT (1 << 9) | |
3984 | #define DVI_MODE_SELECT (0) | |
b9055052 ZW |
3985 | #define SDVOB_BORDER_ENABLE (1 << 7) |
3986 | #define AUDIO_ENABLE (1 << 6) | |
3987 | #define VSYNC_ACTIVE_HIGH (1 << 4) | |
3988 | #define HSYNC_ACTIVE_HIGH (1 << 3) | |
3989 | #define PORT_DETECTED (1 << 2) | |
3990 | ||
461ed3ca ZY |
3991 | /* PCH SDVOB multiplex with HDMIB */ |
3992 | #define PCH_SDVOB HDMIB | |
3993 | ||
b9055052 ZW |
3994 | #define HDMIC 0xe1150 |
3995 | #define HDMID 0xe1160 | |
3996 | ||
3997 | #define PCH_LVDS 0xe1180 | |
3998 | #define LVDS_DETECTED (1 << 1) | |
3999 | ||
98364379 | 4000 | /* vlv has 2 sets of panel control regs. */ |
f12c47b2 VS |
4001 | #define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200) |
4002 | #define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204) | |
4003 | #define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208) | |
4004 | #define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c) | |
4005 | #define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210) | |
4006 | ||
4007 | #define PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300) | |
4008 | #define PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304) | |
4009 | #define PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308) | |
4010 | #define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c) | |
4011 | #define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310) | |
98364379 | 4012 | |
b9055052 ZW |
4013 | #define PCH_PP_STATUS 0xc7200 |
4014 | #define PCH_PP_CONTROL 0xc7204 | |
4a655f04 | 4015 | #define PANEL_UNLOCK_REGS (0xabcd << 16) |
1c0ae80a | 4016 | #define PANEL_UNLOCK_MASK (0xffff << 16) |
b9055052 ZW |
4017 | #define EDP_FORCE_VDD (1 << 3) |
4018 | #define EDP_BLC_ENABLE (1 << 2) | |
4019 | #define PANEL_POWER_RESET (1 << 1) | |
4020 | #define PANEL_POWER_OFF (0 << 0) | |
4021 | #define PANEL_POWER_ON (1 << 0) | |
4022 | #define PCH_PP_ON_DELAYS 0xc7208 | |
f01eca2e KP |
4023 | #define PANEL_PORT_SELECT_MASK (3 << 30) |
4024 | #define PANEL_PORT_SELECT_LVDS (0 << 30) | |
4025 | #define PANEL_PORT_SELECT_DPA (1 << 30) | |
b9055052 | 4026 | #define EDP_PANEL (1 << 30) |
f01eca2e KP |
4027 | #define PANEL_PORT_SELECT_DPC (2 << 30) |
4028 | #define PANEL_PORT_SELECT_DPD (3 << 30) | |
4029 | #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000) | |
4030 | #define PANEL_POWER_UP_DELAY_SHIFT 16 | |
4031 | #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff) | |
4032 | #define PANEL_LIGHT_ON_DELAY_SHIFT 0 | |
4033 | ||
b9055052 | 4034 | #define PCH_PP_OFF_DELAYS 0xc720c |
82ed61fa DV |
4035 | #define PANEL_POWER_PORT_SELECT_MASK (0x3 << 30) |
4036 | #define PANEL_POWER_PORT_LVDS (0 << 30) | |
4037 | #define PANEL_POWER_PORT_DP_A (1 << 30) | |
4038 | #define PANEL_POWER_PORT_DP_C (2 << 30) | |
4039 | #define PANEL_POWER_PORT_DP_D (3 << 30) | |
f01eca2e KP |
4040 | #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000) |
4041 | #define PANEL_POWER_DOWN_DELAY_SHIFT 16 | |
4042 | #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff) | |
4043 | #define PANEL_LIGHT_OFF_DELAY_SHIFT 0 | |
4044 | ||
b9055052 | 4045 | #define PCH_PP_DIVISOR 0xc7210 |
f01eca2e KP |
4046 | #define PP_REFERENCE_DIVIDER_MASK (0xffffff00) |
4047 | #define PP_REFERENCE_DIVIDER_SHIFT 8 | |
4048 | #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) | |
4049 | #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 | |
b9055052 | 4050 | |
5eb08b69 ZW |
4051 | #define PCH_DP_B 0xe4100 |
4052 | #define PCH_DPB_AUX_CH_CTL 0xe4110 | |
4053 | #define PCH_DPB_AUX_CH_DATA1 0xe4114 | |
4054 | #define PCH_DPB_AUX_CH_DATA2 0xe4118 | |
4055 | #define PCH_DPB_AUX_CH_DATA3 0xe411c | |
4056 | #define PCH_DPB_AUX_CH_DATA4 0xe4120 | |
4057 | #define PCH_DPB_AUX_CH_DATA5 0xe4124 | |
4058 | ||
4059 | #define PCH_DP_C 0xe4200 | |
4060 | #define PCH_DPC_AUX_CH_CTL 0xe4210 | |
4061 | #define PCH_DPC_AUX_CH_DATA1 0xe4214 | |
4062 | #define PCH_DPC_AUX_CH_DATA2 0xe4218 | |
4063 | #define PCH_DPC_AUX_CH_DATA3 0xe421c | |
4064 | #define PCH_DPC_AUX_CH_DATA4 0xe4220 | |
4065 | #define PCH_DPC_AUX_CH_DATA5 0xe4224 | |
4066 | ||
4067 | #define PCH_DP_D 0xe4300 | |
4068 | #define PCH_DPD_AUX_CH_CTL 0xe4310 | |
4069 | #define PCH_DPD_AUX_CH_DATA1 0xe4314 | |
4070 | #define PCH_DPD_AUX_CH_DATA2 0xe4318 | |
4071 | #define PCH_DPD_AUX_CH_DATA3 0xe431c | |
4072 | #define PCH_DPD_AUX_CH_DATA4 0xe4320 | |
4073 | #define PCH_DPD_AUX_CH_DATA5 0xe4324 | |
4074 | ||
8db9d77b ZW |
4075 | /* CPT */ |
4076 | #define PORT_TRANS_A_SEL_CPT 0 | |
4077 | #define PORT_TRANS_B_SEL_CPT (1<<29) | |
4078 | #define PORT_TRANS_C_SEL_CPT (2<<29) | |
4079 | #define PORT_TRANS_SEL_MASK (3<<29) | |
1519b995 | 4080 | #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29) |
19d8fe15 DV |
4081 | #define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30) |
4082 | #define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29) | |
8db9d77b ZW |
4083 | |
4084 | #define TRANS_DP_CTL_A 0xe0300 | |
4085 | #define TRANS_DP_CTL_B 0xe1300 | |
4086 | #define TRANS_DP_CTL_C 0xe2300 | |
23670b32 | 4087 | #define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B) |
8db9d77b ZW |
4088 | #define TRANS_DP_OUTPUT_ENABLE (1<<31) |
4089 | #define TRANS_DP_PORT_SEL_B (0<<29) | |
4090 | #define TRANS_DP_PORT_SEL_C (1<<29) | |
4091 | #define TRANS_DP_PORT_SEL_D (2<<29) | |
cb3543c6 | 4092 | #define TRANS_DP_PORT_SEL_NONE (3<<29) |
8db9d77b ZW |
4093 | #define TRANS_DP_PORT_SEL_MASK (3<<29) |
4094 | #define TRANS_DP_AUDIO_ONLY (1<<26) | |
4095 | #define TRANS_DP_ENH_FRAMING (1<<18) | |
4096 | #define TRANS_DP_8BPC (0<<9) | |
4097 | #define TRANS_DP_10BPC (1<<9) | |
4098 | #define TRANS_DP_6BPC (2<<9) | |
4099 | #define TRANS_DP_12BPC (3<<9) | |
220cad3c | 4100 | #define TRANS_DP_BPC_MASK (3<<9) |
8db9d77b ZW |
4101 | #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) |
4102 | #define TRANS_DP_VSYNC_ACTIVE_LOW 0 | |
4103 | #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) | |
4104 | #define TRANS_DP_HSYNC_ACTIVE_LOW 0 | |
94113cec | 4105 | #define TRANS_DP_SYNC_MASK (3<<3) |
8db9d77b ZW |
4106 | |
4107 | /* SNB eDP training params */ | |
4108 | /* SNB A-stepping */ | |
4109 | #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) | |
4110 | #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) | |
4111 | #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) | |
4112 | #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) | |
4113 | /* SNB B-stepping */ | |
3c5a62b5 YL |
4114 | #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22) |
4115 | #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22) | |
4116 | #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22) | |
4117 | #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22) | |
4118 | #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22) | |
8db9d77b ZW |
4119 | #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22) |
4120 | ||
1a2eb460 KP |
4121 | /* IVB */ |
4122 | #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22) | |
4123 | #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22) | |
4124 | #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22) | |
4125 | #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22) | |
4126 | #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22) | |
4127 | #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22) | |
4128 | #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x33 <<22) | |
4129 | ||
4130 | /* legacy values */ | |
4131 | #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22) | |
4132 | #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22) | |
4133 | #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22) | |
4134 | #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22) | |
4135 | #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22) | |
4136 | ||
4137 | #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22) | |
4138 | ||
cae5852d | 4139 | #define FORCEWAKE 0xA18C |
575155a9 JB |
4140 | #define FORCEWAKE_VLV 0x1300b0 |
4141 | #define FORCEWAKE_ACK_VLV 0x1300b4 | |
e7911c48 | 4142 | #define FORCEWAKE_ACK_HSW 0x130044 |
eb43f4af | 4143 | #define FORCEWAKE_ACK 0x130090 |
8d715f00 | 4144 | #define FORCEWAKE_MT 0xa188 /* multi-threaded */ |
c5836c27 CW |
4145 | #define FORCEWAKE_KERNEL 0x1 |
4146 | #define FORCEWAKE_USER 0x2 | |
8d715f00 KP |
4147 | #define FORCEWAKE_MT_ACK 0x130040 |
4148 | #define ECOBUS 0xa180 | |
4149 | #define FORCEWAKE_MT_ENABLE (1<<5) | |
8fd26859 | 4150 | |
dd202c6d BW |
4151 | #define GTFIFODBG 0x120000 |
4152 | #define GT_FIFO_CPU_ERROR_MASK 7 | |
4153 | #define GT_FIFO_OVFERR (1<<2) | |
4154 | #define GT_FIFO_IAWRERR (1<<1) | |
4155 | #define GT_FIFO_IARDERR (1<<0) | |
4156 | ||
91355834 | 4157 | #define GT_FIFO_FREE_ENTRIES 0x120008 |
95736720 | 4158 | #define GT_FIFO_NUM_RESERVED_ENTRIES 20 |
91355834 | 4159 | |
80e829fa DV |
4160 | #define GEN6_UCGCTL1 0x9400 |
4161 | # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) | |
de4a8bd1 | 4162 | # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) |
80e829fa | 4163 | |
406478dc | 4164 | #define GEN6_UCGCTL2 0x9404 |
0f846f81 | 4165 | # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30) |
6edaa7fc | 4166 | # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22) |
eae66b50 | 4167 | # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) |
406478dc | 4168 | # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) |
9ca1d10d | 4169 | # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) |
406478dc | 4170 | |
e3f33d46 JB |
4171 | #define GEN7_UCGCTL4 0x940c |
4172 | #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25) | |
4173 | ||
3b8d8d91 | 4174 | #define GEN6_RPNSWREQ 0xA008 |
8fd26859 CW |
4175 | #define GEN6_TURBO_DISABLE (1<<31) |
4176 | #define GEN6_FREQUENCY(x) ((x)<<25) | |
4177 | #define GEN6_OFFSET(x) ((x)<<19) | |
4178 | #define GEN6_AGGRESSIVE_TURBO (0<<15) | |
4179 | #define GEN6_RC_VIDEO_FREQ 0xA00C | |
4180 | #define GEN6_RC_CONTROL 0xA090 | |
4181 | #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16) | |
4182 | #define GEN6_RC_CTL_RC6p_ENABLE (1<<17) | |
4183 | #define GEN6_RC_CTL_RC6_ENABLE (1<<18) | |
4184 | #define GEN6_RC_CTL_RC1e_ENABLE (1<<20) | |
4185 | #define GEN6_RC_CTL_RC7_ENABLE (1<<22) | |
4186 | #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) | |
4187 | #define GEN6_RC_CTL_HW_ENABLE (1<<31) | |
4188 | #define GEN6_RP_DOWN_TIMEOUT 0xA010 | |
4189 | #define GEN6_RP_INTERRUPT_LIMITS 0xA014 | |
3b8d8d91 | 4190 | #define GEN6_RPSTAT1 0xA01C |
ccab5c82 JB |
4191 | #define GEN6_CAGF_SHIFT 8 |
4192 | #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) | |
8fd26859 CW |
4193 | #define GEN6_RP_CONTROL 0xA024 |
4194 | #define GEN6_RP_MEDIA_TURBO (1<<11) | |
6ed55ee7 BW |
4195 | #define GEN6_RP_MEDIA_MODE_MASK (3<<9) |
4196 | #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9) | |
4197 | #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9) | |
4198 | #define GEN6_RP_MEDIA_HW_MODE (1<<9) | |
4199 | #define GEN6_RP_MEDIA_SW_MODE (0<<9) | |
8fd26859 CW |
4200 | #define GEN6_RP_MEDIA_IS_GFX (1<<8) |
4201 | #define GEN6_RP_ENABLE (1<<7) | |
ccab5c82 JB |
4202 | #define GEN6_RP_UP_IDLE_MIN (0x1<<3) |
4203 | #define GEN6_RP_UP_BUSY_AVG (0x2<<3) | |
4204 | #define GEN6_RP_UP_BUSY_CONT (0x4<<3) | |
5a7dc92a | 4205 | #define GEN7_RP_DOWN_IDLE_AVG (0x2<<0) |
ccab5c82 | 4206 | #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) |
8fd26859 CW |
4207 | #define GEN6_RP_UP_THRESHOLD 0xA02C |
4208 | #define GEN6_RP_DOWN_THRESHOLD 0xA030 | |
ccab5c82 JB |
4209 | #define GEN6_RP_CUR_UP_EI 0xA050 |
4210 | #define GEN6_CURICONT_MASK 0xffffff | |
4211 | #define GEN6_RP_CUR_UP 0xA054 | |
4212 | #define GEN6_CURBSYTAVG_MASK 0xffffff | |
4213 | #define GEN6_RP_PREV_UP 0xA058 | |
4214 | #define GEN6_RP_CUR_DOWN_EI 0xA05C | |
4215 | #define GEN6_CURIAVG_MASK 0xffffff | |
4216 | #define GEN6_RP_CUR_DOWN 0xA060 | |
4217 | #define GEN6_RP_PREV_DOWN 0xA064 | |
8fd26859 CW |
4218 | #define GEN6_RP_UP_EI 0xA068 |
4219 | #define GEN6_RP_DOWN_EI 0xA06C | |
4220 | #define GEN6_RP_IDLE_HYSTERSIS 0xA070 | |
4221 | #define GEN6_RC_STATE 0xA094 | |
4222 | #define GEN6_RC1_WAKE_RATE_LIMIT 0xA098 | |
4223 | #define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C | |
4224 | #define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0 | |
4225 | #define GEN6_RC_EVALUATION_INTERVAL 0xA0A8 | |
4226 | #define GEN6_RC_IDLE_HYSTERSIS 0xA0AC | |
4227 | #define GEN6_RC_SLEEP 0xA0B0 | |
4228 | #define GEN6_RC1e_THRESHOLD 0xA0B4 | |
4229 | #define GEN6_RC6_THRESHOLD 0xA0B8 | |
4230 | #define GEN6_RC6p_THRESHOLD 0xA0BC | |
4231 | #define GEN6_RC6pp_THRESHOLD 0xA0C0 | |
3b8d8d91 | 4232 | #define GEN6_PMINTRMSK 0xA168 |
8fd26859 CW |
4233 | |
4234 | #define GEN6_PMISR 0x44020 | |
4912d041 | 4235 | #define GEN6_PMIMR 0x44024 /* rps_lock */ |
8fd26859 CW |
4236 | #define GEN6_PMIIR 0x44028 |
4237 | #define GEN6_PMIER 0x4402C | |
4238 | #define GEN6_PM_MBOX_EVENT (1<<25) | |
4239 | #define GEN6_PM_THERMAL_EVENT (1<<24) | |
4240 | #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6) | |
4241 | #define GEN6_PM_RP_UP_THRESHOLD (1<<5) | |
4242 | #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4) | |
4243 | #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2) | |
4244 | #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1) | |
4912d041 BW |
4245 | #define GEN6_PM_DEFERRED_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \ |
4246 | GEN6_PM_RP_DOWN_THRESHOLD | \ | |
4247 | GEN6_PM_RP_DOWN_TIMEOUT) | |
8fd26859 | 4248 | |
cce66a28 BW |
4249 | #define GEN6_GT_GFX_RC6_LOCKED 0x138104 |
4250 | #define GEN6_GT_GFX_RC6 0x138108 | |
4251 | #define GEN6_GT_GFX_RC6p 0x13810C | |
4252 | #define GEN6_GT_GFX_RC6pp 0x138110 | |
4253 | ||
8fd26859 CW |
4254 | #define GEN6_PCODE_MAILBOX 0x138124 |
4255 | #define GEN6_PCODE_READY (1<<31) | |
a6044e23 | 4256 | #define GEN6_READ_OC_PARAMS 0xc |
23b2f8bb JB |
4257 | #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 |
4258 | #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 | |
31643d54 BW |
4259 | #define GEN6_PCODE_WRITE_RC6VIDS 0x4 |
4260 | #define GEN6_PCODE_READ_RC6VIDS 0x5 | |
4261 | #define GEN6_ENCODE_RC6_VID(mv) (((mv) / 5) - 245) < 0 ?: 0 | |
4262 | #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) > 0 ? ((vids) * 5) + 245 : 0) | |
8fd26859 | 4263 | #define GEN6_PCODE_DATA 0x138128 |
23b2f8bb | 4264 | #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 |
8fd26859 | 4265 | |
4d85529d BW |
4266 | #define GEN6_GT_CORE_STATUS 0x138060 |
4267 | #define GEN6_CORE_CPD_STATE_MASK (7<<4) | |
4268 | #define GEN6_RCn_MASK 7 | |
4269 | #define GEN6_RC0 0 | |
4270 | #define GEN6_RC3 2 | |
4271 | #define GEN6_RC6 3 | |
4272 | #define GEN6_RC7 4 | |
4273 | ||
e3689190 BW |
4274 | #define GEN7_MISCCPCTL (0x9424) |
4275 | #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0) | |
4276 | ||
4277 | /* IVYBRIDGE DPF */ | |
4278 | #define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */ | |
4279 | #define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14) | |
4280 | #define GEN7_PARITY_ERROR_VALID (1<<13) | |
4281 | #define GEN7_L3CDERRST1_BANK_MASK (3<<11) | |
4282 | #define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8) | |
4283 | #define GEN7_PARITY_ERROR_ROW(reg) \ | |
4284 | ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14) | |
4285 | #define GEN7_PARITY_ERROR_BANK(reg) \ | |
4286 | ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11) | |
4287 | #define GEN7_PARITY_ERROR_SUBBANK(reg) \ | |
4288 | ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) | |
4289 | #define GEN7_L3CDERRST1_ENABLE (1<<7) | |
4290 | ||
b9524a1e BW |
4291 | #define GEN7_L3LOG_BASE 0xB070 |
4292 | #define GEN7_L3LOG_SIZE 0x80 | |
4293 | ||
12f3382b JB |
4294 | #define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */ |
4295 | #define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100 | |
4296 | #define GEN7_MAX_PS_THREAD_DEP (8<<12) | |
4297 | #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) | |
4298 | ||
8ab43976 JB |
4299 | #define GEN7_ROW_CHICKEN2 0xe4f4 |
4300 | #define GEN7_ROW_CHICKEN2_GT2 0xf4f4 | |
4301 | #define DOP_CLOCK_GATING_DISABLE (1<<0) | |
4302 | ||
f4ba9f81 | 4303 | #define G4X_AUD_VID_DID (dev_priv->info->display_mmio_offset + 0x62020) |
e0dac65e WF |
4304 | #define INTEL_AUDIO_DEVCL 0x808629FB |
4305 | #define INTEL_AUDIO_DEVBLC 0x80862801 | |
4306 | #define INTEL_AUDIO_DEVCTG 0x80862802 | |
4307 | ||
4308 | #define G4X_AUD_CNTL_ST 0x620B4 | |
4309 | #define G4X_ELDV_DEVCL_DEVBLC (1 << 13) | |
4310 | #define G4X_ELDV_DEVCTG (1 << 14) | |
4311 | #define G4X_ELD_ADDR (0xf << 5) | |
4312 | #define G4X_ELD_ACK (1 << 4) | |
4313 | #define G4X_HDMIW_HDMIEDID 0x6210C | |
4314 | ||
1202b4c6 | 4315 | #define IBX_HDMIW_HDMIEDID_A 0xE2050 |
9b138a83 WX |
4316 | #define IBX_HDMIW_HDMIEDID_B 0xE2150 |
4317 | #define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ | |
4318 | IBX_HDMIW_HDMIEDID_A, \ | |
4319 | IBX_HDMIW_HDMIEDID_B) | |
1202b4c6 | 4320 | #define IBX_AUD_CNTL_ST_A 0xE20B4 |
9b138a83 WX |
4321 | #define IBX_AUD_CNTL_ST_B 0xE21B4 |
4322 | #define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \ | |
4323 | IBX_AUD_CNTL_ST_A, \ | |
4324 | IBX_AUD_CNTL_ST_B) | |
1202b4c6 WF |
4325 | #define IBX_ELD_BUFFER_SIZE (0x1f << 10) |
4326 | #define IBX_ELD_ADDRESS (0x1f << 5) | |
4327 | #define IBX_ELD_ACK (1 << 4) | |
4328 | #define IBX_AUD_CNTL_ST2 0xE20C0 | |
4329 | #define IBX_ELD_VALIDB (1 << 0) | |
4330 | #define IBX_CP_READYB (1 << 1) | |
4331 | ||
4332 | #define CPT_HDMIW_HDMIEDID_A 0xE5050 | |
9b138a83 WX |
4333 | #define CPT_HDMIW_HDMIEDID_B 0xE5150 |
4334 | #define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ | |
4335 | CPT_HDMIW_HDMIEDID_A, \ | |
4336 | CPT_HDMIW_HDMIEDID_B) | |
1202b4c6 | 4337 | #define CPT_AUD_CNTL_ST_A 0xE50B4 |
9b138a83 WX |
4338 | #define CPT_AUD_CNTL_ST_B 0xE51B4 |
4339 | #define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \ | |
4340 | CPT_AUD_CNTL_ST_A, \ | |
4341 | CPT_AUD_CNTL_ST_B) | |
1202b4c6 | 4342 | #define CPT_AUD_CNTRL_ST2 0xE50C0 |
e0dac65e | 4343 | |
ae662d31 EA |
4344 | /* These are the 4 32-bit write offset registers for each stream |
4345 | * output buffer. It determines the offset from the | |
4346 | * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. | |
4347 | */ | |
4348 | #define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4) | |
4349 | ||
b6daa025 | 4350 | #define IBX_AUD_CONFIG_A 0xe2000 |
9b138a83 WX |
4351 | #define IBX_AUD_CONFIG_B 0xe2100 |
4352 | #define IBX_AUD_CFG(pipe) _PIPE(pipe, \ | |
4353 | IBX_AUD_CONFIG_A, \ | |
4354 | IBX_AUD_CONFIG_B) | |
b6daa025 | 4355 | #define CPT_AUD_CONFIG_A 0xe5000 |
9b138a83 WX |
4356 | #define CPT_AUD_CONFIG_B 0xe5100 |
4357 | #define CPT_AUD_CFG(pipe) _PIPE(pipe, \ | |
4358 | CPT_AUD_CONFIG_A, \ | |
4359 | CPT_AUD_CONFIG_B) | |
b6daa025 WF |
4360 | #define AUD_CONFIG_N_VALUE_INDEX (1 << 29) |
4361 | #define AUD_CONFIG_N_PROG_ENABLE (1 << 28) | |
4362 | #define AUD_CONFIG_UPPER_N_SHIFT 20 | |
4363 | #define AUD_CONFIG_UPPER_N_VALUE (0xff << 20) | |
4364 | #define AUD_CONFIG_LOWER_N_SHIFT 4 | |
4365 | #define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4) | |
4366 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 | |
4367 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16) | |
4368 | #define AUD_CONFIG_DISABLE_NCTS (1 << 3) | |
4369 | ||
9a78b6cc WX |
4370 | /* HSW Audio */ |
4371 | #define HSW_AUD_CONFIG_A 0x65000 /* Audio Configuration Transcoder A */ | |
4372 | #define HSW_AUD_CONFIG_B 0x65100 /* Audio Configuration Transcoder B */ | |
4373 | #define HSW_AUD_CFG(pipe) _PIPE(pipe, \ | |
4374 | HSW_AUD_CONFIG_A, \ | |
4375 | HSW_AUD_CONFIG_B) | |
4376 | ||
4377 | #define HSW_AUD_MISC_CTRL_A 0x65010 /* Audio Misc Control Convert 1 */ | |
4378 | #define HSW_AUD_MISC_CTRL_B 0x65110 /* Audio Misc Control Convert 2 */ | |
4379 | #define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \ | |
4380 | HSW_AUD_MISC_CTRL_A, \ | |
4381 | HSW_AUD_MISC_CTRL_B) | |
4382 | ||
4383 | #define HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 /* Audio DIP and ELD Control State Transcoder A */ | |
4384 | #define HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 /* Audio DIP and ELD Control State Transcoder B */ | |
4385 | #define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \ | |
4386 | HSW_AUD_DIP_ELD_CTRL_ST_A, \ | |
4387 | HSW_AUD_DIP_ELD_CTRL_ST_B) | |
4388 | ||
4389 | /* Audio Digital Converter */ | |
4390 | #define HSW_AUD_DIG_CNVT_1 0x65080 /* Audio Converter 1 */ | |
4391 | #define HSW_AUD_DIG_CNVT_2 0x65180 /* Audio Converter 1 */ | |
4392 | #define AUD_DIG_CNVT(pipe) _PIPE(pipe, \ | |
4393 | HSW_AUD_DIG_CNVT_1, \ | |
4394 | HSW_AUD_DIG_CNVT_2) | |
9b138a83 | 4395 | #define DIP_PORT_SEL_MASK 0x3 |
9a78b6cc WX |
4396 | |
4397 | #define HSW_AUD_EDID_DATA_A 0x65050 | |
4398 | #define HSW_AUD_EDID_DATA_B 0x65150 | |
4399 | #define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \ | |
4400 | HSW_AUD_EDID_DATA_A, \ | |
4401 | HSW_AUD_EDID_DATA_B) | |
4402 | ||
4403 | #define HSW_AUD_PIPE_CONV_CFG 0x6507c /* Audio pipe and converter configs */ | |
4404 | #define HSW_AUD_PIN_ELD_CP_VLD 0x650c0 /* Audio ELD and CP Ready Status */ | |
4405 | #define AUDIO_INACTIVE_C (1<<11) | |
4406 | #define AUDIO_INACTIVE_B (1<<7) | |
4407 | #define AUDIO_INACTIVE_A (1<<3) | |
4408 | #define AUDIO_OUTPUT_ENABLE_A (1<<2) | |
4409 | #define AUDIO_OUTPUT_ENABLE_B (1<<6) | |
4410 | #define AUDIO_OUTPUT_ENABLE_C (1<<10) | |
4411 | #define AUDIO_ELD_VALID_A (1<<0) | |
4412 | #define AUDIO_ELD_VALID_B (1<<4) | |
4413 | #define AUDIO_ELD_VALID_C (1<<8) | |
4414 | #define AUDIO_CP_READY_A (1<<1) | |
4415 | #define AUDIO_CP_READY_B (1<<5) | |
4416 | #define AUDIO_CP_READY_C (1<<9) | |
4417 | ||
9eb3a752 | 4418 | /* HSW Power Wells */ |
5e49cea6 PZ |
4419 | #define HSW_PWR_WELL_CTL1 0x45400 /* BIOS */ |
4420 | #define HSW_PWR_WELL_CTL2 0x45404 /* Driver */ | |
4421 | #define HSW_PWR_WELL_CTL3 0x45408 /* KVMR */ | |
4422 | #define HSW_PWR_WELL_CTL4 0x4540C /* Debug */ | |
4423 | #define HSW_PWR_WELL_ENABLE (1<<31) | |
4424 | #define HSW_PWR_WELL_STATE (1<<30) | |
4425 | #define HSW_PWR_WELL_CTL5 0x45410 | |
9eb3a752 ED |
4426 | #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31) |
4427 | #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20) | |
5e49cea6 PZ |
4428 | #define HSW_PWR_WELL_FORCE_ON (1<<19) |
4429 | #define HSW_PWR_WELL_CTL6 0x45414 | |
9eb3a752 | 4430 | |
e7e104c3 | 4431 | /* Per-pipe DDI Function Control */ |
ad80a810 PZ |
4432 | #define TRANS_DDI_FUNC_CTL_A 0x60400 |
4433 | #define TRANS_DDI_FUNC_CTL_B 0x61400 | |
4434 | #define TRANS_DDI_FUNC_CTL_C 0x62400 | |
4435 | #define TRANS_DDI_FUNC_CTL_EDP 0x6F400 | |
4436 | #define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER(tran, TRANS_DDI_FUNC_CTL_A, \ | |
4437 | TRANS_DDI_FUNC_CTL_B) | |
4438 | #define TRANS_DDI_FUNC_ENABLE (1<<31) | |
e7e104c3 | 4439 | /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ |
ad80a810 PZ |
4440 | #define TRANS_DDI_PORT_MASK (7<<28) |
4441 | #define TRANS_DDI_SELECT_PORT(x) ((x)<<28) | |
4442 | #define TRANS_DDI_PORT_NONE (0<<28) | |
4443 | #define TRANS_DDI_MODE_SELECT_MASK (7<<24) | |
4444 | #define TRANS_DDI_MODE_SELECT_HDMI (0<<24) | |
4445 | #define TRANS_DDI_MODE_SELECT_DVI (1<<24) | |
4446 | #define TRANS_DDI_MODE_SELECT_DP_SST (2<<24) | |
4447 | #define TRANS_DDI_MODE_SELECT_DP_MST (3<<24) | |
4448 | #define TRANS_DDI_MODE_SELECT_FDI (4<<24) | |
4449 | #define TRANS_DDI_BPC_MASK (7<<20) | |
4450 | #define TRANS_DDI_BPC_8 (0<<20) | |
4451 | #define TRANS_DDI_BPC_10 (1<<20) | |
4452 | #define TRANS_DDI_BPC_6 (2<<20) | |
4453 | #define TRANS_DDI_BPC_12 (3<<20) | |
4454 | #define TRANS_DDI_PVSYNC (1<<17) | |
4455 | #define TRANS_DDI_PHSYNC (1<<16) | |
4456 | #define TRANS_DDI_EDP_INPUT_MASK (7<<12) | |
4457 | #define TRANS_DDI_EDP_INPUT_A_ON (0<<12) | |
4458 | #define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12) | |
4459 | #define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12) | |
4460 | #define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12) | |
4461 | #define TRANS_DDI_BFI_ENABLE (1<<4) | |
4462 | #define TRANS_DDI_PORT_WIDTH_X1 (0<<1) | |
4463 | #define TRANS_DDI_PORT_WIDTH_X2 (1<<1) | |
4464 | #define TRANS_DDI_PORT_WIDTH_X4 (3<<1) | |
e7e104c3 | 4465 | |
0e87f667 ED |
4466 | /* DisplayPort Transport Control */ |
4467 | #define DP_TP_CTL_A 0x64040 | |
4468 | #define DP_TP_CTL_B 0x64140 | |
5e49cea6 PZ |
4469 | #define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B) |
4470 | #define DP_TP_CTL_ENABLE (1<<31) | |
4471 | #define DP_TP_CTL_MODE_SST (0<<27) | |
4472 | #define DP_TP_CTL_MODE_MST (1<<27) | |
0e87f667 | 4473 | #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18) |
5e49cea6 | 4474 | #define DP_TP_CTL_FDI_AUTOTRAIN (1<<15) |
0e87f667 ED |
4475 | #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8) |
4476 | #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8) | |
4477 | #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8) | |
d6c0d722 PZ |
4478 | #define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8) |
4479 | #define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8) | |
5e49cea6 | 4480 | #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8) |
d6c0d722 | 4481 | #define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7) |
0e87f667 | 4482 | |
e411b2c1 ED |
4483 | /* DisplayPort Transport Status */ |
4484 | #define DP_TP_STATUS_A 0x64044 | |
4485 | #define DP_TP_STATUS_B 0x64144 | |
5e49cea6 | 4486 | #define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B) |
d6c0d722 | 4487 | #define DP_TP_STATUS_IDLE_DONE (1<<25) |
e411b2c1 ED |
4488 | #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12) |
4489 | ||
03f896a1 ED |
4490 | /* DDI Buffer Control */ |
4491 | #define DDI_BUF_CTL_A 0x64000 | |
4492 | #define DDI_BUF_CTL_B 0x64100 | |
5e49cea6 PZ |
4493 | #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B) |
4494 | #define DDI_BUF_CTL_ENABLE (1<<31) | |
03f896a1 | 4495 | #define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */ |
5e49cea6 | 4496 | #define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */ |
03f896a1 | 4497 | #define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */ |
5e49cea6 | 4498 | #define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */ |
03f896a1 | 4499 | #define DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */ |
5e49cea6 | 4500 | #define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */ |
03f896a1 ED |
4501 | #define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */ |
4502 | #define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */ | |
5e49cea6 PZ |
4503 | #define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */ |
4504 | #define DDI_BUF_EMP_MASK (0xf<<24) | |
4505 | #define DDI_BUF_IS_IDLE (1<<7) | |
79935fca | 4506 | #define DDI_A_4_LANES (1<<4) |
5e49cea6 PZ |
4507 | #define DDI_PORT_WIDTH_X1 (0<<1) |
4508 | #define DDI_PORT_WIDTH_X2 (1<<1) | |
4509 | #define DDI_PORT_WIDTH_X4 (3<<1) | |
03f896a1 ED |
4510 | #define DDI_INIT_DISPLAY_DETECTED (1<<0) |
4511 | ||
bb879a44 ED |
4512 | /* DDI Buffer Translations */ |
4513 | #define DDI_BUF_TRANS_A 0x64E00 | |
4514 | #define DDI_BUF_TRANS_B 0x64E60 | |
5e49cea6 | 4515 | #define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B) |
bb879a44 | 4516 | |
7501a4d8 ED |
4517 | /* Sideband Interface (SBI) is programmed indirectly, via |
4518 | * SBI_ADDR, which contains the register offset; and SBI_DATA, | |
4519 | * which contains the payload */ | |
5e49cea6 PZ |
4520 | #define SBI_ADDR 0xC6000 |
4521 | #define SBI_DATA 0xC6004 | |
7501a4d8 | 4522 | #define SBI_CTL_STAT 0xC6008 |
988d6ee8 PZ |
4523 | #define SBI_CTL_DEST_ICLK (0x0<<16) |
4524 | #define SBI_CTL_DEST_MPHY (0x1<<16) | |
4525 | #define SBI_CTL_OP_IORD (0x2<<8) | |
4526 | #define SBI_CTL_OP_IOWR (0x3<<8) | |
7501a4d8 ED |
4527 | #define SBI_CTL_OP_CRRD (0x6<<8) |
4528 | #define SBI_CTL_OP_CRWR (0x7<<8) | |
4529 | #define SBI_RESPONSE_FAIL (0x1<<1) | |
5e49cea6 PZ |
4530 | #define SBI_RESPONSE_SUCCESS (0x0<<1) |
4531 | #define SBI_BUSY (0x1<<0) | |
4532 | #define SBI_READY (0x0<<0) | |
52f025ef | 4533 | |
ccf1c867 | 4534 | /* SBI offsets */ |
5e49cea6 | 4535 | #define SBI_SSCDIVINTPHASE6 0x0600 |
ccf1c867 ED |
4536 | #define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1) |
4537 | #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1) | |
4538 | #define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8) | |
4539 | #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8) | |
5e49cea6 | 4540 | #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15) |
ccf1c867 | 4541 | #define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0) |
5e49cea6 | 4542 | #define SBI_SSCCTL 0x020c |
ccf1c867 | 4543 | #define SBI_SSCCTL6 0x060C |
dde86e2d | 4544 | #define SBI_SSCCTL_PATHALT (1<<3) |
5e49cea6 | 4545 | #define SBI_SSCCTL_DISABLE (1<<0) |
ccf1c867 ED |
4546 | #define SBI_SSCAUXDIV6 0x0610 |
4547 | #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4) | |
5e49cea6 | 4548 | #define SBI_DBUFF0 0x2a00 |
dde86e2d | 4549 | #define SBI_DBUFF0_ENABLE (1<<0) |
ccf1c867 | 4550 | |
52f025ef | 4551 | /* LPT PIXCLK_GATE */ |
5e49cea6 | 4552 | #define PIXCLK_GATE 0xC6020 |
745ca3be PZ |
4553 | #define PIXCLK_GATE_UNGATE (1<<0) |
4554 | #define PIXCLK_GATE_GATE (0<<0) | |
52f025ef | 4555 | |
e93ea06a | 4556 | /* SPLL */ |
5e49cea6 | 4557 | #define SPLL_CTL 0x46020 |
e93ea06a | 4558 | #define SPLL_PLL_ENABLE (1<<31) |
39bc66c9 DL |
4559 | #define SPLL_PLL_SSC (1<<28) |
4560 | #define SPLL_PLL_NON_SSC (2<<28) | |
5e49cea6 PZ |
4561 | #define SPLL_PLL_FREQ_810MHz (0<<26) |
4562 | #define SPLL_PLL_FREQ_1350MHz (1<<26) | |
e93ea06a | 4563 | |
4dffc404 | 4564 | /* WRPLL */ |
5e49cea6 PZ |
4565 | #define WRPLL_CTL1 0x46040 |
4566 | #define WRPLL_CTL2 0x46060 | |
4567 | #define WRPLL_PLL_ENABLE (1<<31) | |
4568 | #define WRPLL_PLL_SELECT_SSC (0x01<<28) | |
39bc66c9 | 4569 | #define WRPLL_PLL_SELECT_NON_SSC (0x02<<28) |
4dffc404 | 4570 | #define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28) |
ef4d084f | 4571 | /* WRPLL divider programming */ |
5e49cea6 PZ |
4572 | #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0) |
4573 | #define WRPLL_DIVIDER_POST(x) ((x)<<8) | |
4574 | #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16) | |
4dffc404 | 4575 | |
fec9181c ED |
4576 | /* Port clock selection */ |
4577 | #define PORT_CLK_SEL_A 0x46100 | |
4578 | #define PORT_CLK_SEL_B 0x46104 | |
5e49cea6 | 4579 | #define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B) |
fec9181c ED |
4580 | #define PORT_CLK_SEL_LCPLL_2700 (0<<29) |
4581 | #define PORT_CLK_SEL_LCPLL_1350 (1<<29) | |
4582 | #define PORT_CLK_SEL_LCPLL_810 (2<<29) | |
5e49cea6 | 4583 | #define PORT_CLK_SEL_SPLL (3<<29) |
fec9181c ED |
4584 | #define PORT_CLK_SEL_WRPLL1 (4<<29) |
4585 | #define PORT_CLK_SEL_WRPLL2 (5<<29) | |
6441ab5f | 4586 | #define PORT_CLK_SEL_NONE (7<<29) |
fec9181c | 4587 | |
bb523fc0 PZ |
4588 | /* Transcoder clock selection */ |
4589 | #define TRANS_CLK_SEL_A 0x46140 | |
4590 | #define TRANS_CLK_SEL_B 0x46144 | |
4591 | #define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B) | |
4592 | /* For each transcoder, we need to select the corresponding port clock */ | |
4593 | #define TRANS_CLK_SEL_DISABLED (0x0<<29) | |
4594 | #define TRANS_CLK_SEL_PORT(x) ((x+1)<<29) | |
fec9181c | 4595 | |
c9809791 PZ |
4596 | #define _TRANSA_MSA_MISC 0x60410 |
4597 | #define _TRANSB_MSA_MISC 0x61410 | |
4598 | #define TRANS_MSA_MISC(tran) _TRANSCODER(tran, _TRANSA_MSA_MISC, \ | |
4599 | _TRANSB_MSA_MISC) | |
4600 | #define TRANS_MSA_SYNC_CLK (1<<0) | |
4601 | #define TRANS_MSA_6_BPC (0<<5) | |
4602 | #define TRANS_MSA_8_BPC (1<<5) | |
4603 | #define TRANS_MSA_10_BPC (2<<5) | |
4604 | #define TRANS_MSA_12_BPC (3<<5) | |
4605 | #define TRANS_MSA_16_BPC (4<<5) | |
dae84799 | 4606 | |
90e8d31c | 4607 | /* LCPLL Control */ |
5e49cea6 | 4608 | #define LCPLL_CTL 0x130040 |
90e8d31c ED |
4609 | #define LCPLL_PLL_DISABLE (1<<31) |
4610 | #define LCPLL_PLL_LOCK (1<<30) | |
79f689aa PZ |
4611 | #define LCPLL_CLK_FREQ_MASK (3<<26) |
4612 | #define LCPLL_CLK_FREQ_450 (0<<26) | |
5e49cea6 | 4613 | #define LCPLL_CD_CLOCK_DISABLE (1<<25) |
90e8d31c | 4614 | #define LCPLL_CD2X_CLOCK_DISABLE (1<<23) |
79f689aa | 4615 | #define LCPLL_CD_SOURCE_FCLK (1<<21) |
90e8d31c | 4616 | |
69e94b7e ED |
4617 | /* Pipe WM_LINETIME - watermark line time */ |
4618 | #define PIPE_WM_LINETIME_A 0x45270 | |
4619 | #define PIPE_WM_LINETIME_B 0x45274 | |
5e49cea6 PZ |
4620 | #define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \ |
4621 | PIPE_WM_LINETIME_B) | |
4622 | #define PIPE_WM_LINETIME_MASK (0x1ff) | |
4623 | #define PIPE_WM_LINETIME_TIME(x) ((x)) | |
69e94b7e | 4624 | #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16) |
5e49cea6 | 4625 | #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16) |
96d6e350 ED |
4626 | |
4627 | /* SFUSE_STRAP */ | |
5e49cea6 | 4628 | #define SFUSE_STRAP 0xc2014 |
96d6e350 ED |
4629 | #define SFUSE_STRAP_DDIB_DETECTED (1<<2) |
4630 | #define SFUSE_STRAP_DDIC_DETECTED (1<<1) | |
4631 | #define SFUSE_STRAP_DDID_DETECTED (1<<0) | |
4632 | ||
1544d9d5 ED |
4633 | #define WM_DBG 0x45280 |
4634 | #define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0) | |
4635 | #define WM_DBG_DISALLOW_MAXFIFO (1<<1) | |
4636 | #define WM_DBG_DISALLOW_SPRITE (1<<2) | |
4637 | ||
585fb111 | 4638 | #endif /* _I915_REG_H_ */ |