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05235c53 CW |
1 | /* |
2 | * Copyright © 2008-2015 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
b52992c0 | 25 | #include <linux/dma-fence-array.h> |
e8861964 CW |
26 | #include <linux/irq_work.h> |
27 | #include <linux/prefetch.h> | |
e6017571 IM |
28 | #include <linux/sched.h> |
29 | #include <linux/sched/clock.h> | |
f361bf4a | 30 | #include <linux/sched/signal.h> |
fa545cbf | 31 | |
21950ee7 | 32 | #include "i915_active.h" |
696173b0 | 33 | #include "i915_drv.h" |
103b76ee | 34 | #include "i915_globals.h" |
9f58892e | 35 | #include "i915_reset.h" |
696173b0 | 36 | #include "intel_pm.h" |
05235c53 | 37 | |
e8861964 CW |
38 | struct execute_cb { |
39 | struct list_head link; | |
40 | struct irq_work work; | |
41 | struct i915_sw_fence *fence; | |
42 | }; | |
43 | ||
32eb6bcf | 44 | static struct i915_global_request { |
103b76ee | 45 | struct i915_global base; |
32eb6bcf CW |
46 | struct kmem_cache *slab_requests; |
47 | struct kmem_cache *slab_dependencies; | |
e8861964 | 48 | struct kmem_cache *slab_execute_cbs; |
32eb6bcf CW |
49 | } global; |
50 | ||
f54d1867 | 51 | static const char *i915_fence_get_driver_name(struct dma_fence *fence) |
04769652 CW |
52 | { |
53 | return "i915"; | |
54 | } | |
55 | ||
f54d1867 | 56 | static const char *i915_fence_get_timeline_name(struct dma_fence *fence) |
04769652 | 57 | { |
e61e0f51 CW |
58 | /* |
59 | * The timeline struct (as part of the ppgtt underneath a context) | |
05506b5b CW |
60 | * may be freed when the request is no longer in use by the GPU. |
61 | * We could extend the life of a context to beyond that of all | |
62 | * fences, possibly keeping the hw resource around indefinitely, | |
63 | * or we just give them a false name. Since | |
64 | * dma_fence_ops.get_timeline_name is a debug feature, the occasional | |
65 | * lie seems justifiable. | |
66 | */ | |
67 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) | |
68 | return "signaled"; | |
69 | ||
4daffb66 | 70 | return to_request(fence)->gem_context->name ?: "[i915]"; |
04769652 CW |
71 | } |
72 | ||
f54d1867 | 73 | static bool i915_fence_signaled(struct dma_fence *fence) |
04769652 | 74 | { |
e61e0f51 | 75 | return i915_request_completed(to_request(fence)); |
04769652 CW |
76 | } |
77 | ||
f54d1867 | 78 | static bool i915_fence_enable_signaling(struct dma_fence *fence) |
04769652 | 79 | { |
52c0fdb2 | 80 | return i915_request_enable_breadcrumb(to_request(fence)); |
04769652 CW |
81 | } |
82 | ||
f54d1867 | 83 | static signed long i915_fence_wait(struct dma_fence *fence, |
04769652 | 84 | bool interruptible, |
e95433c7 | 85 | signed long timeout) |
04769652 | 86 | { |
62eb3c24 CW |
87 | return i915_request_wait(to_request(fence), |
88 | interruptible | I915_WAIT_PRIORITY, | |
89 | timeout); | |
04769652 CW |
90 | } |
91 | ||
f54d1867 | 92 | static void i915_fence_release(struct dma_fence *fence) |
04769652 | 93 | { |
e61e0f51 | 94 | struct i915_request *rq = to_request(fence); |
04769652 | 95 | |
e61e0f51 CW |
96 | /* |
97 | * The request is put onto a RCU freelist (i.e. the address | |
fc158405 CW |
98 | * is immediately reused), mark the fences as being freed now. |
99 | * Otherwise the debugobjects for the fences are only marked as | |
100 | * freed when the slab cache itself is freed, and so we would get | |
101 | * caught trying to reuse dead objects. | |
102 | */ | |
e61e0f51 | 103 | i915_sw_fence_fini(&rq->submit); |
0c441cb6 | 104 | i915_sw_fence_fini(&rq->semaphore); |
fc158405 | 105 | |
32eb6bcf | 106 | kmem_cache_free(global.slab_requests, rq); |
04769652 CW |
107 | } |
108 | ||
f54d1867 | 109 | const struct dma_fence_ops i915_fence_ops = { |
04769652 CW |
110 | .get_driver_name = i915_fence_get_driver_name, |
111 | .get_timeline_name = i915_fence_get_timeline_name, | |
112 | .enable_signaling = i915_fence_enable_signaling, | |
113 | .signaled = i915_fence_signaled, | |
114 | .wait = i915_fence_wait, | |
115 | .release = i915_fence_release, | |
04769652 CW |
116 | }; |
117 | ||
05235c53 | 118 | static inline void |
e61e0f51 | 119 | i915_request_remove_from_client(struct i915_request *request) |
05235c53 | 120 | { |
c8659efa | 121 | struct drm_i915_file_private *file_priv; |
05235c53 | 122 | |
c8659efa | 123 | file_priv = request->file_priv; |
05235c53 CW |
124 | if (!file_priv) |
125 | return; | |
126 | ||
127 | spin_lock(&file_priv->mm.lock); | |
c8659efa CW |
128 | if (request->file_priv) { |
129 | list_del(&request->client_link); | |
130 | request->file_priv = NULL; | |
131 | } | |
05235c53 | 132 | spin_unlock(&file_priv->mm.lock); |
05235c53 CW |
133 | } |
134 | ||
6faf5916 | 135 | static void reserve_gt(struct drm_i915_private *i915) |
12d3173b | 136 | { |
636918f1 | 137 | if (!i915->gt.active_requests++) |
e4d2006f | 138 | i915_gem_unpark(i915); |
12d3173b CW |
139 | } |
140 | ||
52d7f16e | 141 | static void unreserve_gt(struct drm_i915_private *i915) |
9b6586ae | 142 | { |
b887d615 | 143 | GEM_BUG_ON(!i915->gt.active_requests); |
e4d2006f CW |
144 | if (!--i915->gt.active_requests) |
145 | i915_gem_park(i915); | |
9b6586ae CW |
146 | } |
147 | ||
e61e0f51 | 148 | static void advance_ring(struct i915_request *request) |
cbb60b4b | 149 | { |
b887d615 | 150 | struct intel_ring *ring = request->ring; |
cbb60b4b CW |
151 | unsigned int tail; |
152 | ||
e61e0f51 CW |
153 | /* |
154 | * We know the GPU must have read the request to have | |
cbb60b4b CW |
155 | * sent us the seqno + interrupt, so use the position |
156 | * of tail of the request to update the last known position | |
157 | * of the GPU head. | |
158 | * | |
159 | * Note this requires that we are always called in request | |
160 | * completion order. | |
161 | */ | |
b887d615 CW |
162 | GEM_BUG_ON(!list_is_first(&request->ring_link, &ring->request_list)); |
163 | if (list_is_last(&request->ring_link, &ring->request_list)) { | |
e61e0f51 CW |
164 | /* |
165 | * We may race here with execlists resubmitting this request | |
e6ba9992 CW |
166 | * as we retire it. The resubmission will move the ring->tail |
167 | * forwards (to request->wa_tail). We either read the | |
168 | * current value that was written to hw, or the value that | |
169 | * is just about to be. Either works, if we miss the last two | |
170 | * noops - they are safe to be replayed on a reset. | |
171 | */ | |
36620032 | 172 | tail = READ_ONCE(request->tail); |
643b450a | 173 | list_del(&ring->active_link); |
e6ba9992 | 174 | } else { |
cbb60b4b | 175 | tail = request->postfix; |
e6ba9992 | 176 | } |
b887d615 | 177 | list_del_init(&request->ring_link); |
cbb60b4b | 178 | |
b887d615 | 179 | ring->head = tail; |
cbb60b4b CW |
180 | } |
181 | ||
e61e0f51 | 182 | static void free_capture_list(struct i915_request *request) |
b0fd47ad | 183 | { |
e61e0f51 | 184 | struct i915_capture_list *capture; |
b0fd47ad CW |
185 | |
186 | capture = request->capture_list; | |
187 | while (capture) { | |
e61e0f51 | 188 | struct i915_capture_list *next = capture->next; |
b0fd47ad CW |
189 | |
190 | kfree(capture); | |
191 | capture = next; | |
192 | } | |
193 | } | |
194 | ||
b887d615 CW |
195 | static void __retire_engine_request(struct intel_engine_cs *engine, |
196 | struct i915_request *rq) | |
197 | { | |
b300fde8 | 198 | GEM_TRACE("%s(%s) fence %llx:%lld, current %d\n", |
b887d615 CW |
199 | __func__, engine->name, |
200 | rq->fence.context, rq->fence.seqno, | |
8892f477 | 201 | hwsp_seqno(rq)); |
b887d615 CW |
202 | |
203 | GEM_BUG_ON(!i915_request_completed(rq)); | |
204 | ||
205 | local_irq_disable(); | |
206 | ||
a89d1f92 CW |
207 | spin_lock(&engine->timeline.lock); |
208 | GEM_BUG_ON(!list_is_first(&rq->link, &engine->timeline.requests)); | |
b887d615 | 209 | list_del_init(&rq->link); |
a89d1f92 | 210 | spin_unlock(&engine->timeline.lock); |
b887d615 CW |
211 | |
212 | spin_lock(&rq->lock); | |
5013eb8c | 213 | i915_request_mark_complete(rq); |
0e21834e | 214 | if (!i915_request_signaled(rq)) |
b887d615 CW |
215 | dma_fence_signal_locked(&rq->fence); |
216 | if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &rq->fence.flags)) | |
52c0fdb2 | 217 | i915_request_cancel_breadcrumb(rq); |
b887d615 CW |
218 | if (rq->waitboost) { |
219 | GEM_BUG_ON(!atomic_read(&rq->i915->gt_pm.rps.num_waiters)); | |
220 | atomic_dec(&rq->i915->gt_pm.rps.num_waiters); | |
221 | } | |
222 | spin_unlock(&rq->lock); | |
223 | ||
224 | local_irq_enable(); | |
225 | ||
226 | /* | |
227 | * The backing object for the context is done after switching to the | |
228 | * *next* context. Therefore we cannot retire the previous context until | |
229 | * the next context has already started running. However, since we | |
230 | * cannot take the required locks at i915_request_submit() we | |
231 | * defer the unpinning of the active context to now, retirement of | |
232 | * the subsequent request. | |
233 | */ | |
234 | if (engine->last_retired_context) | |
1fc44d9b CW |
235 | intel_context_unpin(engine->last_retired_context); |
236 | engine->last_retired_context = rq->hw_context; | |
b887d615 CW |
237 | } |
238 | ||
239 | static void __retire_engine_upto(struct intel_engine_cs *engine, | |
240 | struct i915_request *rq) | |
241 | { | |
242 | struct i915_request *tmp; | |
243 | ||
244 | if (list_empty(&rq->link)) | |
245 | return; | |
246 | ||
247 | do { | |
a89d1f92 | 248 | tmp = list_first_entry(&engine->timeline.requests, |
b887d615 CW |
249 | typeof(*tmp), link); |
250 | ||
251 | GEM_BUG_ON(tmp->engine != engine); | |
252 | __retire_engine_request(engine, tmp); | |
253 | } while (tmp != rq); | |
254 | } | |
255 | ||
e61e0f51 | 256 | static void i915_request_retire(struct i915_request *request) |
05235c53 | 257 | { |
21950ee7 | 258 | struct i915_active_request *active, *next; |
fa545cbf | 259 | |
b300fde8 | 260 | GEM_TRACE("%s fence %llx:%lld, current %d\n", |
b887d615 | 261 | request->engine->name, |
d9b13c4d | 262 | request->fence.context, request->fence.seqno, |
8892f477 | 263 | hwsp_seqno(request)); |
d9b13c4d | 264 | |
4c7d62c6 | 265 | lockdep_assert_held(&request->i915->drm.struct_mutex); |
48bc2a4a | 266 | GEM_BUG_ON(!i915_sw_fence_signaled(&request->submit)); |
e61e0f51 | 267 | GEM_BUG_ON(!i915_request_completed(request)); |
4c7d62c6 | 268 | |
e61e0f51 | 269 | trace_i915_request_retire(request); |
80b204bc | 270 | |
cbb60b4b | 271 | advance_ring(request); |
b0fd47ad CW |
272 | free_capture_list(request); |
273 | ||
e61e0f51 CW |
274 | /* |
275 | * Walk through the active list, calling retire on each. This allows | |
fa545cbf CW |
276 | * objects to track their GPU activity and mark themselves as idle |
277 | * when their *last* active request is completed (updating state | |
278 | * tracking lists for eviction, active references for GEM, etc). | |
279 | * | |
280 | * As the ->retire() may free the node, we decouple it first and | |
281 | * pass along the auxiliary information (to avoid dereferencing | |
282 | * the node after the callback). | |
283 | */ | |
284 | list_for_each_entry_safe(active, next, &request->active_list, link) { | |
e61e0f51 CW |
285 | /* |
286 | * In microbenchmarks or focusing upon time inside the kernel, | |
fa545cbf CW |
287 | * we may spend an inordinate amount of time simply handling |
288 | * the retirement of requests and processing their callbacks. | |
289 | * Of which, this loop itself is particularly hot due to the | |
21950ee7 CW |
290 | * cache misses when jumping around the list of |
291 | * i915_active_request. So we try to keep this loop as | |
292 | * streamlined as possible and also prefetch the next | |
293 | * i915_active_request to try and hide the likely cache miss. | |
fa545cbf CW |
294 | */ |
295 | prefetchw(next); | |
296 | ||
297 | INIT_LIST_HEAD(&active->link); | |
0eafec6d | 298 | RCU_INIT_POINTER(active->request, NULL); |
fa545cbf CW |
299 | |
300 | active->retire(active, request); | |
301 | } | |
302 | ||
e61e0f51 | 303 | i915_request_remove_from_client(request); |
05235c53 | 304 | |
1fc44d9b | 305 | intel_context_unpin(request->hw_context); |
e5e1fc47 | 306 | |
b887d615 | 307 | __retire_engine_upto(request->engine, request); |
52e54209 | 308 | |
52d7f16e CW |
309 | unreserve_gt(request->i915); |
310 | ||
32eb6bcf | 311 | i915_sched_node_fini(&request->sched); |
e61e0f51 | 312 | i915_request_put(request); |
05235c53 CW |
313 | } |
314 | ||
e61e0f51 | 315 | void i915_request_retire_upto(struct i915_request *rq) |
05235c53 | 316 | { |
b887d615 | 317 | struct intel_ring *ring = rq->ring; |
e61e0f51 | 318 | struct i915_request *tmp; |
05235c53 | 319 | |
b300fde8 | 320 | GEM_TRACE("%s fence %llx:%lld, current %d\n", |
b887d615 CW |
321 | rq->engine->name, |
322 | rq->fence.context, rq->fence.seqno, | |
8892f477 | 323 | hwsp_seqno(rq)); |
b887d615 | 324 | |
e61e0f51 CW |
325 | lockdep_assert_held(&rq->i915->drm.struct_mutex); |
326 | GEM_BUG_ON(!i915_request_completed(rq)); | |
4ffd6e0c | 327 | |
b887d615 | 328 | if (list_empty(&rq->ring_link)) |
e95433c7 | 329 | return; |
05235c53 CW |
330 | |
331 | do { | |
b887d615 CW |
332 | tmp = list_first_entry(&ring->request_list, |
333 | typeof(*tmp), ring_link); | |
05235c53 | 334 | |
e61e0f51 CW |
335 | i915_request_retire(tmp); |
336 | } while (tmp != rq); | |
05235c53 CW |
337 | } |
338 | ||
e8861964 CW |
339 | static void irq_execute_cb(struct irq_work *wrk) |
340 | { | |
341 | struct execute_cb *cb = container_of(wrk, typeof(*cb), work); | |
342 | ||
343 | i915_sw_fence_complete(cb->fence); | |
344 | kmem_cache_free(global.slab_execute_cbs, cb); | |
345 | } | |
346 | ||
347 | static void __notify_execute_cb(struct i915_request *rq) | |
348 | { | |
349 | struct execute_cb *cb; | |
350 | ||
351 | lockdep_assert_held(&rq->lock); | |
352 | ||
353 | if (list_empty(&rq->execute_cb)) | |
354 | return; | |
355 | ||
356 | list_for_each_entry(cb, &rq->execute_cb, link) | |
357 | irq_work_queue(&cb->work); | |
358 | ||
359 | /* | |
360 | * XXX Rollback on __i915_request_unsubmit() | |
361 | * | |
362 | * In the future, perhaps when we have an active time-slicing scheduler, | |
363 | * it will be interesting to unsubmit parallel execution and remove | |
364 | * busywaits from the GPU until their master is restarted. This is | |
365 | * quite hairy, we have to carefully rollback the fence and do a | |
366 | * preempt-to-idle cycle on the target engine, all the while the | |
367 | * master execute_cb may refire. | |
368 | */ | |
369 | INIT_LIST_HEAD(&rq->execute_cb); | |
370 | } | |
371 | ||
372 | static int | |
373 | i915_request_await_execution(struct i915_request *rq, | |
374 | struct i915_request *signal, | |
375 | gfp_t gfp) | |
376 | { | |
377 | struct execute_cb *cb; | |
378 | ||
379 | if (i915_request_is_active(signal)) | |
380 | return 0; | |
381 | ||
382 | cb = kmem_cache_alloc(global.slab_execute_cbs, gfp); | |
383 | if (!cb) | |
384 | return -ENOMEM; | |
385 | ||
386 | cb->fence = &rq->submit; | |
387 | i915_sw_fence_await(cb->fence); | |
388 | init_irq_work(&cb->work, irq_execute_cb); | |
389 | ||
390 | spin_lock_irq(&signal->lock); | |
391 | if (i915_request_is_active(signal)) { | |
392 | i915_sw_fence_complete(cb->fence); | |
393 | kmem_cache_free(global.slab_execute_cbs, cb); | |
394 | } else { | |
395 | list_add_tail(&cb->link, &signal->execute_cb); | |
396 | } | |
397 | spin_unlock_irq(&signal->lock); | |
398 | ||
399 | return 0; | |
400 | } | |
401 | ||
4ccfee92 | 402 | static void move_to_timeline(struct i915_request *request, |
a89d1f92 | 403 | struct i915_timeline *timeline) |
4ccfee92 | 404 | { |
a89d1f92 CW |
405 | GEM_BUG_ON(request->timeline == &request->engine->timeline); |
406 | lockdep_assert_held(&request->engine->timeline.lock); | |
4ccfee92 | 407 | |
890fd185 | 408 | spin_lock(&request->timeline->lock); |
4ccfee92 CW |
409 | list_move_tail(&request->link, &timeline->requests); |
410 | spin_unlock(&request->timeline->lock); | |
411 | } | |
412 | ||
e61e0f51 | 413 | void __i915_request_submit(struct i915_request *request) |
5590af3e | 414 | { |
73cb9701 | 415 | struct intel_engine_cs *engine = request->engine; |
5590af3e | 416 | |
b300fde8 | 417 | GEM_TRACE("%s fence %llx:%lld -> current %d\n", |
e7702760 | 418 | engine->name, |
d9b13c4d | 419 | request->fence.context, request->fence.seqno, |
8892f477 | 420 | hwsp_seqno(request)); |
d9b13c4d | 421 | |
e60a870d | 422 | GEM_BUG_ON(!irqs_disabled()); |
a89d1f92 | 423 | lockdep_assert_held(&engine->timeline.lock); |
e60a870d | 424 | |
d9e61b66 CW |
425 | if (i915_gem_context_is_banned(request->gem_context)) |
426 | i915_request_skip(request, -EIO); | |
427 | ||
2564fe70 CW |
428 | /* |
429 | * Are we using semaphores when the gpu is already saturated? | |
430 | * | |
431 | * Using semaphores incurs a cost in having the GPU poll a | |
432 | * memory location, busywaiting for it to change. The continual | |
433 | * memory reads can have a noticeable impact on the rest of the | |
434 | * system with the extra bus traffic, stalling the cpu as it too | |
435 | * tries to access memory across the bus (perf stat -e bus-cycles). | |
436 | * | |
437 | * If we installed a semaphore on this request and we only submit | |
438 | * the request after the signaler completed, that indicates the | |
439 | * system is overloaded and using semaphores at this time only | |
440 | * increases the amount of work we are doing. If so, we disable | |
441 | * further use of semaphores until we are idle again, whence we | |
442 | * optimistically try again. | |
443 | */ | |
444 | if (request->sched.semaphores && | |
445 | i915_sw_fence_signaled(&request->semaphore)) | |
446 | request->hw_context->saturated |= request->sched.semaphores; | |
447 | ||
f2d13290 CW |
448 | /* We may be recursing from the signal callback of another i915 fence */ |
449 | spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING); | |
b5773a36 | 450 | |
52c0fdb2 CW |
451 | GEM_BUG_ON(test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags)); |
452 | set_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags); | |
b5773a36 | 453 | |
52c0fdb2 | 454 | if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags) && |
c36beba6 | 455 | !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &request->fence.flags) && |
52c0fdb2 CW |
456 | !i915_request_enable_breadcrumb(request)) |
457 | intel_engine_queue_breadcrumbs(engine); | |
b5773a36 | 458 | |
e8861964 CW |
459 | __notify_execute_cb(request); |
460 | ||
f2d13290 CW |
461 | spin_unlock(&request->lock); |
462 | ||
85474441 CW |
463 | engine->emit_fini_breadcrumb(request, |
464 | request->ring->vaddr + request->postfix); | |
5590af3e | 465 | |
4ccfee92 | 466 | /* Transfer from per-context onto the global per-engine timeline */ |
a89d1f92 | 467 | move_to_timeline(request, &engine->timeline); |
80b204bc | 468 | |
e61e0f51 | 469 | trace_i915_request_execute(request); |
d55ac5bf CW |
470 | } |
471 | ||
e61e0f51 | 472 | void i915_request_submit(struct i915_request *request) |
d55ac5bf CW |
473 | { |
474 | struct intel_engine_cs *engine = request->engine; | |
475 | unsigned long flags; | |
23902e49 | 476 | |
d55ac5bf | 477 | /* Will be called from irq-context when using foreign fences. */ |
a89d1f92 | 478 | spin_lock_irqsave(&engine->timeline.lock, flags); |
d55ac5bf | 479 | |
e61e0f51 | 480 | __i915_request_submit(request); |
d55ac5bf | 481 | |
a89d1f92 | 482 | spin_unlock_irqrestore(&engine->timeline.lock, flags); |
d55ac5bf CW |
483 | } |
484 | ||
e61e0f51 | 485 | void __i915_request_unsubmit(struct i915_request *request) |
d55ac5bf | 486 | { |
d6a2289d | 487 | struct intel_engine_cs *engine = request->engine; |
d55ac5bf | 488 | |
b300fde8 | 489 | GEM_TRACE("%s fence %llx:%lld, current %d\n", |
e7702760 | 490 | engine->name, |
d9b13c4d | 491 | request->fence.context, request->fence.seqno, |
8892f477 | 492 | hwsp_seqno(request)); |
d9b13c4d | 493 | |
e60a870d | 494 | GEM_BUG_ON(!irqs_disabled()); |
a89d1f92 | 495 | lockdep_assert_held(&engine->timeline.lock); |
48bc2a4a | 496 | |
e61e0f51 CW |
497 | /* |
498 | * Only unwind in reverse order, required so that the per-context list | |
d6a2289d CW |
499 | * is kept in seqno/ring order. |
500 | */ | |
80b204bc | 501 | |
d6a2289d CW |
502 | /* We may be recursing from the signal callback of another i915 fence */ |
503 | spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING); | |
b5773a36 | 504 | |
d6a2289d | 505 | if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags)) |
52c0fdb2 | 506 | i915_request_cancel_breadcrumb(request); |
b5773a36 | 507 | |
52c0fdb2 CW |
508 | GEM_BUG_ON(!test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags)); |
509 | clear_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags); | |
b5773a36 | 510 | |
d6a2289d CW |
511 | spin_unlock(&request->lock); |
512 | ||
513 | /* Transfer back from the global per-engine timeline to per-context */ | |
4ccfee92 | 514 | move_to_timeline(request, request->timeline); |
d6a2289d | 515 | |
e61e0f51 CW |
516 | /* |
517 | * We don't need to wake_up any waiters on request->execute, they | |
d6a2289d | 518 | * will get woken by any other event or us re-adding this request |
e61e0f51 | 519 | * to the engine timeline (__i915_request_submit()). The waiters |
d6a2289d CW |
520 | * should be quite adapt at finding that the request now has a new |
521 | * global_seqno to the one they went to sleep on. | |
522 | */ | |
523 | } | |
524 | ||
e61e0f51 | 525 | void i915_request_unsubmit(struct i915_request *request) |
d6a2289d CW |
526 | { |
527 | struct intel_engine_cs *engine = request->engine; | |
528 | unsigned long flags; | |
529 | ||
530 | /* Will be called from irq-context when using foreign fences. */ | |
a89d1f92 | 531 | spin_lock_irqsave(&engine->timeline.lock, flags); |
d6a2289d | 532 | |
e61e0f51 | 533 | __i915_request_unsubmit(request); |
d6a2289d | 534 | |
a89d1f92 | 535 | spin_unlock_irqrestore(&engine->timeline.lock, flags); |
5590af3e CW |
536 | } |
537 | ||
23902e49 | 538 | static int __i915_sw_fence_call |
d55ac5bf | 539 | submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) |
23902e49 | 540 | { |
e61e0f51 | 541 | struct i915_request *request = |
48bc2a4a | 542 | container_of(fence, typeof(*request), submit); |
48bc2a4a CW |
543 | |
544 | switch (state) { | |
545 | case FENCE_COMPLETE: | |
e61e0f51 | 546 | trace_i915_request_submit(request); |
af7a8ffa | 547 | /* |
e61e0f51 CW |
548 | * We need to serialize use of the submit_request() callback |
549 | * with its hotplugging performed during an emergency | |
550 | * i915_gem_set_wedged(). We use the RCU mechanism to mark the | |
551 | * critical section in order to force i915_gem_set_wedged() to | |
552 | * wait until the submit_request() is completed before | |
553 | * proceeding. | |
af7a8ffa DV |
554 | */ |
555 | rcu_read_lock(); | |
d55ac5bf | 556 | request->engine->submit_request(request); |
af7a8ffa | 557 | rcu_read_unlock(); |
48bc2a4a CW |
558 | break; |
559 | ||
560 | case FENCE_FREE: | |
e61e0f51 | 561 | i915_request_put(request); |
48bc2a4a CW |
562 | break; |
563 | } | |
564 | ||
23902e49 CW |
565 | return NOTIFY_DONE; |
566 | } | |
567 | ||
b7404c7e CW |
568 | static int __i915_sw_fence_call |
569 | semaphore_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) | |
570 | { | |
571 | struct i915_request *request = | |
572 | container_of(fence, typeof(*request), semaphore); | |
573 | ||
574 | switch (state) { | |
575 | case FENCE_COMPLETE: | |
a491cc8e | 576 | i915_schedule_bump_priority(request, I915_PRIORITY_NOSEMAPHORE); |
b7404c7e CW |
577 | break; |
578 | ||
579 | case FENCE_FREE: | |
580 | i915_request_put(request); | |
581 | break; | |
582 | } | |
583 | ||
584 | return NOTIFY_DONE; | |
585 | } | |
586 | ||
d22ba0cb CW |
587 | static void ring_retire_requests(struct intel_ring *ring) |
588 | { | |
589 | struct i915_request *rq, *rn; | |
590 | ||
591 | list_for_each_entry_safe(rq, rn, &ring->request_list, ring_link) { | |
592 | if (!i915_request_completed(rq)) | |
593 | break; | |
594 | ||
595 | i915_request_retire(rq); | |
596 | } | |
597 | } | |
598 | ||
599 | static noinline struct i915_request * | |
600 | i915_request_alloc_slow(struct intel_context *ce) | |
601 | { | |
602 | struct intel_ring *ring = ce->ring; | |
603 | struct i915_request *rq; | |
604 | ||
605 | if (list_empty(&ring->request_list)) | |
606 | goto out; | |
607 | ||
608 | /* Ratelimit ourselves to prevent oom from malicious clients */ | |
609 | rq = list_last_entry(&ring->request_list, typeof(*rq), ring_link); | |
610 | cond_synchronize_rcu(rq->rcustate); | |
611 | ||
612 | /* Retire our old requests in the hope that we free some */ | |
613 | ring_retire_requests(ring); | |
614 | ||
615 | out: | |
32eb6bcf | 616 | return kmem_cache_alloc(global.slab_requests, GFP_KERNEL); |
d22ba0cb CW |
617 | } |
618 | ||
8e637178 | 619 | /** |
e61e0f51 | 620 | * i915_request_alloc - allocate a request structure |
8e637178 CW |
621 | * |
622 | * @engine: engine that we wish to issue the request on. | |
623 | * @ctx: context that the request will be associated with. | |
8e637178 CW |
624 | * |
625 | * Returns a pointer to the allocated request if successful, | |
626 | * or an error code if not. | |
627 | */ | |
e61e0f51 CW |
628 | struct i915_request * |
629 | i915_request_alloc(struct intel_engine_cs *engine, struct i915_gem_context *ctx) | |
05235c53 | 630 | { |
e61e0f51 | 631 | struct drm_i915_private *i915 = engine->i915; |
1fc44d9b | 632 | struct intel_context *ce; |
ebece753 CW |
633 | struct i915_timeline *tl; |
634 | struct i915_request *rq; | |
635 | u32 seqno; | |
05235c53 CW |
636 | int ret; |
637 | ||
e61e0f51 | 638 | lockdep_assert_held(&i915->drm.struct_mutex); |
28176ef4 | 639 | |
e7af3116 CW |
640 | /* |
641 | * Preempt contexts are reserved for exclusive use to inject a | |
642 | * preemption context switch. They are never to be used for any trivial | |
643 | * request! | |
644 | */ | |
e61e0f51 | 645 | GEM_BUG_ON(ctx == i915->preempt_context); |
e7af3116 | 646 | |
e61e0f51 CW |
647 | /* |
648 | * ABI: Before userspace accesses the GPU (e.g. execbuffer), report | |
6ffb7d07 | 649 | * EIO if the GPU is already wedged. |
05235c53 | 650 | */ |
c41166f9 CW |
651 | ret = i915_terminally_wedged(i915); |
652 | if (ret) | |
653 | return ERR_PTR(ret); | |
05235c53 | 654 | |
e61e0f51 CW |
655 | /* |
656 | * Pinning the contexts may generate requests in order to acquire | |
e8a9c58f CW |
657 | * GGTT space, so do this first before we reserve a seqno for |
658 | * ourselves. | |
659 | */ | |
1fc44d9b CW |
660 | ce = intel_context_pin(ctx, engine); |
661 | if (IS_ERR(ce)) | |
662 | return ERR_CAST(ce); | |
28176ef4 | 663 | |
6faf5916 | 664 | reserve_gt(i915); |
3ef71149 | 665 | mutex_lock(&ce->ring->timeline->mutex); |
e8a9c58f | 666 | |
b887d615 | 667 | /* Move our oldest request to the slab-cache (if not in use!) */ |
1fc44d9b CW |
668 | rq = list_first_entry(&ce->ring->request_list, typeof(*rq), ring_link); |
669 | if (!list_is_last(&rq->ring_link, &ce->ring->request_list) && | |
7c572e1b | 670 | i915_request_completed(rq)) |
e61e0f51 | 671 | i915_request_retire(rq); |
9b5f4e5e | 672 | |
e61e0f51 CW |
673 | /* |
674 | * Beware: Dragons be flying overhead. | |
5a198b8c CW |
675 | * |
676 | * We use RCU to look up requests in flight. The lookups may | |
677 | * race with the request being allocated from the slab freelist. | |
678 | * That is the request we are writing to here, may be in the process | |
21950ee7 | 679 | * of being read by __i915_active_request_get_rcu(). As such, |
5a198b8c CW |
680 | * we have to be very careful when overwriting the contents. During |
681 | * the RCU lookup, we change chase the request->engine pointer, | |
65e4760e | 682 | * read the request->global_seqno and increment the reference count. |
5a198b8c CW |
683 | * |
684 | * The reference count is incremented atomically. If it is zero, | |
685 | * the lookup knows the request is unallocated and complete. Otherwise, | |
686 | * it is either still in use, or has been reallocated and reset | |
f54d1867 CW |
687 | * with dma_fence_init(). This increment is safe for release as we |
688 | * check that the request we have a reference to and matches the active | |
5a198b8c CW |
689 | * request. |
690 | * | |
691 | * Before we increment the refcount, we chase the request->engine | |
692 | * pointer. We must not call kmem_cache_zalloc() or else we set | |
693 | * that pointer to NULL and cause a crash during the lookup. If | |
694 | * we see the request is completed (based on the value of the | |
695 | * old engine and seqno), the lookup is complete and reports NULL. | |
696 | * If we decide the request is not completed (new engine or seqno), | |
697 | * then we grab a reference and double check that it is still the | |
698 | * active request - which it won't be and restart the lookup. | |
699 | * | |
700 | * Do not use kmem_cache_zalloc() here! | |
701 | */ | |
32eb6bcf | 702 | rq = kmem_cache_alloc(global.slab_requests, |
e61e0f51 CW |
703 | GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN); |
704 | if (unlikely(!rq)) { | |
d22ba0cb | 705 | rq = i915_request_alloc_slow(ce); |
e61e0f51 | 706 | if (!rq) { |
31c70f97 CW |
707 | ret = -ENOMEM; |
708 | goto err_unreserve; | |
709 | } | |
28176ef4 | 710 | } |
05235c53 | 711 | |
65fcb806 | 712 | INIT_LIST_HEAD(&rq->active_list); |
e8861964 | 713 | INIT_LIST_HEAD(&rq->execute_cb); |
ebece753 CW |
714 | |
715 | tl = ce->ring->timeline; | |
716 | ret = i915_timeline_get_seqno(tl, rq, &seqno); | |
717 | if (ret) | |
718 | goto err_free; | |
719 | ||
65fcb806 CW |
720 | rq->i915 = i915; |
721 | rq->engine = engine; | |
4e0d64db | 722 | rq->gem_context = ctx; |
1fc44d9b CW |
723 | rq->hw_context = ce; |
724 | rq->ring = ce->ring; | |
ebece753 | 725 | rq->timeline = tl; |
a89d1f92 | 726 | GEM_BUG_ON(rq->timeline == &engine->timeline); |
ebece753 CW |
727 | rq->hwsp_seqno = tl->hwsp_seqno; |
728 | rq->hwsp_cacheline = tl->hwsp_cacheline; | |
729 | rq->rcustate = get_state_synchronize_rcu(); /* acts as smp_mb() */ | |
73cb9701 | 730 | |
e61e0f51 | 731 | spin_lock_init(&rq->lock); |
ebece753 CW |
732 | dma_fence_init(&rq->fence, &i915_fence_ops, &rq->lock, |
733 | tl->fence_context, seqno); | |
04769652 | 734 | |
48bc2a4a | 735 | /* We bump the ref for the fence chain */ |
e61e0f51 | 736 | i915_sw_fence_init(&i915_request_get(rq)->submit, submit_notify); |
b7404c7e | 737 | i915_sw_fence_init(&i915_request_get(rq)->semaphore, semaphore_notify); |
5590af3e | 738 | |
0c7112a0 | 739 | i915_sched_node_init(&rq->sched); |
52e54209 | 740 | |
5a198b8c | 741 | /* No zalloc, must clear what we need by hand */ |
e61e0f51 CW |
742 | rq->file_priv = NULL; |
743 | rq->batch = NULL; | |
744 | rq->capture_list = NULL; | |
745 | rq->waitboost = false; | |
5a198b8c | 746 | |
05235c53 CW |
747 | /* |
748 | * Reserve space in the ring buffer for all the commands required to | |
749 | * eventually emit this request. This is to guarantee that the | |
e61e0f51 | 750 | * i915_request_add() call can't fail. Note that the reserve may need |
05235c53 CW |
751 | * to be redone if the request is not actually submitted straight |
752 | * away, e.g. because a GPU scheduler has deferred it. | |
ed2922c0 CW |
753 | * |
754 | * Note that due to how we add reserved_space to intel_ring_begin() | |
755 | * we need to double our request to ensure that if we need to wrap | |
756 | * around inside i915_request_add() there is sufficient space at | |
757 | * the beginning of the ring as well. | |
05235c53 | 758 | */ |
85474441 | 759 | rq->reserved_space = 2 * engine->emit_fini_breadcrumb_dw * sizeof(u32); |
05235c53 | 760 | |
2113184c CW |
761 | /* |
762 | * Record the position of the start of the request so that | |
d045446d CW |
763 | * should we detect the updated seqno part-way through the |
764 | * GPU processing the request, we never over-estimate the | |
765 | * position of the head. | |
766 | */ | |
e61e0f51 | 767 | rq->head = rq->ring->emit; |
d045446d | 768 | |
e61e0f51 | 769 | ret = engine->request_alloc(rq); |
b1c24a61 CW |
770 | if (ret) |
771 | goto err_unwind; | |
2113184c | 772 | |
b887d615 | 773 | /* Keep a second pin for the dual retirement along engine and ring */ |
1fc44d9b | 774 | __intel_context_pin(ce); |
b887d615 | 775 | |
b3ee09a4 CW |
776 | rq->infix = rq->ring->emit; /* end of header; start of user payload */ |
777 | ||
9b6586ae | 778 | /* Check that we didn't interrupt ourselves with a new request */ |
b66ea2c2 | 779 | lockdep_assert_held(&rq->timeline->mutex); |
e61e0f51 | 780 | GEM_BUG_ON(rq->timeline->seqno != rq->fence.seqno); |
b66ea2c2 CW |
781 | rq->cookie = lockdep_pin_lock(&rq->timeline->mutex); |
782 | ||
e61e0f51 | 783 | return rq; |
05235c53 | 784 | |
b1c24a61 | 785 | err_unwind: |
1fc44d9b | 786 | ce->ring->emit = rq->head; |
b1c24a61 | 787 | |
1618bdb8 | 788 | /* Make sure we didn't add ourselves to external state before freeing */ |
e61e0f51 | 789 | GEM_BUG_ON(!list_empty(&rq->active_list)); |
0c7112a0 CW |
790 | GEM_BUG_ON(!list_empty(&rq->sched.signalers_list)); |
791 | GEM_BUG_ON(!list_empty(&rq->sched.waiters_list)); | |
1618bdb8 | 792 | |
ebece753 | 793 | err_free: |
32eb6bcf | 794 | kmem_cache_free(global.slab_requests, rq); |
28176ef4 | 795 | err_unreserve: |
3ef71149 | 796 | mutex_unlock(&ce->ring->timeline->mutex); |
52d7f16e | 797 | unreserve_gt(i915); |
1fc44d9b | 798 | intel_context_unpin(ce); |
8e637178 | 799 | return ERR_PTR(ret); |
05235c53 CW |
800 | } |
801 | ||
e766fde6 CW |
802 | static int |
803 | i915_request_await_start(struct i915_request *rq, struct i915_request *signal) | |
804 | { | |
805 | if (list_is_first(&signal->ring_link, &signal->ring->request_list)) | |
806 | return 0; | |
807 | ||
808 | signal = list_prev_entry(signal, ring_link); | |
809 | if (i915_timeline_sync_is_later(rq->timeline, &signal->fence)) | |
810 | return 0; | |
811 | ||
812 | return i915_sw_fence_await_dma_fence(&rq->submit, | |
813 | &signal->fence, 0, | |
814 | I915_FENCE_GFP); | |
815 | } | |
816 | ||
2564fe70 CW |
817 | static intel_engine_mask_t |
818 | already_busywaiting(struct i915_request *rq) | |
819 | { | |
820 | /* | |
821 | * Polling a semaphore causes bus traffic, delaying other users of | |
822 | * both the GPU and CPU. We want to limit the impact on others, | |
823 | * while taking advantage of early submission to reduce GPU | |
824 | * latency. Therefore we restrict ourselves to not using more | |
825 | * than one semaphore from each source, and not using a semaphore | |
826 | * if we have detected the engine is saturated (i.e. would not be | |
827 | * submitted early and cause bus traffic reading an already passed | |
828 | * semaphore). | |
829 | * | |
830 | * See the are-we-too-late? check in __i915_request_submit(). | |
831 | */ | |
832 | return rq->sched.semaphores | rq->hw_context->saturated; | |
833 | } | |
834 | ||
e8861964 CW |
835 | static int |
836 | emit_semaphore_wait(struct i915_request *to, | |
837 | struct i915_request *from, | |
838 | gfp_t gfp) | |
839 | { | |
840 | u32 hwsp_offset; | |
841 | u32 *cs; | |
842 | int err; | |
843 | ||
844 | GEM_BUG_ON(!from->timeline->has_initial_breadcrumb); | |
845 | GEM_BUG_ON(INTEL_GEN(to->i915) < 8); | |
846 | ||
7881e605 | 847 | /* Just emit the first semaphore we see as request space is limited. */ |
2564fe70 | 848 | if (already_busywaiting(to) & from->engine->mask) |
7881e605 CW |
849 | return i915_sw_fence_await_dma_fence(&to->submit, |
850 | &from->fence, 0, | |
851 | I915_FENCE_GFP); | |
852 | ||
e766fde6 CW |
853 | err = i915_request_await_start(to, from); |
854 | if (err < 0) | |
855 | return err; | |
856 | ||
e8861964 CW |
857 | /* We need to pin the signaler's HWSP until we are finished reading. */ |
858 | err = i915_timeline_read_hwsp(from, to, &hwsp_offset); | |
859 | if (err) | |
860 | return err; | |
861 | ||
862 | /* Only submit our spinner after the signaler is running! */ | |
863 | err = i915_request_await_execution(to, from, gfp); | |
864 | if (err) | |
865 | return err; | |
866 | ||
867 | cs = intel_ring_begin(to, 4); | |
868 | if (IS_ERR(cs)) | |
869 | return PTR_ERR(cs); | |
870 | ||
871 | /* | |
872 | * Using greater-than-or-equal here means we have to worry | |
873 | * about seqno wraparound. To side step that issue, we swap | |
874 | * the timeline HWSP upon wrapping, so that everyone listening | |
875 | * for the old (pre-wrap) values do not see the much smaller | |
876 | * (post-wrap) values than they were expecting (and so wait | |
877 | * forever). | |
878 | */ | |
879 | *cs++ = MI_SEMAPHORE_WAIT | | |
880 | MI_SEMAPHORE_GLOBAL_GTT | | |
881 | MI_SEMAPHORE_POLL | | |
882 | MI_SEMAPHORE_SAD_GTE_SDD; | |
883 | *cs++ = from->fence.seqno; | |
884 | *cs++ = hwsp_offset; | |
885 | *cs++ = 0; | |
886 | ||
887 | intel_ring_advance(to, cs); | |
7881e605 CW |
888 | to->sched.semaphores |= from->engine->mask; |
889 | to->sched.flags |= I915_SCHED_HAS_SEMAPHORE_CHAIN; | |
e8861964 CW |
890 | return 0; |
891 | } | |
892 | ||
a2bc4695 | 893 | static int |
e61e0f51 | 894 | i915_request_await_request(struct i915_request *to, struct i915_request *from) |
a2bc4695 | 895 | { |
85e17f59 | 896 | int ret; |
a2bc4695 CW |
897 | |
898 | GEM_BUG_ON(to == from); | |
ceae14bd | 899 | GEM_BUG_ON(to->timeline == from->timeline); |
a2bc4695 | 900 | |
e61e0f51 | 901 | if (i915_request_completed(from)) |
ade0b0c9 CW |
902 | return 0; |
903 | ||
52e54209 | 904 | if (to->engine->schedule) { |
32eb6bcf | 905 | ret = i915_sched_node_add_dependency(&to->sched, &from->sched); |
52e54209 CW |
906 | if (ret < 0) |
907 | return ret; | |
908 | } | |
909 | ||
73cb9701 CW |
910 | if (to->engine == from->engine) { |
911 | ret = i915_sw_fence_await_sw_fence_gfp(&to->submit, | |
912 | &from->submit, | |
2abe2f84 | 913 | I915_FENCE_GFP); |
e8861964 CW |
914 | } else if (intel_engine_has_semaphores(to->engine) && |
915 | to->gem_context->sched.priority >= I915_PRIORITY_NORMAL) { | |
916 | ret = emit_semaphore_wait(to, from, I915_FENCE_GFP); | |
6faf5916 CW |
917 | } else { |
918 | ret = i915_sw_fence_await_dma_fence(&to->submit, | |
919 | &from->fence, 0, | |
920 | I915_FENCE_GFP); | |
a2bc4695 | 921 | } |
a491cc8e CW |
922 | if (ret < 0) |
923 | return ret; | |
924 | ||
925 | if (to->sched.flags & I915_SCHED_HAS_SEMAPHORE_CHAIN) { | |
926 | ret = i915_sw_fence_await_dma_fence(&to->semaphore, | |
927 | &from->fence, 0, | |
928 | I915_FENCE_GFP); | |
929 | if (ret < 0) | |
930 | return ret; | |
931 | } | |
a2bc4695 | 932 | |
a491cc8e | 933 | return 0; |
a2bc4695 CW |
934 | } |
935 | ||
b52992c0 | 936 | int |
e61e0f51 | 937 | i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence) |
b52992c0 | 938 | { |
29ef3fa9 CW |
939 | struct dma_fence **child = &fence; |
940 | unsigned int nchild = 1; | |
b52992c0 | 941 | int ret; |
b52992c0 | 942 | |
e61e0f51 CW |
943 | /* |
944 | * Note that if the fence-array was created in signal-on-any mode, | |
b52992c0 CW |
945 | * we should *not* decompose it into its individual fences. However, |
946 | * we don't currently store which mode the fence-array is operating | |
947 | * in. Fortunately, the only user of signal-on-any is private to | |
948 | * amdgpu and we should not see any incoming fence-array from | |
949 | * sync-file being in signal-on-any mode. | |
950 | */ | |
29ef3fa9 CW |
951 | if (dma_fence_is_array(fence)) { |
952 | struct dma_fence_array *array = to_dma_fence_array(fence); | |
953 | ||
954 | child = array->fences; | |
955 | nchild = array->num_fences; | |
956 | GEM_BUG_ON(!nchild); | |
957 | } | |
b52992c0 | 958 | |
29ef3fa9 CW |
959 | do { |
960 | fence = *child++; | |
961 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) | |
962 | continue; | |
b52992c0 | 963 | |
ceae14bd CW |
964 | /* |
965 | * Requests on the same timeline are explicitly ordered, along | |
e61e0f51 | 966 | * with their dependencies, by i915_request_add() which ensures |
ceae14bd CW |
967 | * that requests are submitted in-order through each ring. |
968 | */ | |
e61e0f51 | 969 | if (fence->context == rq->fence.context) |
ceae14bd CW |
970 | continue; |
971 | ||
47979480 | 972 | /* Squash repeated waits to the same timelines */ |
e61e0f51 | 973 | if (fence->context != rq->i915->mm.unordered_timeline && |
a89d1f92 | 974 | i915_timeline_sync_is_later(rq->timeline, fence)) |
47979480 CW |
975 | continue; |
976 | ||
29ef3fa9 | 977 | if (dma_fence_is_i915(fence)) |
e61e0f51 | 978 | ret = i915_request_await_request(rq, to_request(fence)); |
b52992c0 | 979 | else |
e61e0f51 | 980 | ret = i915_sw_fence_await_dma_fence(&rq->submit, fence, |
29ef3fa9 | 981 | I915_FENCE_TIMEOUT, |
2abe2f84 | 982 | I915_FENCE_GFP); |
b52992c0 CW |
983 | if (ret < 0) |
984 | return ret; | |
47979480 CW |
985 | |
986 | /* Record the latest fence used against each timeline */ | |
e61e0f51 | 987 | if (fence->context != rq->i915->mm.unordered_timeline) |
a89d1f92 | 988 | i915_timeline_sync_set(rq->timeline, fence); |
29ef3fa9 | 989 | } while (--nchild); |
b52992c0 CW |
990 | |
991 | return 0; | |
992 | } | |
993 | ||
a2bc4695 | 994 | /** |
e61e0f51 | 995 | * i915_request_await_object - set this request to (async) wait upon a bo |
a2bc4695 CW |
996 | * @to: request we are wishing to use |
997 | * @obj: object which may be in use on another ring. | |
d8802126 | 998 | * @write: whether the wait is on behalf of a writer |
a2bc4695 CW |
999 | * |
1000 | * This code is meant to abstract object synchronization with the GPU. | |
1001 | * Conceptually we serialise writes between engines inside the GPU. | |
1002 | * We only allow one engine to write into a buffer at any time, but | |
1003 | * multiple readers. To ensure each has a coherent view of memory, we must: | |
1004 | * | |
1005 | * - If there is an outstanding write request to the object, the new | |
1006 | * request must wait for it to complete (either CPU or in hw, requests | |
1007 | * on the same ring will be naturally ordered). | |
1008 | * | |
1009 | * - If we are a write request (pending_write_domain is set), the new | |
1010 | * request must wait for outstanding read requests to complete. | |
1011 | * | |
1012 | * Returns 0 if successful, else propagates up the lower layer error. | |
1013 | */ | |
1014 | int | |
e61e0f51 CW |
1015 | i915_request_await_object(struct i915_request *to, |
1016 | struct drm_i915_gem_object *obj, | |
1017 | bool write) | |
a2bc4695 | 1018 | { |
d07f0e59 CW |
1019 | struct dma_fence *excl; |
1020 | int ret = 0; | |
a2bc4695 CW |
1021 | |
1022 | if (write) { | |
d07f0e59 CW |
1023 | struct dma_fence **shared; |
1024 | unsigned int count, i; | |
1025 | ||
1026 | ret = reservation_object_get_fences_rcu(obj->resv, | |
1027 | &excl, &count, &shared); | |
1028 | if (ret) | |
1029 | return ret; | |
1030 | ||
1031 | for (i = 0; i < count; i++) { | |
e61e0f51 | 1032 | ret = i915_request_await_dma_fence(to, shared[i]); |
d07f0e59 CW |
1033 | if (ret) |
1034 | break; | |
1035 | ||
1036 | dma_fence_put(shared[i]); | |
1037 | } | |
1038 | ||
1039 | for (; i < count; i++) | |
1040 | dma_fence_put(shared[i]); | |
1041 | kfree(shared); | |
a2bc4695 | 1042 | } else { |
d07f0e59 | 1043 | excl = reservation_object_get_excl_rcu(obj->resv); |
a2bc4695 CW |
1044 | } |
1045 | ||
d07f0e59 CW |
1046 | if (excl) { |
1047 | if (ret == 0) | |
e61e0f51 | 1048 | ret = i915_request_await_dma_fence(to, excl); |
a2bc4695 | 1049 | |
d07f0e59 | 1050 | dma_fence_put(excl); |
a2bc4695 CW |
1051 | } |
1052 | ||
d07f0e59 | 1053 | return ret; |
a2bc4695 CW |
1054 | } |
1055 | ||
6dd7526f CW |
1056 | void i915_request_skip(struct i915_request *rq, int error) |
1057 | { | |
1058 | void *vaddr = rq->ring->vaddr; | |
1059 | u32 head; | |
1060 | ||
1061 | GEM_BUG_ON(!IS_ERR_VALUE((long)error)); | |
1062 | dma_fence_set_error(&rq->fence, error); | |
1063 | ||
1064 | /* | |
1065 | * As this request likely depends on state from the lost | |
1066 | * context, clear out all the user operations leaving the | |
1067 | * breadcrumb at the end (so we get the fence notifications). | |
1068 | */ | |
1069 | head = rq->infix; | |
1070 | if (rq->postfix < head) { | |
1071 | memset(vaddr + head, 0, rq->ring->size - head); | |
1072 | head = 0; | |
1073 | } | |
1074 | memset(vaddr + head, 0, rq->postfix - head); | |
1075 | } | |
1076 | ||
ea593dbb CW |
1077 | static struct i915_request * |
1078 | __i915_request_add_to_timeline(struct i915_request *rq) | |
1079 | { | |
1080 | struct i915_timeline *timeline = rq->timeline; | |
1081 | struct i915_request *prev; | |
1082 | ||
1083 | /* | |
1084 | * Dependency tracking and request ordering along the timeline | |
1085 | * is special cased so that we can eliminate redundant ordering | |
1086 | * operations while building the request (we know that the timeline | |
1087 | * itself is ordered, and here we guarantee it). | |
1088 | * | |
1089 | * As we know we will need to emit tracking along the timeline, | |
1090 | * we embed the hooks into our request struct -- at the cost of | |
1091 | * having to have specialised no-allocation interfaces (which will | |
1092 | * be beneficial elsewhere). | |
1093 | * | |
1094 | * A second benefit to open-coding i915_request_await_request is | |
1095 | * that we can apply a slight variant of the rules specialised | |
1096 | * for timelines that jump between engines (such as virtual engines). | |
1097 | * If we consider the case of virtual engine, we must emit a dma-fence | |
1098 | * to prevent scheduling of the second request until the first is | |
1099 | * complete (to maximise our greedy late load balancing) and this | |
1100 | * precludes optimising to use semaphores serialisation of a single | |
1101 | * timeline across engines. | |
1102 | */ | |
1103 | prev = i915_active_request_raw(&timeline->last_request, | |
1104 | &rq->i915->drm.struct_mutex); | |
1105 | if (prev && !i915_request_completed(prev)) { | |
1106 | if (is_power_of_2(prev->engine->mask | rq->engine->mask)) | |
1107 | i915_sw_fence_await_sw_fence(&rq->submit, | |
1108 | &prev->submit, | |
1109 | &rq->submitq); | |
1110 | else | |
1111 | __i915_sw_fence_await_dma_fence(&rq->submit, | |
1112 | &prev->fence, | |
1113 | &rq->dmaq); | |
1114 | if (rq->engine->schedule) | |
1115 | __i915_sched_node_add_dependency(&rq->sched, | |
1116 | &prev->sched, | |
1117 | &rq->dep, | |
1118 | 0); | |
1119 | } | |
1120 | ||
1121 | spin_lock_irq(&timeline->lock); | |
1122 | list_add_tail(&rq->link, &timeline->requests); | |
1123 | spin_unlock_irq(&timeline->lock); | |
1124 | ||
1125 | GEM_BUG_ON(timeline->seqno != rq->fence.seqno); | |
1126 | __i915_active_request_set(&timeline->last_request, rq); | |
1127 | ||
1128 | return prev; | |
1129 | } | |
1130 | ||
05235c53 CW |
1131 | /* |
1132 | * NB: This function is not allowed to fail. Doing so would mean the the | |
1133 | * request is not being tracked for completion but the work itself is | |
1134 | * going to happen on the hardware. This would be a Bad Thing(tm). | |
1135 | */ | |
697b9a87 | 1136 | void i915_request_add(struct i915_request *request) |
05235c53 | 1137 | { |
95b2ab56 | 1138 | struct intel_engine_cs *engine = request->engine; |
a89d1f92 | 1139 | struct i915_timeline *timeline = request->timeline; |
1fc44d9b | 1140 | struct intel_ring *ring = request->ring; |
e61e0f51 | 1141 | struct i915_request *prev; |
73dec95e | 1142 | u32 *cs; |
05235c53 | 1143 | |
dd847a70 | 1144 | GEM_TRACE("%s fence %llx:%lld\n", |
d9b13c4d CW |
1145 | engine->name, request->fence.context, request->fence.seqno); |
1146 | ||
3ef71149 | 1147 | lockdep_assert_held(&request->timeline->mutex); |
b66ea2c2 CW |
1148 | lockdep_unpin_lock(&request->timeline->mutex, request->cookie); |
1149 | ||
e61e0f51 | 1150 | trace_i915_request_add(request); |
0f25dff6 | 1151 | |
8ac71d1d CW |
1152 | /* |
1153 | * Make sure that no request gazumped us - if it was allocated after | |
e61e0f51 | 1154 | * our i915_request_alloc() and called __i915_request_add() before |
c781c978 CW |
1155 | * us, the timeline will hold its seqno which is later than ours. |
1156 | */ | |
9b6586ae | 1157 | GEM_BUG_ON(timeline->seqno != request->fence.seqno); |
c781c978 | 1158 | |
05235c53 CW |
1159 | /* |
1160 | * To ensure that this call will not fail, space for its emissions | |
1161 | * should already have been reserved in the ring buffer. Let the ring | |
1162 | * know that it is time to use that space up. | |
1163 | */ | |
ed2922c0 | 1164 | GEM_BUG_ON(request->reserved_space > request->ring->space); |
05235c53 | 1165 | request->reserved_space = 0; |
05235c53 | 1166 | |
8ac71d1d CW |
1167 | /* |
1168 | * Record the position of the start of the breadcrumb so that | |
05235c53 CW |
1169 | * should we detect the updated seqno part-way through the |
1170 | * GPU processing the request, we never over-estimate the | |
d045446d | 1171 | * position of the ring's HEAD. |
05235c53 | 1172 | */ |
85474441 | 1173 | cs = intel_ring_begin(request, engine->emit_fini_breadcrumb_dw); |
73dec95e TU |
1174 | GEM_BUG_ON(IS_ERR(cs)); |
1175 | request->postfix = intel_ring_offset(request, cs); | |
05235c53 | 1176 | |
ea593dbb | 1177 | prev = __i915_request_add_to_timeline(request); |
f2d13290 | 1178 | |
0f25dff6 | 1179 | list_add_tail(&request->ring_link, &ring->request_list); |
4daffb66 | 1180 | if (list_is_first(&request->ring_link, &ring->request_list)) |
643b450a | 1181 | list_add(&ring->active_link, &request->i915->gt.active_rings); |
c6eeb479 | 1182 | request->i915->gt.active_engines |= request->engine->mask; |
f2d13290 | 1183 | request->emitted_jiffies = jiffies; |
0f25dff6 | 1184 | |
8ac71d1d CW |
1185 | /* |
1186 | * Let the backend know a new request has arrived that may need | |
0de9136d CW |
1187 | * to adjust the existing execution schedule due to a high priority |
1188 | * request - i.e. we may want to preempt the current request in order | |
1189 | * to run a high priority dependency chain *before* we can execute this | |
1190 | * request. | |
1191 | * | |
1192 | * This is called before the request is ready to run so that we can | |
1193 | * decide whether to preempt the entire chain so that it is ready to | |
1194 | * run at the earliest possible convenience. | |
1195 | */ | |
71ace7ca | 1196 | local_bh_disable(); |
b7404c7e | 1197 | i915_sw_fence_commit(&request->semaphore); |
71ace7ca | 1198 | rcu_read_lock(); /* RCU serialisation for set-wedged protection */ |
b16c7651 CW |
1199 | if (engine->schedule) { |
1200 | struct i915_sched_attr attr = request->gem_context->sched; | |
1201 | ||
f9e9e9de CW |
1202 | /* |
1203 | * Boost actual workloads past semaphores! | |
1204 | * | |
1205 | * With semaphores we spin on one engine waiting for another, | |
1206 | * simply to reduce the latency of starting our work when | |
1207 | * the signaler completes. However, if there is any other | |
1208 | * work that we could be doing on this engine instead, that | |
1209 | * is better utilisation and will reduce the overall duration | |
1210 | * of the current work. To avoid PI boosting a semaphore | |
1211 | * far in the distance past over useful work, we keep a history | |
1212 | * of any semaphore use along our dependency chain. | |
1213 | */ | |
7881e605 | 1214 | if (!(request->sched.flags & I915_SCHED_HAS_SEMAPHORE_CHAIN)) |
f9e9e9de CW |
1215 | attr.priority |= I915_PRIORITY_NOSEMAPHORE; |
1216 | ||
b16c7651 CW |
1217 | /* |
1218 | * Boost priorities to new clients (new request flows). | |
1219 | * | |
1220 | * Allow interactive/synchronous clients to jump ahead of | |
1221 | * the bulk clients. (FQ_CODEL) | |
1222 | */ | |
1413b2bc | 1223 | if (list_empty(&request->sched.signalers_list)) |
c80274bb | 1224 | attr.priority |= I915_PRIORITY_WAIT; |
b16c7651 CW |
1225 | |
1226 | engine->schedule(request, &attr); | |
1227 | } | |
47650db0 | 1228 | rcu_read_unlock(); |
5590af3e CW |
1229 | i915_sw_fence_commit(&request->submit); |
1230 | local_bh_enable(); /* Kick the execlists tasklet if just scheduled */ | |
c22b355f CW |
1231 | |
1232 | /* | |
1233 | * In typical scenarios, we do not expect the previous request on | |
1234 | * the timeline to be still tracked by timeline->last_request if it | |
1235 | * has been completed. If the completed request is still here, that | |
1236 | * implies that request retirement is a long way behind submission, | |
1237 | * suggesting that we haven't been retiring frequently enough from | |
1238 | * the combination of retire-before-alloc, waiters and the background | |
1239 | * retirement worker. So if the last request on this timeline was | |
1240 | * already completed, do a catch up pass, flushing the retirement queue | |
1241 | * up to this client. Since we have now moved the heaviest operations | |
1242 | * during retirement onto secondary workers, such as freeing objects | |
1243 | * or contexts, retiring a bunch of requests is mostly list management | |
1244 | * (and cache misses), and so we should not be overly penalizing this | |
1245 | * client by performing excess work, though we may still performing | |
1246 | * work on behalf of others -- but instead we should benefit from | |
1247 | * improved resource management. (Well, that's the theory at least.) | |
1248 | */ | |
e61e0f51 CW |
1249 | if (prev && i915_request_completed(prev)) |
1250 | i915_request_retire_upto(prev); | |
3ef71149 CW |
1251 | |
1252 | mutex_unlock(&request->timeline->mutex); | |
05235c53 CW |
1253 | } |
1254 | ||
1255 | static unsigned long local_clock_us(unsigned int *cpu) | |
1256 | { | |
1257 | unsigned long t; | |
1258 | ||
e61e0f51 CW |
1259 | /* |
1260 | * Cheaply and approximately convert from nanoseconds to microseconds. | |
05235c53 CW |
1261 | * The result and subsequent calculations are also defined in the same |
1262 | * approximate microseconds units. The principal source of timing | |
1263 | * error here is from the simple truncation. | |
1264 | * | |
1265 | * Note that local_clock() is only defined wrt to the current CPU; | |
1266 | * the comparisons are no longer valid if we switch CPUs. Instead of | |
1267 | * blocking preemption for the entire busywait, we can detect the CPU | |
1268 | * switch and use that as indicator of system load and a reason to | |
1269 | * stop busywaiting, see busywait_stop(). | |
1270 | */ | |
1271 | *cpu = get_cpu(); | |
1272 | t = local_clock() >> 10; | |
1273 | put_cpu(); | |
1274 | ||
1275 | return t; | |
1276 | } | |
1277 | ||
1278 | static bool busywait_stop(unsigned long timeout, unsigned int cpu) | |
1279 | { | |
1280 | unsigned int this_cpu; | |
1281 | ||
1282 | if (time_after(local_clock_us(&this_cpu), timeout)) | |
1283 | return true; | |
1284 | ||
1285 | return this_cpu != cpu; | |
1286 | } | |
1287 | ||
52c0fdb2 CW |
1288 | static bool __i915_spin_request(const struct i915_request * const rq, |
1289 | int state, unsigned long timeout_us) | |
05235c53 | 1290 | { |
52c0fdb2 | 1291 | unsigned int cpu; |
b2f2f0fc CW |
1292 | |
1293 | /* | |
1294 | * Only wait for the request if we know it is likely to complete. | |
1295 | * | |
1296 | * We don't track the timestamps around requests, nor the average | |
1297 | * request length, so we do not have a good indicator that this | |
1298 | * request will complete within the timeout. What we do know is the | |
52c0fdb2 CW |
1299 | * order in which requests are executed by the context and so we can |
1300 | * tell if the request has been started. If the request is not even | |
1301 | * running yet, it is a fair assumption that it will not complete | |
1302 | * within our relatively short timeout. | |
b2f2f0fc | 1303 | */ |
52c0fdb2 | 1304 | if (!i915_request_is_running(rq)) |
b2f2f0fc CW |
1305 | return false; |
1306 | ||
e61e0f51 CW |
1307 | /* |
1308 | * When waiting for high frequency requests, e.g. during synchronous | |
05235c53 CW |
1309 | * rendering split between the CPU and GPU, the finite amount of time |
1310 | * required to set up the irq and wait upon it limits the response | |
1311 | * rate. By busywaiting on the request completion for a short while we | |
1312 | * can service the high frequency waits as quick as possible. However, | |
1313 | * if it is a slow request, we want to sleep as quickly as possible. | |
1314 | * The tradeoff between waiting and sleeping is roughly the time it | |
1315 | * takes to sleep on a request, on the order of a microsecond. | |
1316 | */ | |
1317 | ||
1318 | timeout_us += local_clock_us(&cpu); | |
1319 | do { | |
52c0fdb2 CW |
1320 | if (i915_request_completed(rq)) |
1321 | return true; | |
c33ed067 | 1322 | |
05235c53 CW |
1323 | if (signal_pending_state(state, current)) |
1324 | break; | |
1325 | ||
1326 | if (busywait_stop(timeout_us, cpu)) | |
1327 | break; | |
1328 | ||
f2f09a4c | 1329 | cpu_relax(); |
05235c53 CW |
1330 | } while (!need_resched()); |
1331 | ||
1332 | return false; | |
1333 | } | |
1334 | ||
52c0fdb2 CW |
1335 | struct request_wait { |
1336 | struct dma_fence_cb cb; | |
1337 | struct task_struct *tsk; | |
1338 | }; | |
1339 | ||
1340 | static void request_wait_wake(struct dma_fence *fence, struct dma_fence_cb *cb) | |
1341 | { | |
1342 | struct request_wait *wait = container_of(cb, typeof(*wait), cb); | |
1343 | ||
1344 | wake_up_process(wait->tsk); | |
1345 | } | |
1346 | ||
05235c53 | 1347 | /** |
e532be89 | 1348 | * i915_request_wait - wait until execution of request has finished |
e61e0f51 | 1349 | * @rq: the request to wait upon |
ea746f36 | 1350 | * @flags: how to wait |
e95433c7 CW |
1351 | * @timeout: how long to wait in jiffies |
1352 | * | |
e532be89 | 1353 | * i915_request_wait() waits for the request to be completed, for a |
e95433c7 CW |
1354 | * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an |
1355 | * unbounded wait). | |
05235c53 | 1356 | * |
e95433c7 CW |
1357 | * If the caller holds the struct_mutex, the caller must pass I915_WAIT_LOCKED |
1358 | * in via the flags, and vice versa if the struct_mutex is not held, the caller | |
1359 | * must not specify that the wait is locked. | |
05235c53 | 1360 | * |
e95433c7 CW |
1361 | * Returns the remaining time (in jiffies) if the request completed, which may |
1362 | * be zero or -ETIME if the request is unfinished after the timeout expires. | |
1363 | * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is | |
1364 | * pending before the request completes. | |
05235c53 | 1365 | */ |
e61e0f51 | 1366 | long i915_request_wait(struct i915_request *rq, |
e95433c7 CW |
1367 | unsigned int flags, |
1368 | long timeout) | |
05235c53 | 1369 | { |
ea746f36 CW |
1370 | const int state = flags & I915_WAIT_INTERRUPTIBLE ? |
1371 | TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE; | |
52c0fdb2 | 1372 | struct request_wait wait; |
05235c53 CW |
1373 | |
1374 | might_sleep(); | |
e95433c7 | 1375 | GEM_BUG_ON(timeout < 0); |
05235c53 | 1376 | |
e61e0f51 | 1377 | if (i915_request_completed(rq)) |
e95433c7 | 1378 | return timeout; |
05235c53 | 1379 | |
e95433c7 CW |
1380 | if (!timeout) |
1381 | return -ETIME; | |
05235c53 | 1382 | |
e61e0f51 | 1383 | trace_i915_request_wait_begin(rq, flags); |
4680816b | 1384 | |
52c0fdb2 CW |
1385 | /* Optimistic short spin before touching IRQs */ |
1386 | if (__i915_spin_request(rq, state, 5)) | |
1387 | goto out; | |
541ca6ed | 1388 | |
62eb3c24 CW |
1389 | /* |
1390 | * This client is about to stall waiting for the GPU. In many cases | |
1391 | * this is undesirable and limits the throughput of the system, as | |
1392 | * many clients cannot continue processing user input/output whilst | |
1393 | * blocked. RPS autotuning may take tens of milliseconds to respond | |
1394 | * to the GPU load and thus incurs additional latency for the client. | |
1395 | * We can circumvent that by promoting the GPU frequency to maximum | |
1396 | * before we sleep. This makes the GPU throttle up much more quickly | |
1397 | * (good for benchmarks and user experience, e.g. window animations), | |
1398 | * but at a cost of spending more power processing the workload | |
1399 | * (bad for battery). | |
1400 | */ | |
1401 | if (flags & I915_WAIT_PRIORITY) { | |
1402 | if (!i915_request_started(rq) && INTEL_GEN(rq->i915) >= 6) | |
1403 | gen6_rps_boost(rq); | |
b7404c7e | 1404 | local_bh_disable(); /* suspend tasklets for reprioritisation */ |
52c0fdb2 | 1405 | i915_schedule_bump_priority(rq, I915_PRIORITY_WAIT); |
b7404c7e | 1406 | local_bh_enable(); /* kick tasklets en masse */ |
62eb3c24 | 1407 | } |
4680816b | 1408 | |
52c0fdb2 CW |
1409 | wait.tsk = current; |
1410 | if (dma_fence_add_callback(&rq->fence, &wait.cb, request_wait_wake)) | |
1411 | goto out; | |
4680816b | 1412 | |
52c0fdb2 CW |
1413 | for (;;) { |
1414 | set_current_state(state); | |
05235c53 | 1415 | |
52c0fdb2 CW |
1416 | if (i915_request_completed(rq)) |
1417 | break; | |
05235c53 | 1418 | |
05235c53 | 1419 | if (signal_pending_state(state, current)) { |
e95433c7 | 1420 | timeout = -ERESTARTSYS; |
05235c53 CW |
1421 | break; |
1422 | } | |
1423 | ||
e95433c7 CW |
1424 | if (!timeout) { |
1425 | timeout = -ETIME; | |
05235c53 CW |
1426 | break; |
1427 | } | |
1428 | ||
e95433c7 | 1429 | timeout = io_schedule_timeout(timeout); |
05235c53 | 1430 | } |
a49625f9 | 1431 | __set_current_state(TASK_RUNNING); |
05235c53 | 1432 | |
52c0fdb2 CW |
1433 | dma_fence_remove_callback(&rq->fence, &wait.cb); |
1434 | ||
1435 | out: | |
1436 | trace_i915_request_wait_end(rq); | |
e95433c7 | 1437 | return timeout; |
05235c53 | 1438 | } |
4b8de8e6 | 1439 | |
e61e0f51 | 1440 | void i915_retire_requests(struct drm_i915_private *i915) |
4b8de8e6 | 1441 | { |
643b450a | 1442 | struct intel_ring *ring, *tmp; |
4b8de8e6 | 1443 | |
e61e0f51 | 1444 | lockdep_assert_held(&i915->drm.struct_mutex); |
4b8de8e6 | 1445 | |
e61e0f51 | 1446 | if (!i915->gt.active_requests) |
4b8de8e6 CW |
1447 | return; |
1448 | ||
65baf0ef CW |
1449 | list_for_each_entry_safe(ring, tmp, |
1450 | &i915->gt.active_rings, active_link) { | |
1451 | intel_ring_get(ring); /* last rq holds reference! */ | |
b887d615 | 1452 | ring_retire_requests(ring); |
65baf0ef CW |
1453 | intel_ring_put(ring); |
1454 | } | |
4b8de8e6 | 1455 | } |
c835c550 CW |
1456 | |
1457 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) | |
1458 | #include "selftests/mock_request.c" | |
e61e0f51 | 1459 | #include "selftests/i915_request.c" |
c835c550 | 1460 | #endif |
32eb6bcf | 1461 | |
103b76ee CW |
1462 | static void i915_global_request_shrink(void) |
1463 | { | |
1464 | kmem_cache_shrink(global.slab_dependencies); | |
1465 | kmem_cache_shrink(global.slab_execute_cbs); | |
1466 | kmem_cache_shrink(global.slab_requests); | |
1467 | } | |
1468 | ||
1469 | static void i915_global_request_exit(void) | |
1470 | { | |
1471 | kmem_cache_destroy(global.slab_dependencies); | |
1472 | kmem_cache_destroy(global.slab_execute_cbs); | |
1473 | kmem_cache_destroy(global.slab_requests); | |
1474 | } | |
1475 | ||
1476 | static struct i915_global_request global = { { | |
1477 | .shrink = i915_global_request_shrink, | |
1478 | .exit = i915_global_request_exit, | |
1479 | } }; | |
1480 | ||
32eb6bcf CW |
1481 | int __init i915_global_request_init(void) |
1482 | { | |
1483 | global.slab_requests = KMEM_CACHE(i915_request, | |
1484 | SLAB_HWCACHE_ALIGN | | |
1485 | SLAB_RECLAIM_ACCOUNT | | |
1486 | SLAB_TYPESAFE_BY_RCU); | |
1487 | if (!global.slab_requests) | |
1488 | return -ENOMEM; | |
1489 | ||
e8861964 CW |
1490 | global.slab_execute_cbs = KMEM_CACHE(execute_cb, |
1491 | SLAB_HWCACHE_ALIGN | | |
1492 | SLAB_RECLAIM_ACCOUNT | | |
1493 | SLAB_TYPESAFE_BY_RCU); | |
1494 | if (!global.slab_execute_cbs) | |
1495 | goto err_requests; | |
1496 | ||
32eb6bcf CW |
1497 | global.slab_dependencies = KMEM_CACHE(i915_dependency, |
1498 | SLAB_HWCACHE_ALIGN | | |
1499 | SLAB_RECLAIM_ACCOUNT); | |
1500 | if (!global.slab_dependencies) | |
e8861964 | 1501 | goto err_execute_cbs; |
32eb6bcf | 1502 | |
103b76ee | 1503 | i915_global_register(&global.base); |
32eb6bcf CW |
1504 | return 0; |
1505 | ||
e8861964 CW |
1506 | err_execute_cbs: |
1507 | kmem_cache_destroy(global.slab_execute_cbs); | |
32eb6bcf CW |
1508 | err_requests: |
1509 | kmem_cache_destroy(global.slab_requests); | |
1510 | return -ENOMEM; | |
1511 | } |