[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / i915_suspend.c

/*
 *
 * Copyright 2008 (c) Intel Corporation
 *   Jesse Barnes <jbarnes@virtuousgeek.org>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */

#include <drm/drmP.h>
#include <drm/i915_drm.h>
#include "intel_drv.h"
#include "i915_reg.h"

static void i915_save_display(struct drm_i915_private *dev_priv)
{
	/* Display arbitration control */
	if (INTEL_GEN(dev_priv) <= 4)
		dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);

	/* save FBC interval */
	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
		dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
}

static void i915_restore_display(struct drm_i915_private *dev_priv)
{
	/* Display arbitration */
	if (INTEL_GEN(dev_priv) <= 4)
		I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);

	/* only restore FBC info on the platform that supports FBC*/
	intel_fbc_global_disable(dev_priv);

	/* restore FBC interval */
	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
		I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);

	i915_redisable_vga(dev_priv);
}

int i915_save_state(struct drm_i915_private *dev_priv)
{
	struct pci_dev *pdev = dev_priv->drm.pdev;
	int i;

	mutex_lock(&dev_priv->drm.struct_mutex);

	i915_save_display(dev_priv);

	if (IS_GEN4(dev_priv))
		pci_read_config_word(pdev, GCDGMBUS,
				     &dev_priv->regfile.saveGCDGMBUS);

	/* Cache mode state */
	if (INTEL_GEN(dev_priv) < 7)
		dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);

	/* Memory Arbitration state */
	dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);

	/* Scratch space */
	if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) {
		for (i = 0; i < 7; i++) {
			dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
			dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
		}
		for (i = 0; i < 3; i++)
			dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
	} else if (IS_GEN2(dev_priv)) {
		for (i = 0; i < 7; i++)
			dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
	} else if (HAS_GMCH_DISPLAY(dev_priv)) {
		for (i = 0; i < 16; i++) {
			dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
			dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
		}
		for (i = 0; i < 3; i++)
			dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
	}

	mutex_unlock(&dev_priv->drm.struct_mutex);

	return 0;
}

int i915_restore_state(struct drm_i915_private *dev_priv)
{
	struct pci_dev *pdev = dev_priv->drm.pdev;
	int i;

	mutex_lock(&dev_priv->drm.struct_mutex);

	i915_gem_restore_fences(dev_priv);

	if (IS_GEN4(dev_priv))
		pci_write_config_word(pdev, GCDGMBUS,
				      dev_priv->regfile.saveGCDGMBUS);
	i915_restore_display(dev_priv);

	/* Cache mode state */
	if (INTEL_GEN(dev_priv) < 7)
		I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |
			   0xffff0000);

	/* Memory arbitration state */
	I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);

	/* Scratch space */
	if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) {
		for (i = 0; i < 7; i++) {
			I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
			I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
		}
		for (i = 0; i < 3; i++)
			I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
	} else if (IS_GEN2(dev_priv)) {
		for (i = 0; i < 7; i++)
			I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
	} else if (HAS_GMCH_DISPLAY(dev_priv)) {
		for (i = 0; i < 16; i++) {
			I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
			I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
		}
		for (i = 0; i < 3; i++)
			I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
	}

	mutex_unlock(&dev_priv->drm.struct_mutex);

	intel_i2c_reset(dev_priv);

	return 0;
}
Commit	Line	Data
317c35d1 JB	1	/*
	2	*
	3	* Copyright 2008 (c) Intel Corporation
	4	* Jesse Barnes <jbarnes@virtuousgeek.org>
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the
	8	* "Software"), to deal in the Software without restriction, including
	9	* without limitation the rights to use, copy, modify, merge, publish,
	10	* distribute, sub license, and/or sell copies of the Software, and to
	11	* permit persons to whom the Software is furnished to do so, subject to
	12	* the following conditions:
	13	*
	14	* The above copyright notice and this permission notice (including the
	15	* next paragraph) shall be included in all copies or substantial portions
	16	* of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
	19	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	20	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
	21	* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
	22	* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
	23	* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
	24	* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	25	*/
	26
760285e7 DH	27	#include <drm/drmP.h>
760285e7 DH	28	#include <drm/i915_drm.h>
f0217c42	29	#include "intel_drv.h"
5e5b7fa2	30	#include "i915_reg.h"
317c35d1	31
29b74b7f	32	static void i915_save_display(struct drm_i915_private *dev_priv)
fccdaba4	33	{
fccdaba4	34	/* Display arbitration control */
29b74b7f	35	if (INTEL_GEN(dev_priv) <= 4)
8de0add7	36	dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
fccdaba4	37
768cf7f4	38	/* save FBC interval */
9beb5fea	39	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
768cf7f4	40	dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
317c35d1 JB	41	}
317c35d1 JB	42
29b74b7f	43	static void i915_restore_display(struct drm_i915_private *dev_priv)
317c35d1	44	{
881ee988	45	/* Display arbitration */
29b74b7f	46	if (INTEL_GEN(dev_priv) <= 4)
8de0add7	47	I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
317c35d1	48
a2c459ee	49	/* only restore FBC info on the platform that supports FBC*/
c937ab3e	50	intel_fbc_global_disable(dev_priv);
768cf7f4 VS	51
768cf7f4 VS	52	/* restore FBC interval */
9beb5fea	53	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
768cf7f4	54	I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
a65e827d	55
29b74b7f	56	i915_redisable_vga(dev_priv);
1341d655 BG	57	}
1341d655 BG	58
af6dc742	59	int i915_save_state(struct drm_i915_private *dev_priv)
1341d655	60	{
52a05c30	61	struct pci_dev *pdev = dev_priv->drm.pdev;
1341d655 BG	62	int i;
1341d655 BG	63
af6dc742	64	mutex_lock(&dev_priv->drm.struct_mutex);
d70bed19	65
29b74b7f	66	i915_save_display(dev_priv);
1341d655	67
5db94019	68	if (IS_GEN4(dev_priv))
52a05c30	69	pci_read_config_word(pdev, GCDGMBUS,
9f49c376 JB	70	&dev_priv->regfile.saveGCDGMBUS);
9f49c376 JB	71
1341d655	72	/* Cache mode state */
29b74b7f	73	if (INTEL_GEN(dev_priv) < 7)
e8cde23b	74	dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
1341d655 BG	75
1341d655 BG	76	/* Memory Arbitration state */
f4c956ad	77	dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
1341d655 BG	78
1341d655 BG	79	/* Scratch space */
85fa792b VS	80	if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) {
	81	for (i = 0; i < 7; i++) {
	82	dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
	83	dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
	84	}
	85	for (i = 0; i < 3; i++)
	86	dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
	87	} else if (IS_GEN2(dev_priv)) {
	88	for (i = 0; i < 7; i++)
	89	dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
	90	} else if (HAS_GMCH_DISPLAY(dev_priv)) {
	91	for (i = 0; i < 16; i++) {
	92	dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
	93	dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
	94	}
	95	for (i = 0; i < 3; i++)
	96	dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
1341d655	97	}
1341d655	98
af6dc742	99	mutex_unlock(&dev_priv->drm.struct_mutex);
d70bed19	100
1341d655 BG	101	return 0;
	102	}
	103
af6dc742	104	int i915_restore_state(struct drm_i915_private *dev_priv)
1341d655	105	{
52a05c30	106	struct pci_dev *pdev = dev_priv->drm.pdev;
1341d655 BG	107	int i;
1341d655 BG	108
af6dc742	109	mutex_lock(&dev_priv->drm.struct_mutex);
d70bed19	110
4362f4f6	111	i915_gem_restore_fences(dev_priv);
9f49c376	112
5db94019	113	if (IS_GEN4(dev_priv))
52a05c30	114	pci_write_config_word(pdev, GCDGMBUS,
9f49c376	115	dev_priv->regfile.saveGCDGMBUS);
29b74b7f	116	i915_restore_display(dev_priv);
1341d655	117
317c35d1	118	/* Cache mode state */
29b74b7f	119	if (INTEL_GEN(dev_priv) < 7)
e8cde23b JB	120	I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 \|
e8cde23b JB	121	0xffff0000);
317c35d1 JB	122
317c35d1 JB	123	/* Memory arbitration state */
f4c956ad	124	I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE \| 0xffff0000);
317c35d1	125
85fa792b VS	126	/* Scratch space */
	127	if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) {
	128	for (i = 0; i < 7; i++) {
	129	I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
	130	I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
	131	}
	132	for (i = 0; i < 3; i++)
	133	I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
	134	} else if (IS_GEN2(dev_priv)) {
	135	for (i = 0; i < 7; i++)
	136	I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
	137	} else if (HAS_GMCH_DISPLAY(dev_priv)) {
	138	for (i = 0; i < 16; i++) {
	139	I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
	140	I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
	141	}
	142	for (i = 0; i < 3; i++)
	143	I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
317c35d1	144	}
317c35d1	145
af6dc742	146	mutex_unlock(&dev_priv->drm.struct_mutex);
d70bed19	147
af6dc742	148	intel_i2c_reset(dev_priv);
f0217c42	149
317c35d1 JB	150	return 0;
317c35d1 JB	151	}