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0136db58 BW |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/device.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/stat.h> | |
31 | #include <linux/sysfs.h> | |
84bc7581 | 32 | #include "intel_drv.h" |
0136db58 BW |
33 | #include "i915_drv.h" |
34 | ||
5bdebb18 | 35 | #define dev_to_drm_minor(d) dev_get_drvdata((d)) |
14c8d110 | 36 | |
5ab3633d | 37 | #ifdef CONFIG_PM |
f0f59a00 VS |
38 | static u32 calc_residency(struct drm_device *dev, |
39 | i915_reg_t reg) | |
0136db58 BW |
40 | { |
41 | struct drm_i915_private *dev_priv = dev->dev_private; | |
42 | u64 raw_time; /* 32b value may overflow during fixed point math */ | |
2cc9fab1 | 43 | u64 units = 128ULL, div = 100000ULL; |
c8c8fb33 | 44 | u32 ret; |
0136db58 BW |
45 | |
46 | if (!intel_enable_rc6(dev)) | |
47 | return 0; | |
48 | ||
c8c8fb33 PZ |
49 | intel_runtime_pm_get(dev_priv); |
50 | ||
542a6b20 | 51 | /* On VLV and CHV, residency time is in CZ units rather than 1.28us */ |
666a4537 | 52 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
2cc9fab1 VS |
53 | units = 1; |
54 | div = dev_priv->czclk_freq; | |
542a6b20 | 55 | |
e454a05d JB |
56 | if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH) |
57 | units <<= 8; | |
d8135109 ID |
58 | } else if (IS_BROXTON(dev)) { |
59 | units = 1; | |
60 | div = 1200; /* 833.33ns */ | |
e454a05d JB |
61 | } |
62 | ||
63 | raw_time = I915_READ(reg) * units; | |
c8c8fb33 PZ |
64 | ret = DIV_ROUND_UP_ULL(raw_time, div); |
65 | ||
c8c8fb33 PZ |
66 | intel_runtime_pm_put(dev_priv); |
67 | return ret; | |
0136db58 BW |
68 | } |
69 | ||
70 | static ssize_t | |
dbdfd8e9 | 71 | show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf) |
0136db58 | 72 | { |
14c8d110 | 73 | struct drm_minor *dminor = dev_to_drm_minor(kdev); |
3e2a1556 | 74 | return snprintf(buf, PAGE_SIZE, "%x\n", intel_enable_rc6(dminor->dev)); |
0136db58 BW |
75 | } |
76 | ||
77 | static ssize_t | |
dbdfd8e9 | 78 | show_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf) |
0136db58 | 79 | { |
5bdebb18 | 80 | struct drm_minor *dminor = dev_get_drvdata(kdev); |
0136db58 | 81 | u32 rc6_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6); |
3e2a1556 | 82 | return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency); |
0136db58 BW |
83 | } |
84 | ||
85 | static ssize_t | |
dbdfd8e9 | 86 | show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf) |
0136db58 | 87 | { |
14c8d110 | 88 | struct drm_minor *dminor = dev_to_drm_minor(kdev); |
0136db58 | 89 | u32 rc6p_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6p); |
3e2a1556 | 90 | return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency); |
0136db58 BW |
91 | } |
92 | ||
93 | static ssize_t | |
dbdfd8e9 | 94 | show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf) |
0136db58 | 95 | { |
14c8d110 | 96 | struct drm_minor *dminor = dev_to_drm_minor(kdev); |
0136db58 | 97 | u32 rc6pp_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6pp); |
3e2a1556 | 98 | return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency); |
0136db58 BW |
99 | } |
100 | ||
626ad6f3 VS |
101 | static ssize_t |
102 | show_media_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf) | |
103 | { | |
104 | struct drm_minor *dminor = dev_get_drvdata(kdev); | |
105 | u32 rc6_residency = calc_residency(dminor->dev, VLV_GT_MEDIA_RC6); | |
106 | return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency); | |
107 | } | |
108 | ||
0136db58 BW |
109 | static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL); |
110 | static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL); | |
111 | static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL); | |
112 | static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL); | |
626ad6f3 | 113 | static DEVICE_ATTR(media_rc6_residency_ms, S_IRUGO, show_media_rc6_ms, NULL); |
0136db58 BW |
114 | |
115 | static struct attribute *rc6_attrs[] = { | |
116 | &dev_attr_rc6_enable.attr, | |
117 | &dev_attr_rc6_residency_ms.attr, | |
0136db58 BW |
118 | NULL |
119 | }; | |
120 | ||
121 | static struct attribute_group rc6_attr_group = { | |
122 | .name = power_group_name, | |
123 | .attrs = rc6_attrs | |
124 | }; | |
58abf1da RV |
125 | |
126 | static struct attribute *rc6p_attrs[] = { | |
127 | &dev_attr_rc6p_residency_ms.attr, | |
128 | &dev_attr_rc6pp_residency_ms.attr, | |
129 | NULL | |
130 | }; | |
131 | ||
132 | static struct attribute_group rc6p_attr_group = { | |
133 | .name = power_group_name, | |
134 | .attrs = rc6p_attrs | |
135 | }; | |
626ad6f3 VS |
136 | |
137 | static struct attribute *media_rc6_attrs[] = { | |
138 | &dev_attr_media_rc6_residency_ms.attr, | |
139 | NULL | |
140 | }; | |
141 | ||
142 | static struct attribute_group media_rc6_attr_group = { | |
143 | .name = power_group_name, | |
144 | .attrs = media_rc6_attrs | |
145 | }; | |
8c3f929b | 146 | #endif |
0136db58 | 147 | |
84bc7581 BW |
148 | static int l3_access_valid(struct drm_device *dev, loff_t offset) |
149 | { | |
040d2baa | 150 | if (!HAS_L3_DPF(dev)) |
84bc7581 BW |
151 | return -EPERM; |
152 | ||
153 | if (offset % 4 != 0) | |
154 | return -EINVAL; | |
155 | ||
156 | if (offset >= GEN7_L3LOG_SIZE) | |
157 | return -ENXIO; | |
158 | ||
159 | return 0; | |
160 | } | |
161 | ||
162 | static ssize_t | |
163 | i915_l3_read(struct file *filp, struct kobject *kobj, | |
164 | struct bin_attribute *attr, char *buf, | |
165 | loff_t offset, size_t count) | |
166 | { | |
167 | struct device *dev = container_of(kobj, struct device, kobj); | |
14c8d110 | 168 | struct drm_minor *dminor = dev_to_drm_minor(dev); |
84bc7581 BW |
169 | struct drm_device *drm_dev = dminor->dev; |
170 | struct drm_i915_private *dev_priv = drm_dev->dev_private; | |
35a85ac6 | 171 | int slice = (int)(uintptr_t)attr->private; |
3ccfd19d | 172 | int ret; |
84bc7581 | 173 | |
1c3dcd1c BW |
174 | count = round_down(count, 4); |
175 | ||
84bc7581 BW |
176 | ret = l3_access_valid(drm_dev, offset); |
177 | if (ret) | |
178 | return ret; | |
179 | ||
e5ad4026 | 180 | count = min_t(size_t, GEN7_L3LOG_SIZE - offset, count); |
33618ea5 | 181 | |
84bc7581 BW |
182 | ret = i915_mutex_lock_interruptible(drm_dev); |
183 | if (ret) | |
184 | return ret; | |
185 | ||
3ccfd19d BW |
186 | if (dev_priv->l3_parity.remap_info[slice]) |
187 | memcpy(buf, | |
188 | dev_priv->l3_parity.remap_info[slice] + (offset/4), | |
189 | count); | |
190 | else | |
191 | memset(buf, 0, count); | |
84bc7581 | 192 | |
84bc7581 BW |
193 | mutex_unlock(&drm_dev->struct_mutex); |
194 | ||
1c966dd2 | 195 | return count; |
84bc7581 BW |
196 | } |
197 | ||
198 | static ssize_t | |
199 | i915_l3_write(struct file *filp, struct kobject *kobj, | |
200 | struct bin_attribute *attr, char *buf, | |
201 | loff_t offset, size_t count) | |
202 | { | |
203 | struct device *dev = container_of(kobj, struct device, kobj); | |
14c8d110 | 204 | struct drm_minor *dminor = dev_to_drm_minor(dev); |
84bc7581 BW |
205 | struct drm_device *drm_dev = dminor->dev; |
206 | struct drm_i915_private *dev_priv = drm_dev->dev_private; | |
273497e5 | 207 | struct intel_context *ctx; |
84bc7581 | 208 | u32 *temp = NULL; /* Just here to make handling failures easy */ |
35a85ac6 | 209 | int slice = (int)(uintptr_t)attr->private; |
84bc7581 BW |
210 | int ret; |
211 | ||
8245be31 BW |
212 | if (!HAS_HW_CONTEXTS(drm_dev)) |
213 | return -ENXIO; | |
214 | ||
84bc7581 BW |
215 | ret = l3_access_valid(drm_dev, offset); |
216 | if (ret) | |
217 | return ret; | |
218 | ||
219 | ret = i915_mutex_lock_interruptible(drm_dev); | |
220 | if (ret) | |
221 | return ret; | |
222 | ||
35a85ac6 | 223 | if (!dev_priv->l3_parity.remap_info[slice]) { |
84bc7581 BW |
224 | temp = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL); |
225 | if (!temp) { | |
226 | mutex_unlock(&drm_dev->struct_mutex); | |
227 | return -ENOMEM; | |
228 | } | |
229 | } | |
230 | ||
231 | ret = i915_gpu_idle(drm_dev); | |
232 | if (ret) { | |
233 | kfree(temp); | |
234 | mutex_unlock(&drm_dev->struct_mutex); | |
235 | return ret; | |
236 | } | |
237 | ||
238 | /* TODO: Ideally we really want a GPU reset here to make sure errors | |
239 | * aren't propagated. Since I cannot find a stable way to reset the GPU | |
240 | * at this point it is left as a TODO. | |
241 | */ | |
242 | if (temp) | |
35a85ac6 | 243 | dev_priv->l3_parity.remap_info[slice] = temp; |
84bc7581 | 244 | |
35a85ac6 | 245 | memcpy(dev_priv->l3_parity.remap_info[slice] + (offset/4), buf, count); |
84bc7581 | 246 | |
3ccfd19d BW |
247 | /* NB: We defer the remapping until we switch to the context */ |
248 | list_for_each_entry(ctx, &dev_priv->context_list, link) | |
249 | ctx->remap_slice |= (1<<slice); | |
84bc7581 BW |
250 | |
251 | mutex_unlock(&drm_dev->struct_mutex); | |
252 | ||
253 | return count; | |
254 | } | |
255 | ||
256 | static struct bin_attribute dpf_attrs = { | |
257 | .attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)}, | |
258 | .size = GEN7_L3LOG_SIZE, | |
259 | .read = i915_l3_read, | |
260 | .write = i915_l3_write, | |
35a85ac6 BW |
261 | .mmap = NULL, |
262 | .private = (void *)0 | |
263 | }; | |
264 | ||
265 | static struct bin_attribute dpf_attrs_1 = { | |
266 | .attr = {.name = "l3_parity_slice_1", .mode = (S_IRUSR | S_IWUSR)}, | |
267 | .size = GEN7_L3LOG_SIZE, | |
268 | .read = i915_l3_read, | |
269 | .write = i915_l3_write, | |
270 | .mmap = NULL, | |
271 | .private = (void *)1 | |
84bc7581 BW |
272 | }; |
273 | ||
c8c972eb | 274 | static ssize_t gt_act_freq_mhz_show(struct device *kdev, |
df6eedc8 BW |
275 | struct device_attribute *attr, char *buf) |
276 | { | |
14c8d110 | 277 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
df6eedc8 BW |
278 | struct drm_device *dev = minor->dev; |
279 | struct drm_i915_private *dev_priv = dev->dev_private; | |
280 | int ret; | |
281 | ||
5c9669ce TR |
282 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
283 | ||
d46c0517 ID |
284 | intel_runtime_pm_get(dev_priv); |
285 | ||
4fc688ce | 286 | mutex_lock(&dev_priv->rps.hw_lock); |
666a4537 | 287 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
177006a1 | 288 | u32 freq; |
64936258 | 289 | freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
7c59a9c1 | 290 | ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff); |
c8c972eb VS |
291 | } else { |
292 | u32 rpstat = I915_READ(GEN6_RPSTAT1); | |
ed64d66f AG |
293 | if (IS_GEN9(dev_priv)) |
294 | ret = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; | |
295 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
c8c972eb VS |
296 | ret = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
297 | else | |
298 | ret = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
7c59a9c1 | 299 | ret = intel_gpu_freq(dev_priv, ret); |
c8c972eb VS |
300 | } |
301 | mutex_unlock(&dev_priv->rps.hw_lock); | |
302 | ||
303 | intel_runtime_pm_put(dev_priv); | |
304 | ||
305 | return snprintf(buf, PAGE_SIZE, "%d\n", ret); | |
306 | } | |
307 | ||
308 | static ssize_t gt_cur_freq_mhz_show(struct device *kdev, | |
309 | struct device_attribute *attr, char *buf) | |
310 | { | |
311 | struct drm_minor *minor = dev_to_drm_minor(kdev); | |
312 | struct drm_device *dev = minor->dev; | |
313 | struct drm_i915_private *dev_priv = dev->dev_private; | |
314 | int ret; | |
315 | ||
316 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); | |
317 | ||
318 | intel_runtime_pm_get(dev_priv); | |
319 | ||
320 | mutex_lock(&dev_priv->rps.hw_lock); | |
7c59a9c1 | 321 | ret = intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq); |
4fc688ce | 322 | mutex_unlock(&dev_priv->rps.hw_lock); |
df6eedc8 | 323 | |
d46c0517 ID |
324 | intel_runtime_pm_put(dev_priv); |
325 | ||
3e2a1556 | 326 | return snprintf(buf, PAGE_SIZE, "%d\n", ret); |
df6eedc8 BW |
327 | } |
328 | ||
97e4eed7 CW |
329 | static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev, |
330 | struct device_attribute *attr, char *buf) | |
331 | { | |
14c8d110 | 332 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
97e4eed7 CW |
333 | struct drm_device *dev = minor->dev; |
334 | struct drm_i915_private *dev_priv = dev->dev_private; | |
335 | ||
7c59a9c1 VS |
336 | return snprintf(buf, PAGE_SIZE, |
337 | "%d\n", | |
338 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
97e4eed7 CW |
339 | } |
340 | ||
df6eedc8 BW |
341 | static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) |
342 | { | |
14c8d110 | 343 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
df6eedc8 BW |
344 | struct drm_device *dev = minor->dev; |
345 | struct drm_i915_private *dev_priv = dev->dev_private; | |
346 | int ret; | |
347 | ||
5c9669ce TR |
348 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
349 | ||
4fc688ce | 350 | mutex_lock(&dev_priv->rps.hw_lock); |
7c59a9c1 | 351 | ret = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
4fc688ce | 352 | mutex_unlock(&dev_priv->rps.hw_lock); |
df6eedc8 | 353 | |
3e2a1556 | 354 | return snprintf(buf, PAGE_SIZE, "%d\n", ret); |
df6eedc8 BW |
355 | } |
356 | ||
46ddf194 BW |
357 | static ssize_t gt_max_freq_mhz_store(struct device *kdev, |
358 | struct device_attribute *attr, | |
359 | const char *buf, size_t count) | |
360 | { | |
14c8d110 | 361 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
46ddf194 BW |
362 | struct drm_device *dev = minor->dev; |
363 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2a5913a8 | 364 | u32 val; |
46ddf194 BW |
365 | ssize_t ret; |
366 | ||
367 | ret = kstrtou32(buf, 0, &val); | |
368 | if (ret) | |
369 | return ret; | |
370 | ||
5c9669ce TR |
371 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
372 | ||
4fc688ce | 373 | mutex_lock(&dev_priv->rps.hw_lock); |
46ddf194 | 374 | |
7c59a9c1 | 375 | val = intel_freq_opcode(dev_priv, val); |
46ddf194 | 376 | |
2a5913a8 BW |
377 | if (val < dev_priv->rps.min_freq || |
378 | val > dev_priv->rps.max_freq || | |
b39fb297 | 379 | val < dev_priv->rps.min_freq_softlimit) { |
4fc688ce | 380 | mutex_unlock(&dev_priv->rps.hw_lock); |
46ddf194 BW |
381 | return -EINVAL; |
382 | } | |
383 | ||
2a5913a8 | 384 | if (val > dev_priv->rps.rp0_freq) |
31c77388 | 385 | DRM_DEBUG("User requested overclocking to %d\n", |
7c59a9c1 | 386 | intel_gpu_freq(dev_priv, val)); |
31c77388 | 387 | |
b39fb297 | 388 | dev_priv->rps.max_freq_softlimit = val; |
6917c7b9 | 389 | |
f745a80e VS |
390 | val = clamp_t(int, dev_priv->rps.cur_freq, |
391 | dev_priv->rps.min_freq_softlimit, | |
392 | dev_priv->rps.max_freq_softlimit); | |
393 | ||
394 | /* We still need *_set_rps to process the new max_delay and | |
395 | * update the interrupt limits and PMINTRMSK even though | |
396 | * frequency request may be unchanged. */ | |
ffe02b40 | 397 | intel_set_rps(dev, val); |
46ddf194 | 398 | |
4fc688ce | 399 | mutex_unlock(&dev_priv->rps.hw_lock); |
46ddf194 BW |
400 | |
401 | return count; | |
402 | } | |
403 | ||
df6eedc8 BW |
404 | static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) |
405 | { | |
14c8d110 | 406 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
df6eedc8 BW |
407 | struct drm_device *dev = minor->dev; |
408 | struct drm_i915_private *dev_priv = dev->dev_private; | |
409 | int ret; | |
410 | ||
5c9669ce TR |
411 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
412 | ||
4fc688ce | 413 | mutex_lock(&dev_priv->rps.hw_lock); |
7c59a9c1 | 414 | ret = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
4fc688ce | 415 | mutex_unlock(&dev_priv->rps.hw_lock); |
df6eedc8 | 416 | |
3e2a1556 | 417 | return snprintf(buf, PAGE_SIZE, "%d\n", ret); |
df6eedc8 BW |
418 | } |
419 | ||
46ddf194 BW |
420 | static ssize_t gt_min_freq_mhz_store(struct device *kdev, |
421 | struct device_attribute *attr, | |
422 | const char *buf, size_t count) | |
423 | { | |
14c8d110 | 424 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
46ddf194 BW |
425 | struct drm_device *dev = minor->dev; |
426 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2a5913a8 | 427 | u32 val; |
46ddf194 BW |
428 | ssize_t ret; |
429 | ||
430 | ret = kstrtou32(buf, 0, &val); | |
431 | if (ret) | |
432 | return ret; | |
433 | ||
5c9669ce TR |
434 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
435 | ||
4fc688ce | 436 | mutex_lock(&dev_priv->rps.hw_lock); |
46ddf194 | 437 | |
7c59a9c1 | 438 | val = intel_freq_opcode(dev_priv, val); |
0a073b84 | 439 | |
2a5913a8 BW |
440 | if (val < dev_priv->rps.min_freq || |
441 | val > dev_priv->rps.max_freq || | |
442 | val > dev_priv->rps.max_freq_softlimit) { | |
4fc688ce | 443 | mutex_unlock(&dev_priv->rps.hw_lock); |
46ddf194 BW |
444 | return -EINVAL; |
445 | } | |
446 | ||
b39fb297 | 447 | dev_priv->rps.min_freq_softlimit = val; |
6917c7b9 | 448 | |
f745a80e VS |
449 | val = clamp_t(int, dev_priv->rps.cur_freq, |
450 | dev_priv->rps.min_freq_softlimit, | |
451 | dev_priv->rps.max_freq_softlimit); | |
452 | ||
453 | /* We still need *_set_rps to process the new min_delay and | |
454 | * update the interrupt limits and PMINTRMSK even though | |
455 | * frequency request may be unchanged. */ | |
ffe02b40 | 456 | intel_set_rps(dev, val); |
46ddf194 | 457 | |
4fc688ce | 458 | mutex_unlock(&dev_priv->rps.hw_lock); |
46ddf194 BW |
459 | |
460 | return count; | |
461 | ||
462 | } | |
463 | ||
c8c972eb | 464 | static DEVICE_ATTR(gt_act_freq_mhz, S_IRUGO, gt_act_freq_mhz_show, NULL); |
df6eedc8 | 465 | static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL); |
46ddf194 BW |
466 | static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store); |
467 | static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store); | |
df6eedc8 | 468 | |
97e4eed7 | 469 | static DEVICE_ATTR(vlv_rpe_freq_mhz, S_IRUGO, vlv_rpe_freq_mhz_show, NULL); |
ac6ae347 BW |
470 | |
471 | static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf); | |
472 | static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL); | |
473 | static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL); | |
474 | static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL); | |
475 | ||
476 | /* For now we have a static number of RP states */ | |
477 | static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) | |
478 | { | |
14c8d110 | 479 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
ac6ae347 BW |
480 | struct drm_device *dev = minor->dev; |
481 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bc4d91f6 | 482 | u32 val; |
ac6ae347 | 483 | |
bc4d91f6 AG |
484 | if (attr == &dev_attr_gt_RP0_freq_mhz) |
485 | val = intel_gpu_freq(dev_priv, dev_priv->rps.rp0_freq); | |
486 | else if (attr == &dev_attr_gt_RP1_freq_mhz) | |
487 | val = intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq); | |
488 | else if (attr == &dev_attr_gt_RPn_freq_mhz) | |
489 | val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq); | |
490 | else | |
ac6ae347 | 491 | BUG(); |
bc4d91f6 | 492 | |
3e2a1556 | 493 | return snprintf(buf, PAGE_SIZE, "%d\n", val); |
ac6ae347 BW |
494 | } |
495 | ||
df6eedc8 | 496 | static const struct attribute *gen6_attrs[] = { |
c8c972eb | 497 | &dev_attr_gt_act_freq_mhz.attr, |
df6eedc8 BW |
498 | &dev_attr_gt_cur_freq_mhz.attr, |
499 | &dev_attr_gt_max_freq_mhz.attr, | |
500 | &dev_attr_gt_min_freq_mhz.attr, | |
ac6ae347 BW |
501 | &dev_attr_gt_RP0_freq_mhz.attr, |
502 | &dev_attr_gt_RP1_freq_mhz.attr, | |
503 | &dev_attr_gt_RPn_freq_mhz.attr, | |
df6eedc8 BW |
504 | NULL, |
505 | }; | |
506 | ||
97e4eed7 | 507 | static const struct attribute *vlv_attrs[] = { |
c8c972eb | 508 | &dev_attr_gt_act_freq_mhz.attr, |
97e4eed7 CW |
509 | &dev_attr_gt_cur_freq_mhz.attr, |
510 | &dev_attr_gt_max_freq_mhz.attr, | |
511 | &dev_attr_gt_min_freq_mhz.attr, | |
74c4f62b D |
512 | &dev_attr_gt_RP0_freq_mhz.attr, |
513 | &dev_attr_gt_RP1_freq_mhz.attr, | |
514 | &dev_attr_gt_RPn_freq_mhz.attr, | |
97e4eed7 CW |
515 | &dev_attr_vlv_rpe_freq_mhz.attr, |
516 | NULL, | |
517 | }; | |
518 | ||
ef86ddce MK |
519 | static ssize_t error_state_read(struct file *filp, struct kobject *kobj, |
520 | struct bin_attribute *attr, char *buf, | |
521 | loff_t off, size_t count) | |
522 | { | |
523 | ||
524 | struct device *kdev = container_of(kobj, struct device, kobj); | |
14c8d110 | 525 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
ef86ddce MK |
526 | struct drm_device *dev = minor->dev; |
527 | struct i915_error_state_file_priv error_priv; | |
528 | struct drm_i915_error_state_buf error_str; | |
529 | ssize_t ret_count = 0; | |
530 | int ret; | |
531 | ||
532 | memset(&error_priv, 0, sizeof(error_priv)); | |
533 | ||
0a4cd7c8 | 534 | ret = i915_error_state_buf_init(&error_str, to_i915(dev), count, off); |
ef86ddce MK |
535 | if (ret) |
536 | return ret; | |
537 | ||
538 | error_priv.dev = dev; | |
539 | i915_error_state_get(dev, &error_priv); | |
540 | ||
541 | ret = i915_error_state_to_str(&error_str, &error_priv); | |
542 | if (ret) | |
543 | goto out; | |
544 | ||
545 | ret_count = count < error_str.bytes ? count : error_str.bytes; | |
546 | ||
547 | memcpy(buf, error_str.buf, ret_count); | |
548 | out: | |
549 | i915_error_state_put(&error_priv); | |
550 | i915_error_state_buf_release(&error_str); | |
551 | ||
552 | return ret ?: ret_count; | |
553 | } | |
554 | ||
555 | static ssize_t error_state_write(struct file *file, struct kobject *kobj, | |
556 | struct bin_attribute *attr, char *buf, | |
557 | loff_t off, size_t count) | |
558 | { | |
559 | struct device *kdev = container_of(kobj, struct device, kobj); | |
14c8d110 | 560 | struct drm_minor *minor = dev_to_drm_minor(kdev); |
ef86ddce MK |
561 | struct drm_device *dev = minor->dev; |
562 | int ret; | |
563 | ||
564 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
565 | ||
566 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
567 | if (ret) | |
568 | return ret; | |
569 | ||
570 | i915_destroy_error_state(dev); | |
571 | mutex_unlock(&dev->struct_mutex); | |
572 | ||
573 | return count; | |
574 | } | |
575 | ||
576 | static struct bin_attribute error_state_attr = { | |
577 | .attr.name = "error", | |
578 | .attr.mode = S_IRUSR | S_IWUSR, | |
579 | .size = 0, | |
580 | .read = error_state_read, | |
581 | .write = error_state_write, | |
582 | }; | |
583 | ||
0136db58 BW |
584 | void i915_setup_sysfs(struct drm_device *dev) |
585 | { | |
586 | int ret; | |
587 | ||
8c3f929b | 588 | #ifdef CONFIG_PM |
58abf1da | 589 | if (HAS_RC6(dev)) { |
5bdebb18 | 590 | ret = sysfs_merge_group(&dev->primary->kdev->kobj, |
112abd29 DV |
591 | &rc6_attr_group); |
592 | if (ret) | |
593 | DRM_ERROR("RC6 residency sysfs setup failed\n"); | |
594 | } | |
58abf1da RV |
595 | if (HAS_RC6p(dev)) { |
596 | ret = sysfs_merge_group(&dev->primary->kdev->kobj, | |
597 | &rc6p_attr_group); | |
598 | if (ret) | |
599 | DRM_ERROR("RC6p residency sysfs setup failed\n"); | |
600 | } | |
666a4537 | 601 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
626ad6f3 VS |
602 | ret = sysfs_merge_group(&dev->primary->kdev->kobj, |
603 | &media_rc6_attr_group); | |
604 | if (ret) | |
605 | DRM_ERROR("Media RC6 residency sysfs setup failed\n"); | |
606 | } | |
8c3f929b | 607 | #endif |
040d2baa | 608 | if (HAS_L3_DPF(dev)) { |
5bdebb18 | 609 | ret = device_create_bin_file(dev->primary->kdev, &dpf_attrs); |
112abd29 DV |
610 | if (ret) |
611 | DRM_ERROR("l3 parity sysfs setup failed\n"); | |
35a85ac6 BW |
612 | |
613 | if (NUM_L3_SLICES(dev) > 1) { | |
5bdebb18 | 614 | ret = device_create_bin_file(dev->primary->kdev, |
35a85ac6 BW |
615 | &dpf_attrs_1); |
616 | if (ret) | |
617 | DRM_ERROR("l3 parity slice 1 setup failed\n"); | |
618 | } | |
112abd29 | 619 | } |
df6eedc8 | 620 | |
97e4eed7 | 621 | ret = 0; |
666a4537 | 622 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
5bdebb18 | 623 | ret = sysfs_create_files(&dev->primary->kdev->kobj, vlv_attrs); |
97e4eed7 | 624 | else if (INTEL_INFO(dev)->gen >= 6) |
5bdebb18 | 625 | ret = sysfs_create_files(&dev->primary->kdev->kobj, gen6_attrs); |
97e4eed7 CW |
626 | if (ret) |
627 | DRM_ERROR("RPS sysfs setup failed\n"); | |
ef86ddce | 628 | |
5bdebb18 | 629 | ret = sysfs_create_bin_file(&dev->primary->kdev->kobj, |
ef86ddce MK |
630 | &error_state_attr); |
631 | if (ret) | |
632 | DRM_ERROR("error_state sysfs setup failed\n"); | |
0136db58 BW |
633 | } |
634 | ||
635 | void i915_teardown_sysfs(struct drm_device *dev) | |
636 | { | |
5bdebb18 | 637 | sysfs_remove_bin_file(&dev->primary->kdev->kobj, &error_state_attr); |
666a4537 | 638 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
5bdebb18 | 639 | sysfs_remove_files(&dev->primary->kdev->kobj, vlv_attrs); |
97e4eed7 | 640 | else |
5bdebb18 DA |
641 | sysfs_remove_files(&dev->primary->kdev->kobj, gen6_attrs); |
642 | device_remove_bin_file(dev->primary->kdev, &dpf_attrs_1); | |
643 | device_remove_bin_file(dev->primary->kdev, &dpf_attrs); | |
853c70e8 | 644 | #ifdef CONFIG_PM |
5bdebb18 | 645 | sysfs_unmerge_group(&dev->primary->kdev->kobj, &rc6_attr_group); |
58abf1da | 646 | sysfs_unmerge_group(&dev->primary->kdev->kobj, &rc6p_attr_group); |
853c70e8 | 647 | #endif |
0136db58 | 648 | } |