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drm/i915: reorganize the unclaimed register detection code
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79e53945 1/*
39507259 2 * Copyright © 2006 Intel Corporation
79e53945
JB
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
25e341cf 27#include <linux/dmi.h>
9f0e7ff4 28#include <drm/drm_dp_helper.h>
760285e7
DH
29#include <drm/drmP.h>
30#include <drm/i915_drm.h>
79e53945
JB
31#include "i915_drv.h"
32#include "intel_bios.h"
33
9b9d172d 34#define SLAVE_ADDR1 0x70
35#define SLAVE_ADDR2 0x72
79e53945 36
500a8cc4
ZW
37static int panel_type;
38
79e53945
JB
39static void *
40find_section(struct bdb_header *bdb, int section_id)
41{
42 u8 *base = (u8 *)bdb;
43 int index = 0;
44 u16 total, current_size;
45 u8 current_id;
46
47 /* skip to first section */
48 index += bdb->header_size;
49 total = bdb->bdb_size;
50
51 /* walk the sections looking for section_id */
d1f13fd2 52 while (index + 3 < total) {
79e53945
JB
53 current_id = *(base + index);
54 index++;
d1f13fd2 55
79e53945
JB
56 current_size = *((u16 *)(base + index));
57 index += 2;
d1f13fd2
CW
58
59 if (index + current_size > total)
60 return NULL;
61
79e53945
JB
62 if (current_id == section_id)
63 return base + index;
d1f13fd2 64
79e53945
JB
65 index += current_size;
66 }
67
68 return NULL;
69}
70
db545019
DMEA
71static u16
72get_blocksize(void *p)
73{
74 u16 *block_ptr, block_size;
75
76 block_ptr = (u16 *)((char *)p - 2);
77 block_size = *block_ptr;
78 return block_size;
79}
80
79e53945 81static void
88631706 82fill_detail_timing_data(struct drm_display_mode *panel_fixed_mode,
99834ea4 83 const struct lvds_dvo_timing *dvo_timing)
88631706
ML
84{
85 panel_fixed_mode->hdisplay = (dvo_timing->hactive_hi << 8) |
86 dvo_timing->hactive_lo;
87 panel_fixed_mode->hsync_start = panel_fixed_mode->hdisplay +
88 ((dvo_timing->hsync_off_hi << 8) | dvo_timing->hsync_off_lo);
89 panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start +
90 dvo_timing->hsync_pulse_width;
91 panel_fixed_mode->htotal = panel_fixed_mode->hdisplay +
92 ((dvo_timing->hblank_hi << 8) | dvo_timing->hblank_lo);
93
94 panel_fixed_mode->vdisplay = (dvo_timing->vactive_hi << 8) |
95 dvo_timing->vactive_lo;
96 panel_fixed_mode->vsync_start = panel_fixed_mode->vdisplay +
97 dvo_timing->vsync_off;
98 panel_fixed_mode->vsync_end = panel_fixed_mode->vsync_start +
99 dvo_timing->vsync_pulse_width;
100 panel_fixed_mode->vtotal = panel_fixed_mode->vdisplay +
101 ((dvo_timing->vblank_hi << 8) | dvo_timing->vblank_lo);
102 panel_fixed_mode->clock = dvo_timing->clock * 10;
103 panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED;
104
9bc35499
AJ
105 if (dvo_timing->hsync_positive)
106 panel_fixed_mode->flags |= DRM_MODE_FLAG_PHSYNC;
107 else
108 panel_fixed_mode->flags |= DRM_MODE_FLAG_NHSYNC;
109
110 if (dvo_timing->vsync_positive)
111 panel_fixed_mode->flags |= DRM_MODE_FLAG_PVSYNC;
112 else
113 panel_fixed_mode->flags |= DRM_MODE_FLAG_NVSYNC;
114
88631706
ML
115 /* Some VBTs have bogus h/vtotal values */
116 if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal)
117 panel_fixed_mode->htotal = panel_fixed_mode->hsync_end + 1;
118 if (panel_fixed_mode->vsync_end > panel_fixed_mode->vtotal)
119 panel_fixed_mode->vtotal = panel_fixed_mode->vsync_end + 1;
120
121 drm_mode_set_name(panel_fixed_mode);
122}
123
99834ea4
CW
124static bool
125lvds_dvo_timing_equal_size(const struct lvds_dvo_timing *a,
126 const struct lvds_dvo_timing *b)
127{
128 if (a->hactive_hi != b->hactive_hi ||
129 a->hactive_lo != b->hactive_lo)
130 return false;
131
132 if (a->hsync_off_hi != b->hsync_off_hi ||
133 a->hsync_off_lo != b->hsync_off_lo)
134 return false;
135
136 if (a->hsync_pulse_width != b->hsync_pulse_width)
137 return false;
138
139 if (a->hblank_hi != b->hblank_hi ||
140 a->hblank_lo != b->hblank_lo)
141 return false;
142
143 if (a->vactive_hi != b->vactive_hi ||
144 a->vactive_lo != b->vactive_lo)
145 return false;
146
147 if (a->vsync_off != b->vsync_off)
148 return false;
149
150 if (a->vsync_pulse_width != b->vsync_pulse_width)
151 return false;
152
153 if (a->vblank_hi != b->vblank_hi ||
154 a->vblank_lo != b->vblank_lo)
155 return false;
156
157 return true;
158}
159
160static const struct lvds_dvo_timing *
161get_lvds_dvo_timing(const struct bdb_lvds_lfp_data *lvds_lfp_data,
162 const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs,
163 int index)
164{
165 /*
166 * the size of fp_timing varies on the different platform.
167 * So calculate the DVO timing relative offset in LVDS data
168 * entry to get the DVO timing entry
169 */
170
171 int lfp_data_size =
172 lvds_lfp_data_ptrs->ptr[1].dvo_timing_offset -
173 lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset;
174 int dvo_timing_offset =
175 lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset -
176 lvds_lfp_data_ptrs->ptr[0].fp_timing_offset;
177 char *entry = (char *)lvds_lfp_data->data + lfp_data_size * index;
178
179 return (struct lvds_dvo_timing *)(entry + dvo_timing_offset);
180}
181
b0354385
TI
182/* get lvds_fp_timing entry
183 * this function may return NULL if the corresponding entry is invalid
184 */
185static const struct lvds_fp_timing *
186get_lvds_fp_timing(const struct bdb_header *bdb,
187 const struct bdb_lvds_lfp_data *data,
188 const struct bdb_lvds_lfp_data_ptrs *ptrs,
189 int index)
190{
191 size_t data_ofs = (const u8 *)data - (const u8 *)bdb;
192 u16 data_size = ((const u16 *)data)[-1]; /* stored in header */
193 size_t ofs;
194
195 if (index >= ARRAY_SIZE(ptrs->ptr))
196 return NULL;
197 ofs = ptrs->ptr[index].fp_timing_offset;
198 if (ofs < data_ofs ||
199 ofs + sizeof(struct lvds_fp_timing) > data_ofs + data_size)
200 return NULL;
201 return (const struct lvds_fp_timing *)((const u8 *)bdb + ofs);
202}
203
88631706
ML
204/* Try to find integrated panel data */
205static void
206parse_lfp_panel_data(struct drm_i915_private *dev_priv,
207 struct bdb_header *bdb)
79e53945 208{
99834ea4
CW
209 const struct bdb_lvds_options *lvds_options;
210 const struct bdb_lvds_lfp_data *lvds_lfp_data;
211 const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs;
212 const struct lvds_dvo_timing *panel_dvo_timing;
b0354385 213 const struct lvds_fp_timing *fp_timing;
79e53945 214 struct drm_display_mode *panel_fixed_mode;
83a7280e 215 int i, downclock, drrs_mode;
79e53945 216
79e53945
JB
217 lvds_options = find_section(bdb, BDB_LVDS_OPTIONS);
218 if (!lvds_options)
219 return;
220
41aa3448 221 dev_priv->vbt.lvds_dither = lvds_options->pixel_dither;
79e53945
JB
222 if (lvds_options->panel_type == 0xff)
223 return;
6a04002b 224
500a8cc4 225 panel_type = lvds_options->panel_type;
79e53945 226
83a7280e
PB
227 drrs_mode = (lvds_options->dps_panel_type_bits
228 >> (panel_type * 2)) & MODE_MASK;
229 /*
230 * VBT has static DRRS = 0 and seamless DRRS = 2.
231 * The below piece of code is required to adjust vbt.drrs_type
232 * to match the enum drrs_support_type.
233 */
234 switch (drrs_mode) {
235 case 0:
236 dev_priv->vbt.drrs_type = STATIC_DRRS_SUPPORT;
237 DRM_DEBUG_KMS("DRRS supported mode is static\n");
238 break;
239 case 2:
240 dev_priv->vbt.drrs_type = SEAMLESS_DRRS_SUPPORT;
241 DRM_DEBUG_KMS("DRRS supported mode is seamless\n");
242 break;
243 default:
244 dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
245 DRM_DEBUG_KMS("DRRS not supported (VBT input)\n");
246 break;
247 }
248
79e53945
JB
249 lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA);
250 if (!lvds_lfp_data)
251 return;
252
1b16de0b
JB
253 lvds_lfp_data_ptrs = find_section(bdb, BDB_LVDS_LFP_DATA_PTRS);
254 if (!lvds_lfp_data_ptrs)
255 return;
256
41aa3448 257 dev_priv->vbt.lvds_vbt = 1;
79e53945 258
99834ea4
CW
259 panel_dvo_timing = get_lvds_dvo_timing(lvds_lfp_data,
260 lvds_lfp_data_ptrs,
261 lvds_options->panel_type);
79e53945 262
9a298b2a 263 panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
6edc3242
CW
264 if (!panel_fixed_mode)
265 return;
79e53945 266
99834ea4 267 fill_detail_timing_data(panel_fixed_mode, panel_dvo_timing);
79e53945 268
41aa3448 269 dev_priv->vbt.lfp_lvds_vbt_mode = panel_fixed_mode;
79e53945 270
28c97730 271 DRM_DEBUG_KMS("Found panel mode in BIOS VBT tables:\n");
88631706 272 drm_mode_debug_printmodeline(panel_fixed_mode);
37df9673 273
d1fcea6a 274 /*
99834ea4
CW
275 * Iterate over the LVDS panel timing info to find the lowest clock
276 * for the native resolution.
d1fcea6a 277 */
99834ea4 278 downclock = panel_dvo_timing->clock;
d1fcea6a 279 for (i = 0; i < 16; i++) {
99834ea4
CW
280 const struct lvds_dvo_timing *dvo_timing;
281
282 dvo_timing = get_lvds_dvo_timing(lvds_lfp_data,
283 lvds_lfp_data_ptrs,
284 i);
285 if (lvds_dvo_timing_equal_size(dvo_timing, panel_dvo_timing) &&
286 dvo_timing->clock < downclock)
287 downclock = dvo_timing->clock;
d1fcea6a 288 }
99834ea4 289
d330a953 290 if (downclock < panel_dvo_timing->clock && i915.lvds_downclock) {
d1fcea6a 291 dev_priv->lvds_downclock_avail = 1;
99834ea4 292 dev_priv->lvds_downclock = downclock * 10;
bbb0aef5
JP
293 DRM_DEBUG_KMS("LVDS downclock is found in VBT. "
294 "Normal Clock %dKHz, downclock %dKHz\n",
99834ea4 295 panel_fixed_mode->clock, 10*downclock);
d1fcea6a 296 }
b0354385
TI
297
298 fp_timing = get_lvds_fp_timing(bdb, lvds_lfp_data,
299 lvds_lfp_data_ptrs,
300 lvds_options->panel_type);
301 if (fp_timing) {
302 /* check the resolution, just to be sure */
303 if (fp_timing->x_res == panel_fixed_mode->hdisplay &&
304 fp_timing->y_res == panel_fixed_mode->vdisplay) {
41aa3448 305 dev_priv->vbt.bios_lvds_val = fp_timing->lvds_reg_val;
b0354385 306 DRM_DEBUG_KMS("VBT initial LVDS value %x\n",
41aa3448 307 dev_priv->vbt.bios_lvds_val);
b0354385
TI
308 }
309 }
88631706
ML
310}
311
f00076d2
JN
312static void
313parse_lfp_backlight(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
314{
315 const struct bdb_lfp_backlight_data *backlight_data;
316 const struct bdb_lfp_backlight_data_entry *entry;
317
318 backlight_data = find_section(bdb, BDB_LVDS_BACKLIGHT);
319 if (!backlight_data)
320 return;
321
322 if (backlight_data->entry_size != sizeof(backlight_data->data[0])) {
323 DRM_DEBUG_KMS("Unsupported backlight data entry size %u\n",
324 backlight_data->entry_size);
325 return;
326 }
327
328 entry = &backlight_data->data[panel_type];
329
39fbc9c8
JN
330 dev_priv->vbt.backlight.present = entry->type == BDB_BACKLIGHT_TYPE_PWM;
331 if (!dev_priv->vbt.backlight.present) {
332 DRM_DEBUG_KMS("PWM backlight not present in VBT (type %u)\n",
333 entry->type);
334 return;
335 }
336
f00076d2
JN
337 dev_priv->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz;
338 dev_priv->vbt.backlight.active_low_pwm = entry->active_low_pwm;
339 DRM_DEBUG_KMS("VBT backlight PWM modulation frequency %u Hz, "
340 "active %s, min brightness %u, level %u\n",
341 dev_priv->vbt.backlight.pwm_freq_hz,
342 dev_priv->vbt.backlight.active_low_pwm ? "low" : "high",
343 entry->min_brightness,
344 backlight_data->level[panel_type]);
345}
346
88631706
ML
347/* Try to find sdvo panel data */
348static void
349parse_sdvo_panel_data(struct drm_i915_private *dev_priv,
350 struct bdb_header *bdb)
351{
88631706
ML
352 struct lvds_dvo_timing *dvo_timing;
353 struct drm_display_mode *panel_fixed_mode;
5a1e5b6c 354 int index;
79e53945 355
d330a953 356 index = i915.vbt_sdvo_panel_type;
c10e408a
MF
357 if (index == -2) {
358 DRM_DEBUG_KMS("Ignore SDVO panel mode from BIOS VBT tables.\n");
359 return;
360 }
361
5a1e5b6c
CW
362 if (index == -1) {
363 struct bdb_sdvo_lvds_options *sdvo_lvds_options;
364
365 sdvo_lvds_options = find_section(bdb, BDB_SDVO_LVDS_OPTIONS);
366 if (!sdvo_lvds_options)
367 return;
368
369 index = sdvo_lvds_options->panel_type;
370 }
88631706
ML
371
372 dvo_timing = find_section(bdb, BDB_SDVO_PANEL_DTDS);
373 if (!dvo_timing)
374 return;
375
9a298b2a 376 panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
88631706
ML
377 if (!panel_fixed_mode)
378 return;
379
5a1e5b6c 380 fill_detail_timing_data(panel_fixed_mode, dvo_timing + index);
88631706 381
41aa3448 382 dev_priv->vbt.sdvo_lvds_vbt_mode = panel_fixed_mode;
79e53945 383
5a1e5b6c
CW
384 DRM_DEBUG_KMS("Found SDVO panel mode in BIOS VBT tables:\n");
385 drm_mode_debug_printmodeline(panel_fixed_mode);
79e53945
JB
386}
387
9a4114ff
BF
388static int intel_bios_ssc_frequency(struct drm_device *dev,
389 bool alternate)
390{
391 switch (INTEL_INFO(dev)->gen) {
392 case 2:
e91e941b 393 return alternate ? 66667 : 48000;
9a4114ff
BF
394 case 3:
395 case 4:
e91e941b 396 return alternate ? 100000 : 96000;
9a4114ff 397 default:
e91e941b 398 return alternate ? 100000 : 120000;
9a4114ff
BF
399 }
400}
401
79e53945
JB
402static void
403parse_general_features(struct drm_i915_private *dev_priv,
404 struct bdb_header *bdb)
405{
bad720ff 406 struct drm_device *dev = dev_priv->dev;
79e53945
JB
407 struct bdb_general_features *general;
408
79e53945
JB
409 general = find_section(bdb, BDB_GENERAL_FEATURES);
410 if (general) {
41aa3448
RV
411 dev_priv->vbt.int_tv_support = general->int_tv_support;
412 dev_priv->vbt.int_crt_support = general->int_crt_support;
413 dev_priv->vbt.lvds_use_ssc = general->enable_ssc;
414 dev_priv->vbt.lvds_ssc_freq =
9a4114ff 415 intel_bios_ssc_frequency(dev, general->ssc_freq);
41aa3448
RV
416 dev_priv->vbt.display_clock_mode = general->display_clock_mode;
417 dev_priv->vbt.fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted;
3f704fa2 418 DRM_DEBUG_KMS("BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d fdi_rx_polarity_inverted %d\n",
41aa3448
RV
419 dev_priv->vbt.int_tv_support,
420 dev_priv->vbt.int_crt_support,
421 dev_priv->vbt.lvds_use_ssc,
422 dev_priv->vbt.lvds_ssc_freq,
423 dev_priv->vbt.display_clock_mode,
424 dev_priv->vbt.fdi_rx_polarity_inverted);
79e53945
JB
425 }
426}
427
db545019
DMEA
428static void
429parse_general_definitions(struct drm_i915_private *dev_priv,
430 struct bdb_header *bdb)
431{
432 struct bdb_general_definitions *general;
db545019 433
db545019
DMEA
434 general = find_section(bdb, BDB_GENERAL_DEFINITIONS);
435 if (general) {
436 u16 block_size = get_blocksize(general);
437 if (block_size >= sizeof(*general)) {
438 int bus_pin = general->crt_ddc_gmbus_pin;
28c97730 439 DRM_DEBUG_KMS("crt_ddc_bus_pin: %d\n", bus_pin);
3bd7d909 440 if (intel_gmbus_is_port_valid(bus_pin))
41aa3448 441 dev_priv->vbt.crt_ddc_pin = bus_pin;
db545019 442 } else {
28c97730 443 DRM_DEBUG_KMS("BDB_GD too small (%d). Invalid.\n",
3bd7d909 444 block_size);
db545019
DMEA
445 }
446 }
447}
448
9b9d172d 449static void
450parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
44834a67 451 struct bdb_header *bdb)
9b9d172d 452{
453 struct sdvo_device_mapping *p_mapping;
454 struct bdb_general_definitions *p_defs;
768f69c9 455 union child_device_config *p_child;
9b9d172d 456 int i, child_device_num, count;
db545019 457 u16 block_size;
9b9d172d 458
459 p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
460 if (!p_defs) {
44834a67 461 DRM_DEBUG_KMS("No general definition block is found, unable to construct sdvo mapping.\n");
9b9d172d 462 return;
463 }
464 /* judge whether the size of child device meets the requirements.
465 * If the child device size obtained from general definition block
466 * is different with sizeof(struct child_device_config), skip the
467 * parsing of sdvo device info
468 */
469 if (p_defs->child_dev_size != sizeof(*p_child)) {
470 /* different child dev size . Ignore it */
28c97730 471 DRM_DEBUG_KMS("different child size is found. Invalid.\n");
9b9d172d 472 return;
473 }
474 /* get the block size of general definitions */
db545019 475 block_size = get_blocksize(p_defs);
9b9d172d 476 /* get the number of child device */
477 child_device_num = (block_size - sizeof(*p_defs)) /
478 sizeof(*p_child);
479 count = 0;
480 for (i = 0; i < child_device_num; i++) {
481 p_child = &(p_defs->devices[i]);
768f69c9 482 if (!p_child->old.device_type) {
9b9d172d 483 /* skip the device block if device type is invalid */
484 continue;
485 }
768f69c9
PZ
486 if (p_child->old.slave_addr != SLAVE_ADDR1 &&
487 p_child->old.slave_addr != SLAVE_ADDR2) {
9b9d172d 488 /*
489 * If the slave address is neither 0x70 nor 0x72,
490 * it is not a SDVO device. Skip it.
491 */
492 continue;
493 }
768f69c9
PZ
494 if (p_child->old.dvo_port != DEVICE_PORT_DVOB &&
495 p_child->old.dvo_port != DEVICE_PORT_DVOC) {
9b9d172d 496 /* skip the incorrect SDVO port */
0206e353 497 DRM_DEBUG_KMS("Incorrect SDVO port. Skip it\n");
9b9d172d 498 continue;
499 }
28c97730
ZY
500 DRM_DEBUG_KMS("the SDVO device with slave addr %2x is found on"
501 " %s port\n",
768f69c9
PZ
502 p_child->old.slave_addr,
503 (p_child->old.dvo_port == DEVICE_PORT_DVOB) ?
9b9d172d 504 "SDVOB" : "SDVOC");
768f69c9 505 p_mapping = &(dev_priv->sdvo_mappings[p_child->old.dvo_port - 1]);
9b9d172d 506 if (!p_mapping->initialized) {
768f69c9
PZ
507 p_mapping->dvo_port = p_child->old.dvo_port;
508 p_mapping->slave_addr = p_child->old.slave_addr;
509 p_mapping->dvo_wiring = p_child->old.dvo_wiring;
510 p_mapping->ddc_pin = p_child->old.ddc_pin;
511 p_mapping->i2c_pin = p_child->old.i2c_pin;
9b9d172d 512 p_mapping->initialized = 1;
46eb3036 513 DRM_DEBUG_KMS("SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d\n",
e957d772
CW
514 p_mapping->dvo_port,
515 p_mapping->slave_addr,
516 p_mapping->dvo_wiring,
517 p_mapping->ddc_pin,
46eb3036 518 p_mapping->i2c_pin);
9b9d172d 519 } else {
28c97730 520 DRM_DEBUG_KMS("Maybe one SDVO port is shared by "
9b9d172d 521 "two SDVO device.\n");
522 }
768f69c9 523 if (p_child->old.slave2_addr) {
9b9d172d 524 /* Maybe this is a SDVO device with multiple inputs */
525 /* And the mapping info is not added */
28c97730
ZY
526 DRM_DEBUG_KMS("there exists the slave2_addr. Maybe this"
527 " is a SDVO device with multiple inputs.\n");
9b9d172d 528 }
529 count++;
530 }
531
532 if (!count) {
533 /* No SDVO device info is found */
28c97730 534 DRM_DEBUG_KMS("No SDVO device info is found in VBT\n");
9b9d172d 535 }
536 return;
537}
32f9d658
ZW
538
539static void
540parse_driver_features(struct drm_i915_private *dev_priv,
541 struct bdb_header *bdb)
542{
32f9d658
ZW
543 struct bdb_driver_features *driver;
544
32f9d658 545 driver = find_section(bdb, BDB_DRIVER_FEATURES);
652c393a
JB
546 if (!driver)
547 return;
548
6fca55b1 549 if (driver->lvds_config == BDB_DRIVER_FEATURE_EDP)
41aa3448 550 dev_priv->vbt.edp_support = 1;
652c393a 551
5ceb0f9b 552 if (driver->dual_frequency)
652c393a 553 dev_priv->render_reclock_avail = true;
83a7280e
PB
554
555 DRM_DEBUG_KMS("DRRS State Enabled:%d\n", driver->drrs_enabled);
556 /*
557 * If DRRS is not supported, drrs_type has to be set to 0.
558 * This is because, VBT is configured in such a way that
559 * static DRRS is 0 and DRRS not supported is represented by
560 * driver->drrs_enabled=false
561 */
562 if (!driver->drrs_enabled)
563 dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
32f9d658
ZW
564}
565
500a8cc4
ZW
566static void
567parse_edp(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
568{
569 struct bdb_edp *edp;
9f0e7ff4
JB
570 struct edp_power_seq *edp_pps;
571 struct edp_link_params *edp_link_params;
500a8cc4
ZW
572
573 edp = find_section(bdb, BDB_EDP);
574 if (!edp) {
6fca55b1 575 if (dev_priv->vbt.edp_support)
9a30a61f 576 DRM_DEBUG_KMS("No eDP BDB found but eDP panel supported.\n");
500a8cc4
ZW
577 return;
578 }
579
580 switch ((edp->color_depth >> (panel_type * 2)) & 3) {
581 case EDP_18BPP:
41aa3448 582 dev_priv->vbt.edp_bpp = 18;
500a8cc4
ZW
583 break;
584 case EDP_24BPP:
41aa3448 585 dev_priv->vbt.edp_bpp = 24;
500a8cc4
ZW
586 break;
587 case EDP_30BPP:
41aa3448 588 dev_priv->vbt.edp_bpp = 30;
500a8cc4
ZW
589 break;
590 }
5ceb0f9b 591
9f0e7ff4
JB
592 /* Get the eDP sequencing and link info */
593 edp_pps = &edp->power_seqs[panel_type];
594 edp_link_params = &edp->link_params[panel_type];
5ceb0f9b 595
41aa3448 596 dev_priv->vbt.edp_pps = *edp_pps;
5ceb0f9b 597
e13e2b2c
JN
598 switch (edp_link_params->rate) {
599 case EDP_RATE_1_62:
600 dev_priv->vbt.edp_rate = DP_LINK_BW_1_62;
601 break;
602 case EDP_RATE_2_7:
603 dev_priv->vbt.edp_rate = DP_LINK_BW_2_7;
604 break;
605 default:
606 DRM_DEBUG_KMS("VBT has unknown eDP link rate value %u\n",
607 edp_link_params->rate);
608 break;
609 }
610
9f0e7ff4 611 switch (edp_link_params->lanes) {
e13e2b2c 612 case EDP_LANE_1:
41aa3448 613 dev_priv->vbt.edp_lanes = 1;
9f0e7ff4 614 break;
e13e2b2c 615 case EDP_LANE_2:
41aa3448 616 dev_priv->vbt.edp_lanes = 2;
9f0e7ff4 617 break;
e13e2b2c 618 case EDP_LANE_4:
41aa3448 619 dev_priv->vbt.edp_lanes = 4;
9f0e7ff4 620 break;
e13e2b2c
JN
621 default:
622 DRM_DEBUG_KMS("VBT has unknown eDP lane count value %u\n",
623 edp_link_params->lanes);
624 break;
9f0e7ff4 625 }
e13e2b2c 626
9f0e7ff4 627 switch (edp_link_params->preemphasis) {
e13e2b2c 628 case EDP_PREEMPHASIS_NONE:
41aa3448 629 dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_0;
9f0e7ff4 630 break;
e13e2b2c 631 case EDP_PREEMPHASIS_3_5dB:
41aa3448 632 dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_3_5;
9f0e7ff4 633 break;
e13e2b2c 634 case EDP_PREEMPHASIS_6dB:
41aa3448 635 dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_6;
9f0e7ff4 636 break;
e13e2b2c 637 case EDP_PREEMPHASIS_9_5dB:
41aa3448 638 dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_9_5;
9f0e7ff4 639 break;
e13e2b2c
JN
640 default:
641 DRM_DEBUG_KMS("VBT has unknown eDP pre-emphasis value %u\n",
642 edp_link_params->preemphasis);
643 break;
9f0e7ff4 644 }
e13e2b2c 645
9f0e7ff4 646 switch (edp_link_params->vswing) {
e13e2b2c 647 case EDP_VSWING_0_4V:
41aa3448 648 dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_400;
9f0e7ff4 649 break;
e13e2b2c 650 case EDP_VSWING_0_6V:
41aa3448 651 dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_600;
9f0e7ff4 652 break;
e13e2b2c 653 case EDP_VSWING_0_8V:
41aa3448 654 dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_800;
9f0e7ff4 655 break;
e13e2b2c 656 case EDP_VSWING_1_2V:
41aa3448 657 dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_1200;
9f0e7ff4 658 break;
e13e2b2c
JN
659 default:
660 DRM_DEBUG_KMS("VBT has unknown eDP voltage swing value %u\n",
661 edp_link_params->vswing);
662 break;
9f0e7ff4 663 }
500a8cc4
ZW
664}
665
d3b542fc
SK
666static u8 *goto_next_sequence(u8 *data, int *size)
667{
668 u16 len;
669 int tmp = *size;
670
671 if (--tmp < 0)
672 return NULL;
673
674 /* goto first element */
675 data++;
676 while (1) {
677 switch (*data) {
678 case MIPI_SEQ_ELEM_SEND_PKT:
679 /*
680 * skip by this element payload size
681 * skip elem id, command flag and data type
682 */
b0256cdc
SK
683 tmp -= 5;
684 if (tmp < 0)
d3b542fc
SK
685 return NULL;
686
687 data += 3;
688 len = *((u16 *)data);
689
b0256cdc
SK
690 tmp -= len;
691 if (tmp < 0)
d3b542fc
SK
692 return NULL;
693
694 /* skip by len */
695 data = data + 2 + len;
696 break;
697 case MIPI_SEQ_ELEM_DELAY:
698 /* skip by elem id, and delay is 4 bytes */
b0256cdc
SK
699 tmp -= 5;
700 if (tmp < 0)
d3b542fc
SK
701 return NULL;
702
703 data += 5;
704 break;
705 case MIPI_SEQ_ELEM_GPIO:
b0256cdc
SK
706 tmp -= 3;
707 if (tmp < 0)
d3b542fc
SK
708 return NULL;
709
710 data += 3;
711 break;
712 default:
713 DRM_ERROR("Unknown element\n");
714 return NULL;
715 }
716
717 /* end of sequence ? */
718 if (*data == 0)
719 break;
720 }
721
722 /* goto next sequence or end of block byte */
723 if (--tmp < 0)
724 return NULL;
725
726 data++;
727
728 /* update amount of data left for the sequence block to be parsed */
729 *size = tmp;
730 return data;
731}
732
d17c5443
SK
733static void
734parse_mipi(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
735{
d3b542fc
SK
736 struct bdb_mipi_config *start;
737 struct bdb_mipi_sequence *sequence;
738 struct mipi_config *config;
739 struct mipi_pps_data *pps;
740 u8 *data, *seq_data;
741 int i, panel_id, seq_size;
742 u16 block_size;
743
3e6bd011
SK
744 /* parse MIPI blocks only if LFP type is MIPI */
745 if (!dev_priv->vbt.has_mipi)
746 return;
747
d3b542fc
SK
748 /* Initialize this to undefined indicating no generic MIPI support */
749 dev_priv->vbt.dsi.panel_id = MIPI_DSI_UNDEFINED_PANEL_ID;
750
751 /* Block #40 is already parsed and panel_fixed_mode is
752 * stored in dev_priv->lfp_lvds_vbt_mode
753 * resuse this when needed
754 */
d17c5443 755
d3b542fc
SK
756 /* Parse #52 for panel index used from panel_type already
757 * parsed
758 */
759 start = find_section(bdb, BDB_MIPI_CONFIG);
760 if (!start) {
761 DRM_DEBUG_KMS("No MIPI config BDB found");
d17c5443
SK
762 return;
763 }
764
d3b542fc
SK
765 DRM_DEBUG_DRIVER("Found MIPI Config block, panel index = %d\n",
766 panel_type);
767
768 /*
769 * get hold of the correct configuration block and pps data as per
770 * the panel_type as index
771 */
772 config = &start->config[panel_type];
773 pps = &start->pps[panel_type];
774
775 /* store as of now full data. Trim when we realise all is not needed */
776 dev_priv->vbt.dsi.config = kmemdup(config, sizeof(struct mipi_config), GFP_KERNEL);
777 if (!dev_priv->vbt.dsi.config)
778 return;
779
780 dev_priv->vbt.dsi.pps = kmemdup(pps, sizeof(struct mipi_pps_data), GFP_KERNEL);
781 if (!dev_priv->vbt.dsi.pps) {
782 kfree(dev_priv->vbt.dsi.config);
783 return;
784 }
785
786 /* We have mandatory mipi config blocks. Initialize as generic panel */
ea9a6baf 787 dev_priv->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID;
d3b542fc
SK
788
789 /* Check if we have sequence block as well */
790 sequence = find_section(bdb, BDB_MIPI_SEQUENCE);
791 if (!sequence) {
792 DRM_DEBUG_KMS("No MIPI Sequence found, parsing complete\n");
793 return;
794 }
795
796 DRM_DEBUG_DRIVER("Found MIPI sequence block\n");
797
798 block_size = get_blocksize(sequence);
799
800 /*
801 * parse the sequence block for individual sequences
802 */
803 dev_priv->vbt.dsi.seq_version = sequence->version;
804
805 seq_data = &sequence->data[0];
806
807 /*
808 * sequence block is variable length and hence we need to parse and
809 * get the sequence data for specific panel id
810 */
811 for (i = 0; i < MAX_MIPI_CONFIGURATIONS; i++) {
812 panel_id = *seq_data;
813 seq_size = *((u16 *) (seq_data + 1));
814 if (panel_id == panel_type)
815 break;
816
817 /* skip the sequence including seq header of 3 bytes */
818 seq_data = seq_data + 3 + seq_size;
819 if ((seq_data - &sequence->data[0]) > block_size) {
820 DRM_ERROR("Sequence start is beyond sequence block size, corrupted sequence block\n");
821 return;
822 }
823 }
824
825 if (i == MAX_MIPI_CONFIGURATIONS) {
826 DRM_ERROR("Sequence block detected but no valid configuration\n");
827 return;
828 }
829
830 /* check if found sequence is completely within the sequence block
831 * just being paranoid */
832 if (seq_size > block_size) {
833 DRM_ERROR("Corrupted sequence/size, bailing out\n");
834 return;
835 }
836
837 /* skip the panel id(1 byte) and seq size(2 bytes) */
838 dev_priv->vbt.dsi.data = kmemdup(seq_data + 3, seq_size, GFP_KERNEL);
839 if (!dev_priv->vbt.dsi.data)
840 return;
841
842 /*
843 * loop into the sequence data and split into multiple sequneces
844 * There are only 5 types of sequences as of now
845 */
846 data = dev_priv->vbt.dsi.data;
847 dev_priv->vbt.dsi.size = seq_size;
848
849 /* two consecutive 0x00 indicate end of all sequences */
850 while (1) {
851 int seq_id = *data;
852 if (MIPI_SEQ_MAX > seq_id && seq_id > MIPI_SEQ_UNDEFINED) {
853 dev_priv->vbt.dsi.sequence[seq_id] = data;
854 DRM_DEBUG_DRIVER("Found mipi sequence - %d\n", seq_id);
855 } else {
856 DRM_ERROR("undefined sequence\n");
857 goto err;
858 }
859
860 /* partial parsing to skip elements */
861 data = goto_next_sequence(data, &seq_size);
862
863 if (data == NULL) {
864 DRM_ERROR("Sequence elements going beyond block itself. Sequence block parsing failed\n");
865 goto err;
866 }
867
868 if (*data == 0)
869 break; /* end of sequence reached */
870 }
871
872 DRM_DEBUG_DRIVER("MIPI related vbt parsing complete\n");
873 return;
874err:
875 kfree(dev_priv->vbt.dsi.data);
876 dev_priv->vbt.dsi.data = NULL;
877
878 /* error during parsing so set all pointers to null
879 * because of partial parsing */
880 memset(dev_priv->vbt.dsi.sequence, 0, MIPI_SEQ_MAX);
d17c5443
SK
881}
882
6acab15a
PZ
883static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port,
884 struct bdb_header *bdb)
885{
886 union child_device_config *it, *child = NULL;
887 struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port];
888 uint8_t hdmi_level_shift;
889 int i, j;
554d6af5 890 bool is_dvi, is_hdmi, is_dp, is_edp, is_crt;
6bf19e7c 891 uint8_t aux_channel;
6acab15a
PZ
892 /* Each DDI port can have more than one value on the "DVO Port" field,
893 * so look for all the possible values for each port and abort if more
894 * than one is found. */
895 int dvo_ports[][2] = {
896 {DVO_PORT_HDMIA, DVO_PORT_DPA},
897 {DVO_PORT_HDMIB, DVO_PORT_DPB},
898 {DVO_PORT_HDMIC, DVO_PORT_DPC},
899 {DVO_PORT_HDMID, DVO_PORT_DPD},
900 {DVO_PORT_CRT, -1 /* Port E can only be DVO_PORT_CRT */ },
901 };
902
903 /* Find the child device to use, abort if more than one found. */
904 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
905 it = dev_priv->vbt.child_dev + i;
906
907 for (j = 0; j < 2; j++) {
908 if (dvo_ports[port][j] == -1)
909 break;
910
911 if (it->common.dvo_port == dvo_ports[port][j]) {
912 if (child) {
913 DRM_DEBUG_KMS("More than one child device for port %c in VBT.\n",
914 port_name(port));
915 return;
916 }
917 child = it;
918 }
919 }
920 }
921 if (!child)
922 return;
923
6bf19e7c
PZ
924 aux_channel = child->raw[25];
925
78eb06c3
VS
926 is_dvi = child->common.device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING;
927 is_dp = child->common.device_type & DEVICE_TYPE_DISPLAYPORT_OUTPUT;
928 is_crt = child->common.device_type & DEVICE_TYPE_ANALOG_OUTPUT;
929 is_hdmi = is_dvi && (child->common.device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT) == 0;
930 is_edp = is_dp && (child->common.device_type & DEVICE_TYPE_INTERNAL_CONNECTOR);
554d6af5 931
311a2094
PZ
932 info->supports_dvi = is_dvi;
933 info->supports_hdmi = is_hdmi;
934 info->supports_dp = is_dp;
935
554d6af5
PZ
936 DRM_DEBUG_KMS("Port %c VBT info: DP:%d HDMI:%d DVI:%d EDP:%d CRT:%d\n",
937 port_name(port), is_dp, is_hdmi, is_dvi, is_edp, is_crt);
938
939 if (is_edp && is_dvi)
940 DRM_DEBUG_KMS("Internal DP port %c is TMDS compatible\n",
941 port_name(port));
942 if (is_crt && port != PORT_E)
943 DRM_DEBUG_KMS("Port %c is analog\n", port_name(port));
944 if (is_crt && (is_dvi || is_dp))
945 DRM_DEBUG_KMS("Analog port %c is also DP or TMDS compatible\n",
946 port_name(port));
947 if (is_dvi && (port == PORT_A || port == PORT_E))
948 DRM_DEBUG_KMS("Port %c is TMDS compabile\n", port_name(port));
949 if (!is_dvi && !is_dp && !is_crt)
950 DRM_DEBUG_KMS("Port %c is not DP/TMDS/CRT compatible\n",
951 port_name(port));
952 if (is_edp && (port == PORT_B || port == PORT_C || port == PORT_E))
953 DRM_DEBUG_KMS("Port %c is internal DP\n", port_name(port));
6bf19e7c
PZ
954
955 if (is_dvi) {
956 if (child->common.ddc_pin == 0x05 && port != PORT_B)
957 DRM_DEBUG_KMS("Unexpected DDC pin for port B\n");
958 if (child->common.ddc_pin == 0x04 && port != PORT_C)
959 DRM_DEBUG_KMS("Unexpected DDC pin for port C\n");
960 if (child->common.ddc_pin == 0x06 && port != PORT_D)
961 DRM_DEBUG_KMS("Unexpected DDC pin for port D\n");
962 }
963
964 if (is_dp) {
965 if (aux_channel == 0x40 && port != PORT_A)
966 DRM_DEBUG_KMS("Unexpected AUX channel for port A\n");
967 if (aux_channel == 0x10 && port != PORT_B)
968 DRM_DEBUG_KMS("Unexpected AUX channel for port B\n");
969 if (aux_channel == 0x20 && port != PORT_C)
970 DRM_DEBUG_KMS("Unexpected AUX channel for port C\n");
971 if (aux_channel == 0x30 && port != PORT_D)
972 DRM_DEBUG_KMS("Unexpected AUX channel for port D\n");
973 }
974
6acab15a
PZ
975 if (bdb->version >= 158) {
976 /* The VBT HDMI level shift values match the table we have. */
977 hdmi_level_shift = child->raw[7] & 0xF;
978 if (hdmi_level_shift < 0xC) {
979 DRM_DEBUG_KMS("VBT HDMI level shift for port %c: %d\n",
980 port_name(port),
981 hdmi_level_shift);
982 info->hdmi_level_shift = hdmi_level_shift;
983 }
984 }
985}
986
987static void parse_ddi_ports(struct drm_i915_private *dev_priv,
988 struct bdb_header *bdb)
989{
990 struct drm_device *dev = dev_priv->dev;
991 enum port port;
992
993 if (!HAS_DDI(dev))
994 return;
995
996 if (!dev_priv->vbt.child_dev_num)
997 return;
998
999 if (bdb->version < 155)
1000 return;
1001
1002 for (port = PORT_A; port < I915_MAX_PORTS; port++)
1003 parse_ddi_port(dev_priv, port, bdb);
1004}
1005
6363ee6f
ZY
1006static void
1007parse_device_mapping(struct drm_i915_private *dev_priv,
1008 struct bdb_header *bdb)
1009{
1010 struct bdb_general_definitions *p_defs;
768f69c9 1011 union child_device_config *p_child, *child_dev_ptr;
6363ee6f
ZY
1012 int i, child_device_num, count;
1013 u16 block_size;
1014
1015 p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
1016 if (!p_defs) {
44834a67 1017 DRM_DEBUG_KMS("No general definition block is found, no devices defined.\n");
6363ee6f
ZY
1018 return;
1019 }
1020 /* judge whether the size of child device meets the requirements.
1021 * If the child device size obtained from general definition block
1022 * is different with sizeof(struct child_device_config), skip the
1023 * parsing of sdvo device info
1024 */
1025 if (p_defs->child_dev_size != sizeof(*p_child)) {
1026 /* different child dev size . Ignore it */
1027 DRM_DEBUG_KMS("different child size is found. Invalid.\n");
1028 return;
1029 }
1030 /* get the block size of general definitions */
1031 block_size = get_blocksize(p_defs);
1032 /* get the number of child device */
1033 child_device_num = (block_size - sizeof(*p_defs)) /
1034 sizeof(*p_child);
1035 count = 0;
1036 /* get the number of child device that is present */
1037 for (i = 0; i < child_device_num; i++) {
1038 p_child = &(p_defs->devices[i]);
768f69c9 1039 if (!p_child->common.device_type) {
6363ee6f
ZY
1040 /* skip the device block if device type is invalid */
1041 continue;
1042 }
1043 count++;
1044 }
1045 if (!count) {
0206e353 1046 DRM_DEBUG_KMS("no child dev is parsed from VBT\n");
6363ee6f
ZY
1047 return;
1048 }
41aa3448
RV
1049 dev_priv->vbt.child_dev = kcalloc(count, sizeof(*p_child), GFP_KERNEL);
1050 if (!dev_priv->vbt.child_dev) {
6363ee6f
ZY
1051 DRM_DEBUG_KMS("No memory space for child device\n");
1052 return;
1053 }
1054
41aa3448 1055 dev_priv->vbt.child_dev_num = count;
6363ee6f
ZY
1056 count = 0;
1057 for (i = 0; i < child_device_num; i++) {
1058 p_child = &(p_defs->devices[i]);
768f69c9 1059 if (!p_child->common.device_type) {
6363ee6f
ZY
1060 /* skip the device block if device type is invalid */
1061 continue;
1062 }
3e6bd011
SK
1063
1064 if (p_child->common.dvo_port >= DVO_PORT_MIPIA
1065 && p_child->common.dvo_port <= DVO_PORT_MIPID
1066 &&p_child->common.device_type & DEVICE_TYPE_MIPI_OUTPUT) {
1067 DRM_DEBUG_KMS("Found MIPI as LFP\n");
1068 dev_priv->vbt.has_mipi = 1;
1069 dev_priv->vbt.dsi.port = p_child->common.dvo_port;
1070 }
1071
41aa3448 1072 child_dev_ptr = dev_priv->vbt.child_dev + count;
6363ee6f
ZY
1073 count++;
1074 memcpy((void *)child_dev_ptr, (void *)p_child,
1075 sizeof(*p_child));
1076 }
1077 return;
1078}
44834a67 1079
6a04002b
SQ
1080static void
1081init_vbt_defaults(struct drm_i915_private *dev_priv)
1082{
9a4114ff 1083 struct drm_device *dev = dev_priv->dev;
6acab15a 1084 enum port port;
9a4114ff 1085
41aa3448 1086 dev_priv->vbt.crt_ddc_pin = GMBUS_PORT_VGADDC;
6a04002b 1087
56c4b63a
JN
1088 /* Default to having backlight */
1089 dev_priv->vbt.backlight.present = true;
1090
6a04002b 1091 /* LFP panel data */
41aa3448
RV
1092 dev_priv->vbt.lvds_dither = 1;
1093 dev_priv->vbt.lvds_vbt = 0;
6a04002b
SQ
1094
1095 /* SDVO panel data */
41aa3448 1096 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
6a04002b
SQ
1097
1098 /* general features */
41aa3448
RV
1099 dev_priv->vbt.int_tv_support = 1;
1100 dev_priv->vbt.int_crt_support = 1;
9a4114ff
BF
1101
1102 /* Default to using SSC */
41aa3448 1103 dev_priv->vbt.lvds_use_ssc = 1;
f69e5156
DL
1104 /*
1105 * Core/SandyBridge/IvyBridge use alternative (120MHz) reference
1106 * clock for LVDS.
1107 */
1108 dev_priv->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(dev,
1109 !HAS_PCH_SPLIT(dev));
e91e941b 1110 DRM_DEBUG_KMS("Set default to SSC at %d kHz\n", dev_priv->vbt.lvds_ssc_freq);
6acab15a
PZ
1111
1112 for (port = PORT_A; port < I915_MAX_PORTS; port++) {
311a2094
PZ
1113 struct ddi_vbt_port_info *info =
1114 &dev_priv->vbt.ddi_port_info[port];
1115
6acab15a 1116 /* Recommended BSpec default: 800mV 0dB. */
311a2094
PZ
1117 info->hdmi_level_shift = 6;
1118
1119 info->supports_dvi = (port != PORT_A && port != PORT_E);
1120 info->supports_hdmi = info->supports_dvi;
1121 info->supports_dp = (port != PORT_E);
6acab15a 1122 }
6a04002b
SQ
1123}
1124
25e341cf
DV
1125static int __init intel_no_opregion_vbt_callback(const struct dmi_system_id *id)
1126{
1127 DRM_DEBUG_KMS("Falling back to manually reading VBT from "
1128 "VBIOS ROM for %s\n",
1129 id->ident);
1130 return 1;
1131}
1132
1133static const struct dmi_system_id intel_no_opregion_vbt[] = {
1134 {
1135 .callback = intel_no_opregion_vbt_callback,
1136 .ident = "ThinkCentre A57",
1137 .matches = {
1138 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1139 DMI_MATCH(DMI_PRODUCT_NAME, "97027RG"),
1140 },
1141 },
1142 { }
1143};
1144
3dd4e846
CW
1145static struct bdb_header *validate_vbt(char *base, size_t size,
1146 struct vbt_header *vbt,
1147 const char *source)
1148{
1149 size_t offset;
1150 struct bdb_header *bdb;
1151
1152 if (vbt == NULL) {
1153 DRM_DEBUG_DRIVER("VBT signature missing\n");
1154 return NULL;
1155 }
1156
1157 offset = (char *)vbt - base;
1158 if (offset + sizeof(struct vbt_header) > size) {
1159 DRM_DEBUG_DRIVER("VBT header incomplete\n");
1160 return NULL;
1161 }
1162
1163 if (memcmp(vbt->signature, "$VBT", 4)) {
1164 DRM_DEBUG_DRIVER("VBT invalid signature\n");
1165 return NULL;
1166 }
1167
1168 offset += vbt->bdb_offset;
1169 if (offset + sizeof(struct bdb_header) > size) {
1170 DRM_DEBUG_DRIVER("BDB header incomplete\n");
1171 return NULL;
1172 }
1173
1174 bdb = (struct bdb_header *)(base + offset);
1175 if (offset + bdb->bdb_size > size) {
1176 DRM_DEBUG_DRIVER("BDB incomplete\n");
1177 return NULL;
1178 }
1179
1180 DRM_DEBUG_KMS("Using VBT from %s: %20s\n",
1181 source, vbt->signature);
1182 return bdb;
1183}
1184
79e53945 1185/**
6d139a87 1186 * intel_parse_bios - find VBT and initialize settings from the BIOS
79e53945
JB
1187 * @dev: DRM device
1188 *
1189 * Loads the Video BIOS and checks that the VBT exists. Sets scratch registers
1190 * to appropriate values.
1191 *
79e53945
JB
1192 * Returns 0 on success, nonzero on failure.
1193 */
0317c6ce 1194int
6d139a87 1195intel_parse_bios(struct drm_device *dev)
79e53945
JB
1196{
1197 struct drm_i915_private *dev_priv = dev->dev_private;
1198 struct pci_dev *pdev = dev->pdev;
44834a67
CW
1199 struct bdb_header *bdb = NULL;
1200 u8 __iomem *bios = NULL;
1201
ab5c608b
BW
1202 if (HAS_PCH_NOP(dev))
1203 return -ENODEV;
1204
6a04002b 1205 init_vbt_defaults(dev_priv);
f899fc64 1206
44834a67 1207 /* XXX Should this validation be moved to intel_opregion.c? */
3dd4e846
CW
1208 if (!dmi_check_system(intel_no_opregion_vbt) && dev_priv->opregion.vbt)
1209 bdb = validate_vbt((char *)dev_priv->opregion.header, OPREGION_SIZE,
1210 (struct vbt_header *)dev_priv->opregion.vbt,
1211 "OpRegion");
79e53945 1212
44834a67 1213 if (bdb == NULL) {
3dd4e846 1214 size_t i, size;
79e53945 1215
44834a67
CW
1216 bios = pci_map_rom(pdev, &size);
1217 if (!bios)
1218 return -1;
1219
1220 /* Scour memory looking for the VBT signature */
1221 for (i = 0; i + 4 < size; i++) {
3dd4e846
CW
1222 if (memcmp(bios + i, "$VBT", 4) == 0) {
1223 bdb = validate_vbt(bios, size,
1224 (struct vbt_header *)(bios + i),
1225 "PCI ROM");
44834a67
CW
1226 break;
1227 }
1228 }
1229
3dd4e846 1230 if (!bdb) {
44834a67
CW
1231 pci_unmap_rom(pdev, bios);
1232 return -1;
1233 }
44834a67 1234 }
79e53945
JB
1235
1236 /* Grab useful general definitions */
1237 parse_general_features(dev_priv, bdb);
db545019 1238 parse_general_definitions(dev_priv, bdb);
88631706 1239 parse_lfp_panel_data(dev_priv, bdb);
f00076d2 1240 parse_lfp_backlight(dev_priv, bdb);
88631706 1241 parse_sdvo_panel_data(dev_priv, bdb);
9b9d172d 1242 parse_sdvo_device_mapping(dev_priv, bdb);
6363ee6f 1243 parse_device_mapping(dev_priv, bdb);
32f9d658 1244 parse_driver_features(dev_priv, bdb);
500a8cc4 1245 parse_edp(dev_priv, bdb);
d17c5443 1246 parse_mipi(dev_priv, bdb);
6acab15a 1247 parse_ddi_ports(dev_priv, bdb);
32f9d658 1248
44834a67
CW
1249 if (bios)
1250 pci_unmap_rom(pdev, bios);
79e53945
JB
1251
1252 return 0;
1253}
6d139a87
BF
1254
1255/* Ensure that vital registers have been initialised, even if the BIOS
1256 * is absent or just failing to do its job.
1257 */
1258void intel_setup_bios(struct drm_device *dev)
1259{
1260 struct drm_i915_private *dev_priv = dev->dev_private;
1261
1262 /* Set the Panel Power On/Off timings if uninitialized. */
42d42e7e
DL
1263 if (!HAS_PCH_SPLIT(dev) &&
1264 I915_READ(PP_ON_DELAYS) == 0 && I915_READ(PP_OFF_DELAYS) == 0) {
6d139a87
BF
1265 /* Set T2 to 40ms and T5 to 200ms */
1266 I915_WRITE(PP_ON_DELAYS, 0x019007d0);
1267
1268 /* Set T3 to 35ms and Tx to 200ms */
1269 I915_WRITE(PP_OFF_DELAYS, 0x015e07d0);
1270 }
1271}