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drm/i915: move "no VBT in opregion" quirk to intel_opregion_setup()
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_bios.c
CommitLineData
79e53945 1/*
39507259 2 * Copyright © 2006 Intel Corporation
79e53945
JB
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
b30581a4 27
9f0e7ff4 28#include <drm/drm_dp_helper.h>
760285e7
DH
29#include <drm/drmP.h>
30#include <drm/i915_drm.h>
79e53945
JB
31#include "i915_drv.h"
32#include "intel_bios.h"
33
9b9d172d 34#define SLAVE_ADDR1 0x70
35#define SLAVE_ADDR2 0x72
79e53945 36
500a8cc4
ZW
37static int panel_type;
38
e8ef3b4c
JN
39static const void *
40find_section(const void *_bdb, int section_id)
79e53945 41{
e8ef3b4c
JN
42 const struct bdb_header *bdb = _bdb;
43 const u8 *base = _bdb;
79e53945 44 int index = 0;
cd67d226 45 u32 total, current_size;
79e53945
JB
46 u8 current_id;
47
48 /* skip to first section */
49 index += bdb->header_size;
50 total = bdb->bdb_size;
51
52 /* walk the sections looking for section_id */
d1f13fd2 53 while (index + 3 < total) {
79e53945
JB
54 current_id = *(base + index);
55 index++;
d1f13fd2 56
e8ef3b4c 57 current_size = *((const u16 *)(base + index));
79e53945 58 index += 2;
d1f13fd2 59
cd67d226
JN
60 /* The MIPI Sequence Block v3+ has a separate size field. */
61 if (current_id == BDB_MIPI_SEQUENCE && *(base + index) >= 3)
62 current_size = *((const u32 *)(base + index + 1));
63
d1f13fd2
CW
64 if (index + current_size > total)
65 return NULL;
66
79e53945
JB
67 if (current_id == section_id)
68 return base + index;
d1f13fd2 69
79e53945
JB
70 index += current_size;
71 }
72
73 return NULL;
74}
75
db545019 76static u16
e8ef3b4c 77get_blocksize(const void *p)
db545019
DMEA
78{
79 u16 *block_ptr, block_size;
80
81 block_ptr = (u16 *)((char *)p - 2);
82 block_size = *block_ptr;
83 return block_size;
84}
85
79e53945 86static void
88631706 87fill_detail_timing_data(struct drm_display_mode *panel_fixed_mode,
99834ea4 88 const struct lvds_dvo_timing *dvo_timing)
88631706
ML
89{
90 panel_fixed_mode->hdisplay = (dvo_timing->hactive_hi << 8) |
91 dvo_timing->hactive_lo;
92 panel_fixed_mode->hsync_start = panel_fixed_mode->hdisplay +
93 ((dvo_timing->hsync_off_hi << 8) | dvo_timing->hsync_off_lo);
94 panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start +
95 dvo_timing->hsync_pulse_width;
96 panel_fixed_mode->htotal = panel_fixed_mode->hdisplay +
97 ((dvo_timing->hblank_hi << 8) | dvo_timing->hblank_lo);
98
99 panel_fixed_mode->vdisplay = (dvo_timing->vactive_hi << 8) |
100 dvo_timing->vactive_lo;
101 panel_fixed_mode->vsync_start = panel_fixed_mode->vdisplay +
102 dvo_timing->vsync_off;
103 panel_fixed_mode->vsync_end = panel_fixed_mode->vsync_start +
104 dvo_timing->vsync_pulse_width;
105 panel_fixed_mode->vtotal = panel_fixed_mode->vdisplay +
106 ((dvo_timing->vblank_hi << 8) | dvo_timing->vblank_lo);
107 panel_fixed_mode->clock = dvo_timing->clock * 10;
108 panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED;
109
9bc35499
AJ
110 if (dvo_timing->hsync_positive)
111 panel_fixed_mode->flags |= DRM_MODE_FLAG_PHSYNC;
112 else
113 panel_fixed_mode->flags |= DRM_MODE_FLAG_NHSYNC;
114
115 if (dvo_timing->vsync_positive)
116 panel_fixed_mode->flags |= DRM_MODE_FLAG_PVSYNC;
117 else
118 panel_fixed_mode->flags |= DRM_MODE_FLAG_NVSYNC;
119
88631706
ML
120 /* Some VBTs have bogus h/vtotal values */
121 if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal)
122 panel_fixed_mode->htotal = panel_fixed_mode->hsync_end + 1;
123 if (panel_fixed_mode->vsync_end > panel_fixed_mode->vtotal)
124 panel_fixed_mode->vtotal = panel_fixed_mode->vsync_end + 1;
125
126 drm_mode_set_name(panel_fixed_mode);
127}
128
99834ea4
CW
129static const struct lvds_dvo_timing *
130get_lvds_dvo_timing(const struct bdb_lvds_lfp_data *lvds_lfp_data,
131 const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs,
132 int index)
133{
134 /*
135 * the size of fp_timing varies on the different platform.
136 * So calculate the DVO timing relative offset in LVDS data
137 * entry to get the DVO timing entry
138 */
139
140 int lfp_data_size =
141 lvds_lfp_data_ptrs->ptr[1].dvo_timing_offset -
142 lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset;
143 int dvo_timing_offset =
144 lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset -
145 lvds_lfp_data_ptrs->ptr[0].fp_timing_offset;
146 char *entry = (char *)lvds_lfp_data->data + lfp_data_size * index;
147
148 return (struct lvds_dvo_timing *)(entry + dvo_timing_offset);
149}
150
b0354385
TI
151/* get lvds_fp_timing entry
152 * this function may return NULL if the corresponding entry is invalid
153 */
154static const struct lvds_fp_timing *
155get_lvds_fp_timing(const struct bdb_header *bdb,
156 const struct bdb_lvds_lfp_data *data,
157 const struct bdb_lvds_lfp_data_ptrs *ptrs,
158 int index)
159{
160 size_t data_ofs = (const u8 *)data - (const u8 *)bdb;
161 u16 data_size = ((const u16 *)data)[-1]; /* stored in header */
162 size_t ofs;
163
164 if (index >= ARRAY_SIZE(ptrs->ptr))
165 return NULL;
166 ofs = ptrs->ptr[index].fp_timing_offset;
167 if (ofs < data_ofs ||
168 ofs + sizeof(struct lvds_fp_timing) > data_ofs + data_size)
169 return NULL;
170 return (const struct lvds_fp_timing *)((const u8 *)bdb + ofs);
171}
172
88631706
ML
173/* Try to find integrated panel data */
174static void
175parse_lfp_panel_data(struct drm_i915_private *dev_priv,
dcb58a40 176 const struct bdb_header *bdb)
79e53945 177{
99834ea4
CW
178 const struct bdb_lvds_options *lvds_options;
179 const struct bdb_lvds_lfp_data *lvds_lfp_data;
180 const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs;
181 const struct lvds_dvo_timing *panel_dvo_timing;
b0354385 182 const struct lvds_fp_timing *fp_timing;
79e53945 183 struct drm_display_mode *panel_fixed_mode;
c329a4ec 184 int drrs_mode;
79e53945 185
79e53945
JB
186 lvds_options = find_section(bdb, BDB_LVDS_OPTIONS);
187 if (!lvds_options)
188 return;
189
41aa3448 190 dev_priv->vbt.lvds_dither = lvds_options->pixel_dither;
79e53945
JB
191 if (lvds_options->panel_type == 0xff)
192 return;
6a04002b 193
500a8cc4 194 panel_type = lvds_options->panel_type;
79e53945 195
83a7280e
PB
196 drrs_mode = (lvds_options->dps_panel_type_bits
197 >> (panel_type * 2)) & MODE_MASK;
198 /*
199 * VBT has static DRRS = 0 and seamless DRRS = 2.
200 * The below piece of code is required to adjust vbt.drrs_type
201 * to match the enum drrs_support_type.
202 */
203 switch (drrs_mode) {
204 case 0:
205 dev_priv->vbt.drrs_type = STATIC_DRRS_SUPPORT;
206 DRM_DEBUG_KMS("DRRS supported mode is static\n");
207 break;
208 case 2:
209 dev_priv->vbt.drrs_type = SEAMLESS_DRRS_SUPPORT;
210 DRM_DEBUG_KMS("DRRS supported mode is seamless\n");
211 break;
212 default:
213 dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
214 DRM_DEBUG_KMS("DRRS not supported (VBT input)\n");
215 break;
216 }
217
79e53945
JB
218 lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA);
219 if (!lvds_lfp_data)
220 return;
221
1b16de0b
JB
222 lvds_lfp_data_ptrs = find_section(bdb, BDB_LVDS_LFP_DATA_PTRS);
223 if (!lvds_lfp_data_ptrs)
224 return;
225
41aa3448 226 dev_priv->vbt.lvds_vbt = 1;
79e53945 227
99834ea4
CW
228 panel_dvo_timing = get_lvds_dvo_timing(lvds_lfp_data,
229 lvds_lfp_data_ptrs,
230 lvds_options->panel_type);
79e53945 231
9a298b2a 232 panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
6edc3242
CW
233 if (!panel_fixed_mode)
234 return;
79e53945 235
99834ea4 236 fill_detail_timing_data(panel_fixed_mode, panel_dvo_timing);
79e53945 237
41aa3448 238 dev_priv->vbt.lfp_lvds_vbt_mode = panel_fixed_mode;
79e53945 239
28c97730 240 DRM_DEBUG_KMS("Found panel mode in BIOS VBT tables:\n");
88631706 241 drm_mode_debug_printmodeline(panel_fixed_mode);
37df9673 242
b0354385
TI
243 fp_timing = get_lvds_fp_timing(bdb, lvds_lfp_data,
244 lvds_lfp_data_ptrs,
245 lvds_options->panel_type);
246 if (fp_timing) {
247 /* check the resolution, just to be sure */
248 if (fp_timing->x_res == panel_fixed_mode->hdisplay &&
249 fp_timing->y_res == panel_fixed_mode->vdisplay) {
41aa3448 250 dev_priv->vbt.bios_lvds_val = fp_timing->lvds_reg_val;
b0354385 251 DRM_DEBUG_KMS("VBT initial LVDS value %x\n",
41aa3448 252 dev_priv->vbt.bios_lvds_val);
b0354385
TI
253 }
254 }
88631706
ML
255}
256
f00076d2 257static void
dcb58a40
JN
258parse_lfp_backlight(struct drm_i915_private *dev_priv,
259 const struct bdb_header *bdb)
f00076d2
JN
260{
261 const struct bdb_lfp_backlight_data *backlight_data;
262 const struct bdb_lfp_backlight_data_entry *entry;
263
264 backlight_data = find_section(bdb, BDB_LVDS_BACKLIGHT);
265 if (!backlight_data)
266 return;
267
268 if (backlight_data->entry_size != sizeof(backlight_data->data[0])) {
269 DRM_DEBUG_KMS("Unsupported backlight data entry size %u\n",
270 backlight_data->entry_size);
271 return;
272 }
273
274 entry = &backlight_data->data[panel_type];
275
39fbc9c8
JN
276 dev_priv->vbt.backlight.present = entry->type == BDB_BACKLIGHT_TYPE_PWM;
277 if (!dev_priv->vbt.backlight.present) {
278 DRM_DEBUG_KMS("PWM backlight not present in VBT (type %u)\n",
279 entry->type);
280 return;
281 }
282
f00076d2
JN
283 dev_priv->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz;
284 dev_priv->vbt.backlight.active_low_pwm = entry->active_low_pwm;
1de6068e 285 dev_priv->vbt.backlight.min_brightness = entry->min_brightness;
f00076d2
JN
286 DRM_DEBUG_KMS("VBT backlight PWM modulation frequency %u Hz, "
287 "active %s, min brightness %u, level %u\n",
288 dev_priv->vbt.backlight.pwm_freq_hz,
289 dev_priv->vbt.backlight.active_low_pwm ? "low" : "high",
1de6068e 290 dev_priv->vbt.backlight.min_brightness,
f00076d2
JN
291 backlight_data->level[panel_type]);
292}
293
88631706
ML
294/* Try to find sdvo panel data */
295static void
296parse_sdvo_panel_data(struct drm_i915_private *dev_priv,
dcb58a40 297 const struct bdb_header *bdb)
88631706 298{
e8ef3b4c 299 const struct lvds_dvo_timing *dvo_timing;
88631706 300 struct drm_display_mode *panel_fixed_mode;
5a1e5b6c 301 int index;
79e53945 302
d330a953 303 index = i915.vbt_sdvo_panel_type;
c10e408a
MF
304 if (index == -2) {
305 DRM_DEBUG_KMS("Ignore SDVO panel mode from BIOS VBT tables.\n");
306 return;
307 }
308
5a1e5b6c 309 if (index == -1) {
e8ef3b4c 310 const struct bdb_sdvo_lvds_options *sdvo_lvds_options;
5a1e5b6c
CW
311
312 sdvo_lvds_options = find_section(bdb, BDB_SDVO_LVDS_OPTIONS);
313 if (!sdvo_lvds_options)
314 return;
315
316 index = sdvo_lvds_options->panel_type;
317 }
88631706
ML
318
319 dvo_timing = find_section(bdb, BDB_SDVO_PANEL_DTDS);
320 if (!dvo_timing)
321 return;
322
9a298b2a 323 panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
88631706
ML
324 if (!panel_fixed_mode)
325 return;
326
5a1e5b6c 327 fill_detail_timing_data(panel_fixed_mode, dvo_timing + index);
88631706 328
41aa3448 329 dev_priv->vbt.sdvo_lvds_vbt_mode = panel_fixed_mode;
79e53945 330
5a1e5b6c
CW
331 DRM_DEBUG_KMS("Found SDVO panel mode in BIOS VBT tables:\n");
332 drm_mode_debug_printmodeline(panel_fixed_mode);
79e53945
JB
333}
334
9a4114ff
BF
335static int intel_bios_ssc_frequency(struct drm_device *dev,
336 bool alternate)
337{
338 switch (INTEL_INFO(dev)->gen) {
339 case 2:
e91e941b 340 return alternate ? 66667 : 48000;
9a4114ff
BF
341 case 3:
342 case 4:
e91e941b 343 return alternate ? 100000 : 96000;
9a4114ff 344 default:
e91e941b 345 return alternate ? 100000 : 120000;
9a4114ff
BF
346 }
347}
348
79e53945
JB
349static void
350parse_general_features(struct drm_i915_private *dev_priv,
dcb58a40 351 const struct bdb_header *bdb)
79e53945 352{
bad720ff 353 struct drm_device *dev = dev_priv->dev;
e8ef3b4c 354 const struct bdb_general_features *general;
79e53945 355
79e53945
JB
356 general = find_section(bdb, BDB_GENERAL_FEATURES);
357 if (general) {
41aa3448 358 dev_priv->vbt.int_tv_support = general->int_tv_support;
e4abb733
VS
359 /* int_crt_support can't be trusted on earlier platforms */
360 if (bdb->version >= 155 &&
361 (HAS_DDI(dev_priv) || IS_VALLEYVIEW(dev_priv)))
362 dev_priv->vbt.int_crt_support = general->int_crt_support;
41aa3448
RV
363 dev_priv->vbt.lvds_use_ssc = general->enable_ssc;
364 dev_priv->vbt.lvds_ssc_freq =
9a4114ff 365 intel_bios_ssc_frequency(dev, general->ssc_freq);
41aa3448
RV
366 dev_priv->vbt.display_clock_mode = general->display_clock_mode;
367 dev_priv->vbt.fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted;
3f704fa2 368 DRM_DEBUG_KMS("BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d fdi_rx_polarity_inverted %d\n",
41aa3448
RV
369 dev_priv->vbt.int_tv_support,
370 dev_priv->vbt.int_crt_support,
371 dev_priv->vbt.lvds_use_ssc,
372 dev_priv->vbt.lvds_ssc_freq,
373 dev_priv->vbt.display_clock_mode,
374 dev_priv->vbt.fdi_rx_polarity_inverted);
79e53945
JB
375 }
376}
377
db545019
DMEA
378static void
379parse_general_definitions(struct drm_i915_private *dev_priv,
dcb58a40 380 const struct bdb_header *bdb)
db545019 381{
e8ef3b4c 382 const struct bdb_general_definitions *general;
db545019 383
db545019
DMEA
384 general = find_section(bdb, BDB_GENERAL_DEFINITIONS);
385 if (general) {
386 u16 block_size = get_blocksize(general);
387 if (block_size >= sizeof(*general)) {
388 int bus_pin = general->crt_ddc_gmbus_pin;
28c97730 389 DRM_DEBUG_KMS("crt_ddc_bus_pin: %d\n", bus_pin);
88ac7939 390 if (intel_gmbus_is_valid_pin(dev_priv, bus_pin))
41aa3448 391 dev_priv->vbt.crt_ddc_pin = bus_pin;
db545019 392 } else {
28c97730 393 DRM_DEBUG_KMS("BDB_GD too small (%d). Invalid.\n",
3bd7d909 394 block_size);
db545019
DMEA
395 }
396 }
397}
398
e8ef3b4c
JN
399static const union child_device_config *
400child_device_ptr(const struct bdb_general_definitions *p_defs, int i)
90e4f159 401{
e8ef3b4c 402 return (const void *) &p_defs->devices[i * p_defs->child_dev_size];
90e4f159
VS
403}
404
9b9d172d 405static void
406parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
dcb58a40 407 const struct bdb_header *bdb)
9b9d172d 408{
409 struct sdvo_device_mapping *p_mapping;
e8ef3b4c 410 const struct bdb_general_definitions *p_defs;
6cc38aca 411 const struct old_child_dev_config *child; /* legacy */
9b9d172d 412 int i, child_device_num, count;
db545019 413 u16 block_size;
9b9d172d 414
415 p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
416 if (!p_defs) {
44834a67 417 DRM_DEBUG_KMS("No general definition block is found, unable to construct sdvo mapping.\n");
9b9d172d 418 return;
419 }
6cc38aca
JN
420
421 /*
422 * Only parse SDVO mappings when the general definitions block child
423 * device size matches that of the *legacy* child device config
424 * struct. Thus, SDVO mapping will be skipped for newer VBT.
9b9d172d 425 */
6cc38aca
JN
426 if (p_defs->child_dev_size != sizeof(*child)) {
427 DRM_DEBUG_KMS("Unsupported child device size for SDVO mapping.\n");
9b9d172d 428 return;
429 }
430 /* get the block size of general definitions */
db545019 431 block_size = get_blocksize(p_defs);
9b9d172d 432 /* get the number of child device */
433 child_device_num = (block_size - sizeof(*p_defs)) /
90e4f159 434 p_defs->child_dev_size;
9b9d172d 435 count = 0;
436 for (i = 0; i < child_device_num; i++) {
6cc38aca
JN
437 child = &child_device_ptr(p_defs, i)->old;
438 if (!child->device_type) {
9b9d172d 439 /* skip the device block if device type is invalid */
440 continue;
441 }
6cc38aca
JN
442 if (child->slave_addr != SLAVE_ADDR1 &&
443 child->slave_addr != SLAVE_ADDR2) {
9b9d172d 444 /*
445 * If the slave address is neither 0x70 nor 0x72,
446 * it is not a SDVO device. Skip it.
447 */
448 continue;
449 }
6cc38aca
JN
450 if (child->dvo_port != DEVICE_PORT_DVOB &&
451 child->dvo_port != DEVICE_PORT_DVOC) {
9b9d172d 452 /* skip the incorrect SDVO port */
0206e353 453 DRM_DEBUG_KMS("Incorrect SDVO port. Skip it\n");
9b9d172d 454 continue;
455 }
28c97730 456 DRM_DEBUG_KMS("the SDVO device with slave addr %2x is found on"
6cc38aca
JN
457 " %s port\n",
458 child->slave_addr,
459 (child->dvo_port == DEVICE_PORT_DVOB) ?
460 "SDVOB" : "SDVOC");
461 p_mapping = &(dev_priv->sdvo_mappings[child->dvo_port - 1]);
9b9d172d 462 if (!p_mapping->initialized) {
6cc38aca
JN
463 p_mapping->dvo_port = child->dvo_port;
464 p_mapping->slave_addr = child->slave_addr;
465 p_mapping->dvo_wiring = child->dvo_wiring;
466 p_mapping->ddc_pin = child->ddc_pin;
467 p_mapping->i2c_pin = child->i2c_pin;
9b9d172d 468 p_mapping->initialized = 1;
46eb3036 469 DRM_DEBUG_KMS("SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d\n",
e957d772
CW
470 p_mapping->dvo_port,
471 p_mapping->slave_addr,
472 p_mapping->dvo_wiring,
473 p_mapping->ddc_pin,
46eb3036 474 p_mapping->i2c_pin);
9b9d172d 475 } else {
28c97730 476 DRM_DEBUG_KMS("Maybe one SDVO port is shared by "
9b9d172d 477 "two SDVO device.\n");
478 }
6cc38aca 479 if (child->slave2_addr) {
9b9d172d 480 /* Maybe this is a SDVO device with multiple inputs */
481 /* And the mapping info is not added */
28c97730
ZY
482 DRM_DEBUG_KMS("there exists the slave2_addr. Maybe this"
483 " is a SDVO device with multiple inputs.\n");
9b9d172d 484 }
485 count++;
486 }
487
488 if (!count) {
489 /* No SDVO device info is found */
28c97730 490 DRM_DEBUG_KMS("No SDVO device info is found in VBT\n");
9b9d172d 491 }
492 return;
493}
32f9d658
ZW
494
495static void
496parse_driver_features(struct drm_i915_private *dev_priv,
dcb58a40 497 const struct bdb_header *bdb)
32f9d658 498{
e8ef3b4c 499 const struct bdb_driver_features *driver;
32f9d658 500
32f9d658 501 driver = find_section(bdb, BDB_DRIVER_FEATURES);
652c393a
JB
502 if (!driver)
503 return;
504
6fca55b1 505 if (driver->lvds_config == BDB_DRIVER_FEATURE_EDP)
41aa3448 506 dev_priv->vbt.edp_support = 1;
652c393a 507
5ceb0f9b 508 if (driver->dual_frequency)
652c393a 509 dev_priv->render_reclock_avail = true;
83a7280e
PB
510
511 DRM_DEBUG_KMS("DRRS State Enabled:%d\n", driver->drrs_enabled);
512 /*
513 * If DRRS is not supported, drrs_type has to be set to 0.
514 * This is because, VBT is configured in such a way that
515 * static DRRS is 0 and DRRS not supported is represented by
516 * driver->drrs_enabled=false
517 */
518 if (!driver->drrs_enabled)
519 dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
32f9d658
ZW
520}
521
500a8cc4 522static void
dcb58a40 523parse_edp(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
500a8cc4 524{
e8ef3b4c
JN
525 const struct bdb_edp *edp;
526 const struct edp_power_seq *edp_pps;
527 const struct edp_link_params *edp_link_params;
500a8cc4
ZW
528
529 edp = find_section(bdb, BDB_EDP);
530 if (!edp) {
6fca55b1 531 if (dev_priv->vbt.edp_support)
9a30a61f 532 DRM_DEBUG_KMS("No eDP BDB found but eDP panel supported.\n");
500a8cc4
ZW
533 return;
534 }
535
536 switch ((edp->color_depth >> (panel_type * 2)) & 3) {
537 case EDP_18BPP:
41aa3448 538 dev_priv->vbt.edp_bpp = 18;
500a8cc4
ZW
539 break;
540 case EDP_24BPP:
41aa3448 541 dev_priv->vbt.edp_bpp = 24;
500a8cc4
ZW
542 break;
543 case EDP_30BPP:
41aa3448 544 dev_priv->vbt.edp_bpp = 30;
500a8cc4
ZW
545 break;
546 }
5ceb0f9b 547
9f0e7ff4
JB
548 /* Get the eDP sequencing and link info */
549 edp_pps = &edp->power_seqs[panel_type];
550 edp_link_params = &edp->link_params[panel_type];
5ceb0f9b 551
41aa3448 552 dev_priv->vbt.edp_pps = *edp_pps;
5ceb0f9b 553
e13e2b2c
JN
554 switch (edp_link_params->rate) {
555 case EDP_RATE_1_62:
556 dev_priv->vbt.edp_rate = DP_LINK_BW_1_62;
557 break;
558 case EDP_RATE_2_7:
559 dev_priv->vbt.edp_rate = DP_LINK_BW_2_7;
560 break;
561 default:
562 DRM_DEBUG_KMS("VBT has unknown eDP link rate value %u\n",
563 edp_link_params->rate);
564 break;
565 }
566
9f0e7ff4 567 switch (edp_link_params->lanes) {
e13e2b2c 568 case EDP_LANE_1:
41aa3448 569 dev_priv->vbt.edp_lanes = 1;
9f0e7ff4 570 break;
e13e2b2c 571 case EDP_LANE_2:
41aa3448 572 dev_priv->vbt.edp_lanes = 2;
9f0e7ff4 573 break;
e13e2b2c 574 case EDP_LANE_4:
41aa3448 575 dev_priv->vbt.edp_lanes = 4;
9f0e7ff4 576 break;
e13e2b2c
JN
577 default:
578 DRM_DEBUG_KMS("VBT has unknown eDP lane count value %u\n",
579 edp_link_params->lanes);
580 break;
9f0e7ff4 581 }
e13e2b2c 582
9f0e7ff4 583 switch (edp_link_params->preemphasis) {
e13e2b2c 584 case EDP_PREEMPHASIS_NONE:
bd60018a 585 dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_0;
9f0e7ff4 586 break;
e13e2b2c 587 case EDP_PREEMPHASIS_3_5dB:
bd60018a 588 dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_1;
9f0e7ff4 589 break;
e13e2b2c 590 case EDP_PREEMPHASIS_6dB:
bd60018a 591 dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_2;
9f0e7ff4 592 break;
e13e2b2c 593 case EDP_PREEMPHASIS_9_5dB:
bd60018a 594 dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_3;
9f0e7ff4 595 break;
e13e2b2c
JN
596 default:
597 DRM_DEBUG_KMS("VBT has unknown eDP pre-emphasis value %u\n",
598 edp_link_params->preemphasis);
599 break;
9f0e7ff4 600 }
e13e2b2c 601
9f0e7ff4 602 switch (edp_link_params->vswing) {
e13e2b2c 603 case EDP_VSWING_0_4V:
bd60018a 604 dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
9f0e7ff4 605 break;
e13e2b2c 606 case EDP_VSWING_0_6V:
bd60018a 607 dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_1;
9f0e7ff4 608 break;
e13e2b2c 609 case EDP_VSWING_0_8V:
bd60018a 610 dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
9f0e7ff4 611 break;
e13e2b2c 612 case EDP_VSWING_1_2V:
bd60018a 613 dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
9f0e7ff4 614 break;
e13e2b2c
JN
615 default:
616 DRM_DEBUG_KMS("VBT has unknown eDP voltage swing value %u\n",
617 edp_link_params->vswing);
618 break;
9f0e7ff4 619 }
9a57f5bb
SJ
620
621 if (bdb->version >= 173) {
622 uint8_t vswing;
623
9e458034
SJ
624 /* Don't read from VBT if module parameter has valid value*/
625 if (i915.edp_vswing) {
626 dev_priv->edp_low_vswing = i915.edp_vswing == 1;
627 } else {
628 vswing = (edp->edp_vswing_preemph >> (panel_type * 4)) & 0xF;
629 dev_priv->edp_low_vswing = vswing == 0;
630 }
9a57f5bb 631 }
500a8cc4
ZW
632}
633
bfd7ebda 634static void
dcb58a40 635parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
bfd7ebda 636{
e8ef3b4c
JN
637 const struct bdb_psr *psr;
638 const struct psr_table *psr_table;
bfd7ebda
RV
639
640 psr = find_section(bdb, BDB_PSR);
641 if (!psr) {
642 DRM_DEBUG_KMS("No PSR BDB found.\n");
643 return;
644 }
645
646 psr_table = &psr->psr_table[panel_type];
647
648 dev_priv->vbt.psr.full_link = psr_table->full_link;
649 dev_priv->vbt.psr.require_aux_wakeup = psr_table->require_aux_to_wakeup;
650
651 /* Allowed VBT values goes from 0 to 15 */
652 dev_priv->vbt.psr.idle_frames = psr_table->idle_frames < 0 ? 0 :
653 psr_table->idle_frames > 15 ? 15 : psr_table->idle_frames;
654
655 switch (psr_table->lines_to_wait) {
656 case 0:
657 dev_priv->vbt.psr.lines_to_wait = PSR_0_LINES_TO_WAIT;
658 break;
659 case 1:
660 dev_priv->vbt.psr.lines_to_wait = PSR_1_LINE_TO_WAIT;
661 break;
662 case 2:
663 dev_priv->vbt.psr.lines_to_wait = PSR_4_LINES_TO_WAIT;
664 break;
665 case 3:
666 dev_priv->vbt.psr.lines_to_wait = PSR_8_LINES_TO_WAIT;
667 break;
668 default:
669 DRM_DEBUG_KMS("VBT has unknown PSR lines to wait %u\n",
670 psr_table->lines_to_wait);
671 break;
672 }
673
674 dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
675 dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
676}
677
d3b542fc
SK
678static u8 *goto_next_sequence(u8 *data, int *size)
679{
680 u16 len;
681 int tmp = *size;
682
683 if (--tmp < 0)
684 return NULL;
685
686 /* goto first element */
687 data++;
688 while (1) {
689 switch (*data) {
690 case MIPI_SEQ_ELEM_SEND_PKT:
691 /*
692 * skip by this element payload size
693 * skip elem id, command flag and data type
694 */
b0256cdc
SK
695 tmp -= 5;
696 if (tmp < 0)
d3b542fc
SK
697 return NULL;
698
699 data += 3;
700 len = *((u16 *)data);
701
b0256cdc
SK
702 tmp -= len;
703 if (tmp < 0)
d3b542fc
SK
704 return NULL;
705
706 /* skip by len */
707 data = data + 2 + len;
708 break;
709 case MIPI_SEQ_ELEM_DELAY:
710 /* skip by elem id, and delay is 4 bytes */
b0256cdc
SK
711 tmp -= 5;
712 if (tmp < 0)
d3b542fc
SK
713 return NULL;
714
715 data += 5;
716 break;
717 case MIPI_SEQ_ELEM_GPIO:
b0256cdc
SK
718 tmp -= 3;
719 if (tmp < 0)
d3b542fc
SK
720 return NULL;
721
722 data += 3;
723 break;
724 default:
725 DRM_ERROR("Unknown element\n");
726 return NULL;
727 }
728
729 /* end of sequence ? */
730 if (*data == 0)
731 break;
732 }
733
734 /* goto next sequence or end of block byte */
735 if (--tmp < 0)
736 return NULL;
737
738 data++;
739
740 /* update amount of data left for the sequence block to be parsed */
741 *size = tmp;
742 return data;
743}
744
d17c5443 745static void
dcb58a40 746parse_mipi(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
d17c5443 747{
e8ef3b4c
JN
748 const struct bdb_mipi_config *start;
749 const struct bdb_mipi_sequence *sequence;
750 const struct mipi_config *config;
751 const struct mipi_pps_data *pps;
752 u8 *data;
753 const u8 *seq_data;
d3b542fc
SK
754 int i, panel_id, seq_size;
755 u16 block_size;
756
3e6bd011
SK
757 /* parse MIPI blocks only if LFP type is MIPI */
758 if (!dev_priv->vbt.has_mipi)
759 return;
760
d3b542fc
SK
761 /* Initialize this to undefined indicating no generic MIPI support */
762 dev_priv->vbt.dsi.panel_id = MIPI_DSI_UNDEFINED_PANEL_ID;
763
764 /* Block #40 is already parsed and panel_fixed_mode is
765 * stored in dev_priv->lfp_lvds_vbt_mode
766 * resuse this when needed
767 */
d17c5443 768
d3b542fc
SK
769 /* Parse #52 for panel index used from panel_type already
770 * parsed
771 */
772 start = find_section(bdb, BDB_MIPI_CONFIG);
773 if (!start) {
774 DRM_DEBUG_KMS("No MIPI config BDB found");
d17c5443
SK
775 return;
776 }
777
d3b542fc
SK
778 DRM_DEBUG_DRIVER("Found MIPI Config block, panel index = %d\n",
779 panel_type);
780
781 /*
782 * get hold of the correct configuration block and pps data as per
783 * the panel_type as index
784 */
785 config = &start->config[panel_type];
786 pps = &start->pps[panel_type];
787
788 /* store as of now full data. Trim when we realise all is not needed */
789 dev_priv->vbt.dsi.config = kmemdup(config, sizeof(struct mipi_config), GFP_KERNEL);
790 if (!dev_priv->vbt.dsi.config)
791 return;
792
793 dev_priv->vbt.dsi.pps = kmemdup(pps, sizeof(struct mipi_pps_data), GFP_KERNEL);
794 if (!dev_priv->vbt.dsi.pps) {
795 kfree(dev_priv->vbt.dsi.config);
796 return;
797 }
798
799 /* We have mandatory mipi config blocks. Initialize as generic panel */
ea9a6baf 800 dev_priv->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID;
d3b542fc
SK
801
802 /* Check if we have sequence block as well */
803 sequence = find_section(bdb, BDB_MIPI_SEQUENCE);
804 if (!sequence) {
805 DRM_DEBUG_KMS("No MIPI Sequence found, parsing complete\n");
806 return;
807 }
808
cd67d226
JN
809 /* Fail gracefully for forward incompatible sequence block. */
810 if (sequence->version >= 3) {
811 DRM_ERROR("Unable to parse MIPI Sequence Block v3+\n");
812 return;
813 }
814
d3b542fc
SK
815 DRM_DEBUG_DRIVER("Found MIPI sequence block\n");
816
817 block_size = get_blocksize(sequence);
818
819 /*
820 * parse the sequence block for individual sequences
821 */
822 dev_priv->vbt.dsi.seq_version = sequence->version;
823
824 seq_data = &sequence->data[0];
825
826 /*
827 * sequence block is variable length and hence we need to parse and
828 * get the sequence data for specific panel id
829 */
830 for (i = 0; i < MAX_MIPI_CONFIGURATIONS; i++) {
831 panel_id = *seq_data;
832 seq_size = *((u16 *) (seq_data + 1));
833 if (panel_id == panel_type)
834 break;
835
836 /* skip the sequence including seq header of 3 bytes */
837 seq_data = seq_data + 3 + seq_size;
838 if ((seq_data - &sequence->data[0]) > block_size) {
839 DRM_ERROR("Sequence start is beyond sequence block size, corrupted sequence block\n");
840 return;
841 }
842 }
843
844 if (i == MAX_MIPI_CONFIGURATIONS) {
845 DRM_ERROR("Sequence block detected but no valid configuration\n");
846 return;
847 }
848
849 /* check if found sequence is completely within the sequence block
850 * just being paranoid */
851 if (seq_size > block_size) {
852 DRM_ERROR("Corrupted sequence/size, bailing out\n");
853 return;
854 }
855
856 /* skip the panel id(1 byte) and seq size(2 bytes) */
857 dev_priv->vbt.dsi.data = kmemdup(seq_data + 3, seq_size, GFP_KERNEL);
858 if (!dev_priv->vbt.dsi.data)
859 return;
860
861 /*
862 * loop into the sequence data and split into multiple sequneces
863 * There are only 5 types of sequences as of now
864 */
865 data = dev_priv->vbt.dsi.data;
866 dev_priv->vbt.dsi.size = seq_size;
867
868 /* two consecutive 0x00 indicate end of all sequences */
869 while (1) {
870 int seq_id = *data;
871 if (MIPI_SEQ_MAX > seq_id && seq_id > MIPI_SEQ_UNDEFINED) {
872 dev_priv->vbt.dsi.sequence[seq_id] = data;
873 DRM_DEBUG_DRIVER("Found mipi sequence - %d\n", seq_id);
874 } else {
875 DRM_ERROR("undefined sequence\n");
876 goto err;
877 }
878
879 /* partial parsing to skip elements */
880 data = goto_next_sequence(data, &seq_size);
881
882 if (data == NULL) {
883 DRM_ERROR("Sequence elements going beyond block itself. Sequence block parsing failed\n");
884 goto err;
885 }
886
887 if (*data == 0)
888 break; /* end of sequence reached */
889 }
890
891 DRM_DEBUG_DRIVER("MIPI related vbt parsing complete\n");
892 return;
893err:
894 kfree(dev_priv->vbt.dsi.data);
895 dev_priv->vbt.dsi.data = NULL;
896
897 /* error during parsing so set all pointers to null
898 * because of partial parsing */
ed3b6679 899 memset(dev_priv->vbt.dsi.sequence, 0, sizeof(dev_priv->vbt.dsi.sequence));
d17c5443
SK
900}
901
75067dde
AK
902static u8 translate_iboost(u8 val)
903{
904 static const u8 mapping[] = { 1, 3, 7 }; /* See VBT spec */
905
906 if (val >= ARRAY_SIZE(mapping)) {
907 DRM_DEBUG_KMS("Unsupported I_boost value found in VBT (%d), display may not work properly\n", val);
908 return 0;
909 }
910 return mapping[val];
911}
912
6acab15a 913static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port,
dcb58a40 914 const struct bdb_header *bdb)
6acab15a
PZ
915{
916 union child_device_config *it, *child = NULL;
917 struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port];
918 uint8_t hdmi_level_shift;
919 int i, j;
554d6af5 920 bool is_dvi, is_hdmi, is_dp, is_edp, is_crt;
11c1b657 921 uint8_t aux_channel, ddc_pin;
6acab15a
PZ
922 /* Each DDI port can have more than one value on the "DVO Port" field,
923 * so look for all the possible values for each port and abort if more
924 * than one is found. */
2800e4c2
RV
925 int dvo_ports[][3] = {
926 {DVO_PORT_HDMIA, DVO_PORT_DPA, -1},
927 {DVO_PORT_HDMIB, DVO_PORT_DPB, -1},
928 {DVO_PORT_HDMIC, DVO_PORT_DPC, -1},
929 {DVO_PORT_HDMID, DVO_PORT_DPD, -1},
930 {DVO_PORT_CRT, DVO_PORT_HDMIE, DVO_PORT_DPE},
6acab15a
PZ
931 };
932
933 /* Find the child device to use, abort if more than one found. */
934 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
935 it = dev_priv->vbt.child_dev + i;
936
2800e4c2 937 for (j = 0; j < 3; j++) {
6acab15a
PZ
938 if (dvo_ports[port][j] == -1)
939 break;
940
941 if (it->common.dvo_port == dvo_ports[port][j]) {
942 if (child) {
943 DRM_DEBUG_KMS("More than one child device for port %c in VBT.\n",
944 port_name(port));
945 return;
946 }
947 child = it;
948 }
949 }
950 }
951 if (!child)
952 return;
953
6bf19e7c 954 aux_channel = child->raw[25];
11c1b657 955 ddc_pin = child->common.ddc_pin;
6bf19e7c 956
78eb06c3
VS
957 is_dvi = child->common.device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING;
958 is_dp = child->common.device_type & DEVICE_TYPE_DISPLAYPORT_OUTPUT;
959 is_crt = child->common.device_type & DEVICE_TYPE_ANALOG_OUTPUT;
960 is_hdmi = is_dvi && (child->common.device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT) == 0;
961 is_edp = is_dp && (child->common.device_type & DEVICE_TYPE_INTERNAL_CONNECTOR);
554d6af5 962
311a2094
PZ
963 info->supports_dvi = is_dvi;
964 info->supports_hdmi = is_hdmi;
965 info->supports_dp = is_dp;
966
554d6af5
PZ
967 DRM_DEBUG_KMS("Port %c VBT info: DP:%d HDMI:%d DVI:%d EDP:%d CRT:%d\n",
968 port_name(port), is_dp, is_hdmi, is_dvi, is_edp, is_crt);
969
970 if (is_edp && is_dvi)
971 DRM_DEBUG_KMS("Internal DP port %c is TMDS compatible\n",
972 port_name(port));
973 if (is_crt && port != PORT_E)
974 DRM_DEBUG_KMS("Port %c is analog\n", port_name(port));
975 if (is_crt && (is_dvi || is_dp))
976 DRM_DEBUG_KMS("Analog port %c is also DP or TMDS compatible\n",
977 port_name(port));
978 if (is_dvi && (port == PORT_A || port == PORT_E))
9b13494c 979 DRM_DEBUG_KMS("Port %c is TMDS compatible\n", port_name(port));
554d6af5
PZ
980 if (!is_dvi && !is_dp && !is_crt)
981 DRM_DEBUG_KMS("Port %c is not DP/TMDS/CRT compatible\n",
982 port_name(port));
983 if (is_edp && (port == PORT_B || port == PORT_C || port == PORT_E))
984 DRM_DEBUG_KMS("Port %c is internal DP\n", port_name(port));
6bf19e7c
PZ
985
986 if (is_dvi) {
11c1b657
XZ
987 if (port == PORT_E) {
988 info->alternate_ddc_pin = ddc_pin;
989 /* if DDIE share ddc pin with other port, then
990 * dvi/hdmi couldn't exist on the shared port.
991 * Otherwise they share the same ddc bin and system
992 * couldn't communicate with them seperately. */
993 if (ddc_pin == DDC_PIN_B) {
994 dev_priv->vbt.ddi_port_info[PORT_B].supports_dvi = 0;
995 dev_priv->vbt.ddi_port_info[PORT_B].supports_hdmi = 0;
996 } else if (ddc_pin == DDC_PIN_C) {
997 dev_priv->vbt.ddi_port_info[PORT_C].supports_dvi = 0;
998 dev_priv->vbt.ddi_port_info[PORT_C].supports_hdmi = 0;
999 } else if (ddc_pin == DDC_PIN_D) {
1000 dev_priv->vbt.ddi_port_info[PORT_D].supports_dvi = 0;
1001 dev_priv->vbt.ddi_port_info[PORT_D].supports_hdmi = 0;
1002 }
1003 } else if (ddc_pin == DDC_PIN_B && port != PORT_B)
6bf19e7c 1004 DRM_DEBUG_KMS("Unexpected DDC pin for port B\n");
11c1b657 1005 else if (ddc_pin == DDC_PIN_C && port != PORT_C)
6bf19e7c 1006 DRM_DEBUG_KMS("Unexpected DDC pin for port C\n");
11c1b657 1007 else if (ddc_pin == DDC_PIN_D && port != PORT_D)
6bf19e7c
PZ
1008 DRM_DEBUG_KMS("Unexpected DDC pin for port D\n");
1009 }
1010
1011 if (is_dp) {
500ea70d
RV
1012 if (port == PORT_E) {
1013 info->alternate_aux_channel = aux_channel;
1014 /* if DDIE share aux channel with other port, then
1015 * DP couldn't exist on the shared port. Otherwise
1016 * they share the same aux channel and system
1017 * couldn't communicate with them seperately. */
1018 if (aux_channel == DP_AUX_A)
1019 dev_priv->vbt.ddi_port_info[PORT_A].supports_dp = 0;
1020 else if (aux_channel == DP_AUX_B)
1021 dev_priv->vbt.ddi_port_info[PORT_B].supports_dp = 0;
1022 else if (aux_channel == DP_AUX_C)
1023 dev_priv->vbt.ddi_port_info[PORT_C].supports_dp = 0;
1024 else if (aux_channel == DP_AUX_D)
1025 dev_priv->vbt.ddi_port_info[PORT_D].supports_dp = 0;
1026 }
1027 else if (aux_channel == DP_AUX_A && port != PORT_A)
6bf19e7c 1028 DRM_DEBUG_KMS("Unexpected AUX channel for port A\n");
500ea70d 1029 else if (aux_channel == DP_AUX_B && port != PORT_B)
6bf19e7c 1030 DRM_DEBUG_KMS("Unexpected AUX channel for port B\n");
500ea70d 1031 else if (aux_channel == DP_AUX_C && port != PORT_C)
6bf19e7c 1032 DRM_DEBUG_KMS("Unexpected AUX channel for port C\n");
500ea70d 1033 else if (aux_channel == DP_AUX_D && port != PORT_D)
6bf19e7c
PZ
1034 DRM_DEBUG_KMS("Unexpected AUX channel for port D\n");
1035 }
1036
6acab15a
PZ
1037 if (bdb->version >= 158) {
1038 /* The VBT HDMI level shift values match the table we have. */
1039 hdmi_level_shift = child->raw[7] & 0xF;
ce4dd49e
DL
1040 DRM_DEBUG_KMS("VBT HDMI level shift for port %c: %d\n",
1041 port_name(port),
1042 hdmi_level_shift);
1043 info->hdmi_level_shift = hdmi_level_shift;
6acab15a 1044 }
75067dde
AK
1045
1046 /* Parse the I_boost config for SKL and above */
1047 if (bdb->version >= 196 && (child->common.flags_1 & IBOOST_ENABLE)) {
1048 info->dp_boost_level = translate_iboost(child->common.iboost_level & 0xF);
1049 DRM_DEBUG_KMS("VBT (e)DP boost level for port %c: %d\n",
1050 port_name(port), info->dp_boost_level);
1051 info->hdmi_boost_level = translate_iboost(child->common.iboost_level >> 4);
1052 DRM_DEBUG_KMS("VBT HDMI boost level for port %c: %d\n",
1053 port_name(port), info->hdmi_boost_level);
1054 }
6acab15a
PZ
1055}
1056
1057static void parse_ddi_ports(struct drm_i915_private *dev_priv,
dcb58a40 1058 const struct bdb_header *bdb)
6acab15a
PZ
1059{
1060 struct drm_device *dev = dev_priv->dev;
1061 enum port port;
1062
1063 if (!HAS_DDI(dev))
1064 return;
1065
1066 if (!dev_priv->vbt.child_dev_num)
1067 return;
1068
1069 if (bdb->version < 155)
1070 return;
1071
1072 for (port = PORT_A; port < I915_MAX_PORTS; port++)
1073 parse_ddi_port(dev_priv, port, bdb);
1074}
1075
6363ee6f
ZY
1076static void
1077parse_device_mapping(struct drm_i915_private *dev_priv,
dcb58a40 1078 const struct bdb_header *bdb)
6363ee6f 1079{
e8ef3b4c
JN
1080 const struct bdb_general_definitions *p_defs;
1081 const union child_device_config *p_child;
1082 union child_device_config *child_dev_ptr;
6363ee6f 1083 int i, child_device_num, count;
e2d6cf7f
DW
1084 u8 expected_size;
1085 u16 block_size;
6363ee6f
ZY
1086
1087 p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
1088 if (!p_defs) {
44834a67 1089 DRM_DEBUG_KMS("No general definition block is found, no devices defined.\n");
6363ee6f
ZY
1090 return;
1091 }
e2d6cf7f
DW
1092 if (bdb->version < 195) {
1093 expected_size = sizeof(struct old_child_dev_config);
1094 } else if (bdb->version == 195) {
1095 expected_size = 37;
1096 } else if (bdb->version <= 197) {
1097 expected_size = 38;
1098 } else {
1099 expected_size = 38;
1100 BUILD_BUG_ON(sizeof(*p_child) < 38);
1101 DRM_DEBUG_DRIVER("Expected child device config size for VBT version %u not known; assuming %u\n",
1102 bdb->version, expected_size);
1103 }
1104
1105 /* The legacy sized child device config is the minimum we need. */
1106 if (p_defs->child_dev_size < sizeof(struct old_child_dev_config)) {
1107 DRM_ERROR("Child device config size %u is too small.\n",
1108 p_defs->child_dev_size);
6363ee6f
ZY
1109 return;
1110 }
e2d6cf7f
DW
1111
1112 /* Flag an error for unexpected size, but continue anyway. */
1113 if (p_defs->child_dev_size != expected_size)
1114 DRM_ERROR("Unexpected child device config size %u (expected %u for VBT version %u)\n",
1115 p_defs->child_dev_size, expected_size, bdb->version);
1116
6363ee6f
ZY
1117 /* get the block size of general definitions */
1118 block_size = get_blocksize(p_defs);
1119 /* get the number of child device */
1120 child_device_num = (block_size - sizeof(*p_defs)) /
90e4f159 1121 p_defs->child_dev_size;
6363ee6f
ZY
1122 count = 0;
1123 /* get the number of child device that is present */
1124 for (i = 0; i < child_device_num; i++) {
90e4f159 1125 p_child = child_device_ptr(p_defs, i);
768f69c9 1126 if (!p_child->common.device_type) {
6363ee6f
ZY
1127 /* skip the device block if device type is invalid */
1128 continue;
1129 }
1130 count++;
1131 }
1132 if (!count) {
0206e353 1133 DRM_DEBUG_KMS("no child dev is parsed from VBT\n");
6363ee6f
ZY
1134 return;
1135 }
41aa3448
RV
1136 dev_priv->vbt.child_dev = kcalloc(count, sizeof(*p_child), GFP_KERNEL);
1137 if (!dev_priv->vbt.child_dev) {
6363ee6f
ZY
1138 DRM_DEBUG_KMS("No memory space for child device\n");
1139 return;
1140 }
1141
41aa3448 1142 dev_priv->vbt.child_dev_num = count;
6363ee6f
ZY
1143 count = 0;
1144 for (i = 0; i < child_device_num; i++) {
90e4f159 1145 p_child = child_device_ptr(p_defs, i);
768f69c9 1146 if (!p_child->common.device_type) {
6363ee6f
ZY
1147 /* skip the device block if device type is invalid */
1148 continue;
1149 }
3e6bd011
SK
1150
1151 if (p_child->common.dvo_port >= DVO_PORT_MIPIA
1152 && p_child->common.dvo_port <= DVO_PORT_MIPID
1153 &&p_child->common.device_type & DEVICE_TYPE_MIPI_OUTPUT) {
1154 DRM_DEBUG_KMS("Found MIPI as LFP\n");
1155 dev_priv->vbt.has_mipi = 1;
1156 dev_priv->vbt.dsi.port = p_child->common.dvo_port;
1157 }
1158
41aa3448 1159 child_dev_ptr = dev_priv->vbt.child_dev + count;
6363ee6f 1160 count++;
e2d6cf7f
DW
1161
1162 /*
1163 * Copy as much as we know (sizeof) and is available
1164 * (child_dev_size) of the child device. Accessing the data must
1165 * depend on VBT version.
1166 */
1167 memcpy(child_dev_ptr, p_child,
1168 min_t(size_t, p_defs->child_dev_size, sizeof(*p_child)));
6363ee6f
ZY
1169 }
1170 return;
1171}
44834a67 1172
6a04002b
SQ
1173static void
1174init_vbt_defaults(struct drm_i915_private *dev_priv)
1175{
9a4114ff 1176 struct drm_device *dev = dev_priv->dev;
6acab15a 1177 enum port port;
9a4114ff 1178
988c7015 1179 dev_priv->vbt.crt_ddc_pin = GMBUS_PIN_VGADDC;
6a04002b 1180
56c4b63a
JN
1181 /* Default to having backlight */
1182 dev_priv->vbt.backlight.present = true;
1183
6a04002b 1184 /* LFP panel data */
41aa3448
RV
1185 dev_priv->vbt.lvds_dither = 1;
1186 dev_priv->vbt.lvds_vbt = 0;
6a04002b
SQ
1187
1188 /* SDVO panel data */
41aa3448 1189 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
6a04002b
SQ
1190
1191 /* general features */
41aa3448
RV
1192 dev_priv->vbt.int_tv_support = 1;
1193 dev_priv->vbt.int_crt_support = 1;
9a4114ff
BF
1194
1195 /* Default to using SSC */
41aa3448 1196 dev_priv->vbt.lvds_use_ssc = 1;
f69e5156
DL
1197 /*
1198 * Core/SandyBridge/IvyBridge use alternative (120MHz) reference
1199 * clock for LVDS.
1200 */
1201 dev_priv->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(dev,
1202 !HAS_PCH_SPLIT(dev));
e91e941b 1203 DRM_DEBUG_KMS("Set default to SSC at %d kHz\n", dev_priv->vbt.lvds_ssc_freq);
6acab15a
PZ
1204
1205 for (port = PORT_A; port < I915_MAX_PORTS; port++) {
311a2094
PZ
1206 struct ddi_vbt_port_info *info =
1207 &dev_priv->vbt.ddi_port_info[port];
1208
ce4dd49e 1209 info->hdmi_level_shift = HDMI_LEVEL_SHIFT_UNKNOWN;
311a2094
PZ
1210
1211 info->supports_dvi = (port != PORT_A && port != PORT_E);
1212 info->supports_hdmi = info->supports_dvi;
1213 info->supports_dp = (port != PORT_E);
6acab15a 1214 }
6a04002b
SQ
1215}
1216
115719fc 1217static const struct bdb_header *validate_vbt(const void *base,
acbb4793 1218 size_t size,
115719fc 1219 const void *_vbt,
dcb58a40 1220 const char *source)
3dd4e846 1221{
115719fc
WD
1222 size_t offset = _vbt - base;
1223 const struct vbt_header *vbt = _vbt;
dcb58a40 1224 const struct bdb_header *bdb;
3dd4e846 1225
3dd4e846
CW
1226 if (offset + sizeof(struct vbt_header) > size) {
1227 DRM_DEBUG_DRIVER("VBT header incomplete\n");
1228 return NULL;
1229 }
1230
1231 if (memcmp(vbt->signature, "$VBT", 4)) {
1232 DRM_DEBUG_DRIVER("VBT invalid signature\n");
1233 return NULL;
1234 }
1235
1236 offset += vbt->bdb_offset;
1237 if (offset + sizeof(struct bdb_header) > size) {
1238 DRM_DEBUG_DRIVER("BDB header incomplete\n");
1239 return NULL;
1240 }
1241
dcb58a40 1242 bdb = base + offset;
3dd4e846
CW
1243 if (offset + bdb->bdb_size > size) {
1244 DRM_DEBUG_DRIVER("BDB incomplete\n");
1245 return NULL;
1246 }
1247
1248 DRM_DEBUG_KMS("Using VBT from %s: %20s\n",
1249 source, vbt->signature);
1250 return bdb;
1251}
1252
acbb4793 1253static const struct bdb_header *find_vbt(void __iomem *bios, size_t size)
b34a991a
JN
1254{
1255 const struct bdb_header *bdb = NULL;
1256 size_t i;
1257
1258 /* Scour memory looking for the VBT signature. */
1259 for (i = 0; i + 4 < size; i++) {
acbb4793 1260 if (ioread32(bios + i) == *((const u32 *) "$VBT")) {
115719fc
WD
1261 /*
1262 * This is the one place where we explicitly discard the
1263 * address space (__iomem) of the BIOS/VBT. From now on
1264 * everything is based on 'base', and treated as regular
1265 * memory.
1266 */
1267 void *_bios = (void __force *) bios;
1268
1269 bdb = validate_vbt(_bios, size, _bios + i, "PCI ROM");
b34a991a
JN
1270 break;
1271 }
1272 }
1273
1274 return bdb;
1275}
1276
79e53945 1277/**
6d139a87 1278 * intel_parse_bios - find VBT and initialize settings from the BIOS
79e53945
JB
1279 * @dev: DRM device
1280 *
1281 * Loads the Video BIOS and checks that the VBT exists. Sets scratch registers
1282 * to appropriate values.
1283 *
79e53945
JB
1284 * Returns 0 on success, nonzero on failure.
1285 */
0317c6ce 1286int
6d139a87 1287intel_parse_bios(struct drm_device *dev)
79e53945
JB
1288{
1289 struct drm_i915_private *dev_priv = dev->dev_private;
1290 struct pci_dev *pdev = dev->pdev;
dcb58a40 1291 const struct bdb_header *bdb = NULL;
44834a67
CW
1292 u8 __iomem *bios = NULL;
1293
ab5c608b
BW
1294 if (HAS_PCH_NOP(dev))
1295 return -ENODEV;
1296
6a04002b 1297 init_vbt_defaults(dev_priv);
f899fc64 1298
44834a67 1299 /* XXX Should this validation be moved to intel_opregion.c? */
b30581a4 1300 if (dev_priv->opregion.vbt)
dcb58a40
JN
1301 bdb = validate_vbt(dev_priv->opregion.header, OPREGION_SIZE,
1302 dev_priv->opregion.vbt, "OpRegion");
79e53945 1303
44834a67 1304 if (bdb == NULL) {
b34a991a 1305 size_t size;
79e53945 1306
44834a67
CW
1307 bios = pci_map_rom(pdev, &size);
1308 if (!bios)
1309 return -1;
1310
b34a991a 1311 bdb = find_vbt(bios, size);
3dd4e846 1312 if (!bdb) {
44834a67
CW
1313 pci_unmap_rom(pdev, bios);
1314 return -1;
1315 }
44834a67 1316 }
79e53945
JB
1317
1318 /* Grab useful general definitions */
1319 parse_general_features(dev_priv, bdb);
db545019 1320 parse_general_definitions(dev_priv, bdb);
88631706 1321 parse_lfp_panel_data(dev_priv, bdb);
f00076d2 1322 parse_lfp_backlight(dev_priv, bdb);
88631706 1323 parse_sdvo_panel_data(dev_priv, bdb);
9b9d172d 1324 parse_sdvo_device_mapping(dev_priv, bdb);
6363ee6f 1325 parse_device_mapping(dev_priv, bdb);
32f9d658 1326 parse_driver_features(dev_priv, bdb);
500a8cc4 1327 parse_edp(dev_priv, bdb);
bfd7ebda 1328 parse_psr(dev_priv, bdb);
d17c5443 1329 parse_mipi(dev_priv, bdb);
6acab15a 1330 parse_ddi_ports(dev_priv, bdb);
32f9d658 1331
44834a67
CW
1332 if (bios)
1333 pci_unmap_rom(pdev, bios);
79e53945
JB
1334
1335 return 0;
1336}